2025.2:
 * Version 17.0
 * Feature Enhancement: Added Sync LVDS mode support with X5IO Wizard IP for Versal Gen2 devices
 * Feature Enhancement: Replaced the xlconstant IP with an inline HDL ilconstant in the Example Design.
 * Feature Enhancement: Added Example Design support with Versal Adaptive SoC Transceivers Wizard Subsystem IP for Versal devices.
 * Other: Added new devices support
 * Other: Enable visibility of hierarchy, cells and schematics in Vivado GUI
 * Other: MMCM instantiation is replaced with the clocking wizard in the Example Design
 * Other: Removed the FREQ_HZ bus_parameter from userclk, userclk2, rxuserclk and rxuserclk2 input ports
 * Revision change in one or more subcores

2025.1.1:
 * Version 16.2 (Rev. 24)
 * Revision change in one or more subcores

2025.1:
 * Version 16.2 (Rev. 23)
 * Feature Enhancement: Added Sync LVDS mode support with Advanced IO Wizard IP for versal devices
 * Other: Updated IP Catalog taxonomy structure. This change has no impact to the IP.
 * Other: Updated packaged all example subcores with properties.
 * Other: Added device support
 * Other: Updated VHDL testbench to stop simulation properly without giving failure message in case of test pass.
 * Other: Updated advanced io wizard IP version from v1.0 to v1.1.
 * Revision change in one or more subcores

2024.2.2:
 * Version 16.2 (Rev. 22)
 * No changes

2024.2.1:
 * Version 16.2 (Rev. 22)
 * General: Added device support

2024.2:
 * Version 16.2 (Rev. 21)
 * Feature Enhancement: Added support for Sync LVDS mode with Advanced IO Wiz for Versal
 * Other: Added device support
 * Revision change in one or more subcores

2024.1.2:
 * Version 16.2 (Rev. 20)
 * General: Added device support

2024.1.1:
 * Version 16.2 (Rev. 19)
 * General: Added device support
 * Revision change in one or more subcores

2024.1:
 * Version 16.2 (Rev. 18)
 * General: IP packaging adjustments to address warnings from IP Packager integrity check
 * General: Added device support
 * Revision change in one or more subcores

2023.2.2:
 * Version 16.2 (Rev. 17)
 * Feature Enhancement: Added support for new Versal devices.
 * Revision change in one or more subcores

2023.2.1:
 * Version 16.2 (Rev. 16)
 * Feature Enhancement: Added support for new Versal devices.
 * Revision change in one or more subcores

2023.2:
 * Version 16.2 (Rev. 15)
 * Feature Enhancement: Added support for new Versal devices.
 * Other: Rebrand to AMD copyright information.
 * Other: Replaced xpm async fifo in rx gearbox with sync fifo in LVDS mode in Versal devices.
 * Other: Added a seperate toggle signal for rx datapath in 7 series 1000BASEX transceiver logic when RxGmiiClkSrc is TXOUTCLK.
 * Revision change in one or more subcores

2023.1.2:
 * Version 16.2 (Rev. 14)
 * Feature Enhancement: Added support for new Versal devices

2023.1.1:
 * Version 16.2 (Rev. 13)
 * Feature Enhancement: Added support for new Versal devices

2023.1:
 * Version 16.2 (Rev. 12)
 * Feature Enhancement: Added support for new Versal devices
 * Revision change in one or more subcores

2022.2.2:
 * Version 16.2 (Rev. 11)
 * Feature Enhancement: Added support new Versal devices
 * Revision change in one or more subcores

2022.2.1:
 * Version 16.2 (Rev. 10)
 * Feature Enhancement: Added support for Avalon and new Versal devices
 * Revision change in one or more subcores

2022.2:
 * Version 16.2 (Rev. 9)
 * Bug Fix: Synthesis Error Fix- Disabled gtwiz_buffbypass_tx_done_in port enablement for versal in 1588 mode
 * Bug Fix: Synthesis Error FIx- Synthesis failure on XA Kintex/Spartan Devices fixed
 * Feature Enhancement: Added suppport for new Versal devices
 * Revision change in one or more subcores

2022.1.2:
 * Version 16.2 (Rev. 8)
 * No changes

2022.1.1:
 * Version 16.2 (Rev. 8)
 * No changes

2022.1:
 * Version 16.2 (Rev. 8)
 * Bug Fix: Removed BUFGCE-BUFGCE_DIV Cascade on TX clocking Path in SGMII/1000Basex over LVDS Configuration for Versal Devices
 * Feature Enhancement: Added PS GEM as a Selectable Input Option for Versal Devices.
 * Feature Enhancement: Added Support for new Versal devices.
 * Feature Enhancement: Added 500Mhz and 625Mhz GT REFCLK support for versal device
 * Revision change in one or more subcores

2021.2.2:
 * Version 16.2 (Rev. 7)
 * No changes

2021.2.1:
 * Version 16.2 (Rev. 7)
 * Feature Enhancement: Added Support for Artix Ultrascale plus devices

2021.2:
 * Version 16.2 (Rev. 6)
 * Feature Enhancement: Added New device Support for Versal devices
 * Revision change in one or more subcores

2021.1.1:
 * Version 16.2 (Rev. 5)
 * Revision change in one or more subcores

2021.1:
 * Version 16.2 (Rev. 4)
 * Feature Enhancement: Added 156.25 and 312.5 Mhz frequency option to SGMII or 1000BaseX over LVDS for Versal Devices
 * Feature Enhancement: Added lane selection support to GT Based block automation for Versal devices
 * Revision change in one or more subcores

2020.3:
 * Version 16.2 (Rev. 3)
 * Feature Enhancement: Added GTYP Support for Versal Premium devices
 * Feature Enhancement: LVDS support with Advanced IO Wizard IP for Versal devices
 * Feature Enhancement: Removed the reset syncers for gtwiz_reset_tx_done_out and gtwiz_reset_rx_done_out
 * Revision change in one or more subcores

2020.2.2:
 * Version 16.2 (Rev. 2)
 * Feature Enhancement: Added GTYP Support for Versal Premium devices
 * Feature Enhancement: LVDS support with Advanced IO Wizard IP for Versal devices

2020.2.1:
 * Version 16.2 (Rev. 1)
 * No changes

2020.2:
 * Version 16.2 (Rev. 1)
 * Bug Fix: Fixed the GUI issue while selecting the 1000BaseX over LVDS the LVDS refclk option should not be visible
 * Bug Fix: Fixed the BOTH configuration option visibility based on the GT availability
 * Other: Updated the freq_hz param to integer for independent_clock_bufg port
 * Other: Updated with syncers as a part of IP waivers at Axi Ethernet HIP
 * Other: Updated the gt_quad_base and gt_reset_ip core version to v1.1
 * Revision change in one or more subcores

2020.1.1:
 * Version 16.2
 * No changes

2020.1:
 * Version 16.2
 * Feature Enhancement: Updated Versal devices support
 * Feature Enhancement: Updated the FREQ_TOLERANCE_HZ for independent_clock_bufg port
 * Other: Updated with waivers in the XDC
 * Revision change in one or more subcores

2019.2.2:
 * Version 16.1 (Rev. 7)
 * No changes

2019.2.1:
 * Version 16.1 (Rev. 7)
 * No changes

2019.2:
 * Version 16.1 (Rev. 7)
 * Bug Fix: Fixed for TIMINGs DRCs and CDCs
 * Revision change in one or more subcores

2019.1.3:
 * Version 16.1 (Rev. 6)
 * No changes

2019.1.2:
 * Version 16.1 (Rev. 6)
 * No changes

2019.1.1:
 * Version 16.1 (Rev. 6)
 * No changes

2019.1:
 * Version 16.1 (Rev. 6)
 * Bug Fix: Updated the reset logic for s_axi_resetn to AXI4 lite ipif module
 * Bug Fix: Updated GUI DRC check for Drp Clock Rate
 * Bug Fix: Updated the CDR logic for Master and Slave data read from FIFO for 1000BaseX and SGMII mode for AR-72084
 * Bug Fix: Updated the fix for auto-neg restart self clear for cl37
 * Revision change in one or more subcores

2018.3.1:
 * Version 16.1 (Rev. 5)
 * No changes

2018.3:
 * Version 16.1 (Rev. 5)
 * Feature Enhancement: Added 2.5G speed support for Artix-7 -2L devices
 * Feature Enhancement: Added support for preamble shrinkage for 2.5G core speed
 * Revision change in one or more subcores

2018.2:
 * Version 16.1 (Rev. 4)
 * Bug Fix: Updated the rxuserclk/rxuserclk2 clock generation with BUFGCE and CE is connected to MMCM_LOCKED
 * Other: Cleared the IntRdEna based on the IntReset assertion
 * Other: Added new devices GTY support
 * Revision change in one or more subcores

2018.1:
 * Version 16.1 (Rev. 3)
 * Bug Fix: Fixed the lvds refclk selection based on sync and async clock configuration in the GUI
 * Bug Fix: Updated the REFCLK pin frequency for IDELAYE2 based on the input clock
 * Revision change in one or more subcores

2017.4:
 * Version 16.1 (Rev. 2)
 * Feature Enhancement: Added support for rxoutclk for 1588 ptp
 * Other: Updated for timing fix
 * Revision change in one or more subcores

2017.3:
 * Version 16.1 (Rev. 1)
 * Unwanted constraint of create_clock on rxoutclk removed from XDC
 * Incorrect dumping of transceiver file in example design folder corrected when GT in example design is chosen.
 * In the transceiver module, the toggle switch is made independent of the rxreset to make sure the TX data is not disturbed
 * Revision change in one or more subcores

2017.2:
 * Version 16.1
 * gtpowergood output port added for Ultrascale and Ultrascale+ devices in modes with transceivers.
 * Ultrascale+ production support added.

2017.1:
 * Version 16.0 (Rev. 2)
 * Parameter added InstantiateBitslice0 for Native Mode LVDS Solution.
 * Port updates in Native mode LVDS Solution to support integration of multiple IP instances seemlessly.
 * Multiple reference clock option given for Synchronous SGMII Native Mode LVDS Solution selectable based on ClockSelection parameter.
 * Revision change in one or more subcores

2016.4:
 * Version 16.0 (Rev. 1)
 * Bugfix for clock correction in rx elastic buffer for Asynchronous LVDS modes.
 * Updates in constraints for SGMII mode when interfaced with GEM.
 * For 7-Series LVDS transceiver dependency of Transmitter reset on phy loss of sync removed.
 * Revision change in one or more subcores

2016.3:
 * Version 16.0
 * Port Change: phyaddr port added ,earlier this was a core parameter.
 * Bug Fix: naming of generated clock removed from block XDC while interfacing with GEM,to avoid naming conflict in case of multiple instances of IP
 * New Feature: Added support for Multi-lane Asynchronous SGMII/BASEX over LVDS for Ultrascale and Ultrascale+ devices
 * New Feature: Added option to select GT location for Ultrascale and Ultrascale+ devices
 * Feature Enhancement: Added support for Spartan-7 Devices.
 * Feature Enhancement: Added logic to perform clock correction on C1/C2 code groups in recieve elastic buffer.
 * Feature Enhancement: Added option to choose from Synchronous SGMII based on component mode and Asynchronous SGMII solution based on Native mode of IO for Ultrascale.
 * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
 * Revision change in one or more subcores

2016.2:
 * Version 15.2 (Rev. 1)
 * Bugfix for extra port required by GTWizard for older Ultrascale devices which used callibration logic.
 * Revision change in one or more subcores

2016.1:
 * Version 15.2
 * Adding GTYE3 and GTYE4 support.
 * Adding selection option for GTH and GTY transceivers for Ultrascale and Ultrascale+ devices.
 * Added support for Virtex Ultrascale+ devices.
 * Added support to interface with GEM of Zynq Ultrascale+ devices.
 * Added support for GT in example design for Ultrascale and Ultrascale+ devices.
 * Added support for Rx GMII interface to work at RXOUTCLK.
 * Changes to HDL library management to support Vivado IP simulation library
 * Revision change in one or more subcores

2015.4.2:
 * Version 15.1 (Rev. 1)
 * No changes

2015.4.1:
 * Version 15.1 (Rev. 1)
 * No changes

2015.4:
 * Version 15.1 (Rev. 1)
 * Updated Default Latency numbers of GTXE2 and GTHE2 transceivers.
 * Removing Transceiver_type user parameter as its redundant and not user editable.
 * Revision change in one or more subcores

2015.3:
 * Version 15.1
 * Added Zynq Ultrascale plus support.
 * Changing txdiffctrl default value to "1000".
 * Added 2.5G support to Artix-7 devices (-2 and -3 speed grades) devices.
 * Added 3ms startup delay on CPLL/PLL0 controlled by EXAMPLE_SIMULATION.
 * GT wizard updated to v3_6 for Series-7 transceivers.
 * Register 2 and Register 3 updated with OUI values for Xilinx.
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

2015.2.1:
 * Version 15.0 (Rev. 1)
 * No changes

2015.2:
 * Version 15.0 (Rev. 1)
 * Default Insertion Loss at Nyquist value of transceiver configuration preset changed to result in better default RX equalization settings for Gigabit-Ethernet preset; now using LPM rather than DFE

2015.1:
 * Version 15.0
 * Added 2.5 Support for Series-7 Devices(Except Artix-7 and Zynq devices with Artix Fabric) and Ultrascale Devices.
 * 1588 permutations using the Time-of-Day format,An issue has been fixed in the receiver timestamp whereby the seconds field could occasionally be in advance by 1 second.
 * Fixed SGMII over LVDS issue in deseialization for Ultrascale Devices.
 * Added options for gtrefclk and DRP/Freerun Clock (Independent Clock) in GUI for Ultrascale Devices.
 * Default Series-7 Equalization changed to LPM from DFE for GTHE2 and GTXE2 transceivers to match GT Wizard.
 * GT wizard updated to v3_5 for Series-7 transceivers.
 * Moved required BUFG on gtrefclk in devices with GTHE2 and GTXE2 to shared logic.
 * Moved BUFG on recovered clock to shared logic.
 * Added mmcm_reset output port for configurations using transceiver to reset the external mmcm to generate userclk/userclk2.
 * Constraints updates.
 * Added txinhibit to the transceiver debug signals.
 * Added pcsrsvdin to the transceiver debug signals for ultrascale devices.
 * C_RUDI behaviour fixed by adding pipeline on RXCLKCORCNT.
 * gtwizard_ultrascale upgraded to v1_5.

2014.4.1:
 * Version 14.3 (Rev. 1)
 * No changes

2014.4:
 * Version 14.3 (Rev. 1)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Added support for 7-Series Defense-grade, Automotive, and Low Voltage parts.
 * Corrected value of dont_reset_on_data_error input to 7-Series Transceiver FSMs to 0.
 * Changed default value of RXPRBS_ERR_LOOPBACK to 0 for 7-Series Transceivers.
 * Disabling Reset of GT FSMs in case of prbs selection for 7-Series Transceivers.

2014.3:
 * Version 14.3
 * gtwizard_ultrascale upgraded to v1_4.
 * GT updates for Series-7 transceivers.
 * Fix done for high temperature callibration failure for sgmii over lvds in Series-7
 * Added 3 seconds watchdog timer which resets rx path for sgmii over lvds modes and also in case of 7 series transceiver
 * Soft reset provision added for sgmii over lvds
 * Bugfix for AutoNegotiation resetting in case of resetdone deassertion instead of pausing
 * Included component library in vhdl block and block wrapper
 * Changed BUFG to BUFH on rxoutclk for Base-X and SGMII mode without fabric elastic buffer for Series-7
 * Reduced timing DRCs and warnings
 * Changed size of gt0_dmonitor_width depending on type of transceiver
 * Corrected rxpmaresetdone port in cases where it was undriven

2014.2:
 * Version 14.2 (Rev. 1)
 * gtwizard_ultrascale upgraded to v1_3.
 * Minor constraints modification as per change in tool behaviour.
 * Removal and corrections in unused synchronizers in 7-Series transceiver Reset FSM.

2014.1:
 * Version 14.2
 * Enabling SGMII over LVDS feature for Ultrascale devices.
 * GT updates for Series-7 transceivers (Tx/Rx startup FSM updates).
 * Source of rxusrclk and rxusrclk2 for BASEX modes changed to rxoutclk instead of txoutclk.
 * Added missing XDC constraints  for rxoutclk in BASEX mode.
 * Change in definition of resetdone port.It now indicates the completion of rx and tx startup sequence.
 * Transceiver reset done indication gated with LINK_STATUS indication register.
 * Optional External MDIO interface added to control external phy,added optional parameter Ext_Management_Interface.
 * Changed EXAMPLE_SIMULATION Parameter from Boolean to Integer.
 * Freerunning clock of 50Mhz added for ultrascale devices for sgmii and basex modes .
 * Virtex UltraScale Pre-Production support added.
 * Internal device family name change, no functional changes
 * Support for Zynq7015 device added.

2013.4:
 * Version 14.1
 * Kintex Ultrascale Pre-Production Support.
 * Increased the number of optional transceiver control and status ports.
 * GT updates for Series-7 transceivers (Tx/Rx startup FSM updates).

2013.3:
 * Version 14.0
 * Link timer value ports removed from block_wrapper
 * GT updates for Series-7 transceivers (Termination settings updates,attribute updates,hierarchy update).
 * Enhanced support for IP Integrator.
 * Reduced warnings in synthesis and simulation.
 * Updated clock synchronizers to improve Mean Time Between Failures (MTBF) for metastability.
 * Added optional transceiver control and status ports.
 * Added support for the out of context flow.
 * Added GUI option to include or exclude shareable logic resources in the core. Please refer to the Product Guide for information and port changes.
 * New board GUI tab for targeting evaluation boards
 * Marking Production for Virtex-7 and Zynq-7000 families.

2013.2:
 * Version 13.0
 * Constraints processing order changed.
 * Phyad made a GUI parameter.
 * eye_mon_wait_time removed from block_wrapper portlist.
 * GT updates for Series-7 transceivers.
 * Added AN Support for Zynq GEM for SGMII over Transceiver and SGMII over LVDS modes
 * Marking Production for Artix-7 family.

2013.1:
 * Version 12.0
 * GT updates for Series-7 transceivers.
 * Added Zynq support for SGMII over LVDS feature.
 * Added parameter EXAMPLE_SIMULATION to be tied 1 in simulation.
 * Marking Production for Kintex-7 family.

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