m255
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R0
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R0
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!s11f vlog 2021.2_1 2021.05, May 15 2021
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!s112 1.1
!i10d 8192
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!i10f 100
cModel Technology
Z1 d/home/ankaoc/Desktop/rocket/rocket-chip/targets/asic/rocket
T_opt
!s110 1783629340
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Z2 04 14 4 work asic_rocket_tb fast 0
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Z3 !s124 OEM100
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Z4 tCvgOpt 0
n@_opt
Z5 OL;O;2021.2_1;73
R1
T_opt1
!s110 1783633806
ViK;F?JzUaIlf8Vzm70F7P1
R2
=1-000ae431a4f1-6a50178d-cf22e-11760
R3
o-quiet -auto_acc_if_foreign -work /home/onur/Desktop/rocket/rocket-chip/targets/asic/rocket/work -suppress 3009
R4
n@_opt1
R5
R1
T_opt2
!s110 1783629933
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R2
=1-000ae431a4f1-6a50086d-29125-10746
R3
o-quiet -auto_acc_if_foreign -work targets/asic/rocket/work -suppress 3009 +acc
R4
n@_opt2
R5
R1
vaccum_dump
Z6 DXx6 sv_std 3 std 0 22 9oUSJO;AeEaW`l:M@^WG92
R6
Z7 DXx4 work 11 definitions 0 22 f]1[P940GzQNm3]c1g86Z2
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Z8 !s110 1783636363
Z9 VDg1SIo80bB@j0V0VzS_@n1
r1
!s85 0
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!s100 J=:0>8Jgoee<[eLDmE2zc3
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!s105 accum_dump_sv_unit
S1
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Z11 w1780558678
Z12 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv
Z13 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv
!i122 37
L0 3 149
Z14 OL;L;2021.2_1;73
31
Z15 !s108 1783636363.000000
!s107 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Z16 !s90 +define+PRINTF_COND=0|-sv|-work|work|-f|/home/onur/Desktop/rocket/rocket-chip/targets/asic/rocket/out/filelists/asic_rtl.f|
!i113 0
Z17 o-sv -work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
Z18 !s92 +define+PRINTF_COND=0 -sv -work work +incdir+/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
R4
Xaccum_dump_sv_unit
R6
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R7
R8
VGhPX;kk]ULB>BJ0=j=fRN2
r1
!s85 0
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!s100 =H74fBC]Zl6z=6F_B_7ND0
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S1
R10
R11
R12
R13
!i122 37
Z19 L0 1 0
R14
31
R15
Z20 !s107 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esktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DCache.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CompareRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_sbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_aggregator.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroup.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w55.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w43.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w15.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_UInt5_To_UInt5.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_DTMInfo_To_DTMInfo.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureChain_JTAGIdcodeBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CSRFile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CLINTClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CLINT.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/BreakpointUnit.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncValidSync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetRegVec_w2_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetRegVec_w1_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_TLBundleD_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_TLBundleA_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_DebugInternalBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_TLBundleD_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_TLBundleA_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_DebugInternalBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter8_DCacheMetadataReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter4_DCacheDataReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter3_LLWB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter2_Valid_PTWReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/APBGpsBlock.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AMOALU.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/clock/asic_pll_model.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/pulse_gen.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/trck_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acq_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/sync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/spill_register.sv|/home/onur/Desktop/r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R16
!i113 0
R17
R18
R4
vacq_ca_gen
R6
R6
R7
DXx4 work 18 acq_ca_gen_sv_unit 0 22 WV99DYM:ZjhDca49LI3=12
R8
R9
r1
!s85 0
!i10b 1
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IaFXZzGKhOLB1`Wca[zNGH0
!s105 acq_ca_gen_sv_unit
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R10
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31
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R21
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31
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vacq_channel_fast
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R10
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vacq_corr
R6
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31
R15
R20
R16
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Xacq_corr_sv_unit
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R7
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VHG@`:nAjF0FD2ALag7iDX3
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R10
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R24
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R20
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vacq_nco_carr
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31
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R20
R16
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Xacq_nco_carr_sv_unit
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R7
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R10
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R27
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!i122 37
R19
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31
R15
R20
R16
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R18
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vacq_peak_srch
R6
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r1
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R20
R16
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vacq_top
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31
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Xacq_top_sv_unit
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VG?SDcc2;O9oBc[1>bPcic2
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R10
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R29
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31
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R20
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vacq_wrapper
R6
R6
R7
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Xacq_wrapper_pkg
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vafe_top
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31
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R20
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VeokLl4n=Qch3iDN9:MRnI1
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R33
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R23
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vAMOALU
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31
R15
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n@a@m@o@a@l@u
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/APBGpsBlock.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/APBGpsBlock.sv
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r1
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31
R15
R20
R16
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R18
R4
n@a@p@b@gps@block
vArbiter2_Valid_PTWReq
R6
R8
!i10b 1
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter2_Valid_PTWReq.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter2_Valid_PTWReq.sv
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Z36 L0 31 12
R9
R14
r1
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31
R15
R20
R16
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R18
R4
n@arbiter2_@valid_@p@t@w@req
vArbiter3_LLWB
R6
R8
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter3_LLWB.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter3_LLWB.sv
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Z37 L0 31 16
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R14
r1
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31
R15
R20
R16
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R18
R4
n@arbiter3_@l@l@w@b
vArbiter4_DCacheDataReq
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R8
!i10b 1
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter4_DCacheDataReq.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter4_DCacheDataReq.sv
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R14
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R15
R20
R16
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R17
R18
R4
n@arbiter4_@d@cache@data@req
vArbiter8_DCacheMetadataReq
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R8
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter8_DCacheMetadataReq.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter8_DCacheMetadataReq.sv
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R14
r1
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31
R15
R20
R16
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R17
R18
R4
n@arbiter8_@d@cache@metadata@req
vasic_pll_model
R6
R8
!i10b 1
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R10
w1783014475
8/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/clock/asic_pll_model.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/clock/asic_pll_model.sv
!i122 37
L0 3 40
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vasic_rocket_tb
R6
Z38 !s110 1783633804
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R10
w1783027532
8/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/asic_rocket_tb.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/asic_rocket_tb.sv
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R14
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31
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Z81 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv
!i122 37
L0 19 70
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@l@f_carr
XLF_carr_sv_unit
R6
R6
R7
R8
V2nR<[cH7gngS<Af^9Mhdj3
r1
!s85 0
!i10b 1
!s100 aQ2iilmS>DBz^QLg8?n>a3
I2nR<[cH7gngS<Af^9Mhdj3
!i103 1
S1
R10
R11
R80
R81
!i122 37
L0 17 0
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@l@f_carr_sv_unit
vLF_code
R6
R6
R7
DXx4 work 15 LF_code_sv_unit 0 22 Qc0njBN_R]mViBEkSKjE`3
R8
R9
r1
!s85 0
!i10b 1
!s100 D6;k1D2I6RMNYG63IGD?91
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!s105 LF_code_sv_unit
S1
R10
R11
Z82 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv
Z83 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv
!i122 37
L0 18 85
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@l@f_code
XLF_code_sv_unit
R6
R6
R7
R8
VQc0njBN_R]mViBEkSKjE`3
r1
!s85 0
!i10b 1
!s100 [<E5RQULnH>11I^^YPbS=0
IQc0njBN_R]mViBEkSKjE`3
!i103 1
S1
R10
R11
R82
R83
!i122 37
L0 16 0
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@l@f_code_sv_unit
vlock_detector
R6
R6
R7
DXx4 work 21 lock_detector_sv_unit 0 22 kdjF[IBCz`c=7Z[F]Q5P@3
R8
R9
r1
!s85 0
!i10b 1
!s100 Hk7]o9MFB;c4MSlEASSLl1
IHOJ`:dWR``D9_OP3:_>I^1
!s105 lock_detector_sv_unit
S1
R10
R49
Z84 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv
Z85 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv
!i122 37
L0 23 144
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xlock_detector_sv_unit
R6
R6
R7
R8
VkdjF[IBCz`c=7Z[F]Q5P@3
r1
!s85 0
!i10b 1
!s100 g_bAl1Z35o?77^I[V66o@0
IkdjF[IBCz`c=7Z[F]Q5P@3
!i103 1
S1
R10
R49
R84
R85
!i122 37
R26
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vMulAddRecFNPipe_l2_e11_s53
R6
R8
!i10b 1
!s100 nBmOdVZIoXoRHzJUAgngi0
IK7^T`;lkha?MiPXdG006M2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv
!i122 37
L0 31 209
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@pipe_l2_e11_s53
vMulAddRecFNPipe_l2_e8_s24
R6
R8
!i10b 1
!s100 HKO>XKOTS``L;LX`T:bOh2
IFe[o<KCXgfMa3Q:k9SMId3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e8_s24.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e8_s24.sv
!i122 37
R54
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@pipe_l2_e8_s24
vMulAddRecFNToRaw_postMul
R6
R8
!i10b 1
!s100 Z[>8[U9DMhkSTQB`OJL6C0
Ia3a8I[zBW[`MaOELdl>YJ0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul.sv
!i122 37
L0 31 165
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@to@raw_post@mul
vMulAddRecFNToRaw_postMul_1
R6
R8
!i10b 1
!s100 _<dm4h_T5GGb;VCN61]]42
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S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul_1.sv
!i122 37
L0 31 252
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@to@raw_post@mul_1
vMulAddRecFNToRaw_preMul
R6
R8
!i10b 1
!s100 z`]hA;A;S<jz@o_28@;Q03
I<P441oTE?ohJ`<BYNo<942
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul.sv
!i122 37
Z86 L0 31 83
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@to@raw_pre@mul
vMulAddRecFNToRaw_preMul_1
R6
R8
!i10b 1
!s100 Io:08M:;VNkAlDO1J7V^:2
I]e7igRYAG_JJcfnJQNc0C1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul_1.sv
!i122 37
R58
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@to@raw_pre@mul_1
vMulDiv
R6
R8
!i10b 1
!s100 =mK<zIVYXU1hU1nDBS6lf2
I05OjT:]Doa2Zj;=?>J<Bj0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulDiv.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulDiv.sv
!i122 37
L0 31 119
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@div
vnav_solve_timer
R6
DXx4 work 19 nav_solve_timer_pkg 0 22 fEzomUEUnah:ca3mRzJLD3
R8
!i10b 1
!s100 SJ?dhoKiGMSQObUz2YQj[1
ISCWCci5RImQ]QiAC0D9YT0
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer.sv
!i122 37
L0 2 77
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
Xnav_solve_timer_pkg
R6
R8
!i10b 1
!s100 i5:488b=QGWggLM0?aEc^3
IfEzomUEUnah:ca3mRzJLD3
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer_pkg.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer_pkg.sv
!i122 37
R75
VfEzomUEUnah:ca3mRzJLD3
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vNCO_carr
R6
R6
R7
DXx4 work 16 NCO_carr_sv_unit 0 22 <L6<gRz>J35NDKf:SYT?`1
R8
R9
r1
!s85 0
!i10b 1
!s100 `78U5<Y[ACERAJai<TcNI1
Ic7z_0Q=^dOzz]ZBSkee>Z1
!s105 NCO_carr_sv_unit
S1
R10
R11
Z87 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv
Z88 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv
!i122 37
L0 14 120
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@n@c@o_carr
XNCO_carr_sv_unit
R6
R6
R7
R8
V<L6<gRz>J35NDKf:SYT?`1
r1
!s85 0
!i10b 1
!s100 knc[3zG1VXI^ka`8>nX0K3
I<L6<gRz>J35NDKf:SYT?`1
!i103 1
S1
R10
R11
R87
R88
!i122 37
L0 12 0
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@n@c@o_carr_sv_unit
vNCO_code
R6
R6
R7
DXx4 work 16 NCO_code_sv_unit 0 22 Q^Ge;zzNd2:<JSNNH31191
R8
R9
r1
!s85 0
!i10b 1
!s100 O7=1k7P83m3LQA]6TZY7I1
ISVDTm<XbCi`nmD994eiDE3
!s105 NCO_code_sv_unit
S1
R10
Z89 w1783624211
Z90 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_code.sv
Z91 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_code.sv
!i122 37
L0 22 157
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@n@c@o_code
XNCO_code_sv_unit
R6
R6
R7
R8
VQ^Ge;zzNd2:<JSNNH31191
r1
!s85 0
!i10b 1
!s100 3jjc4:14hMgiz:EFKVENM3
IQ^Ge;zzNd2:<JSNNH31191
!i103 1
S1
R10
R89
R90
R91
!i122 37
R23
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@n@c@o_code_sv_unit
vNonSyncResetSynchronizerPrimitiveShiftReg_d3
R6
R8
!i10b 1
!s100 I^_Rhd2nfzBlbkMOIm>5O0
ICBkPZ3n`7oG@5CMT6h5L52
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv
!i122 37
R37
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@non@sync@reset@synchronizer@primitive@shift@reg_d3
vOptimizationBarrier_TLBEntryData
R6
R8
!i10b 1
!s100 9NLE99UkeAB?HI2Oh8GdM2
Ia0UfOkGEY1Q_fjT1z5lm<3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/OptimizationBarrier_TLBEntryData.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/OptimizationBarrier_TLBEntryData.sv
!i122 37
Z92 L0 31 52
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@optimization@barrier_@t@l@b@entry@data
vPeripheryBus_cbus
R6
R8
!i10b 1
!s100 PNUadYGX`m]?cG<9YI0kf3
Ik^B64X]U5jH>feWGOgMSf3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_cbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_cbus.sv
!i122 37
L0 31 1456
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@periphery@bus_cbus
vPeripheryBus_pbus
R6
R8
!i10b 1
!s100 `GM_:@^oETlhk5d?`CckF1
IW<i_IAPPoljVfQ[Cjo`aQ0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_pbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_pbus.sv
!i122 37
L0 31 1048
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@periphery@bus_pbus
vPLICClockSinkDomain
R6
R8
!i10b 1
!s100 PZ=A9b_TDmh<4Fg:daDoV0
IYYli7h>Ee;F@1;>]N=niB1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICClockSinkDomain.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICClockSinkDomain.sv
!i122 37
L0 31 67
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@l@i@c@clock@sink@domain
vPLICFanIn
R6
R8
!i10b 1
!s100 bHb>42?c;MH08:fidJIDZ3
IA9]d;@1N<`AC?h9?=HHMK1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICFanIn.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICFanIn.sv
!i122 37
R63
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@l@i@c@fan@in
vplusarg_reader
R6
R8
!i10b 1
!s100 ]N8Qg;1>hCZ5LO5RiYBEZ1
ICfKI^99AHeHcI;z0>J;=i2
S1
R10
Z93 w1782901798
8/home/onur/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/plusarg_reader.v
F/home/onur/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/plusarg_reader.v
!i122 37
L0 7 20
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vPlusArgTimeout
R6
R8
!i10b 1
!s100 YPMIm?E_ofmnJj8zUnWZ?0
IKNzfQEcWk7B;HF07@nC?H2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PlusArgTimeout.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PlusArgTimeout.sv
!i122 37
Z94 L0 31 25
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@plus@arg@timeout
vPMAChecker
R6
R8
!i10b 1
!s100 ^X`=m?6f?g4;F;LNIhHIE2
IP0bSWB^NG8f^SU4S?a[Qm1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMAChecker.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMAChecker.sv
!i122 37
L0 31 79
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@m@a@checker
vPMPChecker_s2
R6
R8
!i10b 1
!s100 ;MKQoLWk`jZ=]9k9l>PbV3
I4<0RT_1gP4lg76BSRmc:V3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s2.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s2.sv
!i122 37
Z95 L0 31 90
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@m@p@checker_s2
vPMPChecker_s3
R6
R8
!i10b 1
!s100 H_dWQPGgzHbk:;PAXH7fA1
IE`]JOf`2UbCjnR:5ANoCK1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s3.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s3.sv
!i122 37
R71
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@m@p@checker_s3
vPTW
R6
R8
!i10b 1
!s100 XX`6Q_Q4@CIGUXCMfodOJ1
IF2QG`=A@aK]4AWW]9_Ka03
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PTW.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PTW.sv
!i122 37
R71
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@t@w
vpulse_gen
R6
R8
!i10b 1
!s100 FXEF97F=?OMJ8cJDAebhE1
ImRFbdH_0Vzd_TnL65l6lA1
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/pulse_gen.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/pulse_gen.sv
!i122 37
R66
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vQueue1_RegMapperInput_i23_m8
R6
R8
!i10b 1
!s100 AokH>W`0;NgMn3Kfj_O<J2
I;B55f;ZRGF^FSbMm:V@aN1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_RegMapperInput_i23_m8.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_RegMapperInput_i23_m8.sv
!i122 37
R69
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue1_@reg@mapper@input_i23_m8
vQueue1_RegMapperInput_i9_m8
R6
R8
!i10b 1
!s100 I`K6:A=EXX@DaffM=8:O53
IVIn4dA4Xf7jCTD>8eg?LJ1
S1
R10
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S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuter.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuter.sv
!i122 37
R68
R9
R14
r1
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31
R15
R20
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R17
R18
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n@t@l@debug@module@outer
vTLDebugModuleOuterAsync
R6
R8
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S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuterAsync.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuterAsync.sv
!i122 37
R74
R9
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31
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n@t@l@debug@module@outer@async
vTLError
R6
R8
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLError.sv
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!i122 37
R86
R9
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31
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n@t@l@error
vTLError_1
R6
R8
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R10
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLError_1.sv
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!i122 37
R73
R9
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31
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n@t@l@error_1
vTLFIFOFixer
R6
R8
!i10b 1
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R10
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer.sv
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!i122 37
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R9
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31
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n@t@l@f@i@f@o@fixer
vTLFIFOFixer_1
R6
R8
!i10b 1
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R10
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer_1.sv
!i122 37
Z114 L0 31 92
R9
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31
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n@t@l@f@i@f@o@fixer_1
vTLFIFOFixer_2
R6
R8
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R10
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer_2.sv
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!i122 37
R114
R9
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31
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n@t@l@f@i@f@o@fixer_2
vTLFpgaSPI
R6
R8
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R10
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaSPI.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaSPI.sv
!i122 37
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R9
R14
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31
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n@t@l@fpga@s@p@i
vTLFpgaUART
R6
R8
!i10b 1
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaUART.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaUART.sv
!i122 37
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R9
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31
R15
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n@t@l@fpga@u@a@r@t
vTLFragmenter_1
R6
R8
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_1.sv
!i122 37
L0 31 159
R9
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31
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n@t@l@fragmenter_1
vTLFragmenter_bootrom
R6
R8
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R10
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_bootrom.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_bootrom.sv
!i122 37
Z115 L0 31 124
R9
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31
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n@t@l@fragmenter_bootrom
vTLFragmenter_CLINT
R6
R8
!i10b 1
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R10
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_CLINT.sv
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!i122 37
R77
R9
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31
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n@t@l@fragmenter_@c@l@i@n@t
vTLFragmenter_Debug
R6
R8
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_Debug.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_Debug.sv
!i122 37
R77
R9
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31
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n@t@l@fragmenter_@debug
vTLFragmenter_FPGAGPS
R6
R8
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_FPGAGPS.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_FPGAGPS.sv
!i122 37
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31
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n@t@l@fragmenter_@f@p@g@a@g@p@s
vTLFragmenter_FPGAUART
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R8
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!i122 37
R77
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31
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n@t@l@fragmenter_@f@p@g@a@u@a@r@t
vTLFragmenter_PLIC
R6
R8
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F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_PLIC.sv
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R77
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31
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n@t@l@fragmenter_@p@l@i@c
vTLInterconnectCoupler_cbus_to_bootrom
R6
R8
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R10
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv
!i122 37
R92
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r1
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31
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n@t@l@interconnect@coupler_cbus_to_bootrom
vTLInterconnectCoupler_cbus_to_bus_named_pbus
R6
R8
!i10b 1
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv
!i122 37
Z116 L0 31 128
R9
R14
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31
R15
R20
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R17
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R4
n@t@l@interconnect@coupler_cbus_to_bus_named_pbus
vTLInterconnectCoupler_cbus_to_clint
R6
R8
!i10b 1
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv
!i122 37
Z117 L0 31 66
R9
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r1
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31
R15
R20
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!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_cbus_to_clint
vTLInterconnectCoupler_cbus_to_debug
R6
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!i10b 1
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv
!i122 37
R117
R9
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r1
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31
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n@t@l@interconnect@coupler_cbus_to_debug
vTLInterconnectCoupler_cbus_to_plic
R6
R8
!i10b 1
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R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv
!i122 37
R117
R9
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r1
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31
R15
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R18
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n@t@l@interconnect@coupler_cbus_to_plic
vTLInterconnectCoupler_cbus_to_rockettile
R6
R8
!i10b 1
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv
!i122 37
R52
R9
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31
R15
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!i113 0
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n@t@l@interconnect@coupler_cbus_to_rockettile
vTLInterconnectCoupler_fbus_from_debug_sb
R6
R8
!i10b 1
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R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv
!i122 37
L0 31 72
R9
R14
r1
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31
R15
R20
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!i113 0
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R18
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n@t@l@interconnect@coupler_fbus_from_debug_sb
vTLInterconnectCoupler_pbus_to_fpga_uart
R6
R8
!i10b 1
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv
!i122 37
R117
R9
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r1
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31
R15
R20
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!i113 0
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n@t@l@interconnect@coupler_pbus_to_fpga_uart
vTLInterconnectCoupler_pbus_to_gps
R6
R8
!i10b 1
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv
!i122 37
L0 31 267
R9
R14
r1
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R15
R20
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!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_pbus_to_gps
vTLInterconnectCoupler_sbus_from_bus_named_fbus
R6
R8
!i10b 1
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv
!i122 37
R115
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_sbus_from_bus_named_fbus
vTLInterconnectCoupler_sbus_from_rockettile
R6
R8
!i10b 1
!s100 3@>8mNk6j0ZkeNjEgj8z83
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R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv
!i122 37
R114
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_sbus_from_rockettile
vTLInterconnectCoupler_sbus_to_bus_named_cbus
R6
R8
!i10b 1
!s100 ?4X]HHkaSS5jIWKHVk7So1
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv
!i122 37
R116
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
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n@t@l@interconnect@coupler_sbus_to_bus_named_cbus
vTLPLIC
R6
R8
!i10b 1
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8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLPLIC.sv
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!i122 37
L0 31 380
R9
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31
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n@t@l@p@l@i@c
vTLROM
R6
R8
!i10b 1
!s100 Cf3]^CeiDe4GUFJZE;Jiz3
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLROM.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLROM.sv
!i122 37
L0 31 277
R9
R14
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31
R15
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R18
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n@t@l@r@o@m
vTLToAPB
R6
R8
!i10b 1
!s100 0ff_LnR^7fWN:oIe>21mm1
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLToAPB.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLToAPB.sv
!i122 37
L0 31 130
R9
R14
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31
R15
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n@t@l@to@a@p@b
vTLWidthWidget1
R6
R8
!i10b 1
!s100 RBKF>KgXZcKEcABFML[S_3
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R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget1.sv
!i122 37
R62
R9
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31
R15
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n@t@l@width@widget1
vTLWidthWidget8
R6
R8
!i10b 1
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n@v@c@u118@rocket@system
