Merge tdk_new and Ti375 Efinity support

Keep the current GPS software and Genesys2/VCU118 flows while integrating Ti375C529 Efinity, flash, programming, and debug support. Add board-specific SPI NOR profiles and persistent GPS flash layouts across all three boards.
This commit is contained in:
onur
2026-08-13 01:28:46 +03:00
33 changed files with 2434 additions and 180 deletions
+10 -4
View File
@@ -10,8 +10,8 @@ FPGA_BOARD ?= vcu118
endif
FPGA_TARGET_DIR := targets/fpga/$(FPGA_BOARD)
.PHONY: help doctor soc-hw fpga-rtl fpga-bitstream fpga-elf-flash-image fpga-mcs fpga-flash-app fpga-flash fpga-flash-bitstream fpga-flash-mcs fpga-flash-all fpga-program fpga-debug-openocd fpga-debug-load fpga-uart fpga-config asic-rtl asic-sim clean
.PHONY: fpga_rtl fpga_bitstream fpga_elf_flash_image fpga_mcs fpga_flash_app fpga_flash fpga_flash_bitstream fpga_flash_mcs fpga_flash_all fpga_program fpga_debug_openocd fpga_debug_load fpga_uart fpga_config
.PHONY: help doctor soc-hw fpga-rtl fpga-bitstream fpga-elf-flash-image fpga-mcs fpga-flash-app fpga-flash fpga-flash-bitstream fpga-flash-mcs fpga-flash-all fpga-program fpga-detect fpga-debug-openocd fpga-debug-load fpga-uart fpga-config asic-rtl asic-sim clean
.PHONY: fpga_rtl fpga_bitstream fpga_elf_flash_image fpga_mcs fpga_flash_app fpga_flash fpga_flash_bitstream fpga_flash_mcs fpga_flash_all fpga_program fpga_detect fpga_debug_openocd fpga_debug_load fpga_uart fpga_config
help:
@printf '%s\n' \
@@ -19,11 +19,12 @@ help:
' make doctor # check local JDK/Mill/CIRCT and RISC-V tools' \
' make soc-hw # emit shared SoC FIRRTL through FPGA config' \
' make fpga-rtl # emit selected FPGA SystemVerilog and wrapper' \
' make fpga-bitstream # run selected FPGA Vivado bitstream flow' \
' make fpga-bitstream # run selected board vendor bitstream flow' \
' make fpga-elf-flash-image' \
' # build APP ELF and board flash-format app image' \
' make fpga-mcs # generate combined bitstream + app MCS/BIN' \
' make fpga-program # program selected FPGA SRAM' \
' make fpga-detect # run selected board USB/JTAG detection target' \
' make fpga-flash-app # build flash-format app image and program app flash region' \
' make fpga-flash # alias for fpga-flash-app' \
' make fpga-flash-bitstream' \
@@ -39,7 +40,7 @@ help:
' make asic-sim # run ASIC-style Questa sanity simulation' \
'' \
'Config:' \
' FPGA_BOARD=$(FPGA_BOARD) # vcu118 or genesys2' \
' FPGA_BOARD=$(FPGA_BOARD) # vcu118, genesys2, or ti375c529' \
' UART_BAUD=460800 # FPGA firmware and host listener default' \
' GPS_ESKF_ENABLE=1 # gps_system: 1 ESKF, 0 GPS-only' \
' IMU_SENSOR=auto # gps_system: auto, tdk, st or stm' \
@@ -49,6 +50,7 @@ help:
' make -C hardware/soc help' \
' make -C targets/fpga/vcu118 help' \
' make -C targets/fpga/genesys2 help' \
' make -C targets/fpga/ti375c529 help' \
' make -C targets/asic/rocket help'
doctor:
@@ -72,6 +74,9 @@ fpga-mcs:
fpga-program:
$(MAKE) -C $(FPGA_TARGET_DIR) program-fpga
fpga-detect:
$(MAKE) -C $(FPGA_TARGET_DIR) detect
fpga-flash-app fpga-flash:
$(MAKE) -C $(FPGA_TARGET_DIR) program-flash
@@ -106,6 +111,7 @@ fpga_flash_bitstream: fpga-flash-bitstream
fpga_flash_mcs: fpga-flash-mcs
fpga_flash_all: fpga-flash-all
fpga_program: fpga-program
fpga_detect: fpga-detect
fpga_debug_openocd: fpga-debug-openocd
fpga_debug_load: fpga-debug-load
fpga_uart: fpga-uart