Document STEVAL INT1 hardware verification
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@@ -14,13 +14,15 @@ be integrated separately after the IMU link is verified.
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| SDA | JC2 | SPI MOSI / SDI |
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| SDO | JC3 | SPI MISO |
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| SCL | JC4 | SPI clock / SPC |
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| INT1 | JC9 | active-high data-ready interrupt |
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| VDD | 3.3 V | sensor supply |
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| VDDIO | 3.3 V | digital I/O supply |
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| GND | GND | common ground |
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| INT1 | JB1 | active-high data-ready interrupt |
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| VDD | JC6 / 3.3 V | sensor supply |
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| VDDIO | JC12 / 3.3 V | digital I/O supply |
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| GND | JC5 or JC11 | common ground |
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`CS` is mandatory for four-wire SPI. Never feed 5 V to VDDIO. JC9 is routed
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through the FPGA 3FF synchronizer to PLIC device 11.
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`CS` is mandatory for four-wire SPI. Never feed 5 V to VDDIO. The current
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Genesys2 constraint routes JB1 (`V29`) through the FPGA 3FF synchronizer to
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PLIC device 11. Older README revisions named JC9 (`AK30`); that mapping is no
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longer valid. JC10 is reserved for the GPS PPS output.
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## Hardware bring-up results (2026-07-13)
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@@ -65,6 +67,36 @@ These measurements are for the stationary board in its test orientation. The
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nonzero gyro mean is startup bias to be estimated by stationary calibration,
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not angular motion.
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### INT1 live recheck (2026-07-16)
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The current `tdk_ekf` Genesys2 bitstream was reused without synthesis. The
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standalone ELF was loaded into DTIM through the already-running OpenOCD/GDB
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server and UART was observed on `/dev/ttyUSB2` at 115200 baud.
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With only SPI connected, all eight `WHO_AM_I` probes returned `0x6c`,
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configuration read-back was `CTRL1_XL=0x40`, `CTRL2_G=0x40`,
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`CTRL3_C=0x44`, `STATUS=0x07`, and foreground polling returned coherent
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samples. No `IMU_RAW` rows arrived from the interrupt test and the final
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`interrupt_count` was zero. This separated a working SPI/data path from a
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missing physical interrupt connection.
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After STEVAL `INT1` was moved to Genesys2 JB1, the same ELF immediately
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produced continuous interrupt-driven `IMU_RAW` rows. A live counter snapshot
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showed:
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- `interrupt_count=4084` and `interrupt_sample_count=4084`;
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- `interrupt_read_fail_count=0` and `queue_overflow_count=0`;
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- `unexpected_irq_count=0` and `unexpected_trap_cause=0`;
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- sequence 0 through 1165 covered 11.012478 seconds, corresponding to
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105.789 Hz and a 9.453 ms mean period for the configured 104 Hz ODR.
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One representative stationary sample was accel `[-3854, -9397, -13071]`,
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gyro `[35, -4, -32]`, and temperature raw `1265`. The sequence continued
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monotonically during the observed UART window. This verifies the physical
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STEVAL INT1 -> JB1/V29 -> 3FF synchronizer -> PLIC 11 -> C ISR -> SPI burst ->
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SPSC queue path. It does not yet constitute a combined GPS + ST + ESKF moving
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platform test.
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## Build and load
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From the repository root:
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