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Document STEVAL INT1 hardware verification

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onur
2026-07-16 17:51:43 +03:00
parent 927f6e2858
commit 38a96dd88f
4 changed files with 78 additions and 34 deletions
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targets/fpga/genesys2/README.md
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@@ -127,12 +127,15 @@ pmod_spi_dq[3] AG30 JC8
Pin constraintleri `hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc`
dosyasindadir ve Vivado akisi tarafindan her RF modunda okunur.
Sensorden gelen external interrupt hatti SPI'dan bagimsizdir. `pmod_irq`
olarak JC9'a cikar ve PLIC'te `BSP_PMOD_IRQ` (`11`) ID'siyle gorunur.
Sensorden gelen external interrupt hatti SPI'dan bagimsizdir. Guncel pin
planinda `pmod_irq` PMOD JB pin 1'e cikar ve PLIC'te `BSP_PMOD_IRQ` (`11`)
ID'siyle gorunur. Eski `JC9/AK30` eslemesi 2026-07-14'te `JB1/V29` olarak
degistirildi; mevcut XDC ve bitstream icin sensor `INT1` hatti JB1'e
baglanmalidir. JC10 GPS PPS cikisidir.
```text
port FPGA pin PMOD pin
pmod_irq AK30 JC9
pmod_irq V29 JB1
```
Pin constraintleri `hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc`