diff --git a/README.md b/README.md
index 9b1a537..998e590 100644
--- a/README.md
+++ b/README.md
@@ -560,12 +560,12 @@ interface:        SPIx4
 
 ### Ti375C529 Efinity build ve flash
 
-Efinity `/tools/efinix/efinity`, `/opt`, kullanici dizini ve
-`tools/local/efinity` altinda aranir. Farkli bir kurulum
-`EFINITY_HOME=/path/to/efinity/2025.2` ile secilebilir. `fpga-bitstream`, uzun
-RTL elaborasyonundan once kurulumdaki `bin/setup.sh` ve `scripts/efx_run.py`
-dosyalarini kontrol eder. Build, SRAM'e gecici programlama ve kart tespiti
-kokten su sekilde yapilir:
+Efinity `/tools/efinix/efinity`, `/tools/Efinix/efinity`, `/opt`, kullanici
+dizini ve `tools/local/efinity` altinda aranir. Farkli bir kurulum
+`EFINITY_HOME=/path/to/efinity/<version>` ile secilebilir. `fpga-bitstream`,
+uzun RTL elaborasyonundan once kurulumdaki `bin/setup.sh` ve
+`scripts/efx_run.py` dosyalarini kontrol eder. Build, SRAM'e gecici programlama
+ve kart tespiti kokten su sekilde yapilir:
 
 ```sh
 make FPGA_BOARD=ti375c529 fpga-config
diff --git a/targets/fpga/ti375c529/Makefile b/targets/fpga/ti375c529/Makefile
index 2f508eb..82cfc56 100644
--- a/targets/fpga/ti375c529/Makefile
+++ b/targets/fpga/ti375c529/Makefile
@@ -1,7 +1,8 @@
 SHELL := /bin/bash
 .SHELLFLAGS := -euo pipefail -c
 .ONESHELL:
-.NOTPARALLEL: detect interface map bitstream program-fpga program-flash-loader
+.NOTPARALLEL: detect interface map map-locked bitstream bitstream-locked \
+	program-fpga program-flash-loader
 
 FPGA_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
 REPO_DIR := $(abspath $(FPGA_DIR)/../../..)
@@ -15,6 +16,7 @@ DEBUG_DIR := $(FPGA_DIR)/flow/debug
 TOOL_SCRIPT_DIR := $(FPGA_DIR)/tools
 OUT_DIR := $(FPGA_DIR)/out
 LOG_DIR := $(OUT_DIR)/logs
+BUILD_LOCK ?= $(OUT_DIR)/.bitstream.lock
 
 include $(REPO_DIR)/tools/project.mk
 
@@ -87,7 +89,7 @@ GDB_LOAD_SCRIPT ?= $(DEBUG_DIR)/gdb_load_and_run.gdb
 GDB_ATTACH_SCRIPT ?= $(DEBUG_DIR)/gdb_attach.gdb
 
 .PHONY: help all fpga-config efinity-build-check efinity-program-check \
-	detect software chisel rtl soc interface map bitstream \
+	detect software chisel rtl soc interface map map-locked bitstream bitstream-locked \
 	program-fpga debug-openocd debug-load debug-gdb uart-listen \
 	flash-image flash-regions program-flash program-flash-elf \
 	program-flash-bitstream program-flash-regions program-flash-all \
@@ -121,8 +123,8 @@ all: bitstream
 efinity-build-check:
 	@if [[ -z "$(strip $(EFINITY_HOME))" ]]; then
 	  echo "Efinity installation not found." >&2
-	  echo "Install Efinity 2025.2, then set EFINITY_HOME=/path/to/efinity/2025.2." >&2
-	  echo "Searched /tools/efinix/efinity, /opt, \$$HOME, and tools/local/efinity." >&2
+	  echo "Install Efinity, then set EFINITY_HOME=/path/to/efinity/<version>." >&2
+	  echo "Searched /tools/efinix, /tools/Efinix, /opt, \$$HOME, and tools/local/efinity." >&2
 	  exit 1
 	fi
 	for required in "$(EFINITY_SETUP)" "$(EFX_RUN)"; do
@@ -300,7 +302,18 @@ interface: efinity-build-check $(INTERFACE_SCRIPT)
 	python3 "$(EFX_RUN)" "$(PROJECT_XML)" --flow interface --un_flow \
 	  --pt_opts "peri_scripts=$(INTERFACE_SCRIPT)" 2>&1 | tee "$(LOG_DIR)/interface.log"
 
-map: efinity-build-check rtl interface
+map: efinity-build-check
+	@mkdir -p "$(dir $(BUILD_LOCK))"
+	set +e
+	flock -E 75 -n "$(BUILD_LOCK)" $(MAKE) -C "$(FPGA_DIR)" map-locked
+	status=$$?
+	set -e
+	if [[ $$status -eq 75 ]]; then
+	  echo "Another Ti375 bitstream/map build is already running." >&2
+	fi
+	exit $$status
+
+map-locked: rtl interface
 	@mkdir -p "$(LOG_DIR)"
 	cd "$(FLOW_DIR)"
 	set +u
@@ -311,7 +324,18 @@ map: efinity-build-check rtl interface
 	set -u
 	python3 "$(EFX_RUN)" "$(PROJECT_XML)" --flow map 2>&1 | tee "$(LOG_DIR)/map.log"
 
-bitstream: efinity-build-check rtl interface
+bitstream: efinity-build-check
+	@mkdir -p "$(dir $(BUILD_LOCK))"
+	set +e
+	flock -E 75 -n "$(BUILD_LOCK)" $(MAKE) -C "$(FPGA_DIR)" bitstream-locked
+	status=$$?
+	set -e
+	if [[ $$status -eq 75 ]]; then
+	  echo "Another Ti375 bitstream/map build is already running." >&2
+	fi
+	exit $$status
+
+bitstream-locked: rtl interface
 	@mkdir -p "$(LOG_DIR)" "$(dir $(BIT_FILE))"
 	cd "$(FLOW_DIR)"
 	set +u
diff --git a/targets/fpga/ti375c529/README.md b/targets/fpga/ti375c529/README.md
index 5cb3789..f4da862 100644
--- a/targets/fpga/ti375c529/README.md
+++ b/targets/fpga/ti375c529/README.md
@@ -17,18 +17,20 @@ make FPGA_BOARD=ti375c529 fpga-program
 ```
 
 The Makefile auto-discovers versioned Efinity installations under
-`/tools/efinix/efinity`, `/opt`, the current user's home directory, and
-`tools/local/efinity`. Override discovery when required:
+`/tools/efinix/efinity`, `/tools/Efinix/efinity`, `/opt`, the current user's
+home directory, and `tools/local/efinity`. Override discovery when required:
 
 ```bash
 make FPGA_BOARD=ti375c529 fpga-bitstream \
-  EFINITY_HOME=/path/to/efinity/2025.2
+  EFINITY_HOME=/path/to/efinity/<version>
 ```
 
 `fpga-rtl` does not require Efinity. The `interface`, `bitstream`, and
 programming targets require a complete Efinity installation containing
 `bin/setup.sh` and `scripts/efx_run.py`; they now stop before hardware
 elaboration with a direct diagnostic when it is absent.
+Concurrent Ti375 `map` or `bitstream` invocations are rejected because they
+share generated FIRRTL, SystemVerilog, and Efinity work directories.
 
 Programming auto-selects the connected Ti375 development kit. If more than
 one compatible FTDI device is attached, run `make FPGA_BOARD=ti375c529
diff --git a/tools/project.mk b/tools/project.mk
index 99c9c54..f50c286 100644
--- a/tools/project.mk
+++ b/tools/project.mk
@@ -18,6 +18,7 @@ CIRCT_LIB_DIR ?= $(patsubst %/bin/firtool,%/lib,$(FIRTOOL))
 VIVADO ?= $(lastword $(sort $(wildcard /tools/Xilinx/*/Vivado/bin/vivado) $(shell command -v vivado 2>/dev/null)))
 _EFINITY_SETUP_CANDIDATES := $(sort \
   $(wildcard /tools/efinix/efinity/*/bin/setup.sh) \
+  $(wildcard /tools/Efinix/efinity/*/bin/setup.sh) \
   $(wildcard /opt/efinix/efinity/*/bin/setup.sh) \
   $(wildcard /opt/efinity/bin/setup.sh) \
   $(wildcard /opt/efinity/*/bin/setup.sh) \