feat(fpga): add Ti375 Efinity flow

Makefile

@@ -19,7 +19,7 @@ help:
 	  '  make doctor          # check local JDK/Mill/CIRCT and RISC-V tools' \
 	  '  make soc-hw          # emit shared SoC FIRRTL through FPGA config' \
 	  '  make fpga-rtl        # emit selected FPGA SystemVerilog and wrapper' \
-	  '  make fpga-bitstream  # run selected FPGA Vivado bitstream flow' \
+	  '  make fpga-bitstream  # run selected board vendor bitstream flow' \
 	  '  make fpga-elf-flash-image' \
 	  '                       # build APP ELF and board flash-format app image' \
 	  '  make fpga-mcs        # generate combined bitstream + app MCS/BIN' \
@@ -39,7 +39,7 @@ help:
 	  '  make asic-sim        # run ASIC-style Questa sanity simulation' \
 	  '' \
 	  'Config:' \
-	  '  FPGA_BOARD=$(FPGA_BOARD)  # vcu118 or genesys2' \
+	  '  FPGA_BOARD=$(FPGA_BOARD)  # vcu118, genesys2, or ti375c529' \
 	  '  UART_BAUD=460800          # FPGA firmware and host listener default' \
 	  '  GPS_ESKF_ENABLE=1         # gps_system: 1 ESKF, 0 GPS-only' \
 	  '  IMU_SENSOR=auto           # gps_system: auto, tdk, st or stm' \
@@ -49,6 +49,7 @@ help:
 	  '  make -C hardware/soc help' \
 	  '  make -C targets/fpga/vcu118 help' \
 	  '  make -C targets/fpga/genesys2 help' \
+	  '  make -C targets/fpga/ti375c529 help' \
 	  '  make -C targets/asic/rocket help'
 
 doctor: