feat(fpga): add Ti375 Efinity flow

hardware/fpga/ti375c529/rtl/Makefile

@@ -0,0 +1,18 @@
+.PHONY: help all shell generated clean
+
+help:
+	@echo "Ti375C529 RTL targets:"
+	@echo "  make shell      # list hand-written FPGA shell RTL"
+	@echo "  make generated  # generate Rocket SystemVerilog and Efinix wrapper"
+	@echo "  make clean      # remove generated wrapper/verilog"
+
+all: generated
+
+shell:
+	@find . -type f -name '*.sv' -print | sort
+
+generated:
+	@$(MAKE) -C ../../../../targets/fpga/ti375c529 rtl
+
+clean:
+	rm -rf ../../../generated/ti375c529-soc-verilog ../../../../targets/fpga/ti375c529/out/build/generated