diff --git a/targets/fpga/ti375c529/Makefile b/targets/fpga/ti375c529/Makefile
index 82cfc56..d70966f 100644
--- a/targets/fpga/ti375c529/Makefile
+++ b/targets/fpga/ti375c529/Makefile
@@ -299,7 +299,7 @@ interface: efinity-build-check $(INTERFACE_SCRIPT)
 	  exit 1
 	fi
 	set -u
-	python3 "$(EFX_RUN)" "$(PROJECT_XML)" --flow interface --un_flow \
+	python3 -u "$(EFX_RUN)" "$(PROJECT_XML)" --flow interface --un_flow \
 	  --pt_opts "peri_scripts=$(INTERFACE_SCRIPT)" 2>&1 | tee "$(LOG_DIR)/interface.log"
 
 map: efinity-build-check
@@ -322,7 +322,7 @@ map-locked: rtl interface
 	  exit 1
 	fi
 	set -u
-	python3 "$(EFX_RUN)" "$(PROJECT_XML)" --flow map 2>&1 | tee "$(LOG_DIR)/map.log"
+	python3 -u "$(EFX_RUN)" "$(PROJECT_XML)" --flow map 2>&1 | tee "$(LOG_DIR)/map.log"
 
 bitstream: efinity-build-check
 	@mkdir -p "$(dir $(BUILD_LOCK))"
@@ -345,9 +345,9 @@ bitstream-locked: rtl interface
 	fi
 	set -u
 	: > "$(LOG_DIR)/full.log"
-	python3 "$(EFX_RUN)" "$(PROJECT_XML)" --flow map 2>&1 | tee -a "$(LOG_DIR)/full.log"
-	python3 "$(EFX_RUN)" "$(PROJECT_XML)" --flow pnr --work_dir work_pnr 2>&1 | tee -a "$(LOG_DIR)/full.log"
-	python3 "$(EFX_RUN)" "$(PROJECT_XML)" --flow pgm --work_dir work_pnr 2>&1 | tee -a "$(LOG_DIR)/full.log"
+	python3 -u "$(EFX_RUN)" "$(PROJECT_XML)" --flow map 2>&1 | tee -a "$(LOG_DIR)/full.log"
+	python3 -u "$(EFX_RUN)" "$(PROJECT_XML)" --flow pnr --work_dir work_pnr 2>&1 | tee -a "$(LOG_DIR)/full.log"
+	python3 -u "$(EFX_RUN)" "$(PROJECT_XML)" --flow pgm --work_dir work_pnr 2>&1 | tee -a "$(LOG_DIR)/full.log"
 	generated_bit="$$(find "$(FLOW_DIR)/outflow" "$(OUT_DIR)" -type f -name 'ti375c529_rocket.bit' 2>/dev/null | head -n 1)"
 	if [[ -z "$$generated_bit" ]]; then
 	  echo "Efinity completed without a discoverable ti375c529_rocket.bit" >&2
diff --git a/targets/fpga/ti375c529/README.md b/targets/fpga/ti375c529/README.md
index f4da862..29938ad 100644
--- a/targets/fpga/ti375c529/README.md
+++ b/targets/fpga/ti375c529/README.md
@@ -31,6 +31,8 @@ programming targets require a complete Efinity installation containing
 elaboration with a direct diagnostic when it is absent.
 Concurrent Ti375 `map` or `bitstream` invocations are rejected because they
 share generated FIRRTL, SystemVerilog, and Efinity work directories.
+Efinity is run with unbuffered Python output so `map`, `pnr`, and `pgm`
+progress remains visible in the terminal and `out/logs/full.log`.
 
 Programming auto-selects the connected Ti375 development kit. If more than
 one compatible FTDI device is attached, run `make FPGA_BOARD=ti375c529