diff --git a/.Xil/Vivado-198675-onur/.lpr b/.Xil/Vivado-198675-onur/.lpr
deleted file mode 100644
index 04ef66e..0000000
--- a/.Xil/Vivado-198675-onur/.lpr
+++ /dev/null
@@ -1,7 +0,0 @@
-
-
-
-
-
-
-
diff --git a/.Xil/Vivado-198675-onur/elab.rtd b/.Xil/Vivado-198675-onur/elab.rtd
deleted file mode 100644
index 116ec17..0000000
Binary files a/.Xil/Vivado-198675-onur/elab.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/equivDumpFile.info b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/equivDumpFile.info
deleted file mode 100644
index 5f2df82..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/equivDumpFile.info
+++ /dev/null
@@ -1,5 +0,0 @@
-/u_rocket/VCU118RocketSystem__GC0#79:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#0
-/u_rocket/VCU118RocketSystem__GC0#80:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#1
-/u_rocket/VCU118RocketSystem__GC0#293:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#405
-/u_rocket/VCU118RocketSystem__GC0#291:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#403
-/u_rocket/VCU118RocketSystem__GC0#292:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#404
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1220760385.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1220760385.rtd
deleted file mode 100644
index 2348936..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index 86ffb16..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1294509424.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1294509424.rtd
deleted file mode 100644
index d61c610..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index c83f544..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/136113302.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/136113302.rtd
deleted file mode 100644
index 2776e57..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd
deleted file mode 100644
index 1f62b25..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1672436263.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1672436263.rtd
deleted file mode 100644
index e6e136d..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index e5ce9b4..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2438764479.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2438764479.rtd
deleted file mode 100644
index e9eacaa..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2438764479.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd
deleted file mode 100644
index 9c73b4b..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2610937407.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2610937407.rtd
deleted file mode 100644
index 254d9e1..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index 398bafa..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2737226844.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2737226844.rtd
deleted file mode 100644
index 43ca13a..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index d039fbc..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2962621930.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2962621930.rtd
deleted file mode 100644
index 40b8f1a..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index 5eb0629..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3482045580.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3482045580.rtd
deleted file mode 100644
index a47eceb..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index 10951ce..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3990655999.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3990655999.rtd
deleted file mode 100644
index 5042e09..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3990655999.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd
deleted file mode 100644
index 74b3cd2..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/976197094.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/976197094.rtd
deleted file mode 100644
index 1520f95..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd
deleted file mode 100644
index fc83633..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/global_name.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/global_name.straps.rtd
deleted file mode 100644
index 67b0314..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/instToEncGenName.map b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/instToEncGenName.map
deleted file mode 100644
index ffd5092..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/g/instToEncGenName.map
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0:2438764479
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
-/genesys2_rocket_top__GC0:3990655999
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/genomeDependencyGraph.out b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/genomeDependencyGraph.out
deleted file mode 100644
index f100a16..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/genomeDependencyGraph.out
+++ /dev/null
@@ -1,50 +0,0 @@
-GENOME NON_GENOME PIN 406: GENOME NON_GENOME PIN 0
-GENOME NON_GENOME PIN 0: GENOME NON_GENOME PIN 406
-GENOME NON_GENOME PIN 407: GENOME NON_GENOME PIN 1
-GENOME NON_GENOME PIN 1: GENOME NON_GENOME PIN 407
-GENOME NON_GENOME PIN 805: GENOME NON_GENOME PIN 403
-GENOME NON_GENOME PIN 403: GENOME NON_GENOME PIN 805
-GENOME NON_GENOME PIN 806: GENOME NON_GENOME PIN 404
-GENOME NON_GENOME PIN 404: GENOME NON_GENOME PIN 806
-GENOME NON_GENOME PIN 807: GENOME NON_GENOME PIN 405
-GENOME NON_GENOME PIN 405: GENOME NON_GENOME PIN 807
-INST TLToAPB PIN 119: INST VCU118RocketSystem__GC0 PIN 83 TYPE 5
-INST TLToAPB PIN 120: INST VCU118RocketSystem__GC0 PIN 84 TYPE 5
-INST TLToAPB PIN 121: INST VCU118RocketSystem__GC0 PIN 85 TYPE 5
-INST TLToAPB PIN 122: INST VCU118RocketSystem__GC0 PIN 86 TYPE 5
-INST TLToAPB PIN 123: INST VCU118RocketSystem__GC0 PIN 87 TYPE 5
-INST TLToAPB PIN 162: INST VCU118RocketSystem__GC0 PIN 126 TYPE 5
-INST TLToAPB PIN 163: INST VCU118RocketSystem__GC0 PIN 127 TYPE 5
-INST TLToAPB PIN 164: INST VCU118RocketSystem__GC0 PIN 128 TYPE 5
-INST TLToAPB PIN 165: INST VCU118RocketSystem__GC0 PIN 129 TYPE 5
-INST TLToAPB PIN 166: INST VCU118RocketSystem__GC0 PIN 130 TYPE 5
-INST TLToAPB PIN 167: INST VCU118RocketSystem__GC0 PIN 131 TYPE 5
-INST TLToAPB PIN 168: INST VCU118RocketSystem__GC0 PIN 132 TYPE 5
-INST TLToAPB PIN 169: INST VCU118RocketSystem__GC0 PIN 133 TYPE 5
-INST TLToAPB PIN 170: INST VCU118RocketSystem__GC0 PIN 134 TYPE 5
-INST TLToAPB PIN 171: INST VCU118RocketSystem__GC0 PIN 135 TYPE 5
-INST TLToAPB PIN 172: INST VCU118RocketSystem__GC0 PIN 136 TYPE 5
-INST TLToAPB PIN 205: INST VCU118RocketSystem__GC0 PIN 169 TYPE 5
-INST TilePRCIDomain__GC0 PIN 728: INST VCU118RocketSystem__GC0 PIN 289 TYPE 5
-INST TilePRCIDomain__GC0 PIN 808: INST RocketTile__GCB0 PIN 74 TYPE 5
-INST VCU118RocketSystem__GC0 PIN 79: INST TilePRCIDomain__GC0 PIN 0 TYPE 3 INST FPU__GB0 PIN 301 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST DCache PIN 338 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 80: INST TilePRCIDomain__GC0 PIN 1 TYPE 3 INST FPU__GB1 PIN 323 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST DCache PIN 339 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 293: INST TilePRCIDomain__GC0 PIN 405 TYPE 3 INST RocketTile__GCB0 PIN 1114 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 291: INST TilePRCIDomain__GC0 PIN 403 TYPE 3 INST RocketTile__GCB0 PIN 1115 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 292: INST TilePRCIDomain__GC0 PIN 404 TYPE 3 INST RocketTile__GCB0 PIN 1116 TYPE 4
-INST TLToAPB PIN 2: INST VCU118RocketSystem__GC0 PIN 489 TYPE 0 GENOME TLToAPB PIN 2
-INST TLToAPB PIN 3: INST VCU118RocketSystem__GC0 PIN 490 TYPE 0 GENOME TLToAPB PIN 3
-INST TLToAPB PIN 5: INST VCU118RocketSystem__GC0 PIN 492 TYPE 0 GENOME TLToAPB PIN 5
-INST TLToAPB PIN 6: INST VCU118RocketSystem__GC0 PIN 493 TYPE 0 GENOME TLToAPB PIN 6
-INST TLToAPB PIN 16: INST VCU118RocketSystem__GC0 PIN 503 TYPE 0 GENOME TLToAPB PIN 16
-INST TilePRCIDomain__GC0 PIN 218: INST VCU118RocketSystem__GC0 PIN 550 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 218
-INST TilePRCIDomain__GC0 PIN 219: INST VCU118RocketSystem__GC0 PIN 551 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 219
-INST TilePRCIDomain__GC0 PIN 284: INST VCU118RocketSystem__GC0 PIN 616 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 284
-INST TilePRCIDomain__GC0 PIN 0: GENOME TilePRCIDomain__GC0 PIN 0
-INST TilePRCIDomain__GC0 PIN 1: GENOME TilePRCIDomain__GC0 PIN 1
-INST TilePRCIDomain__GC0 PIN 403: GENOME TilePRCIDomain__GC0 PIN 403
-INST TilePRCIDomain__GC0 PIN 404: GENOME TilePRCIDomain__GC0 PIN 404
-INST TilePRCIDomain__GC0 PIN 405: GENOME TilePRCIDomain__GC0 PIN 405
-INST TilePRCIDomain__GC0 PIN 805: INST VCU118RocketSystem__GC0 PIN 291 TYPE 5
-INST TilePRCIDomain__GC0 PIN 806: INST VCU118RocketSystem__GC0 PIN 292 TYPE 5
-INST TilePRCIDomain__GC0 PIN 807: INST VCU118RocketSystem__GC0 PIN 293 TYPE 5
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/genomes.map b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/genomes.map
deleted file mode 100644
index 0315b46..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/genomes.map
+++ /dev/null
@@ -1,11 +0,0 @@
-FPU__GB0 5DAD0A60
-FPU__GB1 5F9D5100
-FPU__GB2 30286540
-RocketTile__GCB0 70535300
-DCache 319F2560
-TilePRCIDomain__GC0 3467DF00
-tracking_wrapper 3147BB20
-APBGpsBlock__GC0 6072B480
-TLToAPB 7048B120
-VCU118RocketSystem__GC0 4BC09200
-genesys2_rocket_top__GC0 316D2180
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2ECDAC80.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2ECDAC80.rtd
deleted file mode 100644
index 4298d82..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2ECDAC80.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2ECDB620.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2ECDB620.rtd
deleted file mode 100644
index 14b09bd..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2ECDB620.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2F5B08C0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2F5B08C0.rtd
deleted file mode 100644
index f12a871..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2F5B08C0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2F8EB1C0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2F8EB1C0.rtd
deleted file mode 100644
index 021259e..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/2F8EB1C0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/3159FDC0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/3159FDC0.rtd
deleted file mode 100644
index b338047..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/3159FDC0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/462CC640.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/462CC640.rtd
deleted file mode 100644
index ee5fb25..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/462CC640.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/46327200.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/46327200.rtd
deleted file mode 100644
index 3a37be3..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/46327200.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/46408120.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/46408120.rtd
deleted file mode 100644
index f3051ce..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/46408120.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/56B868A0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/56B868A0.rtd
deleted file mode 100644
index 74c2898..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/56B868A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/57156320.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/57156320.rtd
deleted file mode 100644
index a8c8978..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/57156320.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/611E74A0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/611E74A0.rtd
deleted file mode 100644
index 445a363..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/611E74A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/design.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/design.rtd
deleted file mode 100644
index 781b567..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/files.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/files.rtd
deleted file mode 100644
index 19449f9..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/files.rtd
+++ /dev/null
@@ -1,13 +0,0 @@
-design.rtd
-straps.rtd
-2ECDAC80.rtd
-2ECDB620.rtd
-2F5B08C0.rtd
-3159FDC0.rtd
-611E74A0.rtd
-57156320.rtd
-56B868A0.rtd
-46327200.rtd
-462CC640.rtd
-46408120.rtd
-2F8EB1C0.rtd
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/straps.rtd
deleted file mode 100644
index 0875ded..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/uniqInferGenToOrigInferGen.map b/.Xil/Vivado-198675-onur/incrSyn/1309558296/a/uniqInferGenToOrigInferGen.map
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/genomeDependencyGraph.out b/.Xil/Vivado-198675-onur/incrSyn/1309558296/genomeDependencyGraph.out
deleted file mode 100644
index c100635..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/genomeDependencyGraph.out
+++ /dev/null
@@ -1,899 +0,0 @@
-GENOME NON_GENOME PIN 406: GENOME NON_GENOME PIN 0
-GENOME NON_GENOME PIN 0: GENOME NON_GENOME PIN 406
-GENOME NON_GENOME PIN 407: GENOME NON_GENOME PIN 1
-GENOME NON_GENOME PIN 1: GENOME NON_GENOME PIN 407
-GENOME NON_GENOME PIN 805: GENOME NON_GENOME PIN 403 GENOME NON_GENOME PIN 867
-GENOME NON_GENOME PIN 403: GENOME NON_GENOME PIN 805 GENOME NON_GENOME PIN 465
-GENOME NON_GENOME PIN 806: GENOME NON_GENOME PIN 404 GENOME NON_GENOME PIN 744
-GENOME NON_GENOME PIN 404: GENOME NON_GENOME PIN 806
-GENOME NON_GENOME PIN 807: GENOME NON_GENOME PIN 405
-GENOME NON_GENOME PIN 405: GENOME NON_GENOME PIN 807
-INST TLToAPB PIN 119: INST VCU118RocketSystem__GC0 PIN 83 TYPE 5
-INST TLToAPB PIN 120: INST VCU118RocketSystem__GC0 PIN 84 TYPE 5
-INST TLToAPB PIN 121: INST VCU118RocketSystem__GC0 PIN 85 TYPE 5
-INST TLToAPB PIN 122: INST VCU118RocketSystem__GC0 PIN 86 TYPE 5
-INST TLToAPB PIN 123: INST VCU118RocketSystem__GC0 PIN 87 TYPE 5
-INST TLToAPB PIN 162: INST VCU118RocketSystem__GC0 PIN 126 TYPE 5
-INST TLToAPB PIN 163: INST VCU118RocketSystem__GC0 PIN 127 TYPE 5
-INST TLToAPB PIN 164: INST VCU118RocketSystem__GC0 PIN 128 TYPE 5
-INST TLToAPB PIN 165: INST VCU118RocketSystem__GC0 PIN 129 TYPE 5
-INST TLToAPB PIN 166: INST VCU118RocketSystem__GC0 PIN 130 TYPE 5
-INST TLToAPB PIN 167: INST VCU118RocketSystem__GC0 PIN 131 TYPE 5
-INST TLToAPB PIN 168: INST VCU118RocketSystem__GC0 PIN 132 TYPE 5
-INST TLToAPB PIN 169: INST VCU118RocketSystem__GC0 PIN 133 TYPE 5
-INST TLToAPB PIN 170: INST VCU118RocketSystem__GC0 PIN 134 TYPE 5
-INST TLToAPB PIN 171: INST VCU118RocketSystem__GC0 PIN 135 TYPE 5
-INST TLToAPB PIN 172: INST VCU118RocketSystem__GC0 PIN 136 TYPE 5
-INST TLToAPB PIN 205: INST VCU118RocketSystem__GC0 PIN 169 TYPE 5
-INST TilePRCIDomain__GC0 PIN 728: INST VCU118RocketSystem__GC0 PIN 289 TYPE 5
-INST TilePRCIDomain__GC0 PIN 808: INST RocketTile__GCB0 PIN 74 TYPE 5
-INST VCU118RocketSystem__GC0 PIN 79: INST TilePRCIDomain__GC0 PIN 0 TYPE 3 INST FPU__GB0 PIN 301 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST DCache PIN 338 TYPE 4 GENOME VCU118RocketSystem__GC0 PIN 79
-INST VCU118RocketSystem__GC0 PIN 80: INST TilePRCIDomain__GC0 PIN 1 TYPE 3 INST FPU__GB1 PIN 323 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST DCache PIN 339 TYPE 4 GENOME VCU118RocketSystem__GC0 PIN 80
-INST VCU118RocketSystem__GC0 PIN 293: INST TilePRCIDomain__GC0 PIN 405 TYPE 3 INST RocketTile__GCB0 PIN 1114 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 291: INST TilePRCIDomain__GC0 PIN 403 TYPE 3 INST RocketTile__GCB0 PIN 1115 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 292: INST TilePRCIDomain__GC0 PIN 404 TYPE 3 INST RocketTile__GCB0 PIN 1116 TYPE 4
-INST TLToAPB PIN 2: INST VCU118RocketSystem__GC0 PIN 489 TYPE 0 GENOME TLToAPB PIN 2
-INST TLToAPB PIN 3: INST VCU118RocketSystem__GC0 PIN 490 TYPE 0 GENOME TLToAPB PIN 3
-INST TLToAPB PIN 5: INST VCU118RocketSystem__GC0 PIN 492 TYPE 0 GENOME TLToAPB PIN 5
-INST TLToAPB PIN 6: INST VCU118RocketSystem__GC0 PIN 493 TYPE 0 GENOME TLToAPB PIN 6
-INST TLToAPB PIN 16: INST VCU118RocketSystem__GC0 PIN 503 TYPE 0 GENOME TLToAPB PIN 16
-INST TilePRCIDomain__GC0 PIN 218: INST VCU118RocketSystem__GC0 PIN 550 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 218
-INST TilePRCIDomain__GC0 PIN 219: INST VCU118RocketSystem__GC0 PIN 551 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 219
-INST TilePRCIDomain__GC0 PIN 284: INST VCU118RocketSystem__GC0 PIN 616 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 284
-INST TilePRCIDomain__GC0 PIN 0: GENOME TilePRCIDomain__GC0 PIN 0
-INST TilePRCIDomain__GC0 PIN 1: GENOME TilePRCIDomain__GC0 PIN 1
-INST TilePRCIDomain__GC0 PIN 403: GENOME TilePRCIDomain__GC0 PIN 403
-INST TilePRCIDomain__GC0 PIN 404: GENOME TilePRCIDomain__GC0 PIN 404
-INST TilePRCIDomain__GC0 PIN 405: GENOME TilePRCIDomain__GC0 PIN 405
-INST TilePRCIDomain__GC0 PIN 805: INST VCU118RocketSystem__GC0 PIN 291 TYPE 5
-INST TilePRCIDomain__GC0 PIN 806: INST VCU118RocketSystem__GC0 PIN 292 TYPE 5
-INST TilePRCIDomain__GC0 PIN 807: INST VCU118RocketSystem__GC0 PIN 293 TYPE 5
-INST genesys2_rocket_top__GC0 PIN 78: INST NON_GENOME PIN 33 TYPE 5
-INST genesys2_rocket_top__GC0 PIN 79: INST NON_GENOME PIN 34 TYPE 5
-INST genesys2_rocket_top__GC0 PIN 6: INST genesys2_rocket_top__GC0 PIN 12 TYPE 2 INST NON_GENOME PIN 10 TYPE 4
-INST genesys2_rocket_top__GC0 PIN 63: INST NON_GENOME PIN 102 TYPE 1 GENOME genesys2_rocket_top__GC0 PIN 63
-INST APBGpsBlock__GC0 PIN 110: INST TLToAPB PIN 52 TYPE 5
-INST APBGpsBlock__GC0 PIN 112: INST TLToAPB PIN 83 TYPE 5
-INST APBGpsBlock__GC0 PIN 113: INST TLToAPB PIN 84 TYPE 5
-INST APBGpsBlock__GC0 PIN 114: INST TLToAPB PIN 85 TYPE 5
-INST APBGpsBlock__GC0 PIN 115: INST TLToAPB PIN 86 TYPE 5
-INST APBGpsBlock__GC0 PIN 116: INST TLToAPB PIN 87 TYPE 5
-INST APBGpsBlock__GC0 PIN 117: INST TLToAPB PIN 88 TYPE 5
-INST APBGpsBlock__GC0 PIN 118: INST TLToAPB PIN 89 TYPE 5
-INST APBGpsBlock__GC0 PIN 119: INST TLToAPB PIN 90 TYPE 5
-INST APBGpsBlock__GC0 PIN 120: INST TLToAPB PIN 91 TYPE 5
-INST APBGpsBlock__GC0 PIN 121: INST TLToAPB PIN 92 TYPE 5
-INST APBGpsBlock__GC0 PIN 122: INST TLToAPB PIN 93 TYPE 5
-INST APBGpsBlock__GC0 PIN 123: INST TLToAPB PIN 94 TYPE 5
-INST APBGpsBlock__GC0 PIN 124: INST TLToAPB PIN 95 TYPE 5
-INST APBGpsBlock__GC0 PIN 125: INST TLToAPB PIN 96 TYPE 5
-INST APBGpsBlock__GC0 PIN 126: INST TLToAPB PIN 97 TYPE 5
-INST APBGpsBlock__GC0 PIN 127: INST TLToAPB PIN 98 TYPE 5
-INST APBGpsBlock__GC0 PIN 128: INST TLToAPB PIN 99 TYPE 5
-INST APBGpsBlock__GC0 PIN 129: INST TLToAPB PIN 100 TYPE 5
-INST APBGpsBlock__GC0 PIN 130: INST TLToAPB PIN 101 TYPE 5
-INST APBGpsBlock__GC0 PIN 131: INST TLToAPB PIN 102 TYPE 5
-INST APBGpsBlock__GC0 PIN 132: INST TLToAPB PIN 103 TYPE 5
-INST APBGpsBlock__GC0 PIN 133: INST TLToAPB PIN 104 TYPE 5
-INST APBGpsBlock__GC0 PIN 134: INST TLToAPB PIN 105 TYPE 5
-INST APBGpsBlock__GC0 PIN 135: INST TLToAPB PIN 106 TYPE 5
-INST APBGpsBlock__GC0 PIN 136: INST TLToAPB PIN 107 TYPE 5
-INST APBGpsBlock__GC0 PIN 137: INST TLToAPB PIN 108 TYPE 5
-INST APBGpsBlock__GC0 PIN 138: INST TLToAPB PIN 109 TYPE 5
-INST NON_GENOME PIN 51: INST VCU118RocketSystem__GC0 PIN 171 TYPE 3 INST tracking_wrapper PIN 35 TYPE 4 INST APBGpsBlock__GC0 PIN 80 TYPE 4 INST TLToAPB PIN 115 TYPE 4
-INST NON_GENOME PIN 52: INST VCU118RocketSystem__GC0 PIN 172 TYPE 3 INST APBGpsBlock__GC0 PIN 151 TYPE 4 INST TLToAPB PIN 116 TYPE 4
-INST tracking_wrapper PIN 50: INST TLToAPB PIN 52 TYPE 5
-INST NON_GENOME PIN 55: INST VCU118RocketSystem__GC0 PIN 79 TYPE 3 INST DCache PIN 338 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB0 PIN 301 TYPE 4 INST TilePRCIDomain__GC0 PIN 406 TYPE 4
-INST NON_GENOME PIN 56: INST VCU118RocketSystem__GC0 PIN 80 TYPE 3 INST DCache PIN 339 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST FPU__GB1 PIN 323 TYPE 4 INST TilePRCIDomain__GC0 PIN 407 TYPE 4
-INST RocketTile__GCB0 PIN 1244: INST TilePRCIDomain__GC0 PIN 7 TYPE 5
-INST RocketTile__GCB0 PIN 1245: INST TilePRCIDomain__GC0 PIN 8 TYPE 5
-INST RocketTile__GCB0 PIN 1251: INST TilePRCIDomain__GC0 PIN 14 TYPE 5
-INST RocketTile__GCB0 PIN 1650: INST DCache PIN 336 TYPE 5
-INST RocketTile__GCB0 PIN 1651: INST DCache PIN 337 TYPE 5
-INST DCache PIN 342: INST RocketTile__GCB0 PIN 2 TYPE 5
-INST DCache PIN 349: INST RocketTile__GCB0 PIN 9 TYPE 5
-INST TilePRCIDomain__GC0 PIN 5: INST RocketTile__GCB0 PIN 3 TYPE 3 INST DCache PIN 343 TYPE 4
-INST TilePRCIDomain__GC0 PIN 6: INST RocketTile__GCB0 PIN 4 TYPE 3 INST DCache PIN 344 TYPE 4
-INST TilePRCIDomain__GC0 PIN 9: INST RocketTile__GCB0 PIN 5 TYPE 3 INST DCache PIN 345 TYPE 4
-INST TilePRCIDomain__GC0 PIN 10: INST RocketTile__GCB0 PIN 6 TYPE 3 INST DCache PIN 346 TYPE 4
-INST TilePRCIDomain__GC0 PIN 11: INST RocketTile__GCB0 PIN 7 TYPE 3 INST DCache PIN 347 TYPE 4
-INST TilePRCIDomain__GC0 PIN 12: INST RocketTile__GCB0 PIN 8 TYPE 3 INST DCache PIN 348 TYPE 4
-INST TilePRCIDomain__GC0 PIN 16: INST RocketTile__GCB0 PIN 10 TYPE 3 INST DCache PIN 350 TYPE 4
-INST TilePRCIDomain__GC0 PIN 17: INST RocketTile__GCB0 PIN 11 TYPE 3 INST DCache PIN 351 TYPE 4
-INST TilePRCIDomain__GC0 PIN 18: INST RocketTile__GCB0 PIN 12 TYPE 3 INST DCache PIN 352 TYPE 4
-INST TilePRCIDomain__GC0 PIN 19: INST RocketTile__GCB0 PIN 13 TYPE 3 INST DCache PIN 353 TYPE 4
-INST TilePRCIDomain__GC0 PIN 20: INST RocketTile__GCB0 PIN 14 TYPE 3 INST DCache PIN 354 TYPE 4
-INST TilePRCIDomain__GC0 PIN 21: INST RocketTile__GCB0 PIN 15 TYPE 3 INST DCache PIN 355 TYPE 4
-INST TilePRCIDomain__GC0 PIN 22: INST RocketTile__GCB0 PIN 16 TYPE 3 INST DCache PIN 356 TYPE 4
-INST TilePRCIDomain__GC0 PIN 23: INST RocketTile__GCB0 PIN 17 TYPE 3 INST DCache PIN 357 TYPE 4
-INST TilePRCIDomain__GC0 PIN 24: INST RocketTile__GCB0 PIN 18 TYPE 3 INST DCache PIN 358 TYPE 4
-INST TilePRCIDomain__GC0 PIN 25: INST RocketTile__GCB0 PIN 19 TYPE 3 INST DCache PIN 359 TYPE 4
-INST TilePRCIDomain__GC0 PIN 26: INST RocketTile__GCB0 PIN 20 TYPE 3 INST DCache PIN 360 TYPE 4
-INST TilePRCIDomain__GC0 PIN 27: INST RocketTile__GCB0 PIN 21 TYPE 3 INST DCache PIN 361 TYPE 4
-INST TilePRCIDomain__GC0 PIN 28: INST RocketTile__GCB0 PIN 22 TYPE 3 INST DCache PIN 362 TYPE 4
-INST TilePRCIDomain__GC0 PIN 29: INST RocketTile__GCB0 PIN 23 TYPE 3 INST DCache PIN 363 TYPE 4
-INST TilePRCIDomain__GC0 PIN 30: INST RocketTile__GCB0 PIN 24 TYPE 3 INST DCache PIN 364 TYPE 4
-INST TilePRCIDomain__GC0 PIN 31: INST RocketTile__GCB0 PIN 25 TYPE 3 INST DCache PIN 365 TYPE 4
-INST TilePRCIDomain__GC0 PIN 32: INST RocketTile__GCB0 PIN 26 TYPE 3 INST DCache PIN 366 TYPE 4
-INST TilePRCIDomain__GC0 PIN 33: INST RocketTile__GCB0 PIN 27 TYPE 3 INST DCache PIN 367 TYPE 4
-INST TilePRCIDomain__GC0 PIN 34: INST RocketTile__GCB0 PIN 28 TYPE 3 INST DCache PIN 368 TYPE 4
-INST TilePRCIDomain__GC0 PIN 35: INST RocketTile__GCB0 PIN 29 TYPE 3 INST DCache PIN 369 TYPE 4
-INST TilePRCIDomain__GC0 PIN 36: INST RocketTile__GCB0 PIN 30 TYPE 3 INST DCache PIN 370 TYPE 4
-INST TilePRCIDomain__GC0 PIN 37: INST RocketTile__GCB0 PIN 31 TYPE 3 INST DCache PIN 371 TYPE 4
-INST TilePRCIDomain__GC0 PIN 38: INST RocketTile__GCB0 PIN 32 TYPE 3 INST DCache PIN 372 TYPE 4
-INST TilePRCIDomain__GC0 PIN 39: INST RocketTile__GCB0 PIN 33 TYPE 3 INST DCache PIN 373 TYPE 4
-INST TilePRCIDomain__GC0 PIN 40: INST RocketTile__GCB0 PIN 34 TYPE 3 INST DCache PIN 374 TYPE 4
-INST TilePRCIDomain__GC0 PIN 41: INST RocketTile__GCB0 PIN 35 TYPE 3 INST DCache PIN 375 TYPE 4
-INST TilePRCIDomain__GC0 PIN 42: INST RocketTile__GCB0 PIN 36 TYPE 3 INST DCache PIN 376 TYPE 4
-INST TilePRCIDomain__GC0 PIN 43: INST RocketTile__GCB0 PIN 37 TYPE 3 INST DCache PIN 377 TYPE 4
-INST TilePRCIDomain__GC0 PIN 44: INST RocketTile__GCB0 PIN 38 TYPE 3 INST DCache PIN 378 TYPE 4
-INST TilePRCIDomain__GC0 PIN 45: INST RocketTile__GCB0 PIN 39 TYPE 3 INST DCache PIN 379 TYPE 4
-INST TilePRCIDomain__GC0 PIN 46: INST RocketTile__GCB0 PIN 40 TYPE 3 INST DCache PIN 380 TYPE 4
-INST TilePRCIDomain__GC0 PIN 47: INST RocketTile__GCB0 PIN 41 TYPE 3 INST DCache PIN 381 TYPE 4
-INST TilePRCIDomain__GC0 PIN 48: INST RocketTile__GCB0 PIN 42 TYPE 3 INST DCache PIN 382 TYPE 4
-INST TilePRCIDomain__GC0 PIN 49: INST RocketTile__GCB0 PIN 43 TYPE 3 INST DCache PIN 383 TYPE 4
-INST TilePRCIDomain__GC0 PIN 50: INST RocketTile__GCB0 PIN 44 TYPE 3 INST DCache PIN 384 TYPE 4
-INST TilePRCIDomain__GC0 PIN 51: INST RocketTile__GCB0 PIN 45 TYPE 3 INST DCache PIN 385 TYPE 4
-INST TilePRCIDomain__GC0 PIN 52: INST RocketTile__GCB0 PIN 46 TYPE 3 INST DCache PIN 386 TYPE 4
-INST TilePRCIDomain__GC0 PIN 53: INST RocketTile__GCB0 PIN 47 TYPE 3 INST DCache PIN 387 TYPE 4
-INST TilePRCIDomain__GC0 PIN 54: INST RocketTile__GCB0 PIN 48 TYPE 3 INST DCache PIN 388 TYPE 4
-INST TilePRCIDomain__GC0 PIN 55: INST RocketTile__GCB0 PIN 49 TYPE 3 INST DCache PIN 389 TYPE 4
-INST TilePRCIDomain__GC0 PIN 56: INST RocketTile__GCB0 PIN 50 TYPE 3 INST DCache PIN 390 TYPE 4
-INST TilePRCIDomain__GC0 PIN 57: INST RocketTile__GCB0 PIN 51 TYPE 3 INST DCache PIN 391 TYPE 4
-INST TilePRCIDomain__GC0 PIN 58: INST RocketTile__GCB0 PIN 52 TYPE 3 INST DCache PIN 392 TYPE 4
-INST TilePRCIDomain__GC0 PIN 59: INST RocketTile__GCB0 PIN 53 TYPE 3 INST DCache PIN 393 TYPE 4
-INST TilePRCIDomain__GC0 PIN 60: INST RocketTile__GCB0 PIN 54 TYPE 3 INST DCache PIN 394 TYPE 4
-INST TilePRCIDomain__GC0 PIN 61: INST RocketTile__GCB0 PIN 55 TYPE 3 INST DCache PIN 395 TYPE 4
-INST TilePRCIDomain__GC0 PIN 62: INST RocketTile__GCB0 PIN 56 TYPE 3 INST DCache PIN 396 TYPE 4
-INST TilePRCIDomain__GC0 PIN 63: INST RocketTile__GCB0 PIN 57 TYPE 3 INST DCache PIN 397 TYPE 4
-INST TilePRCIDomain__GC0 PIN 64: INST RocketTile__GCB0 PIN 58 TYPE 3 INST DCache PIN 398 TYPE 4
-INST TilePRCIDomain__GC0 PIN 65: INST RocketTile__GCB0 PIN 59 TYPE 3 INST DCache PIN 399 TYPE 4
-INST TilePRCIDomain__GC0 PIN 66: INST RocketTile__GCB0 PIN 60 TYPE 3 INST DCache PIN 400 TYPE 4
-INST TilePRCIDomain__GC0 PIN 67: INST RocketTile__GCB0 PIN 61 TYPE 3 INST DCache PIN 401 TYPE 4
-INST TilePRCIDomain__GC0 PIN 68: INST RocketTile__GCB0 PIN 62 TYPE 3 INST DCache PIN 402 TYPE 4
-INST TilePRCIDomain__GC0 PIN 69: INST RocketTile__GCB0 PIN 63 TYPE 3 INST DCache PIN 403 TYPE 4
-INST TilePRCIDomain__GC0 PIN 70: INST RocketTile__GCB0 PIN 64 TYPE 3 INST DCache PIN 404 TYPE 4
-INST TilePRCIDomain__GC0 PIN 71: INST RocketTile__GCB0 PIN 65 TYPE 3 INST DCache PIN 405 TYPE 4
-INST TilePRCIDomain__GC0 PIN 72: INST RocketTile__GCB0 PIN 66 TYPE 3 INST DCache PIN 406 TYPE 4
-INST TilePRCIDomain__GC0 PIN 73: INST RocketTile__GCB0 PIN 67 TYPE 3 INST DCache PIN 407 TYPE 4
-INST TilePRCIDomain__GC0 PIN 74: INST RocketTile__GCB0 PIN 68 TYPE 3 INST DCache PIN 408 TYPE 4
-INST TilePRCIDomain__GC0 PIN 75: INST RocketTile__GCB0 PIN 69 TYPE 3 INST DCache PIN 409 TYPE 4
-INST TilePRCIDomain__GC0 PIN 76: INST RocketTile__GCB0 PIN 70 TYPE 3 INST DCache PIN 410 TYPE 4
-INST TilePRCIDomain__GC0 PIN 77: INST RocketTile__GCB0 PIN 71 TYPE 3 INST DCache PIN 411 TYPE 4
-INST TilePRCIDomain__GC0 PIN 78: INST RocketTile__GCB0 PIN 72 TYPE 3 INST DCache PIN 412 TYPE 4
-INST TilePRCIDomain__GC0 PIN 79: INST RocketTile__GCB0 PIN 73 TYPE 3 INST DCache PIN 413 TYPE 4
-INST RocketTile__GCB0 PIN 324: INST RocketTile__GCB0 PIN 325 TYPE 2 INST DCache PIN 465 TYPE 4
-INST RocketTile__GCB0 PIN 315: INST RocketTile__GCB0 PIN 326 TYPE 2 INST DCache PIN 466 TYPE 4
-INST RocketTile__GCB0 PIN 403: INST RocketTile__GCB0 PIN 465 TYPE 2 INST DCache PIN 605 TYPE 4
-INST RocketTile__GCB0 PIN 466: INST DCache PIN 606 TYPE 1 GENOME RocketTile__GCB0 PIN 466
-INST RocketTile__GCB0 PIN 467: INST DCache PIN 607 TYPE 1 GENOME RocketTile__GCB0 PIN 467
-INST RocketTile__GCB0 PIN 470: INST RocketTile__GCB0 PIN 532 TYPE 2 INST DCache PIN 672 TYPE 4
-INST RocketTile__GCB0 PIN 533: INST DCache PIN 673 TYPE 1 GENOME RocketTile__GCB0 PIN 533
-INST RocketTile__GCB0 PIN 534: INST DCache PIN 674 TYPE 1 GENOME RocketTile__GCB0 PIN 534
-INST RocketTile__GCB0 PIN 537: INST RocketTile__GCB0 PIN 599 TYPE 2 INST DCache PIN 739 TYPE 4
-INST RocketTile__GCB0 PIN 600: INST DCache PIN 740 TYPE 1 GENOME RocketTile__GCB0 PIN 600
-INST RocketTile__GCB0 PIN 601: INST DCache PIN 741 TYPE 1 GENOME RocketTile__GCB0 PIN 601
-INST RocketTile__GCB0 PIN 604: INST RocketTile__GCB0 PIN 666 TYPE 2 INST DCache PIN 806 TYPE 4
-INST RocketTile__GCB0 PIN 667: INST DCache PIN 807 TYPE 1 GENOME RocketTile__GCB0 PIN 667
-INST RocketTile__GCB0 PIN 668: INST DCache PIN 808 TYPE 1 GENOME RocketTile__GCB0 PIN 668
-INST RocketTile__GCB0 PIN 671: INST RocketTile__GCB0 PIN 733 TYPE 2 INST DCache PIN 873 TYPE 4
-INST RocketTile__GCB0 PIN 734: INST DCache PIN 874 TYPE 1 GENOME RocketTile__GCB0 PIN 734
-INST RocketTile__GCB0 PIN 735: INST DCache PIN 875 TYPE 1 GENOME RocketTile__GCB0 PIN 735
-INST RocketTile__GCB0 PIN 738: INST RocketTile__GCB0 PIN 800 TYPE 2 INST DCache PIN 940 TYPE 4
-INST RocketTile__GCB0 PIN 801: INST DCache PIN 941 TYPE 1 GENOME RocketTile__GCB0 PIN 801
-INST RocketTile__GCB0 PIN 802: INST DCache PIN 942 TYPE 1 GENOME RocketTile__GCB0 PIN 802
-INST RocketTile__GCB0 PIN 805: INST RocketTile__GCB0 PIN 867 TYPE 2 INST DCache PIN 1007 TYPE 4
-INST RocketTile__GCB0 PIN 868: INST DCache PIN 1008 TYPE 1 GENOME RocketTile__GCB0 PIN 868
-INST RocketTile__GCB0 PIN 869: INST DCache PIN 1009 TYPE 1 GENOME RocketTile__GCB0 PIN 869
-INST RocketTile__GCB0 PIN 872: INST RocketTile__GCB0 PIN 934 TYPE 2 INST DCache PIN 1074 TYPE 4
-INST RocketTile__GCB0 PIN 935: INST DCache PIN 1075 TYPE 1 GENOME RocketTile__GCB0 PIN 935
-INST RocketTile__GCB0 PIN 936: INST DCache PIN 1076 TYPE 1 GENOME RocketTile__GCB0 PIN 936
-INST DCache PIN 7: INST RocketTile__GCB0 PIN 1125 TYPE 0 GENOME DCache PIN 7
-INST DCache PIN 8: INST RocketTile__GCB0 PIN 1126 TYPE 0 GENOME DCache PIN 8
-INST DCache PIN 43: INST RocketTile__GCB0 PIN 1161 TYPE 0 GENOME DCache PIN 43
-INST DCache PIN 44: INST RocketTile__GCB0 PIN 1162 TYPE 0 GENOME DCache PIN 44
-INST DCache PIN 45: INST RocketTile__GCB0 PIN 1163 TYPE 0 GENOME DCache PIN 45
-INST DCache PIN 46: INST RocketTile__GCB0 PIN 1164 TYPE 0 GENOME DCache PIN 46
-INST DCache PIN 330: INST RocketTile__GCB0 PIN 1644 TYPE 0 GENOME DCache PIN 330
-INST DCache PIN 331: INST RocketTile__GCB0 PIN 1645 TYPE 0 GENOME DCache PIN 331
-INST FPU__GB2 PIN 317: INST FPU__GB1 PIN 162 TYPE 5
-INST FPU__GB2 PIN 323: INST FPU__GB1 PIN 137 TYPE 5
-INST FPU__GB2 PIN 393: INST FPU__GB1 PIN 1 TYPE 5
-INST FPU__GB2 PIN 171: INST FPU__GB1 PIN 525 TYPE 0 GENOME FPU__GB2 PIN 171
-INST FPU__GB2 PIN 172: INST FPU__GB1 PIN 526 TYPE 0 GENOME FPU__GB2 PIN 172
-INST FPU__GB2 PIN 173: INST FPU__GB1 PIN 527 TYPE 0 GENOME FPU__GB2 PIN 173
-INST FPU__GB2 PIN 174: INST FPU__GB1 PIN 528 TYPE 0 GENOME FPU__GB2 PIN 174
-INST FPU__GB2 PIN 306: INST FPU__GB1 PIN 531 TYPE 0 GENOME FPU__GB2 PIN 306
-INST FPU__GB2 PIN 307: INST FPU__GB1 PIN 532 TYPE 0 GENOME FPU__GB2 PIN 307
-INST FPU__GB2 PIN 308: INST FPU__GB1 PIN 533 TYPE 0 GENOME FPU__GB2 PIN 308
-INST DCache PIN 124: INST RocketTile__GCB0 PIN 1040 TYPE 3 INST FPU__GB1 PIN 641 TYPE 4
-INST DCache PIN 125: INST RocketTile__GCB0 PIN 1041 TYPE 3 INST FPU__GB1 PIN 642 TYPE 4
-INST DCache PIN 126: INST RocketTile__GCB0 PIN 1042 TYPE 3 INST FPU__GB1 PIN 643 TYPE 4
-INST DCache PIN 127: INST RocketTile__GCB0 PIN 1043 TYPE 3 INST FPU__GB1 PIN 644 TYPE 4
-INST DCache PIN 128: INST RocketTile__GCB0 PIN 1044 TYPE 3 INST FPU__GB1 PIN 645 TYPE 4
-INST DCache PIN 199: INST RocketTile__GCB0 PIN 1045 TYPE 3 INST FPU__GB1 PIN 646 TYPE 4
-INST DCache PIN 200: INST RocketTile__GCB0 PIN 1046 TYPE 3 INST FPU__GB1 PIN 647 TYPE 4
-INST DCache PIN 201: INST RocketTile__GCB0 PIN 1047 TYPE 3 INST FPU__GB1 PIN 648 TYPE 4
-INST DCache PIN 202: INST RocketTile__GCB0 PIN 1048 TYPE 3 INST FPU__GB1 PIN 649 TYPE 4
-INST DCache PIN 203: INST RocketTile__GCB0 PIN 1049 TYPE 3 INST FPU__GB1 PIN 650 TYPE 4
-INST DCache PIN 204: INST RocketTile__GCB0 PIN 1050 TYPE 3 INST FPU__GB1 PIN 651 TYPE 4
-INST DCache PIN 205: INST RocketTile__GCB0 PIN 1051 TYPE 3 INST FPU__GB1 PIN 652 TYPE 4
-INST DCache PIN 206: INST RocketTile__GCB0 PIN 1052 TYPE 3 INST FPU__GB1 PIN 653 TYPE 4
-INST DCache PIN 207: INST RocketTile__GCB0 PIN 1053 TYPE 3 INST FPU__GB1 PIN 654 TYPE 4
-INST DCache PIN 208: INST RocketTile__GCB0 PIN 1054 TYPE 3 INST FPU__GB1 PIN 655 TYPE 4
-INST DCache PIN 209: INST RocketTile__GCB0 PIN 1055 TYPE 3 INST FPU__GB1 PIN 656 TYPE 4
-INST DCache PIN 210: INST RocketTile__GCB0 PIN 1056 TYPE 3 INST FPU__GB1 PIN 657 TYPE 4
-INST DCache PIN 211: INST RocketTile__GCB0 PIN 1057 TYPE 3 INST FPU__GB1 PIN 658 TYPE 4
-INST DCache PIN 212: INST RocketTile__GCB0 PIN 1058 TYPE 3 INST FPU__GB1 PIN 659 TYPE 4
-INST DCache PIN 213: INST RocketTile__GCB0 PIN 1059 TYPE 3 INST FPU__GB1 PIN 660 TYPE 4
-INST DCache PIN 214: INST RocketTile__GCB0 PIN 1060 TYPE 3 INST FPU__GB1 PIN 661 TYPE 4
-INST DCache PIN 215: INST RocketTile__GCB0 PIN 1061 TYPE 3 INST FPU__GB1 PIN 662 TYPE 4
-INST DCache PIN 216: INST RocketTile__GCB0 PIN 1062 TYPE 3 INST FPU__GB1 PIN 663 TYPE 4
-INST DCache PIN 217: INST RocketTile__GCB0 PIN 1063 TYPE 3 INST FPU__GB1 PIN 664 TYPE 4
-INST DCache PIN 218: INST RocketTile__GCB0 PIN 1064 TYPE 3 INST FPU__GB1 PIN 665 TYPE 4
-INST DCache PIN 219: INST RocketTile__GCB0 PIN 1065 TYPE 3 INST FPU__GB1 PIN 666 TYPE 4
-INST DCache PIN 220: INST RocketTile__GCB0 PIN 1066 TYPE 3 INST FPU__GB1 PIN 667 TYPE 4
-INST DCache PIN 221: INST RocketTile__GCB0 PIN 1067 TYPE 3 INST FPU__GB1 PIN 668 TYPE 4
-INST DCache PIN 222: INST RocketTile__GCB0 PIN 1068 TYPE 3 INST FPU__GB1 PIN 669 TYPE 4
-INST DCache PIN 223: INST RocketTile__GCB0 PIN 1069 TYPE 3 INST FPU__GB1 PIN 670 TYPE 4
-INST DCache PIN 224: INST RocketTile__GCB0 PIN 1070 TYPE 3 INST FPU__GB1 PIN 671 TYPE 4
-INST DCache PIN 225: INST RocketTile__GCB0 PIN 1071 TYPE 3 INST FPU__GB1 PIN 672 TYPE 4
-INST DCache PIN 226: INST RocketTile__GCB0 PIN 1072 TYPE 3 INST FPU__GB1 PIN 673 TYPE 4
-INST DCache PIN 227: INST RocketTile__GCB0 PIN 1073 TYPE 3 INST FPU__GB1 PIN 674 TYPE 4
-INST DCache PIN 228: INST RocketTile__GCB0 PIN 1074 TYPE 3 INST FPU__GB1 PIN 675 TYPE 4
-INST DCache PIN 229: INST RocketTile__GCB0 PIN 1075 TYPE 3 INST FPU__GB1 PIN 676 TYPE 4
-INST DCache PIN 230: INST RocketTile__GCB0 PIN 1076 TYPE 3 INST FPU__GB1 PIN 677 TYPE 4
-INST DCache PIN 231: INST RocketTile__GCB0 PIN 1077 TYPE 3 INST FPU__GB1 PIN 678 TYPE 4
-INST DCache PIN 232: INST RocketTile__GCB0 PIN 1078 TYPE 3 INST FPU__GB1 PIN 679 TYPE 4
-INST DCache PIN 233: INST RocketTile__GCB0 PIN 1079 TYPE 3 INST FPU__GB1 PIN 680 TYPE 4
-INST DCache PIN 234: INST RocketTile__GCB0 PIN 1080 TYPE 3 INST FPU__GB1 PIN 681 TYPE 4
-INST DCache PIN 235: INST RocketTile__GCB0 PIN 1081 TYPE 3 INST FPU__GB1 PIN 682 TYPE 4
-INST DCache PIN 236: INST RocketTile__GCB0 PIN 1082 TYPE 3 INST FPU__GB1 PIN 683 TYPE 4
-INST DCache PIN 237: INST RocketTile__GCB0 PIN 1083 TYPE 3 INST FPU__GB1 PIN 684 TYPE 4
-INST DCache PIN 238: INST RocketTile__GCB0 PIN 1084 TYPE 3 INST FPU__GB1 PIN 685 TYPE 4
-INST DCache PIN 239: INST RocketTile__GCB0 PIN 1085 TYPE 3 INST FPU__GB1 PIN 686 TYPE 4
-INST DCache PIN 240: INST RocketTile__GCB0 PIN 1086 TYPE 3 INST FPU__GB1 PIN 687 TYPE 4
-INST DCache PIN 241: INST RocketTile__GCB0 PIN 1087 TYPE 3 INST FPU__GB1 PIN 688 TYPE 4
-INST DCache PIN 242: INST RocketTile__GCB0 PIN 1088 TYPE 3 INST FPU__GB1 PIN 689 TYPE 4
-INST DCache PIN 243: INST RocketTile__GCB0 PIN 1089 TYPE 3 INST FPU__GB1 PIN 690 TYPE 4
-INST DCache PIN 244: INST RocketTile__GCB0 PIN 1090 TYPE 3 INST FPU__GB1 PIN 691 TYPE 4
-INST DCache PIN 245: INST RocketTile__GCB0 PIN 1091 TYPE 3 INST FPU__GB1 PIN 692 TYPE 4
-INST DCache PIN 246: INST RocketTile__GCB0 PIN 1092 TYPE 3 INST FPU__GB1 PIN 693 TYPE 4
-INST DCache PIN 247: INST RocketTile__GCB0 PIN 1093 TYPE 3 INST FPU__GB1 PIN 694 TYPE 4
-INST DCache PIN 248: INST RocketTile__GCB0 PIN 1094 TYPE 3 INST FPU__GB1 PIN 695 TYPE 4
-INST DCache PIN 249: INST RocketTile__GCB0 PIN 1095 TYPE 3 INST FPU__GB1 PIN 696 TYPE 4
-INST DCache PIN 250: INST RocketTile__GCB0 PIN 1096 TYPE 3 INST FPU__GB1 PIN 697 TYPE 4
-INST DCache PIN 251: INST RocketTile__GCB0 PIN 1097 TYPE 3 INST FPU__GB1 PIN 698 TYPE 4
-INST DCache PIN 252: INST RocketTile__GCB0 PIN 1098 TYPE 3 INST FPU__GB1 PIN 699 TYPE 4
-INST DCache PIN 253: INST RocketTile__GCB0 PIN 1099 TYPE 3 INST FPU__GB1 PIN 700 TYPE 4
-INST DCache PIN 254: INST RocketTile__GCB0 PIN 1100 TYPE 3 INST FPU__GB1 PIN 701 TYPE 4
-INST DCache PIN 255: INST RocketTile__GCB0 PIN 1101 TYPE 3 INST FPU__GB1 PIN 702 TYPE 4
-INST DCache PIN 256: INST RocketTile__GCB0 PIN 1102 TYPE 3 INST FPU__GB1 PIN 703 TYPE 4
-INST DCache PIN 257: INST RocketTile__GCB0 PIN 1103 TYPE 3 INST FPU__GB1 PIN 704 TYPE 4
-INST DCache PIN 258: INST RocketTile__GCB0 PIN 1104 TYPE 3 INST FPU__GB1 PIN 705 TYPE 4
-INST DCache PIN 259: INST RocketTile__GCB0 PIN 1105 TYPE 3 INST FPU__GB1 PIN 706 TYPE 4
-INST DCache PIN 260: INST RocketTile__GCB0 PIN 1106 TYPE 3 INST FPU__GB1 PIN 707 TYPE 4
-INST DCache PIN 261: INST RocketTile__GCB0 PIN 1107 TYPE 3 INST FPU__GB1 PIN 708 TYPE 4
-INST DCache PIN 262: INST RocketTile__GCB0 PIN 1108 TYPE 3 INST FPU__GB1 PIN 709 TYPE 4
-INST DCache PIN 132: INST RocketTile__GCB0 PIN 1039 TYPE 3 INST FPU__GB1 PIN 710 TYPE 4
-INST RocketTile__GCB0 PIN 198: INST TilePRCIDomain__GC0 PIN 531 TYPE 0 GENOME RocketTile__GCB0 PIN 198
-INST RocketTile__GCB0 PIN 202: INST TilePRCIDomain__GC0 PIN 732 TYPE 0 GENOME RocketTile__GCB0 PIN 202
-INST RocketTile__GCB0 PIN 203: INST TilePRCIDomain__GC0 PIN 733 TYPE 0 GENOME RocketTile__GCB0 PIN 203
-INST VCU118RocketSystem__GC0 PIN 331: INST NON_GENOME PIN 34 TYPE 0 GENOME VCU118RocketSystem__GC0 PIN 331
-INST VCU118RocketSystem__GC0 PIN 334: INST VCU118RocketSystem__GC0 PIN 335 TYPE 2 INST NON_GENOME PIN 46 TYPE 4 INST VCU118RocketSystem__GC0 PIN 336 TYPE 2 INST NON_GENOME PIN 47 TYPE 4
-INST RocketTile__GCB0 PIN 2: GENOME RocketTile__GCB0 PIN 2
-INST RocketTile__GCB0 PIN 3: GENOME RocketTile__GCB0 PIN 3
-INST RocketTile__GCB0 PIN 4: GENOME RocketTile__GCB0 PIN 4
-INST RocketTile__GCB0 PIN 5: GENOME RocketTile__GCB0 PIN 5
-INST RocketTile__GCB0 PIN 6: GENOME RocketTile__GCB0 PIN 6
-INST RocketTile__GCB0 PIN 7: GENOME RocketTile__GCB0 PIN 7
-INST RocketTile__GCB0 PIN 8: GENOME RocketTile__GCB0 PIN 8
-INST RocketTile__GCB0 PIN 9: GENOME RocketTile__GCB0 PIN 9
-INST RocketTile__GCB0 PIN 10: GENOME RocketTile__GCB0 PIN 10
-INST RocketTile__GCB0 PIN 11: GENOME RocketTile__GCB0 PIN 11
-INST RocketTile__GCB0 PIN 12: GENOME RocketTile__GCB0 PIN 12
-INST RocketTile__GCB0 PIN 13: GENOME RocketTile__GCB0 PIN 13
-INST RocketTile__GCB0 PIN 14: GENOME RocketTile__GCB0 PIN 14
-INST RocketTile__GCB0 PIN 15: GENOME RocketTile__GCB0 PIN 15
-INST RocketTile__GCB0 PIN 16: GENOME RocketTile__GCB0 PIN 16
-INST RocketTile__GCB0 PIN 17: GENOME RocketTile__GCB0 PIN 17
-INST RocketTile__GCB0 PIN 18: GENOME RocketTile__GCB0 PIN 18
-INST RocketTile__GCB0 PIN 19: GENOME RocketTile__GCB0 PIN 19
-INST RocketTile__GCB0 PIN 20: GENOME RocketTile__GCB0 PIN 20
-INST RocketTile__GCB0 PIN 21: GENOME RocketTile__GCB0 PIN 21
-INST RocketTile__GCB0 PIN 22: GENOME RocketTile__GCB0 PIN 22
-INST RocketTile__GCB0 PIN 23: GENOME RocketTile__GCB0 PIN 23
-INST RocketTile__GCB0 PIN 24: GENOME RocketTile__GCB0 PIN 24
-INST RocketTile__GCB0 PIN 25: GENOME RocketTile__GCB0 PIN 25
-INST RocketTile__GCB0 PIN 26: GENOME RocketTile__GCB0 PIN 26
-INST RocketTile__GCB0 PIN 27: GENOME RocketTile__GCB0 PIN 27
-INST RocketTile__GCB0 PIN 28: GENOME RocketTile__GCB0 PIN 28
-INST RocketTile__GCB0 PIN 29: GENOME RocketTile__GCB0 PIN 29
-INST RocketTile__GCB0 PIN 30: GENOME RocketTile__GCB0 PIN 30
-INST RocketTile__GCB0 PIN 31: GENOME RocketTile__GCB0 PIN 31
-INST RocketTile__GCB0 PIN 32: GENOME RocketTile__GCB0 PIN 32
-INST RocketTile__GCB0 PIN 33: GENOME RocketTile__GCB0 PIN 33
-INST RocketTile__GCB0 PIN 34: GENOME RocketTile__GCB0 PIN 34
-INST RocketTile__GCB0 PIN 35: GENOME RocketTile__GCB0 PIN 35
-INST RocketTile__GCB0 PIN 36: GENOME RocketTile__GCB0 PIN 36
-INST RocketTile__GCB0 PIN 37: GENOME RocketTile__GCB0 PIN 37
-INST RocketTile__GCB0 PIN 38: GENOME RocketTile__GCB0 PIN 38
-INST RocketTile__GCB0 PIN 39: GENOME RocketTile__GCB0 PIN 39
-INST RocketTile__GCB0 PIN 40: GENOME RocketTile__GCB0 PIN 40
-INST RocketTile__GCB0 PIN 41: GENOME RocketTile__GCB0 PIN 41
-INST RocketTile__GCB0 PIN 42: GENOME RocketTile__GCB0 PIN 42
-INST RocketTile__GCB0 PIN 43: GENOME RocketTile__GCB0 PIN 43
-INST RocketTile__GCB0 PIN 44: GENOME RocketTile__GCB0 PIN 44
-INST RocketTile__GCB0 PIN 45: GENOME RocketTile__GCB0 PIN 45
-INST RocketTile__GCB0 PIN 46: GENOME RocketTile__GCB0 PIN 46
-INST RocketTile__GCB0 PIN 47: GENOME RocketTile__GCB0 PIN 47
-INST RocketTile__GCB0 PIN 48: GENOME RocketTile__GCB0 PIN 48
-INST RocketTile__GCB0 PIN 49: GENOME RocketTile__GCB0 PIN 49
-INST RocketTile__GCB0 PIN 50: GENOME RocketTile__GCB0 PIN 50
-INST RocketTile__GCB0 PIN 51: GENOME RocketTile__GCB0 PIN 51
-INST RocketTile__GCB0 PIN 52: GENOME RocketTile__GCB0 PIN 52
-INST RocketTile__GCB0 PIN 53: GENOME RocketTile__GCB0 PIN 53
-INST RocketTile__GCB0 PIN 54: GENOME RocketTile__GCB0 PIN 54
-INST RocketTile__GCB0 PIN 55: GENOME RocketTile__GCB0 PIN 55
-INST RocketTile__GCB0 PIN 56: GENOME RocketTile__GCB0 PIN 56
-INST RocketTile__GCB0 PIN 57: GENOME RocketTile__GCB0 PIN 57
-INST RocketTile__GCB0 PIN 58: GENOME RocketTile__GCB0 PIN 58
-INST RocketTile__GCB0 PIN 59: GENOME RocketTile__GCB0 PIN 59
-INST RocketTile__GCB0 PIN 60: GENOME RocketTile__GCB0 PIN 60
-INST RocketTile__GCB0 PIN 61: GENOME RocketTile__GCB0 PIN 61
-INST RocketTile__GCB0 PIN 62: GENOME RocketTile__GCB0 PIN 62
-INST RocketTile__GCB0 PIN 63: GENOME RocketTile__GCB0 PIN 63
-INST RocketTile__GCB0 PIN 64: GENOME RocketTile__GCB0 PIN 64
-INST RocketTile__GCB0 PIN 65: GENOME RocketTile__GCB0 PIN 65
-INST RocketTile__GCB0 PIN 66: GENOME RocketTile__GCB0 PIN 66
-INST RocketTile__GCB0 PIN 67: GENOME RocketTile__GCB0 PIN 67
-INST RocketTile__GCB0 PIN 68: GENOME RocketTile__GCB0 PIN 68
-INST RocketTile__GCB0 PIN 69: GENOME RocketTile__GCB0 PIN 69
-INST RocketTile__GCB0 PIN 70: GENOME RocketTile__GCB0 PIN 70
-INST RocketTile__GCB0 PIN 71: GENOME RocketTile__GCB0 PIN 71
-INST RocketTile__GCB0 PIN 72: GENOME RocketTile__GCB0 PIN 72
-INST RocketTile__GCB0 PIN 73: GENOME RocketTile__GCB0 PIN 73
-INST RocketTile__GCB0 PIN 74: GENOME RocketTile__GCB0 PIN 74
-INST RocketTile__GCB0 PIN 325: GENOME RocketTile__GCB0 PIN 325
-INST RocketTile__GCB0 PIN 326: GENOME RocketTile__GCB0 PIN 326
-INST RocketTile__GCB0 PIN 465: GENOME RocketTile__GCB0 PIN 465
-INST RocketTile__GCB0 PIN 532: GENOME RocketTile__GCB0 PIN 532
-INST RocketTile__GCB0 PIN 599: GENOME RocketTile__GCB0 PIN 599
-INST RocketTile__GCB0 PIN 666: GENOME RocketTile__GCB0 PIN 666
-INST RocketTile__GCB0 PIN 733: GENOME RocketTile__GCB0 PIN 733
-INST RocketTile__GCB0 PIN 800: GENOME RocketTile__GCB0 PIN 800
-INST RocketTile__GCB0 PIN 867: GENOME RocketTile__GCB0 PIN 867
-INST RocketTile__GCB0 PIN 934: GENOME RocketTile__GCB0 PIN 934
-INST RocketTile__GCB0 PIN 1037: GENOME RocketTile__GCB0 PIN 1037
-INST RocketTile__GCB0 PIN 1038: GENOME RocketTile__GCB0 PIN 1038
-INST RocketTile__GCB0 PIN 1039: GENOME RocketTile__GCB0 PIN 1039
-INST RocketTile__GCB0 PIN 1040: GENOME RocketTile__GCB0 PIN 1040
-INST RocketTile__GCB0 PIN 1041: GENOME RocketTile__GCB0 PIN 1041
-INST RocketTile__GCB0 PIN 1042: GENOME RocketTile__GCB0 PIN 1042
-INST RocketTile__GCB0 PIN 1043: GENOME RocketTile__GCB0 PIN 1043
-INST RocketTile__GCB0 PIN 1044: GENOME RocketTile__GCB0 PIN 1044
-INST RocketTile__GCB0 PIN 1045: GENOME RocketTile__GCB0 PIN 1045
-INST RocketTile__GCB0 PIN 1046: GENOME RocketTile__GCB0 PIN 1046
-INST RocketTile__GCB0 PIN 1047: GENOME RocketTile__GCB0 PIN 1047
-INST RocketTile__GCB0 PIN 1048: GENOME RocketTile__GCB0 PIN 1048
-INST RocketTile__GCB0 PIN 1049: GENOME RocketTile__GCB0 PIN 1049
-INST RocketTile__GCB0 PIN 1050: GENOME RocketTile__GCB0 PIN 1050
-INST RocketTile__GCB0 PIN 1051: GENOME RocketTile__GCB0 PIN 1051
-INST RocketTile__GCB0 PIN 1052: GENOME RocketTile__GCB0 PIN 1052
-INST RocketTile__GCB0 PIN 1053: GENOME RocketTile__GCB0 PIN 1053
-INST RocketTile__GCB0 PIN 1054: GENOME RocketTile__GCB0 PIN 1054
-INST RocketTile__GCB0 PIN 1055: GENOME RocketTile__GCB0 PIN 1055
-INST RocketTile__GCB0 PIN 1056: GENOME RocketTile__GCB0 PIN 1056
-INST RocketTile__GCB0 PIN 1057: GENOME RocketTile__GCB0 PIN 1057
-INST RocketTile__GCB0 PIN 1058: GENOME RocketTile__GCB0 PIN 1058
-INST RocketTile__GCB0 PIN 1059: GENOME RocketTile__GCB0 PIN 1059
-INST RocketTile__GCB0 PIN 1060: GENOME RocketTile__GCB0 PIN 1060
-INST RocketTile__GCB0 PIN 1061: GENOME RocketTile__GCB0 PIN 1061
-INST RocketTile__GCB0 PIN 1062: GENOME RocketTile__GCB0 PIN 1062
-INST RocketTile__GCB0 PIN 1063: GENOME RocketTile__GCB0 PIN 1063
-INST RocketTile__GCB0 PIN 1064: GENOME RocketTile__GCB0 PIN 1064
-INST RocketTile__GCB0 PIN 1065: GENOME RocketTile__GCB0 PIN 1065
-INST RocketTile__GCB0 PIN 1066: GENOME RocketTile__GCB0 PIN 1066
-INST RocketTile__GCB0 PIN 1067: GENOME RocketTile__GCB0 PIN 1067
-INST RocketTile__GCB0 PIN 1068: GENOME RocketTile__GCB0 PIN 1068
-INST RocketTile__GCB0 PIN 1069: GENOME RocketTile__GCB0 PIN 1069
-INST RocketTile__GCB0 PIN 1070: GENOME RocketTile__GCB0 PIN 1070
-INST RocketTile__GCB0 PIN 1071: GENOME RocketTile__GCB0 PIN 1071
-INST RocketTile__GCB0 PIN 1072: GENOME RocketTile__GCB0 PIN 1072
-INST RocketTile__GCB0 PIN 1073: GENOME RocketTile__GCB0 PIN 1073
-INST RocketTile__GCB0 PIN 1074: GENOME RocketTile__GCB0 PIN 1074
-INST RocketTile__GCB0 PIN 1075: GENOME RocketTile__GCB0 PIN 1075
-INST RocketTile__GCB0 PIN 1076: GENOME RocketTile__GCB0 PIN 1076
-INST RocketTile__GCB0 PIN 1077: GENOME RocketTile__GCB0 PIN 1077
-INST RocketTile__GCB0 PIN 1078: GENOME RocketTile__GCB0 PIN 1078
-INST RocketTile__GCB0 PIN 1079: GENOME RocketTile__GCB0 PIN 1079
-INST RocketTile__GCB0 PIN 1080: GENOME RocketTile__GCB0 PIN 1080
-INST RocketTile__GCB0 PIN 1081: GENOME RocketTile__GCB0 PIN 1081
-INST RocketTile__GCB0 PIN 1082: GENOME RocketTile__GCB0 PIN 1082
-INST RocketTile__GCB0 PIN 1083: GENOME RocketTile__GCB0 PIN 1083
-INST RocketTile__GCB0 PIN 1084: GENOME RocketTile__GCB0 PIN 1084
-INST RocketTile__GCB0 PIN 1085: GENOME RocketTile__GCB0 PIN 1085
-INST RocketTile__GCB0 PIN 1086: GENOME RocketTile__GCB0 PIN 1086
-INST RocketTile__GCB0 PIN 1087: GENOME RocketTile__GCB0 PIN 1087
-INST RocketTile__GCB0 PIN 1088: GENOME RocketTile__GCB0 PIN 1088
-INST RocketTile__GCB0 PIN 1089: GENOME RocketTile__GCB0 PIN 1089
-INST RocketTile__GCB0 PIN 1090: GENOME RocketTile__GCB0 PIN 1090
-INST RocketTile__GCB0 PIN 1091: GENOME RocketTile__GCB0 PIN 1091
-INST RocketTile__GCB0 PIN 1092: GENOME RocketTile__GCB0 PIN 1092
-INST RocketTile__GCB0 PIN 1093: GENOME RocketTile__GCB0 PIN 1093
-INST RocketTile__GCB0 PIN 1094: GENOME RocketTile__GCB0 PIN 1094
-INST RocketTile__GCB0 PIN 1095: GENOME RocketTile__GCB0 PIN 1095
-INST RocketTile__GCB0 PIN 1096: GENOME RocketTile__GCB0 PIN 1096
-INST RocketTile__GCB0 PIN 1097: GENOME RocketTile__GCB0 PIN 1097
-INST RocketTile__GCB0 PIN 1098: GENOME RocketTile__GCB0 PIN 1098
-INST RocketTile__GCB0 PIN 1099: GENOME RocketTile__GCB0 PIN 1099
-INST RocketTile__GCB0 PIN 1100: GENOME RocketTile__GCB0 PIN 1100
-INST RocketTile__GCB0 PIN 1101: GENOME RocketTile__GCB0 PIN 1101
-INST RocketTile__GCB0 PIN 1102: GENOME RocketTile__GCB0 PIN 1102
-INST RocketTile__GCB0 PIN 1103: GENOME RocketTile__GCB0 PIN 1103
-INST RocketTile__GCB0 PIN 1104: GENOME RocketTile__GCB0 PIN 1104
-INST RocketTile__GCB0 PIN 1105: GENOME RocketTile__GCB0 PIN 1105
-INST RocketTile__GCB0 PIN 1106: GENOME RocketTile__GCB0 PIN 1106
-INST RocketTile__GCB0 PIN 1107: GENOME RocketTile__GCB0 PIN 1107
-INST RocketTile__GCB0 PIN 1108: GENOME RocketTile__GCB0 PIN 1108
-INST RocketTile__GCB0 PIN 1125: GENOME RocketTile__GCB0 PIN 1125
-INST RocketTile__GCB0 PIN 1126: GENOME RocketTile__GCB0 PIN 1126
-INST RocketTile__GCB0 PIN 1161: GENOME RocketTile__GCB0 PIN 1161
-INST RocketTile__GCB0 PIN 1162: GENOME RocketTile__GCB0 PIN 1162
-INST RocketTile__GCB0 PIN 1163: GENOME RocketTile__GCB0 PIN 1163
-INST RocketTile__GCB0 PIN 1164: GENOME RocketTile__GCB0 PIN 1164
-INST RocketTile__GCB0 PIN 1644: GENOME RocketTile__GCB0 PIN 1644
-INST RocketTile__GCB0 PIN 1645: GENOME RocketTile__GCB0 PIN 1645
-GENOME NON_GENOME PIN 1241: GENOME NON_GENOME PIN 2
-GENOME NON_GENOME PIN 2: GENOME NON_GENOME PIN 1241
-GENOME NON_GENOME PIN 1242: GENOME NON_GENOME PIN 3
-GENOME NON_GENOME PIN 3: GENOME NON_GENOME PIN 1242
-GENOME NON_GENOME PIN 1243: GENOME NON_GENOME PIN 4
-GENOME NON_GENOME PIN 4: GENOME NON_GENOME PIN 1243
-GENOME NON_GENOME PIN 1246: GENOME NON_GENOME PIN 5
-GENOME NON_GENOME PIN 5: GENOME NON_GENOME PIN 1246
-GENOME NON_GENOME PIN 1247: GENOME NON_GENOME PIN 6
-GENOME NON_GENOME PIN 6: GENOME NON_GENOME PIN 1247 GENOME NON_GENOME PIN 12
-GENOME NON_GENOME PIN 1248: GENOME NON_GENOME PIN 7
-GENOME NON_GENOME PIN 7: GENOME NON_GENOME PIN 1248
-GENOME NON_GENOME PIN 1249: GENOME NON_GENOME PIN 8
-GENOME NON_GENOME PIN 8: GENOME NON_GENOME PIN 1249
-GENOME NON_GENOME PIN 1252: GENOME NON_GENOME PIN 9
-GENOME NON_GENOME PIN 9: GENOME NON_GENOME PIN 1252
-GENOME NON_GENOME PIN 1253: GENOME NON_GENOME PIN 10
-GENOME NON_GENOME PIN 10: GENOME NON_GENOME PIN 1253
-GENOME NON_GENOME PIN 1254: GENOME NON_GENOME PIN 11
-GENOME NON_GENOME PIN 11: GENOME NON_GENOME PIN 1254
-GENOME NON_GENOME PIN 1255: GENOME NON_GENOME PIN 12
-GENOME NON_GENOME PIN 12: GENOME NON_GENOME PIN 1255 GENOME NON_GENOME PIN 6
-GENOME NON_GENOME PIN 1256: GENOME NON_GENOME PIN 13
-GENOME NON_GENOME PIN 13: GENOME NON_GENOME PIN 1256
-GENOME NON_GENOME PIN 1257: GENOME NON_GENOME PIN 14
-GENOME NON_GENOME PIN 14: GENOME NON_GENOME PIN 1257
-GENOME NON_GENOME PIN 1258: GENOME NON_GENOME PIN 15
-GENOME NON_GENOME PIN 15: GENOME NON_GENOME PIN 1258
-GENOME NON_GENOME PIN 1259: GENOME NON_GENOME PIN 16
-GENOME NON_GENOME PIN 16: GENOME NON_GENOME PIN 1259
-GENOME NON_GENOME PIN 1260: GENOME NON_GENOME PIN 17
-GENOME NON_GENOME PIN 17: GENOME NON_GENOME PIN 1260
-GENOME NON_GENOME PIN 1261: GENOME NON_GENOME PIN 18
-GENOME NON_GENOME PIN 18: GENOME NON_GENOME PIN 1261
-GENOME NON_GENOME PIN 1262: GENOME NON_GENOME PIN 19
-GENOME NON_GENOME PIN 19: GENOME NON_GENOME PIN 1262
-GENOME NON_GENOME PIN 1263: GENOME NON_GENOME PIN 20
-GENOME NON_GENOME PIN 20: GENOME NON_GENOME PIN 1263
-GENOME NON_GENOME PIN 1264: GENOME NON_GENOME PIN 21
-GENOME NON_GENOME PIN 21: GENOME NON_GENOME PIN 1264
-GENOME NON_GENOME PIN 1265: GENOME NON_GENOME PIN 22
-GENOME NON_GENOME PIN 22: GENOME NON_GENOME PIN 1265
-GENOME NON_GENOME PIN 1266: GENOME NON_GENOME PIN 23
-GENOME NON_GENOME PIN 23: GENOME NON_GENOME PIN 1266
-GENOME NON_GENOME PIN 1267: GENOME NON_GENOME PIN 24
-GENOME NON_GENOME PIN 24: GENOME NON_GENOME PIN 1267
-GENOME NON_GENOME PIN 1268: GENOME NON_GENOME PIN 25
-GENOME NON_GENOME PIN 25: GENOME NON_GENOME PIN 1268
-GENOME NON_GENOME PIN 1269: GENOME NON_GENOME PIN 26
-GENOME NON_GENOME PIN 26: GENOME NON_GENOME PIN 1269
-GENOME NON_GENOME PIN 1270: GENOME NON_GENOME PIN 27
-GENOME NON_GENOME PIN 27: GENOME NON_GENOME PIN 1270
-GENOME NON_GENOME PIN 1271: GENOME NON_GENOME PIN 28
-GENOME NON_GENOME PIN 28: GENOME NON_GENOME PIN 1271
-GENOME NON_GENOME PIN 1272: GENOME NON_GENOME PIN 29
-GENOME NON_GENOME PIN 29: GENOME NON_GENOME PIN 1272
-GENOME NON_GENOME PIN 1273: GENOME NON_GENOME PIN 30
-GENOME NON_GENOME PIN 30: GENOME NON_GENOME PIN 1273
-GENOME NON_GENOME PIN 1274: GENOME NON_GENOME PIN 31
-GENOME NON_GENOME PIN 31: GENOME NON_GENOME PIN 1274
-GENOME NON_GENOME PIN 1275: GENOME NON_GENOME PIN 32
-GENOME NON_GENOME PIN 32: GENOME NON_GENOME PIN 1275
-GENOME NON_GENOME PIN 1276: GENOME NON_GENOME PIN 33
-GENOME NON_GENOME PIN 33: GENOME NON_GENOME PIN 1276
-GENOME NON_GENOME PIN 1277: GENOME NON_GENOME PIN 34
-GENOME NON_GENOME PIN 34: GENOME NON_GENOME PIN 1277
-GENOME NON_GENOME PIN 1278: GENOME NON_GENOME PIN 35
-GENOME NON_GENOME PIN 35: GENOME NON_GENOME PIN 1278
-GENOME NON_GENOME PIN 1279: GENOME NON_GENOME PIN 36
-GENOME NON_GENOME PIN 36: GENOME NON_GENOME PIN 1279
-GENOME NON_GENOME PIN 1280: GENOME NON_GENOME PIN 37
-GENOME NON_GENOME PIN 37: GENOME NON_GENOME PIN 1280
-GENOME NON_GENOME PIN 1281: GENOME NON_GENOME PIN 38
-GENOME NON_GENOME PIN 38: GENOME NON_GENOME PIN 1281
-GENOME NON_GENOME PIN 1282: GENOME NON_GENOME PIN 39
-GENOME NON_GENOME PIN 39: GENOME NON_GENOME PIN 1282
-GENOME NON_GENOME PIN 1283: GENOME NON_GENOME PIN 40
-GENOME NON_GENOME PIN 40: GENOME NON_GENOME PIN 1283
-GENOME NON_GENOME PIN 1284: GENOME NON_GENOME PIN 41
-GENOME NON_GENOME PIN 41: GENOME NON_GENOME PIN 1284
-GENOME NON_GENOME PIN 1285: GENOME NON_GENOME PIN 42
-GENOME NON_GENOME PIN 42: GENOME NON_GENOME PIN 1285
-GENOME NON_GENOME PIN 1286: GENOME NON_GENOME PIN 43
-GENOME NON_GENOME PIN 43: GENOME NON_GENOME PIN 1286
-GENOME NON_GENOME PIN 1287: GENOME NON_GENOME PIN 44
-GENOME NON_GENOME PIN 44: GENOME NON_GENOME PIN 1287
-GENOME NON_GENOME PIN 1288: GENOME NON_GENOME PIN 45
-GENOME NON_GENOME PIN 45: GENOME NON_GENOME PIN 1288
-GENOME NON_GENOME PIN 1289: GENOME NON_GENOME PIN 46
-GENOME NON_GENOME PIN 46: GENOME NON_GENOME PIN 1289
-GENOME NON_GENOME PIN 1290: GENOME NON_GENOME PIN 47
-GENOME NON_GENOME PIN 47: GENOME NON_GENOME PIN 1290
-GENOME NON_GENOME PIN 1291: GENOME NON_GENOME PIN 48
-GENOME NON_GENOME PIN 48: GENOME NON_GENOME PIN 1291
-GENOME NON_GENOME PIN 1292: GENOME NON_GENOME PIN 49
-GENOME NON_GENOME PIN 49: GENOME NON_GENOME PIN 1292
-GENOME NON_GENOME PIN 1293: GENOME NON_GENOME PIN 50
-GENOME NON_GENOME PIN 50: GENOME NON_GENOME PIN 1293
-GENOME NON_GENOME PIN 1294: GENOME NON_GENOME PIN 51
-GENOME NON_GENOME PIN 51: GENOME NON_GENOME PIN 1294
-GENOME NON_GENOME PIN 1295: GENOME NON_GENOME PIN 52
-GENOME NON_GENOME PIN 52: GENOME NON_GENOME PIN 1295
-GENOME NON_GENOME PIN 1296: GENOME NON_GENOME PIN 53
-GENOME NON_GENOME PIN 53: GENOME NON_GENOME PIN 1296
-GENOME NON_GENOME PIN 1297: GENOME NON_GENOME PIN 54
-GENOME NON_GENOME PIN 54: GENOME NON_GENOME PIN 1297
-GENOME NON_GENOME PIN 1298: GENOME NON_GENOME PIN 55
-GENOME NON_GENOME PIN 55: GENOME NON_GENOME PIN 1298
-GENOME NON_GENOME PIN 1299: GENOME NON_GENOME PIN 56
-GENOME NON_GENOME PIN 56: GENOME NON_GENOME PIN 1299
-GENOME NON_GENOME PIN 1300: GENOME NON_GENOME PIN 57
-GENOME NON_GENOME PIN 57: GENOME NON_GENOME PIN 1300
-GENOME NON_GENOME PIN 1301: GENOME NON_GENOME PIN 58
-GENOME NON_GENOME PIN 58: GENOME NON_GENOME PIN 1301
-GENOME NON_GENOME PIN 1302: GENOME NON_GENOME PIN 59
-GENOME NON_GENOME PIN 59: GENOME NON_GENOME PIN 1302
-GENOME NON_GENOME PIN 1303: GENOME NON_GENOME PIN 60
-GENOME NON_GENOME PIN 60: GENOME NON_GENOME PIN 1303
-GENOME NON_GENOME PIN 1304: GENOME NON_GENOME PIN 61
-GENOME NON_GENOME PIN 61: GENOME NON_GENOME PIN 1304
-GENOME NON_GENOME PIN 1305: GENOME NON_GENOME PIN 62
-GENOME NON_GENOME PIN 62: GENOME NON_GENOME PIN 1305
-GENOME NON_GENOME PIN 1306: GENOME NON_GENOME PIN 63
-GENOME NON_GENOME PIN 63: GENOME NON_GENOME PIN 1306
-GENOME NON_GENOME PIN 1307: GENOME NON_GENOME PIN 64
-GENOME NON_GENOME PIN 64: GENOME NON_GENOME PIN 1307
-GENOME NON_GENOME PIN 1308: GENOME NON_GENOME PIN 65
-GENOME NON_GENOME PIN 65: GENOME NON_GENOME PIN 1308
-GENOME NON_GENOME PIN 1309: GENOME NON_GENOME PIN 66
-GENOME NON_GENOME PIN 66: GENOME NON_GENOME PIN 1309
-GENOME NON_GENOME PIN 1310: GENOME NON_GENOME PIN 67
-GENOME NON_GENOME PIN 67: GENOME NON_GENOME PIN 1310
-GENOME NON_GENOME PIN 1311: GENOME NON_GENOME PIN 68
-GENOME NON_GENOME PIN 68: GENOME NON_GENOME PIN 1311
-GENOME NON_GENOME PIN 1312: GENOME NON_GENOME PIN 69
-GENOME NON_GENOME PIN 69: GENOME NON_GENOME PIN 1312
-GENOME NON_GENOME PIN 1313: GENOME NON_GENOME PIN 70
-GENOME NON_GENOME PIN 70: GENOME NON_GENOME PIN 1313
-GENOME NON_GENOME PIN 1314: GENOME NON_GENOME PIN 71
-GENOME NON_GENOME PIN 71: GENOME NON_GENOME PIN 1314
-GENOME NON_GENOME PIN 1315: GENOME NON_GENOME PIN 72
-GENOME NON_GENOME PIN 72: GENOME NON_GENOME PIN 1315
-GENOME NON_GENOME PIN 1316: GENOME NON_GENOME PIN 73
-GENOME NON_GENOME PIN 73: GENOME NON_GENOME PIN 1316
-GENOME NON_GENOME PIN 83: GENOME NON_GENOME PIN 119 GENOME NON_GENOME PIN 120
-GENOME NON_GENOME PIN 119: GENOME NON_GENOME PIN 83
-GENOME NON_GENOME PIN 120: GENOME NON_GENOME PIN 83
-GENOME NON_GENOME PIN 324: GENOME NON_GENOME PIN 315 GENOME NON_GENOME PIN 325
-GENOME NON_GENOME PIN 315: GENOME NON_GENOME PIN 324 GENOME NON_GENOME PIN 326
-GENOME NON_GENOME PIN 325: GENOME NON_GENOME PIN 324
-GENOME NON_GENOME PIN 326: GENOME NON_GENOME PIN 315
-GENOME NON_GENOME PIN 465: GENOME NON_GENOME PIN 403 GENOME NON_GENOME PIN 464
-GENOME NON_GENOME PIN 470: GENOME NON_GENOME PIN 532
-GENOME NON_GENOME PIN 532: GENOME NON_GENOME PIN 470
-GENOME NON_GENOME PIN 537: GENOME NON_GENOME PIN 599
-GENOME NON_GENOME PIN 599: GENOME NON_GENOME PIN 537
-GENOME NON_GENOME PIN 604: GENOME NON_GENOME PIN 666
-GENOME NON_GENOME PIN 666: GENOME NON_GENOME PIN 604
-GENOME NON_GENOME PIN 671: GENOME NON_GENOME PIN 733
-GENOME NON_GENOME PIN 733: GENOME NON_GENOME PIN 671
-GENOME NON_GENOME PIN 738: GENOME NON_GENOME PIN 800
-GENOME NON_GENOME PIN 800: GENOME NON_GENOME PIN 738
-GENOME NON_GENOME PIN 867: GENOME NON_GENOME PIN 805
-GENOME NON_GENOME PIN 872: GENOME NON_GENOME PIN 934
-GENOME NON_GENOME PIN 934: GENOME NON_GENOME PIN 872
-GENOME NON_GENOME PIN 1445: GENOME NON_GENOME PIN 1038
-GENOME NON_GENOME PIN 1038: GENOME NON_GENOME PIN 1445
-GENOME NON_GENOME PIN 1446: GENOME NON_GENOME PIN 1039
-GENOME NON_GENOME PIN 1039: GENOME NON_GENOME PIN 1446
-GENOME NON_GENOME PIN 1438: GENOME NON_GENOME PIN 1040
-GENOME NON_GENOME PIN 1040: GENOME NON_GENOME PIN 1438
-GENOME NON_GENOME PIN 1439: GENOME NON_GENOME PIN 1041
-GENOME NON_GENOME PIN 1041: GENOME NON_GENOME PIN 1439
-GENOME NON_GENOME PIN 1440: GENOME NON_GENOME PIN 1042
-GENOME NON_GENOME PIN 1042: GENOME NON_GENOME PIN 1440
-GENOME NON_GENOME PIN 1441: GENOME NON_GENOME PIN 1043
-GENOME NON_GENOME PIN 1043: GENOME NON_GENOME PIN 1441
-GENOME NON_GENOME PIN 1442: GENOME NON_GENOME PIN 1044
-GENOME NON_GENOME PIN 1044: GENOME NON_GENOME PIN 1442
-GENOME NON_GENOME PIN 1513: GENOME NON_GENOME PIN 1045
-GENOME NON_GENOME PIN 1045: GENOME NON_GENOME PIN 1513
-GENOME NON_GENOME PIN 1514: GENOME NON_GENOME PIN 1046
-GENOME NON_GENOME PIN 1046: GENOME NON_GENOME PIN 1514
-GENOME NON_GENOME PIN 1515: GENOME NON_GENOME PIN 1047
-GENOME NON_GENOME PIN 1047: GENOME NON_GENOME PIN 1515
-GENOME NON_GENOME PIN 1516: GENOME NON_GENOME PIN 1048
-GENOME NON_GENOME PIN 1048: GENOME NON_GENOME PIN 1516
-GENOME NON_GENOME PIN 1517: GENOME NON_GENOME PIN 1049
-GENOME NON_GENOME PIN 1049: GENOME NON_GENOME PIN 1517
-GENOME NON_GENOME PIN 1518: GENOME NON_GENOME PIN 1050
-GENOME NON_GENOME PIN 1050: GENOME NON_GENOME PIN 1518
-GENOME NON_GENOME PIN 1519: GENOME NON_GENOME PIN 1051
-GENOME NON_GENOME PIN 1051: GENOME NON_GENOME PIN 1519
-GENOME NON_GENOME PIN 1520: GENOME NON_GENOME PIN 1052
-GENOME NON_GENOME PIN 1052: GENOME NON_GENOME PIN 1520
-GENOME NON_GENOME PIN 1521: GENOME NON_GENOME PIN 1053
-GENOME NON_GENOME PIN 1053: GENOME NON_GENOME PIN 1521
-GENOME NON_GENOME PIN 1522: GENOME NON_GENOME PIN 1054
-GENOME NON_GENOME PIN 1054: GENOME NON_GENOME PIN 1522
-GENOME NON_GENOME PIN 1523: GENOME NON_GENOME PIN 1055
-GENOME NON_GENOME PIN 1055: GENOME NON_GENOME PIN 1523
-GENOME NON_GENOME PIN 1524: GENOME NON_GENOME PIN 1056
-GENOME NON_GENOME PIN 1056: GENOME NON_GENOME PIN 1524
-GENOME NON_GENOME PIN 1525: GENOME NON_GENOME PIN 1057
-GENOME NON_GENOME PIN 1057: GENOME NON_GENOME PIN 1525
-GENOME NON_GENOME PIN 1526: GENOME NON_GENOME PIN 1058
-GENOME NON_GENOME PIN 1058: GENOME NON_GENOME PIN 1526
-GENOME NON_GENOME PIN 1527: GENOME NON_GENOME PIN 1059
-GENOME NON_GENOME PIN 1059: GENOME NON_GENOME PIN 1527
-GENOME NON_GENOME PIN 1528: GENOME NON_GENOME PIN 1060
-GENOME NON_GENOME PIN 1060: GENOME NON_GENOME PIN 1528
-GENOME NON_GENOME PIN 1529: GENOME NON_GENOME PIN 1061
-GENOME NON_GENOME PIN 1061: GENOME NON_GENOME PIN 1529
-GENOME NON_GENOME PIN 1530: GENOME NON_GENOME PIN 1062
-GENOME NON_GENOME PIN 1062: GENOME NON_GENOME PIN 1530
-GENOME NON_GENOME PIN 1531: GENOME NON_GENOME PIN 1063
-GENOME NON_GENOME PIN 1063: GENOME NON_GENOME PIN 1531
-GENOME NON_GENOME PIN 1532: GENOME NON_GENOME PIN 1064
-GENOME NON_GENOME PIN 1064: GENOME NON_GENOME PIN 1532
-GENOME NON_GENOME PIN 1533: GENOME NON_GENOME PIN 1065
-GENOME NON_GENOME PIN 1065: GENOME NON_GENOME PIN 1533
-GENOME NON_GENOME PIN 1534: GENOME NON_GENOME PIN 1066
-GENOME NON_GENOME PIN 1066: GENOME NON_GENOME PIN 1534
-GENOME NON_GENOME PIN 1535: GENOME NON_GENOME PIN 1067
-GENOME NON_GENOME PIN 1067: GENOME NON_GENOME PIN 1535
-GENOME NON_GENOME PIN 1536: GENOME NON_GENOME PIN 1068
-GENOME NON_GENOME PIN 1068: GENOME NON_GENOME PIN 1536
-GENOME NON_GENOME PIN 1537: GENOME NON_GENOME PIN 1069
-GENOME NON_GENOME PIN 1069: GENOME NON_GENOME PIN 1537
-GENOME NON_GENOME PIN 1538: GENOME NON_GENOME PIN 1070
-GENOME NON_GENOME PIN 1070: GENOME NON_GENOME PIN 1538
-GENOME NON_GENOME PIN 1539: GENOME NON_GENOME PIN 1071
-GENOME NON_GENOME PIN 1071: GENOME NON_GENOME PIN 1539
-GENOME NON_GENOME PIN 1540: GENOME NON_GENOME PIN 1072
-GENOME NON_GENOME PIN 1072: GENOME NON_GENOME PIN 1540
-GENOME NON_GENOME PIN 1541: GENOME NON_GENOME PIN 1073
-GENOME NON_GENOME PIN 1073: GENOME NON_GENOME PIN 1541
-GENOME NON_GENOME PIN 1542: GENOME NON_GENOME PIN 1074
-GENOME NON_GENOME PIN 1074: GENOME NON_GENOME PIN 1542 GENOME NON_GENOME PIN 1012
-GENOME NON_GENOME PIN 1543: GENOME NON_GENOME PIN 1075
-GENOME NON_GENOME PIN 1075: GENOME NON_GENOME PIN 1543
-GENOME NON_GENOME PIN 1544: GENOME NON_GENOME PIN 1076
-GENOME NON_GENOME PIN 1076: GENOME NON_GENOME PIN 1544
-GENOME NON_GENOME PIN 1545: GENOME NON_GENOME PIN 1077
-GENOME NON_GENOME PIN 1077: GENOME NON_GENOME PIN 1545
-GENOME NON_GENOME PIN 1546: GENOME NON_GENOME PIN 1078
-GENOME NON_GENOME PIN 1078: GENOME NON_GENOME PIN 1546
-GENOME NON_GENOME PIN 1547: GENOME NON_GENOME PIN 1079
-GENOME NON_GENOME PIN 1079: GENOME NON_GENOME PIN 1547
-GENOME NON_GENOME PIN 1548: GENOME NON_GENOME PIN 1080
-GENOME NON_GENOME PIN 1080: GENOME NON_GENOME PIN 1548
-GENOME NON_GENOME PIN 1549: GENOME NON_GENOME PIN 1081
-GENOME NON_GENOME PIN 1081: GENOME NON_GENOME PIN 1549
-GENOME NON_GENOME PIN 1550: GENOME NON_GENOME PIN 1082
-GENOME NON_GENOME PIN 1082: GENOME NON_GENOME PIN 1550
-GENOME NON_GENOME PIN 1551: GENOME NON_GENOME PIN 1083
-GENOME NON_GENOME PIN 1083: GENOME NON_GENOME PIN 1551
-GENOME NON_GENOME PIN 1552: GENOME NON_GENOME PIN 1084
-GENOME NON_GENOME PIN 1084: GENOME NON_GENOME PIN 1552
-GENOME NON_GENOME PIN 1553: GENOME NON_GENOME PIN 1085
-GENOME NON_GENOME PIN 1085: GENOME NON_GENOME PIN 1553
-GENOME NON_GENOME PIN 1554: GENOME NON_GENOME PIN 1086
-GENOME NON_GENOME PIN 1086: GENOME NON_GENOME PIN 1554
-GENOME NON_GENOME PIN 1555: GENOME NON_GENOME PIN 1087
-GENOME NON_GENOME PIN 1087: GENOME NON_GENOME PIN 1555
-GENOME NON_GENOME PIN 1556: GENOME NON_GENOME PIN 1088
-GENOME NON_GENOME PIN 1088: GENOME NON_GENOME PIN 1556
-GENOME NON_GENOME PIN 1557: GENOME NON_GENOME PIN 1089
-GENOME NON_GENOME PIN 1089: GENOME NON_GENOME PIN 1557
-GENOME NON_GENOME PIN 1558: GENOME NON_GENOME PIN 1090
-GENOME NON_GENOME PIN 1090: GENOME NON_GENOME PIN 1558
-GENOME NON_GENOME PIN 1559: GENOME NON_GENOME PIN 1091
-GENOME NON_GENOME PIN 1091: GENOME NON_GENOME PIN 1559
-GENOME NON_GENOME PIN 1560: GENOME NON_GENOME PIN 1092
-GENOME NON_GENOME PIN 1092: GENOME NON_GENOME PIN 1560
-GENOME NON_GENOME PIN 1561: GENOME NON_GENOME PIN 1093
-GENOME NON_GENOME PIN 1093: GENOME NON_GENOME PIN 1561
-GENOME NON_GENOME PIN 1562: GENOME NON_GENOME PIN 1094
-GENOME NON_GENOME PIN 1094: GENOME NON_GENOME PIN 1562
-GENOME NON_GENOME PIN 1563: GENOME NON_GENOME PIN 1095
-GENOME NON_GENOME PIN 1095: GENOME NON_GENOME PIN 1563
-GENOME NON_GENOME PIN 1564: GENOME NON_GENOME PIN 1096
-GENOME NON_GENOME PIN 1096: GENOME NON_GENOME PIN 1564
-GENOME NON_GENOME PIN 1565: GENOME NON_GENOME PIN 1097
-GENOME NON_GENOME PIN 1097: GENOME NON_GENOME PIN 1565
-GENOME NON_GENOME PIN 1566: GENOME NON_GENOME PIN 1098
-GENOME NON_GENOME PIN 1098: GENOME NON_GENOME PIN 1566
-GENOME NON_GENOME PIN 1567: GENOME NON_GENOME PIN 1099
-GENOME NON_GENOME PIN 1099: GENOME NON_GENOME PIN 1567
-GENOME NON_GENOME PIN 1568: GENOME NON_GENOME PIN 1100
-GENOME NON_GENOME PIN 1100: GENOME NON_GENOME PIN 1568
-GENOME NON_GENOME PIN 1569: GENOME NON_GENOME PIN 1101
-GENOME NON_GENOME PIN 1101: GENOME NON_GENOME PIN 1569
-GENOME NON_GENOME PIN 1570: GENOME NON_GENOME PIN 1102
-GENOME NON_GENOME PIN 1102: GENOME NON_GENOME PIN 1570
-GENOME NON_GENOME PIN 1571: GENOME NON_GENOME PIN 1103
-GENOME NON_GENOME PIN 1103: GENOME NON_GENOME PIN 1571
-GENOME NON_GENOME PIN 1572: GENOME NON_GENOME PIN 1104
-GENOME NON_GENOME PIN 1104: GENOME NON_GENOME PIN 1572
-GENOME NON_GENOME PIN 1573: GENOME NON_GENOME PIN 1105
-GENOME NON_GENOME PIN 1105: GENOME NON_GENOME PIN 1573
-GENOME NON_GENOME PIN 1574: GENOME NON_GENOME PIN 1106
-GENOME NON_GENOME PIN 1106: GENOME NON_GENOME PIN 1574
-GENOME NON_GENOME PIN 1575: GENOME NON_GENOME PIN 1107
-GENOME NON_GENOME PIN 1107: GENOME NON_GENOME PIN 1575
-GENOME NON_GENOME PIN 1576: GENOME NON_GENOME PIN 1108
-GENOME NON_GENOME PIN 1108: GENOME NON_GENOME PIN 1576
-INST RocketTile__GCB0 PIN 1241: INST TilePRCIDomain__GC0 PIN 4 TYPE 5
-INST RocketTile__GCB0 PIN 1242: INST TilePRCIDomain__GC0 PIN 5 TYPE 5
-INST RocketTile__GCB0 PIN 1252: INST TilePRCIDomain__GC0 PIN 15 TYPE 5
-INST RocketTile__GCB0 PIN 1445: INST DCache PIN 131 TYPE 5
-INST RocketTile__GCB0 PIN 1446: INST DCache PIN 132 TYPE 5
-INST RocketTile__GCB0 PIN 82: INST TilePRCIDomain__GC0 PIN 415 TYPE 0 GENOME RocketTile__GCB0 PIN 82
-INST RocketTile__GCB0 PIN 121: INST TilePRCIDomain__GC0 PIN 454 TYPE 0 GENOME RocketTile__GCB0 PIN 121
-INST RocketTile__GCB0 PIN 122: INST TilePRCIDomain__GC0 PIN 455 TYPE 0 GENOME RocketTile__GCB0 PIN 122
-INST DCache PIN 131: GENOME DCache PIN 131
-INST DCache PIN 336: GENOME DCache PIN 336
-INST DCache PIN 337: GENOME DCache PIN 337
-INST DCache PIN 465: GENOME DCache PIN 465 INST RocketTile__GCB0 PIN 324 TYPE 5
-INST DCache PIN 464: GENOME DCache PIN 464
-INST DCache PIN 466: GENOME DCache PIN 466 INST RocketTile__GCB0 PIN 315 TYPE 5
-INST DCache PIN 455: GENOME DCache PIN 455
-INST DCache PIN 605: GENOME DCache PIN 605 INST RocketTile__GCB0 PIN 403 TYPE 5
-INST DCache PIN 543: GENOME DCache PIN 543
-INST DCache PIN 606: GENOME DCache PIN 606
-INST DCache PIN 607: GENOME DCache PIN 607
-INST DCache PIN 672: GENOME DCache PIN 672 INST RocketTile__GCB0 PIN 470 TYPE 5
-INST DCache PIN 610: GENOME DCache PIN 610
-INST DCache PIN 673: GENOME DCache PIN 673
-INST DCache PIN 674: GENOME DCache PIN 674
-INST DCache PIN 739: GENOME DCache PIN 739 INST RocketTile__GCB0 PIN 537 TYPE 5
-INST DCache PIN 677: GENOME DCache PIN 677
-INST DCache PIN 740: GENOME DCache PIN 740
-INST DCache PIN 741: GENOME DCache PIN 741
-INST DCache PIN 806: GENOME DCache PIN 806 INST RocketTile__GCB0 PIN 604 TYPE 5
-INST DCache PIN 744: GENOME DCache PIN 744
-INST DCache PIN 807: GENOME DCache PIN 807
-INST DCache PIN 808: GENOME DCache PIN 808
-INST DCache PIN 873: GENOME DCache PIN 873 INST RocketTile__GCB0 PIN 671 TYPE 5
-INST DCache PIN 811: GENOME DCache PIN 811
-INST DCache PIN 874: GENOME DCache PIN 874
-INST DCache PIN 875: GENOME DCache PIN 875
-INST DCache PIN 940: GENOME DCache PIN 940 INST RocketTile__GCB0 PIN 738 TYPE 5
-INST DCache PIN 878: GENOME DCache PIN 878
-INST DCache PIN 941: GENOME DCache PIN 941
-INST DCache PIN 942: GENOME DCache PIN 942
-INST DCache PIN 1007: GENOME DCache PIN 1007 INST RocketTile__GCB0 PIN 805 TYPE 5
-INST DCache PIN 945: GENOME DCache PIN 945
-INST DCache PIN 1008: GENOME DCache PIN 1008
-INST DCache PIN 1009: GENOME DCache PIN 1009
-INST DCache PIN 1074: GENOME DCache PIN 1074 INST RocketTile__GCB0 PIN 872 TYPE 5
-INST DCache PIN 1012: GENOME DCache PIN 1012
-INST DCache PIN 1075: GENOME DCache PIN 1075
-INST DCache PIN 1076: GENOME DCache PIN 1076
-GENOME NON_GENOME PIN 464: GENOME NON_GENOME PIN 465
-GENOME NON_GENOME PIN 455: GENOME NON_GENOME PIN 466
-GENOME NON_GENOME PIN 466: GENOME NON_GENOME PIN 455
-GENOME NON_GENOME PIN 543: GENOME NON_GENOME PIN 605
-GENOME NON_GENOME PIN 605: GENOME NON_GENOME PIN 543
-GENOME NON_GENOME PIN 610: GENOME NON_GENOME PIN 672
-GENOME NON_GENOME PIN 672: GENOME NON_GENOME PIN 610
-GENOME NON_GENOME PIN 677: GENOME NON_GENOME PIN 739
-GENOME NON_GENOME PIN 739: GENOME NON_GENOME PIN 677
-GENOME NON_GENOME PIN 744: GENOME NON_GENOME PIN 806
-GENOME NON_GENOME PIN 811: GENOME NON_GENOME PIN 873
-GENOME NON_GENOME PIN 873: GENOME NON_GENOME PIN 811
-GENOME NON_GENOME PIN 878: GENOME NON_GENOME PIN 940
-GENOME NON_GENOME PIN 940: GENOME NON_GENOME PIN 878
-GENOME NON_GENOME PIN 945: GENOME NON_GENOME PIN 1007
-GENOME NON_GENOME PIN 1007: GENOME NON_GENOME PIN 945
-GENOME NON_GENOME PIN 1012: GENOME NON_GENOME PIN 1074
-INST VCU118RocketSystem__GC0 PIN 83: GENOME VCU118RocketSystem__GC0 PIN 83
-INST VCU118RocketSystem__GC0 PIN 84: GENOME VCU118RocketSystem__GC0 PIN 84
-INST VCU118RocketSystem__GC0 PIN 85: GENOME VCU118RocketSystem__GC0 PIN 85
-INST VCU118RocketSystem__GC0 PIN 86: GENOME VCU118RocketSystem__GC0 PIN 86
-INST VCU118RocketSystem__GC0 PIN 87: GENOME VCU118RocketSystem__GC0 PIN 87
-INST VCU118RocketSystem__GC0 PIN 126: GENOME VCU118RocketSystem__GC0 PIN 126
-INST VCU118RocketSystem__GC0 PIN 127: GENOME VCU118RocketSystem__GC0 PIN 127
-INST VCU118RocketSystem__GC0 PIN 128: GENOME VCU118RocketSystem__GC0 PIN 128
-INST VCU118RocketSystem__GC0 PIN 129: GENOME VCU118RocketSystem__GC0 PIN 129
-INST VCU118RocketSystem__GC0 PIN 130: GENOME VCU118RocketSystem__GC0 PIN 130
-INST VCU118RocketSystem__GC0 PIN 131: GENOME VCU118RocketSystem__GC0 PIN 131
-INST VCU118RocketSystem__GC0 PIN 132: GENOME VCU118RocketSystem__GC0 PIN 132
-INST VCU118RocketSystem__GC0 PIN 133: GENOME VCU118RocketSystem__GC0 PIN 133
-INST VCU118RocketSystem__GC0 PIN 134: GENOME VCU118RocketSystem__GC0 PIN 134
-INST VCU118RocketSystem__GC0 PIN 135: GENOME VCU118RocketSystem__GC0 PIN 135
-INST VCU118RocketSystem__GC0 PIN 136: GENOME VCU118RocketSystem__GC0 PIN 136
-INST VCU118RocketSystem__GC0 PIN 169: GENOME VCU118RocketSystem__GC0 PIN 169
-INST VCU118RocketSystem__GC0 PIN 171: GENOME VCU118RocketSystem__GC0 PIN 171
-INST VCU118RocketSystem__GC0 PIN 172: GENOME VCU118RocketSystem__GC0 PIN 172
-INST VCU118RocketSystem__GC0 PIN 289: GENOME VCU118RocketSystem__GC0 PIN 289
-INST VCU118RocketSystem__GC0 PIN 335: GENOME VCU118RocketSystem__GC0 PIN 335
-INST VCU118RocketSystem__GC0 PIN 336: GENOME VCU118RocketSystem__GC0 PIN 336
-INST VCU118RocketSystem__GC0 PIN 489: GENOME VCU118RocketSystem__GC0 PIN 489
-INST VCU118RocketSystem__GC0 PIN 490: GENOME VCU118RocketSystem__GC0 PIN 490
-INST VCU118RocketSystem__GC0 PIN 492: GENOME VCU118RocketSystem__GC0 PIN 492
-INST VCU118RocketSystem__GC0 PIN 493: GENOME VCU118RocketSystem__GC0 PIN 493
-INST VCU118RocketSystem__GC0 PIN 503: GENOME VCU118RocketSystem__GC0 PIN 503
-INST VCU118RocketSystem__GC0 PIN 550: GENOME VCU118RocketSystem__GC0 PIN 550
-INST VCU118RocketSystem__GC0 PIN 551: GENOME VCU118RocketSystem__GC0 PIN 551
-INST VCU118RocketSystem__GC0 PIN 616: GENOME VCU118RocketSystem__GC0 PIN 616
-GENOME NON_GENOME PIN 360: GENOME NON_GENOME PIN 79
-GENOME NON_GENOME PIN 79: GENOME NON_GENOME PIN 360
-GENOME NON_GENOME PIN 361: GENOME NON_GENOME PIN 80
-GENOME NON_GENOME PIN 80: GENOME NON_GENOME PIN 361
-GENOME NON_GENOME PIN 356: GENOME NON_GENOME PIN 171
-GENOME NON_GENOME PIN 171: GENOME NON_GENOME PIN 356
-GENOME NON_GENOME PIN 357: GENOME NON_GENOME PIN 172
-GENOME NON_GENOME PIN 172: GENOME NON_GENOME PIN 357
-GENOME NON_GENOME PIN 334: GENOME NON_GENOME PIN 335 GENOME NON_GENOME PIN 336
-GENOME NON_GENOME PIN 335: GENOME NON_GENOME PIN 334
-GENOME NON_GENOME PIN 336: GENOME NON_GENOME PIN 334
-INST FPU__GB1 PIN 1: GENOME FPU__GB1 PIN 1
-INST FPU__GB1 PIN 137: GENOME FPU__GB1 PIN 137
-INST FPU__GB1 PIN 162: GENOME FPU__GB1 PIN 162
-INST FPU__GB1 PIN 525: GENOME FPU__GB1 PIN 525
-INST FPU__GB1 PIN 526: GENOME FPU__GB1 PIN 526
-INST FPU__GB1 PIN 527: GENOME FPU__GB1 PIN 527
-INST FPU__GB1 PIN 528: GENOME FPU__GB1 PIN 528
-INST FPU__GB1 PIN 531: GENOME FPU__GB1 PIN 531
-INST FPU__GB1 PIN 532: GENOME FPU__GB1 PIN 532
-INST FPU__GB1 PIN 533: GENOME FPU__GB1 PIN 533
-GENOME NON_GENOME PIN 536: GENOME NON_GENOME PIN 146
-GENOME NON_GENOME PIN 146: GENOME NON_GENOME PIN 536
-INST TilePRCIDomain__GC0 PIN 4: GENOME TilePRCIDomain__GC0 PIN 4
-INST TilePRCIDomain__GC0 PIN 7: GENOME TilePRCIDomain__GC0 PIN 7
-INST TilePRCIDomain__GC0 PIN 8: GENOME TilePRCIDomain__GC0 PIN 8
-INST TilePRCIDomain__GC0 PIN 14: GENOME TilePRCIDomain__GC0 PIN 14
-INST TilePRCIDomain__GC0 PIN 15: GENOME TilePRCIDomain__GC0 PIN 15
-INST TilePRCIDomain__GC0 PIN 415: GENOME TilePRCIDomain__GC0 PIN 415
-INST TilePRCIDomain__GC0 PIN 454: GENOME TilePRCIDomain__GC0 PIN 454
-INST TilePRCIDomain__GC0 PIN 455: GENOME TilePRCIDomain__GC0 PIN 455
-INST TilePRCIDomain__GC0 PIN 531: GENOME TilePRCIDomain__GC0 PIN 531
-INST TilePRCIDomain__GC0 PIN 732: GENOME TilePRCIDomain__GC0 PIN 732
-INST TilePRCIDomain__GC0 PIN 733: GENOME TilePRCIDomain__GC0 PIN 733
-INST genesys2_rocket_top__GC0 PIN 12: GENOME genesys2_rocket_top__GC0 PIN 12
-INST TLToAPB PIN 52: GENOME TLToAPB PIN 52
-INST FPU__GB2 PIN 1: INST FPU__GB1 PIN 146 TYPE 3 INST RocketTile__GCB0 PIN 1654 TYPE 4
-INST RocketTile__GCB0 PIN 83: INST RocketTile__GCB0 PIN 119 TYPE 2 INST TilePRCIDomain__GC0 PIN 452 TYPE 4 INST RocketTile__GCB0 PIN 120 TYPE 2 INST TilePRCIDomain__GC0 PIN 453 TYPE 4
-INST RocketTile__GCB0 PIN 119: GENOME RocketTile__GCB0 PIN 119
-INST RocketTile__GCB0 PIN 120: GENOME RocketTile__GCB0 PIN 120
-INST TilePRCIDomain__GC0 PIN 452: GENOME TilePRCIDomain__GC0 PIN 452 INST RocketTile__GCB0 PIN 83 TYPE 5
-INST TilePRCIDomain__GC0 PIN 416: GENOME TilePRCIDomain__GC0 PIN 416
-INST TilePRCIDomain__GC0 PIN 453: GENOME TilePRCIDomain__GC0 PIN 453 INST RocketTile__GCB0 PIN 83 TYPE 5
-GENOME NON_GENOME PIN 416: GENOME NON_GENOME PIN 452 GENOME NON_GENOME PIN 453
-GENOME NON_GENOME PIN 452: GENOME NON_GENOME PIN 416
-GENOME NON_GENOME PIN 453: GENOME NON_GENOME PIN 416
-INST FPU__GB1 PIN 146: GENOME FPU__GB1 PIN 146
-INST FPU__GB1 PIN 536: INST FPU__GB2 PIN 1 TYPE 5
-DISSOLVE_GENOME: GENOME tracking_wrapper
-INST TilePRCIDomain__GC0 PIN 204: INST VCU118RocketSystem__GC0 PIN 485 TYPE 0
-INST TilePRCIDomain__GC0 PIN 208: INST VCU118RocketSystem__GC0 PIN 540 TYPE 0
-INST TilePRCIDomain__GC0 PIN 212: INST VCU118RocketSystem__GC0 PIN 544 TYPE 0
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/equivDumpFile.info b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/equivDumpFile.info
deleted file mode 100644
index b4f5727..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/equivDumpFile.info
+++ /dev/null
@@ -1,156 +0,0 @@
-/genesys2_rocket_top__GC0#6:/genesys2_rocket_top__GC0#12
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#5:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#3
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#6:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#4
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#9:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#5
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#10:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#6
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#11:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#7
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#12:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#8
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#16:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#10
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#17:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#11
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#18:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#12
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#19:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#13
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#20:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#14
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#21:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#15
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#22:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#16
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#23:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#17
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#24:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#18
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#25:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#19
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#26:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#20
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#27:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#21
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#28:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#22
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#29:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#23
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#30:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#24
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#31:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#25
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#32:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#26
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#33:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#27
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#34:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#28
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#35:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#29
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#36:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#30
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#37:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#31
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#38:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#32
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#39:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#33
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#40:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#34
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#41:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#35
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#42:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#36
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#43:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#37
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#44:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#38
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#45:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#39
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#46:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#40
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#47:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#41
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#48:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#42
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#49:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#43
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#50:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#44
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#51:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#45
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#52:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#46
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#53:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#47
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#54:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#48
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#55:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#49
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#56:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#50
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#57:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#51
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#58:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#52
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#59:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#53
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#60:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#54
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#61:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#55
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#62:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#56
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#63:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#57
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#64:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#58
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#65:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#59
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#66:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#60
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#67:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#61
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#68:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#62
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#69:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#63
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#70:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#64
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#71:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#65
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#72:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#66
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#73:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#67
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#74:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#68
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#75:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#69
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#76:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#70
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#77:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#71
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#78:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#72
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#79:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#73
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#324:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#325
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#315:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#326
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#403:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#465
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#470:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#532
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#537:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#599
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#604:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#666
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#671:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#733
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#738:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#800
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#805:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#867
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#872:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#934
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#124:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1040
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#125:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1041
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#126:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1042
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#127:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1043
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#128:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1044
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#199:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1045
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#200:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1046
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#201:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1047
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#202:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1048
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#203:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1049
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#204:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1050
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#205:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1051
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#206:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1052
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#207:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1053
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#208:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1054
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#209:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1055
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#210:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1056
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#211:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1057
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#212:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1058
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#213:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1059
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#214:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1060
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#215:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1061
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#216:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1062
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#217:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1063
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#218:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1064
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#219:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1065
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#220:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1066
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#221:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1067
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#222:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1068
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#223:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1069
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#224:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1070
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#225:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1071
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#226:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1072
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#227:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1073
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#228:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1074
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#229:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1075
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#230:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1076
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#231:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1077
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#232:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1078
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#233:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1079
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#234:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1080
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#235:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1081
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#236:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1082
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#237:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1083
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#238:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1084
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#239:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1085
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#240:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1086
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#241:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1087
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#242:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1088
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#243:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1089
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#244:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1090
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#245:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1091
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#246:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1092
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#247:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1093
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#248:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1094
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#249:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1095
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#250:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1096
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#251:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1097
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#252:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1098
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#253:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1099
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#254:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1100
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#255:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1101
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#256:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1102
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#257:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1103
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#258:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1104
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#259:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1105
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#260:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1106
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#261:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1107
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#262:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1108
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#132:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1039
-/u_rocket/VCU118RocketSystem__GC0#334:/u_rocket/VCU118RocketSystem__GC0#335
-/u_rocket/VCU118RocketSystem__GC0#334:/u_rocket/VCU118RocketSystem__GC0#336
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2#1:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1#146
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#83:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#119
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#83:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#120
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1220760385.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1220760385.rtd
deleted file mode 100644
index 2c51de2..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index c116038..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1294509424.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1294509424.rtd
deleted file mode 100644
index 4148f9a..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index 9814855..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/136113302.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/136113302.rtd
deleted file mode 100644
index a2600d9..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd
deleted file mode 100644
index 2166989..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1672436263.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1672436263.rtd
deleted file mode 100644
index 4e6f6a8..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index 9b5ff85..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2438764479.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2438764479.rtd
deleted file mode 100644
index 159ff0a..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2438764479.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd
deleted file mode 100644
index d670ce5..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2610937407.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2610937407.rtd
deleted file mode 100644
index c3b0c2e..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index dc3f9b4..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2737226844.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2737226844.rtd
deleted file mode 100644
index e14b3c2..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index 8589c0a..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2962621930.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2962621930.rtd
deleted file mode 100644
index 288ad37..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index 0fc52ac..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3482045580.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3482045580.rtd
deleted file mode 100644
index af37765..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index 45f3ef1..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3990655999.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3990655999.rtd
deleted file mode 100644
index 824560e..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3990655999.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd
deleted file mode 100644
index 086665d..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/976197094.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/976197094.rtd
deleted file mode 100644
index aa6cfd5..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd
deleted file mode 100644
index 43be038..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/global_name.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/global_name.straps.rtd
deleted file mode 100644
index 99a7499..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/instToEncGenName.map b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/instToEncGenName.map
deleted file mode 100644
index 5e84eed..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/g/instToEncGenName.map
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
-/genesys2_rocket_top__GC0:3990655999
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0:2438764479
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/stitchPoint.lst b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/stitchPoint.lst
deleted file mode 100644
index 840b612..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/stitchPoint.lst
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/fpga_gps_domain/tl2apb
-/u_rocket/fpga_gps_domain/dev/tracking_8
-/u_rocket/fpga_gps_domain/dev/tracking_7
-/u_rocket/fpga_gps_domain/dev/tracking_6
-/u_rocket/fpga_gps_domain/dev/tracking_5
-/u_rocket/fpga_gps_domain/dev/tracking_4
-/u_rocket/fpga_gps_domain/dev/tracking_3
-/u_rocket/fpga_gps_domain/dev/tracking_2
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0
-/u_rocket/fpga_gps_domain/dev/tracking_1
-/u_rocket/fpga_gps_domain/dev/tracking_0
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache
-/u_rocket/VCU118RocketSystem__GC0
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1
-/genesys2_rocket_top__GC0
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2ECDAC80.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2ECDAC80.rtd
deleted file mode 100644
index 9a856d2..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2ECDAC80.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2ECDB620.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2ECDB620.rtd
deleted file mode 100644
index ad6a336..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2ECDB620.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2F5B08C0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2F5B08C0.rtd
deleted file mode 100644
index 9b24a26..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2F5B08C0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2F8EB1C0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2F8EB1C0.rtd
deleted file mode 100644
index 964dcba..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/2F8EB1C0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/3159FDC0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/3159FDC0.rtd
deleted file mode 100644
index fbce035..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/3159FDC0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/462CC640.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/462CC640.rtd
deleted file mode 100644
index 53843d0..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/462CC640.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/46327200.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/46327200.rtd
deleted file mode 100644
index b0506ec..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/46327200.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/46408120.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/46408120.rtd
deleted file mode 100644
index 8ebbeb3..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/46408120.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/56B868A0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/56B868A0.rtd
deleted file mode 100644
index 8164e48..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/56B868A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/57156320.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/57156320.rtd
deleted file mode 100644
index 1a01c90..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/57156320.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/611E74A0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/611E74A0.rtd
deleted file mode 100644
index b3af2b9..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/611E74A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/design.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/design.rtd
deleted file mode 100644
index ddbf1d1..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/files.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/files.rtd
deleted file mode 100644
index 19449f9..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/files.rtd
+++ /dev/null
@@ -1,13 +0,0 @@
-design.rtd
-straps.rtd
-2ECDAC80.rtd
-2ECDB620.rtd
-2F5B08C0.rtd
-3159FDC0.rtd
-611E74A0.rtd
-57156320.rtd
-56B868A0.rtd
-46327200.rtd
-462CC640.rtd
-46408120.rtd
-2F8EB1C0.rtd
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/straps.rtd
deleted file mode 100644
index 5d5f617..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/uniqInferGenToOrigInferGen.map b/.Xil/Vivado-198675-onur/incrSyn/1309558296/o/uniqInferGenToOrigInferGen.map
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/childModToGenomes.map b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/childModToGenomes.map
deleted file mode 100644
index d1483ba..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/childModToGenomes.map
+++ /dev/null
@@ -1,8313 +0,0 @@
-case__792: FPU__GB1,
-logic__5758: RocketTile__GCB0,
-logic__6934: VCU118RocketSystem__GC0,
-logic__8485: APBGpsBlock__GC0,
-case__683: FPU__GB2,
-logic__3335: FPU__GB1,
-case__1540: tracking_wrapper,
-logic__7309: VCU118RocketSystem__GC0,
-case__848: RocketTile__GCB0,
-muxpart__267: VCU118RocketSystem__GC0,
-logic__8937: tracking_wrapper,
-logic__9398: tracking_wrapper,
-logic__619: genesys2_rocket_top__GC0,
-case__414: VCU118RocketSystem__GC0,
-logic__1324: VCU118RocketSystem__GC0,
-reg__558: FPU__GB1,
-Repeater_TLBundleA_a29d32s2k1z3u: VCU118RocketSystem__GC0,
-logic__8303: VCU118RocketSystem__GC0,
-logic__9150: tracking_wrapper,
-cordic_atan_one_stage__parameterized0: tracking_wrapper,
-logic__5474: RocketTile__GCB0,
-reg__845: RocketTile__GCB0,
-case__958: RocketTile__GCB0,
-case__1497: APBGpsBlock__GC0,
-case__1115: VCU118RocketSystem__GC0,
-logic__5328: RocketTile__GCB0,
-logic__8158: VCU118RocketSystem__GC0,
-datapath__31: VCU118RocketSystem__GC0,
-reg__468: FPU__GB0,
-case__1395: APBGpsBlock__GC0,
-logic__4464: FPU__GB1,
-logic__8678: APBGpsBlock__GC0,
-logic__5359: RocketTile__GCB0,
-case__437: VCU118RocketSystem__GC0,
-logic__2221: DCache,
-logic__6157: RocketTile__GCB0,
-logic__5164: RocketTile__GCB0,
-logic__6282: RocketTile__GCB0,
-datapath__209: VCU118RocketSystem__GC0,
-reg__576: FPU__GB1,
-logic__591: genesys2_rocket_top__GC0,
-reg__227: VCU118RocketSystem__GC0,
-reg__672: RocketTile__GCB0,
-reg__748: RocketTile__GCB0,
-reg__1415: tracking_wrapper,
-logic__6010: RocketTile__GCB0,
-logic__4405: FPU__GB1,
-logic__5259: RocketTile__GCB0,
-case__1133: VCU118RocketSystem__GC0,
-logic__510: genesys2_rocket_top__GC0,
-logic__7206: VCU118RocketSystem__GC0,
-datapath__35: VCU118RocketSystem__GC0,
-reg__604: FPU__GB2,
-logic__8071: VCU118RocketSystem__GC0,
-logic__9300: tracking_wrapper,
-logic__115: genesys2_rocket_top__GC0,
-logic__7916: VCU118RocketSystem__GC0,
-reg__848: RocketTile__GCB0,
-logic__9356: tracking_wrapper,
-logic__7074: VCU118RocketSystem__GC0,
-logic__943: VCU118RocketSystem__GC0,
-logic__3518: FPU__GB1,
-logic__1518: VCU118RocketSystem__GC0,
-logic__4970: FPU__GB2,
-case__989: VCU118RocketSystem__GC0,
-reg__1410: tracking_wrapper,
-datapath__675: tracking_wrapper,
-logic__6728: TilePRCIDomain__GC0,
-datapath__200: VCU118RocketSystem__GC0,
-case__539: DCache,
-logic__7427: VCU118RocketSystem__GC0,
-reg__1360: tracking_wrapper,
-logic__6150: RocketTile__GCB0,
-reg__462: FPU__GB0,
-case__748: FPU__GB2,
-reg__1084: VCU118RocketSystem__GC0,
-reg__82: genesys2_rocket_top__GC0,
-logic__1695: VCU118RocketSystem__GC0,
-reg__344: DCache,
-logic__6050: RocketTile__GCB0,
-cordic_atan_basic__parameterized0: tracking_wrapper,
-datapath__153: VCU118RocketSystem__GC0,
-case__348: VCU118RocketSystem__GC0,
-logic__3224: RocketTile__GCB0,
-reg__711: RocketTile__GCB0,
-logic__8025: VCU118RocketSystem__GC0,
-reg__459: FPU__GB0,
-logic__5073: FPU__GB1,
-datapath__215: VCU118RocketSystem__GC0,
-DCache: DCache,
-logic__4356: FPU__GB1,
-logic__3047: RocketTile__GCB0,
-case__654: FPU__GB1,
-datapath__293: RocketTile__GCB0,
-logic__3504: FPU__GB1,
-datapath__92: VCU118RocketSystem__GC0,
-logic__3503: FPU__GB1,
-logic__4072: FPU__GB2,
-logic__5945: RocketTile__GCB0,
-logic__208: genesys2_rocket_top__GC0,
-logic__9186: tracking_wrapper,
-reg__1058: VCU118RocketSystem__GC0,
-logic__1886: VCU118RocketSystem__GC0,
-reg__207: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__637: APBGpsBlock__GC0,
-case__574: RocketTile__GCB0,
-case__1530: APBGpsBlock__GC0,
-logic__4905: FPU__GB2,
-logic__2598: DCache,
-logic__8497: APBGpsBlock__GC0,
-logic__9085: tracking_wrapper,
-logic__5858: RocketTile__GCB0,
-reg__572: FPU__GB1,
-logic__1681: VCU118RocketSystem__GC0,
-logic__6129: RocketTile__GCB0,
-case__1725: APBGpsBlock__GC0,
-logic__4395: FPU__GB1,
-logic__900: VCU118RocketSystem__GC0,
-logic__3435: FPU__GB1,
-logic__6077: RocketTile__GCB0,
-logic__8913: tracking_wrapper,
-logic__1952: VCU118RocketSystem__GC0,
-logic__3442: FPU__GB1,
-logic__6639: RocketTile__GCB0,
-reg__1251: tracking_wrapper,
-logic__9332: tracking_wrapper,
-logic__4317: FPU__GB1,
-case__1301: APBGpsBlock__GC0,
-logic__978: VCU118RocketSystem__GC0,
-logic__9369: tracking_wrapper,
-logic__1095: VCU118RocketSystem__GC0,
-logic__7239: VCU118RocketSystem__GC0,
-datapath__57: VCU118RocketSystem__GC0,
-logic__947: VCU118RocketSystem__GC0,
-logic__9600: TLToAPB,
-case__1603: tracking_wrapper,
-reg__420: RocketTile__GCB0,
-logic__4635: FPU__GB1,
-case__1346: APBGpsBlock__GC0,
-logic__2464: DCache,
-reg__998: VCU118RocketSystem__GC0,
-IntToFP: FPU__GB2,
-reg__192: VCU118RocketSystem__GC0,
-FixedClockBroadcast_4: VCU118RocketSystem__GC0,
-logic__4416: FPU__GB1,
-logic__9113: tracking_wrapper,
-logic__2731: DCache,
-reg__434: RocketTile__GCB0,
-logic__4656: FPU__GB2,
-reg__592: FPU__GB2,
-logic__197: genesys2_rocket_top__GC0,
-case__1597: tracking_wrapper,
-case__36: genesys2_rocket_top__GC0,
-logic__1330: VCU118RocketSystem__GC0,
-reg__581: FPU__GB1,
-case__604: RocketTile__GCB0,
-logic__5920: RocketTile__GCB0,
-case__973: RocketTile__GCB0,
-reg__1143: APBGpsBlock__GC0,
-logic__5673: RocketTile__GCB0,
-reg__527: FPU__GB2,
-datapath__611: APBGpsBlock__GC0,
-reg__1077: VCU118RocketSystem__GC0,
-datapath__298: RocketTile__GCB0,
-logic__8883: tracking_wrapper,
-logic__1381: VCU118RocketSystem__GC0,
-datapath__178: VCU118RocketSystem__GC0,
-case__545: DCache,
-datapath__656: tracking_wrapper,
-logic__7144: VCU118RocketSystem__GC0,
-datapath__458: RocketTile__GCB0,
-logic__9078: tracking_wrapper,
-reg__415: RocketTile__GCB0,
-reg__1024: VCU118RocketSystem__GC0,
-case__1328: APBGpsBlock__GC0,
-reg__259: VCU118RocketSystem__GC0,
-logic__4217: FPU__GB1,
-logic__7282: VCU118RocketSystem__GC0,
-case__651: FPU__GB1,
-case__521: DCache,
-logic__3316: FPU__GB1,
-reg__333: DCache,
-logic__7200: VCU118RocketSystem__GC0,
-logic__1487: VCU118RocketSystem__GC0,
-reg__528: FPU__GB2,
-logic__8314: VCU118RocketSystem__GC0,
-logic__4737: FPU__GB2,
-logic__6458: RocketTile__GCB0,
-logic__7381: VCU118RocketSystem__GC0,
-logic__2262: DCache,
-logic__4985: FPU__GB1,
-case__1082: VCU118RocketSystem__GC0,
-logic__1682: VCU118RocketSystem__GC0,
-reg__200: VCU118RocketSystem__GC0,
-acq_peak_srch: APBGpsBlock__GC0,
-reg__1081: VCU118RocketSystem__GC0,
-logic__7412: VCU118RocketSystem__GC0,
-muxpart__382: tracking_wrapper,
-reg__550: FPU__GB1,
-logic__3496: FPU__GB1,
-case__184: genesys2_rocket_top__GC0,
-logic__6814: VCU118RocketSystem__GC0,
-case__693: FPU__GB2,
-case__1379: APBGpsBlock__GC0,
-logic__1293: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__5178: RocketTile__GCB0,
-case__921: RocketTile__GCB0,
-case__220: genesys2_rocket_top__GC0,
-reg__1379: tracking_wrapper,
-case__206: genesys2_rocket_top__GC0,
-reg__984: VCU118RocketSystem__GC0,
-logic__8284: VCU118RocketSystem__GC0,
-case__153: genesys2_rocket_top__GC0,
-datapath__230: VCU118RocketSystem__GC0,
-reg__1248: tracking_wrapper,
-counter__5: genesys2_rocket_top__GC0,
-case__146: genesys2_rocket_top__GC0,
-case__1251: VCU118RocketSystem__GC0,
-muxpart__212: FPU__GB0,
-reg__92: genesys2_rocket_top__GC0,
-logic__2834: DCache,
-logic__6076: RocketTile__GCB0,
-case__698: FPU__GB2,
-case__900: RocketTile__GCB0,
-logic__906: VCU118RocketSystem__GC0,
-logic__4360: FPU__GB1,
-reg__1331: tracking_wrapper,
-reg__832: RocketTile__GCB0,
-RecFNToRecFN: FPU__GB1,
-muxpart__161: VCU118RocketSystem__GC0,
-logic__7792: VCU118RocketSystem__GC0,
-case__635: RocketTile__GCB0,
-logic__7202: VCU118RocketSystem__GC0,
-case__991: VCU118RocketSystem__GC0,
-case__260: VCU118RocketSystem__GC0,
-logic__9063: tracking_wrapper,
-logic__7852: VCU118RocketSystem__GC0,
-logic__2822: DCache,
-logic__3356: FPU__GB1,
-reg__492: FPU__GB1,
-case__712: FPU__GB1,
-logic__7042: VCU118RocketSystem__GC0,
-reg__427: RocketTile__GCB0,
-datapath__464: RocketTile__GCB0,
-logic__6780: VCU118RocketSystem__GC0,
-logic__3323: FPU__GB1,
-logic__6803: VCU118RocketSystem__GC0,
-logic__6830: VCU118RocketSystem__GC0,
-logic__7729: VCU118RocketSystem__GC0,
-case__1129: VCU118RocketSystem__GC0,
-reg__361: DCache,
-reg__132: VCU118RocketSystem__GC0,
-logic__2093: RocketTile__GCB0,
-datapath__278: DCache,
-logic__7396: VCU118RocketSystem__GC0,
-reg__347: DCache,
-case__278: VCU118RocketSystem__GC0,
-case__1495: APBGpsBlock__GC0,
-datapath__226: VCU118RocketSystem__GC0,
-logic__8568: APBGpsBlock__GC0,
-reg__64: genesys2_rocket_top__GC0,
-case__4: genesys2_rocket_top__GC0,
-datapath__289: RocketTile__GCB0,
-reg__315: VCU118RocketSystem__GC0,
-case__328: VCU118RocketSystem__GC0,
-logic__6075: RocketTile__GCB0,
-muxpart__301: APBGpsBlock__GC0,
-datapath__202: VCU118RocketSystem__GC0,
-logic__3303: RocketTile__GCB0,
-reg__1144: APBGpsBlock__GC0,
-reg__496: FPU__GB1,
-logic__8283: VCU118RocketSystem__GC0,
-reg__1357: tracking_wrapper,
-logic__5568: RocketTile__GCB0,
-datapath__537: VCU118RocketSystem__GC0,
-datapath__472: RocketTile__GCB0,
-logic__7115: VCU118RocketSystem__GC0,
-reg__1204: APBGpsBlock__GC0,
-logic__3187: RocketTile__GCB0,
-logic__2868: DCache,
-reg__793: RocketTile__GCB0,
-logic__8113: VCU118RocketSystem__GC0,
-logic__7179: VCU118RocketSystem__GC0,
-case__1155: VCU118RocketSystem__GC0,
-case__603: RocketTile__GCB0,
-reg__1034: VCU118RocketSystem__GC0,
-logic__6974: VCU118RocketSystem__GC0,
-logic__6821: VCU118RocketSystem__GC0,
-case__363: VCU118RocketSystem__GC0,
-datapath__99: VCU118RocketSystem__GC0,
-reg__884: VCU118RocketSystem__GC0,
-TLFIFOFixer: VCU118RocketSystem__GC0,
-reg__1319: tracking_wrapper,
-logic__7443: VCU118RocketSystem__GC0,
-reg__503: FPU__GB1,
-logic__6828: VCU118RocketSystem__GC0,
-logic__3: genesys2_rocket_top__GC0,
-keep__14: tracking_wrapper,
-logic__4304: FPU__GB1,
-logic__5460: RocketTile__GCB0,
-MulAddRecFNToRaw_preMul: FPU__GB1,
-reg__1012: VCU118RocketSystem__GC0,
-reg__1166: APBGpsBlock__GC0,
-logic__4796: FPU__GB2,
-logic__2887: DCache,
-logic__7277: VCU118RocketSystem__GC0,
-case__57: genesys2_rocket_top__GC0,
-datapath__379: FPU__GB1,
-case__1574: tracking_wrapper,
-logic__9429: tracking_wrapper,
-logic__9015: tracking_wrapper,
-logic__8425: APBGpsBlock__GC0,
-reg__198: VCU118RocketSystem__GC0,
-logic__1998: VCU118RocketSystem__GC0,
-logic__925: VCU118RocketSystem__GC0,
-logic__6525: RocketTile__GCB0,
-case__1112: VCU118RocketSystem__GC0,
-reg__202: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4827: FPU__GB2,
-case__1295: APBGpsBlock__GC0,
-logic__3998: FPU__GB2,
-logic__2257: DCache,
-logic__8948: tracking_wrapper,
-reg__1100: APBGpsBlock__GC0,
-datapath__437: RocketTile__GCB0,
-case__489: RocketTile__GCB0,
-case__797: FPU__GB1,
-case__966: RocketTile__GCB0,
-logic__9609: genesys2_rocket_top__GC0,
-logic__1550: VCU118RocketSystem__GC0,
-muxpart__198: FPU__GB0,
-logic__9508: tracking_wrapper,
-case__680: FPU__GB2,
-logic__271: genesys2_rocket_top__GC0,
-logic__1950: VCU118RocketSystem__GC0,
-logic__1030: VCU118RocketSystem__GC0,
-logic__3535: FPU__GB1,
-TLDebugModuleOuterAsync: VCU118RocketSystem__GC0,
-cdc_fifo_gray: tracking_wrapper,
-case__1477: APBGpsBlock__GC0,
-TLWidthWidget8_1: VCU118RocketSystem__GC0, RocketTile__GCB0,
-logic__131: genesys2_rocket_top__GC0,
-case__1185: VCU118RocketSystem__GC0,
-reg__288: VCU118RocketSystem__GC0,
-ClockGroupAggregator_aggregator: VCU118RocketSystem__GC0,
-logic__6160: RocketTile__GCB0,
-logic__5151: RocketTile__GCB0,
-case__1202: VCU118RocketSystem__GC0,
-logic__1862: VCU118RocketSystem__GC0,
-case__117: genesys2_rocket_top__GC0,
-datapath__56: VCU118RocketSystem__GC0,
-logic__6751: VCU118RocketSystem__GC0,
-datapath__516: VCU118RocketSystem__GC0,
-logic__8428: APBGpsBlock__GC0,
-datapath__447: RocketTile__GCB0,
-case__912: RocketTile__GCB0,
-datapath__432: RocketTile__GCB0,
-datapath__627: APBGpsBlock__GC0,
-reg__717: RocketTile__GCB0,
-reg__1032: VCU118RocketSystem__GC0,
-logic__4436: FPU__GB1,
-case__1329: APBGpsBlock__GC0,
-reg__701: RocketTile__GCB0,
-logic__9521: APBGpsBlock__GC0,
-case__1499: APBGpsBlock__GC0,
-logic__599: genesys2_rocket_top__GC0,
-logic__9345: tracking_wrapper,
-reg__720: RocketTile__GCB0,
-logic__9528: APBGpsBlock__GC0,
-reg__213: VCU118RocketSystem__GC0,
-logic__9383: tracking_wrapper,
-logic__5475: RocketTile__GCB0,
-datapath__510: VCU118RocketSystem__GC0,
-logic__3833: FPU__GB2,
-case__1660: tracking_wrapper,
-logic__3953: FPU__GB2,
-logic__2515: RocketTile__GCB0, DCache,
-logic__8517: APBGpsBlock__GC0,
-reg__279: VCU118RocketSystem__GC0,
-logic__3636: FPU__GB2, FPU__GB1,
-logic__5316: RocketTile__GCB0,
-reg__1182: APBGpsBlock__GC0,
-logic__2716: DCache,
-logic__6614: RocketTile__GCB0,
-logic__6096: RocketTile__GCB0,
-logic__6123: RocketTile__GCB0,
-reg__153: VCU118RocketSystem__GC0,
-datapath__425: RocketTile__GCB0,
-reg__1133: APBGpsBlock__GC0,
-reg__749: RocketTile__GCB0,
-logic__7421: VCU118RocketSystem__GC0,
-logic__5205: RocketTile__GCB0,
-case__751: FPU__GB2,
-logic__4448: FPU__GB1,
-case__1435: APBGpsBlock__GC0,
-reg__677: RocketTile__GCB0,
-logic__2109: RocketTile__GCB0,
-datapath__284: DCache,
-logic__7258: VCU118RocketSystem__GC0,
-reg__98: genesys2_rocket_top__GC0,
-logic__1806: VCU118RocketSystem__GC0,
-logic__7204: VCU118RocketSystem__GC0,
-reg__151: VCU118RocketSystem__GC0,
-reg__396: RocketTile__GCB0,
-logic__4391: FPU__GB1,
-case__1724: APBGpsBlock__GC0,
-rockettile_icache_data_arrays_512x32: RocketTile__GCB0,
-logic__7417: VCU118RocketSystem__GC0,
-datapath__204: VCU118RocketSystem__GC0,
-case__789: FPU__GB1,
-reg__615: FPU__GB1,
-logic__2196: DCache,
-reg__737: RocketTile__GCB0,
-logic__1420: VCU118RocketSystem__GC0,
-logic__5332: RocketTile__GCB0,
-case__1224: VCU118RocketSystem__GC0,
-logic__4866: FPU__GB2,
-logic__2632: DCache,
-logic__5093: FPU__GB1,
-reg__368: DCache,
-Queue1_TLBundleA_a29d32s7k1z2u: TLToAPB,
-logic__6847: VCU118RocketSystem__GC0,
-logic__1656: VCU118RocketSystem__GC0,
-logic__9522: APBGpsBlock__GC0,
-reg__1402: tracking_wrapper,
-case__573: RocketTile__GCB0,
-case__1153: VCU118RocketSystem__GC0,
-case__1124: VCU118RocketSystem__GC0,
-logic__7250: VCU118RocketSystem__GC0,
-AsyncResetRegVec_w2_i0: VCU118RocketSystem__GC0,
-datapath__250: VCU118RocketSystem__GC0,
-muxpart__214: FPU__GB0,
-case__994: VCU118RocketSystem__GC0,
-logic__4923: FPU__GB1,
-muxpart__20: genesys2_rocket_top__GC0,
-reg__336: DCache,
-logic__3358: FPU__GB1,
-logic__7972: VCU118RocketSystem__GC0,
-logic__1348: VCU118RocketSystem__GC0,
-logic__4661: FPU__GB2,
-logic__9554: APBGpsBlock__GC0,
-logic__3887: FPU__GB2,
-logic__3021: RocketTile__GCB0,
-datapath__391: FPU__GB2,
-logic__700: genesys2_rocket_top__GC0,
-reg__1318: tracking_wrapper,
-logic__6108: RocketTile__GCB0,
-case__942: RocketTile__GCB0,
-logic__6130: RocketTile__GCB0,
-logic__560: genesys2_rocket_top__GC0,
-datapath__152: VCU118RocketSystem__GC0,
-logic__4638: FPU__GB1,
-logic__1110: VCU118RocketSystem__GC0,
-acq_corr: APBGpsBlock__GC0,
-logic__631: genesys2_rocket_top__GC0,
-reg__981: VCU118RocketSystem__GC0,
-datapath__90: VCU118RocketSystem__GC0,
-datapath__467: RocketTile__GCB0,
-logic__5962: RocketTile__GCB0,
-logic__2467: DCache,
-logic__3318: FPU__GB1,
-case__1003: VCU118RocketSystem__GC0,
-logic__5542: RocketTile__GCB0,
-logic__6863: VCU118RocketSystem__GC0,
-logic__3554: FPU__GB1,
-reg__982: VCU118RocketSystem__GC0,
-reg__1225: tracking_wrapper,
-logic__5092: FPU__GB1,
-logic__2873: DCache,
-logic__2530: RocketTile__GCB0, DCache,
-logic__5904: RocketTile__GCB0,
-reg__32: genesys2_rocket_top__GC0,
-logic__5097: FPU__GB1,
-logic__501: genesys2_rocket_top__GC0,
-logic__1598: VCU118RocketSystem__GC0,
-logic__3234: RocketTile__GCB0,
-logic__1045: VCU118RocketSystem__GC0,
-case__1601: tracking_wrapper,
-case__1208: VCU118RocketSystem__GC0,
-logic__6286: RocketTile__GCB0,
-logic__1794: VCU118RocketSystem__GC0,
-logic__4867: FPU__GB2,
-datapath__275: DCache,
-logic__877: VCU118RocketSystem__GC0,
-logic__2818: DCache,
-logic__8603: APBGpsBlock__GC0,
-datapath__206: VCU118RocketSystem__GC0,
-case__613: RocketTile__GCB0,
-double_ff_syn__parameterized0: tracking_wrapper,
-reg__1419: tracking_wrapper,
-datapath__320: FPU__GB1,
-logic__1552: VCU118RocketSystem__GC0,
-reg__789: RocketTile__GCB0,
-case__530: DCache,
-logic__5115: FPU__GB1,
-datapath__160: VCU118RocketSystem__GC0,
-logic__6023: RocketTile__GCB0,
-logic__1258: VCU118RocketSystem__GC0,
-logic__5876: RocketTile__GCB0,
-logic__317: genesys2_rocket_top__GC0,
-logic__4741: FPU__GB2,
-logic__4703: FPU__GB2,
-TLFragmenter_bootrom: VCU118RocketSystem__GC0,
-mult_46_15_61: APBGpsBlock__GC0,
-logic__108: genesys2_rocket_top__GC0,
-logic__1337: VCU118RocketSystem__GC0,
-logic__6040: RocketTile__GCB0,
-logic__217: genesys2_rocket_top__GC0,
-case__771: FPU__GB2,
-reg__475: FPU__GB0,
-logic__2583: DCache,
-reg__325: DCache,
-reg__614: FPU__GB1,
-logic__8493: APBGpsBlock__GC0,
-datapath__445: RocketTile__GCB0,
-datapath__24: genesys2_rocket_top__GC0,
-reg__1162: APBGpsBlock__GC0,
-logic__5509: RocketTile__GCB0,
-logic__5327: RocketTile__GCB0,
-logic__7384: VCU118RocketSystem__GC0,
-reg__1096: APBGpsBlock__GC0,
-logic__4820: FPU__GB2,
-reg__1193: APBGpsBlock__GC0,
-reg__1039: VCU118RocketSystem__GC0,
-datapath__34: VCU118RocketSystem__GC0,
-case__1623: tracking_wrapper,
-case__411: VCU118RocketSystem__GC0,
-logic__2881: DCache,
-reg__1008: VCU118RocketSystem__GC0,
-rocket_bscan_dmi_tunnel: genesys2_rocket_top__GC0,
-logic__3351: FPU__GB1,
-reg__1392: tracking_wrapper,
-case__1716: tracking_wrapper,
-datapath__574: APBGpsBlock__GC0,
-TLBuffer_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__1962: VCU118RocketSystem__GC0,
-case__978: RocketTile__GCB0,
-logic__7003: VCU118RocketSystem__GC0,
-logic__5382: RocketTile__GCB0,
-case__440: VCU118RocketSystem__GC0,
-logic__4007: FPU__GB2,
-reg__519: FPU__GB1,
-logic__5481: RocketTile__GCB0,
-logic__7462: VCU118RocketSystem__GC0,
-logic__7177: VCU118RocketSystem__GC0,
-logic__1266: VCU118RocketSystem__GC0,
-reg__936: VCU118RocketSystem__GC0,
-logic__6053: RocketTile__GCB0,
-datapath__158: VCU118RocketSystem__GC0,
-reg__362: DCache,
-datapath__448: RocketTile__GCB0,
-logic__7543: VCU118RocketSystem__GC0,
-case__336: VCU118RocketSystem__GC0,
-logic__4435: FPU__GB1,
-reg__304: VCU118RocketSystem__GC0,
-logic__6833: VCU118RocketSystem__GC0,
-logic__1478: VCU118RocketSystem__GC0,
-logic__9272: tracking_wrapper,
-datapath__604: APBGpsBlock__GC0,
-reg__1334: tracking_wrapper,
-dsp48e1__15: APBGpsBlock__GC0,
-reg__725: RocketTile__GCB0,
-case__740: FPU__GB2,
-case__614: RocketTile__GCB0,
-reg__916: VCU118RocketSystem__GC0,
-datapath__172: VCU118RocketSystem__GC0,
-datapath__671: tracking_wrapper,
-datapath__1: genesys2_rocket_top__GC0,
-logic__9196: tracking_wrapper,
-reg__398: RocketTile__GCB0,
-logic__3774: FPU__GB2,
-reg__740: RocketTile__GCB0,
-logic__7793: VCU118RocketSystem__GC0,
-case__1010: VCU118RocketSystem__GC0,
-ram_2x123: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__175: VCU118RocketSystem__GC0,
-reg__602: FPU__GB2,
-logic__2078: RocketTile__GCB0,
-logic__6025: RocketTile__GCB0,
-reg__505: FPU__GB1,
-reg__1128: APBGpsBlock__GC0,
-logic__7404: VCU118RocketSystem__GC0,
-logic__1315: VCU118RocketSystem__GC0,
-logic__3343: FPU__GB1,
-logic__8614: APBGpsBlock__GC0,
-muxpart__193: FPU__GB0,
-reg__545: FPU__GB1,
-logic__53: genesys2_rocket_top__GC0,
-reg__575: FPU__GB1,
-reg__1316: tracking_wrapper,
-logic__7450: VCU118RocketSystem__GC0,
-reg__1035: VCU118RocketSystem__GC0,
-logic__3352: FPU__GB1,
-case__1291: APBGpsBlock__GC0,
-bram__parameterized0: APBGpsBlock__GC0,
-logic__5716: RocketTile__GCB0,
-logic__5038: FPU__GB1,
-datapath__649: tracking_wrapper,
-logic__144: genesys2_rocket_top__GC0,
-reg__861: RocketTile__GCB0,
-logic__2538: RocketTile__GCB0, DCache,
-logic__4872: FPU__GB2,
-datapath__614: APBGpsBlock__GC0,
-case__1237: VCU118RocketSystem__GC0,
-case__354: VCU118RocketSystem__GC0,
-reg__669: RocketTile__GCB0,
-logic__5256: RocketTile__GCB0,
-reg__945: VCU118RocketSystem__GC0,
-case__831: RocketTile__GCB0,
-logic__699: genesys2_rocket_top__GC0,
-logic__6638: RocketTile__GCB0,
-logic__796: VCU118RocketSystem__GC0,
-logic__4704: FPU__GB2,
-logic__8356: APBGpsBlock__GC0,
-reg__1066: VCU118RocketSystem__GC0,
-reg__1304: tracking_wrapper,
-case__1535: APBGpsBlock__GC0,
-logic__320: genesys2_rocket_top__GC0,
-case__652: FPU__GB1,
-logic__3436: FPU__GB1,
-logic__7452: VCU118RocketSystem__GC0,
-reg__523: FPU__GB2,
-logic__3345: FPU__GB1,
-reg__920: VCU118RocketSystem__GC0,
-logic__5584: RocketTile__GCB0,
-logic__5984: RocketTile__GCB0,
-datapath__696: tracking_wrapper,
-case__897: RocketTile__GCB0,
-case__1339: APBGpsBlock__GC0,
-logic__6541: RocketTile__GCB0,
-logic__3338: FPU__GB1,
-datapath__288: RocketTile__GCB0,
-logic__9571: TLToAPB,
-logic__6708: RocketTile__GCB0,
-logic__5383: RocketTile__GCB0,
-reg__291: VCU118RocketSystem__GC0,
-logic__4192: FPU__GB1,
-reg__433: RocketTile__GCB0,
-logic__8176: VCU118RocketSystem__GC0,
-reg__375: DCache,
-reg__1433: VCU118RocketSystem__GC0,
-logic__5017: FPU__GB1,
-case__116: genesys2_rocket_top__GC0,
-logic__1727: VCU118RocketSystem__GC0,
-case__1667: tracking_wrapper,
-logic__3334: FPU__GB1,
-reg__651: FPU__GB1,
-logic__7536: VCU118RocketSystem__GC0,
-case__347: VCU118RocketSystem__GC0,
-case__303: VCU118RocketSystem__GC0,
-logic__1336: VCU118RocketSystem__GC0,
-datapath__598: APBGpsBlock__GC0,
-logic__9402: tracking_wrapper,
-reg__526: FPU__GB2,
-logic__9567: APBGpsBlock__GC0,
-reg__750: RocketTile__GCB0,
-case__853: RocketTile__GCB0,
-dsp48e1__27: APBGpsBlock__GC0,
-case__253: VCU118RocketSystem__GC0,
-case__1537: tracking_wrapper,
-datapath__686: tracking_wrapper,
-logic__8207: VCU118RocketSystem__GC0,
-logic__4584: FPU__GB2, FPU__GB1,
-case__1364: APBGpsBlock__GC0,
-logic__7287: VCU118RocketSystem__GC0,
-logic__5146: RocketTile__GCB0,
-logic__6610: RocketTile__GCB0,
-logic__7422: VCU118RocketSystem__GC0,
-logic__1502: VCU118RocketSystem__GC0,
-logic__7286: VCU118RocketSystem__GC0,
-case__469: VCU118RocketSystem__GC0,
-logic__4392: FPU__GB1,
-reg__376: DCache,
-logic__1211: VCU118RocketSystem__GC0,
-reg__659: FPU__GB1,
-logic__3864: FPU__GB2,
-logic__2011: VCU118RocketSystem__GC0,
-logic__5514: RocketTile__GCB0,
-datapath__342: FPU__GB2,
-reg__1215: APBGpsBlock__GC0,
-datapath__397: FPU__GB2,
-case__1093: VCU118RocketSystem__GC0,
-logic__7700: VCU118RocketSystem__GC0,
-logic__7025: VCU118RocketSystem__GC0,
-case__1419: APBGpsBlock__GC0,
-logic__6074: RocketTile__GCB0,
-logic__5458: RocketTile__GCB0,
-datapath__219: VCU118RocketSystem__GC0,
-regfile_32x65: FPU__GB0,
-logic__7498: VCU118RocketSystem__GC0,
-datapath__625: APBGpsBlock__GC0,
-logic__4445: FPU__GB1,
-reg__857: RocketTile__GCB0,
-reg__821: RocketTile__GCB0,
-logic__1789: VCU118RocketSystem__GC0,
-case__435: VCU118RocketSystem__GC0,
-logic__3987: FPU__GB2,
-datapath__659: tracking_wrapper,
-datapath__115: VCU118RocketSystem__GC0,
-datapath__40: VCU118RocketSystem__GC0,
-logic__2155: DCache,
-reg__1088: APBGpsBlock__GC0, tracking_wrapper,
-logic__561: genesys2_rocket_top__GC0,
-reg__1001: VCU118RocketSystem__GC0,
-ClockGroup: VCU118RocketSystem__GC0,
-logic__3509: FPU__GB1,
-reg__290: VCU118RocketSystem__GC0,
-case__1085: VCU118RocketSystem__GC0,
-logic__5016: FPU__GB1,
-TLAtomicAutomata_pbus: VCU118RocketSystem__GC0,
-datapath__706: tracking_wrapper,
-counter__34: VCU118RocketSystem__GC0,
-logic__6941: VCU118RocketSystem__GC0,
-logic__4066: FPU__GB2,
-datapath__482: RocketTile__GCB0,
-reg__826: RocketTile__GCB0,
-logic__7365: VCU118RocketSystem__GC0,
-logic__1127: VCU118RocketSystem__GC0,
-logic__8083: VCU118RocketSystem__GC0,
-case__249: VCU118RocketSystem__GC0,
-reg__583: FPU__GB2,
-reg__277: VCU118RocketSystem__GC0,
-reg__1098: APBGpsBlock__GC0,
-logic__3888: FPU__GB2,
-datapath__460: RocketTile__GCB0,
-case__1234: VCU118RocketSystem__GC0,
-logic__6690: RocketTile__GCB0,
-logic__4078: FPU__GB2,
-reg__694: RocketTile__GCB0,
-case__476: VCU118RocketSystem__GC0,
-logic__8662: APBGpsBlock__GC0,
-dual_port_bram: APBGpsBlock__GC0,
-case__1744: TLToAPB,
-datapath__666: tracking_wrapper,
-IBuf: RocketTile__GCB0,
-logic__2045: VCU118RocketSystem__GC0,
-logic__3018: RocketTile__GCB0,
-logic__2374: DCache,
-case__807: FPU__GB1,
-reg__617: FPU__GB1,
-logic__121: genesys2_rocket_top__GC0,
-case__1326: APBGpsBlock__GC0,
-logic__3583: FPU__GB1,
-logic__1142: VCU118RocketSystem__GC0,
-code_loop_discriminator: tracking_wrapper,
-counter__18: APBGpsBlock__GC0,
-logic__6795: VCU118RocketSystem__GC0,
-logic__8953: tracking_wrapper,
-logic__1525: VCU118RocketSystem__GC0,
-RecFNToIN: FPU__GB2,
-logic__3202: RocketTile__GCB0,
-logic__1731: VCU118RocketSystem__GC0,
-reg__895: VCU118RocketSystem__GC0,
-logic__2504: RocketTile__GCB0, DCache,
-reg__232: VCU118RocketSystem__GC0,
-muxpart__226: FPU__GB0,
-case__957: RocketTile__GCB0,
-reg__73: genesys2_rocket_top__GC0,
-logic__8026: VCU118RocketSystem__GC0,
-logic__6295: RocketTile__GCB0,
-logic__8426: APBGpsBlock__GC0,
-reg__652: FPU__GB1,
-logic__7143: VCU118RocketSystem__GC0,
-logic__3344: FPU__GB1,
-case__236: VCU118RocketSystem__GC0,
-reg__204: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-muxpart__65: genesys2_rocket_top__GC0,
-logic__8244: VCU118RocketSystem__GC0,
-reg__471: FPU__GB0,
-logic__880: VCU118RocketSystem__GC0,
-reg__1065: VCU118RocketSystem__GC0,
-datapath__713: TLToAPB,
-logic__4393: FPU__GB1,
-logic__7235: VCU118RocketSystem__GC0,
-datapath__66: VCU118RocketSystem__GC0,
-reg__844: RocketTile__GCB0,
-reg__425: RocketTile__GCB0,
-logic__6609: RocketTile__GCB0,
-logic__7189: VCU118RocketSystem__GC0,
-case__823: RocketTile__GCB0,
-logic__2008: VCU118RocketSystem__GC0,
-datapath__693: tracking_wrapper,
-logic__4362: FPU__GB1,
-datapath__663: tracking_wrapper,
-logic__3756: FPU__GB2,
-muxpart__6: genesys2_rocket_top__GC0,
-logic__8972: tracking_wrapper,
-logic__2872: DCache,
-addsub__1: tracking_wrapper,
-case__1397: APBGpsBlock__GC0,
-logic__8473: APBGpsBlock__GC0,
-muxpart__149: genesys2_rocket_top__GC0,
-logic__253: genesys2_rocket_top__GC0,
-reg__302: VCU118RocketSystem__GC0,
-case__1213: VCU118RocketSystem__GC0,
-reg__324: DCache,
-logic__9270: tracking_wrapper,
-logic__8891: tracking_wrapper,
-logic__6590: RocketTile__GCB0,
-reg__795: RocketTile__GCB0,
-case__892: RocketTile__GCB0,
-datapath__355: FPU__GB2,
-logic__5061: FPU__GB1,
-logic__7039: VCU118RocketSystem__GC0,
-case__1198: VCU118RocketSystem__GC0,
-logic__5473: RocketTile__GCB0,
-case__1640: tracking_wrapper,
-logic__8190: VCU118RocketSystem__GC0,
-case__1076: VCU118RocketSystem__GC0,
-logic__1151: VCU118RocketSystem__GC0,
-logic__3100: RocketTile__GCB0,
-logic__4462: FPU__GB1,
-logic__3891: FPU__GB2,
-datapath__192: VCU118RocketSystem__GC0,
-case__317: VCU118RocketSystem__GC0,
-logic__5491: RocketTile__GCB0,
-logic__618: genesys2_rocket_top__GC0,
-case__129: genesys2_rocket_top__GC0,
-case__1035: VCU118RocketSystem__GC0,
-case__719: FPU__GB1,
-ifft_abs_sqr: APBGpsBlock__GC0,
-logic__5925: RocketTile__GCB0,
-logic__5993: RocketTile__GCB0,
-logic__1308: VCU118RocketSystem__GC0,
-logic__243: genesys2_rocket_top__GC0,
-reg__1368: tracking_wrapper,
-logic__183: genesys2_rocket_top__GC0,
-datapath__603: APBGpsBlock__GC0,
-dsp48e1__2: APBGpsBlock__GC0,
-reg__493: FPU__GB1,
-ClockCrossingReg_w55: VCU118RocketSystem__GC0,
-logic__7598: VCU118RocketSystem__GC0,
-reg__535: FPU__GB2,
-reg__824: RocketTile__GCB0,
-muxpart__261: RocketTile__GCB0,
-logic__7357: VCU118RocketSystem__GC0,
-logic__1521: VCU118RocketSystem__GC0,
-logic__5937: RocketTile__GCB0,
-logic__3463: FPU__GB1,
-logic__4409: FPU__GB1,
-muxpart__33: genesys2_rocket_top__GC0,
-logic__1819: VCU118RocketSystem__GC0,
-logic__1426: VCU118RocketSystem__GC0,
-logic__8674: APBGpsBlock__GC0,
-logic__8107: VCU118RocketSystem__GC0,
-logic__7690: VCU118RocketSystem__GC0,
-logic__7366: VCU118RocketSystem__GC0,
-case__294: VCU118RocketSystem__GC0,
-logic__8963: tracking_wrapper,
-case__1151: VCU118RocketSystem__GC0,
-reg__403: RocketTile__GCB0,
-logic__6946: VCU118RocketSystem__GC0,
-reg__93: genesys2_rocket_top__GC0,
-logic__4916: FPU__GB2,
-logic__7267: VCU118RocketSystem__GC0,
-reg__1387: tracking_wrapper,
-reg__690: RocketTile__GCB0,
-reg__87: genesys2_rocket_top__GC0,
-datapath__499: VCU118RocketSystem__GC0,
-logic__1569: VCU118RocketSystem__GC0,
-case__296: VCU118RocketSystem__GC0,
-datapath__390: FPU__GB2,
-case__366: VCU118RocketSystem__GC0,
-reg__712: RocketTile__GCB0,
-datapath__323: FPU__GB2, FPU__GB1,
-case__1421: APBGpsBlock__GC0,
-datapath__471: RocketTile__GCB0,
-logic__6022: RocketTile__GCB0,
-reg__953: VCU118RocketSystem__GC0,
-logic__1359: VCU118RocketSystem__GC0,
-logic__3473: FPU__GB1,
-logic__1924: VCU118RocketSystem__GC0,
-datapath__684: tracking_wrapper,
-case__1381: APBGpsBlock__GC0,
-keep__4: genesys2_rocket_top__GC0,
-case__1114: VCU118RocketSystem__GC0,
-datapath__527: VCU118RocketSystem__GC0,
-case__1637: tracking_wrapper,
-logic__1696: VCU118RocketSystem__GC0,
-datapath__331: FPU__GB2,
-case__1188: VCU118RocketSystem__GC0,
-logic__4815: FPU__GB2,
-dsp48e1__18: APBGpsBlock__GC0,
-TLInterconnectCoupler_sbus_from_rockettile: VCU118RocketSystem__GC0,
-logic__9200: tracking_wrapper,
-logic__2684: DCache,
-logic__9386: tracking_wrapper,
-logic__9428: tracking_wrapper,
-logic__5992: RocketTile__GCB0,
-muxpart__152: genesys2_rocket_top__GC0,
-logic__7742: VCU118RocketSystem__GC0,
-case__846: RocketTile__GCB0,
-reg__1006: VCU118RocketSystem__GC0,
-case__376: VCU118RocketSystem__GC0,
-reg__1407: tracking_wrapper,
-reg__850: RocketTile__GCB0,
-logic__2178: DCache,
-logic__4410: FPU__GB1,
-reg__274: VCU118RocketSystem__GC0,
-case__8: genesys2_rocket_top__GC0,
-logic__7243: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_cbus_to_rockettile: VCU118RocketSystem__GC0,
-case__1394: APBGpsBlock__GC0,
-datapath__474: RocketTile__GCB0,
-logic__4424: FPU__GB1,
-logic__5703: RocketTile__GCB0,
-logic__6530: RocketTile__GCB0,
-counter__33: tracking_wrapper,
-logic__3983: FPU__GB2,
-case__1691: tracking_wrapper,
-reg__387: RocketTile__GCB0,
-logic__5705: RocketTile__GCB0,
-logic__9354: tracking_wrapper,
-reg__1147: APBGpsBlock__GC0,
-logic__86: genesys2_rocket_top__GC0,
-datapath__193: VCU118RocketSystem__GC0,
-muxpart__70: genesys2_rocket_top__GC0,
-case__883: RocketTile__GCB0,
-logic__1191: VCU118RocketSystem__GC0,
-logic__7844: VCU118RocketSystem__GC0,
-case__1157: VCU118RocketSystem__GC0,
-logic__7588: VCU118RocketSystem__GC0,
-logic__5939: RocketTile__GCB0,
-reg__1266: tracking_wrapper,
-CLINTClockSinkDomain: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a28d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__6606: RocketTile__GCB0,
-logic__4426: FPU__GB1,
-case__704: FPU__GB1,
-case__1163: VCU118RocketSystem__GC0,
-logic__9440: tracking_wrapper,
-dsp48e1__40: tracking_wrapper,
-logic__6924: VCU118RocketSystem__GC0,
-reg__360: DCache,
-logic__6729: TilePRCIDomain__GC0,
-logic__8699: APBGpsBlock__GC0,
-case__1183: VCU118RocketSystem__GC0,
-case__518: DCache,
-logic__1265: VCU118RocketSystem__GC0,
-BreakpointUnit: RocketTile__GCB0,
-case__689: FPU__GB2,
-logic__5706: RocketTile__GCB0,
-logic__5909: RocketTile__GCB0,
-logic__2968: RocketTile__GCB0,
-logic__7269: VCU118RocketSystem__GC0,
-logic__7066: VCU118RocketSystem__GC0,
-logic__3631: FPU__GB2, FPU__GB1,
-logic__9026: tracking_wrapper,
-logic__5789: RocketTile__GCB0,
-logic__3926: FPU__GB2,
-case__1396: APBGpsBlock__GC0,
-logic__4980: FPU__GB1,
-PLICFanIn: VCU118RocketSystem__GC0,
-logic__9298: tracking_wrapper,
-logic__9081: tracking_wrapper,
-dsp48e1__37: tracking_wrapper,
-reg__319: RocketTile__GCB0,
-reg__598: FPU__GB2,
-logic__8265: VCU118RocketSystem__GC0,
-logic__1166: VCU118RocketSystem__GC0,
-case__6: genesys2_rocket_top__GC0,
-logic__8302: VCU118RocketSystem__GC0,
-logic__1647: VCU118RocketSystem__GC0,
-reg__866: TilePRCIDomain__GC0,
-double_ff_syn: APBGpsBlock__GC0, tracking_wrapper,
-logic__5793: RocketTile__GCB0,
-datapath__266: DCache,
-logic__2199: DCache,
-logic__6287: RocketTile__GCB0,
-RoundAnyRawFNToRecFN_2: FPU__GB2,
-reg__1361: tracking_wrapper,
-logic__293: genesys2_rocket_top__GC0,
-logic__4873: FPU__GB2,
-case__1526: APBGpsBlock__GC0,
-case__473: VCU118RocketSystem__GC0,
-logic__4412: FPU__GB1,
-logic__5386: RocketTile__GCB0,
-logic__3812: FPU__GB2,
-logic__5571: RocketTile__GCB0,
-logic__6017: RocketTile__GCB0,
-case__774: FPU__GB1,
-logic__3341: FPU__GB1,
-logic__5244: RocketTile__GCB0,
-reg__1119: APBGpsBlock__GC0,
-logic__5446: RocketTile__GCB0,
-case__1267: APBGpsBlock__GC0,
-datapath__664: tracking_wrapper,
-reg__691: RocketTile__GCB0,
-logic__5385: RocketTile__GCB0,
-logic__5657: RocketTile__GCB0,
-case__1586: tracking_wrapper,
-case__492: RocketTile__GCB0,
-reg__117: VCU118RocketSystem__GC0,
-logic__6176: RocketTile__GCB0,
-reg__1289: tracking_wrapper,
-logic__9077: tracking_wrapper,
-logic__1590: VCU118RocketSystem__GC0,
-muxpart__191: FPU__GB0,
-logic__5942: RocketTile__GCB0,
-logic__4062: FPU__GB2,
-reg__296: VCU118RocketSystem__GC0,
-logic__2060: VCU118RocketSystem__GC0,
-logic__1233: VCU118RocketSystem__GC0,
-logic__9608: genesys2_rocket_top__GC0,
-case__960: RocketTile__GCB0,
-case__990: VCU118RocketSystem__GC0,
-logic__1666: VCU118RocketSystem__GC0,
-reg__825: RocketTile__GCB0,
-case__788: FPU__GB1,
-logic__3349: FPU__GB1,
-reg__19: genesys2_rocket_top__GC0,
-logic__1149: VCU118RocketSystem__GC0,
-reg__1340: tracking_wrapper,
-logic__6124: RocketTile__GCB0,
-logic__4463: FPU__GB1,
-reg__30: genesys2_rocket_top__GC0,
-reg__1082: VCU118RocketSystem__GC0,
-logic__8863: APBGpsBlock__GC0,
-case__1030: VCU118RocketSystem__GC0,
-case__624: RocketTile__GCB0,
-logic__7290: VCU118RocketSystem__GC0,
-datapath__51: VCU118RocketSystem__GC0,
-logic__56: genesys2_rocket_top__GC0,
-case__1016: VCU118RocketSystem__GC0,
-reg__758: RocketTile__GCB0,
-logic__3135: RocketTile__GCB0,
-logic__3620: FPU__GB2, FPU__GB1,
-datapath__155: VCU118RocketSystem__GC0,
-logic__3257: RocketTile__GCB0,
-case__684: FPU__GB2,
-case__1648: tracking_wrapper,
-logic__8138: VCU118RocketSystem__GC0,
-logic__7979: VCU118RocketSystem__GC0,
-logic__3755: FPU__GB2,
-datapath__257: VCU118RocketSystem__GC0,
-logic__3915: FPU__GB2,
-reg__742: RocketTile__GCB0,
-reg__611: FPU__GB2,
-logic__124: genesys2_rocket_top__GC0,
-datapath__310: FPU__GB1,
-reg__726: RocketTile__GCB0,
-reg__1309: tracking_wrapper,
-case__720: FPU__GB1,
-reg__1201: APBGpsBlock__GC0,
-logic__6035: RocketTile__GCB0,
-logic__7193: VCU118RocketSystem__GC0,
-logic__4700: FPU__GB2,
-datapath__14: genesys2_rocket_top__GC0,
-logic__3430: FPU__GB1,
-reg__407: RocketTile__GCB0,
-case__901: RocketTile__GCB0,
-case__1738: TLToAPB,
-case__1649: tracking_wrapper,
-logic__4038: FPU__GB2,
-logic__4439: FPU__GB1,
-logic__8869: APBGpsBlock__GC0,
-extram__5: APBGpsBlock__GC0,
-reg__1378: tracking_wrapper,
-logic__7597: VCU118RocketSystem__GC0,
-muxpart__238: FPU__GB1,
-logic__2672: DCache,
-TLFragmenter_CLINT: VCU118RocketSystem__GC0,
-case__629: RocketTile__GCB0,
-Queue2_TLBundleD_a32d8s1k1z4u: VCU118RocketSystem__GC0,
-datapath__116: VCU118RocketSystem__GC0,
-logic__9446: tracking_wrapper,
-logic__2556: DCache,
-logic__5483: RocketTile__GCB0,
-logic__8050: VCU118RocketSystem__GC0,
-logic__1522: VCU118RocketSystem__GC0,
-reg__715: RocketTile__GCB0,
-logic__2825: DCache,
-case__857: RocketTile__GCB0,
-logic__8901: tracking_wrapper,
-muxpart__29: genesys2_rocket_top__GC0,
-logic__6619: RocketTile__GCB0,
-case__2: genesys2_rocket_top__GC0,
-logic__795: VCU118RocketSystem__GC0,
-datapath__383: FPU__GB2, FPU__GB1,
-datapath__387: FPU__GB2,
-logic__2943: DCache,
-reg__872: VCU118RocketSystem__GC0,
-datapath__442: RocketTile__GCB0,
-logic__5930: RocketTile__GCB0,
-datapath__239: VCU118RocketSystem__GC0,
-butterfly__parameterized1: APBGpsBlock__GC0,
-logic__5599: RocketTile__GCB0,
-case__909: RocketTile__GCB0,
-datapath__352: FPU__GB2,
-reg__190: VCU118RocketSystem__GC0,
-case__1134: VCU118RocketSystem__GC0,
-logic__7431: VCU118RocketSystem__GC0,
-case__379: VCU118RocketSystem__GC0,
-logic__3516: FPU__GB1,
-case__764: FPU__GB2,
-logic__3107: RocketTile__GCB0,
-logic__3448: FPU__GB1,
-logic__5618: RocketTile__GCB0,
-logic__4050: FPU__GB2,
-logic__4380: FPU__GB1,
-logic__1850: VCU118RocketSystem__GC0,
-reg__142: VCU118RocketSystem__GC0,
-case__1666: tracking_wrapper,
-addsub__4: tracking_wrapper,
-logic__8567: APBGpsBlock__GC0,
-logic__2687: DCache,
-reg__94: genesys2_rocket_top__GC0,
-case__438: VCU118RocketSystem__GC0,
-case__355: VCU118RocketSystem__GC0,
-datapath__75: VCU118RocketSystem__GC0,
-datapath__519: VCU118RocketSystem__GC0,
-logic__8816: APBGpsBlock__GC0,
-logic__3617: FPU__GB2, FPU__GB1,
-logic__1946: VCU118RocketSystem__GC0,
-reg__570: FPU__GB1,
-reg__1171: APBGpsBlock__GC0,
-logic__4310: FPU__GB1,
-logic__1393: VCU118RocketSystem__GC0,
-case__334: VCU118RocketSystem__GC0,
-logic__5384: RocketTile__GCB0,
-logic__4862: FPU__GB2,
-logic__875: VCU118RocketSystem__GC0,
-logic__4117: FPU__GB2,
-logic__9062: tracking_wrapper,
-logic__1715: VCU118RocketSystem__GC0,
-case__1071: VCU118RocketSystem__GC0,
-datapath__159: VCU118RocketSystem__GC0,
-reg__419: RocketTile__GCB0,
-muxpart__47: genesys2_rocket_top__GC0,
-datapath__62: VCU118RocketSystem__GC0,
-VCU118RocketSystem__GC0: VCU118RocketSystem__GC0,
-logic__2415: DCache,
-case__1473: APBGpsBlock__GC0,
-logic__149: genesys2_rocket_top__GC0,
-muxpart__262: RocketTile__GCB0,
-reg__239: VCU118RocketSystem__GC0,
-logic__5033: FPU__GB1,
-case__971: RocketTile__GCB0,
-logic__3979: FPU__GB2,
-reg__393: RocketTile__GCB0,
-reg__273: VCU118RocketSystem__GC0,
-reg__753: RocketTile__GCB0,
-logic__6719: RocketTile__GCB0,
-logic__4708: FPU__GB2,
-case__1229: VCU118RocketSystem__GC0,
-datapath__384: FPU__GB2, FPU__GB1,
-case__760: FPU__GB2,
-datapath__456: RocketTile__GCB0,
-logic__649: genesys2_rocket_top__GC0,
-logic__641: genesys2_rocket_top__GC0,
-logic__1783: VCU118RocketSystem__GC0,
-datapath__135: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__791: RocketTile__GCB0,
-reg__757: RocketTile__GCB0,
-case__1650: tracking_wrapper,
-reg__574: FPU__GB1,
-case__1305: APBGpsBlock__GC0,
-case__787: FPU__GB1,
-case__1337: APBGpsBlock__GC0,
-case__972: RocketTile__GCB0,
-case__1184: VCU118RocketSystem__GC0,
-logic__9441: tracking_wrapper,
-logic__2489: RocketTile__GCB0, DCache,
-IntSyncCrossingSource_n1x2: VCU118RocketSystem__GC0,
-reg__402: RocketTile__GCB0,
-case__1: genesys2_rocket_top__GC0,
-logic__5861: RocketTile__GCB0,
-datapath__277: DCache,
-case__697: FPU__GB2,
-case__949: RocketTile__GCB0,
-logic__1: genesys2_rocket_top__GC0,
-case__410: VCU118RocketSystem__GC0,
-logic__2522: RocketTile__GCB0, DCache,
-logic__7609: VCU118RocketSystem__GC0,
-case__1474: APBGpsBlock__GC0,
-reg__265: VCU118RocketSystem__GC0,
-logic__5340: RocketTile__GCB0,
-case__1194: VCU118RocketSystem__GC0,
-logic__4397: FPU__GB1,
-logic__7877: VCU118RocketSystem__GC0,
-reg__716: RocketTile__GCB0,
-logic__9382: tracking_wrapper,
-logic__8038: VCU118RocketSystem__GC0,
-logic__7005: VCU118RocketSystem__GC0,
-datapath__328: FPU__GB2,
-case__1179: VCU118RocketSystem__GC0,
-datapath__676: tracking_wrapper,
-case__1062: VCU118RocketSystem__GC0,
-logic__4929: FPU__GB1,
-reg__90: genesys2_rocket_top__GC0,
-logic__4977: FPU__GB1,
-logic__2861: DCache,
-logic__6838: VCU118RocketSystem__GC0,
-logic__794: VCU118RocketSystem__GC0,
-logic__7053: VCU118RocketSystem__GC0,
-reg__225: VCU118RocketSystem__GC0,
-logic__8960: tracking_wrapper,
-logic__233: genesys2_rocket_top__GC0,
-cdc_fifo_gray_dst: tracking_wrapper,
-reg__814: RocketTile__GCB0,
-reg__223: VCU118RocketSystem__GC0,
-logic__1973: VCU118RocketSystem__GC0,
-logic__2063: RocketTile__GCB0,
-reg__881: VCU118RocketSystem__GC0,
-logic__6627: RocketTile__GCB0,
-reg__621: FPU__GB1,
-logic__5032: FPU__GB1,
-logic__1125: VCU118RocketSystem__GC0,
-reg__205: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2315: DCache,
-logic__3885: FPU__GB2,
-datapath__609: APBGpsBlock__GC0,
-case__1287: APBGpsBlock__GC0,
-case__876: RocketTile__GCB0,
-case__493: RocketTile__GCB0,
-logic__3599: FPU__GB2, FPU__GB1,
-reg__217: VCU118RocketSystem__GC0,
-logic__2894: DCache,
-logic__7991: VCU118RocketSystem__GC0,
-reg__152: VCU118RocketSystem__GC0,
-logic__4384: FPU__GB1,
-case__1681: tracking_wrapper,
-case__205: genesys2_rocket_top__GC0,
-reg__180: VCU118RocketSystem__GC0,
-datapath__63: VCU118RocketSystem__GC0,
-logic__7864: VCU118RocketSystem__GC0,
-logic__1079: VCU118RocketSystem__GC0,
-reg__467: FPU__GB0,
-TLBusBypass: VCU118RocketSystem__GC0,
-logic__3635: FPU__GB2, FPU__GB1,
-reg__568: FPU__GB1,
-logic__3978: FPU__GB2,
-logic__1303: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__832: RocketTile__GCB0,
-muxpart__174: FPU__GB0,
-datapath__704: tracking_wrapper,
-reg__1229: tracking_wrapper,
-logic__6511: RocketTile__GCB0,
-RoundAnyRawFNToRecFN_3: FPU__GB1,
-logic__2746: DCache,
-logic__2898: DCache,
-logic__399: genesys2_rocket_top__GC0,
-case__1247: VCU118RocketSystem__GC0,
-reg__438: RocketTile__GCB0,
-extrom: APBGpsBlock__GC0,
-Queue2_TLBundleD_a29d64s2k1z3u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__639: genesys2_rocket_top__GC0,
-logic__5125: FPU__GB1,
-logic__7826: VCU118RocketSystem__GC0,
-logic__5798: RocketTile__GCB0,
-logic__5028: FPU__GB1,
-logic__7552: VCU118RocketSystem__GC0,
-case__346: VCU118RocketSystem__GC0,
-case__1260: APBGpsBlock__GC0,
-case__219: genesys2_rocket_top__GC0,
-case__951: RocketTile__GCB0,
-reg__1370: tracking_wrapper,
-reg__68: genesys2_rocket_top__GC0,
-case__1219: VCU118RocketSystem__GC0,
-logic__7909: VCU118RocketSystem__GC0,
-case__1018: VCU118RocketSystem__GC0,
-logic__1355: VCU118RocketSystem__GC0,
-FPToFP: FPU__GB1,
-case__617: RocketTile__GCB0,
-muxpart__35: genesys2_rocket_top__GC0,
-logic__7933: VCU118RocketSystem__GC0,
-logic__1405: VCU118RocketSystem__GC0,
-bram: APBGpsBlock__GC0,
-muxpart__150: genesys2_rocket_top__GC0,
-logic__7058: VCU118RocketSystem__GC0,
-logic__972: VCU118RocketSystem__GC0,
-logic__2781: DCache,
-reg__322: DCache,
-case__1627: tracking_wrapper,
-mult_30_25_55: tracking_wrapper,
-logic__7564: VCU118RocketSystem__GC0,
-logic__1833: VCU118RocketSystem__GC0,
-logic__5320: RocketTile__GCB0,
-logic__7368: VCU118RocketSystem__GC0,
-case__844: RocketTile__GCB0,
-logic__6840: VCU118RocketSystem__GC0,
-reg__390: RocketTile__GCB0,
-logic__8516: APBGpsBlock__GC0,
-reg__165: VCU118RocketSystem__GC0,
-reg__663: FPU__GB1,
-reg__637: FPU__GB1,
-reg__224: VCU118RocketSystem__GC0,
-logic__5931: RocketTile__GCB0,
-logic__2671: DCache,
-logic__8696: APBGpsBlock__GC0,
-Repeater_TLBundleA_a29d64s2k1z3u_2: VCU118RocketSystem__GC0,
-logic__5593: RocketTile__GCB0,
-muxpart__243: FPU__GB1,
-logic__1468: VCU118RocketSystem__GC0,
-case__1075: VCU118RocketSystem__GC0,
-logic__5142: RocketTile__GCB0,
-logic__1906: VCU118RocketSystem__GC0,
-datapath__710: tracking_wrapper,
-logic__4375: FPU__GB1,
-case__191: genesys2_rocket_top__GC0,
-logic__7299: VCU118RocketSystem__GC0,
-case__367: VCU118RocketSystem__GC0,
-datapath__687: tracking_wrapper,
-logic__8090: VCU118RocketSystem__GC0,
-reg__888: VCU118RocketSystem__GC0,
-case__391: VCU118RocketSystem__GC0,
-case__770: FPU__GB1,
-logic__2367: DCache,
-reg__977: VCU118RocketSystem__GC0,
-logic__9216: tracking_wrapper,
-datapath__529: VCU118RocketSystem__GC0,
-logic__9314: tracking_wrapper,
-reg__571: FPU__GB1,
-reg__1103: APBGpsBlock__GC0,
-logic__2225: DCache,
-logic__1588: VCU118RocketSystem__GC0,
-logic__1481: VCU118RocketSystem__GC0,
-logic__7000: VCU118RocketSystem__GC0,
-case__672: FPU__GB2,
-logic__1517: VCU118RocketSystem__GC0,
-case__291: VCU118RocketSystem__GC0,
-case__618: RocketTile__GCB0,
-reg__102: genesys2_rocket_top__GC0,
-logic__1235: VCU118RocketSystem__GC0,
-logic__5263: RocketTile__GCB0,
-logic__9274: tracking_wrapper,
-case__1568: tracking_wrapper,
-logic__7401: VCU118RocketSystem__GC0,
-logic__4385: FPU__GB1,
-logic__3904: FPU__GB2,
-logic__8610: APBGpsBlock__GC0,
-datapath__577: APBGpsBlock__GC0,
-logic__6956: VCU118RocketSystem__GC0,
-logic__1841: VCU118RocketSystem__GC0,
-logic__9462: tracking_wrapper,
-logic__1451: VCU118RocketSystem__GC0,
-logic__4459: FPU__GB1,
-reg__721: RocketTile__GCB0,
-logic__1787: VCU118RocketSystem__GC0,
-logic__4480: FPU__GB1,
-logic__2664: DCache,
-logic__3712: FPU__GB2,
-reg__1130: APBGpsBlock__GC0,
-logic__2937: DCache,
-reg__675: RocketTile__GCB0,
-datapath__708: tracking_wrapper,
-logic__9147: tracking_wrapper,
-muxpart__197: FPU__GB0,
-reg__1359: tracking_wrapper,
-case__554: DCache,
-logic__7178: VCU118RocketSystem__GC0,
-logic__4257: FPU__GB1,
-case__433: VCU118RocketSystem__GC0,
-logic__4378: FPU__GB1,
-case__1069: VCU118RocketSystem__GC0,
-datapath__639: APBGpsBlock__GC0,
-logic__5341: RocketTile__GCB0,
-reg__636: FPU__GB1,
-logic__7649: VCU118RocketSystem__GC0,
-logic__1752: VCU118RocketSystem__GC0,
-datapath__68: VCU118RocketSystem__GC0,
-logic__6970: VCU118RocketSystem__GC0,
-logic__5129: FPU__GB1,
-reg__429: RocketTile__GCB0,
-rom__8: tracking_wrapper,
-logic__8666: APBGpsBlock__GC0,
-reg__391: RocketTile__GCB0,
-case__1563: tracking_wrapper,
-logic__5373: RocketTile__GCB0,
-reg__1294: tracking_wrapper,
-logic__1870: VCU118RocketSystem__GC0,
-logic__5625: RocketTile__GCB0,
-logic__3054: RocketTile__GCB0,
-case__52: genesys2_rocket_top__GC0,
-case__798: FPU__GB1,
-logic__3705: FPU__GB2,
-logic__2495: RocketTile__GCB0, DCache,
-logic__8016: VCU118RocketSystem__GC0,
-case__384: VCU118RocketSystem__GC0,
-case__810: FPU__GB1,
-logic__2355: DCache,
-reg__907: VCU118RocketSystem__GC0,
-comp_mult: APBGpsBlock__GC0,
-logic__6646: RocketTile__GCB0,
-logic__4367: FPU__GB1,
-TLFragmenter_Debug: VCU118RocketSystem__GC0,
-datapath__370: FPU__GB1,
-logic__4921: FPU__GB2,
-logic__6352: RocketTile__GCB0,
-logic__1960: VCU118RocketSystem__GC0,
-logic__4390: FPU__GB1,
-case__1621: tracking_wrapper,
-case__964: RocketTile__GCB0,
-logic__7883: VCU118RocketSystem__GC0,
-logic__7458: VCU118RocketSystem__GC0,
-datapath__552: APBGpsBlock__GC0,
-logic__5308: RocketTile__GCB0,
-logic__4914: FPU__GB2,
-datapath__147: VCU118RocketSystem__GC0,
-datapath__141: VCU118RocketSystem__GC0,
-logic__4333: FPU__GB1,
-logic__946: VCU118RocketSystem__GC0,
-logic__4470: FPU__GB1,
-case__940: RocketTile__GCB0,
-logic__7889: VCU118RocketSystem__GC0,
-case__1372: APBGpsBlock__GC0,
-logic__3520: FPU__GB1,
-datapath__514: VCU118RocketSystem__GC0,
-logic__1983: VCU118RocketSystem__GC0,
-logic__4216: FPU__GB1,
-logic__7769: VCU118RocketSystem__GC0,
-logic__2557: DCache,
-reg__460: FPU__GB0,
-TLXbar_cbus_out_i1_o7_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__3172: RocketTile__GCB0,
-logic__6054: RocketTile__GCB0,
-case__1066: VCU118RocketSystem__GC0,
-logic__1117: VCU118RocketSystem__GC0,
-case__29: genesys2_rocket_top__GC0,
-logic__788: VCU118RocketSystem__GC0,
-logic__5621: RocketTile__GCB0,
-reg__51: genesys2_rocket_top__GC0,
-reg__140: VCU118RocketSystem__GC0,
-logic__7825: VCU118RocketSystem__GC0,
-case__1633: tracking_wrapper,
-datapath__12: genesys2_rocket_top__GC0,
-logic__7367: VCU118RocketSystem__GC0,
-case__730: FPU__GB2, FPU__GB1,
-logic__2726: DCache,
-logic__3251: RocketTile__GCB0,
-logic__2585: DCache,
-reg__1427: TLToAPB,
-reg__585: FPU__GB2,
-muxpart__164: DCache,
-case__1711: tracking_wrapper,
-logic__7024: VCU118RocketSystem__GC0,
-datapath__647: tracking_wrapper,
-reg__1382: tracking_wrapper,
-case__676: FPU__GB2,
-logic__8775: APBGpsBlock__GC0,
-case__533: DCache,
-case__745: FPU__GB2,
-logic__363: genesys2_rocket_top__GC0,
-reg__966: VCU118RocketSystem__GC0,
-logic__5928: RocketTile__GCB0,
-logic__3062: RocketTile__GCB0,
-logic__670: genesys2_rocket_top__GC0,
-case__777: FPU__GB1,
-logic__7922: VCU118RocketSystem__GC0,
-logic__3818: FPU__GB2,
-logic__147: genesys2_rocket_top__GC0,
-logic__6773: VCU118RocketSystem__GC0,
-logic__3861: FPU__GB2,
-case__444: VCU118RocketSystem__GC0,
-case__517: DCache,
-plusarg_reader: RocketTile__GCB0,
-muxpart__73: genesys2_rocket_top__GC0,
-case__1612: tracking_wrapper,
-logic__5847: RocketTile__GCB0,
-logic__9401: tracking_wrapper,
-reg__289: VCU118RocketSystem__GC0,
-case__413: VCU118RocketSystem__GC0,
-reg__1425: TLToAPB,
-logic__6110: RocketTile__GCB0,
-logic__4212: FPU__GB1,
-reg__969: VCU118RocketSystem__GC0,
-logic__5381: RocketTile__GCB0,
-logic__4587: FPU__GB2, FPU__GB1,
-logic__5902: RocketTile__GCB0,
-case__460: VCU118RocketSystem__GC0,
-case__778: FPU__GB1,
-logic__60: genesys2_rocket_top__GC0,
-reg__1043: VCU118RocketSystem__GC0,
-logic__9205: tracking_wrapper,
-logic__556: genesys2_rocket_top__GC0,
-case__910: RocketTile__GCB0,
-case__913: RocketTile__GCB0,
-case__1177: VCU118RocketSystem__GC0,
-reg__729: RocketTile__GCB0,
-case__59: genesys2_rocket_top__GC0,
-muxpart__228: FPU__GB0,
-logic__6113: RocketTile__GCB0,
-logic__4590: FPU__GB2, FPU__GB1,
-reg__1107: APBGpsBlock__GC0,
-datapath__568: APBGpsBlock__GC0,
-logic__1385: VCU118RocketSystem__GC0,
-logic__9564: APBGpsBlock__GC0,
-logic__5468: RocketTile__GCB0,
-logic__2395: DCache,
-reg__935: VCU118RocketSystem__GC0,
-case__1569: tracking_wrapper,
-logic__546: genesys2_rocket_top__GC0,
-datapath__486: RocketTile__GCB0,
-reg__138: VCU118RocketSystem__GC0,
-datapath__489: TilePRCIDomain__GC0,
-reg__174: VCU118RocketSystem__GC0,
-case__762: FPU__GB2,
-datapath__502: VCU118RocketSystem__GC0,
-datapath__700: tracking_wrapper,
-logic__7387: VCU118RocketSystem__GC0,
-logic__1167: VCU118RocketSystem__GC0,
-case__1664: tracking_wrapper,
-datapath__531: VCU118RocketSystem__GC0,
-datapath__515: VCU118RocketSystem__GC0,
-logic__2036: VCU118RocketSystem__GC0,
-logic__8017: VCU118RocketSystem__GC0,
-muxpart__229: FPU__GB0,
-logic__6996: VCU118RocketSystem__GC0,
-logic__6661: RocketTile__GCB0,
-case__19: genesys2_rocket_top__GC0,
-reg__1396: tracking_wrapper,
-logic__304: genesys2_rocket_top__GC0,
-logic__2483: RocketTile__GCB0, DCache,
-reg__1049: VCU118RocketSystem__GC0,
-TLWidthWidget8_2: VCU118RocketSystem__GC0,
-case__13: genesys2_rocket_top__GC0,
-case__1591: tracking_wrapper,
-case__780: FPU__GB1,
-logic__7203: VCU118RocketSystem__GC0,
-datapath__673: tracking_wrapper,
-dsp48e1__8: APBGpsBlock__GC0,
-case__866: RocketTile__GCB0,
-TLXbar_dmixbar_i1_o2_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__6745: VCU118RocketSystem__GC0,
-logic__1121: VCU118RocketSystem__GC0,
-logic__3582: FPU__GB1,
-reg__1346: tracking_wrapper,
-logic__7672: VCU118RocketSystem__GC0,
-logic__1839: VCU118RocketSystem__GC0,
-logic__8365: APBGpsBlock__GC0,
-reg__718: RocketTile__GCB0,
-case__1708: tracking_wrapper,
-logic__9524: APBGpsBlock__GC0,
-logic__5922: RocketTile__GCB0,
-reg__210: VCU118RocketSystem__GC0,
-reg__620: FPU__GB1,
-reg__469: FPU__GB0,
-reg__775: RocketTile__GCB0,
-case__865: RocketTile__GCB0,
-reg__894: VCU118RocketSystem__GC0,
-datapath__422: RocketTile__GCB0,
-case__1686: tracking_wrapper,
-keep__10: APBGpsBlock__GC0, tracking_wrapper,
-reg__231: VCU118RocketSystem__GC0,
-logic__3576: FPU__GB1,
-datapath__386: FPU__GB1,
-dsp48e1__41: tracking_wrapper,
-logic__719: genesys2_rocket_top__GC0,
-case__943: RocketTile__GCB0,
-eth_rf_core: genesys2_rocket_top__GC0,
-logic__7041: VCU118RocketSystem__GC0,
-logic__6125: RocketTile__GCB0,
-logic__5704: RocketTile__GCB0,
-case__593: RocketTile__GCB0,
-reg__436: RocketTile__GCB0,
-logic__9034: tracking_wrapper,
-reg__738: RocketTile__GCB0,
-muxpart__380: tracking_wrapper,
-muxpart__368: tracking_wrapper,
-logic__5507: RocketTile__GCB0,
-datapath__290: RocketTile__GCB0,
-datapath__311: FPU__GB1,
-logic__2749: DCache,
-logic__2566: DCache,
-logic__392: genesys2_rocket_top__GC0,
-case__1187: VCU118RocketSystem__GC0,
-logic__7604: VCU118RocketSystem__GC0,
-datapath__132: VCU118RocketSystem__GC0,
-logic__6501: RocketTile__GCB0,
-logic__5486: RocketTile__GCB0,
-reg__67: genesys2_rocket_top__GC0,
-logic__7430: VCU118RocketSystem__GC0,
-logic__2683: DCache,
-case__710: FPU__GB1,
-logic__2498: RocketTile__GCB0, DCache,
-TLInterconnectCoupler_cbus_to_debug: VCU118RocketSystem__GC0,
-case__371: VCU118RocketSystem__GC0,
-reg__27: genesys2_rocket_top__GC0,
-reg__377: RocketTile__GCB0,
-NCO_carr: tracking_wrapper,
-case__561: DCache,
-logic__7446: VCU118RocketSystem__GC0,
-reg__49: genesys2_rocket_top__GC0,
-logic__5267: RocketTile__GCB0,
-PMAChecker: RocketTile__GCB0, DCache,
-datapath__120: VCU118RocketSystem__GC0,
-logic__845: VCU118RocketSystem__GC0,
-case__1740: TLToAPB,
-case__826: RocketTile__GCB0,
-case__660: FPU__GB2, FPU__GB1,
-reg__1132: APBGpsBlock__GC0,
-muxpart__179: FPU__GB0,
-logic__6750: VCU118RocketSystem__GC0,
-datapath__279: DCache,
-logic__4116: FPU__GB2,
-reg__565: FPU__GB1,
-logic__7967: VCU118RocketSystem__GC0,
-datapath__465: RocketTile__GCB0,
-logic__5482: RocketTile__GCB0,
-logic__9526: APBGpsBlock__GC0,
-logic__4556: FPU__GB2, FPU__GB1,
-case__487: VCU118RocketSystem__GC0,
-logic__4769: FPU__GB2,
-logic__373: genesys2_rocket_top__GC0,
-logic__1660: VCU118RocketSystem__GC0,
-logic__5550: RocketTile__GCB0,
-counter__4: genesys2_rocket_top__GC0,
-reg__498: FPU__GB1,
-case__1161: VCU118RocketSystem__GC0,
-reg__1367: tracking_wrapper,
-logic__3558: FPU__GB1,
-logic__6333: RocketTile__GCB0,
-logic__7610: VCU118RocketSystem__GC0,
-muxpart__25: genesys2_rocket_top__GC0,
-logic__881: VCU118RocketSystem__GC0,
-logic__3427: FPU__GB1,
-datapath__677: tracking_wrapper,
-logic__5915: RocketTile__GCB0,
-logic__1648: VCU118RocketSystem__GC0,
-logic__1459: VCU118RocketSystem__GC0,
-case__1144: VCU118RocketSystem__GC0,
-logic__3038: RocketTile__GCB0,
-logic__1200: VCU118RocketSystem__GC0,
-logic__2560: DCache,
-logic__7032: VCU118RocketSystem__GC0,
-logic__4305: FPU__GB1,
-logic__6868: VCU118RocketSystem__GC0,
-logic__4396: FPU__GB1,
-reg__1255: tracking_wrapper,
-reg__399: RocketTile__GCB0,
-datapath__606: APBGpsBlock__GC0,
-logic__8184: VCU118RocketSystem__GC0,
-logic__5850: RocketTile__GCB0,
-logic__4909: FPU__GB2,
-logic__2565: DCache,
-logic__7087: VCU118RocketSystem__GC0,
-muxpart__36: genesys2_rocket_top__GC0,
-reg__627: FPU__GB1,
-logic__6042: RocketTile__GCB0,
-reg__209: VCU118RocketSystem__GC0,
-logic__8048: VCU118RocketSystem__GC0,
-logic__5434: RocketTile__GCB0,
-reg__1411: tracking_wrapper,
-logic__4936: FPU__GB1,
-reg__1076: VCU118RocketSystem__GC0,
-logic__7454: VCU118RocketSystem__GC0,
-case__953: RocketTile__GCB0,
-case__1296: APBGpsBlock__GC0,
-case__552: DCache,
-case__1555: tracking_wrapper,
-logic__5366: RocketTile__GCB0,
-logic__1161: VCU118RocketSystem__GC0,
-logic__1871: VCU118RocketSystem__GC0,
-reg__787: RocketTile__GCB0,
-reg__852: RocketTile__GCB0,
-logic__1942: VCU118RocketSystem__GC0,
-muxpart__236: FPU__GB0,
-logic__6633: RocketTile__GCB0,
-reg__14: genesys2_rocket_top__GC0,
-case__836: RocketTile__GCB0,
-logic__7679: VCU118RocketSystem__GC0,
-logic__4913: FPU__GB2,
-datapath__712: tracking_wrapper,
-case__1227: VCU118RocketSystem__GC0,
-datapath__182: VCU118RocketSystem__GC0,
-logic__2762: DCache,
-logic__2812: DCache,
-case__568: DCache,
-logic__985: VCU118RocketSystem__GC0,
-logic__1262: VCU118RocketSystem__GC0,
-case__120: genesys2_rocket_top__GC0,
-logic__5079: FPU__GB1,
-rockettile_dcache_data_arrays_0_131072x64: DCache,
-logic__8013: VCU118RocketSystem__GC0,
-logic__1662: VCU118RocketSystem__GC0,
-logic__1600: VCU118RocketSystem__GC0,
-datapath__431: RocketTile__GCB0,
-logic__494: genesys2_rocket_top__GC0,
-muxpart__217: FPU__GB0,
-logic__5448: RocketTile__GCB0,
-logic__3437: FPU__GB1,
-IntSyncSyncCrossingSink_n1x1: TilePRCIDomain__GC0,
-reg__1020: VCU118RocketSystem__GC0,
-logic__7756: VCU118RocketSystem__GC0,
-logic__1880: VCU118RocketSystem__GC0,
-logic__7705: VCU118RocketSystem__GC0,
-logic__1388: VCU118RocketSystem__GC0,
-logic__8202: VCU118RocketSystem__GC0,
-reg__1196: APBGpsBlock__GC0,
-case__636: RocketTile__GCB0,
-gray_to_binary: tracking_wrapper,
-reg__868: TilePRCIDomain__GC0,
-logic__513: genesys2_rocket_top__GC0,
-logic__1599: VCU118RocketSystem__GC0,
-logic__1261: VCU118RocketSystem__GC0,
-logic__5744: RocketTile__GCB0,
-logic__1283: VCU118RocketSystem__GC0,
-logic__2621: DCache,
-logic__4853: FPU__GB2,
-case__1544: tracking_wrapper,
-logic__5696: RocketTile__GCB0,
-logic__1177: VCU118RocketSystem__GC0,
-logic__2139: RocketTile__GCB0,
-reg__482: FPU__GB0,
-logic__7762: VCU118RocketSystem__GC0,
-logic__4381: FPU__GB1,
-logic__229: genesys2_rocket_top__GC0,
-case__295: VCU118RocketSystem__GC0,
-case__189: genesys2_rocket_top__GC0,
-logic__4801: FPU__GB2,
-reg__948: VCU118RocketSystem__GC0,
-datapath__249: VCU118RocketSystem__GC0,
-logic__5255: RocketTile__GCB0,
-datapath__382: FPU__GB2, FPU__GB1,
-case__793: FPU__GB1,
-DivSqrtRawFN_small: FPU__GB2,
-logic__8027: VCU118RocketSystem__GC0,
-reg__849: RocketTile__GCB0,
-logic__4040: FPU__GB2,
-logic__7435: VCU118RocketSystem__GC0,
-logic__1077: VCU118RocketSystem__GC0,
-logic__753: VCU118RocketSystem__GC0,
-logic__3360: FPU__GB1,
-logic__3673: FPU__GB2, FPU__GB1,
-TLAsyncCrossingSink_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__6278: RocketTile__GCB0,
-logic__2941: DCache,
-reg__1253: tracking_wrapper,
-logic__3653: FPU__GB2, FPU__GB1,
-logic__3188: RocketTile__GCB0,
-logic__8823: APBGpsBlock__GC0,
-logic__1961: VCU118RocketSystem__GC0,
-FPToInt: FPU__GB2,
-logic__1748: VCU118RocketSystem__GC0,
-case__1103: VCU118RocketSystem__GC0,
-logic__1223: VCU118RocketSystem__GC0,
-case__961: RocketTile__GCB0,
-logic__7132: VCU118RocketSystem__GC0,
-logic__1551: VCU118RocketSystem__GC0,
-logic__3502: FPU__GB1,
-logic__5963: RocketTile__GCB0,
-logic__7220: VCU118RocketSystem__GC0,
-case__1292: APBGpsBlock__GC0,
-logic__3125: RocketTile__GCB0,
-logic__7285: VCU118RocketSystem__GC0,
-datapath__18: genesys2_rocket_top__GC0,
-datapath__327: FPU__GB2,
-case__147: genesys2_rocket_top__GC0,
-muxpart__53: genesys2_rocket_top__GC0,
-logic__7197: VCU118RocketSystem__GC0,
-logic__1790: VCU118RocketSystem__GC0,
-logic__1589: VCU118RocketSystem__GC0,
-logic__4188: FPU__GB1,
-logic__7276: VCU118RocketSystem__GC0,
-logic__1853: VCU118RocketSystem__GC0,
-muxpart__260: RocketTile__GCB0,
-case__893: RocketTile__GCB0,
-logic__4035: FPU__GB2,
-case__1501: APBGpsBlock__GC0,
-reg__1343: tracking_wrapper,
-keep__11: APBGpsBlock__GC0, tracking_wrapper,
-reg__88: genesys2_rocket_top__GC0,
-case__1128: VCU118RocketSystem__GC0,
-case__775: FPU__GB1,
-reg__256: VCU118RocketSystem__GC0,
-case__516: DCache,
-logic__8032: VCU118RocketSystem__GC0,
-reg__1123: APBGpsBlock__GC0,
-case__392: VCU118RocketSystem__GC0,
-datapath__496: VCU118RocketSystem__GC0,
-logic__1657: VCU118RocketSystem__GC0,
-case__344: VCU118RocketSystem__GC0,
-logic__2852: DCache,
-case__1584: tracking_wrapper,
-logic__5377: RocketTile__GCB0,
-logic__2631: DCache,
-logic__606: genesys2_rocket_top__GC0,
-logic__1846: VCU118RocketSystem__GC0,
-logic__1575: VCU118RocketSystem__GC0,
-datapath__714: TLToAPB,
-reg__199: VCU118RocketSystem__GC0,
-logic__4551: FPU__GB2, FPU__GB1,
-reg__267: VCU118RocketSystem__GC0,
-logic__5661: RocketTile__GCB0,
-reg__177: VCU118RocketSystem__GC0,
-case__394: VCU118RocketSystem__GC0,
-datapath__571: APBGpsBlock__GC0,
-logic__6059: RocketTile__GCB0,
-logic__920: VCU118RocketSystem__GC0,
-datapath__444: RocketTile__GCB0,
-logic__7978: VCU118RocketSystem__GC0,
-logic__9439: tracking_wrapper,
-case__1527: APBGpsBlock__GC0,
-reg__741: RocketTile__GCB0,
-muxpart__131: genesys2_rocket_top__GC0,
-case__439: VCU118RocketSystem__GC0,
-case__320: VCU118RocketSystem__GC0,
-datapath__562: APBGpsBlock__GC0,
-reg__144: VCU118RocketSystem__GC0,
-reg__395: RocketTile__GCB0,
-logic__7318: VCU118RocketSystem__GC0,
-reg__1090: APBGpsBlock__GC0,
-logic__9586: TLToAPB,
-logic__4400: FPU__GB1,
-logic__2313: DCache,
-datapath__130: VCU118RocketSystem__GC0,
-datapath__317: FPU__GB1,
-logic__5556: RocketTile__GCB0,
-logic__9577: TLToAPB,
-logic__4734: FPU__GB2,
-reg__1236: tracking_wrapper,
-reg__865: TilePRCIDomain__GC0,
-logic__5059: FPU__GB1,
-case__1392: APBGpsBlock__GC0,
-case__728: FPU__GB2, FPU__GB1,
-logic__1619: VCU118RocketSystem__GC0,
-reg__994: VCU118RocketSystem__GC0,
-reg__314: VCU118RocketSystem__GC0,
-logic__3811: FPU__GB2,
-datapath__410: FPU__GB1,
-case__286: VCU118RocketSystem__GC0,
-case__275: VCU118RocketSystem__GC0,
-TLFpgaUART: VCU118RocketSystem__GC0,
-case__555: DCache,
-dsp48e1__39: tracking_wrapper,
-logic__4233: FPU__GB1,
-datapath__276: DCache,
-datapath__591: APBGpsBlock__GC0,
-muxpart__75: genesys2_rocket_top__GC0,
-logic__7395: VCU118RocketSystem__GC0,
-logic__6905: VCU118RocketSystem__GC0,
-reg__1073: VCU118RocketSystem__GC0,
-logic__1584: VCU118RocketSystem__GC0,
-logic__3610: FPU__GB2, FPU__GB1,
-logic__8166: VCU118RocketSystem__GC0,
-reg__130: VCU118RocketSystem__GC0,
-logic__2992: RocketTile__GCB0,
-muxpart__67: genesys2_rocket_top__GC0,
-logic__4576: FPU__GB2, FPU__GB1,
-logic__2670: DCache,
-logic__9201: tracking_wrapper,
-logic__8108: VCU118RocketSystem__GC0,
-logic__5392: RocketTile__GCB0,
-dsp48e1__26: APBGpsBlock__GC0,
-case__234: VCU118RocketSystem__GC0,
-muxpart__211: FPU__GB0,
-logic__6834: VCU118RocketSystem__GC0,
-logic__9400: tracking_wrapper,
-datapath__607: APBGpsBlock__GC0,
-logic__3111: RocketTile__GCB0,
-SystemBus: VCU118RocketSystem__GC0,
-reg__587: FPU__GB2,
-logic__6865: VCU118RocketSystem__GC0,
-logic__873: VCU118RocketSystem__GC0,
-logic__2753: DCache,
-case__1606: tracking_wrapper,
-logic__4640: FPU__GB1,
-datapath__455: RocketTile__GCB0,
-reg__421: RocketTile__GCB0,
-reg__1080: VCU118RocketSystem__GC0,
-logic__3551: FPU__GB1,
-reg__783: RocketTile__GCB0,
-logic__9163: tracking_wrapper,
-logic__714: genesys2_rocket_top__GC0,
-logic__9438: tracking_wrapper,
-muxpart__129: genesys2_rocket_top__GC0,
-logic__142: genesys2_rocket_top__GC0,
-logic__5553: RocketTile__GCB0,
-reg__221: VCU118RocketSystem__GC0,
-case__316: VCU118RocketSystem__GC0,
-logic__878: VCU118RocketSystem__GC0,
-logic__3428: FPU__GB1,
-logic__6758: VCU118RocketSystem__GC0,
-datapath__565: APBGpsBlock__GC0,
-logic__1404: VCU118RocketSystem__GC0,
-datapath__318: FPU__GB1,
-logic__6889: VCU118RocketSystem__GC0,
-case__138: genesys2_rocket_top__GC0,
-dsp48e1__20: APBGpsBlock__GC0,
-PTW: RocketTile__GCB0,
-logic__5978: RocketTile__GCB0,
-case__305: VCU118RocketSystem__GC0,
-logic__1070: VCU118RocketSystem__GC0,
-logic__5525: RocketTile__GCB0,
-logic__6540: RocketTile__GCB0,
-logic__5219: RocketTile__GCB0,
-logic__8884: tracking_wrapper,
-datapath__652: tracking_wrapper,
-reg__84: genesys2_rocket_top__GC0,
-logic__9107: tracking_wrapper,
-muxpart__242: FPU__GB2,
-dual_port_bram__parameterized1: APBGpsBlock__GC0,
-case__739: FPU__GB2,
-logic__6051: RocketTile__GCB0,
-case__427: VCU118RocketSystem__GC0,
-reg__803: RocketTile__GCB0,
-logic__8275: VCU118RocketSystem__GC0,
-logic__960: VCU118RocketSystem__GC0,
-case__1039: VCU118RocketSystem__GC0,
-logic__5411: RocketTile__GCB0,
-logic__9584: TLToAPB,
-reg__1164: APBGpsBlock__GC0,
-logic__4928: FPU__GB1,
-datapath__602: APBGpsBlock__GC0,
-case__1204: VCU118RocketSystem__GC0,
-ram__3: VCU118RocketSystem__GC0,
-logic__8878: APBGpsBlock__GC0,
-logic__4777: FPU__GB2,
-logic__8191: VCU118RocketSystem__GC0,
-reg__1358: tracking_wrapper,
-logic__7298: VCU118RocketSystem__GC0,
-logic__4722: FPU__GB2,
-reg__724: RocketTile__GCB0,
-logic__712: genesys2_rocket_top__GC0,
-case__1006: VCU118RocketSystem__GC0,
-logic__2729: DCache,
-logic__1493: VCU118RocketSystem__GC0,
-logic__8215: VCU118RocketSystem__GC0,
-logic__4687: FPU__GB2,
-logic__964: VCU118RocketSystem__GC0,
-case__496: RocketTile__GCB0,
-logic__269: genesys2_rocket_top__GC0,
-logic__7654: VCU118RocketSystem__GC0,
-logic__2963: RocketTile__GCB0,
-reg__397: RocketTile__GCB0,
-logic__3506: FPU__GB1,
-logic__6724: TilePRCIDomain__GC0,
-case__113: genesys2_rocket_top__GC0,
-logic__8868: APBGpsBlock__GC0,
-reg__1330: tracking_wrapper,
-muxpart__165: DCache,
-case__666: FPU__GB1,
-reg__689: RocketTile__GCB0,
-datapath__168: VCU118RocketSystem__GC0,
-case__1531: APBGpsBlock__GC0,
-logic__4263: FPU__GB1,
-datapath__643: tracking_wrapper,
-reg__216: VCU118RocketSystem__GC0,
-reg__1322: tracking_wrapper,
-datapath__436: RocketTile__GCB0,
-logic__1446: VCU118RocketSystem__GC0,
-logic__642: genesys2_rocket_top__GC0,
-case__1142: VCU118RocketSystem__GC0,
-logic__9569: TLToAPB,
-reg__1042: VCU118RocketSystem__GC0,
-case__1104: VCU118RocketSystem__GC0,
-logic__7293: VCU118RocketSystem__GC0,
-muxpart__18: genesys2_rocket_top__GC0,
-datapath__408: FPU__GB1,
-reg__149: VCU118RocketSystem__GC0,
-case__1371: APBGpsBlock__GC0,
-muxpart__168: RocketTile__GCB0,
-logic__9344: tracking_wrapper,
-extram__6: APBGpsBlock__GC0,
-datapath__179: VCU118RocketSystem__GC0,
-reg__539: FPU__GB1,
-logic__13: genesys2_rocket_top__GC0,
-reg__1063: VCU118RocketSystem__GC0,
-logic__9358: tracking_wrapper,
-logic__1604: VCU118RocketSystem__GC0,
-datapath__39: VCU118RocketSystem__GC0,
-case__501: RocketTile__GCB0,
-logic__8355: APBGpsBlock__GC0,
-muxpart__194: FPU__GB0,
-datapath__505: VCU118RocketSystem__GC0,
-datapath__133: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__1061: VCU118RocketSystem__GC0,
-ClockSinkDomain: VCU118RocketSystem__GC0,
-logic__4950: FPU__GB1,
-case__235: VCU118RocketSystem__GC0,
-case__670: FPU__GB2,
-AMOALU: DCache,
-logic__2635: DCache,
-reg__1424: TLToAPB,
-reg__564: FPU__GB1,
-datapath__52: VCU118RocketSystem__GC0,
-reg__337: DCache,
-reg__46: genesys2_rocket_top__GC0,
-logic__8238: VCU118RocketSystem__GC0,
-case__839: RocketTile__GCB0,
-reg__356: DCache,
-logic__5023: FPU__GB1,
-logic__6969: VCU118RocketSystem__GC0,
-case__290: VCU118RocketSystem__GC0,
-reg__851: RocketTile__GCB0,
-case__1154: VCU118RocketSystem__GC0,
-logic__1869: VCU118RocketSystem__GC0,
-logic__9512: tracking_wrapper,
-case__1036: VCU118RocketSystem__GC0,
-logic__6776: VCU118RocketSystem__GC0,
-reg__1324: tracking_wrapper,
-case__1262: APBGpsBlock__GC0,
-logic__3256: RocketTile__GCB0,
-logic__2335: DCache,
-logic__8762: APBGpsBlock__GC0,
-reg__63: genesys2_rocket_top__GC0,
-logic__7173: VCU118RocketSystem__GC0,
-logic__2061: RocketTile__GCB0,
-datapath__71: VCU118RocketSystem__GC0,
-datapath__651: tracking_wrapper,
-logic__4178: FPU__GB1,
-reg__137: VCU118RocketSystem__GC0,
-datapath__439: RocketTile__GCB0,
-logic__4300: FPU__GB1,
-reg__700: RocketTile__GCB0,
-logic__4466: FPU__GB1,
-datapath__131: VCU118RocketSystem__GC0,
-case__1732: APBGpsBlock__GC0,
-reg__72: genesys2_rocket_top__GC0,
-logic__1653: VCU118RocketSystem__GC0,
-logic__2548: DCache,
-reg__579: FPU__GB1,
-logic__4281: FPU__GB1,
-case__402: VCU118RocketSystem__GC0,
-reg__441: RocketTile__GCB0,
-logic__6651: RocketTile__GCB0,
-logic__8419: APBGpsBlock__GC0,
-logic__8200: VCU118RocketSystem__GC0,
-reg__905: VCU118RocketSystem__GC0,
-logic__1955: VCU118RocketSystem__GC0,
-logic__1669: VCU118RocketSystem__GC0,
-logic__9578: TLToAPB,
-case__1559: tracking_wrapper,
-logic__4982: FPU__GB1,
-case__551: DCache,
-ram_2x10: VCU118RocketSystem__GC0,
-reg__882: VCU118RocketSystem__GC0,
-case__512: DCache,
-logic__4962: FPU__GB1,
-datapath__306: RocketTile__GCB0,
-logic__6642: RocketTile__GCB0,
-logic__9395: tracking_wrapper,
-logic__9316: tracking_wrapper,
-case__1140: VCU118RocketSystem__GC0,
-reg__359: DCache,
-case__240: VCU118RocketSystem__GC0,
-datapath__443: RocketTile__GCB0,
-case__130: genesys2_rocket_top__GC0,
-logic__1483: VCU118RocketSystem__GC0,
-logic__4474: FPU__GB1,
-logic__1384: VCU118RocketSystem__GC0,
-case__497: RocketTile__GCB0,
-datapath__616: APBGpsBlock__GC0,
-logic__3260: RocketTile__GCB0,
-reg__696: RocketTile__GCB0,
-logic__1460: VCU118RocketSystem__GC0,
-logic__6856: VCU118RocketSystem__GC0,
-datapath__227: VCU118RocketSystem__GC0,
-case__1050: VCU118RocketSystem__GC0,
-logic__9217: tracking_wrapper,
-logic__2310: DCache,
-case__598: RocketTile__GCB0,
-logic__8039: VCU118RocketSystem__GC0,
-logic__1034: VCU118RocketSystem__GC0,
-logic__7303: VCU118RocketSystem__GC0,
-case__1228: VCU118RocketSystem__GC0,
-datapath__398: FPU__GB2,
-reg__693: RocketTile__GCB0,
-case__1130: VCU118RocketSystem__GC0,
-reg__805: RocketTile__GCB0,
-logic__1594: VCU118RocketSystem__GC0,
-logic__3215: RocketTile__GCB0,
-logic__4981: FPU__GB1,
-logic__1232: VCU118RocketSystem__GC0,
-logic__4248: FPU__GB1,
-logic__3637: FPU__GB2, FPU__GB1,
-reg__657: FPU__GB1,
-logic__7153: VCU118RocketSystem__GC0,
-muxpart__192: FPU__GB0,
-case__558: DCache,
-case__16: genesys2_rocket_top__GC0,
-reg__1030: VCU118RocketSystem__GC0,
-logic__3033: RocketTile__GCB0,
-case__155: genesys2_rocket_top__GC0,
-logic__2600: DCache,
-logic__537: genesys2_rocket_top__GC0,
-logic__5379: RocketTile__GCB0,
-Queue1_RegMapperInput_i23_m8: VCU118RocketSystem__GC0,
-logic__4558: FPU__GB2, FPU__GB1,
-logic__8763: APBGpsBlock__GC0,
-datapath__546: VCU118RocketSystem__GC0,
-case__1054: VCU118RocketSystem__GC0,
-logic__1865: VCU118RocketSystem__GC0,
-logic__5208: RocketTile__GCB0,
-logic__5686: RocketTile__GCB0,
-case__372: VCU118RocketSystem__GC0,
-dsp48e1__6: APBGpsBlock__GC0,
-reg__470: FPU__GB0,
-case__230: VCU118RocketSystem__GC0,
-logic__3931: FPU__GB2,
-reg__506: FPU__GB1,
-case__522: DCache,
-logic__6662: RocketTile__GCB0,
-logic__1894: VCU118RocketSystem__GC0,
-reg__166: VCU118RocketSystem__GC0,
-logic__8760: APBGpsBlock__GC0,
-reg__99: genesys2_rocket_top__GC0,
-muxpart__159: VCU118RocketSystem__GC0,
-case__722: FPU__GB1,
-logic__722: genesys2_rocket_top__GC0,
-logic__7853: VCU118RocketSystem__GC0,
-logic__321: genesys2_rocket_top__GC0,
-case__1097: VCU118RocketSystem__GC0,
-logic__713: genesys2_rocket_top__GC0,
-logic__6949: VCU118RocketSystem__GC0,
-reg__382: RocketTile__GCB0,
-case__1098: VCU118RocketSystem__GC0,
-logic__4258: FPU__GB1,
-reg__562: FPU__GB1,
-logic__4184: FPU__GB1,
-reg__802: RocketTile__GCB0,
-logic__987: VCU118RocketSystem__GC0,
-logic__4899: FPU__GB2,
-reg__1362: tracking_wrapper,
-logic__1987: VCU118RocketSystem__GC0,
-logic__1711: VCU118RocketSystem__GC0,
-logic__9596: TLToAPB,
-logic__2995: RocketTile__GCB0,
-case__1203: VCU118RocketSystem__GC0,
-logic__3598: FPU__GB2, FPU__GB1,
-case__406: VCU118RocketSystem__GC0,
-logic__5122: FPU__GB1,
-logic__1126: VCU118RocketSystem__GC0,
-datapath__30: VCU118RocketSystem__GC0,
-logic__4401: FPU__GB1,
-logic__8109: VCU118RocketSystem__GC0,
-case__536: DCache,
-datapath__324: FPU__GB2, FPU__GB1,
-case__1639: tracking_wrapper,
-case__997: VCU118RocketSystem__GC0,
-logic__5582: RocketTile__GCB0,
-datapath__27: genesys2_rocket_top__GC0,
-logic__7378: VCU118RocketSystem__GC0,
-datapath__185: VCU118RocketSystem__GC0,
-logic__2235: DCache,
-CSRFile: RocketTile__GCB0,
-case__141: genesys2_rocket_top__GC0,
-reg__284: VCU118RocketSystem__GC0,
-logic__4180: FPU__GB1,
-counter__14: APBGpsBlock__GC0,
-muxpart__27: genesys2_rocket_top__GC0,
-reg__262: VCU118RocketSystem__GC0,
-reg__437: RocketTile__GCB0,
-logic__4504: FPU__GB1,
-RocketTile__GCB0: RocketTile__GCB0,
-case__1205: VCU118RocketSystem__GC0,
-logic__1868: VCU118RocketSystem__GC0,
-logic__3739: FPU__GB2,
-case__976: RocketTile__GCB0,
-datapath__623: APBGpsBlock__GC0,
-logic__8399: APBGpsBlock__GC0,
-logic__7408: VCU118RocketSystem__GC0,
-SBToTL: VCU118RocketSystem__GC0,
-TLFpgaSPI: VCU118RocketSystem__GC0,
-reg__1044: VCU118RocketSystem__GC0,
-logic__6870: VCU118RocketSystem__GC0,
-logic__2446: DCache,
-logic__5638: RocketTile__GCB0,
-logic__8958: tracking_wrapper,
-case__195: genesys2_rocket_top__GC0,
-reg__71: genesys2_rocket_top__GC0,
-muxpart__50: genesys2_rocket_top__GC0,
-case__428: VCU118RocketSystem__GC0,
-reg__129: VCU118RocketSystem__GC0,
-logic__2696: DCache,
-datapath__107: VCU118RocketSystem__GC0,
-logic__6816: VCU118RocketSystem__GC0,
-logic__2742: DCache,
-logic__7405: VCU118RocketSystem__GC0,
-case__947: RocketTile__GCB0,
-logic__7347: VCU118RocketSystem__GC0,
-case__622: RocketTile__GCB0,
-logic__1899: VCU118RocketSystem__GC0,
-logic__785: VCU118RocketSystem__GC0,
-logic__5471: RocketTile__GCB0,
-logic__9124: tracking_wrapper,
-datapath__300: RocketTile__GCB0,
-datapath__508: VCU118RocketSystem__GC0,
-datapath__473: RocketTile__GCB0,
-logic__5376: RocketTile__GCB0,
-reg__1046: VCU118RocketSystem__GC0,
-case__321: VCU118RocketSystem__GC0,
-reg__1195: APBGpsBlock__GC0,
-reg__58: genesys2_rocket_top__GC0,
-case__61: genesys2_rocket_top__GC0,
-reg__340: DCache,
-logic__2614: DCache,
-logic__135: genesys2_rocket_top__GC0,
-case__1095: VCU118RocketSystem__GC0,
-case__472: VCU118RocketSystem__GC0,
-logic__4179: FPU__GB1,
-logic__6174: RocketTile__GCB0,
-logic__6947: VCU118RocketSystem__GC0,
-logic__6746: VCU118RocketSystem__GC0,
-case__312: VCU118RocketSystem__GC0,
-logic__738: genesys2_rocket_top__GC0,
-case__23: genesys2_rocket_top__GC0,
-case__727: FPU__GB2, FPU__GB1,
-muxpart__188: FPU__GB0,
-logic__7185: VCU118RocketSystem__GC0,
-logic__7400: VCU118RocketSystem__GC0,
-reg__6: genesys2_rocket_top__GC0,
-logic__7268: VCU118RocketSystem__GC0,
-TLBuffer_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7628: VCU118RocketSystem__GC0,
-reg__353: DCache,
-case__655: FPU__GB1,
-ram_2x115: TilePRCIDomain__GC0,
-logic__7379: VCU118RocketSystem__GC0,
-logic__58: genesys2_rocket_top__GC0,
-logic__9023: tracking_wrapper,
-logic__7660: VCU118RocketSystem__GC0,
-reg__413: RocketTile__GCB0,
-addsub__6: tracking_wrapper,
-logic__3216: RocketTile__GCB0,
-logic__4514: FPU__GB2, FPU__GB1,
-logic__4963: FPU__GB1,
-logic__1728: VCU118RocketSystem__GC0,
-logic__1723: VCU118RocketSystem__GC0,
-logic__2826: DCache,
-reg__511: FPU__GB1,
-logic__5983: RocketTile__GCB0,
-logic__6593: RocketTile__GCB0,
-logic__4162: FPU__GB1,
-datapath__599: APBGpsBlock__GC0,
-RecFNToIN_1: FPU__GB2,
-reg__352: DCache,
-logic__6903: VCU118RocketSystem__GC0,
-datapath__624: APBGpsBlock__GC0,
-muxpart__215: FPU__GB0,
-reg__1293: tracking_wrapper,
-datapath__307: RocketTile__GCB0,
-logic__6583: RocketTile__GCB0,
-case__941: RocketTile__GCB0,
-datapath__542: VCU118RocketSystem__GC0,
-datapath__167: VCU118RocketSystem__GC0,
-datapath__162: VCU118RocketSystem__GC0,
-reg__327: DCache,
-reg__958: VCU118RocketSystem__GC0,
-case__449: VCU118RocketSystem__GC0,
-reg__552: FPU__GB1,
-logic__5425: RocketTile__GCB0,
-logic__6979: VCU118RocketSystem__GC0,
-logic__5046: FPU__GB1,
-datapath__361: FPU__GB1,
-case__1031: VCU118RocketSystem__GC0,
-case__375: VCU118RocketSystem__GC0,
-logic__835: VCU118RocketSystem__GC0,
-case__142: genesys2_rocket_top__GC0,
-logic__2486: RocketTile__GCB0, DCache,
-logic__8182: VCU118RocketSystem__GC0,
-logic__6955: VCU118RocketSystem__GC0,
-reg__169: VCU118RocketSystem__GC0,
-logic__666: genesys2_rocket_top__GC0,
-reg__1124: APBGpsBlock__GC0,
-logic__4984: FPU__GB1,
-logic__2816: DCache,
-reg__1202: APBGpsBlock__GC0,
-logic__1741: VCU118RocketSystem__GC0,
-logic__2679: DCache,
-logic__9020: tracking_wrapper,
-logic__4932: FPU__GB1,
-reg__924: VCU118RocketSystem__GC0, APBGpsBlock__GC0,
-logic__5717: RocketTile__GCB0,
-reg__746: RocketTile__GCB0,
-logic__7255: VCU118RocketSystem__GC0,
-reg__910: VCU118RocketSystem__GC0,
-logic__979: VCU118RocketSystem__GC0,
-logic__6173: RocketTile__GCB0,
-logic__4316: FPU__GB1,
-logic__7101: VCU118RocketSystem__GC0,
-logic__5693: RocketTile__GCB0,
-logic__8237: VCU118RocketSystem__GC0,
-logic__9384: tracking_wrapper,
-datapath__91: VCU118RocketSystem__GC0,
-ClockGroupAggregator_pbus: VCU118RocketSystem__GC0,
-dsp48e1__30: tracking_wrapper,
-logic__5972: RocketTile__GCB0,
-logic__7229: VCU118RocketSystem__GC0,
-logic__4407: FPU__GB1,
-logic__5193: RocketTile__GCB0,
-logic__922: VCU118RocketSystem__GC0,
-logic__2173: DCache,
-logic__5472: RocketTile__GCB0,
-reg__490: FPU__GB1,
-logic__3972: FPU__GB2,
-case__44: genesys2_rocket_top__GC0,
-case__1324: APBGpsBlock__GC0,
-reg__128: VCU118RocketSystem__GC0,
-reg__370: DCache,
-logic__8832: APBGpsBlock__GC0,
-logic__6041: RocketTile__GCB0,
-logic__9244: tracking_wrapper,
-case__419: VCU118RocketSystem__GC0,
-datapath__426: RocketTile__GCB0,
-logic__7706: VCU118RocketSystem__GC0,
-reg__706: RocketTile__GCB0,
-logic__7142: VCU118RocketSystem__GC0,
-case__380: VCU118RocketSystem__GC0,
-reg__1146: APBGpsBlock__GC0,
-logic__5433: RocketTile__GCB0,
-case__608: RocketTile__GCB0,
-logic__6451: RocketTile__GCB0,
-logic__6283: RocketTile__GCB0,
-logic__1257: VCU118RocketSystem__GC0,
-reg__155: VCU118RocketSystem__GC0,
-logic__7576: VCU118RocketSystem__GC0,
-logic__1809: VCU118RocketSystem__GC0,
-reg__833: RocketTile__GCB0,
-muxpart__173: FPU__GB0,
-reg__914: VCU118RocketSystem__GC0,
-logic__6880: VCU118RocketSystem__GC0,
-case__1668: tracking_wrapper,
-logic__150: genesys2_rocket_top__GC0,
-case__241: VCU118RocketSystem__GC0,
-logic__1581: VCU118RocketSystem__GC0,
-logic__5154: RocketTile__GCB0,
-logic__7120: VCU118RocketSystem__GC0,
-case__1645: tracking_wrapper,
-case__1641: tracking_wrapper,
-logic__4806: FPU__GB2,
-case__834: RocketTile__GCB0,
-datapath__234: VCU118RocketSystem__GC0,
-muxpart__202: FPU__GB0,
-case__858: RocketTile__GCB0,
-logic__8037: VCU118RocketSystem__GC0,
-datapath__517: VCU118RocketSystem__GC0,
-logic__3319: FPU__GB1,
-logic__4039: FPU__GB2,
-case__306: VCU118RocketSystem__GC0,
-logic__3354: FPU__GB1,
-logic__1341: VCU118RocketSystem__GC0,
-case__1489: APBGpsBlock__GC0,
-muxpart__170: FPU__GB0,
-accum_dump: tracking_wrapper,
-case__790: FPU__GB1,
-logic__9058: tracking_wrapper,
-logic__7373: VCU118RocketSystem__GC0,
-reg__480: FPU__GB0,
-case__20: genesys2_rocket_top__GC0,
-case__1511: APBGpsBlock__GC0,
-logic__8578: APBGpsBlock__GC0,
-logic__8167: VCU118RocketSystem__GC0,
-logic__961: VCU118RocketSystem__GC0,
-logic__5940: RocketTile__GCB0,
-counter__10: DCache,
-logic__593: genesys2_rocket_top__GC0,
-logic__206: genesys2_rocket_top__GC0,
-reg__1033: VCU118RocketSystem__GC0,
-reg__666: RocketTile__GCB0,
-case__703: FPU__GB1,
-logic__6826: VCU118RocketSystem__GC0,
-logic__5048: FPU__GB1,
-logic__6667: RocketTile__GCB0,
-logic__6515: RocketTile__GCB0,
-datapath__29: genesys2_rocket_top__GC0,
-logic__6896: VCU118RocketSystem__GC0,
-logic__1616: VCU118RocketSystem__GC0,
-case__1217: VCU118RocketSystem__GC0,
-logic__1652: VCU118RocketSystem__GC0,
-logic__8785: APBGpsBlock__GC0,
-logic__218: genesys2_rocket_top__GC0,
-logic__1455: VCU118RocketSystem__GC0,
-reg__971: VCU118RocketSystem__GC0,
-logic__8112: VCU118RocketSystem__GC0,
-logic__3312: RocketTile__GCB0,
-logic__3480: FPU__GB1,
-datapath__121: VCU118RocketSystem__GC0,
-muxpart__176: FPU__GB0,
-case__1611: tracking_wrapper,
-logic__7750: VCU118RocketSystem__GC0,
-logic__4718: FPU__GB2,
-datapath__702: tracking_wrapper,
-logic__5488: RocketTile__GCB0,
-reg__123: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-dsp48e1__32: tracking_wrapper,
-logic__9359: tracking_wrapper,
-reg__495: FPU__GB1,
-reg__606: FPU__GB2,
-logic__3624: FPU__GB2, FPU__GB1,
-case__43: genesys2_rocket_top__GC0,
-case__1554: tracking_wrapper,
-TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u: RocketTile__GCB0,
-dsp48e1__12: APBGpsBlock__GC0,
-case__37: genesys2_rocket_top__GC0,
-case__1206: VCU118RocketSystem__GC0,
-signinv__1: VCU118RocketSystem__GC0,
-logic__1023: VCU118RocketSystem__GC0,
-reg__141: VCU118RocketSystem__GC0,
-reg__967: VCU118RocketSystem__GC0,
-logic__9018: tracking_wrapper,
-logic__2853: DCache,
-logic__3112: RocketTile__GCB0,
-logic__4594: FPU__GB2, FPU__GB1,
-reg__560: FPU__GB1,
-muxpart__224: FPU__GB0,
-logic__5515: RocketTile__GCB0,
-datapath__374: FPU__GB1,
-reg__1306: tracking_wrapper,
-logic__7394: VCU118RocketSystem__GC0,
-reg__127: VCU118RocketSystem__GC0,
-reg__1211: APBGpsBlock__GC0,
-logic__4469: FPU__GB1,
-case__1089: VCU118RocketSystem__GC0,
-logic__1951: VCU118RocketSystem__GC0,
-logic__893: VCU118RocketSystem__GC0,
-logic__2245: DCache,
-logic__5303: RocketTile__GCB0,
-case__480: VCU118RocketSystem__GC0,
-datapath__569: APBGpsBlock__GC0,
-logic__5948: RocketTile__GCB0,
-logic__3552: FPU__GB1,
-case__1380: APBGpsBlock__GC0,
-logic__5544: RocketTile__GCB0,
-logic__4959: FPU__GB1,
-logic__7858: VCU118RocketSystem__GC0,
-case__374: VCU118RocketSystem__GC0,
-logic__5581: RocketTile__GCB0,
-reg__688: RocketTile__GCB0,
-logic__1173: VCU118RocketSystem__GC0,
-logic__2630: DCache,
-logic__3911: FPU__GB2,
-reg__253: VCU118RocketSystem__GC0,
-case__741: FPU__GB2,
-logic__9040: tracking_wrapper,
-case__735: FPU__GB1,
-logic__7667: VCU118RocketSystem__GC0,
-case__28: genesys2_rocket_top__GC0,
-logic__2242: DCache,
-reg__41: genesys2_rocket_top__GC0,
-reg__354: DCache,
-logic__372: genesys2_rocket_top__GC0,
-logic__7033: VCU118RocketSystem__GC0,
-datapath__304: RocketTile__GCB0,
-reg__771: RocketTile__GCB0,
-datapath__118: VCU118RocketSystem__GC0,
-logic__4969: FPU__GB1,
-logic__3482: FPU__GB1,
-AsyncQueueSink_TLBundleA_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-case__867: RocketTile__GCB0,
-extrom__1: APBGpsBlock__GC0,
-case__1078: VCU118RocketSystem__GC0,
-logic__3184: RocketTile__GCB0,
-datapath__335: FPU__GB2,
-muxpart__256: RocketTile__GCB0,
-reg__858: RocketTile__GCB0,
-datapath__197: VCU118RocketSystem__GC0,
-logic__2279: DCache,
-case__1436: APBGpsBlock__GC0,
-logic__9329: tracking_wrapper,
-logic__4443: FPU__GB1,
-logic__1889: VCU118RocketSystem__GC0,
-reg__810: RocketTile__GCB0,
-logic__9267: tracking_wrapper,
-reg__685: RocketTile__GCB0,
-reg__554: FPU__GB1,
-logic__7391: VCU118RocketSystem__GC0,
-datapath__321: FPU__GB2, FPU__GB1,
-logic__6741: VCU118RocketSystem__GC0,
-datapath__217: VCU118RocketSystem__GC0,
-logic__7546: VCU118RocketSystem__GC0,
-datapath__679: tracking_wrapper,
-case__1658: tracking_wrapper,
-logic__351: genesys2_rocket_top__GC0,
-logic__6940: VCU118RocketSystem__GC0,
-PeripheryBus_cbus: VCU118RocketSystem__GC0,
-reg__463: FPU__GB0,
-reg__1045: VCU118RocketSystem__GC0,
-case__1119: VCU118RocketSystem__GC0,
-logic__6170: RocketTile__GCB0,
-datapath__503: VCU118RocketSystem__GC0,
-reg__271: VCU118RocketSystem__GC0,
-logic__8352: APBGpsBlock__GC0,
-logic__2776: DCache,
-logic__9141: tracking_wrapper,
-case__527: DCache,
-logic__4505: FPU__GB1,
-logic__3044: RocketTile__GCB0,
-logic__3803: FPU__GB2,
-reg__1386: tracking_wrapper,
-logic__6998: VCU118RocketSystem__GC0,
-case__1058: VCU118RocketSystem__GC0,
-logic__812: VCU118RocketSystem__GC0,
-logic__7226: VCU118RocketSystem__GC0,
-reg__873: VCU118RocketSystem__GC0,
-logic__6684: RocketTile__GCB0,
-logic__7145: VCU118RocketSystem__GC0,
-logic__4490: FPU__GB1,
-logic__6760: VCU118RocketSystem__GC0,
-logic__210: genesys2_rocket_top__GC0,
-reg__823: RocketTile__GCB0,
-Queue2_TLBundleA_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__5932: RocketTile__GCB0,
-logic__2260: DCache,
-logic__8910: tracking_wrapper,
-case__804: FPU__GB0,
-muxpart__208: FPU__GB0,
-reg__121: VCU118RocketSystem__GC0,
-case__1365: APBGpsBlock__GC0,
-logic__9151: tracking_wrapper,
-case__886: RocketTile__GCB0,
-reg__1282: tracking_wrapper,
-logic__3082: RocketTile__GCB0,
-case__3: genesys2_rocket_top__GC0,
-logic__1245: VCU118RocketSystem__GC0,
-reg__170: VCU118RocketSystem__GC0,
-logic__2690: DCache,
-logic__4557: FPU__GB2, FPU__GB1,
-datapath__156: VCU118RocketSystem__GC0,
-case__1422: APBGpsBlock__GC0,
-case__1041: VCU118RocketSystem__GC0,
-reg__371: DCache,
-datapath__401: FPU__GB2,
-datapath__459: RocketTile__GCB0,
-FrontBus: VCU118RocketSystem__GC0,
-muxpart__233: FPU__GB0,
-logic__548: genesys2_rocket_top__GC0,
-logic__4555: FPU__GB2, FPU__GB1,
-case__1086: VCU118RocketSystem__GC0,
-DivSqrtRawFN_small_1: FPU__GB2,
-case__1102: VCU118RocketSystem__GC0,
-reg__1287: tracking_wrapper,
-case: genesys2_rocket_top__GC0,
-logic__1548: VCU118RocketSystem__GC0,
-reg__56: genesys2_rocket_top__GC0,
-logic__6929: VCU118RocketSystem__GC0,
-reg__191: VCU118RocketSystem__GC0,
-case__214: genesys2_rocket_top__GC0,
-logic__7571: VCU118RocketSystem__GC0,
-logic__6823: VCU118RocketSystem__GC0,
-reg__525: FPU__GB2,
-reg__801: RocketTile__GCB0,
-case__924: RocketTile__GCB0,
-logic__5495: RocketTile__GCB0,
-logic__3297: RocketTile__GCB0,
-logic__4473: FPU__GB1,
-logic__6909: VCU118RocketSystem__GC0,
-logic__5393: RocketTile__GCB0,
-Repeater_TLBundleA_a17d64s2k1z3u: VCU118RocketSystem__GC0,
-case__1065: VCU118RocketSystem__GC0,
-case__304: VCU118RocketSystem__GC0,
-muxpart__51: genesys2_rocket_top__GC0,
-logic__6650: RocketTile__GCB0,
-logic__1150: VCU118RocketSystem__GC0,
-logic__7307: VCU118RocketSystem__GC0,
-datapath__13: genesys2_rocket_top__GC0,
-logic__130: genesys2_rocket_top__GC0,
-logic__3040: RocketTile__GCB0,
-logic__1774: VCU118RocketSystem__GC0,
-logic__965: VCU118RocketSystem__GC0,
-case__772: FPU__GB2,
-logic__85: genesys2_rocket_top__GC0,
-case__1055: VCU118RocketSystem__GC0,
-reg__1345: tracking_wrapper,
-logic__5846: RocketTile__GCB0,
-logic__8224: VCU118RocketSystem__GC0,
-reg__678: RocketTile__GCB0,
-logic__5380: RocketTile__GCB0,
-IntSyncSyncCrossingSink_n1x2: TilePRCIDomain__GC0,
-datapath__196: VCU118RocketSystem__GC0,
-reg__1233: tracking_wrapper,
-logic__2702: DCache,
-reg__44: genesys2_rocket_top__GC0,
-logic__6166: RocketTile__GCB0,
-muxpart__14: genesys2_rocket_top__GC0,
-IntSyncCrossingSource_n1x1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7640: VCU118RocketSystem__GC0,
-reg__303: VCU118RocketSystem__GC0,
-muxpart__258: RocketTile__GCB0,
-case__289: VCU118RocketSystem__GC0,
-muxpart__359: APBGpsBlock__GC0,
-case__279: VCU118RocketSystem__GC0,
-muxpart__379: tracking_wrapper,
-reg__1337: tracking_wrapper,
-logic__4931: FPU__GB1,
-logic__6827: VCU118RocketSystem__GC0,
-datapath__136: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__388: RocketTile__GCB0,
-logic__7428: VCU118RocketSystem__GC0,
-reg__1163: APBGpsBlock__GC0,
-case__1513: APBGpsBlock__GC0,
-reg__530: FPU__GB2,
-case__1615: tracking_wrapper,
-case__284: VCU118RocketSystem__GC0,
-logic__2413: DCache,
-logic__4265: FPU__GB1,
-reg__1308: tracking_wrapper,
-case__675: FPU__GB2,
-logic__7322: VCU118RocketSystem__GC0,
-logic__5936: RocketTile__GCB0,
-logic__5691: RocketTile__GCB0,
-reg__295: VCU118RocketSystem__GC0,
-datapath__112: VCU118RocketSystem__GC0,
-logic__7655: VCU118RocketSystem__GC0,
-logic__5407: RocketTile__GCB0,
-logic__1685: VCU118RocketSystem__GC0,
-logic__4403: FPU__GB1,
-case__55: genesys2_rocket_top__GC0,
-logic__3016: RocketTile__GCB0,
-logic__8969: tracking_wrapper,
-reg__86: genesys2_rocket_top__GC0,
-case__308: VCU118RocketSystem__GC0,
-logic__4748: FPU__GB2,
-case__1626: tracking_wrapper,
-logic__679: genesys2_rocket_top__GC0,
-reg__1342: tracking_wrapper,
-logic__4352: FPU__GB1,
-reg__665: RocketTile__GCB0,
-logic__6079: RocketTile__GCB0,
-logic__207: genesys2_rocket_top__GC0,
-datapath__350: FPU__GB2,
-case__1052: VCU118RocketSystem__GC0,
-logic__7505: VCU118RocketSystem__GC0,
-logic__1278: VCU118RocketSystem__GC0,
-logic__2492: RocketTile__GCB0, DCache,
-counter__28: tracking_wrapper,
-reg__1017: VCU118RocketSystem__GC0,
-logic__7186: VCU118RocketSystem__GC0,
-logic__1106: VCU118RocketSystem__GC0,
-reg__993: VCU118RocketSystem__GC0,
-logic__7213: VCU118RocketSystem__GC0,
-reg__1176: APBGpsBlock__GC0,
-datapath__336: FPU__GB2,
-case__202: genesys2_rocket_top__GC0,
-reg__29: genesys2_rocket_top__GC0,
-Queue2_TLBundleD_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__558: genesys2_rocket_top__GC0,
-reg__911: VCU118RocketSystem__GC0,
-reg__1372: tracking_wrapper,
-reg__507: FPU__GB1,
-datapath__612: APBGpsBlock__GC0,
-logic__2977: RocketTile__GCB0,
-logic__4318: FPU__GB1,
-muxpart__34: genesys2_rocket_top__GC0,
-logic__5039: FPU__GB1,
-logic__2701: DCache,
-logic__779: VCU118RocketSystem__GC0,
-case__525: DCache,
-logic__9114: tracking_wrapper,
-datapath__657: tracking_wrapper,
-counter__9: VCU118RocketSystem__GC0,
-logic__9580: TLToAPB,
-case__514: DCache,
-logic__1615: VCU118RocketSystem__GC0,
-datapath__72: VCU118RocketSystem__GC0,
-case__1572: tracking_wrapper,
-logic__5949: RocketTile__GCB0,
-reg__650: FPU__GB1,
-logic__7537: VCU118RocketSystem__GC0,
-logic__5536: RocketTile__GCB0,
-logic__7876: VCU118RocketSystem__GC0,
-logic__7510: VCU118RocketSystem__GC0,
-datapath__479: RocketTile__GCB0,
-logic__1463: VCU118RocketSystem__GC0,
-case__451: VCU118RocketSystem__GC0,
-case__1432: APBGpsBlock__GC0,
-reg__735: RocketTile__GCB0,
-reg__524: FPU__GB2,
-dsp48e1__9: APBGpsBlock__GC0,
-logic__3328: FPU__GB1,
-logic__4089: FPU__GB2,
-case__441: VCU118RocketSystem__GC0,
-reg__1028: VCU118RocketSystem__GC0,
-logic__5150: RocketTile__GCB0,
-afe_top: APBGpsBlock__GC0,
-logic__7464: VCU118RocketSystem__GC0,
-logic__9562: APBGpsBlock__GC0,
-datapath__363: FPU__GB1,
-logic__7955: VCU118RocketSystem__GC0,
-muxpart__230: FPU__GB0,
-logic__1674: VCU118RocketSystem__GC0,
-case__1370: APBGpsBlock__GC0,
-logic__7360: VCU118RocketSystem__GC0,
-logic__3553: FPU__GB1,
-reg__76: genesys2_rocket_top__GC0,
-case__152: genesys2_rocket_top__GC0,
-logic__3165: RocketTile__GCB0,
-case__992: VCU118RocketSystem__GC0,
-reg__1274: tracking_wrapper,
-logic__8249: VCU118RocketSystem__GC0,
-logic__7155: VCU118RocketSystem__GC0,
-case__1308: APBGpsBlock__GC0,
-reg__201: VCU118RocketSystem__GC0,
-reg__863: TilePRCIDomain__GC0,
-case__851: RocketTile__GCB0,
-muxpart__190: FPU__GB0,
-reg__902: VCU118RocketSystem__GC0,
-case__424: VCU118RocketSystem__GC0,
-logic__624: genesys2_rocket_top__GC0,
-logic__7175: VCU118RocketSystem__GC0,
-logic__1730: VCU118RocketSystem__GC0,
-TLXbar_sbus_i2_o1_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__42: genesys2_rocket_top__GC0,
-reg__655: FPU__GB1,
-DCacheDataArray: DCache,
-case__993: VCU118RocketSystem__GC0,
-logic__5786: RocketTile__GCB0,
-case__208: genesys2_rocket_top__GC0,
-case__824: RocketTile__GCB0,
-logic__4108: FPU__GB2,
-reg__1040: VCU118RocketSystem__GC0,
-datapath__707: tracking_wrapper,
-logic__2967: RocketTile__GCB0,
-muxpart__185: FPU__GB0,
-logic__8254: VCU118RocketSystem__GC0,
-case__333: VCU118RocketSystem__GC0,
-logic__6021: RocketTile__GCB0,
-logic__3916: FPU__GB2,
-logic__1986: VCU118RocketSystem__GC0,
-fft_radix_2: APBGpsBlock__GC0,
-reg__369: DCache,
-logic__7082: VCU118RocketSystem__GC0,
-reg__612: FPU__GB1,
-logic__2537: RocketTile__GCB0, DCache,
-datapath__540: VCU118RocketSystem__GC0,
-logic__7302: VCU118RocketSystem__GC0,
-reg__1432: TLToAPB,
-logic__2254: DCache,
-logic__4094: FPU__GB2,
-datapath__252: VCU118RocketSystem__GC0,
-case__784: FPU__GB2,
-logic__8023: VCU118RocketSystem__GC0,
-acq_wrapper: APBGpsBlock__GC0,
-datapath__477: RocketTile__GCB0,
-logic__2470: DCache,
-logic__8420: APBGpsBlock__GC0,
-logic__8012: VCU118RocketSystem__GC0,
-case__457: VCU118RocketSystem__GC0,
-logic__3466: FPU__GB1,
-logic__8503: APBGpsBlock__GC0,
-dsp48e1__31: tracking_wrapper,
-muxpart__189: FPU__GB0,
-logic__6683: RocketTile__GCB0,
-logic__7945: VCU118RocketSystem__GC0,
-logic__9367: tracking_wrapper,
-case__880: RocketTile__GCB0,
-logic__4572: FPU__GB2, FPU__GB1,
-logic__849: VCU118RocketSystem__GC0,
-case__232: VCU118RocketSystem__GC0,
-case__556: DCache,
-logic__7139: VCU118RocketSystem__GC0,
-case__820: RocketTile__GCB0,
-muxpart__133: genesys2_rocket_top__GC0,
-logic__7028: VCU118RocketSystem__GC0,
-reg__822: RocketTile__GCB0,
-reg__1185: APBGpsBlock__GC0,
-case__1608: tracking_wrapper,
-reg__684: RocketTile__GCB0,
-logic__1751: VCU118RocketSystem__GC0,
-datapath__286: RocketTile__GCB0,
-logic__2675: DCache,
-case__399: VCU118RocketSystem__GC0,
-reg__1007: VCU118RocketSystem__GC0,
-logic__2911: DCache,
-logic__6620: RocketTile__GCB0,
-logic__8197: VCU118RocketSystem__GC0,
-logic__4394: FPU__GB1,
-logic__3270: RocketTile__GCB0,
-reg__47: genesys2_rocket_top__GC0,
-logic__7775: VCU118RocketSystem__GC0,
-case__1599: tracking_wrapper,
-logic__9357: tracking_wrapper,
-logic__8181: VCU118RocketSystem__GC0,
-logic__871: VCU118RocketSystem__GC0,
-datapath__245: VCU118RocketSystem__GC0,
-logic__4353: FPU__GB1,
-reg__582: FPU__GB2,
-logic__8582: APBGpsBlock__GC0,
-logic__6765: VCU118RocketSystem__GC0,
-logic__1397: VCU118RocketSystem__GC0,
-logic__2985: RocketTile__GCB0,
-logic__613: genesys2_rocket_top__GC0,
-reg__229: VCU118RocketSystem__GC0,
-logic__2770: DCache,
-reg__577: FPU__GB1,
-logic__1447: VCU118RocketSystem__GC0,
-reg__704: RocketTile__GCB0,
-logic__3183: RocketTile__GCB0,
-case__1158: VCU118RocketSystem__GC0,
-logic__5112: FPU__GB1,
-logic__6825: VCU118RocketSystem__GC0,
-logic__993: VCU118RocketSystem__GC0,
-logic__3034: RocketTile__GCB0,
-reg__60: genesys2_rocket_top__GC0,
-muxpart__128: genesys2_rocket_top__GC0,
-datapath__509: VCU118RocketSystem__GC0,
-case__1015: VCU118RocketSystem__GC0,
-ram_2x124: VCU118RocketSystem__GC0,
-reg__1323: tracking_wrapper,
-case__854: RocketTile__GCB0,
-case__233: VCU118RocketSystem__GC0,
-datapath__44: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-ram__5: VCU118RocketSystem__GC0,
-reg__573: FPU__GB1,
-case__210: genesys2_rocket_top__GC0,
-case__453: VCU118RocketSystem__GC0,
-logic__1744: VCU118RocketSystem__GC0,
-case__200: genesys2_rocket_top__GC0,
-TLROM: VCU118RocketSystem__GC0,
-case__811: FPU__GB1,
-logic__5527: RocketTile__GCB0,
-logic__7441: VCU118RocketSystem__GC0,
-case__592: RocketTile__GCB0,
-reg__996: VCU118RocketSystem__GC0,
-logic__4330: FPU__GB1,
-logic__2475: RocketTile__GCB0, DCache,
-logic__5369: RocketTile__GCB0,
-case__1592: tracking_wrapper,
-reg__24: genesys2_rocket_top__GC0,
-logic__3826: FPU__GB2,
-reg__124: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__728: RocketTile__GCB0,
-logic__816: VCU118RocketSystem__GC0,
-logic__4645: FPU__GB2,
-case__1476: APBGpsBlock__GC0,
-reg__1069: VCU118RocketSystem__GC0,
-case__293: VCU118RocketSystem__GC0,
-reg__254: VCU118RocketSystem__GC0,
-logic__180: genesys2_rocket_top__GC0,
-logic__7448: VCU118RocketSystem__GC0,
-logic__1130: VCU118RocketSystem__GC0,
-case__1560: tracking_wrapper,
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1: VCU118RocketSystem__GC0,
-case__481: VCU118RocketSystem__GC0,
-logic__3561: FPU__GB1,
-logic__6899: VCU118RocketSystem__GC0,
-case__562: DCache,
-reg__146: VCU118RocketSystem__GC0,
-logic__923: VCU118RocketSystem__GC0,
-logic__2622: DCache,
-logic__4175: FPU__GB1,
-logic__749: genesys2_rocket_top__GC0,
-reg__101: genesys2_rocket_top__GC0,
-case__1122: VCU118RocketSystem__GC0,
-logic__5484: RocketTile__GCB0,
-logic__8688: APBGpsBlock__GC0,
-datapath__449: RocketTile__GCB0,
-case__1218: VCU118RocketSystem__GC0,
-logic__6782: VCU118RocketSystem__GC0,
-reg__1131: APBGpsBlock__GC0,
-datapath__299: RocketTile__GCB0,
-keep__5: genesys2_rocket_top__GC0,
-logic__7009: VCU118RocketSystem__GC0,
-reg__1404: tracking_wrapper,
-muxpart__31: genesys2_rocket_top__GC0,
-muxpart__16: genesys2_rocket_top__GC0,
-DivSqrtRecFNToRaw_small_1: FPU__GB2,
-logic__4974: FPU__GB1,
-logic__1636: VCU118RocketSystem__GC0,
-MulAddRecFNToRaw_postMul_1: FPU__GB1,
-logic__9604: genesys2_rocket_top__GC0,
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0: VCU118RocketSystem__GC0, APBGpsBlock__GC0,
-logic__1069: VCU118RocketSystem__GC0,
-case__1590: tracking_wrapper,
-reg__734: RocketTile__GCB0,
-logic__4422: FPU__GB1,
-reg__384: RocketTile__GCB0,
-datapath__523: VCU118RocketSystem__GC0,
-case__532: DCache,
-case__717: FPU__GB1,
-reg__870: VCU118RocketSystem__GC0,
-case__60: genesys2_rocket_top__GC0,
-case__1241: VCU118RocketSystem__GC0,
-case__256: VCU118RocketSystem__GC0,
-reg__122: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__114: genesys2_rocket_top__GC0,
-logic__7397: VCU118RocketSystem__GC0,
-logic__7849: VCU118RocketSystem__GC0,
-logic__5364: RocketTile__GCB0,
-reg__17: genesys2_rocket_top__GC0,
-logic__8241: VCU118RocketSystem__GC0,
-datapath__229: VCU118RocketSystem__GC0,
-logic__5927: RocketTile__GCB0,
-logic__3261: RocketTile__GCB0,
-case__467: VCU118RocketSystem__GC0,
-logic__4639: FPU__GB1,
-logic__4617: FPU__GB2, FPU__GB1,
-logic__7283: VCU118RocketSystem__GC0,
-case__446: VCU118RocketSystem__GC0,
-logic__1419: VCU118RocketSystem__GC0,
-logic__1220: VCU118RocketSystem__GC0,
-butterfly: APBGpsBlock__GC0,
-rom__4: APBGpsBlock__GC0,
-muxpart__203: FPU__GB0,
-logic__3342: FPU__GB1,
-logic__1277: VCU118RocketSystem__GC0,
-case__1240: VCU118RocketSystem__GC0,
-logic__3330: FPU__GB1,
-case__590: RocketTile__GCB0,
-muxpart__231: FPU__GB0,
-datapath__512: VCU118RocketSystem__GC0,
-case__217: genesys2_rocket_top__GC0,
-logic__897: VCU118RocketSystem__GC0,
-datapath__253: VCU118RocketSystem__GC0,
-reg__405: RocketTile__GCB0,
-logic__4983: FPU__GB1,
-logic__1861: VCU118RocketSystem__GC0,
-reg__214: VCU118RocketSystem__GC0,
-logic__9610: genesys2_rocket_top__GC0,
-logic__3113: RocketTile__GCB0,
-reg__414: RocketTile__GCB0,
-logic__47: genesys2_rocket_top__GC0,
-logic__4421: FPU__GB1,
-case__611: RocketTile__GCB0,
-muxpart__206: FPU__GB0,
-logic__7310: VCU118RocketSystem__GC0,
-logic__1254: VCU118RocketSystem__GC0,
-datapath__576: APBGpsBlock__GC0,
-logic__6862: VCU118RocketSystem__GC0,
-reg__681: RocketTile__GCB0,
-reg__813: RocketTile__GCB0,
-muxpart__21: genesys2_rocket_top__GC0,
-logic__1688: VCU118RocketSystem__GC0,
-datapath__553: APBGpsBlock__GC0,
-logic__7136: VCU118RocketSystem__GC0,
-logic__1307: VCU118RocketSystem__GC0,
-logic__2582: DCache,
-datapath__8: genesys2_rocket_top__GC0,
-datapath__584: APBGpsBlock__GC0,
-logic__3856: FPU__GB2,
-datapath__636: APBGpsBlock__GC0,
-datapath__641: APBGpsBlock__GC0,
-case__248: VCU118RocketSystem__GC0,
-reg__1281: tracking_wrapper,
-datapath__337: FPU__GB2,
-logic__7237: VCU118RocketSystem__GC0,
-reg__934: VCU118RocketSystem__GC0,
-reg__589: FPU__GB2,
-logic__3314: FPU__GB1,
-logic__5372: RocketTile__GCB0,
-datapath__274: DCache,
-logic__2758: DCache,
-logic__8585: APBGpsBlock__GC0,
-reg__607: FPU__GB2,
-PlusArgTimeout: RocketTile__GCB0,
-reg__1364: tracking_wrapper,
-muxpart__344: APBGpsBlock__GC0,
-case__601: RocketTile__GCB0,
-case__1200: VCU118RocketSystem__GC0,
-case__390: VCU118RocketSystem__GC0,
-datapath__469: RocketTile__GCB0,
-case__1420: APBGpsBlock__GC0,
-muxpart__4: genesys2_rocket_top__GC0,
-logic__1821: VCU118RocketSystem__GC0,
-logic__8329: APBGpsBlock__GC0,
-logic__790: VCU118RocketSystem__GC0,
-logic__3957: FPU__GB2,
-logic__2980: RocketTile__GCB0,
-logic__9311: tracking_wrapper,
-logic__5374: RocketTile__GCB0,
-datapath__381: FPU__GB2, FPU__GB1,
-Arbiter8_DCacheMetadataReq: DCache,
-reg__645: FPU__GB1,
-case__1625: tracking_wrapper,
-logic__1328: VCU118RocketSystem__GC0,
-logic__820: VCU118RocketSystem__GC0,
-case__547: DCache,
-case__1127: VCU118RocketSystem__GC0,
-logic__3614: FPU__GB2, FPU__GB1,
-dsp48e1__44: tracking_wrapper,
-logic__4107: FPU__GB2,
-logic__8907: tracking_wrapper,
-case__1226: VCU118RocketSystem__GC0,
-logic__7723: VCU118RocketSystem__GC0,
-datapath__125: VCU118RocketSystem__GC0,
-reg__1231: tracking_wrapper,
-reg__843: RocketTile__GCB0,
-logic__6011: RocketTile__GCB0,
-logic__5221: RocketTile__GCB0,
-logic__6506: RocketTile__GCB0,
-case__1528: APBGpsBlock__GC0,
-logic__2209: DCache,
-logic__3494: FPU__GB1,
-logic__5440: RocketTile__GCB0,
-logic__6085: RocketTile__GCB0,
-logic__9022: tracking_wrapper,
-logic__7121: VCU118RocketSystem__GC0,
-logic__3472: FPU__GB1,
-case__436: VCU118RocketSystem__GC0,
-case__300: VCU118RocketSystem__GC0,
-logic__4269: FPU__GB1,
-muxpart__80: genesys2_rocket_top__GC0,
-Arbiter3_LLWB: RocketTile__GCB0,
-logic__4374: FPU__GB1,
-logic__8282: VCU118RocketSystem__GC0,
-logic__6156: RocketTile__GCB0,
-case__1233: VCU118RocketSystem__GC0,
-extram__2: RocketTile__GCB0,
-logic__5687: RocketTile__GCB0,
-datapath__539: VCU118RocketSystem__GC0,
-logic__6960: VCU118RocketSystem__GC0,
-reg__816: RocketTile__GCB0,
-logic__3325: FPU__GB1,
-logic__3074: RocketTile__GCB0,
-logic__6500: RocketTile__GCB0,
-case__1475: APBGpsBlock__GC0,
-RocketALU: RocketTile__GCB0,
-ram_2x120: VCU118RocketSystem__GC0,
-logic__3555: FPU__GB1,
-logic__4569: FPU__GB2, FPU__GB1,
-dsp48e1__34: tracking_wrapper,
-logic__8287: VCU118RocketSystem__GC0,
-reg__1135: APBGpsBlock__GC0,
-logic__1793: VCU118RocketSystem__GC0,
-logic__1773: VCU118RocketSystem__GC0,
-datapath__244: VCU118RocketSystem__GC0,
-TLFragmenter_PLIC: VCU118RocketSystem__GC0,
-logic__7392: VCU118RocketSystem__GC0,
-logic__6637: RocketTile__GCB0,
-datapath__303: RocketTile__GCB0,
-reg__723: RocketTile__GCB0,
-reg__23: genesys2_rocket_top__GC0,
-logic__4943: FPU__GB2,
-logic__8225: VCU118RocketSystem__GC0,
-logic__7547: VCU118RocketSystem__GC0,
-case__1506: APBGpsBlock__GC0,
-case__773: FPU__GB1,
-reg__923: VCU118RocketSystem__GC0,
-logic__3880: FPU__GB2,
-reg__1241: tracking_wrapper,
-logic__2931: DCache,
-logic__6321: RocketTile__GCB0,
-logic__857: VCU118RocketSystem__GC0,
-reg__662: FPU__GB1,
-logic__1570: VCU118RocketSystem__GC0,
-logic__4675: FPU__GB2,
-datapath__47: VCU118RocketSystem__GC0,
-reg__1199: APBGpsBlock__GC0,
-datapath__404: FPU__GB2,
-logic__2518: RocketTile__GCB0, DCache,
-logic__8605: APBGpsBlock__GC0,
-logic__4444: FPU__GB1,
-logic__5933: RocketTile__GCB0,
-reg__96: genesys2_rocket_top__GC0,
-logic__7997: VCU118RocketSystem__GC0,
-logic__7832: VCU118RocketSystem__GC0,
-logic__2049: VCU118RocketSystem__GC0,
-logic__647: genesys2_rocket_top__GC0,
-logic__7043: VCU118RocketSystem__GC0,
-reg__917: VCU118RocketSystem__GC0,
-logic__3159: RocketTile__GCB0,
-reg__781: RocketTile__GCB0,
-logic__4398: FPU__GB1,
-logic__7871: VCU118RocketSystem__GC0,
-logic__8328: APBGpsBlock__GC0,
-reg__484: FPU__GB0,
-logic__751: VCU118RocketSystem__GC0,
-reg__538: FPU__GB1,
-reg__1188: APBGpsBlock__GC0,
-reg__3: genesys2_rocket_top__GC0,
-logic__955: VCU118RocketSystem__GC0,
-datapath__260: RocketTile__GCB0,
-datapath__690: tracking_wrapper,
-logic__2250: DCache,
-keep__8: genesys2_rocket_top__GC0,
-datapath__715: VCU118RocketSystem__GC0,
-logic__2022: VCU118RocketSystem__GC0,
-case__302: VCU118RocketSystem__GC0,
-logic__9010: tracking_wrapper,
-reg__762: RocketTile__GCB0,
-reg__111: VCU118RocketSystem__GC0,
-logic__2232: DCache,
-logic__783: VCU118RocketSystem__GC0,
-datapath__617: APBGpsBlock__GC0,
-case__123: genesys2_rocket_top__GC0,
-reg__283: VCU118RocketSystem__GC0,
-counter__27: tracking_wrapper,
-logic__188: genesys2_rocket_top__GC0,
-case__828: RocketTile__GCB0,
-logic__9232: tracking_wrapper,
-logic__8889: tracking_wrapper,
-logic__7639: VCU118RocketSystem__GC0,
-logic__6748: VCU118RocketSystem__GC0,
-reg__1327: tracking_wrapper,
-case__520: DCache,
-logic__6553: RocketTile__GCB0,
-datapath__534: VCU118RocketSystem__GC0,
-logic__4289: FPU__GB1,
-case__1113: VCU118RocketSystem__GC0,
-reg__772: RocketTile__GCB0,
-logic__4954: FPU__GB1,
-logic__7316: VCU118RocketSystem__GC0,
-extram__7: APBGpsBlock__GC0,
-logic__4008: FPU__GB2,
-reg__1341: tracking_wrapper,
-case__1117: VCU118RocketSystem__GC0,
-logic__1094: VCU118RocketSystem__GC0,
-reg__811: RocketTile__GCB0,
-case__1236: VCU118RocketSystem__GC0,
-case__747: FPU__GB2,
-logic__5914: RocketTile__GCB0,
-logic__1949: VCU118RocketSystem__GC0,
-datapath__364: FPU__GB1,
-logic__3012: RocketTile__GCB0,
-logic__2584: DCache,
-logic__5426: RocketTile__GCB0,
-datapath__224: VCU118RocketSystem__GC0,
-case__299: VCU118RocketSystem__GC0,
-logic__8784: APBGpsBlock__GC0,
-logic__5304: RocketTile__GCB0,
-muxpart__151: genesys2_rocket_top__GC0,
-datapath__538: VCU118RocketSystem__GC0,
-case__1734: TLToAPB,
-logic__718: genesys2_rocket_top__GC0,
-reg__874: VCU118RocketSystem__GC0,
-case__882: RocketTile__GCB0,
-case__247: VCU118RocketSystem__GC0,
-logic__2516: RocketTile__GCB0, DCache,
-logic__8442: APBGpsBlock__GC0,
-datapath__377: FPU__GB1,
-reg__358: DCache,
-logic__4566: FPU__GB2, FPU__GB1,
-logic__4491: FPU__GB1,
-case__1056: VCU118RocketSystem__GC0,
-logic__2680: DCache,
-datapath__83: VCU118RocketSystem__GC0,
-logic__2152: DCache,
-logic__6575: RocketTile__GCB0,
-case__894: RocketTile__GCB0,
-logic__1124: VCU118RocketSystem__GC0,
-datapath__586: APBGpsBlock__GC0,
-reg__1038: VCU118RocketSystem__GC0,
-logic__1396: VCU118RocketSystem__GC0,
-reg__74: genesys2_rocket_top__GC0,
-logic__7808: VCU118RocketSystem__GC0,
-counter__30: tracking_wrapper,
-case__1539: tracking_wrapper,
-datapath__3: genesys2_rocket_top__GC0,
-datapath__184: VCU118RocketSystem__GC0,
-logic__4999: FPU__GB1,
-logic__7096: VCU118RocketSystem__GC0,
-case__1019: VCU118RocketSystem__GC0,
-datapath__556: APBGpsBlock__GC0,
-muxpart__17: genesys2_rocket_top__GC0,
-logic__5913: RocketTile__GCB0,
-case__830: RocketTile__GCB0,
-logic__2263: DCache,
-case__926: RocketTile__GCB0,
-logic__1845: VCU118RocketSystem__GC0,
-logic__7594: VCU118RocketSystem__GC0,
-datapath__291: RocketTile__GCB0,
-case__1437: APBGpsBlock__GC0,
-logic__4830: FPU__GB2,
-reg__1238: tracking_wrapper,
-logic__4728: FPU__GB2,
-case__180: genesys2_rocket_top__GC0,
-logic__2705: DCache,
-TLError: VCU118RocketSystem__GC0,
-reg__432: RocketTile__GCB0,
-case__491: RocketTile__GCB0,
-reg__1252: tracking_wrapper,
-logic__2102: RocketTile__GCB0,
-reg__272: VCU118RocketSystem__GC0,
-logic__5076: FPU__GB1,
-datapath__326: FPU__GB1,
-case__422: VCU118RocketSystem__GC0,
-logic__4043: FPU__GB2,
-logic__6804: VCU118RocketSystem__GC0,
-logic__5172: RocketTile__GCB0,
-logic__6952: VCU118RocketSystem__GC0,
-case__1080: VCU118RocketSystem__GC0,
-logic__6933: VCU118RocketSystem__GC0,
-logic__4379: FPU__GB1,
-reg__1078: VCU118RocketSystem__GC0,
-logic__5361: RocketTile__GCB0,
-logic__9520: APBGpsBlock__GC0,
-logic__622: genesys2_rocket_top__GC0,
-case__1159: VCU118RocketSystem__GC0,
-logic__5916: RocketTile__GCB0,
-case__734: FPU__GB2, FPU__GB1,
-datapath__64: VCU118RocketSystem__GC0,
-case__1172: VCU118RocketSystem__GC0,
-logic__7026: VCU118RocketSystem__GC0,
-case__519: DCache,
-logic__8548: APBGpsBlock__GC0,
-case__623: RocketTile__GCB0,
-reg__875: VCU118RocketSystem__GC0,
-case__1718: tracking_wrapper,
-datapath__110: VCU118RocketSystem__GC0,
-reg__828: RocketTile__GCB0,
-case__696: FPU__GB2,
-logic__1732: VCU118RocketSystem__GC0,
-reg__243: VCU118RocketSystem__GC0,
-case__911: RocketTile__GCB0,
-case__1593: tracking_wrapper,
-case__1181: VCU118RocketSystem__GC0,
-cordic_atan_basic: tracking_wrapper,
-case__1121: VCU118RocketSystem__GC0,
-logic__9427: tracking_wrapper,
-extram__1: DCache,
-logic__520: genesys2_rocket_top__GC0,
-case__1096: VCU118RocketSystem__GC0,
-case__1028: VCU118RocketSystem__GC0,
-logic__1073: VCU118RocketSystem__GC0,
-logic__7184: VCU118RocketSystem__GC0,
-logic__1605: VCU118RocketSystem__GC0,
-logic__2170: DCache,
-MulAddRecFNPipe_l2_e8_s24: FPU__GB1,
-DivSqrtRecFN_small_1: FPU__GB2,
-logic__953: VCU118RocketSystem__GC0,
-logic__1810: VCU118RocketSystem__GC0,
-case__647: FPU__GB1,
-reg__306: VCU118RocketSystem__GC0,
-muxpart__160: VCU118RocketSystem__GC0,
-logic__8022: VCU118RocketSystem__GC0,
-logic__3166: RocketTile__GCB0,
-case__1207: VCU118RocketSystem__GC0,
-reg__676: RocketTile__GCB0,
-case__950: RocketTile__GCB0,
-logic__7946: VCU118RocketSystem__GC0,
-logic__9096: tracking_wrapper,
-reg__1245: tracking_wrapper,
-logic__529: genesys2_rocket_top__GC0,
-logic__7730: VCU118RocketSystem__GC0,
-logic__7645: VCU118RocketSystem__GC0,
-logic__7156: VCU118RocketSystem__GC0,
-logic__6893: VCU118RocketSystem__GC0,
-counter__25: tracking_wrapper,
-logic__2030: VCU118RocketSystem__GC0,
-logic__2821: DCache,
-logic__7251: VCU118RocketSystem__GC0,
-reg__1016: VCU118RocketSystem__GC0,
-logic__5827: RocketTile__GCB0,
-case__1170: VCU118RocketSystem__GC0,
-logic__634: genesys2_rocket_top__GC0,
-logic__6848: VCU118RocketSystem__GC0,
-logic__3348: FPU__GB1,
-logic__7352: VCU118RocketSystem__GC0,
-case__245: VCU118RocketSystem__GC0,
-reg__1314: tracking_wrapper,
-logic__4320: FPU__GB1,
-logic__5363: RocketTile__GCB0,
-reg__110: VCU118RocketSystem__GC0,
-mdio_rtl8211e_init: genesys2_rocket_top__GC0,
-logic__6857: VCU118RocketSystem__GC0,
-logic__5952: RocketTile__GCB0,
-keep: genesys2_rocket_top__GC0,
-logic__6869: VCU118RocketSystem__GC0,
-reg__730: RocketTile__GCB0,
-reg__667: RocketTile__GCB0,
-logic__7151: VCU118RocketSystem__GC0,
-logic__850: VCU118RocketSystem__GC0,
-reg__752: RocketTile__GCB0,
-reg__1356: tracking_wrapper,
-logic__7372: VCU118RocketSystem__GC0,
-logic__4321: FPU__GB1,
-logic__3523: FPU__GB1,
-logic__9519: APBGpsBlock__GC0,
-logic__892: VCU118RocketSystem__GC0,
-reg__318: RocketTile__GCB0,
-reg__435: RocketTile__GCB0,
-logic__1084: VCU118RocketSystem__GC0,
-logic__5406: RocketTile__GCB0,
-datapath__481: RocketTile__GCB0,
-reg__154: VCU118RocketSystem__GC0,
-reg__518: FPU__GB1,
-case__1201: VCU118RocketSystem__GC0,
-logic__3827: FPU__GB2,
-reg__428: RocketTile__GCB0,
-reg__182: VCU118RocketSystem__GC0,
-dsp48e1__14: APBGpsBlock__GC0,
-counter__2: genesys2_rocket_top__GC0,
-ram: VCU118RocketSystem__GC0,
-reg__1168: APBGpsBlock__GC0,
-case__1263: APBGpsBlock__GC0,
-logic__8947: tracking_wrapper,
-case__239: VCU118RocketSystem__GC0,
-logic__6757: VCU118RocketSystem__GC0,
-counter__23: APBGpsBlock__GC0,
-addsub__5: tracking_wrapper,
-case__459: VCU118RocketSystem__GC0,
-case__1588: tracking_wrapper,
-case__207: genesys2_rocket_top__GC0,
-reg__1391: tracking_wrapper,
-logic__4578: FPU__GB2, FPU__GB1,
-logic__610: genesys2_rocket_top__GC0,
-logic__7067: VCU118RocketSystem__GC0,
-datapath__93: VCU118RocketSystem__GC0,
-case__541: DCache,
-logic__6798: VCU118RocketSystem__GC0,
-logic__6547: RocketTile__GCB0,
-logic__8057: VCU118RocketSystem__GC0,
-logic__3276: RocketTile__GCB0,
-logic__129: genesys2_rocket_top__GC0,
-reg__710: RocketTile__GCB0,
-logic__7172: VCU118RocketSystem__GC0,
-TLDebugModuleInner: VCU118RocketSystem__GC0,
-logic__3830: FPU__GB2,
-logic__1063: VCU118RocketSystem__GC0,
-datapath__312: FPU__GB1,
-logic__5906: RocketTile__GCB0,
-datapath__365: FPU__GB1,
-case__1125: VCU118RocketSystem__GC0,
-datapath__124: VCU118RocketSystem__GC0,
-logic__1583: VCU118RocketSystem__GC0,
-reg__773: RocketTile__GCB0,
-logic__3326: FPU__GB1,
-datapath__575: APBGpsBlock__GC0,
-logic__8049: VCU118RocketSystem__GC0,
-reg__1004: VCU118RocketSystem__GC0,
-datapath__33: VCU118RocketSystem__GC0,
-logic__9129: tracking_wrapper,
-datapath__340: FPU__GB2,
-reg__943: VCU118RocketSystem__GC0,
-case__878: RocketTile__GCB0,
-logic__230: genesys2_rocket_top__GC0,
-logic__625: genesys2_rocket_top__GC0,
-dsp48e1__36: tracking_wrapper,
-case__570: DCache,
-logic__5362: RocketTile__GCB0,
-case__849: RocketTile__GCB0,
-logic__3537: FPU__GB1,
-case__471: VCU118RocketSystem__GC0,
-datapath__451: RocketTile__GCB0,
-logic__4163: FPU__GB1,
-logic__4389: FPU__GB1,
-reg__125: VCU118RocketSystem__GC0,
-logic: genesys2_rocket_top__GC0,
-logic__4789: FPU__GB2,
-logic__9566: APBGpsBlock__GC0,
-logic__3892: FPU__GB2,
-logic__6668: RocketTile__GCB0,
-logic__9159: tracking_wrapper,
-reg__40: genesys2_rocket_top__GC0,
-logic__9458: tracking_wrapper,
-logic__5149: RocketTile__GCB0,
-datapath__487: TilePRCIDomain__GC0,
-logic__9355: tracking_wrapper,
-datapath__169: VCU118RocketSystem__GC0,
-datapath__154: VCU118RocketSystem__GC0,
-reg__446: RocketTile__GCB0,
-reg__417: RocketTile__GCB0,
-logic__5856: RocketTile__GCB0,
-case__462: VCU118RocketSystem__GC0,
-case__1148: VCU118RocketSystem__GC0,
-reg__1000: VCU118RocketSystem__GC0,
-logic__1304: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2739: DCache,
-reg__1160: APBGpsBlock__GC0,
-case__160: genesys2_rocket_top__GC0,
-logic__8904: tracking_wrapper,
-logic__2620: DCache,
-case__929: RocketTile__GCB0,
-case__715: FPU__GB1,
-reg__1280: tracking_wrapper,
-logic__3932: FPU__GB2,
-logic__7228: VCU118RocketSystem__GC0,
-logic__6153: RocketTile__GCB0,
-datapath__672: tracking_wrapper,
-logic__3313: RocketTile__GCB0,
-logic__8806: APBGpsBlock__GC0,
-datapath__438: RocketTile__GCB0,
-logic__6884: VCU118RocketSystem__GC0,
-logic__3327: FPU__GB1,
-logic__5535: RocketTile__GCB0,
-case__908: RocketTile__GCB0,
-logic__4415: FPU__GB1,
-logic__8788: APBGpsBlock__GC0,
-reg__489: FPU__GB1,
-logic__9269: tracking_wrapper,
-reg__1118: APBGpsBlock__GC0,
-case__563: DCache,
-logic__4938: FPU__GB1,
-reg__1062: VCU118RocketSystem__GC0,
-reg__557: FPU__GB1,
-muxpart__156: genesys2_rocket_top__GC0,
-reg__983: VCU118RocketSystem__GC0,
-logic__6759: VCU118RocketSystem__GC0,
-case__1400: APBGpsBlock__GC0,
-reg__381: RocketTile__GCB0,
-logic__959: VCU118RocketSystem__GC0,
-muxpart__381: tracking_wrapper,
-reg__903: VCU118RocketSystem__GC0,
-case__194: genesys2_rocket_top__GC0,
-logic__7170: VCU118RocketSystem__GC0,
-fft_radix_2__parameterized0: APBGpsBlock__GC0,
-reg__782: RocketTile__GCB0,
-logic__6768: VCU118RocketSystem__GC0,
-logic__3332: FPU__GB1,
-logic__4968: FPU__GB1,
-reg__1093: APBGpsBlock__GC0,
-logic__2438: DCache,
-logic__7002: VCU118RocketSystem__GC0,
-logic__6906: VCU118RocketSystem__GC0,
-datapath__183: VCU118RocketSystem__GC0,
-datapath__122: VCU118RocketSystem__GC0,
-logic__4253: FPU__GB1,
-case__1624: tracking_wrapper,
-logic__1578: VCU118RocketSystem__GC0,
-case__244: VCU118RocketSystem__GC0,
-logic__4653: FPU__GB2,
-reg__293: VCU118RocketSystem__GC0,
-logic__6146: RocketTile__GCB0,
-case__1508: APBGpsBlock__GC0,
-case__755: FPU__GB2,
-logic__7915: VCU118RocketSystem__GC0,
-reg__380: RocketTile__GCB0,
-logic__2521: RocketTile__GCB0, DCache,
-logic__3819: FPU__GB2,
-case__1005: VCU118RocketSystem__GC0,
-logic__7406: VCU118RocketSystem__GC0,
-logic__6855: VCU118RocketSystem__GC0,
-case__609: RocketTile__GCB0,
-case__231: VCU118RocketSystem__GC0,
-logic__602: genesys2_rocket_top__GC0,
-logic__5404: RocketTile__GCB0,
-logic__2625: DCache,
-datapath__189: VCU118RocketSystem__GC0,
-NCO_code: tracking_wrapper,
-logic__1788: VCU118RocketSystem__GC0,
-logic__1505: VCU118RocketSystem__GC0,
-case__280: VCU118RocketSystem__GC0,
-datapath__76: VCU118RocketSystem__GC0,
-logic__3588: FPU__GB2, FPU__GB1,
-datapath__26: genesys2_rocket_top__GC0,
-logic__7231: VCU118RocketSystem__GC0,
-logic__4949: FPU__GB1,
-case__1298: APBGpsBlock__GC0,
-logic__3272: RocketTile__GCB0,
-case__196: genesys2_rocket_top__GC0,
-AsyncQueueSink_TLBundleD_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-reg__743: RocketTile__GCB0,
-case__1575: tracking_wrapper,
-ITLB: RocketTile__GCB0,
-logic__4082: FPU__GB2,
-case__1542: tracking_wrapper,
-logic__3557: FPU__GB1,
-reg__1384: tracking_wrapper,
-logic__6348: RocketTile__GCB0,
-case__1167: VCU118RocketSystem__GC0,
-logic__1609: VCU118RocketSystem__GC0,
-case__1110: VCU118RocketSystem__GC0,
-datapath__518: VCU118RocketSystem__GC0,
-logic__1780: VCU118RocketSystem__GC0,
-logic__1854: VCU118RocketSystem__GC0,
-logic__4598: FPU__GB2, FPU__GB1,
-reg__1157: APBGpsBlock__GC0,
-logic__1430: VCU118RocketSystem__GC0,
-logic__87: genesys2_rocket_top__GC0,
-reg__719: RocketTile__GCB0,
-reg__949: VCU118RocketSystem__GC0,
-logic__1118: VCU118RocketSystem__GC0,
-reg__230: VCU118RocketSystem__GC0,
-logic__3053: RocketTile__GCB0,
-logic__7831: VCU118RocketSystem__GC0,
-logic__7751: VCU118RocketSystem__GC0,
-case__855: RocketTile__GCB0,
-reg__167: VCU118RocketSystem__GC0,
-logic__4264: FPU__GB1,
-logic__3797: FPU__GB2,
-case__887: RocketTile__GCB0,
-reg__970: VCU118RocketSystem__GC0,
-logic__7895: VCU118RocketSystem__GC0,
-reg__973: VCU118RocketSystem__GC0,
-logic__6147: RocketTile__GCB0,
-logic__2991: RocketTile__GCB0,
-logic__5485: RocketTile__GCB0,
-logic__6701: RocketTile__GCB0,
-logic__7466: VCU118RocketSystem__GC0,
-logic__7399: VCU118RocketSystem__GC0,
-datapath__585: APBGpsBlock__GC0,
-logic__3346: FPU__GB1,
-logic__6531: RocketTile__GCB0,
-logic__8047: VCU118RocketSystem__GC0,
-logic__6052: RocketTile__GCB0,
-logic__337: genesys2_rocket_top__GC0,
-dsp48e1__35: tracking_wrapper,
-logic__7376: VCU118RocketSystem__GC0,
-datapath__36: VCU118RocketSystem__GC0,
-reg__1021: VCU118RocketSystem__GC0,
-logic__1620: VCU118RocketSystem__GC0,
-logic__2813: DCache,
-logic__4915: FPU__GB2,
-reg__1194: APBGpsBlock__GC0,
-logic__7201: VCU118RocketSystem__GC0,
-logic__554: genesys2_rocket_top__GC0,
-reg__20: genesys2_rocket_top__GC0,
-logic__7222: VCU118RocketSystem__GC0,
-logic__6817: VCU118RocketSystem__GC0,
-logic__9542: APBGpsBlock__GC0,
-dsp48e1__24: APBGpsBlock__GC0,
-reg__1014: VCU118RocketSystem__GC0,
-reg__838: RocketTile__GCB0,
-logic__8028: VCU118RocketSystem__GC0,
-logic__5441: RocketTile__GCB0,
-logic__4294: FPU__GB1,
-muxpart__126: genesys2_rocket_top__GC0,
-muxpart__23: genesys2_rocket_top__GC0,
-ClockCrossingReg_w43: VCU118RocketSystem__GC0,
-reg__1267: tracking_wrapper,
-logic__2648: DCache,
-logic__8236: VCU118RocketSystem__GC0,
-case__477: VCU118RocketSystem__GC0,
-logic__5293: RocketTile__GCB0,
-case__458: VCU118RocketSystem__GC0,
-datapath__95: VCU118RocketSystem__GC0,
-reg__1111: APBGpsBlock__GC0,
-reg__867: TilePRCIDomain__GC0,
-logic__5094: FPU__GB1,
-reg__1365: tracking_wrapper,
-reg__956: VCU118RocketSystem__GC0,
-case__671: FPU__GB2,
-case__1679: tracking_wrapper,
-reg__426: RocketTile__GCB0,
-logic__6867: VCU118RocketSystem__GC0,
-logic__6338: RocketTile__GCB0,
-logic__2227: DCache,
-logic__5886: RocketTile__GCB0,
-logic__1155: VCU118RocketSystem__GC0,
-logic__7275: VCU118RocketSystem__GC0,
-logic__1267: VCU118RocketSystem__GC0,
-logic__628: genesys2_rocket_top__GC0,
-case__1168: VCU118RocketSystem__GC0,
-logic__2129: RocketTile__GCB0,
-logic__611: genesys2_rocket_top__GC0,
-muxpart__48: genesys2_rocket_top__GC0,
-reg__45: genesys2_rocket_top__GC0,
-case__388: VCU118RocketSystem__GC0,
-logic__6618: RocketTile__GCB0,
-logic__3340: FPU__GB1,
-logic__3017: RocketTile__GCB0,
-logic__8059: VCU118RocketSystem__GC0,
-logic__3475: FPU__GB1,
-case__1565: tracking_wrapper,
-reg__351: DCache,
-logic__9208: tracking_wrapper,
-dsp48e1__42: tracking_wrapper,
-muxpart__181: FPU__GB0,
-logic__6114: RocketTile__GCB0,
-logic__1246: VCU118RocketSystem__GC0,
-case__1634: tracking_wrapper,
-logic__3028: RocketTile__GCB0,
-logic__6296: RocketTile__GCB0,
-datapath__190: VCU118RocketSystem__GC0,
-dsp48e1__13: APBGpsBlock__GC0,
-logic__9370: tracking_wrapper,
-datapath__19: genesys2_rocket_top__GC0,
-reg__644: FPU__GB1,
-logic__1603: VCU118RocketSystem__GC0,
-logic__8281: VCU118RocketSystem__GC0,
-case__161: genesys2_rocket_top__GC0,
-case__1709: tracking_wrapper,
-logic__3447: FPU__GB1,
-ram__2: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__1295: tracking_wrapper,
-logic__1160: VCU118RocketSystem__GC0,
-logic__3321: FPU__GB1,
-logic__5202: RocketTile__GCB0,
-case__899: RocketTile__GCB0,
-muxpart__63: genesys2_rocket_top__GC0,
-case__274: VCU118RocketSystem__GC0,
-reg__837: RocketTile__GCB0,
-logic__6640: RocketTile__GCB0,
-logic__8030: VCU118RocketSystem__GC0,
-datapath__246: VCU118RocketSystem__GC0,
-case__915: RocketTile__GCB0,
-logic__5713: RocketTile__GCB0,
-logic__7538: VCU118RocketSystem__GC0,
-logic__3907: FPU__GB2,
-logic__4577: FPU__GB2, FPU__GB1,
-muxpart__343: APBGpsBlock__GC0,
-logic__1638: VCU118RocketSystem__GC0,
-datapath__145: VCU118RocketSystem__GC0,
-reg__1397: tracking_wrapper,
-logic__4652: FPU__GB2,
-logic__2534: RocketTile__GCB0, DCache,
-logic__7034: VCU118RocketSystem__GC0,
-logic__2094: RocketTile__GCB0,
-logic__9372: tracking_wrapper,
-reg__83: genesys2_rocket_top__GC0,
-logic__1980: VCU118RocketSystem__GC0,
-FPU__GB2: FPU__GB2,
-logic__8864: APBGpsBlock__GC0,
-logic__1294: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__963: RocketTile__GCB0,
-logic__3611: FPU__GB2, FPU__GB1,
-logic__2917: DCache,
-reg__770: RocketTile__GCB0,
-reg__139: VCU118RocketSystem__GC0,
-datapath__466: RocketTile__GCB0,
-datapath__590: APBGpsBlock__GC0,
-reg__514: FPU__GB1,
-muxpart__28: genesys2_rocket_top__GC0,
-reg__901: VCU118RocketSystem__GC0,
-datapath__491: VCU118RocketSystem__GC0,
-reg__1137: APBGpsBlock__GC0,
-logic__3804: FPU__GB2,
-logic__5938: RocketTile__GCB0,
-logic__7711: VCU118RocketSystem__GC0,
-logic__9423: tracking_wrapper,
-reg__386: RocketTile__GCB0,
-logic__2458: DCache,
-case__288: VCU118RocketSystem__GC0,
-logic__4413: FPU__GB1,
-case__41: genesys2_rocket_top__GC0,
-logic__8070: VCU118RocketSystem__GC0,
-case__1101: VCU118RocketSystem__GC0,
-logic__5410: RocketTile__GCB0,
-reg__754: RocketTile__GCB0,
-counter__17: APBGpsBlock__GC0,
-datapath__507: VCU118RocketSystem__GC0,
-reg__699: RocketTile__GCB0,
-cordic_atan_one_stage: tracking_wrapper,
-reg__57: genesys2_rocket_top__GC0,
-logic__7111: VCU118RocketSystem__GC0,
-logic__1982: VCU118RocketSystem__GC0,
-logic__9397: tracking_wrapper,
-datapath__371: FPU__GB1,
-case__310: VCU118RocketSystem__GC0,
-case__426: VCU118RocketSystem__GC0,
-case__746: FPU__GB2,
-logic__7212: VCU118RocketSystem__GC0,
-case__543: DCache,
-logic__4205: FPU__GB1,
-logic__331: genesys2_rocket_top__GC0,
-logic__7263: VCU118RocketSystem__GC0,
-case__711: FPU__GB1,
-reg__938: VCU118RocketSystem__GC0,
-reg__708: RocketTile__GCB0,
-logic__5958: RocketTile__GCB0,
-logic__6009: RocketTile__GCB0,
-case__109: genesys2_rocket_top__GC0,
-logic__7364: VCU118RocketSystem__GC0,
-logic__3870: FPU__GB2,
-logic__2434: DCache,
-logic__661: genesys2_rocket_top__GC0,
-reg__968: VCU118RocketSystem__GC0,
-muxpart__377: tracking_wrapper,
-reg__1246: tracking_wrapper,
-case__1259: APBGpsBlock__GC0,
-case__27: genesys2_rocket_top__GC0,
-logic__3246: RocketTile__GCB0,
-logic__248: genesys2_rocket_top__GC0,
-case__14: genesys2_rocket_top__GC0,
-reg__992: VCU118RocketSystem__GC0,
-logic__6763: VCU118RocketSystem__GC0,
-logic__1804: VCU118RocketSystem__GC0,
-logic__5944: RocketTile__GCB0,
-logic__1965: VCU118RocketSystem__GC0,
-logic__9189: tracking_wrapper,
-logic__7837: VCU118RocketSystem__GC0,
-logic__3032: RocketTile__GCB0,
-reg__946: VCU118RocketSystem__GC0,
-logic__1131: VCU118RocketSystem__GC0,
-logic__754: VCU118RocketSystem__GC0,
-logic__5305: RocketTile__GCB0,
-case__586: RocketTile__GCB0,
-case__1299: APBGpsBlock__GC0,
-logic__6344: RocketTile__GCB0,
-muxpart__54: genesys2_rocket_top__GC0,
-datapath__548: APBGpsBlock__GC0,
-datapath__441: RocketTile__GCB0,
-muxpart__345: APBGpsBlock__GC0,
-logic__2046: VCU118RocketSystem__GC0,
-logic__1573: VCU118RocketSystem__GC0,
-logic__8874: APBGpsBlock__GC0,
-ram_2x99: VCU118RocketSystem__GC0,
-case__389: VCU118RocketSystem__GC0,
-ram__7: TilePRCIDomain__GC0,
-reg__18: genesys2_rocket_top__GC0,
-logic__1535: VCU118RocketSystem__GC0,
-logic__1086: VCU118RocketSystem__GC0,
-reg__632: FPU__GB1,
-logic__4425: FPU__GB1,
-logic__3946: FPU__GB2,
-case__126: genesys2_rocket_top__GC0,
-logic__3734: FPU__GB2,
-logic__3886: FPU__GB2,
-case__181: genesys2_rocket_top__GC0,
-reg__623: FPU__GB1,
-logic__2422: DCache,
-reg__106: genesys2_rocket_top__GC0,
-logic__934: VCU118RocketSystem__GC0,
-logic__854: VCU118RocketSystem__GC0,
-logic__1608: VCU118RocketSystem__GC0,
-logic__7684: VCU118RocketSystem__GC0,
-reg__613: FPU__GB1,
-logic__6140: RocketTile__GCB0,
-logic__3060: RocketTile__GCB0,
-logic__4559: FPU__GB2, FPU__GB1,
-TLFragmenter_FPGAUART: VCU118RocketSystem__GC0,
-case__132: genesys2_rocket_top__GC0,
-case__708: FPU__GB1,
-datapath__73: VCU118RocketSystem__GC0,
-reg__707: RocketTile__GCB0,
-reg__238: VCU118RocketSystem__GC0,
-logic__1524: VCU118RocketSystem__GC0,
-reg__133: VCU118RocketSystem__GC0,
-logic__1988: VCU118RocketSystem__GC0,
-muxpart__378: tracking_wrapper,
-logic__259: genesys2_rocket_top__GC0,
-logic__9330: tracking_wrapper,
-case__1340: APBGpsBlock__GC0,
-reg__1041: VCU118RocketSystem__GC0,
-reg__1272: tracking_wrapper,
-reg__561: FPU__GB1,
-case__648: FPU__GB1,
-case__1026: VCU118RocketSystem__GC0,
-spill_register: tracking_wrapper,
-logic__3657: FPU__GB2, FPU__GB1,
-case__633: RocketTile__GCB0,
-logic__250: genesys2_rocket_top__GC0,
-keep__3: genesys2_rocket_top__GC0,
-logic__1840: VCU118RocketSystem__GC0,
-reg__178: VCU118RocketSystem__GC0,
-case__327: VCU118RocketSystem__GC0,
-reg__1161: APBGpsBlock__GC0,
-case__1180: VCU118RocketSystem__GC0,
-case__871: RocketTile__GCB0,
-reg__913: VCU118RocketSystem__GC0,
-TLBuffer_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-case__1106: VCU118RocketSystem__GC0,
-logic__7116: VCU118RocketSystem__GC0,
-logic__6871: VCU118RocketSystem__GC0,
-logic__2414: DCache,
-logic__5409: RocketTile__GCB0,
-reg__1117: APBGpsBlock__GC0,
-datapath__292: RocketTile__GCB0,
-case__158: genesys2_rocket_top__GC0,
-reg__486: FPU__GB0,
-datapath__271: DCache,
-datapath__15: genesys2_rocket_top__GC0,
-reg__345: DCache,
-logic__4468: FPU__GB1,
-reg__1052: VCU118RocketSystem__GC0,
-reg__383: RocketTile__GCB0,
-logic__1733: VCU118RocketSystem__GC0,
-logic__3005: RocketTile__GCB0,
-logic__7086: VCU118RocketSystem__GC0,
-case__799: FPU__GB1,
-logic__9529: APBGpsBlock__GC0,
-logic__3123: RocketTile__GCB0,
-logic__8400: APBGpsBlock__GC0,
-logic__5960: RocketTile__GCB0,
-logic__2433: DCache,
-logic__5198: RocketTile__GCB0,
-case__595: RocketTile__GCB0,
-datapath__251: VCU118RocketSystem__GC0,
-reg__1416: tracking_wrapper,
-logic__1001: VCU118RocketSystem__GC0,
-logic__6711: RocketTile__GCB0,
-muxpart__210: FPU__GB0,
-logic__8508: APBGpsBlock__GC0,
-case__229: VCU118RocketSystem__GC0,
-logic__2641: DCache,
-muxpart__24: genesys2_rocket_top__GC0,
-datapath__500: VCU118RocketSystem__GC0,
-datapath__309: RocketTile__GCB0,
-logic__8819: APBGpsBlock__GC0,
-case__1685: tracking_wrapper,
-reg__100: genesys2_rocket_top__GC0,
-logic__3832: FPU__GB2,
-logic__3119: RocketTile__GCB0,
-logic__6055: RocketTile__GCB0,
-datapath__396: FPU__GB2,
-reg__409: RocketTile__GCB0,
-dsp48e1__19: APBGpsBlock__GC0,
-case__682: FPU__GB2,
-logic__4404: FPU__GB1,
-acq_ca_gen: APBGpsBlock__GC0,
-reg__363: DCache,
-logic__9158: tracking_wrapper,
-logic__9090: tracking_wrapper,
-rom__7: tracking_wrapper,
-reg__513: FPU__GB1,
-reg__947: VCU118RocketSystem__GC0,
-case__1285: APBGpsBlock__GC0,
-logic__7696: VCU118RocketSystem__GC0,
-logic__5375: RocketTile__GCB0,
-case__1192: VCU118RocketSystem__GC0,
-logic__4476: FPU__GB1,
-logic__2553: DCache,
-reg__401: RocketTile__GCB0,
-datapath__424: RocketTile__GCB0,
-reg__1242: tracking_wrapper,
-case__1008: VCU118RocketSystem__GC0,
-logic__9261: tracking_wrapper,
-logic__771: VCU118RocketSystem__GC0,
-case__625: RocketTile__GCB0,
-reg__1383: tracking_wrapper,
-case__895: RocketTile__GCB0,
-logic__2214: DCache,
-logic__1580: VCU118RocketSystem__GC0,
-datapath__372: FPU__GB1,
-logic__1413: VCU118RocketSystem__GC0,
-logic__3070: RocketTile__GCB0,
-logic__2001: VCU118RocketSystem__GC0,
-logic__6754: VCU118RocketSystem__GC0,
-logic__6957: VCU118RocketSystem__GC0,
-logic__2777: DCache,
-logic__3855: FPU__GB2,
-datapath__45: VCU118RocketSystem__GC0,
-logic__9152: tracking_wrapper,
-logic__5207: RocketTile__GCB0,
-logic__5055: FPU__GB1,
-datapath__483: RocketTile__GCB0,
-case__1481: APBGpsBlock__GC0,
-datapath__285: DCache,
-logic__2769: DCache,
-logic__1610: VCU118RocketSystem__GC0,
-logic__7300: VCU118RocketSystem__GC0,
-case__1073: VCU118RocketSystem__GC0,
-reg__697: RocketTile__GCB0,
-PMPChecker_s2: RocketTile__GCB0,
-reg__1222: tracking_wrapper,
-reg__609: FPU__GB2,
-logic__9100: tracking_wrapper,
-reg__546: FPU__GB1,
-case__577: RocketTile__GCB0,
-datapath__80: VCU118RocketSystem__GC0,
-logic__2476: RocketTile__GCB0, DCache,
-case__1210: VCU118RocketSystem__GC0,
-logic__9505: tracking_wrapper,
-datapath__412: FPU__GB1,
-logic__7423: VCU118RocketSystem__GC0,
-logic__1593: VCU118RocketSystem__GC0,
-logic__4417: FPU__GB1,
-logic__612: genesys2_rocket_top__GC0,
-logic__7960: VCU118RocketSystem__GC0,
-logic__935: VCU118RocketSystem__GC0,
-logic__2602: DCache,
-logic__3536: FPU__GB1,
-reg__1209: APBGpsBlock__GC0,
-logic__9565: APBGpsBlock__GC0,
-reg__601: FPU__GB2,
-datapath__645: tracking_wrapper,
-logic__5296: RocketTile__GCB0,
-logic__3613: FPU__GB2, FPU__GB1,
-case__188: genesys2_rocket_top__GC0,
-logic__140: genesys2_rocket_top__GC0,
-logic__8274: VCU118RocketSystem__GC0,
-logic__824: VCU118RocketSystem__GC0,
-logic__4651: FPU__GB2,
-reg__972: VCU118RocketSystem__GC0,
-logic__3513: FPU__GB1,
-datapath__554: APBGpsBlock__GC0,
-logic__1784: VCU118RocketSystem__GC0,
-reg__444: RocketTile__GCB0,
-muxpart__383: tracking_wrapper,
-logic__2090: RocketTile__GCB0,
-reg__312: VCU118RocketSystem__GC0,
-logic__7045: VCU118RocketSystem__GC0,
-reg__187: VCU118RocketSystem__GC0,
-reg__856: RocketTile__GCB0,
-logic__1334: VCU118RocketSystem__GC0,
-logic__3717: FPU__GB2,
-case__596: RocketTile__GCB0,
-keep__16: tracking_wrapper,
-muxpart__207: FPU__GB0,
-logic__5119: FPU__GB1,
-logic__2143: RocketTile__GCB0,
-logic__3429: FPU__GB1,
-case__779: FPU__GB1,
-logic__4104: FPU__GB2,
-datapath__535: VCU118RocketSystem__GC0,
-logic__1623: VCU118RocketSystem__GC0,
-muxpart__72: genesys2_rocket_top__GC0,
-datapath__308: RocketTile__GCB0,
-logic__4029: FPU__GB2,
-reg__540: FPU__GB1,
-logic__4095: FPU__GB2,
-case__1143: VCU118RocketSystem__GC0,
-datapath__213: VCU118RocketSystem__GC0,
-datapath__166: VCU118RocketSystem__GC0,
-case__461: VCU118RocketSystem__GC0,
-logic__6917: VCU118RocketSystem__GC0,
-reg__896: VCU118RocketSystem__GC0,
-muxpart__200: FPU__GB0,
-logic__6939: VCU118RocketSystem__GC0,
-logic__4298: FPU__GB1,
-logic__5041: FPU__GB1,
-case__1665: tracking_wrapper,
-case__529: DCache,
-case__1269: APBGpsBlock__GC0,
-datapath__446: RocketTile__GCB0,
-logic__9518: APBGpsBlock__GC0,
-case__466: VCU118RocketSystem__GC0,
-logic__9273: tracking_wrapper,
-reg__886: VCU118RocketSystem__GC0,
-reg__248: VCU118RocketSystem__GC0,
-logic__7022: VCU118RocketSystem__GC0,
-logic__6877: VCU118RocketSystem__GC0,
-logic__6796: VCU118RocketSystem__GC0,
-logic__8792: APBGpsBlock__GC0,
-reg__1003: VCU118RocketSystem__GC0,
-reg__208: VCU118RocketSystem__GC0,
-logic__2382: DCache,
-logic__4837: FPU__GB2,
-reg__745: RocketTile__GCB0,
-reg__1104: APBGpsBlock__GC0,
-muxpart__360: tracking_wrapper,
-case__729: FPU__GB2, FPU__GB1,
-logic__8673: APBGpsBlock__GC0,
-case__879: RocketTile__GCB0,
-logic__9014: tracking_wrapper,
-logic__5619: RocketTile__GCB0,
-logic__8171: VCU118RocketSystem__GC0,
-logic__254: genesys2_rocket_top__GC0,
-reg__682: RocketTile__GCB0,
-logic__1309: VCU118RocketSystem__GC0,
-case__706: FPU__GB1,
-logic__1239: VCU118RocketSystem__GC0,
-reg__520: FPU__GB1,
-logic__5991: RocketTile__GCB0,
-reg__150: VCU118RocketSystem__GC0,
-logic__4181: FPU__GB1,
-logic__7559: VCU118RocketSystem__GC0,
-case__1505: APBGpsBlock__GC0,
-logic__1352: VCU118RocketSystem__GC0,
-logic__997: VCU118RocketSystem__GC0,
-logic__834: VCU118RocketSystem__GC0,
-logic__6083: RocketTile__GCB0,
-datapath__313: FPU__GB1,
-reg__1141: APBGpsBlock__GC0,
-datapath__678: tracking_wrapper,
-muxpart__32: genesys2_rocket_top__GC0,
-case__490: RocketTile__GCB0,
-logic__1992: VCU118RocketSystem__GC0,
-logic__1930: VCU118RocketSystem__GC0,
-logic__9385: tracking_wrapper,
-logic__4196: FPU__GB1,
-logic__1019: VCU118RocketSystem__GC0,
-reg__1421: tracking_wrapper,
-logic__3699: FPU__GB2,
-logic__1276: VCU118RocketSystem__GC0,
-case__7: genesys2_rocket_top__GC0,
-logic__3853: FPU__GB2,
-case__896: RocketTile__GCB0,
-reg__1037: VCU118RocketSystem__GC0,
-reg__897: VCU118RocketSystem__GC0,
-datapath__341: FPU__GB2,
-case__475: VCU118RocketSystem__GC0,
-datapath__402: FPU__GB2,
-logic__8056: VCU118RocketSystem__GC0,
-logic__7622: VCU118RocketSystem__GC0,
-logic__2243: DCache,
-muxpart__12: genesys2_rocket_top__GC0,
-case__1009: VCU118RocketSystem__GC0,
-logic__1977: VCU118RocketSystem__GC0,
-logic__5018: FPU__GB1,
-reg__1317: tracking_wrapper,
-logic__6951: VCU118RocketSystem__GC0,
-case__463: VCU118RocketSystem__GC0,
-reg__188: VCU118RocketSystem__GC0,
-logic__1080: VCU118RocketSystem__GC0,
-logic__750: VCU118RocketSystem__GC0,
-reg__509: FPU__GB1,
-logic__1755: VCU118RocketSystem__GC0,
-reg__1258: tracking_wrapper,
-logic__5601: RocketTile__GCB0,
-datapath__683: tracking_wrapper,
-reg__739: RocketTile__GCB0,
-logic__5049: FPU__GB1,
-logic__5279: RocketTile__GCB0,
-reg__1313: tracking_wrapper,
-reg__1344: tracking_wrapper,
-logic__6948: VCU118RocketSystem__GC0,
-logic__2650: DCache,
-logic__7093: VCU118RocketSystem__GC0,
-RoundAnyRawFNToRecFN: FPU__GB2, FPU__GB1,
-reg__1244: tracking_wrapper,
-case__1398: APBGpsBlock__GC0,
-reg__1067: VCU118RocketSystem__GC0,
-muxpart__237: FPU__GB0,
-case__504: RocketTile__GCB0,
-muxpart__41: genesys2_rocket_top__GC0,
-RoundRawFNToRecFN: FPU__GB2, FPU__GB1,
-logic__173: genesys2_rocket_top__GC0,
-logic__1273: VCU118RocketSystem__GC0,
-case__1617: tracking_wrapper,
-reg__28: genesys2_rocket_top__GC0,
-logic__288: genesys2_rocket_top__GC0,
-case__685: FPU__GB2,
-logic__3850: FPU__GB2,
-logic__8966: tracking_wrapper,
-logic__3050: RocketTile__GCB0,
-reg__85: genesys2_rocket_top__GC0,
-logic__5428: RocketTile__GCB0,
-case__970: RocketTile__GCB0,
-addsub__3: tracking_wrapper,
-logic__7521: VCU118RocketSystem__GC0,
-case__1541: tracking_wrapper,
-datapath__644: tracking_wrapper,
-reg__1399: tracking_wrapper,
-case__1288: APBGpsBlock__GC0,
-logic__3245: RocketTile__GCB0,
-logic__6904: VCU118RocketSystem__GC0,
-datapath__348: FPU__GB2,
-datapath__164: VCU118RocketSystem__GC0,
-case__112: genesys2_rocket_top__GC0,
-case__485: VCU118RocketSystem__GC0,
-reg__389: RocketTile__GCB0,
-logic__5681: RocketTile__GCB0,
-logic__1234: VCU118RocketSystem__GC0,
-logic__2375: DCache,
-logic__6811: VCU118RocketSystem__GC0,
-case__407: VCU118RocketSystem__GC0,
-logic__5796: RocketTile__GCB0,
-logic__5551: RocketTile__GCB0,
-case__186: genesys2_rocket_top__GC0,
-case__329: VCU118RocketSystem__GC0,
-logic__3039: RocketTile__GCB0,
-logic__2370: DCache,
-case__982: RocketTile__GCB0,
-datapath__685: tracking_wrapper,
-logic__4130: FPU__GB2,
-case__995: VCU118RocketSystem__GC0,
-reg__1105: APBGpsBlock__GC0,
-case__325: VCU118RocketSystem__GC0,
-case__228: VCU118RocketSystem__GC0,
-logic__2649: DCache,
-case__1479: APBGpsBlock__GC0,
-case__1532: APBGpsBlock__GC0,
-reg__1068: VCU118RocketSystem__GC0,
-case__640: RocketTile__GCB0,
-logic__4250: FPU__GB1,
-logic__2096: RocketTile__GCB0,
-logic__4520: FPU__GB2, FPU__GB1,
-logic__4206: FPU__GB1,
-logic__4051: FPU__GB2,
-logic__3930: FPU__GB2,
-reg__298: VCU118RocketSystem__GC0,
-Queue1_TLBundleA_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__844: VCU118RocketSystem__GC0,
-datapath__484: RocketTile__GCB0,
-reg__622: FPU__GB1,
-logic__5547: RocketTile__GCB0,
-logic__8940: tracking_wrapper,
-reg__976: VCU118RocketSystem__GC0,
-logic__7389: VCU118RocketSystem__GC0,
-logic__8353: APBGpsBlock__GC0,
-datapath__668: tracking_wrapper,
-logic__8683: APBGpsBlock__GC0,
-reg__488: FPU__GB1,
-reg__147: VCU118RocketSystem__GC0,
-datapath__423: RocketTile__GCB0,
-case__1585: tracking_wrapper,
-reg__268: VCU118RocketSystem__GC0,
-case__1439: APBGpsBlock__GC0,
-logic__1671: VCU118RocketSystem__GC0,
-datapath__119: VCU118RocketSystem__GC0,
-logic__5229: RocketTile__GCB0,
-logic__5520: RocketTile__GCB0,
-ClockGroupAggregator_cbus: VCU118RocketSystem__GC0,
-logic__604: genesys2_rocket_top__GC0,
-reg__890: VCU118RocketSystem__GC0,
-reg__1276: tracking_wrapper,
-logic__4786: FPU__GB2,
-case__1391: APBGpsBlock__GC0,
-logic__4123: FPU__GB2,
-logic__9017: tracking_wrapper,
-logic__6671: RocketTile__GCB0,
-reg__1354: tracking_wrapper,
-reg__862: RocketTile__GCB0,
-case__643: RocketTile__GCB0,
-case__1620: tracking_wrapper,
-counter__13: VCU118RocketSystem__GC0,
-case__415: VCU118RocketSystem__GC0,
-reg__346: DCache,
-reg__965: VCU118RocketSystem__GC0,
-logic__6874: VCU118RocketSystem__GC0,
-logic__1416: VCU118RocketSystem__GC0,
-datapath__697: tracking_wrapper,
-reg__990: VCU118RocketSystem__GC0,
-logic__1022: VCU118RocketSystem__GC0,
-case__802: FPU__GB1,
-case__1440: APBGpsBlock__GC0,
-datapath__129: VCU118RocketSystem__GC0,
-logic__5533: RocketTile__GCB0,
-case__1165: VCU118RocketSystem__GC0,
-logic__1042: VCU118RocketSystem__GC0,
-case__1342: APBGpsBlock__GC0,
-reg__840: RocketTile__GCB0,
-reg__1175: APBGpsBlock__GC0,
-case__642: RocketTile__GCB0,
-logic__8951: tracking_wrapper,
-reg__1178: APBGpsBlock__GC0,
-datapath__333: FPU__GB2,
-logic__112: genesys2_rocket_top__GC0,
-reg__162: VCU118RocketSystem__GC0,
-logic__3619: FPU__GB2, FPU__GB1,
-logic__9243: tracking_wrapper,
-reg__97: genesys2_rocket_top__GC0,
-datapath__272: DCache,
-case__190: genesys2_rocket_top__GC0,
-logic__393: genesys2_rocket_top__GC0,
-reg__1092: APBGpsBlock__GC0,
-case__221: genesys2_rocket_top__GC0,
-logic__7270: VCU118RocketSystem__GC0,
-logic__1013: VCU118RocketSystem__GC0,
-reg__250: VCU118RocketSystem__GC0,
-case__873: RocketTile__GCB0,
-case__938: RocketTile__GCB0,
-reg__474: FPU__GB0,
-logic__8810: APBGpsBlock__GC0,
-logic__266: genesys2_rocket_top__GC0,
-logic__7558: VCU118RocketSystem__GC0,
-case__1561: tracking_wrapper,
-logic__6643: RocketTile__GCB0,
-TLXbar_pbus_out_i1_o3_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-case__1663: tracking_wrapper,
-logic__1078: VCU118RocketSystem__GC0,
-datapath__10: genesys2_rocket_top__GC0,
-logic__9461: tracking_wrapper,
-case__716: FPU__GB1,
-logic__895: VCU118RocketSystem__GC0,
-case__725: FPU__GB2, FPU__GB1,
-case__1120: VCU118RocketSystem__GC0,
-logic__1018: VCU118RocketSystem__GC0,
-reg__885: VCU118RocketSystem__GC0,
-logic__2461: DCache,
-IntXbar_i1_o1: VCU118RocketSystem__GC0,
-logic__3860: FPU__GB2,
-logic__5200: RocketTile__GCB0,
-logic__8330: APBGpsBlock__GC0,
-TLBuffer_a32d64s2k1z3u: RocketTile__GCB0,
-datapath__544: VCU118RocketSystem__GC0,
-logic__6080: RocketTile__GCB0,
-reg__1300: tracking_wrapper,
-case__259: VCU118RocketSystem__GC0,
-reg__483: FPU__GB0,
-case__695: FPU__GB2,
-muxpart__77: genesys2_rocket_top__GC0,
-case__1091: VCU118RocketSystem__GC0,
-reg__703: RocketTile__GCB0,
-case__1721: tracking_wrapper,
-case__954: RocketTile__GCB0,
-rom: VCU118RocketSystem__GC0,
-case__691: FPU__GB2,
-reg__1347: tracking_wrapper,
-reg__15: genesys2_rocket_top__GC0,
-logic__2862: DCache,
-logic__3025: RocketTile__GCB0,
-logic__3178: RocketTile__GCB0,
-logic__5600: RocketTile__GCB0,
-logic__5549: RocketTile__GCB0,
-reg__1234: tracking_wrapper,
-logic__7393: VCU118RocketSystem__GC0,
-muxpart__209: FPU__GB0,
-logic__4888: FPU__GB2,
-logic__1454: VCU118RocketSystem__GC0,
-datapath__378: FPU__GB1,
-muxpart__37: genesys2_rocket_top__GC0,
-case__707: FPU__GB1,
-datapath__101: VCU118RocketSystem__GC0,
-case__1363: APBGpsBlock__GC0,
-logic__3695: FPU__GB1,
-reg__774: RocketTile__GCB0,
-case__890: RocketTile__GCB0,
-case__352: VCU118RocketSystem__GC0,
-datapath__368: FPU__GB1,
-case__1741: TLToAPB,
-logic__8412: APBGpsBlock__GC0,
-logic__5534: RocketTile__GCB0,
-logic__8472: APBGpsBlock__GC0,
-logic__6172: RocketTile__GCB0,
-logic__3788: FPU__GB2,
-datapath__709: tracking_wrapper,
-logic__8934: tracking_wrapper,
-logic__4646: FPU__GB2,
-muxpart__46: genesys2_rocket_top__GC0,
-muxpart__232: FPU__GB0,
-PMPChecker_s3: DCache,
-case__1390: APBGpsBlock__GC0,
-case__610: RocketTile__GCB0,
-reg__605: FPU__GB2,
-logic__4560: FPU__GB2, FPU__GB1,
-logic__2031: VCU118RocketSystem__GC0,
-reg__34: genesys2_rocket_top__GC0,
-logic__200: genesys2_rocket_top__GC0,
-logic__8931: tracking_wrapper,
-logic__4309: FPU__GB1,
-muxpart__153: genesys2_rocket_top__GC0,
-logic__9331: tracking_wrapper,
-case__1040: VCU118RocketSystem__GC0,
-logic__1389: VCU118RocketSystem__GC0,
-logic__6154: RocketTile__GCB0,
-datapath__176: VCU118RocketSystem__GC0,
-case__49: genesys2_rocket_top__GC0,
-logic__686: genesys2_rocket_top__GC0,
-case__1081: VCU118RocketSystem__GC0,
-case__1727: APBGpsBlock__GC0,
-logic__6596: RocketTile__GCB0,
-logic__1670: VCU118RocketSystem__GC0,
-reg__543: FPU__GB1,
-reg__508: FPU__GB1,
-case__1336: APBGpsBlock__GC0,
-logic__4782: FPU__GB2,
-logic__7813: VCU118RocketSystem__GC0,
-case__1286: APBGpsBlock__GC0,
-logic__915: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__925: RocketTile__GCB0,
-case__242: VCU118RocketSystem__GC0,
-case__738: FPU__GB2,
-logic__5155: RocketTile__GCB0,
-logic__7621: VCU118RocketSystem__GC0,
-case__311: VCU118RocketSystem__GC0,
-datapath__613: APBGpsBlock__GC0,
-case__105: genesys2_rocket_top__GC0,
-logic__3004: RocketTile__GCB0,
-logic__650: genesys2_rocket_top__GC0,
-reg__276: VCU118RocketSystem__GC0,
-case__523: DCache,
-case__809: FPU__GB1,
-logic__3329: FPU__GB1,
-case__1534: APBGpsBlock__GC0,
-case__736: FPU__GB2,
-case__1252: VCU118RocketSystem__GC0,
-logic__1526: VCU118RocketSystem__GC0,
-reg__1393: tracking_wrapper,
-reg__148: VCU118RocketSystem__GC0,
-logic__982: VCU118RocketSystem__GC0,
-reg__500: FPU__GB1,
-case__667: FPU__GB2,
-logic__4785: FPU__GB2,
-reg__1284: tracking_wrapper,
-datapath__485: RocketTile__GCB0,
-case__319: VCU118RocketSystem__GC0,
-datapath__360: FPU__GB1,
-case__115: genesys2_rocket_top__GC0,
-case__1536: APBGpsBlock__GC0,
-logic__15: genesys2_rocket_top__GC0,
-logic__825: VCU118RocketSystem__GC0,
-muxpart__172: FPU__GB0,
-case__224: genesys2_rocket_top__GC0,
-logic__7192: VCU118RocketSystem__GC0,
-reg__1026: VCU118RocketSystem__GC0,
-reg__1420: tracking_wrapper,
-logic__1740: VCU118RocketSystem__GC0,
-case__785: FPU__GB1,
-logic__1009: VCU118RocketSystem__GC0,
-logic__2519: RocketTile__GCB0, DCache,
-logic__9590: TLToAPB,
-case__1646: tracking_wrapper,
-logic__2016: VCU118RocketSystem__GC0,
-counter__32: tracking_wrapper,
-logic__9607: genesys2_rocket_top__GC0,
-case__448: VCU118RocketSystem__GC0,
-case__928: RocketTile__GCB0,
-logic__3531: FPU__GB1,
-reg__827: RocketTile__GCB0,
-logic__4732: FPU__GB2,
-logic__59: genesys2_rocket_top__GC0,
-reg__1114: APBGpsBlock__GC0,
-reg__78: genesys2_rocket_top__GC0,
-case__616: RocketTile__GCB0,
-logic__8276: VCU118RocketSystem__GC0,
-datapath__470: RocketTile__GCB0,
-reg__355: DCache,
-muxpart__40: genesys2_rocket_top__GC0,
-logic__7939: VCU118RocketSystem__GC0,
-case__398: VCU118RocketSystem__GC0,
-case__349: VCU118RocketSystem__GC0,
-reg__105: genesys2_rocket_top__GC0,
-logic__4402: FPU__GB1,
-counter__22: APBGpsBlock__GC0,
-logic__502: genesys2_rocket_top__GC0,
-reg__679: RocketTile__GCB0,
-reg__1320: tracking_wrapper,
-datapath__661: tracking_wrapper,
-TLBuffer_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__2638: DCache,
-logic__7100: VCU118RocketSystem__GC0,
-logic__2148: DCache,
-reg__1218: APBGpsBlock__GC0,
-logic__5611: RocketTile__GCB0,
-logic__8348: APBGpsBlock__GC0,
-logic__1214: VCU118RocketSystem__GC0,
-datapath__270: DCache,
-reg__722: RocketTile__GCB0,
-reg__853: RocketTile__GCB0,
-logic__2788: DCache,
-case__482: VCU118RocketSystem__GC0,
-logic__1927: VCU118RocketSystem__GC0,
-case__627: RocketTile__GCB0,
-reg__1011: VCU118RocketSystem__GC0,
-logic__4848: FPU__GB2,
-case__996: VCU118RocketSystem__GC0,
-logic__4532: FPU__GB2, FPU__GB1,
-logic__2226: DCache,
-datapath__43: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__3510: FPU__GB1,
-logic__9236: tracking_wrapper,
-logic__8196: VCU118RocketSystem__GC0,
-reg__643: FPU__GB1,
-logic__3225: RocketTile__GCB0,
-logic__1876: VCU118RocketSystem__GC0,
-datapath__287: RocketTile__GCB0,
-logic__9268: tracking_wrapper,
-logic__6988: VCU118RocketSystem__GC0,
-logic__8579: APBGpsBlock__GC0,
-logic__7187: VCU118RocketSystem__GC0,
-logic__2353: DCache,
-logic__2021: VCU118RocketSystem__GC0,
-logic__4427: FPU__GB1,
-logic__9193: tracking_wrapper,
-reg__510: FPU__GB1,
-datapath__322: FPU__GB2, FPU__GB1,
-logic__8504: APBGpsBlock__GC0,
-reg__747: RocketTile__GCB0,
-case__1543: tracking_wrapper,
-case__1556: tracking_wrapper,
-logic__3315: FPU__GB1,
-reg__25: genesys2_rocket_top__GC0,
-logic__7348: VCU118RocketSystem__GC0,
-logic__792: VCU118RocketSystem__GC0,
-logic__1637: VCU118RocketSystem__GC0,
-muxpart__158: VCU118RocketSystem__GC0,
-case__1264: APBGpsBlock__GC0,
-logic__4465: FPU__GB1,
-reg__1268: tracking_wrapper,
-case__283: VCU118RocketSystem__GC0,
-case__664: FPU__GB2, FPU__GB1,
-case__767: FPU__GB2,
-case__503: RocketTile__GCB0,
-case__690: FPU__GB2,
-reg__89: genesys2_rocket_top__GC0,
-logic__8043: VCU118RocketSystem__GC0,
-TLXbar_pbus_in_i1_o1_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__133: genesys2_rocket_top__GC0,
-reg__763: RocketTile__GCB0,
-reg__933: VCU118RocketSystem__GC0,
-logic__6682: RocketTile__GCB0,
-case__26: genesys2_rocket_top__GC0,
-logic__9157: tracking_wrapper,
-datapath__367: FPU__GB1,
-case__931: RocketTile__GCB0,
-twiddle_ram: APBGpsBlock__GC0,
-case__509: DCache,
-reg__804: RocketTile__GCB0,
-logic__6092: RocketTile__GCB0,
-case__212: genesys2_rocket_top__GC0,
-logic__1197: VCU118RocketSystem__GC0,
-reg__1414: tracking_wrapper,
-case__450: VCU118RocketSystem__GC0,
-logic__222: genesys2_rocket_top__GC0,
-case__528: DCache,
-case__1486: APBGpsBlock__GC0,
-reg__1381: tracking_wrapper,
-logic__2387: DCache,
-reg__597: FPU__GB2,
-logic__4319: FPU__GB1,
-logic__512: genesys2_rocket_top__GC0,
-logic__8066: VCU118RocketSystem__GC0,
-logic__2218: DCache,
-reg__664: FPU__GB1,
-reg__1303: tracking_wrapper,
-reg__1097: APBGpsBlock__GC0,
-logic__6030: RocketTile__GCB0,
-logic__9046: tracking_wrapper,
-case__1622: tracking_wrapper,
-datapath__261: RocketTile__GCB0,
-case__17: genesys2_rocket_top__GC0,
-logic__9558: APBGpsBlock__GC0,
-case__149: genesys2_rocket_top__GC0,
-datapath__148: VCU118RocketSystem__GC0,
-reg__854: RocketTile__GCB0,
-reg__1172: APBGpsBlock__GC0,
-logic__5459: RocketTile__GCB0,
-case__656: FPU__GB2, FPU__GB1,
-datapath__339: FPU__GB2,
-logic__5685: RocketTile__GCB0,
-logic__6024: RocketTile__GCB0,
-reg__1408: tracking_wrapper,
-logic__4101: FPU__GB2,
-logic__1571: VCU118RocketSystem__GC0,
-reg__449: RocketTile__GCB0,
-logic__4553: FPU__GB2, FPU__GB1,
-case__621: RocketTile__GCB0,
-logic__727: genesys2_rocket_top__GC0,
-logic__1186: VCU118RocketSystem__GC0,
-case__162: genesys2_rocket_top__GC0,
-case__495: RocketTile__GCB0,
-case__1330: APBGpsBlock__GC0,
-datapath__420: RocketTile__GCB0,
-logic__5532: RocketTile__GCB0,
-logic__8501: APBGpsBlock__GC0,
-reg__456: FPU__GB0,
-logic__3035: RocketTile__GCB0,
-case__1675: tracking_wrapper,
-logic__6497: RocketTile__GCB0,
-reg__442: RocketTile__GCB0,
-logic__8320: VCU118RocketSystem__GC0,
-logic__1572: VCU118RocketSystem__GC0,
-datapath__17: genesys2_rocket_top__GC0,
-logic__6722: RocketTile__GCB0,
-case__281: VCU118RocketSystem__GC0,
-datapath__366: FPU__GB1,
-logic__4098: FPU__GB2,
-logic__2875: DCache,
-datapath__325: FPU__GB2, FPU__GB1,
-muxpart__167: RocketTile__GCB0,
-case__1060: VCU118RocketSystem__GC0,
-logic__8326: APBGpsBlock__GC0,
-logic__910: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6744: VCU118RocketSystem__GC0,
-logic__9561: APBGpsBlock__GC0,
-reg__788: RocketTile__GCB0,
-logic__6676: RocketTile__GCB0,
-case__1243: VCU118RocketSystem__GC0,
-logic__9115: tracking_wrapper,
-logic__1576: VCU118RocketSystem__GC0,
-logic__9463: tracking_wrapper,
-logic__4361: FPU__GB1,
-logic__107: genesys2_rocket_top__GC0,
-case__1496: APBGpsBlock__GC0,
-reg__809: RocketTile__GCB0,
-muxpart__384: tracking_wrapper,
-case__1714: tracking_wrapper,
-logic__2295: DCache,
-muxpart__295: APBGpsBlock__GC0,
-logic__3618: FPU__GB2, FPU__GB1,
-case__1037: VCU118RocketSystem__GC0,
-logic__8680: APBGpsBlock__GC0,
-logic__767: VCU118RocketSystem__GC0,
-datapath__344: FPU__GB2,
-muxpart__180: FPU__GB0,
-reg__266: VCU118RocketSystem__GC0,
-case__506: RocketTile__GCB0,
-logic__2394: DCache,
-logic__8255: VCU118RocketSystem__GC0,
-case__653: FPU__GB1,
-logic__6781: VCU118RocketSystem__GC0,
-logic__6691: RocketTile__GCB0,
-reg__168: VCU118RocketSystem__GC0,
-logic__1083: VCU118RocketSystem__GC0,
-reg__1351: tracking_wrapper,
-case__1297: APBGpsBlock__GC0,
-logic__4339: FPU__GB1,
-case__1221: VCU118RocketSystem__GC0,
-logic__2244: DCache,
-logic__5935: RocketTile__GCB0,
-CompareRecFN: FPU__GB2,
-case__122: genesys2_rocket_top__GC0,
-case__468: VCU118RocketSystem__GC0,
-logic__5246: RocketTile__GCB0,
-case__557: DCache,
-logic__5985: RocketTile__GCB0,
-reg__501: FPU__GB1,
-logic__3002: RocketTile__GCB0,
-logic__6632: RocketTile__GCB0,
-rom__3: APBGpsBlock__GC0,
-logic__5264: RocketTile__GCB0,
-logic__3013: RocketTile__GCB0,
-counter__12: VCU118RocketSystem__GC0,
-datapath__506: VCU118RocketSystem__GC0,
-logic__1136: VCU118RocketSystem__GC0,
-dsp48e1__11: APBGpsBlock__GC0,
-logic__5628: RocketTile__GCB0,
-reg__547: FPU__GB1,
-logic__5487: RocketTile__GCB0,
-reg__831: RocketTile__GCB0,
-logic__8970: tracking_wrapper,
-logic__1038: VCU118RocketSystem__GC0,
-logic__804: VCU118RocketSystem__GC0,
-datapath__547: APBGpsBlock__GC0,
-case__597: RocketTile__GCB0,
-logic__3616: FPU__GB2, FPU__GB1,
-logic__3794: FPU__GB2,
-logic__4521: FPU__GB2, FPU__GB1,
-logic__1719: VCU118RocketSystem__GC0,
-logic__8922: tracking_wrapper,
-logic__7227: VCU118RocketSystem__GC0,
-logic__1201: VCU118RocketSystem__GC0,
-case__872: RocketTile__GCB0,
-logic__1531: VCU118RocketSystem__GC0,
-logic__4948: FPU__GB1,
-logic__2782: DCache,
-logic__4419: FPU__GB1,
-logic__8778: APBGpsBlock__GC0,
-reg__536: FPU__GB2,
-logic__6664: RocketTile__GCB0,
-logic__916: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7004: VCU118RocketSystem__GC0,
-logic__2203: DCache,
-case__1512: APBGpsBlock__GC0,
-reg__997: VCU118RocketSystem__GC0,
-datapath__498: VCU118RocketSystem__GC0,
-logic__4749: FPU__GB2,
-case__889: RocketTile__GCB0,
-logic__7528: VCU118RocketSystem__GC0,
-TLAsyncCrossingSource_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-dual_port_ram: APBGpsBlock__GC0,
-case__432: VCU118RocketSystem__GC0,
-dual_port_bram__parameterized0: APBGpsBlock__GC0,
-logic__911: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7757: VCU118RocketSystem__GC0,
-reg__1315: tracking_wrapper,
-AsyncResetRegVec_w1_i0: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__370: VCU118RocketSystem__GC0,
-logic__4878: FPU__GB2,
-case__1671: tracking_wrapper,
-logic__2103: RocketTile__GCB0,
-case__1373: APBGpsBlock__GC0,
-reg__310: VCU118RocketSystem__GC0,
-case__474: VCU118RocketSystem__GC0,
-logic__1633: VCU118RocketSystem__GC0,
-logic__1085: VCU118RocketSystem__GC0,
-reg__1259: tracking_wrapper,
-logic__2285: DCache,
-datapath__555: APBGpsBlock__GC0,
-logic__1904: VCU118RocketSystem__GC0,
-logic__6565: RocketTile__GCB0,
-logic__3357: FPU__GB1,
-reg__892: VCU118RocketSystem__GC0,
-reg__760: RocketTile__GCB0,
-logic__389: genesys2_rocket_top__GC0,
-logic__1181: VCU118RocketSystem__GC0,
-logic__930: VCU118RocketSystem__GC0,
-case__630: RocketTile__GCB0,
-logic__5669: RocketTile__GCB0,
-case__361: VCU118RocketSystem__GC0,
-logic__5: genesys2_rocket_top__GC0,
-case__818: RocketTile__GCB0,
-logic__4649: FPU__GB2,
-logic__7247: VCU118RocketSystem__GC0,
-logic__9299: tracking_wrapper,
-logic__2948: DCache,
-case__313: VCU118RocketSystem__GC0,
-logic__6081: RocketTile__GCB0,
-logic__6696: RocketTile__GCB0,
-reg__1380: tracking_wrapper,
-logic__662: genesys2_rocket_top__GC0,
-logic__7774: VCU118RocketSystem__GC0,
-OptimizationBarrier_TLBEntryData: RocketTile__GCB0, DCache,
-case__583: RocketTile__GCB0,
-case__835: RocketTile__GCB0,
-logic__4783: FPU__GB2,
-muxpart__163: DCache,
-logic__3175: RocketTile__GCB0,
-reg__842: RocketTile__GCB0,
-reg__54: genesys2_rocket_top__GC0,
-logic__6028: RocketTile__GCB0,
-logic__7363: VCU118RocketSystem__GC0,
-case__1029: VCU118RocketSystem__GC0,
-logic__5503: RocketTile__GCB0,
-case__544: DCache,
-logic__1152: VCU118RocketSystem__GC0,
-logic__7319: VCU118RocketSystem__GC0,
-logic__4259: FPU__GB1,
-reg__478: FPU__GB0,
-logic__5070: FPU__GB1,
-case__164: genesys2_rocket_top__GC0,
-logic__5926: RocketTile__GCB0,
-datapath__427: RocketTile__GCB0,
-logic__1229: VCU118RocketSystem__GC0,
-logic__7633: VCU118RocketSystem__GC0,
-logic__7211: VCU118RocketSystem__GC0,
-case__842: RocketTile__GCB0,
-logic__6721: RocketTile__GCB0,
-logic__4315: FPU__GB1,
-logic__7215: VCU118RocketSystem__GC0,
-case__315: VCU118RocketSystem__GC0,
-counter__31: tracking_wrapper,
-logic__7358: VCU118RocketSystem__GC0,
-reg__912: VCU118RocketSystem__GC0,
-reg__1087: APBGpsBlock__GC0, tracking_wrapper,
-case__39: genesys2_rocket_top__GC0,
-reg__987: VCU118RocketSystem__GC0,
-logic__1279: VCU118RocketSystem__GC0,
-logic__5955: RocketTile__GCB0,
-reg__846: RocketTile__GCB0,
-nav_solve_timer: tracking_wrapper,
-logic__9144: tracking_wrapper,
-logic__326: genesys2_rocket_top__GC0,
-case__1256: VCU118RocketSystem__GC0,
-case__1344: APBGpsBlock__GC0,
-reg__61: genesys2_rocket_top__GC0,
-sample_counter: APBGpsBlock__GC0,
-butterfly__parameterized0: APBGpsBlock__GC0,
-FixedClockBroadcast_5: VCU118RocketSystem__GC0,
-logic__4256: FPU__GB1,
-logic__235: genesys2_rocket_top__GC0,
-case__905: RocketTile__GCB0,
-logic__1020: VCU118RocketSystem__GC0,
-case__1294: APBGpsBlock__GC0,
-case__1072: VCU118RocketSystem__GC0,
-logic__2076: RocketTile__GCB0,
-logic__3262: RocketTile__GCB0,
-muxpart__241: FPU__GB2,
-logic__1729: VCU118RocketSystem__GC0,
-logic__3041: RocketTile__GCB0,
-logic__9341: tracking_wrapper,
-case__1105: VCU118RocketSystem__GC0,
-case__801: FPU__GB1,
-logic__7221: VCU118RocketSystem__GC0,
-logic__3139: RocketTile__GCB0,
-datapath__222: VCU118RocketSystem__GC0,
-case__845: RocketTile__GCB0,
-logic__1027: VCU118RocketSystem__GC0,
-datapath__314: FPU__GB1,
-logic__6720: RocketTile__GCB0,
-logic__8601: APBGpsBlock__GC0,
-case__1051: VCU118RocketSystem__GC0,
-datapath__596: APBGpsBlock__GC0,
-datapath__357: FPU__GB2,
-logic__2815: DCache,
-logic__9457: tracking_wrapper,
-logic__161: genesys2_rocket_top__GC0,
-reg__591: FPU__GB2,
-case__282: VCU118RocketSystem__GC0,
-logic__3716: FPU__GB2,
-case__1596: tracking_wrapper,
-case__203: genesys2_rocket_top__GC0,
-logic__1433: VCU118RocketSystem__GC0,
-datapath__570: APBGpsBlock__GC0,
-logic__5943: RocketTile__GCB0,
-logic__7440: VCU118RocketSystem__GC0,
-reg__1257: tracking_wrapper,
-logic__6068: RocketTile__GCB0,
-case__765: FPU__GB2,
-reg__616: FPU__GB1,
-logic__717: genesys2_rocket_top__GC0,
-datapath__528: VCU118RocketSystem__GC0,
-logic__9559: APBGpsBlock__GC0,
-logic__4368: FPU__GB1,
-logic__3294: RocketTile__GCB0,
-logic__4552: FPU__GB2, FPU__GB1,
-logic__894: VCU118RocketSystem__GC0,
-case__1191: VCU118RocketSystem__GC0,
-logic__2552: DCache,
-keep__7: genesys2_rocket_top__GC0,
-reg__512: FPU__GB1,
-reg__1145: APBGpsBlock__GC0,
-TLXbar_cbus_in_i1_o1_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-reg__1156: APBGpsBlock__GC0,
-case__337: VCU118RocketSystem__GC0,
-logic__5260: RocketTile__GCB0,
-datapath__16: genesys2_rocket_top__GC0,
-case__1338: APBGpsBlock__GC0,
-logic__4998: FPU__GB1,
-logic__6502: RocketTile__GCB0,
-logic__5857: RocketTile__GCB0,
-case__56: genesys2_rocket_top__GC0,
-dsp48e1__46: tracking_wrapper,
-logic__838: VCU118RocketSystem__GC0,
-logic__1383: VCU118RocketSystem__GC0,
-logic__1099: VCU118RocketSystem__GC0,
-logic__9555: APBGpsBlock__GC0,
-logic__4418: FPU__GB1,
-logic__8102: VCU118RocketSystem__GC0,
-datapath__243: VCU118RocketSystem__GC0,
-logic__3432: FPU__GB1,
-logic__8089: VCU118RocketSystem__GC0,
-datapath__302: RocketTile__GCB0,
-reg__1115: APBGpsBlock__GC0,
-logic__6989: VCU118RocketSystem__GC0,
-logic__890: VCU118RocketSystem__GC0,
-reg__537: FPU__GB1,
-logic__4200: FPU__GB1,
-case__1504: APBGpsBlock__GC0,
-logic__7223: VCU118RocketSystem__GC0,
-datapath__207: VCU118RocketSystem__GC0,
-case__425: VCU118RocketSystem__GC0,
-reg__341: DCache,
-logic__1442: VCU118RocketSystem__GC0,
-logic__8809: APBGpsBlock__GC0,
-case__1046: VCU118RocketSystem__GC0,
-reg__451: RocketTile__GCB0,
-logic__396: genesys2_rocket_top__GC0,
-reg__744: RocketTile__GCB0,
-logic__4081: FPU__GB2,
-datapath__149: VCU118RocketSystem__GC0,
-logic__6584: RocketTile__GCB0,
-logic__4508: FPU__GB1,
-case__526: DCache,
-logic__9052: tracking_wrapper,
-logic__9415: tracking_wrapper,
-logic__7218: VCU118RocketSystem__GC0,
-case__479: VCU118RocketSystem__GC0,
-reg__181: VCU118RocketSystem__GC0,
-datapath__694: tracking_wrapper,
-rom__1: APBGpsBlock__GC0,
-bootromClockSinkDomain: VCU118RocketSystem__GC0,
-logic__6507: RocketTile__GCB0,
-reg__559: FPU__GB1,
-logic__7763: VCU118RocketSystem__GC0,
-logic__1981: VCU118RocketSystem__GC0,
-case__362: VCU118RocketSystem__GC0,
-logic__2163: DCache,
-logic__2402: DCache,
-logic__5617: RocketTile__GCB0,
-datapath__545: VCU118RocketSystem__GC0,
-logic__7371: VCU118RocketSystem__GC0,
-logic__7174: VCU118RocketSystem__GC0,
-logic__3501: FPU__GB1,
-logic__8033: VCU118RocketSystem__GC0,
-logic__8765: APBGpsBlock__GC0,
-logic__6060: RocketTile__GCB0,
-reg__400: RocketTile__GCB0,
-case__478: VCU118RocketSystem__GC0,
-logic__6665: RocketTile__GCB0,
-logic__4787: FPU__GB2,
-datapath__413: FPU__GB1,
-datapath__620: APBGpsBlock__GC0,
-logic__4500: FPU__GB1,
-datapath__42: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__1340: VCU118RocketSystem__GC0,
-reg__219: VCU118RocketSystem__GC0,
-logic__5710: RocketTile__GCB0,
-case__223: genesys2_rocket_top__GC0,
-case__581: RocketTile__GCB0,
-logic__5065: FPU__GB1,
-muxpart__7: genesys2_rocket_top__GC0,
-logic__1820: VCU118RocketSystem__GC0,
-case__159: genesys2_rocket_top__GC0,
-case__150: genesys2_rocket_top__GC0,
-logic__7459: VCU118RocketSystem__GC0,
-logic__3426: FPU__GB1,
-case__637: RocketTile__GCB0,
-reg__282: VCU118RocketSystem__GC0,
-logic__7814: VCU118RocketSystem__GC0,
-case__1726: APBGpsBlock__GC0,
-case__965: RocketTile__GCB0,
-reg__765: RocketTile__GCB0,
-logic__2549: DCache,
-logic__4349: FPU__GB1,
-logic__8198: VCU118RocketSystem__GC0,
-case__1578: tracking_wrapper,
-case__269: VCU118RocketSystem__GC0,
-datapath__108: VCU118RocketSystem__GC0,
-case__1683: tracking_wrapper,
-logic__4614: FPU__GB2, FPU__GB1,
-datapath__134: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6762: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_pbus_to_gps: VCU118RocketSystem__GC0,
-logic__6058: RocketTile__GCB0,
-logic__4942: FPU__GB2,
-logic__4420: FPU__GB1,
-case__1431: APBGpsBlock__GC0,
-logic__607: genesys2_rocket_top__GC0,
-case__455: VCU118RocketSystem__GC0,
-reg__455: RocketTile__GCB0,
-reg__1056: VCU118RocketSystem__GC0,
-reg__1047: VCU118RocketSystem__GC0,
-reg__1142: APBGpsBlock__GC0,
-logic__6505: RocketTile__GCB0,
-RoundAnyRawFNToRecFN_4: FPU__GB2, FPU__GB1,
-logic__2761: DCache,
-logic__7135: VCU118RocketSystem__GC0,
-logic__4655: FPU__GB2,
-logic__4573: FPU__GB2, FPU__GB1,
-muxpart__213: FPU__GB0,
-logic__8218: VCU118RocketSystem__GC0,
-logic__1689: VCU118RocketSystem__GC0,
-case__1742: TLToAPB,
-case__814: RocketTile__GCB0,
-logic__2910: DCache,
-logic__2790: DCache,
-logic__9145: tracking_wrapper,
-case__1147: VCU118RocketSystem__GC0,
-reg__378: RocketTile__GCB0,
-logic__6681: RocketTile__GCB0,
-case__791: FPU__GB1,
-logic__7359: VCU118RocketSystem__GC0,
-reg__1247: tracking_wrapper,
-reg__367: DCache,
-reg__114: VCU118RocketSystem__GC0,
-logic__6039: RocketTile__GCB0,
-logic__2430: DCache,
-case__1020: VCU118RocketSystem__GC0,
-datapath__560: APBGpsBlock__GC0,
-reg__317: RocketTile__GCB0,
-logic__8663: APBGpsBlock__GC0,
-logic__3793: FPU__GB2,
-case__125: genesys2_rocket_top__GC0,
-reg__784: RocketTile__GCB0,
-reg__1395: tracking_wrapper,
-reg__928: VCU118RocketSystem__GC0,
-reg__628: FPU__GB1,
-datapath__415: RocketTile__GCB0,
-reg__316: VCU118RocketSystem__GC0,
-logic__3709: FPU__GB2,
-logic__303: genesys2_rocket_top__GC0,
-logic__88: genesys2_rocket_top__GC0,
-logic__1925: VCU118RocketSystem__GC0,
-datapath__296: RocketTile__GCB0,
-keep__13: tracking_wrapper,
-TLInterconnectCoupler_cbus_to_plic: VCU118RocketSystem__GC0,
-datapath__594: APBGpsBlock__GC0,
-logic__4499: FPU__GB1,
-Queue1_RegMapperInput_i9_m8: VCU118RocketSystem__GC0,
-logic__2162: DCache,
-reg__1226: tracking_wrapper,
-logic__7380: VCU118RocketSystem__GC0,
-datapath__170: VCU118RocketSystem__GC0,
-counter__26: tracking_wrapper,
-reg__255: VCU118RocketSystem__GC0,
-datapath__407: FPU__GB1,
-reg__1150: APBGpsBlock__GC0,
-logic__9426: tracking_wrapper,
-TLInterconnectCoupler_fbus_from_debug_sb: VCU118RocketSystem__GC0,
-logic__5003: FPU__GB1,
-logic__2206: DCache,
-logic__9425: tracking_wrapper,
-case__927: RocketTile__GCB0,
-logic__3711: FPU__GB2,
-case__431: VCU118RocketSystem__GC0,
-logic__6031: RocketTile__GCB0,
-counter__29: tracking_wrapper,
-logic__4802: FPU__GB2,
-case__447: VCU118RocketSystem__GC0,
-logic__4215: FPU__GB1,
-datapath__102: VCU118RocketSystem__GC0,
-logic__3581: FPU__GB1,
-reg__163: VCU118RocketSystem__GC0,
-case__1616: tracking_wrapper,
-logic__5424: RocketTile__GCB0,
-case__606: RocketTile__GCB0,
-logic__1443: VCU118RocketSystem__GC0,
-logic__1803: VCU118RocketSystem__GC0,
-logic__5022: FPU__GB1,
-reg__1155: APBGpsBlock__GC0,
-case__753: FPU__GB2,
-logic__8189: VCU118RocketSystem__GC0,
-logic__5457: RocketTile__GCB0,
-counter__16: APBGpsBlock__GC0,
-case__1225: VCU118RocketSystem__GC0,
-logic__2814: DCache,
-acq_top: APBGpsBlock__GC0,
-logic__1499: VCU118RocketSystem__GC0,
-reg__1406: tracking_wrapper,
-reg__1165: APBGpsBlock__GC0,
-case__40: genesys2_rocket_top__GC0,
-logic__870: VCU118RocketSystem__GC0,
-case__1682: tracking_wrapper,
-datapath__259: VCU118RocketSystem__GC0,
-tracking_wrapper: tracking_wrapper,
-CLINT: VCU118RocketSystem__GC0,
-reg__709: RocketTile__GCB0,
-reg__1075: VCU118RocketSystem__GC0,
-logic__1259: VCU118RocketSystem__GC0,
-reg__379: RocketTile__GCB0,
-case__786: FPU__GB1,
-muxpart__264: VCU118RocketSystem__GC0,
-reg__1224: tracking_wrapper,
-logic__6677: RocketTile__GCB0,
-logic__4920: FPU__GB2,
-logic__6027: RocketTile__GCB0,
-reg__549: FPU__GB1,
-logic__2064: RocketTile__GCB0,
-datapath__242: VCU118RocketSystem__GC0,
-reg__22: genesys2_rocket_top__GC0,
-logic__4690: FPU__GB2,
-logic__2113: RocketTile__GCB0,
-logic__5929: RocketTile__GCB0,
-logic__7718: VCU118RocketSystem__GC0,
-logic__7271: VCU118RocketSystem__GC0,
-logic__1202: VCU118RocketSystem__GC0,
-datapath__65: VCU118RocketSystem__GC0,
-lock_detector: tracking_wrapper,
-logic__1822: VCU118RocketSystem__GC0,
-logic__3271: RocketTile__GCB0,
-logic__1247: VCU118RocketSystem__GC0,
-Queue2_TLBundleA_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__8971: tracking_wrapper,
-logic__8560: APBGpsBlock__GC0,
-logic__4493: FPU__GB1,
-logic__4350: FPU__GB1,
-logic__4666: FPU__GB2,
-reg__1349: tracking_wrapper,
-logic__4693: FPU__GB2,
-logic__4006: FPU__GB2,
-case__694: FPU__GB2,
-TLInterconnectCoupler_cbus_to_bootrom: VCU118RocketSystem__GC0,
-logic__1874: VCU118RocketSystem__GC0,
-reg__477: FPU__GB0,
-logic__6599: RocketTile__GCB0,
-case__1619: tracking_wrapper,
-logic__196: genesys2_rocket_top__GC0,
-reg__246: VCU118RocketSystem__GC0,
-logic__9585: TLToAPB,
-case__127: genesys2_rocket_top__GC0,
-case__678: FPU__GB2,
-case__638: RocketTile__GCB0,
-case__531: DCache,
-logic__4129: FPU__GB2,
-logic__2926: DCache,
-logic__5526: RocketTile__GCB0,
-logic__5692: RocketTile__GCB0,
-case__32: genesys2_rocket_top__GC0,
-case__612: RocketTile__GCB0,
-reg__1292: tracking_wrapper,
-logic__4898: FPU__GB2,
-logic__1847: VCU118RocketSystem__GC0,
-reg__1025: VCU118RocketSystem__GC0,
-logic__1918: VCU118RocketSystem__GC0,
-datapath__595: APBGpsBlock__GC0,
-counter__3: genesys2_rocket_top__GC0,
-case__1123: VCU118RocketSystem__GC0,
-case__650: FPU__GB1,
-logic__216: genesys2_rocket_top__GC0,
-reg__780: RocketTile__GCB0,
-logic__7374: VCU118RocketSystem__GC0,
-reg__1122: APBGpsBlock__GC0,
-reg__1398: tracking_wrapper,
-logic__4351: FPU__GB1,
-logic__5153: RocketTile__GCB0,
-case__1145: VCU118RocketSystem__GC0,
-reg__1348: tracking_wrapper,
-logic__5700: RocketTile__GCB0,
-logic__8496: APBGpsBlock__GC0,
-logic__8925: tracking_wrapper,
-logic__2884: DCache,
-logic__7238: VCU118RocketSystem__GC0,
-case__808: FPU__GB1,
-logic__2068: RocketTile__GCB0,
-logic__3030: RocketTile__GCB0,
-reg__588: FPU__GB2,
-logic__9044: tracking_wrapper,
-logic__5315: RocketTile__GCB0,
-logic__8325: APBGpsBlock__GC0,
-reg__481: FPU__GB0,
-logic__2730: DCache,
-logic__5500: RocketTile__GCB0,
-case__412: VCU118RocketSystem__GC0,
-case__1079: VCU118RocketSystem__GC0,
-case__494: RocketTile__GCB0,
-reg__245: VCU118RocketSystem__GC0,
-case__591: RocketTile__GCB0,
-logic__6105: RocketTile__GCB0,
-datapath__87: VCU118RocketSystem__GC0,
-case__1325: APBGpsBlock__GC0,
-reg__1373: tracking_wrapper,
-case__343: VCU118RocketSystem__GC0,
-logic__3777: FPU__GB2,
-reg__1192: APBGpsBlock__GC0,
-logic__1737: VCU118RocketSystem__GC0,
-reg__1149: APBGpsBlock__GC0,
-logic__7954: VCU118RocketSystem__GC0,
-case__679: FPU__GB2,
-logic__4496: FPU__GB1,
-logic__8336: APBGpsBlock__GC0,
-case__702: FPU__GB2,
-reg__366: DCache,
-logic__598: genesys2_rocket_top__GC0,
-logic__9368: tracking_wrapper,
-logic__8492: APBGpsBlock__GC0,
-logic__4997: FPU__GB1,
-logic__2137: RocketTile__GCB0,
-muxpart__68: genesys2_rocket_top__GC0,
-logic__3498: FPU__GB1,
-case__819: RocketTile__GCB0,
-datapath__468: RocketTile__GCB0,
-datapath__411: FPU__GB1,
-reg__242: VCU118RocketSystem__GC0,
-logic__4090: FPU__GB2,
-logic__7456: VCU118RocketSystem__GC0,
-logic__9597: TLToAPB,
-reg__404: RocketTile__GCB0,
-case__781: FPU__GB1,
-reg__991: VCU118RocketSystem__GC0,
-logic__6576: RocketTile__GCB0,
-reg__1288: tracking_wrapper,
-case__1723: tracking_wrapper,
-logic__8600: APBGpsBlock__GC0,
-case__204: genesys2_rocket_top__GC0,
-logic__8035: VCU118RocketSystem__GC0,
-case__1389: APBGpsBlock__GC0,
-logic__4363: FPU__GB1,
-logic__305: genesys2_rocket_top__GC0,
-datapath__699: tracking_wrapper,
-logic__7274: VCU118RocketSystem__GC0,
-datapath__188: VCU118RocketSystem__GC0,
-logic__4565: FPU__GB2, FPU__GB1,
-reg__1198: APBGpsBlock__GC0,
-logic__2517: RocketTile__GCB0, DCache,
-datapath__648: tracking_wrapper,
-datapath__228: VCU118RocketSystem__GC0,
-logic__2006: VCU118RocketSystem__GC0,
-muxpart__376: tracking_wrapper,
-datapath__521: VCU118RocketSystem__GC0,
-logic__6835: VCU118RocketSystem__GC0,
-logic__3569: FPU__GB1,
-case__1564: tracking_wrapper,
-logic__9104: tracking_wrapper,
-logic__5887: RocketTile__GCB0,
-datapath__41: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__218: VCU118RocketSystem__GC0,
-reg__348: DCache,
-case__246: VCU118RocketSystem__GC0,
-logic__9004: tracking_wrapper,
-case__1367: APBGpsBlock__GC0,
-logic__4475: FPU__GB1,
-logic__4141: FPU__GB2,
-datapath__241: VCU118RocketSystem__GC0,
-reg__1070: VCU118RocketSystem__GC0,
-case__1290: APBGpsBlock__GC0,
-logic__4277: FPU__GB1,
-case__404: VCU118RocketSystem__GC0,
-logic__2169: DCache,
-reg__608: FPU__GB2,
-logic__8369: APBGpsBlock__GC0,
-logic__283: genesys2_rocket_top__GC0,
-datapath__171: VCU118RocketSystem__GC0,
-reg__692: RocketTile__GCB0,
-logic__3795: FPU__GB2,
-datapath__356: FPU__GB2,
-case__209: genesys2_rocket_top__GC0,
-datapath__86: VCU118RocketSystem__GC0,
-logic__7425: VCU118RocketSystem__GC0,
-datapath__231: VCU118RocketSystem__GC0,
-reg__1129: APBGpsBlock__GC0,
-case__933: RocketTile__GCB0,
-case__721: FPU__GB1,
-reg__197: VCU118RocketSystem__GC0,
-reg__135: VCU118RocketSystem__GC0,
-logic__1823: VCU118RocketSystem__GC0,
-case__331: VCU118RocketSystem__GC0,
-datapath__269: DCache,
-rom__2: APBGpsBlock__GC0,
-case__888: RocketTile__GCB0,
-reg__286: VCU118RocketSystem__GC0,
-reg__567: FPU__GB1,
-logic__5508: RocketTile__GCB0,
-TLBuffer_a32d64s1k1z4u_1: RocketTile__GCB0,
-muxpart__227: FPU__GB0,
-logic__2480: RocketTile__GCB0, DCache,
-logic__9525: APBGpsBlock__GC0,
-datapath__631: APBGpsBlock__GC0,
-logic__5414: RocketTile__GCB0,
-logic__5956: RocketTile__GCB0,
-reg__1009: VCU118RocketSystem__GC0,
-reg__522: FPU__GB2,
-datapath__258: VCU118RocketSystem__GC0,
-datapath__703: tracking_wrapper,
-logic__9396: tracking_wrapper,
-reg__1325: tracking_wrapper,
-logic__5439: RocketTile__GCB0,
-datapath__589: APBGpsBlock__GC0,
-case__1426: APBGpsBlock__GC0,
-muxpart__10: genesys2_rocket_top__GC0,
-logic__9045: tracking_wrapper,
-logic__3302: RocketTile__GCB0,
-logic__4561: FPU__GB2, FPU__GB1,
-logic__5934: RocketTile__GCB0,
-logic__2077: RocketTile__GCB0,
-reg__143: VCU118RocketSystem__GC0,
-logic__6104: RocketTile__GCB0,
-reg__979: VCU118RocketSystem__GC0,
-case__330: VCU118RocketSystem__GC0,
-logic__8214: VCU118RocketSystem__GC0,
-logic__5187: RocketTile__GCB0,
-datapath__211: VCU118RocketSystem__GC0,
-logic__1665: VCU118RocketSystem__GC0,
-logic__3700: FPU__GB2,
-logic__3425: FPU__GB1,
-case__382: VCU118RocketSystem__GC0,
-logic__3751: FPU__GB2,
-case__1156: VCU118RocketSystem__GC0,
-reg__880: VCU118RocketSystem__GC0,
-logic__6327: RocketTile__GCB0,
-logic__6163: RocketTile__GCB0,
-case__1509: APBGpsBlock__GC0,
-datapath__587: APBGpsBlock__GC0,
-logic__7308: VCU118RocketSystem__GC0,
-reg__473: FPU__GB0,
-case__1580: tracking_wrapper,
-reg__1048: VCU118RocketSystem__GC0,
-datapath__203: VCU118RocketSystem__GC0,
-reg__1191: APBGpsBlock__GC0,
-logic__5907: RocketTile__GCB0,
-case__579: RocketTile__GCB0,
-logic__8815: APBGpsBlock__GC0,
-case__1484: APBGpsBlock__GC0,
-case__817: RocketTile__GCB0,
-muxpart__166: DCache,
-logic__4164: FPU__GB1,
-case__357: VCU118RocketSystem__GC0,
-logic__6747: VCU118RocketSystem__GC0,
-APBGpsBlock__GC0: APBGpsBlock__GC0,
-logic__6961: VCU118RocketSystem__GC0,
-case__705: FPU__GB1,
-reg__252: VCU118RocketSystem__GC0,
-case__257: VCU118RocketSystem__GC0,
-logic__2728: DCache,
-logic__4791: FPU__GB2,
-logic__5620: RocketTile__GCB0,
-logic__357: genesys2_rocket_top__GC0,
-case__1087: VCU118RocketSystem__GC0,
-case__350: VCU118RocketSystem__GC0,
-dsp48e1__28: APBGpsBlock__GC0,
-case__724: FPU__GB2, FPU__GB1,
-case__1231: VCU118RocketSystem__GC0,
-datapath__37: VCU118RocketSystem__GC0,
-reg__702: RocketTile__GCB0,
-logic__7447: VCU118RocketSystem__GC0,
-logic__7065: VCU118RocketSystem__GC0,
-logic__4414: FPU__GB1,
-logic__6534: RocketTile__GCB0,
-logic__1347: VCU118RocketSystem__GC0,
-case__408: VCU118RocketSystem__GC0,
-logic__3497: FPU__GB1,
-case__1222: VCU118RocketSystem__GC0,
-datapath__495: VCU118RocketSystem__GC0,
-logic__6680: RocketTile__GCB0,
-reg__1027: VCU118RocketSystem__GC0,
-logic__7361: VCU118RocketSystem__GC0,
-datapath__254: VCU118RocketSystem__GC0,
-reg__584: FPU__GB2,
-reg__1079: VCU118RocketSystem__GC0,
-case__1000: VCU118RocketSystem__GC0,
-logic__148: genesys2_rocket_top__GC0,
-logic__6155: RocketTile__GCB0,
-logic__2181: DCache,
-logic__4892: FPU__GB2,
-logic__6918: VCU118RocketSystem__GC0,
-case__1375: APBGpsBlock__GC0,
-AsyncQueueSource_TLBundleA_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-reg__179: VCU118RocketSystem__GC0,
-datapath__97: VCU118RocketSystem__GC0,
-logic__8185: VCU118RocketSystem__GC0,
-cos2x: tracking_wrapper,
-logic__2055: VCU118RocketSystem__GC0,
-case__508: RocketTile__GCB0,
-case__1676: tracking_wrapper,
-reg__1189: APBGpsBlock__GC0,
-TilePRCIDomain__GC0: TilePRCIDomain__GC0,
-datapath__695: tracking_wrapper,
-reg__687: RocketTile__GCB0,
-reg__877: VCU118RocketSystem__GC0,
-logic__6343: RocketTile__GCB0,
-logic__9511: tracking_wrapper,
-logic__4758: FPU__GB2,
-case__1088: VCU118RocketSystem__GC0,
-reg__464: FPU__GB0,
-logic__8761: APBGpsBlock__GC0,
-case__599: RocketTile__GCB0,
-logic__4990: FPU__GB1,
-logic__1288: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__199: genesys2_rocket_top__GC0,
-case__182: genesys2_rocket_top__GC0,
-datapath__262: RocketTile__GCB0,
-logic__7436: VCU118RocketSystem__GC0,
-case__524: DCache,
-logic__4494: FPU__GB1,
-reg__331: DCache,
-logic__2032: VCU118RocketSystem__GC0,
-logic__826: VCU118RocketSystem__GC0,
-logic__7044: VCU118RocketSystem__GC0,
-logic__1401: VCU118RocketSystem__GC0,
-logic__839: VCU118RocketSystem__GC0,
-case__1485: APBGpsBlock__GC0,
-logic__1527: VCU118RocketSystem__GC0,
-logic__4881: FPU__GB2,
-muxpart__257: RocketTile__GCB0,
-datapath__163: VCU118RocketSystem__GC0,
-case__1595: tracking_wrapper,
-logic__1329: VCU118RocketSystem__GC0,
-logic__7388: VCU118RocketSystem__GC0,
-logic__8219: VCU118RocketSystem__GC0,
-logic__5979: RocketTile__GCB0,
-logic__7413: VCU118RocketSystem__GC0,
-logic__2354: DCache,
-case__46: genesys2_rocket_top__GC0,
-case__1195: VCU118RocketSystem__GC0,
-reg__1426: TLToAPB,
-logic__752: VCU118RocketSystem__GC0,
-reg__593: FPU__GB2,
-case__1687: tracking_wrapper,
-logic__7122: VCU118RocketSystem__GC0,
-logic__956: VCU118RocketSystem__GC0,
-case__263: VCU118RocketSystem__GC0,
-reg__1321: tracking_wrapper,
-case__254: VCU118RocketSystem__GC0,
-reg__640: FPU__GB1,
-case__1038: VCU118RocketSystem__GC0,
-datapath__247: VCU118RocketSystem__GC0,
-logic__5240: RocketTile__GCB0,
-datapath__332: FPU__GB2,
-logic__2138: RocketTile__GCB0,
-muxpart__184: FPU__GB0,
-logic__5417: RocketTile__GCB0,
-logic__2520: RocketTile__GCB0, DCache,
-muxpart__44: genesys2_rocket_top__GC0,
-logic__2104: RocketTile__GCB0,
-logic__3061: RocketTile__GCB0,
-logic__7437: VCU118RocketSystem__GC0,
-reg__686: RocketTile__GCB0,
-reg__39: genesys2_rocket_top__GC0,
-reg__212: VCU118RocketSystem__GC0,
-reg__893: VCU118RocketSystem__GC0,
-logic__1423: VCU118RocketSystem__GC0,
-logic__5216: RocketTile__GCB0,
-datapath__395: FPU__GB2,
-case__713: FPU__GB1,
-case__955: RocketTile__GCB0,
-logic__5574: RocketTile__GCB0,
-logic__1111: VCU118RocketSystem__GC0,
-reg__285: VCU118RocketSystem__GC0,
-logic__921: VCU118RocketSystem__GC0,
-reg__1243: tracking_wrapper,
-logic__6131: RocketTile__GCB0,
-logic__9262: tracking_wrapper,
-case__488: VCU118RocketSystem__GC0,
-logic__2275: DCache,
-datapath__462: RocketTile__GCB0,
-case__505: RocketTile__GCB0,
-reg__226: VCU118RocketSystem__GC0,
-logic__8183: VCU118RocketSystem__GC0,
-logic__7940: VCU118RocketSystem__GC0,
-logic__6764: VCU118RocketSystem__GC0,
-logic__7015: VCU118RocketSystem__GC0,
-logic__5201: RocketTile__GCB0,
-reg__1: genesys2_rocket_top__GC0,
-case__452: VCU118RocketSystem__GC0,
-logic__5052: FPU__GB1,
-logic__4844: FPU__GB2,
-logic__6043: RocketTile__GCB0,
-case__1090: VCU118RocketSystem__GC0,
-reg__1434: genesys2_rocket_top__GC0,
-case__1502: APBGpsBlock__GC0,
-logic__4506: FPU__GB1,
-case__118: genesys2_rocket_top__GC0,
-datapath__114: VCU118RocketSystem__GC0,
-counter__8: VCU118RocketSystem__GC0,
-case__856: RocketTile__GCB0,
-reg__961: VCU118RocketSystem__GC0,
-logic__3560: FPU__GB1,
-reg__62: genesys2_rocket_top__GC0,
-logic__9575: TLToAPB,
-counter__6: genesys2_rocket_top__GC0,
-logic__8438: APBGpsBlock__GC0,
-logic__3339: FPU__GB1,
-logic__1064: VCU118RocketSystem__GC0,
-reg__1275: tracking_wrapper,
-case__1109: VCU118RocketSystem__GC0,
-logic__4852: FPU__GB2,
-logic__6715: RocketTile__GCB0,
-logic__3431: FPU__GB1,
-logic__8337: APBGpsBlock__GC0,
-logic__7390: VCU118RocketSystem__GC0,
-logic__1538: VCU118RocketSystem__GC0,
-case__267: VCU118RocketSystem__GC0,
-case__1610: tracking_wrapper,
-datapath__123: VCU118RocketSystem__GC0,
-case__572: DCache,
-case__1027: VCU118RocketSystem__GC0,
-case__918: RocketTile__GCB0,
-logic__4152: FPU__GB2,
-logic__6658: RocketTile__GCB0,
-reg__1148: APBGpsBlock__GC0,
-reg__900: VCU118RocketSystem__GC0,
-logic__8172: VCU118RocketSystem__GC0,
-datapath__622: APBGpsBlock__GC0,
-logic__6615: RocketTile__GCB0,
-case__108: genesys2_rocket_top__GC0,
-logic__9346: tracking_wrapper,
-logic__3528: FPU__GB1,
-case__1211: VCU118RocketSystem__GC0,
-logic__84: genesys2_rocket_top__GC0,
-datapath__524: VCU118RocketSystem__GC0,
-logic__1516: VCU118RocketSystem__GC0,
-muxpart__219: FPU__GB0,
-reg__11: genesys2_rocket_top__GC0,
-logic__1896: VCU118RocketSystem__GC0,
-logic__1614: VCU118RocketSystem__GC0,
-logic__2954: DCache,
-reg__544: FPU__GB1,
-case__151: genesys2_rocket_top__GC0,
-datapath__218: VCU118RocketSystem__GC0,
-datapath__633: APBGpsBlock__GC0,
-logic__2362: DCache,
-case__216: genesys2_rocket_top__GC0,
-datapath__550: APBGpsBlock__GC0,
-logic__1936: VCU118RocketSystem__GC0,
-logic__6807: VCU118RocketSystem__GC0,
-rf_31x64: RocketTile__GCB0,
-case__919: RocketTile__GCB0,
-logic__6520: RocketTile__GCB0,
-logic__1331: VCU118RocketSystem__GC0,
-logic__2407: DCache,
-reg__942: VCU118RocketSystem__GC0,
-datapath__181: VCU118RocketSystem__GC0,
-reg__1401: tracking_wrapper,
-reg__115: VCU118RocketSystem__GC0,
-spill_register_flushable: tracking_wrapper,
-case__988: VCU118RocketSystem__GC0,
-logic__5128: FPU__GB1,
-logic__7996: VCU118RocketSystem__GC0,
-logic__7444: VCU118RocketSystem__GC0,
-logic__8870: APBGpsBlock__GC0,
-logic__2007: VCU118RocketSystem__GC0,
-logic__6660: RocketTile__GCB0,
-logic__3754: FPU__GB2,
-case__1417: APBGpsBlock__GC0,
-case__385: VCU118RocketSystem__GC0,
-datapath__619: APBGpsBlock__GC0,
-logic__4489: FPU__GB1,
-logic__7402: VCU118RocketSystem__GC0,
-case__430: VCU118RocketSystem__GC0,
-logic__7984: VCU118RocketSystem__GC0,
-case__360: VCU118RocketSystem__GC0,
-reg__1310: tracking_wrapper,
-logic__4647: FPU__GB2,
-datapath__103: VCU118RocketSystem__GC0,
-logic__6133: RocketTile__GCB0,
-ShiftQueue: RocketTile__GCB0,
-logic__4747: FPU__GB2,
-logic__5901: RocketTile__GCB0,
-datapath__113: VCU118RocketSystem__GC0,
-case__135: genesys2_rocket_top__GC0,
-logic__5209: RocketTile__GCB0,
-logic__7001: VCU118RocketSystem__GC0,
-case__369: VCU118RocketSystem__GC0,
-logic__2449: DCache,
-case__500: RocketTile__GCB0,
-logic__7460: VCU118RocketSystem__GC0,
-logic__1284: VCU118RocketSystem__GC0,
-reg__596: FPU__GB2,
-case__1239: VCU118RocketSystem__GC0,
-datapath__629: APBGpsBlock__GC0,
-reg__756: RocketTile__GCB0,
-case__975: RocketTile__GCB0,
-logic__7928: VCU118RocketSystem__GC0,
-case__875: RocketTile__GCB0,
-logic__5175: RocketTile__GCB0,
-logic__786: VCU118RocketSystem__GC0,
-datapath__475: RocketTile__GCB0,
-reg__31: genesys2_rocket_top__GC0,
-ram__8: VCU118RocketSystem__GC0,
-logic__3784: FPU__GB2,
-fft_radix_2__parameterized1: APBGpsBlock__GC0,
-logic__3099: RocketTile__GCB0,
-logic__4895: FPU__GB2,
-logic__2778: DCache,
-case__183: genesys2_rocket_top__GC0,
-logic__9530: APBGpsBlock__GC0,
-case__559: DCache,
-logic__1890: VCU118RocketSystem__GC0,
-logic__5251: RocketTile__GCB0,
-logic__7870: VCU118RocketSystem__GC0,
-logic__3477: FPU__GB1,
-reg__786: RocketTile__GCB0,
-muxpart__76: genesys2_rocket_top__GC0,
-ClockCrossingReg_w15: VCU118RocketSystem__GC0,
-reg__21: genesys2_rocket_top__GC0,
-logic__7052: VCU118RocketSystem__GC0,
-reg__731: RocketTile__GCB0,
-datapath__345: FPU__GB2,
-logic__8345: APBGpsBlock__GC0,
-case__307: VCU118RocketSystem__GC0,
-case__1074: VCU118RocketSystem__GC0,
-case__750: FPU__GB2,
-muxpart__254: RocketTile__GCB0,
-logic__898: VCU118RocketSystem__GC0,
-case__631: RocketTile__GCB0,
-case__1369: APBGpsBlock__GC0,
-TLXbar_fbus_i1_o1_a32d64s1k1z4u: VCU118RocketSystem__GC0,
-logic__9069: tracking_wrapper,
-logic__7442: VCU118RocketSystem__GC0,
-logic__1855: VCU118RocketSystem__GC0,
-case__335: VCU118RocketSystem__GC0,
-logic__3236: RocketTile__GCB0,
-case__838: RocketTile__GCB0,
-logic__8267: VCU118RocketSystem__GC0,
-logic__8333: APBGpsBlock__GC0,
-muxpart__385: tracking_wrapper,
-logic__2603: DCache,
-logic__7126: VCU118RocketSystem__GC0,
-logic__3519: FPU__GB1,
-logic__7: genesys2_rocket_top__GC0,
-reg__817: RocketTile__GCB0,
-case__222: genesys2_rocket_top__GC0,
-logic__3078: RocketTile__GCB0,
-logic__3495: FPU__GB1,
-case__1430: APBGpsBlock__GC0,
-logic__733: genesys2_rocket_top__GC0,
-logic__7083: VCU118RocketSystem__GC0,
-reg__906: VCU118RocketSystem__GC0,
-reg__779: RocketTile__GCB0,
-reg__338: DCache,
-logic__3003: RocketTile__GCB0,
-logic__1664: VCU118RocketSystem__GC0,
-datapath__151: VCU118RocketSystem__GC0,
-datapath__711: tracking_wrapper,
-logic__132: genesys2_rocket_top__GC0,
-logic__5546: RocketTile__GCB0,
-logic__61: genesys2_rocket_top__GC0,
-logic__1931: VCU118RocketSystem__GC0,
-logic__6592: RocketTile__GCB0,
-case__1024: VCU118RocketSystem__GC0,
-reg__834: RocketTile__GCB0,
-case__1048: VCU118RocketSystem__GC0,
-logic__7006: VCU118RocketSystem__GC0,
-logic__4488: FPU__GB1,
-case__1427: APBGpsBlock__GC0,
-reg__1023: VCU118RocketSystem__GC0,
-logic__7910: VCU118RocketSystem__GC0,
-datapath__543: VCU118RocketSystem__GC0,
-case__18: genesys2_rocket_top__GC0,
-case__1190: VCU118RocketSystem__GC0,
-case__397: VCU118RocketSystem__GC0,
-muxpart__245: FPU__GB1,
-case__1160: VCU118RocketSystem__GC0,
-logic__7207: VCU118RocketSystem__GC0,
-logic__2105: RocketTile__GCB0,
-logic__2294: DCache,
-datapath__530: VCU118RocketSystem__GC0,
-case__841: RocketTile__GCB0,
-muxpart__244: FPU__GB1,
-case__553: DCache,
-logic__6931: VCU118RocketSystem__GC0,
-reg__172: VCU118RocketSystem__GC0,
-logic__4908: FPU__GB2,
-datapath__551: APBGpsBlock__GC0,
-logic__872: VCU118RocketSystem__GC0,
-logic__4: genesys2_rocket_top__GC0,
-reg__1262: tracking_wrapper,
-reg__1214: APBGpsBlock__GC0,
-logic__7152: VCU118RocketSystem__GC0,
-datapath__566: APBGpsBlock__GC0,
-logic__7181: VCU118RocketSystem__GC0,
-case__1614: tracking_wrapper,
-logic__3209: RocketTile__GCB0,
-reg__542: FPU__GB1,
-case__119: genesys2_rocket_top__GC0,
-logic__7159: VCU118RocketSystem__GC0,
-case__409: VCU118RocketSystem__GC0,
-ram_2x78: VCU118RocketSystem__GC0,
-datapath__104: VCU118RocketSystem__GC0,
-muxpart__266: VCU118RocketSystem__GC0,
-logic__6733: VCU118RocketSystem__GC0,
-logic__9410: tracking_wrapper,
-reg__1366: tracking_wrapper,
-logic__6930: VCU118RocketSystem__GC0,
-logic__7900: VCU118RocketSystem__GC0,
-reg__1232: tracking_wrapper,
-logic__18: genesys2_rocket_top__GC0,
-case__277: VCU118RocketSystem__GC0,
-case__881: RocketTile__GCB0,
-logic__6037: RocketTile__GCB0,
-case__987: VCU118RocketSystem__GC0,
-logic__5683: RocketTile__GCB0,
-reg__922: VCU118RocketSystem__GC0,
-logic__2217: DCache,
-muxpart__157: VCU118RocketSystem__GC0,
-logic__134: genesys2_rocket_top__GC0,
-logic__6611: RocketTile__GCB0,
-reset_synch: tracking_wrapper,
-logic__7407: VCU118RocketSystem__GC0,
-case__1334: APBGpsBlock__GC0,
-reg__673: RocketTile__GCB0,
-logic__9021: tracking_wrapper,
-logic__9059: tracking_wrapper,
-reg__1106: APBGpsBlock__GC0,
-logic__6621: RocketTile__GCB0,
-reg__185: VCU118RocketSystem__GC0,
-logic__3508: FPU__GB1,
-reg__53: genesys2_rocket_top__GC0,
-logic__2042: VCU118RocketSystem__GC0,
-case__243: VCU118RocketSystem__GC0,
-logic__7301: VCU118RocketSystem__GC0,
-logic__3514: FPU__GB1,
-logic__2236: DCache,
-logic__9467: tracking_wrapper,
-logic__9: genesys2_rocket_top__GC0,
-eth_rf_genesys2: genesys2_rocket_top__GC0,
-logic__8684: APBGpsBlock__GC0,
-case__131: genesys2_rocket_top__GC0,
-logic__7768: VCU118RocketSystem__GC0,
-case__1712: tracking_wrapper,
-case__502: RocketTile__GCB0,
-logic__5919: RocketTile__GCB0,
-logic__7453: VCU118RocketSystem__GC0,
-logic__6805: VCU118RocketSystem__GC0,
-case__1594: tracking_wrapper,
-logic__9387: tracking_wrapper,
-logic__8890: tracking_wrapper,
-logic__4937: FPU__GB1,
-logic__5826: RocketTile__GCB0,
-logic__6802: VCU118RocketSystem__GC0,
-reg__189: VCU118RocketSystem__GC0,
-reg__1010: VCU118RocketSystem__GC0,
-case__1529: APBGpsBlock__GC0,
-logic__8188: VCU118RocketSystem__GC0,
-reg__955: VCU118RocketSystem__GC0,
-logic__3298: RocketTile__GCB0,
-muxpart__52: genesys2_rocket_top__GC0,
-logic__2029: VCU118RocketSystem__GC0,
-logic__3201: RocketTile__GCB0,
-datapath__492: VCU118RocketSystem__GC0,
-logic__4234: FPU__GB1,
-logic__50: genesys2_rocket_top__GC0,
-logic__1875: VCU118RocketSystem__GC0,
-reg__939: VCU118RocketSystem__GC0,
-reg__466: FPU__GB0,
-logic__3268: RocketTile__GCB0,
-reg__203: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__5253: RocketTile__GCB0,
-dsp48e1__29: tracking_wrapper,
-logic__7786: VCU118RocketSystem__GC0,
-reg__260: VCU118RocketSystem__GC0,
-case__1587: tracking_wrapper,
-logic__6049: RocketTile__GCB0,
-datapath__238: VCU118RocketSystem__GC0,
-reg__339: DCache,
-logic__5987: RocketTile__GCB0,
-datapath__316: FPU__GB1,
-logic__2051: VCU118RocketSystem__GC0,
-logic__4788: FPU__GB2,
-logic__6577: RocketTile__GCB0,
-logic__3445: FPU__GB1,
-logic__497: genesys2_rocket_top__GC0,
-logic__3632: FPU__GB2, FPU__GB1,
-FixedClockBroadcast_1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__544: genesys2_rocket_top__GC0,
-logic__3612: FPU__GB2, FPU__GB1,
-logic__3696: FPU__GB1,
-reg__52: genesys2_rocket_top__GC0,
-logic__3591: FPU__GB2, FPU__GB1,
-reg__1227: tracking_wrapper,
-case__47: genesys2_rocket_top__GC0,
-case__309: VCU118RocketSystem__GC0,
-logic__5852: RocketTile__GCB0,
-logic__6858: VCU118RocketSystem__GC0,
-case__133: genesys2_rocket_top__GC0,
-logic__1236: VCU118RocketSystem__GC0,
-logic__2942: DCache,
-logic__2741: DCache,
-case__1713: tracking_wrapper,
-datapath__419: RocketTile__GCB0,
-logic__6841: VCU118RocketSystem__GC0,
-logic__6753: VCU118RocketSystem__GC0,
-logic__8690: APBGpsBlock__GC0,
-case__1257: APBGpsBlock__GC0,
-logic__2754: DCache,
-logic__4347: FPU__GB1,
-muxpart__130: genesys2_rocket_top__GC0,
-muxpart__43: genesys2_rocket_top__GC0,
-case__980: RocketTile__GCB0,
-logic__5358: RocketTile__GCB0,
-logic__2097: RocketTile__GCB0,
-case__936: RocketTile__GCB0,
-logic__194: genesys2_rocket_top__GC0,
-case__114: genesys2_rocket_top__GC0,
-logic__1096: VCU118RocketSystem__GC0,
-logic__8885: tracking_wrapper,
-logic__4209: FPU__GB1,
-logic__7261: VCU118RocketSystem__GC0,
-logic__2185: DCache,
-cordic_angle_lut__parameterized0: tracking_wrapper,
-muxpart__62: genesys2_rocket_top__GC0,
-reg__326: DCache,
-dsp48e1__43: tracking_wrapper,
-reg__233: VCU118RocketSystem__GC0,
-case__903: RocketTile__GCB0,
-logic__6082: RocketTile__GCB0,
-case__38: genesys2_rocket_top__GC0,
-logic__8075: VCU118RocketSystem__GC0,
-logic__5616: RocketTile__GCB0,
-case__1632: tracking_wrapper,
-reg__1220: tracking_wrapper,
-muxpart__42: genesys2_rocket_top__GC0,
-reg__1116: APBGpsBlock__GC0,
-logic__6718: RocketTile__GCB0,
-logic__1827: VCU118RocketSystem__GC0,
-logic__8174: VCU118RocketSystem__GC0,
-dsp48e1__25: APBGpsBlock__GC0,
-logic__7124: VCU118RocketSystem__GC0,
-logic__2065: RocketTile__GCB0,
-datapath__55: VCU118RocketSystem__GC0,
-logic__6038: RocketTile__GCB0,
-reg__447: RocketTile__GCB0,
-datapath__665: tracking_wrapper,
-logic__1519: VCU118RocketSystem__GC0,
-logic__1100: VCU118RocketSystem__GC0,
-logic__7311: VCU118RocketSystem__GC0,
-case__752: FPU__GB2,
-logic__6276: RocketTile__GCB0,
-datapath__536: VCU118RocketSystem__GC0,
-case__378: VCU118RocketSystem__GC0,
-case__377: VCU118RocketSystem__GC0,
-logic__8687: APBGpsBlock__GC0,
-logic__988: VCU118RocketSystem__GC0,
-reg__1086: VCU118RocketSystem__GC0,
-case__1327: APBGpsBlock__GC0,
-logic__888: VCU118RocketSystem__GC0,
-dsp48e1__17: APBGpsBlock__GC0,
-logic__6792: VCU118RocketSystem__GC0,
-reg__1091: APBGpsBlock__GC0,
-case__110: genesys2_rocket_top__GC0,
-reg__164: VCU118RocketSystem__GC0,
-logic__3471: FPU__GB1,
-logic__552: genesys2_rocket_top__GC0,
-datapath__157: VCU118RocketSystem__GC0,
-reg__633: FPU__GB1,
-case__356: VCU118RocketSystem__GC0,
-case__1341: APBGpsBlock__GC0,
-logic__6702: RocketTile__GCB0,
-case__1524: APBGpsBlock__GC0,
-reg__624: FPU__GB1,
-case__1303: APBGpsBlock__GC0,
-case__681: FPU__GB2,
-logic__874: VCU118RocketSystem__GC0,
-reg__215: VCU118RocketSystem__GC0,
-case__511: DCache,
-logic__9327: tracking_wrapper,
-reg__1210: APBGpsBlock__GC0,
-logic__4643: FPU__GB2,
-reg__281: VCU118RocketSystem__GC0,
-case__268: VCU118RocketSystem__GC0,
-logic__1093: VCU118RocketSystem__GC0,
-datapath__50: VCU118RocketSystem__GC0,
-reg__555: FPU__GB1,
-reg__654: FPU__GB1,
-logic__6812: VCU118RocketSystem__GC0,
-logic__1515: VCU118RocketSystem__GC0,
-datapath__281: DCache,
-logic__7461: VCU118RocketSystem__GC0,
-logic__5239: RocketTile__GCB0,
-logic__4406: FPU__GB1,
-case__538: DCache,
-case__187: genesys2_rocket_top__GC0,
-trck_cntrl: tracking_wrapper,
-logic__6084: RocketTile__GCB0,
-reg__1051: VCU118RocketSystem__GC0,
-logic__116: genesys2_rocket_top__GC0,
-logic__178: genesys2_rocket_top__GC0,
-logic__4472: FPU__GB1,
-reg__453: RocketTile__GCB0,
-logic__9589: TLToAPB,
-reg__807: RocketTile__GCB0,
-logic__4823: FPU__GB2,
-case__1438: APBGpsBlock__GC0,
-logic__5353: RocketTile__GCB0,
-logic__191: genesys2_rocket_top__GC0,
-case__843: RocketTile__GCB0,
-rom__6: tracking_wrapper,
-case__1043: VCU118RocketSystem__GC0,
-logic__7259: VCU118RocketSystem__GC0,
-logic__143: genesys2_rocket_top__GC0,
-logic__43: genesys2_rocket_top__GC0,
-logic__5982: RocketTile__GCB0,
-case__1728: APBGpsBlock__GC0,
-logic__5194: RocketTile__GCB0,
-logic__4484: FPU__GB1,
-reg__1019: VCU118RocketSystem__GC0,
-logic__5100: FPU__GB1,
-logic__5828: RocketTile__GCB0,
-logic__1174: VCU118RocketSystem__GC0,
-FixedClockBroadcast_3: VCU118RocketSystem__GC0,
-logic__1323: VCU118RocketSystem__GC0,
-reg__126: VCU118RocketSystem__GC0,
-datapath__403: FPU__GB2,
-datapath__294: RocketTile__GCB0,
-logic__384: genesys2_rocket_top__GC0,
-logic__1513: VCU118RocketSystem__GC0,
-muxpart__263: RocketTile__GCB0,
-logic__6810: VCU118RocketSystem__GC0,
-case__977: RocketTile__GCB0,
-case__1232: VCU118RocketSystem__GC0,
-logic__7455: VCU118RocketSystem__GC0,
-case__342: VCU118RocketSystem__GC0,
-logic__3235: RocketTile__GCB0,
-case__1216: VCU118RocketSystem__GC0,
-logic__8036: VCU118RocketSystem__GC0,
-case__1680: tracking_wrapper,
-reg__1335: tracking_wrapper,
-case__969: RocketTile__GCB0,
-logic__6797: VCU118RocketSystem__GC0,
-logic__4023: FPU__GB2,
-logic__4755: FPU__GB2,
-logic__6: genesys2_rocket_top__GC0,
-reg__1353: tracking_wrapper,
-keep__15: tracking_wrapper,
-logic__348: genesys2_rocket_top__GC0,
-datapath__240: VCU118RocketSystem__GC0,
-case__946: RocketTile__GCB0,
-case__1715: tracking_wrapper,
-logic__6334: RocketTile__GCB0,
-reg__7: genesys2_rocket_top__GC0,
-logic__5986: RocketTile__GCB0,
-logic__1528: VCU118RocketSystem__GC0,
-reg__134: VCU118RocketSystem__GC0,
-logic__9235: tracking_wrapper,
-logic__8011: VCU118RocketSystem__GC0,
-logic__8888: tracking_wrapper,
-reg__95: genesys2_rocket_top__GC0,
-logic__14: genesys2_rocket_top__GC0,
-sync: tracking_wrapper,
-datapath__319: FPU__GB1,
-logic__5107: FPU__GB1,
-reg__424: RocketTile__GCB0,
-reg__841: RocketTile__GCB0,
-logic__8324: APBGpsBlock__GC0,
-case__1630: tracking_wrapper,
-case__632: RocketTile__GCB0,
-logic__6997: VCU118RocketSystem__GC0,
-AsyncQueueSource_DebugInternalBundle: VCU118RocketSystem__GC0,
-logic__1090: VCU118RocketSystem__GC0,
-reg__1228: tracking_wrapper,
-logic__7410: VCU118RocketSystem__GC0,
-logic__2901: DCache,
-case__821: RocketTile__GCB0,
-logic__5543: RocketTile__GCB0,
-logic__2373: DCache,
-logic__6749: VCU118RocketSystem__GC0,
-case__1333: APBGpsBlock__GC0,
-logic__4583: FPU__GB2, FPU__GB1,
-logic__167: genesys2_rocket_top__GC0,
-case__542: DCache,
-reg__569: FPU__GB1,
-muxpart__358: APBGpsBlock__GC0,
-logic__7433: VCU118RocketSystem__GC0,
-logic__9089: tracking_wrapper,
-datapath__701: tracking_wrapper,
-case__930: RocketTile__GCB0,
-reg__342: DCache,
-divider__parameterized0: tracking_wrapper,
-case__619: RocketTile__GCB0,
-logic__4991: FPU__GB1,
-logic__905: VCU118RocketSystem__GC0,
-logic__3288: RocketTile__GCB0,
-reg__161: VCU118RocketSystem__GC0,
-case__1692: tracking_wrapper,
-logic__1514: VCU118RocketSystem__GC0,
-datapath__513: VCU118RocketSystem__GC0,
-case__341: VCU118RocketSystem__GC0,
-reg__835: RocketTile__GCB0,
-logic__1362: VCU118RocketSystem__GC0,
-logic__1905: VCU118RocketSystem__GC0,
-case__761: FPU__GB2,
-logic__6761: VCU118RocketSystem__GC0,
-reg__836: RocketTile__GCB0,
-divider: tracking_wrapper,
-muxpart__61: genesys2_rocket_top__GC0,
-reg__806: RocketTile__GCB0,
-case__634: RocketTile__GCB0,
-case__266: VCU118RocketSystem__GC0,
-case__499: RocketTile__GCB0,
-logic__1325: VCU118RocketSystem__GC0,
-logic__5010: FPU__GB2,
-TLAtomicAutomata_cbus: VCU118RocketSystem__GC0,
-logic__64: genesys2_rocket_top__GC0,
-muxpart__55: genesys2_rocket_top__GC0,
-logic__7565: VCU118RocketSystem__GC0,
-reg__103: genesys2_rocket_top__GC0,
-reg__797: RocketTile__GCB0,
-reg__1336: tracking_wrapper,
-logic__4717: FPU__GB2,
-reg__334: DCache,
-logic__5677: RocketTile__GCB0,
-logic__9591: TLToAPB,
-dsp48e1__47: tracking_wrapper,
-datapath__392: FPU__GB2,
-reg__422: RocketTile__GCB0,
-reg__48: genesys2_rocket_top__GC0,
-reg__118: VCU118RocketSystem__GC0,
-logic__7292: VCU118RocketSystem__GC0,
-logic__7031: VCU118RocketSystem__GC0,
-reg__674: RocketTile__GCB0,
-datapath__232: VCU118RocketSystem__GC0,
-logic__2678: DCache,
-datapath__369: FPU__GB1,
-case__1719: tracking_wrapper,
-logic__8916: tracking_wrapper,
-logic__8559: APBGpsBlock__GC0,
-logic__3895: FPU__GB2,
-case__1162: VCU118RocketSystem__GC0,
-logic__6649: RocketTile__GCB0,
-dsp48e1__5: APBGpsBlock__GC0,
-logic__122: genesys2_rocket_top__GC0,
-reg__1074: VCU118RocketSystem__GC0,
-logic__9312: tracking_wrapper,
-case__571: DCache,
-case__1331: APBGpsBlock__GC0,
-reg__944: VCU118RocketSystem__GC0,
-datapath__476: RocketTile__GCB0,
-logic__5291: RocketTile__GCB0,
-case__137: genesys2_rocket_top__GC0,
-logic__4286: FPU__GB1,
-reg__978: VCU118RocketSystem__GC0,
-logic__7411: VCU118RocketSystem__GC0,
-logic__9523: APBGpsBlock__GC0,
-logic__5910: RocketTile__GCB0,
-reg__1371: tracking_wrapper,
-logic__7985: VCU118RocketSystem__GC0,
-reg__294: VCU118RocketSystem__GC0,
-logic__1287: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__450: RocketTile__GCB0,
-reg__1151: APBGpsBlock__GC0,
-logic__1549: VCU118RocketSystem__GC0,
-counter__21: APBGpsBlock__GC0,
-logic__3481: FPU__GB1,
-logic__4733: FPU__GB2,
-logic__5528: RocketTile__GCB0,
-logic__6670: RocketTile__GCB0,
-reg__855: RocketTile__GCB0,
-case__345: VCU118RocketSystem__GC0,
-logic__3785: FPU__GB2,
-logic__1464: VCU118RocketSystem__GC0,
-logic__808: VCU118RocketSystem__GC0,
-logic__9456: tracking_wrapper,
-logic__1146: VCU118RocketSystem__GC0,
-case__763: FPU__GB2,
-reg__764: RocketTile__GCB0,
-case__904: RocketTile__GCB0,
-case__1736: TLToAPB,
-ram__1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__5339: RocketTile__GCB0,
-case__1189: VCU118RocketSystem__GC0,
-case__192: genesys2_rocket_top__GC0,
-datapath__98: VCU118RocketSystem__GC0,
-logic__5653: RocketTile__GCB0,
-logic__2736: DCache,
-case__968: RocketTile__GCB0,
-case__1717: tracking_wrapper,
-reg__1036: VCU118RocketSystem__GC0,
-logic__7059: VCU118RocketSystem__GC0,
-logic__2667: DCache,
-logic__2390: DCache,
-reg__517: FPU__GB1,
-logic__9315: tracking_wrapper,
-logic__8957: tracking_wrapper,
-logic__8580: APBGpsBlock__GC0,
-reg__193: VCU118RocketSystem__GC0,
-logic__1692: VCU118RocketSystem__GC0,
-reg__328: DCache,
-logic__4662: FPU__GB2,
-reg__423: RocketTile__GCB0,
-case__227: genesys2_rocket_top__GC0,
-datapath__454: RocketTile__GCB0,
-datapath__561: APBGpsBlock__GC0,
-logic__358: genesys2_rocket_top__GC0,
-case__139: genesys2_rocket_top__GC0,
-reg__1240: tracking_wrapper,
-logic__7398: VCU118RocketSystem__GC0,
-reg__452: RocketTile__GCB0,
-logic__632: genesys2_rocket_top__GC0,
-PeripheryBus_pbus: VCU118RocketSystem__GC0,
-logic__9579: TLToAPB,
-case__607: RocketTile__GCB0,
-muxpart__246: RocketTile__GCB0,
-reg__957: VCU118RocketSystem__GC0,
-logic__6655: RocketTile__GCB0,
-logic__6925: VCU118RocketSystem__GC0,
-datapath__453: RocketTile__GCB0,
-case__1137: VCU118RocketSystem__GC0,
-case__1562: tracking_wrapper,
-reg__321: DCache,
-case__1053: VCU118RocketSystem__GC0,
-logic__4183: FPU__GB1,
-logic__4679: FPU__GB2,
-logic__2156: DCache,
-reg__349: DCache,
-case__1293: APBGpsBlock__GC0,
-reg__909: VCU118RocketSystem__GC0,
-logic__1795: VCU118RocketSystem__GC0,
-logic__971: VCU118RocketSystem__GC0,
-logic__4019: FPU__GB2,
-logic__1450: VCU118RocketSystem__GC0,
-case__251: VCU118RocketSystem__GC0,
-logic__4996: FPU__GB1,
-reg__646: FPU__GB1,
-rom__5: APBGpsBlock__GC0,
-datapath__82: VCU118RocketSystem__GC0,
-case__1014: VCU118RocketSystem__GC0,
-logic__3835: FPU__GB2,
-logic__7951: VCU118RocketSystem__GC0,
-datapath__494: VCU118RocketSystem__GC0,
-reg__1173: APBGpsBlock__GC0,
-reg__136: VCU118RocketSystem__GC0,
-reg__329: DCache,
-case__1033: VCU118RocketSystem__GC0,
-logic__8882: tracking_wrapper,
-logic__6919: VCU118RocketSystem__GC0,
-INToRecFN: FPU__GB2,
-logic__1165: VCU118RocketSystem__GC0,
-reg__247: VCU118RocketSystem__GC0,
-logic__8679: APBGpsBlock__GC0,
-datapath__268: DCache,
-logic__1910: VCU118RocketSystem__GC0,
-case__1573: tracking_wrapper,
-case__1376: APBGpsBlock__GC0,
-logic__4726: FPU__GB2,
-logic__789: VCU118RocketSystem__GC0,
-logic__7973: VCU118RocketSystem__GC0,
-logic__7904: VCU118RocketSystem__GC0,
-logic__7685: VCU118RocketSystem__GC0,
-case__1677: tracking_wrapper,
-reg__309: VCU118RocketSystem__GC0,
-logic__2261: DCache,
-logic__2089: RocketTile__GCB0,
-case__1643: tracking_wrapper,
-datapath__353: FPU__GB2,
-reg__418: RocketTile__GCB0,
-logic__7048: VCU118RocketSystem__GC0,
-reg__275: VCU118RocketSystem__GC0,
-reg__796: RocketTile__GCB0,
-case__661: FPU__GB2, FPU__GB1,
-logic__6806: VCU118RocketSystem__GC0,
-logic__8327: APBGpsBlock__GC0,
-extram__8: APBGpsBlock__GC0,
-muxpart__8: genesys2_rocket_top__GC0,
-logic__938: VCU118RocketSystem__GC0,
-reg__1290: tracking_wrapper,
-reg__131: VCU118RocketSystem__GC0,
-logic__4554: FPU__GB2, FPU__GB1,
-counter__1: genesys2_rocket_top__GC0,
-logic__8175: VCU118RocketSystem__GC0,
-logic__5975: RocketTile__GCB0,
-datapath__150: VCU118RocketSystem__GC0,
-case__825: RocketTile__GCB0,
-logic__7648: VCU118RocketSystem__GC0,
-case__1047: VCU118RocketSystem__GC0,
-logic__5004: FPU__GB2,
-case__1571: tracking_wrapper,
-case__847: RocketTile__GCB0,
-counter__20: APBGpsBlock__GC0,
-logic__4345: FPU__GB1,
-logic__4851: FPU__GB2,
-logic__2619: DCache,
-case__1636: tracking_wrapper,
-logic__1456: VCU118RocketSystem__GC0,
-reg__443: RocketTile__GCB0,
-reg__237: VCU118RocketSystem__GC0,
-reg__553: FPU__GB1,
-logic__1836: VCU118RocketSystem__GC0,
-case__166: genesys2_rocket_top__GC0,
-Repeater_TLBundleA_a26d64s2k1z3u: VCU118RocketSystem__GC0,
-reg__532: FPU__GB2,
-logic__5477: RocketTile__GCB0,
-logic__5521: RocketTile__GCB0,
-logic__3871: FPU__GB2,
-Queue2_TLBundleA_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__4136: FPU__GB2,
-FPU__GB0: FPU__GB0,
-logic__3333: FPU__GB1,
-datapath__38: VCU118RocketSystem__GC0,
-case__1164: VCU118RocketSystem__GC0,
-MulAddRecFNPipe_l2_e11_s53: FPU__GB1,
-muxpart__58: genesys2_rocket_top__GC0,
-case__134: genesys2_rocket_top__GC0,
-case__358: VCU118RocketSystem__GC0,
-datapath__70: VCU118RocketSystem__GC0,
-logic__8919: tracking_wrapper,
-logic__5699: RocketTile__GCB0,
-reg__1328: tracking_wrapper,
-reg__91: genesys2_rocket_top__GC0,
-logic__9556: APBGpsBlock__GC0,
-logic__4971: FPU__GB2,
-datapath__126: VCU118RocketSystem__GC0,
-reg__516: FPU__GB1,
-reg__1057: VCU118RocketSystem__GC0,
-reg__430: RocketTile__GCB0,
-logic__4135: FPU__GB2,
-logic__7154: VCU118RocketSystem__GC0,
-logic__6987: VCU118RocketSystem__GC0,
-case__1007: VCU118RocketSystem__GC0,
-logic__2208: DCache,
-logic__1017: VCU118RocketSystem__GC0,
-datapath__375: FPU__GB1,
-MulDiv: RocketTile__GCB0,
-case__1487: APBGpsBlock__GC0,
-logic__2661: DCache,
-muxpart__60: genesys2_rocket_top__GC0,
-logic__9563: APBGpsBlock__GC0,
-logic__1529: VCU118RocketSystem__GC0,
-logic__3488: FPU__GB1,
-logic__4781: FPU__GB2,
-case__381: VCU118RocketSystem__GC0,
-muxpart__177: FPU__GB0,
-logic__5871: RocketTile__GCB0,
-logic__9027: tracking_wrapper,
-logic__3283: RocketTile__GCB0,
-logic__638: genesys2_rocket_top__GC0,
-RoundRawFNToRecFN_1: FPU__GB2, FPU__GB1,
-case__215: genesys2_rocket_top__GC0,
-case__1250: VCU118RocketSystem__GC0,
-case__1032: VCU118RocketSystem__GC0,
-logic__8360: APBGpsBlock__GC0,
-logic__2082: RocketTile__GCB0,
-logic__3217: RocketTile__GCB0,
-reg__556: FPU__GB1,
-logic__2839: DCache,
-logic__2944: DCache,
-IntSyncCrossingSource_n1x1_Registered: VCU118RocketSystem__GC0,
-rockettile_icache_tag_array_0_64x21: RocketTile__GCB0,
-logic__8213: VCU118RocketSystem__GC0,
-logic__3512: FPU__GB1,
-logic__1553: VCU118RocketSystem__GC0,
-ErrorDeviceWrapper: VCU118RocketSystem__GC0,
-datapath__632: APBGpsBlock__GC0,
-case__1004: VCU118RocketSystem__GC0,
-reg__1429: TLToAPB,
-reg__1022: VCU118RocketSystem__GC0,
-logic__1344: VCU118RocketSystem__GC0,
-logic__8227: VCU118RocketSystem__GC0,
-reg__220: VCU118RocketSystem__GC0,
-logic__2121: RocketTile__GCB0,
-logic__8617: APBGpsBlock__GC0,
-datapath__109: VCU118RocketSystem__GC0,
-logic__4507: FPU__GB1,
-logic__5501: RocketTile__GCB0,
-logic__123: genesys2_rocket_top__GC0,
-logic__7146: VCU118RocketSystem__GC0,
-logic__1318: VCU118RocketSystem__GC0,
-reg__1136: APBGpsBlock__GC0,
-reg: genesys2_rocket_top__GC0,
-logic__7416: VCU118RocketSystem__GC0,
-logic__7023: VCU118RocketSystem__GC0,
-genesys2_rocket_top__GC0: genesys2_rocket_top__GC0,
-case__1126: VCU118RocketSystem__GC0,
-logic__3980: FPU__GB2,
-logic__514: genesys2_rocket_top__GC0,
-reg__626: FPU__GB2,
-logic__5783: RocketTile__GCB0,
-logic__4727: FPU__GB2,
-reg__485: FPU__GB0,
-logic__3652: FPU__GB2, FPU__GB1,
-reg__1333: tracking_wrapper,
-reg__43: genesys2_rocket_top__GC0,
-logic__1967: VCU118RocketSystem__GC0,
-case__783: FPU__GB2,
-Arbiter2_Valid_PTWReq: RocketTile__GCB0,
-HellaCacheArbiter: RocketTile__GCB0,
-logic__8956: tracking_wrapper,
-case__1607: tracking_wrapper,
-logic__7230: VCU118RocketSystem__GC0,
-reg__929: VCU118RocketSystem__GC0,
-reg__1181: APBGpsBlock__GC0,
-logic__2108: RocketTile__GCB0,
-reg__1174: APBGpsBlock__GC0,
-logic__989: VCU118RocketSystem__GC0,
-logic__8695: APBGpsBlock__GC0,
-reg__211: VCU118RocketSystem__GC0,
-logic__5106: FPU__GB1,
-case__699: FPU__GB2,
-ICache: RocketTile__GCB0,
-logic__7691: VCU118RocketSystem__GC0,
-case__252: VCU118RocketSystem__GC0,
-reg__661: FPU__GB1,
-logic__3189: RocketTile__GCB0,
-reg__1095: APBGpsBlock__GC0,
-logic__851: VCU118RocketSystem__GC0,
-reg__1299: tracking_wrapper,
-logic__4654: FPU__GB2,
-datapath__564: APBGpsBlock__GC0,
-logic__4697: FPU__GB2,
-logic__5270: RocketTile__GCB0,
-reg__766: RocketTile__GCB0,
-reg__642: FPU__GB1,
-logic__3487: FPU__GB1,
-logic__4195: FPU__GB1,
-logic__2819: DCache,
-logic__7078: VCU118RocketSystem__GC0,
-logic__6809: VCU118RocketSystem__GC0,
-reg__776: RocketTile__GCB0,
-datapath__480: RocketTile__GCB0,
-case__776: FPU__GB1,
-muxpart__216: FPU__GB0,
-reg__625: FPU__GB1,
-logic__5836: RocketTile__GCB0,
-datapath__580: APBGpsBlock__GC0,
-logic__54: genesys2_rocket_top__GC0,
-muxpart__79: genesys2_rocket_top__GC0,
-logic__1490: VCU118RocketSystem__GC0,
-logic__4364: FPU__GB1,
-logic__4843: FPU__GB2,
-reg__1291: tracking_wrapper,
-logic__6138: RocketTile__GCB0,
-logic__9118: tracking_wrapper,
-logic__4738: FPU__GB2,
-datapath__526: VCU118RocketSystem__GC0,
-reg__261: VCU118RocketSystem__GC0,
-reg__116: VCU118RocketSystem__GC0,
-case__1083: VCU118RocketSystem__GC0,
-logic__1563: VCU118RocketSystem__GC0,
-logic__2166: DCache,
-reg__454: RocketTile__GCB0,
-logic__1564: VCU118RocketSystem__GC0,
-case__756: FPU__GB2,
-logic__7424: VCU118RocketSystem__GC0,
-logic__7036: VCU118RocketSystem__GC0,
-reg__1072: VCU118RocketSystem__GC0,
-logic__1911: VCU118RocketSystem__GC0,
-reg__184: VCU118RocketSystem__GC0,
-case__868: RocketTile__GCB0,
-logic__2172: DCache,
-case__859: RocketTile__GCB0,
-AsyncQueueSink_DebugInternalBundle: VCU118RocketSystem__GC0,
-reg__235: VCU118RocketSystem__GC0,
-logic__4299: FPU__GB1,
-logic__6688: RocketTile__GCB0,
-logic__5688: RocketTile__GCB0,
-logic__6326: RocketTile__GCB0,
-reg__157: VCU118RocketSystem__GC0,
-case__1733: APBGpsBlock__GC0,
-logic__5903: RocketTile__GCB0,
-logic__4479: FPU__GB1,
-case__1042: VCU118RocketSystem__GC0,
-logic__2333: DCache,
-case__1063: VCU118RocketSystem__GC0,
-logic__7465: VCU118RocketSystem__GC0,
-reg__186: VCU118RocketSystem__GC0,
-reg__635: FPU__GB1,
-datapath__421: RocketTile__GCB0,
-muxpart__69: genesys2_rocket_top__GC0,
-logic__6902: VCU118RocketSystem__GC0,
-case__351: VCU118RocketSystem__GC0,
-logic__5083: FPU__GB0,
-case__580: RocketTile__GCB0,
-reg__1158: APBGpsBlock__GC0,
-reg__1217: APBGpsBlock__GC0,
-logic__6591: RocketTile__GCB0,
-case__1478: APBGpsBlock__GC0,
-logic__5529: RocketTile__GCB0,
-datapath__583: APBGpsBlock__GC0,
-case__1746: VCU118RocketSystem__GC0,
-logic__1074: VCU118RocketSystem__GC0,
-logic__924: VCU118RocketSystem__GC0,
-logic__6644: RocketTile__GCB0,
-datapath__389: FPU__GB2,
-case__1108: VCU118RocketSystem__GC0,
-logic__9318: tracking_wrapper,
-datapath__376: FPU__GB1,
-logic__4807: FPU__GB2,
-datapath__4: genesys2_rocket_top__GC0,
-logic__5947: RocketTile__GCB0,
-reg__869: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__1071: VCU118RocketSystem__GC0,
-logic__6654: RocketTile__GCB0,
-logic__5066: FPU__GB1,
-case__373: VCU118RocketSystem__GC0,
-case__323: VCU118RocketSystem__GC0,
-dsp48e1: FPU__GB1,
-logic__3628: FPU__GB2, FPU__GB1,
-logic__6536: RocketTile__GCB0,
-logic__6175: RocketTile__GCB0,
-case__998: VCU118RocketSystem__GC0,
-datapath__256: VCU118RocketSystem__GC0,
-logic__5604: RocketTile__GCB0,
-datapath__452: RocketTile__GCB0,
-reg__1112: APBGpsBlock__GC0,
-case__1604: tracking_wrapper,
-logic__5797: RocketTile__GCB0,
-logic__5898: RocketTile__GCB0,
-cacode_gen_trck: tracking_wrapper,
-logic__7570: VCU118RocketSystem__GC0,
-logic__7903: VCU118RocketSystem__GC0,
-logic__9424: tracking_wrapper,
-case__937: RocketTile__GCB0,
-datapath__493: VCU118RocketSystem__GC0,
-reg__1237: tracking_wrapper,
-case__944: RocketTile__GCB0,
-logic__9399: tracking_wrapper,
-reg__373: DCache,
-logic__5284: RocketTile__GCB0,
-case__1284: APBGpsBlock__GC0,
-logic__9373: tracking_wrapper,
-logic__9570: TLToAPB,
-reg__670: RocketTile__GCB0,
-logic__6026: RocketTile__GCB0,
-reg__445: RocketTile__GCB0,
-datapath__670: tracking_wrapper,
-logic__9197: tracking_wrapper,
-logic__3337: FPU__GB1,
-logic__1358: VCU118RocketSystem__GC0,
-logic__5395: RocketTile__GCB0,
-logic__4774: FPU__GB2,
-reg__926: VCU118RocketSystem__GC0, APBGpsBlock__GC0,
-logic__3086: RocketTile__GCB0,
-logic__7882: VCU118RocketSystem__GC0,
-logic__5281: RocketTile__GCB0,
-datapath__578: APBGpsBlock__GC0,
-logic__6928: VCU118RocketSystem__GC0,
-logic__1089: VCU118RocketSystem__GC0,
-muxpart__218: FPU__GB0,
-logic__863: VCU118RocketSystem__GC0,
-case__1577: tracking_wrapper,
-case__1600: tracking_wrapper,
-case__983: RocketTile__GCB0,
-logic__889: VCU118RocketSystem__GC0,
-case__1735: TLToAPB,
-logic__2083: RocketTile__GCB0,
-muxpart__205: FPU__GB0,
-TLDebugModule: VCU118RocketSystem__GC0,
-logic__5235: RocketTile__GCB0,
-reg__1213: APBGpsBlock__GC0,
-logic__2820: DCache,
-logic__5977: RocketTile__GCB0,
-reg__77: genesys2_rocket_top__GC0,
-logic__3854: FPU__GB2,
-case__1149: VCU118RocketSystem__GC0,
-logic__5252: RocketTile__GCB0,
-case__869: RocketTile__GCB0,
-logic__6647: RocketTile__GCB0,
-logic__6535: RocketTile__GCB0,
-logic__8051: VCU118RocketSystem__GC0,
-logic__4308: FPU__GB1,
-datapath__582: APBGpsBlock__GC0,
-logic__7369: VCU118RocketSystem__GC0,
-logic__3578: FPU__GB1,
-logic__3565: FPU__GB1,
-datapath__373: FPU__GB1,
-logic__2159: DCache,
-muxpart__187: FPU__GB0,
-logic__9039: tracking_wrapper,
-muxpart__13: genesys2_rocket_top__GC0,
-reg__599: FPU__GB2,
-logic__3205: RocketTile__GCB0,
-logic__2005: VCU118RocketSystem__GC0,
-logic__2280: DCache,
-logic__7291: VCU118RocketSystem__GC0,
-logic__6999: VCU118RocketSystem__GC0,
-logic__2017: VCU118RocketSystem__GC0,
-logic__5908: RocketTile__GCB0,
-reg__634: FPU__GB1,
-reg__1002: VCU118RocketSystem__GC0,
-logic__6537: RocketTile__GCB0,
-case__154: genesys2_rocket_top__GC0,
-case__401: VCU118RocketSystem__GC0,
-logic__4301: FPU__GB1,
-logic__6689: RocketTile__GCB0,
-logic__5496: RocketTile__GCB0,
-logic__901: VCU118RocketSystem__GC0,
-logic__6349: RocketTile__GCB0,
-case__148: genesys2_rocket_top__GC0,
-logic__4346: FPU__GB1,
-logic__830: VCU118RocketSystem__GC0,
-case__1306: APBGpsBlock__GC0,
-logic__6132: RocketTile__GCB0,
-case__1631: tracking_wrapper,
-TLFragmenter_FPGAGPS: VCU118RocketSystem__GC0,
-SynchronizerShiftReg_w1_d3: TilePRCIDomain__GC0,
-logic__1319: VCU118RocketSystem__GC0,
-logic__2955: DCache,
-case__815: RocketTile__GCB0,
-case__1173: VCU118RocketSystem__GC0,
-logic__1816: VCU118RocketSystem__GC0,
-reg__411: RocketTile__GCB0,
-logic__603: genesys2_rocket_top__GC0,
-logic__3710: FPU__GB2,
-datapath__417: RocketTile__GCB0,
-reg__1060: VCU118RocketSystem__GC0,
-reg__883: VCU118RocketSystem__GC0,
-case__386: VCU118RocketSystem__GC0,
-datapath__511: VCU118RocketSystem__GC0,
-logic__3584: FPU__GB1,
-reg__595: FPU__GB2,
-logic__9030: tracking_wrapper,
-datapath__400: FPU__GB2,
-logic__5167: RocketTile__GCB0,
-logic__3284: RocketTile__GCB0,
-logic__2018: VCU118RocketSystem__GC0,
-TLWidthWidget8_3: VCU118RocketSystem__GC0,
-case__1223: VCU118RocketSystem__GC0,
-logic__6881: VCU118RocketSystem__GC0,
-case__264: VCU118RocketSystem__GC0,
-DMIToTL: VCU118RocketSystem__GC0,
-case__258: VCU118RocketSystem__GC0,
-logic__343: genesys2_rocket_top__GC0,
-signinv__2: APBGpsBlock__GC0,
-muxpart__56: genesys2_rocket_top__GC0,
-case__800: FPU__GB1,
-logic__8044: VCU118RocketSystem__GC0,
-case__403: VCU118RocketSystem__GC0,
-logic__7418: VCU118RocketSystem__GC0,
-logic__5921: RocketTile__GCB0,
-logic__4775: FPU__GB2,
-reg__1054: VCU118RocketSystem__GC0,
-case__250: VCU118RocketSystem__GC0,
-logic__793: VCU118RocketSystem__GC0,
-case__564: DCache,
-reg__964: VCU118RocketSystem__GC0,
-TLFIFOFixer_2: VCU118RocketSystem__GC0,
-case__769: FPU__GB2,
-reg__1179: APBGpsBlock__GC0,
-case__434: VCU118RocketSystem__GC0,
-reg__580: FPU__GB1,
-logic__6034: RocketTile__GCB0,
-counter__19: APBGpsBlock__GC0,
-logic__8604: APBGpsBlock__GC0,
-logic__5964: RocketTile__GCB0,
-AsyncQueueSource_TLBundleD_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-case__1209: VCU118RocketSystem__GC0,
-reg__891: VCU118RocketSystem__GC0,
-logic__5391: RocketTile__GCB0,
-case__806: FPU__GB1,
-logic__2443: DCache,
-Rocket: RocketTile__GCB0,
-case__1393: APBGpsBlock__GC0,
-case__663: FPU__GB2, FPU__GB1,
-logic__7150: VCU118RocketSystem__GC0,
-logic__1321: VCU118RocketSystem__GC0,
-muxpart__11: genesys2_rocket_top__GC0,
-logic__8273: VCU118RocketSystem__GC0,
-case__813: RocketTile__GCB0,
-logic__163: genesys2_rocket_top__GC0,
-datapath__525: VCU118RocketSystem__GC0,
-logic__9374: tracking_wrapper,
-logic__9340: tracking_wrapper,
-logic__2960: DCache,
-Frontend: RocketTile__GCB0,
-reg__658: FPU__GB1,
-case__314: VCU118RocketSystem__GC0,
-logic__2190: DCache,
-reg__1412: tracking_wrapper,
-reg__55: genesys2_rocket_top__GC0,
-logic__2904: DCache,
-logic__743: genesys2_rocket_top__GC0,
-logic__1339: VCU118RocketSystem__GC0,
-case__1323: APBGpsBlock__GC0,
-reg__705: RocketTile__GCB0,
-logic__9032: tracking_wrapper,
-logic__3094: RocketTile__GCB0,
-datapath__533: VCU118RocketSystem__GC0,
-datapath__191: VCU118RocketSystem__GC0,
-logic__4759: FPU__GB2,
-logic__532: genesys2_rocket_top__GC0,
-logic__1132: VCU118RocketSystem__GC0,
-reg__301: VCU118RocketSystem__GC0,
-logic__7362: VCU118RocketSystem__GC0,
-reg__768: RocketTile__GCB0,
-logic__6277: RocketTile__GCB0,
-case__1429: APBGpsBlock__GC0,
-reg__1363: tracking_wrapper,
-logic__4523: FPU__GB2, FPU__GB1,
-logic__4142: FPU__GB2,
-reg__1015: VCU118RocketSystem__GC0,
-reg__412: RocketTile__GCB0,
-logic__9263: tracking_wrapper,
-case__21: genesys2_rocket_top__GC0,
-reg__1307: tracking_wrapper,
-reg__313: VCU118RocketSystem__GC0,
-case__578: RocketTile__GCB0,
-datapath__22: genesys2_rocket_top__GC0,
-logic__7157: VCU118RocketSystem__GC0,
-logic__5565: RocketTile__GCB0,
-dsp48e1__7: APBGpsBlock__GC0,
-logic__9019: tracking_wrapper,
-reg__1250: tracking_wrapper,
-logic__4344: FPU__GB1,
-case__546: DCache,
-logic__3090: RocketTile__GCB0,
-reg__26: genesys2_rocket_top__GC0,
-counter__11: VCU118RocketSystem__GC0,
-addsub: APBGpsBlock__GC0,
-logic__7075: VCU118RocketSystem__GC0,
-logic__1162: VCU118RocketSystem__GC0,
-datapath__59: VCU118RocketSystem__GC0,
-reg__940: VCU118RocketSystem__GC0,
-logic__550: genesys2_rocket_top__GC0,
-reg__36: genesys2_rocket_top__GC0,
-logic__7027: VCU118RocketSystem__GC0,
-case__1220: VCU118RocketSystem__GC0,
-logic__7780: VCU118RocketSystem__GC0,
-datapath__359: FPU__GB2,
-logic__5989: RocketTile__GCB0,
-muxpart__223: FPU__GB0,
-case__1023: VCU118RocketSystem__GC0,
-case__1242: VCU118RocketSystem__GC0,
-reg__1428: TLToAPB,
-reg__158: VCU118RocketSystem__GC0,
-logic__891: VCU118RocketSystem__GC0,
-datapath__329: FPU__GB2,
-datapath__658: tracking_wrapper,
-logic__3476: FPU__GB1,
-case__301: VCU118RocketSystem__GC0,
-logic__8693: APBGpsBlock__GC0,
-reg__1249: tracking_wrapper,
-logic__5405: RocketTile__GCB0,
-case__318: VCU118RocketSystem__GC0,
-reg__1409: tracking_wrapper,
-logic__2: genesys2_rocket_top__GC0,
-reg__871: VCU118RocketSystem__GC0,
-logic__1409: VCU118RocketSystem__GC0,
-datapath__9: genesys2_rocket_top__GC0,
-logic__1577: VCU118RocketSystem__GC0,
-logic__6100: RocketTile__GCB0,
-logic__4199: FPU__GB1,
-logic__6992: VCU118RocketSystem__GC0,
-extladd: RocketTile__GCB0,
-Repeater_TLBundleA_a32d64s2k1z3u: RocketTile__GCB0,
-logic__3275: RocketTile__GCB0,
-case__1482: APBGpsBlock__GC0,
-TLBuffer_a32d64s2k1z4u_1: VCU118RocketSystem__GC0,
-logic__3105: RocketTile__GCB0,
-reg__963: VCU118RocketSystem__GC0,
-reg__733: RocketTile__GCB0,
-muxpart__154: genesys2_rocket_top__GC0,
-case__649: FPU__GB1,
-logic__2711: DCache,
-logic__3036: RocketTile__GCB0,
-logic__1926: VCU118RocketSystem__GC0,
-TLFIFOFixer_1: VCU118RocketSystem__GC0,
-case__1302: APBGpsBlock__GC0,
-datapath__399: FPU__GB2,
-case__932: RocketTile__GCB0,
-reg__1221: tracking_wrapper,
-dsp48e1__33: tracking_wrapper,
-logic__1579: VCU118RocketSystem__GC0,
-case__874: RocketTile__GCB0,
-case__1602: tracking_wrapper,
-logic__2740: DCache,
-logic__6950: VCU118RocketSystem__GC0,
-datapath__248: VCU118RocketSystem__GC0,
-logic__5171: RocketTile__GCB0,
-logic__7171: VCU118RocketSystem__GC0,
-datapath__237: VCU118RocketSystem__GC0,
-logic__2288: DCache,
-case__860: RocketTile__GCB0,
-logic__4773: FPU__GB2,
-reg__995: VCU118RocketSystem__GC0,
-datapath__630: APBGpsBlock__GC0,
-logic__5971: RocketTile__GCB0,
-dsp48e1__38: tracking_wrapper,
-logic__7530: VCU118RocketSystem__GC0,
-reg__534: FPU__GB2,
-logic__6524: RocketTile__GCB0,
-counter__7: genesys2_rocket_top__GC0,
-logic__8248: VCU118RocketSystem__GC0,
-case__298: VCU118RocketSystem__GC0,
-muxpart__15: genesys2_rocket_top__GC0,
-reg__374: DCache,
-datapath__567: APBGpsBlock__GC0,
-case__1266: APBGpsBlock__GC0,
-case__1731: APBGpsBlock__GC0,
-case__1669: tracking_wrapper,
-datapath__5: genesys2_rocket_top__GC0,
-datapath__428: RocketTile__GCB0,
-logic__7079: VCU118RocketSystem__GC0,
-logic__8441: APBGpsBlock__GC0,
-case__916: RocketTile__GCB0,
-case__549: DCache,
-reg__736: RocketTile__GCB0,
-datapath__601: APBGpsBlock__GC0,
-TLDebugModuleOuter: VCU118RocketSystem__GC0,
-logic__9568: APBGpsBlock__GC0,
-reg__586: FPU__GB2,
-case__1249: VCU118RocketSystem__GC0,
-counter__24: APBGpsBlock__GC0,
-logic__5143: RocketTile__GCB0,
-datapath__621: APBGpsBlock__GC0,
-logic__1824: VCU118RocketSystem__GC0,
-logic__2293: DCache,
-logic__3317: FPU__GB1,
-muxpart__155: genesys2_rocket_top__GC0,
-logic__4177: FPU__GB1,
-reg__156: VCU118RocketSystem__GC0,
-datapath__608: APBGpsBlock__GC0,
-logic__720: genesys2_rocket_top__GC0,
-logic__7236: VCU118RocketSystem__GC0,
-logic__896: VCU118RocketSystem__GC0,
-logic__9239: tracking_wrapper,
-case__948: RocketTile__GCB0,
-logic__2878: DCache,
-case__812: RocketTile__GCB0,
-case__1254: VCU118RocketSystem__GC0,
-logic__5976: RocketTile__GCB0,
-logic__5895: RocketTile__GCB0,
-datapath__593: APBGpsBlock__GC0,
-logic__1217: VCU118RocketSystem__GC0,
-logic__9073: tracking_wrapper,
-case__1077: VCU118RocketSystem__GC0,
-case__986: VCU118RocketSystem__GC0,
-reg__755: RocketTile__GCB0,
-logic__4303: FPU__GB1,
-logic__8018: VCU118RocketSystem__GC0,
-reg__2: genesys2_rocket_top__GC0,
-reg__954: VCU118RocketSystem__GC0,
-logic__9271: tracking_wrapper,
-case__565: DCache,
-datapath__450: RocketTile__GCB0,
-datapath__638: APBGpsBlock__GC0,
-logic__6126: RocketTile__GCB0,
-datapath__187: VCU118RocketSystem__GC0,
-logic__5905: RocketTile__GCB0,
-logic__2547: DCache,
-reg__541: FPU__GB1,
-muxpart__64: genesys2_rocket_top__GC0,
-logic__1634: VCU118RocketSystem__GC0,
-datapath__84: VCU118RocketSystem__GC0,
-logic__9500: tracking_wrapper,
-logic__1661: VCU118RocketSystem__GC0,
-logic__2100: RocketTile__GCB0,
-datapath__615: APBGpsBlock__GC0,
-reg__1377: tracking_wrapper,
-case__833: RocketTile__GCB0,
-datapath__235: VCU118RocketSystem__GC0,
-logic__6512: RocketTile__GCB0,
-logic__5461: RocketTile__GCB0,
-logic__5399: RocketTile__GCB0,
-logic__3527: FPU__GB1,
-logic__300: genesys2_rocket_top__GC0,
-logic__128: genesys2_rocket_top__GC0,
-FPGAUARTClockSinkDomain: VCU118RocketSystem__GC0,
-datapath__698: tracking_wrapper,
-reg__767: RocketTile__GCB0,
-logic__5047: FPU__GB1,
-datapath__343: FPU__GB2,
-logic__2604: DCache,
-reg__448: RocketTile__GCB0,
-logic__5271: RocketTile__GCB0,
-logic__6666: RocketTile__GCB0,
-reg__603: FPU__GB2,
-logic__3200: RocketTile__GCB0,
-logic__594: genesys2_rocket_top__GC0,
-logic__8928: tracking_wrapper,
-reg__1375: tracking_wrapper,
-logic__8021: VCU118RocketSystem__GC0,
-logic__7603: VCU118RocketSystem__GC0,
-reg__249: VCU118RocketSystem__GC0,
-logic__6723: TilePRCIDomain__GC0,
-datapath__165: VCU118RocketSystem__GC0,
-logic__1817: VCU118RocketSystem__GC0,
-logic__8500: APBGpsBlock__GC0,
-datapath__610: APBGpsBlock__GC0,
-reg__594: FPU__GB2,
-logic__3556: FPU__GB1,
-logic__3625: FPU__GB2, FPU__GB1,
-logic__5204: RocketTile__GCB0,
-logic__1539: VCU118RocketSystem__GC0,
-reg__1390: tracking_wrapper,
-logic__4922: FPU__GB1,
-case__1012: VCU118RocketSystem__GC0,
-logic__3540: FPU__GB1,
-case__156: genesys2_rocket_top__GC0,
-logic__7110: VCU118RocketSystem__GC0,
-datapath__46: VCU118RocketSystem__GC0,
-case__53: genesys2_rocket_top__GC0,
-logic__109: genesys2_rocket_top__GC0,
-logic__7787: VCU118RocketSystem__GC0,
-logic__5348: RocketTile__GCB0,
-case__687: FPU__GB2,
-logic__7990: VCU118RocketSystem__GC0,
-logic__1895: VCU118RocketSystem__GC0,
-case__795: FPU__GB1,
-datapath__210: VCU118RocketSystem__GC0,
-logic__7158: VCU118RocketSystem__GC0,
-logic__1909: VCU118RocketSystem__GC0,
-logic__4428: FPU__GB1,
-reg__761: RocketTile__GCB0,
-reg__649: FPU__GB1,
-logic__605: genesys2_rocket_top__GC0,
-logic__1338: VCU118RocketSystem__GC0,
-datapath__105: VCU118RocketSystem__GC0,
-logic__9601: TLToAPB,
-datapath__263: DCache,
-muxpart__183: FPU__GB0,
-logic__7529: VCU118RocketSystem__GC0,
-reg__113: VCU118RocketSystem__GC0,
-logic__5516: RocketTile__GCB0,
-datapath__2: genesys2_rocket_top__GC0,
-logic__848: VCU118RocketSystem__GC0,
-muxpart__199: FPU__GB0,
-logic__6679: RocketTile__GCB0,
-case__270: VCU118RocketSystem__GC0,
-case__1141: VCU118RocketSystem__GC0,
-logic__1322: VCU118RocketSystem__GC0,
-logic__6813: VCU118RocketSystem__GC0,
-reg__820: RocketTile__GCB0,
-case__605: RocketTile__GCB0,
-logic__643: genesys2_rocket_top__GC0,
-logic__3233: RocketTile__GCB0,
-logic__7205: VCU118RocketSystem__GC0,
-logic__5438: RocketTile__GCB0,
-logic__5946: RocketTile__GCB0,
-logic__3676: FPU__GB2, FPU__GB1,
-logic__2914: DCache,
-reg__112: VCU118RocketSystem__GC0,
-logic__5792: RocketTile__GCB0,
-ram__6: RocketTile__GCB0,
-logic__2715: DCache,
-logic__3834: FPU__GB2,
-reg__13: genesys2_rocket_top__GC0,
-logic__7661: VCU118RocketSystem__GC0,
-case__1582: tracking_wrapper,
-logic__2171: DCache,
-datapath__283: DCache,
-logic__264: genesys2_rocket_top__GC0,
-logic__3649: FPU__GB2, FPU__GB1,
-logic__5062: FPU__GB1,
-TLInterconnectCoupler_cbus_to_bus_named_pbus: VCU118RocketSystem__GC0,
-case__626: RocketTile__GCB0,
-logic__6557: RocketTile__GCB0,
-logic__7210: VCU118RocketSystem__GC0,
-logic__6730: TilePRCIDomain__GC0,
-datapath__635: APBGpsBlock__GC0,
-logic__4377: FPU__GB1,
-reg__1422: tracking_wrapper,
-logic__3446: FPU__GB1,
-logic__2334: DCache,
-logic__1382: VCU118RocketSystem__GC0,
-logic__8952: tracking_wrapper,
-case__1374: APBGpsBlock__GC0,
-case__1662: tracking_wrapper,
-case__5: genesys2_rocket_top__GC0,
-case__550: DCache,
-logic__7284: VCU118RocketSystem__GC0,
-reg__1235: tracking_wrapper,
-logic__5973: RocketTile__GCB0,
-logic__5040: FPU__GB1,
-reg__619: FPU__GB1,
-datapath__662: tracking_wrapper,
-reg__183: VCU118RocketSystem__GC0,
-logic__8571: APBGpsBlock__GC0,
-logic__791: VCU118RocketSystem__GC0,
-case__548: DCache,
-case__1245: VCU118RocketSystem__GC0,
-muxpart__220: FPU__GB0,
-logic__4650: FPU__GB2,
-logic__3758: FPU__GB2,
-reg__109: genesys2_rocket_top__GC0,
-reg__1385: tracking_wrapper,
-TLFragmenter_1: RocketTile__GCB0,
-logic__5292: RocketTile__GCB0,
-logic__7553: VCU118RocketSystem__GC0,
-datapath__225: VCU118RocketSystem__GC0,
-logic__3058: RocketTile__GCB0,
-logic__7865: VCU118RocketSystem__GC0,
-reg__292: VCU118RocketSystem__GC0,
-logic__6738: VCU118RocketSystem__GC0,
-reg__794: RocketTile__GCB0,
-logic__5116: FPU__GB1,
-reg__1167: APBGpsBlock__GC0,
-datapath__457: RocketTile__GCB0,
-FPUFMAPipe_l3_f32: FPU__GB1,
-case__464: VCU118RocketSystem__GC0,
-logic__3984: FPU__GB2,
-case__584: RocketTile__GCB0,
-logic__3577: FPU__GB1,
-logic__6029: RocketTile__GCB0,
-logic__9326: tracking_wrapper,
-mult_53_53_106: FPU__GB1,
-case__1581: tracking_wrapper,
-case__1710: tracking_wrapper,
-logic__3238: RocketTile__GCB0,
-logic__5002: FPU__GB1,
-reg__1296: tracking_wrapper,
-logic__7589: VCU118RocketSystem__GC0,
-case__365: VCU118RocketSystem__GC0,
-logic__1260: VCU118RocketSystem__GC0,
-reg__440: RocketTile__GCB0,
-reg__1005: VCU118RocketSystem__GC0,
-logic__7262: VCU118RocketSystem__GC0,
-logic__1226: VCU118RocketSystem__GC0,
-logic__5562: RocketTile__GCB0,
-logic__6071: RocketTile__GCB0,
-logic__7370: VCU118RocketSystem__GC0,
-case__1480: APBGpsBlock__GC0,
-reg__590: FPU__GB2,
-mult_66_66_66: RocketTile__GCB0,
-counter__15: APBGpsBlock__GC0,
-logic__592: genesys2_rocket_top__GC0,
-case__297: VCU118RocketSystem__GC0,
-case__816: RocketTile__GCB0,
-logic__7020: VCU118RocketSystem__GC0,
-logic__6641: RocketTile__GCB0,
-reg__889: VCU118RocketSystem__GC0,
-datapath__100: VCU118RocketSystem__GC0,
-logic__4776: FPU__GB2,
-case__400: VCU118RocketSystem__GC0,
-logic__4840: FPU__GB2,
-datapath__295: RocketTile__GCB0,
-reg__918: VCU118RocketSystem__GC0,
-logic__4086: FPU__GB2,
-logic__6562: RocketTile__GCB0,
-TLBusBypassBar: VCU118RocketSystem__GC0,
-case__1002: VCU118RocketSystem__GC0,
-logic__879: VCU118RocketSystem__GC0,
-reg__815: RocketTile__GCB0,
-case__1107: VCU118RocketSystem__GC0,
-logic__3722: FPU__GB2,
-logic__6036: RocketTile__GCB0,
-datapath__297: RocketTile__GCB0,
-logic__4471: FPU__GB1,
-case__1100: VCU118RocketSystem__GC0,
-logic__4711: FPU__GB2,
-logic__726: genesys2_rocket_top__GC0,
-keep__9: genesys2_rocket_top__GC0,
-logic__5649: RocketTile__GCB0,
-case__566: DCache,
-case__165: genesys2_rocket_top__GC0,
-case__1174: VCU118RocketSystem__GC0,
-reg__839: RocketTile__GCB0,
-logic__1945: VCU118RocketSystem__GC0,
-logic__6513: RocketTile__GCB0,
-logic__6842: VCU118RocketSystem__GC0,
-reg__497: FPU__GB1,
-datapath__418: RocketTile__GCB0,
-muxpart__204: FPU__GB0,
-bit_gen: tracking_wrapper,
-case__1428: APBGpsBlock__GC0,
-logic__4822: FPU__GB2,
-datapath__346: FPU__GB2,
-logic__3759: FPU__GB2,
-case__276: VCU118RocketSystem__GC0,
-case__659: FPU__GB2, FPU__GB1,
-logic__4760: FPU__GB2,
-logic__939: VCU118RocketSystem__GC0,
-logic__4648: FPU__GB2,
-logic__2601: DCache,
-logic__7798: VCU118RocketSystem__GC0,
-case__674: FPU__GB2,
-logic__4712: FPU__GB2,
-reg__244: VCU118RocketSystem__GC0,
-logic__2833: DCache,
-logic__1335: VCU118RocketSystem__GC0,
-logic__9031: tracking_wrapper,
-logic__1558: VCU118RocketSystem__GC0,
-logic__7961: VCU118RocketSystem__GC0,
-datapath__60: VCU118RocketSystem__GC0,
-logic__4780: FPU__GB2,
-logic__7634: VCU118RocketSystem__GC0,
-logic__5988: RocketTile__GCB0,
-reg__785: RocketTile__GCB0,
-datapath__25: genesys2_rocket_top__GC0,
-logic__7527: VCU118RocketSystem__GC0,
-reg__278: VCU118RocketSystem__GC0,
-logic__8774: APBGpsBlock__GC0,
-reg__1405: tracking_wrapper,
-logic__4770: FPU__GB2,
-logic__1703: VCU118RocketSystem__GC0,
-logic__2874: DCache,
-logic__2062: RocketTile__GCB0,
-logic__3029: RocketTile__GCB0,
-case__292: VCU118RocketSystem__GC0,
-reg__33: genesys2_rocket_top__GC0,
-datapath__67: VCU118RocketSystem__GC0,
-logic__4784: FPU__GB2,
-logic__5974: RocketTile__GCB0,
-logic__3101: RocketTile__GCB0,
-muxpart__162: DCache,
-logic__4930: FPU__GB1,
-logic__8201: VCU118RocketSystem__GC0,
-logic__7353: VCU118RocketSystem__GC0,
-case__324: VCU118RocketSystem__GC0,
-muxpart__38: genesys2_rocket_top__GC0,
-datapath__650: tracking_wrapper,
-logic__5868: RocketTile__GCB0,
-logic__7306: VCU118RocketSystem__GC0,
-reg__1083: VCU118RocketSystem__GC0,
-logic__5490: RocketTile__GCB0,
-logic__876: VCU118RocketSystem__GC0,
-logic__8700: APBGpsBlock__GC0,
-logic__5069: FPU__GB1,
-muxpart__259: RocketTile__GCB0,
-case__62: genesys2_rocket_top__GC0,
-logic__3118: RocketTile__GCB0,
-reg__1169: APBGpsBlock__GC0,
-logic__6559: RocketTile__GCB0,
-logic__7859: VCU118RocketSystem__GC0,
-logic__7504: VCU118RocketSystem__GC0,
-logic__6636: RocketTile__GCB0,
-reg__898: VCU118RocketSystem__GC0,
-logic__3457: FPU__GB1,
-logic__2200: DCache,
-reg__656: FPU__GB1,
-logic__8195: VCU118RocketSystem__GC0,
-case__405: VCU118RocketSystem__GC0,
-logic__5577: RocketTile__GCB0,
-muxpart__5: genesys2_rocket_top__GC0,
-reg__952: VCU118RocketSystem__GC0,
-logic__1180: VCU118RocketSystem__GC0,
-reg__566: FPU__GB1,
-reg__1256: tracking_wrapper,
-reg__1352: tracking_wrapper,
-logic__9343: tracking_wrapper,
-muxpart__22: genesys2_rocket_top__GC0,
-logic__7123: VCU118RocketSystem__GC0,
-logic__2797: DCache,
-logic__3129: RocketTile__GCB0,
-logic__4752: FPU__GB2,
-reg__680: RocketTile__GCB0,
-case__658: FPU__GB2, FPU__GB1,
-reg__1431: TLToAPB,
-logic__9301: tracking_wrapper,
-logic__10: genesys2_rocket_top__GC0,
-logic__2330: DCache,
-logic__1932: VCU118RocketSystem__GC0,
-reg__108: genesys2_rocket_top__GC0,
-case__1377: APBGpsBlock__GC0,
-logic__7439: VCU118RocketSystem__GC0,
-logic__6808: VCU118RocketSystem__GC0,
-case__339: VCU118RocketSystem__GC0,
-logic__8024: VCU118RocketSystem__GC0,
-case__507: RocketTile__GCB0,
-logic__3831: FPU__GB2,
-case__383: VCU118RocketSystem__GC0,
-case__959: RocketTile__GCB0,
-case__862: RocketTile__GCB0,
-case__935: RocketTile__GCB0,
-sample_align: APBGpsBlock__GC0,
-logic__8973: tracking_wrapper,
-logic__6517: RocketTile__GCB0,
-datapath__186: VCU118RocketSystem__GC0,
-logic__4182: FPU__GB1,
-logic__3898: FPU__GB2,
-DivSqrtRecFN_small: FPU__GB2,
-logic__3130: RocketTile__GCB0,
-logic__8299: VCU118RocketSystem__GC0,
-logic__4819: FPU__GB2,
-reg__439: RocketTile__GCB0,
-case__1368: APBGpsBlock__GC0,
-reg__648: FPU__GB1,
-case__732: FPU__GB2, FPU__GB1,
-datapath__81: VCU118RocketSystem__GC0,
-logic__9033: tracking_wrapper,
-reg__915: VCU118RocketSystem__GC0,
-logic__1974: VCU118RocketSystem__GC0,
-logic__333: genesys2_rocket_top__GC0,
-datapath__61: VCU118RocketSystem__GC0,
-logic__6678: RocketTile__GCB0,
-case__255: VCU118RocketSystem__GC0,
-dsp48e1__22: APBGpsBlock__GC0,
-reg__1305: tracking_wrapper,
-datapath__440: RocketTile__GCB0,
-datapath__478: RocketTile__GCB0,
-logic__1484: VCU118RocketSystem__GC0,
-muxpart__74: genesys2_rocket_top__GC0,
-logic__7382: VCU118RocketSystem__GC0,
-case__1425: APBGpsBlock__GC0,
-logic__2050: VCU118RocketSystem__GC0,
-case__1674: tracking_wrapper,
-logic__3515: FPU__GB1,
-muxpart__255: RocketTile__GCB0,
-reg__1394: tracking_wrapper,
-case__1558: tracking_wrapper,
-logic__5840: RocketTile__GCB0,
-logic__5684: RocketTile__GCB0,
-reg__1126: APBGpsBlock__GC0,
-reg__1159: APBGpsBlock__GC0,
-logic__9156: tracking_wrapper,
-reg__919: VCU118RocketSystem__GC0,
-logic__1244: VCU118RocketSystem__GC0,
-reg__406: RocketTile__GCB0,
-logic__7445: VCU118RocketSystem__GC0,
-logic__195: genesys2_rocket_top__GC0,
-logic__860: VCU118RocketSystem__GC0,
-logic__3350: FPU__GB1,
-datapath__144: VCU118RocketSystem__GC0,
-case__759: FPU__GB2,
-datapath__23: genesys2_rocket_top__GC0,
-reg__1286: tracking_wrapper,
-logic__7426: VCU118RocketSystem__GC0,
-reg__1338: tracking_wrapper,
-logic__2101: RocketTile__GCB0,
-logic__8262: VCU118RocketSystem__GC0,
-logic__9212: tracking_wrapper,
-datapath__233: VCU118RocketSystem__GC0,
-datapath__94: VCU118RocketSystem__GC0,
-datapath__334: FPU__GB2,
-reg__392: RocketTile__GCB0,
-logic__665: genesys2_rocket_top__GC0,
-reg__962: VCU118RocketSystem__GC0,
-reg__145: VCU118RocketSystem__GC0,
-extladd__1: tracking_wrapper,
-datapath__600: APBGpsBlock__GC0,
-logic__1482: VCU118RocketSystem__GC0,
-logic__4357: FPU__GB1,
-MulAddRecFNToRaw_postMul: FPU__GB1,
-case__1507: APBGpsBlock__GC0,
-logic__5152: RocketTile__GCB0,
-TLError_1: VCU118RocketSystem__GC0,
-reg__921: VCU118RocketSystem__GC0,
-logic__4889: FPU__GB2,
-case__1493: APBGpsBlock__GC0,
-case__454: VCU118RocketSystem__GC0,
-logic__9051: tracking_wrapper,
-case__226: genesys2_rocket_top__GC0,
-datapath__205: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_sbus_to_bus_named_cbus: VCU118RocketSystem__GC0,
-keep__1: genesys2_rocket_top__GC0,
-logic__6815: VCU118RocketSystem__GC0,
-logic__6602: RocketTile__GCB0,
-datapath__497: VCU118RocketSystem__GC0,
-datapath__660: tracking_wrapper,
-logic__5278: RocketTile__GCB0,
-logic__2117: RocketTile__GCB0,
-logic__2743: DCache,
-RoundAnyRawFNToRecFN_1: FPU__GB2,
-logic__3573: FPU__GB1,
-logic__2811: DCache,
-reg__364: DCache,
-logic__5867: RocketTile__GCB0,
-logic__6135: RocketTile__GCB0,
-case__265: VCU118RocketSystem__GC0,
-logic__4522: FPU__GB2, FPU__GB1,
-logic__8206: VCU118RocketSystem__GC0,
-datapath__146: VCU118RocketSystem__GC0,
-logic__298: genesys2_rocket_top__GC0,
-datapath__667: tracking_wrapper,
-logic__7735: VCU118RocketSystem__GC0,
-logic__2133: RocketTile__GCB0,
-case__967: RocketTile__GCB0,
-muxpart__30: genesys2_rocket_top__GC0,
-logic__6981: VCU118RocketSystem__GC0,
-case__1730: APBGpsBlock__GC0,
-logic__5280: RocketTile__GCB0,
-extladd__2: tracking_wrapper,
-logic__7176: VCU118RocketSystem__GC0,
-reg__251: VCU118RocketSystem__GC0,
-LF_code: tracking_wrapper,
-datapath__305: RocketTile__GCB0,
-case__456: VCU118RocketSystem__GC0,
-datapath__435: RocketTile__GCB0,
-logic__7699: VCU118RocketSystem__GC0,
-case__922: RocketTile__GCB0,
-case__852: RocketTile__GCB0,
-logic__2191: DCache,
-datapath__194: VCU118RocketSystem__GC0,
-case__513: DCache,
-logic__9501: tracking_wrapper,
-reg__308: VCU118RocketSystem__GC0,
-logic__2153: DCache,
-case__483: VCU118RocketSystem__GC0,
-logic__9016: tracking_wrapper,
-ram_2x77: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__273: VCU118RocketSystem__GC0,
-datapath__520: VCU118RocketSystem__GC0,
-reg__932: VCU118RocketSystem__GC0,
-case__465: VCU118RocketSystem__GC0,
-reg__714: RocketTile__GCB0,
-logic__8141: VCU118RocketSystem__GC0,
-reg__81: genesys2_rocket_top__GC0,
-logic__5559: RocketTile__GCB0,
-logic__9204: tracking_wrapper,
-logic__2474: RocketTile__GCB0, DCache,
-datapath__220: VCU118RocketSystem__GC0,
-datapath__573: APBGpsBlock__GC0,
-logic__2427: DCache,
-reg__876: VCU118RocketSystem__GC0,
-logic__3359: FPU__GB1,
-case__22: genesys2_rocket_top__GC0,
-case__850: RocketTile__GCB0,
-datapath__174: VCU118RocketSystem__GC0,
-IntXbar_i3_o1: RocketTile__GCB0,
-reg__1207: APBGpsBlock__GC0,
-reg__35: genesys2_rocket_top__GC0,
-logic__7097: VCU118RocketSystem__GC0,
-datapath__255: VCU118RocketSystem__GC0,
-case__602: RocketTile__GCB0,
-logic__2871: DCache,
-datapath__69: VCU118RocketSystem__GC0,
-case__1045: VCU118RocketSystem__GC0,
-logic__5981: RocketTile__GCB0,
-logic__4790: FPU__GB2,
-muxpart__225: FPU__GB0,
-logic__6275: RocketTile__GCB0,
-DTLB: DCache,
-logic__5317: RocketTile__GCB0,
-logic__4497: FPU__GB1,
-logic__6648: RocketTile__GCB0,
-datapath__393: FPU__GB2,
-reg__1216: APBGpsBlock__GC0,
-case__1246: VCU118RocketSystem__GC0,
-logic__4917: FPU__GB2,
-logic__2342: DCache,
-logic__5824: RocketTile__GCB0,
-datapath__558: APBGpsBlock__GC0,
-logic__2239: DCache,
-keep__2: genesys2_rocket_top__GC0,
-muxpart__57: genesys2_rocket_top__GC0,
-case__1605: tracking_wrapper,
-reg__1140: APBGpsBlock__GC0,
-case__498: RocketTile__GCB0,
-datapath__128: VCU118RocketSystem__GC0,
-case__677: FPU__GB2,
-logic__6653: RocketTile__GCB0,
-case__332: VCU118RocketSystem__GC0,
-logic__7219: VCU118RocketSystem__GC0,
-reg__431: RocketTile__GCB0,
-logic__4340: FPU__GB1,
-logic__4927: FPU__GB1,
-logic__4501: FPU__GB1,
-reg__830: RocketTile__GCB0,
-case__1366: APBGpsBlock__GC0,
-muxpart__127: genesys2_rocket_top__GC0,
-case__322: VCU118RocketSystem__GC0,
-reg__1277: tracking_wrapper,
-reg__1329: tracking_wrapper,
-logic__9527: APBGpsBlock__GC0,
-logic__1893: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a12d64s2k1z3u: VCU118RocketSystem__GC0,
-reg__980: VCU118RocketSystem__GC0,
-logic__3778: FPU__GB2,
-case__1021: VCU118RocketSystem__GC0,
-case__395: VCU118RocketSystem__GC0,
-logic__9560: APBGpsBlock__GC0,
-muxpart__175: FPU__GB0,
-logic__8092: VCU118RocketSystem__GC0,
-TLToAPB: TLToAPB,
-reg__732: RocketTile__GCB0,
-logic__6016: RocketTile__GCB0,
-logic__4083: FPU__GB2,
-logic__8484: APBGpsBlock__GC0,
-reg__1094: APBGpsBlock__GC0,
-logic__2765: DCache,
-logic__6339: RocketTile__GCB0,
-case__1689: tracking_wrapper,
-logic__6866: VCU118RocketSystem__GC0,
-reg__320: RocketTile__GCB0,
-case__1672: tracking_wrapper,
-case__1169: VCU118RocketSystem__GC0,
-logic__1698: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__8212: VCU118RocketSystem__GC0,
-case__1099: VCU118RocketSystem__GC0,
-datapath__301: RocketTile__GCB0,
-datapath__490: TilePRCIDomain__GC0,
-case__945: RocketTile__GCB0,
-logic__695: genesys2_rocket_top__GC0,
-logic__2789: DCache,
-datapath__688: tracking_wrapper,
-case__1503: APBGpsBlock__GC0,
-logic__6652: RocketTile__GCB0,
-logic__6843: VCU118RocketSystem__GC0,
-logic__4792: FPU__GB2,
-logic__5951: RocketTile__GCB0,
-dsp48e1__10: APBGpsBlock__GC0,
-muxpart__247: RocketTile__GCB0,
-dsp48e1__21: APBGpsBlock__GC0,
-datapath__640: APBGpsBlock__GC0,
-case__803: FPU__GB1,
-logic__8764: APBGpsBlock__GC0,
-logic__1021: VCU118RocketSystem__GC0,
-muxpart__221: FPU__GB0,
-case__1131: VCU118RocketSystem__GC0,
-logic__7278: VCU118RocketSystem__GC0,
-reg__472: FPU__GB0,
-logic__2930: DCache,
-divider_fsm: APBGpsBlock__GC0,
-logic__5845: RocketTile__GCB0,
-logic__1651: VCU118RocketSystem__GC0,
-logic__2052: VCU118RocketSystem__GC0,
-logic__7616: VCU118RocketSystem__GC0,
-reg__937: VCU118RocketSystem__GC0,
-cdc_fifo_gray_src: tracking_wrapper,
-datapath__78: VCU118RocketSystem__GC0,
-muxpart__319: APBGpsBlock__GC0,
-case__829: RocketTile__GCB0,
-case__1729: APBGpsBlock__GC0,
-logic__8341: APBGpsBlock__GC0,
-logic__3920: FPU__GB2,
-reg__335: DCache,
-logic__8959: tracking_wrapper,
-logic__7966: VCU118RocketSystem__GC0,
-logic__4644: FPU__GB2,
-logic__7315: VCU118RocketSystem__GC0,
-reg__829: RocketTile__GCB0,
-logic__7921: VCU118RocketSystem__GC0,
-logic__1101: VCU118RocketSystem__GC0,
-logic__3474: FPU__GB1,
-logic__8898: tracking_wrapper,
-logic__7071: VCU118RocketSystem__GC0,
-logic__2984: RocketTile__GCB0,
-case__1212: VCU118RocketSystem__GC0,
-case__1193: VCU118RocketSystem__GC0,
-case__1150: VCU118RocketSystem__GC0,
-logic__7254: VCU118RocketSystem__GC0,
-logic__3881: FPU__GB2,
-datapath__221: VCU118RocketSystem__GC0,
-logic__3331: FPU__GB1,
-case__1049: VCU118RocketSystem__GC0,
-logic__7343: VCU118RocketSystem__GC0,
-reg__502: FPU__GB1,
-case__645: FPU__GB0,
-logic__2599: DCache,
-logic__310: genesys2_rocket_top__GC0,
-reg__1400: tracking_wrapper,
-logic__3280: RocketTile__GCB0,
-logic__2479: RocketTile__GCB0, DCache,
-datapath__48: VCU118RocketSystem__GC0,
-case__1500: APBGpsBlock__GC0,
-logic__1707: VCU118RocketSystem__GC0,
-logic__6033: RocketTile__GCB0,
-logic__7807: VCU118RocketSystem__GC0,
-logic__3059: RocketTile__GCB0,
-muxpart__45: genesys2_rocket_top__GC0,
-logic__5941: RocketTile__GCB0,
-datapath__488: TilePRCIDomain__GC0,
-logic__907: VCU118RocketSystem__GC0,
-reg__618: FPU__GB1,
-case__1171: VCU118RocketSystem__GC0,
-logic__5844: RocketTile__GCB0,
-logic__3796: FPU__GB2,
-logic__899: VCU118RocketSystem__GC0,
-case__1707: tracking_wrapper,
-logic__5694: RocketTile__GCB0,
-logic__1320: VCU118RocketSystem__GC0,
-logic__3643: FPU__GB2, FPU__GB1,
-case__742: FPU__GB2,
-datapath__21: genesys2_rocket_top__GC0,
-logic__6785: VCU118RocketSystem__GC0,
-case__1235: VCU118RocketSystem__GC0,
-reg__465: FPU__GB0,
-case__35: genesys2_rocket_top__GC0,
-logic__8293: VCU118RocketSystem__GC0,
-reg__104: genesys2_rocket_top__GC0,
-logic__6558: RocketTile__GCB0,
-logic__1734: VCU118RocketSystem__GC0,
-logic__3355: FPU__GB1,
-logic__7180: VCU118RocketSystem__GC0,
-reg__1435: genesys2_rocket_top__GC0,
-logic__8411: APBGpsBlock__GC0,
-logic__6088: RocketTile__GCB0,
-case__1138: VCU118RocketSystem__GC0,
-reg__206: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4481: FPU__GB1,
-logic__787: VCU118RocketSystem__GC0,
-logic__6657: RocketTile__GCB0,
-logic__8581: APBGpsBlock__GC0,
-TLDebugModuleInnerAsync: VCU118RocketSystem__GC0,
-logic__7119: VCU118RocketSystem__GC0,
-datapath__195: VCU118RocketSystem__GC0,
-case__271: VCU118RocketSystem__GC0,
-datapath__106: VCU118RocketSystem__GC0,
-case__805: FPU__GB1,
-logic__2727: DCache,
-logic__5990: RocketTile__GCB0,
-logic__9412: tracking_wrapper,
-reg__264: VCU118RocketSystem__GC0,
-case__368: VCU118RocketSystem__GC0,
-logic__9146: tracking_wrapper,
-datapath__433: RocketTile__GCB0,
-logic__4429: FPU__GB1,
-case__211: genesys2_rocket_top__GC0,
-logic__8892: tracking_wrapper,
-logic__8672: APBGpsBlock__GC0,
-logic__7820: VCU118RocketSystem__GC0,
-datapath__654: tracking_wrapper,
-logic__5825: RocketTile__GCB0,
-reg__297: VCU118RocketSystem__GC0,
-logic__2314: DCache,
-logic__1024: VCU118RocketSystem__GC0,
-ram__4: VCU118RocketSystem__GC0,
-reg__610: FPU__GB2,
-logic__3597: FPU__GB2, FPU__GB1,
-case__285: VCU118RocketSystem__GC0,
-reg__16: genesys2_rocket_top__GC0,
-logic__2224: DCache,
-logic__7134: VCU118RocketSystem__GC0,
-reg__812: RocketTile__GCB0,
-datapath__53: VCU118RocketSystem__GC0,
-logic__7040: VCU118RocketSystem__GC0,
-case__575: RocketTile__GCB0,
-reg__864: TilePRCIDomain__GC0,
-logic__7415: VCU118RocketSystem__GC0,
-reg__240: VCU118RocketSystem__GC0,
-logic__9240: tracking_wrapper,
-logic__4511: FPU__GB2, FPU__GB1,
-logic__4423: FPU__GB1,
-logic__2851: DCache,
-logic__2473: RocketTile__GCB0, DCache,
-case__1067: VCU118RocketSystem__GC0,
-case__560: DCache,
-reg__859: RocketTile__GCB0,
-datapath__7: genesys2_rocket_top__GC0,
-case__1176: VCU118RocketSystem__GC0,
-datapath__642: APBGpsBlock__GC0,
-muxpart__182: FPU__GB0,
-reg__1190: APBGpsBlock__GC0,
-reg__899: VCU118RocketSystem__GC0,
-case__641: RocketTile__GCB0,
-case__668: FPU__GB2,
-logic__6139: RocketTile__GCB0,
-case__262: VCU118RocketSystem__GC0,
-logic__5510: RocketTile__GCB0,
-reg__330: DCache,
-logic__8: genesys2_rocket_top__GC0,
-case__1743: TLToAPB,
-muxpart__251: RocketTile__GCB0,
-logic__623: genesys2_rocket_top__GC0,
-reg__70: genesys2_rocket_top__GC0,
-case__353: VCU118RocketSystem__GC0,
-logic__7260: VCU118RocketSystem__GC0,
-datapath__216: VCU118RocketSystem__GC0,
-case__338: VCU118RocketSystem__GC0,
-logic__4492: FPU__GB1,
-logic__6734: VCU118RocketSystem__GC0,
-case__885: RocketTile__GCB0,
-logic__3971: FPU__GB2,
-logic__3443: FPU__GB1,
-TLWidthWidget1: VCU118RocketSystem__GC0,
-logic__966: VCU118RocketSystem__GC0,
-datapath__592: APBGpsBlock__GC0,
-case__1673: tracking_wrapper,
-case__726: FPU__GB2, FPU__GB1,
-case__34: genesys2_rocket_top__GC0,
-logic__9517: tracking_wrapper,
-case__418: VCU118RocketSystem__GC0,
-logic__2897: DCache,
-logic__5176: RocketTile__GCB0,
-reg__1283: tracking_wrapper,
-case__1378: APBGpsBlock__GC0,
-case__163: genesys2_rocket_top__GC0,
-addsub__2: tracking_wrapper,
-logic__2002: VCU118RocketSystem__GC0,
-case__1022: VCU118RocketSystem__GC0,
-case__956: RocketTile__GCB0,
-logic__5598: RocketTile__GCB0,
-logic__3757: FPU__GB2,
-FPGASPIClockSinkDomain: VCU118RocketSystem__GC0,
-logic__6508: RocketTile__GCB0,
-case__884: RocketTile__GCB0,
-case__985: RocketTile__GCB0,
-logic__8624: APBGpsBlock__GC0,
-logic__6032: RocketTile__GCB0,
-logic__9302: tracking_wrapper,
-logic__2125: RocketTile__GCB0,
-logic__2586: DCache,
-Queue1_TLBundleD_a29d32s7k1z2u: TLToAPB,
-logic__6735: VCU118RocketSystem__GC0,
-logic__5134: FPU__GB1,
-case__1068: VCU118RocketSystem__GC0,
-logic__6673: RocketTile__GCB0,
-case__1013: VCU118RocketSystem__GC0,
-logic__778: VCU118RocketSystem__GC0,
-reg__1197: APBGpsBlock__GC0,
-logic__1292: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6794: VCU118RocketSystem__GC0,
-logic__2095: RocketTile__GCB0,
-datapath__380: FPU__GB2, FPU__GB1,
-logic__6109: RocketTile__GCB0,
-logic__2835: DCache,
-case__1418: APBGpsBlock__GC0,
-case__107: genesys2_rocket_top__GC0,
-datapath__406: FPU__GB2,
-muxpart__235: FPU__GB0,
-logic__4941: FPU__GB1,
-datapath__634: APBGpsBlock__GC0,
-logic__775: VCU118RocketSystem__GC0,
-logic__5841: RocketTile__GCB0,
-keep__12: tracking_wrapper,
-logic__4461: FPU__GB1,
-case__907: RocketTile__GCB0,
-reg__698: RocketTile__GCB0,
-logic__5707: RocketTile__GCB0,
-logic__6143: RocketTile__GCB0,
-logic__887: VCU118RocketSystem__GC0,
-reg__258: VCU118RocketSystem__GC0,
-reg__119: VCU118RocketSystem__GC0,
-datapath__628: APBGpsBlock__GC0,
-logic__4189: FPU__GB1,
-logic__5206: RocketTile__GCB0,
-datapath__74: VCU118RocketSystem__GC0,
-TLWidthWidget8_4: VCU118RocketSystem__GC0,
-logic__7133: VCU118RocketSystem__GC0,
-case__1335: APBGpsBlock__GC0,
-case__1084: VCU118RocketSystem__GC0,
-logic__3646: FPU__GB2, FPU__GB1,
-acq_nco_carr: APBGpsBlock__GC0,
-ScratchpadSlavePort: RocketTile__GCB0,
-logic__3521: FPU__GB1,
-logic__4498: FPU__GB1,
-logic__7495: VCU118RocketSystem__GC0,
-logic__3522: FPU__GB1,
-logic__4682: FPU__GB2,
-logic__4354: FPU__GB1,
-datapath: genesys2_rocket_top__GC0,
-reg__974: VCU118RocketSystem__GC0,
-case__974: RocketTile__GCB0,
-case__906: RocketTile__GCB0,
-case__1166: VCU118RocketSystem__GC0,
-logic__5961: RocketTile__GCB0,
-logic__3750: FPU__GB2,
-logic__3066: RocketTile__GCB0,
-logic__4046: FPU__GB2,
-logic__1921: VCU118RocketSystem__GC0,
-logic__8058: VCU118RocketSystem__GC0,
-reg__759: RocketTile__GCB0,
-logic__6926: VCU118RocketSystem__GC0,
-logic__4156: FPU__GB1,
-case__24: genesys2_rocket_top__GC0,
-logic__4667: FPU__GB2,
-logic__7112: VCU118RocketSystem__GC0,
-logic__2322: DCache,
-logic__2268: DCache,
-logic__4262: FPU__GB1,
-reg__299: VCU118RocketSystem__GC0,
-logic__2347: DCache,
-reg__476: FPU__GB0,
-case__445: VCU118RocketSystem__GC0,
-logic__7894: VCU118RocketSystem__GC0,
-logic__7409: VCU118RocketSystem__GC0,
-case__600: RocketTile__GCB0,
-logic__9153: tracking_wrapper,
-logic__5060: FPU__GB1,
-case__111: genesys2_rocket_top__GC0,
-logic__6839: VCU118RocketSystem__GC0,
-logic__4683: FPU__GB2,
-case__58: genesys2_rocket_top__GC0,
-logic__7802: VCU118RocketSystem__GC0,
-logic__7615: VCU118RocketSystem__GC0,
-reg__808: RocketTile__GCB0,
-case__261: VCU118RocketSystem__GC0,
-logic__3484: FPU__GB1,
-case__620: RocketTile__GCB0,
-reg__176: VCU118RocketSystem__GC0,
-case__193: genesys2_rocket_top__GC0,
-logic__7801: VCU118RocketSystem__GC0,
-reg__50: genesys2_rocket_top__GC0,
-logic__496: genesys2_rocket_top__GC0,
-logic__118: genesys2_rocket_top__GC0,
-reg__521: FPU__GB2,
-case__782: FPU__GB1,
-datapath__85: VCU118RocketSystem__GC0,
-logic__3566: FPU__GB1,
-logic__8513: APBGpsBlock__GC0,
-logic__6073: RocketTile__GCB0,
-logic__1298: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__1044: VCU118RocketSystem__GC0,
-muxpart__186: FPU__GB0,
-logic__2725: DCache,
-logic__113: genesys2_rocket_top__GC0,
-case__1583: tracking_wrapper,
-logic__4355: FPU__GB1,
-case__587: RocketTile__GCB0,
-logic__5637: RocketTile__GCB0,
-logic__7375: VCU118RocketSystem__GC0,
-logic__1796: VCU118RocketSystem__GC0,
-logic__3779: FPU__GB2,
-logic__2542: DCache,
-logic__169: genesys2_rocket_top__GC0,
-logic__5682: RocketTile__GCB0,
-reg__458: FPU__GB0,
-logic__7429: VCU118RocketSystem__GC0,
-logic__3229: RocketTile__GCB0,
-reg__959: VCU118RocketSystem__GC0,
-logic__2501: RocketTile__GCB0, DCache,
-logic__2151: DCache,
-case__396: VCU118RocketSystem__GC0,
-reg__236: VCU118RocketSystem__GC0,
-case__861: RocketTile__GCB0,
-logic__6078: RocketTile__GCB0,
-logic__3708: FPU__GB2,
-datapath__581: APBGpsBlock__GC0,
-datapath__11: genesys2_rocket_top__GC0,
-case__1011: VCU118RocketSystem__GC0,
-TLPLIC: VCU118RocketSystem__GC0,
-logic__6818: VCU118RocketSystem__GC0,
-reg__1302: tracking_wrapper,
-logic__8979: tracking_wrapper,
-logic__4009: FPU__GB2,
-logic__1574: VCU118RocketSystem__GC0,
-case__1570: tracking_wrapper,
-logic__3642: FPU__GB2, FPU__GB1,
-logic__4052: FPU__GB2,
-datapath__214: VCU118RocketSystem__GC0,
-case__692: FPU__GB2,
-muxpart__375: tracking_wrapper,
-extram: genesys2_rocket_top__GC0,
-logic__2981: RocketTile__GCB0,
-logic__3524: FPU__GB1,
-logic__5583: RocketTile__GCB0,
-logic__5950: RocketTile__GCB0,
-muxpart__222: FPU__GB0,
-case__218: genesys2_rocket_top__GC0,
-reg__986: VCU118RocketSystem__GC0,
-reg__1350: tracking_wrapper,
-case__1688: tracking_wrapper,
-datapath__653: tracking_wrapper,
-case__864: RocketTile__GCB0,
-reg__479: FPU__GB0,
-reg__1113: APBGpsBlock__GC0,
-logic__6923: VCU118RocketSystem__GC0,
-datapath__111: VCU118RocketSystem__GC0,
-reg__1311: tracking_wrapper,
-logic__2278: DCache,
-case__567: DCache,
-LF_carr: tracking_wrapper,
-logic__7539: VCU118RocketSystem__GC0,
-reg__941: VCU118RocketSystem__GC0,
-logic__9000: tracking_wrapper,
-logic__8800: APBGpsBlock__GC0,
-logic__1805: VCU118RocketSystem__GC0,
-muxpart: genesys2_rocket_top__GC0,
-logic__5408: RocketTile__GCB0,
-reg__1018: VCU118RocketSystem__GC0,
-logic__5851: RocketTile__GCB0,
-logic__1917: VCU118RocketSystem__GC0,
-logic__6514: RocketTile__GCB0,
-case__1498: APBGpsBlock__GC0,
-logic__2154: DCache,
-case__588: RocketTile__GCB0,
-case__144: genesys2_rocket_top__GC0,
-case__840: RocketTile__GCB0,
-case__157: genesys2_rocket_top__GC0,
-logic__7678: VCU118RocketSystem__GC0,
-logic__4386: FPU__GB1,
-logic__6550: RocketTile__GCB0,
-logic__336: genesys2_rocket_top__GC0,
-case__387: VCU118RocketSystem__GC0,
-logic__4126: FPU__GB2,
-case__1492: APBGpsBlock__GC0,
-reg__860: RocketTile__GCB0,
-case__920: RocketTile__GCB0,
-case__238: VCU118RocketSystem__GC0,
-case__1345: APBGpsBlock__GC0,
-logic__7105: VCU118RocketSystem__GC0,
-logic__6669: RocketTile__GCB0,
-datapath__49: VCU118RocketSystem__GC0,
-case__1737: TLToAPB,
-case__1332: APBGpsBlock__GC0,
-case__1265: APBGpsBlock__GC0,
-reg__80: genesys2_rocket_top__GC0,
-logic__3701: FPU__GB2,
-reg__75: genesys2_rocket_top__GC0,
-reg__769: RocketTile__GCB0,
-logic__8266: VCU118RocketSystem__GC0,
-logic__7062: VCU118RocketSystem__GC0,
-logic__3223: RocketTile__GCB0,
-reg__629: FPU__GB1,
-reg__951: VCU118RocketSystem__GC0,
-logic__3336: FPU__GB1,
-logic__5258: RocketTile__GCB0,
-reg__79: genesys2_rocket_top__GC0,
-case__615: RocketTile__GCB0,
-case__714: FPU__GB1,
-logic__8074: VCU118RocketSystem__GC0,
-logic__7457: VCU118RocketSystem__GC0,
-logic__7344: VCU118RocketSystem__GC0,
-case__1001: VCU118RocketSystem__GC0,
-logic__3353: FPU__GB1,
-logic__2744: DCache,
-logic__4765: FPU__GB2,
-datapath__388: FPU__GB2,
-case__718: FPU__GB1,
-logic__8288: VCU118RocketSystem__GC0,
-logic__4460: FPU__GB1,
-logic__8867: APBGpsBlock__GC0,
-logic__7314: VCU118RocketSystem__GC0,
-case__1613: tracking_wrapper,
-case__749: FPU__GB2,
-datapath__349: FPU__GB2,
-case__416: VCU118RocketSystem__GC0,
-reg__1278: tracking_wrapper,
-reg__777: RocketTile__GCB0,
-TLBuffer_a32d64s2k1z3u_1: TilePRCIDomain__GC0,
-logic__7451: VCU118RocketSystem__GC0,
-logic__9140: tracking_wrapper,
-logic__3694: FPU__GB1,
-reg__487: FPU__GB0,
-logic__4833: FPU__GB2,
-datapath__20: genesys2_rocket_top__GC0,
-case__891: RocketTile__GCB0,
-case__952: RocketTile__GCB0,
-datapath__597: APBGpsBlock__GC0,
-datapath__692: tracking_wrapper,
-logic__2302: DCache,
-logic__4348: FPU__GB1,
-case__1136: VCU118RocketSystem__GC0,
-reg__1298: tracking_wrapper,
-case__326: VCU118RocketSystem__GC0,
-logic__4816: FPU__GB2,
-reg__638: FPU__GB1,
-logic__7125: VCU118RocketSystem__GC0,
-logic__3301: RocketTile__GCB0,
-logic__1675: VCU118RocketSystem__GC0,
-reg__818: RocketTile__GCB0,
-reg__107: genesys2_rocket_top__GC0,
-logic__648: genesys2_rocket_top__GC0,
-case__420: VCU118RocketSystem__GC0,
-logic__5220: RocketTile__GCB0,
-reg__457: FPU__GB0,
-case__796: FPU__GB1,
-logic__5965: RocketTile__GCB0,
-logic__4336: FPU__GB1,
-case__1304: APBGpsBlock__GC0,
-logic__3912: FPU__GB2,
-logic__6312: RocketTile__GCB0,
-logic__3780: FPU__GB2,
-logic__3802: FPU__GB2,
-datapath__563: APBGpsBlock__GC0,
-case__1598: tracking_wrapper,
-logic__8173: VCU118RocketSystem__GC0,
-case__515: DCache,
-case__124: genesys2_rocket_top__GC0,
-datapath__142: VCU118RocketSystem__GC0,
-case__733: FPU__GB2, FPU__GB1,
-logic__7266: VCU118RocketSystem__GC0,
-datapath__77: VCU118RocketSystem__GC0,
-reg__1134: APBGpsBlock__GC0,
-logic__7888: VCU118RocketSystem__GC0,
-logic__7463: VCU118RocketSystem__GC0,
-datapath__208: VCU118RocketSystem__GC0,
-logic__276: genesys2_rocket_top__GC0,
-reg__631: FPU__GB1,
-logic__5465: RocketTile__GCB0,
-logic__7717: VCU118RocketSystem__GC0,
-logic__1412: VCU118RocketSystem__GC0,
-case__962: RocketTile__GCB0,
-logic__8296: VCU118RocketSystem__GC0,
-case__1178: VCU118RocketSystem__GC0,
-logic__6984: VCU118RocketSystem__GC0,
-logic__7747: VCU118RocketSystem__GC0,
-logic__4955: FPU__GB1,
-reg__1312: tracking_wrapper,
-logic__7245: VCU118RocketSystem__GC0,
-case__30: genesys2_rocket_top__GC0,
-reg__1230: tracking_wrapper,
-logic__2207: DCache,
-logic__8277: VCU118RocketSystem__GC0,
-case__1289: APBGpsBlock__GC0,
-logic__4545: FPU__GB2, FPU__GB1,
-datapath__559: APBGpsBlock__GC0,
-logic__6171: RocketTile__GCB0,
-logic__2327: DCache,
-binary_to_gray: tracking_wrapper,
-case__688: FPU__GB2,
-logic__1109: VCU118RocketSystem__GC0,
-datapath__358: FPU__GB2,
-case__1139: VCU118RocketSystem__GC0,
-AsyncValidSync: VCU118RocketSystem__GC0,
-logic__6801: VCU118RocketSystem__GC0,
-logic__5624: RocketTile__GCB0,
-datapath__681: tracking_wrapper,
-logic__3615: FPU__GB2, FPU__GB1,
-logic__6824: VCU118RocketSystem__GC0,
-reg__1219: APBGpsBlock__GC0,
-MulAddRecFNToRaw_preMul_1: FPU__GB1,
-logic__7149: VCU118RocketSystem__GC0,
-dsp48e1__16: APBGpsBlock__GC0,
-logic__1582: VCU118RocketSystem__GC0,
-datapath__362: FPU__GB1,
-logic__8321: APBGpsBlock__GC0,
-datapath__79: VCU118RocketSystem__GC0,
-logic__2999: RocketTile__GCB0,
-case__287: VCU118RocketSystem__GC0,
-reg__927: VCU118RocketSystem__GC0,
-datapath__414: RocketTile__GCB0,
-reg__1184: APBGpsBlock__GC0,
-logic__4411: FPU__GB1,
-case__1152: VCU118RocketSystem__GC0,
-logic__6585: RocketTile__GCB0,
-logic__5257: RocketTile__GCB0,
-datapath__212: VCU118RocketSystem__GC0,
-logic__757: VCU118RocketSystem__GC0,
-logic__2720: DCache,
-case__535: DCache,
-logic__4768: FPU__GB2,
-muxpart__178: FPU__GB0,
-logic__9043: tracking_wrapper,
-logic__5378: RocketTile__GCB0,
-reg__4: genesys2_rocket_top__GC0,
-reg__988: VCU118RocketSystem__GC0,
-reg__287: VCU118RocketSystem__GC0,
-datapath__117: VCU118RocketSystem__GC0,
-reg__120: VCU118RocketSystem__GC0,
-logic__954: VCU118RocketSystem__GC0,
-keep__17: genesys2_rocket_top__GC0,
-case__1057: VCU118RocketSystem__GC0,
-logic__1818: VCU118RocketSystem__GC0,
-datapath__689: tracking_wrapper,
-case__1215: VCU118RocketSystem__GC0,
-logic__5084: FPU__GB0,
-logic__4302: FPU__GB1,
-case__827: RocketTile__GCB0,
-datapath__588: APBGpsBlock__GC0,
-datapath__394: FPU__GB2,
-case__1567: tracking_wrapper,
-reg__531: FPU__GB2,
-reg__695: RocketTile__GCB0,
-logic__886: VCU118RocketSystem__GC0,
-reg__683: RocketTile__GCB0,
-logic__2891: DCache,
-reg__1154: APBGpsBlock__GC0,
-case__1175: VCU118RocketSystem__GC0,
-case__1132: VCU118RocketSystem__GC0,
-reg__160: VCU118RocketSystem__GC0,
-case__423: VCU118RocketSystem__GC0,
-case__364: VCU118RocketSystem__GC0,
-case__934: RocketTile__GCB0,
-logic__7214: VCU118RocketSystem__GC0,
-reg__280: VCU118RocketSystem__GC0,
-Repeater_TLBundleD_a32d64s1k1z4u: VCU118RocketSystem__GC0,
-case__1483: APBGpsBlock__GC0,
-logic__2838: DCache,
-logic__5665: RocketTile__GCB0,
-datapath__264: DCache,
-reg__1031: VCU118RocketSystem__GC0,
-logic__3117: RocketTile__GCB0,
-logic__6018: RocketTile__GCB0,
-logic__2932: DCache,
-logic__6672: RocketTile__GCB0,
-logic__784: VCU118RocketSystem__GC0,
-logic__3347: FPU__GB1,
-datapath__549: APBGpsBlock__GC0,
-logic__4680: FPU__GB2,
-logic__7724: VCU118RocketSystem__GC0,
-datapath__501: VCU118RocketSystem__GC0,
-reg__159: VCU118RocketSystem__GC0,
-logic__7666: VCU118RocketSystem__GC0,
-datapath__88: VCU118RocketSystem__GC0,
-logic__3152: RocketTile__GCB0,
-reg__1170: APBGpsBlock__GC0,
-logic__9557: APBGpsBlock__GC0,
-case__1362: APBGpsBlock__GC0,
-reg__630: FPU__GB1,
-case__486: VCU118RocketSystem__GC0,
-logic__2854: DCache,
-datapath__330: FPU__GB2,
-reg__1413: tracking_wrapper,
-reg__1055: VCU118RocketSystem__GC0,
-logic__4495: FPU__GB1,
-reg__660: FPU__GB1,
-logic__3564: FPU__GB1,
-logic__7188: VCU118RocketSystem__GC0,
-logic__6279: RocketTile__GCB0,
-logic__7383: VCU118RocketSystem__GC0,
-logic__2253: DCache,
-logic__2271: DCache,
-logic__6793: VCU118RocketSystem__GC0,
-logic__4793: FPU__GB2,
-logic__5236: RocketTile__GCB0,
-muxpart__201: FPU__GB0,
-case__1399: APBGpsBlock__GC0,
-logic__1208: VCU118RocketSystem__GC0,
-logic__3511: FPU__GB1,
-reg__847: RocketTile__GCB0,
-case__657: FPU__GB2, FPU__GB1,
-case__863: RocketTile__GCB0,
-logic__5177: RocketTile__GCB0,
-reg__1264: tracking_wrapper,
-logic__8199: VCU118RocketSystem__GC0,
-logic__6864: VCU118RocketSystem__GC0,
-case__999: VCU118RocketSystem__GC0,
-reg__1355: tracking_wrapper,
-logic__3505: FPU__GB1,
-datapath__557: APBGpsBlock__GC0,
-reg__307: VCU118RocketSystem__GC0,
-logic__5163: RocketTile__GCB0,
-reg__10: genesys2_rocket_top__GC0,
-reg__960: VCU118RocketSystem__GC0,
-logic__1800: VCU118RocketSystem__GC0,
-logic__4877: FPU__GB2,
-TLInterconnectCoupler_cbus_to_clint: VCU118RocketSystem__GC0,
-reg__989: VCU118RocketSystem__GC0,
-logic__6752: VCU118RocketSystem__GC0,
-datapath__705: tracking_wrapper,
-datapath__140: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6645: RocketTile__GCB0,
-logic__7736: VCU118RocketSystem__GC0,
-case__237: VCU118RocketSystem__GC0,
-case__534: DCache,
-logic__3031: RocketTile__GCB0,
-logic__2393: DCache,
-reg__1108: APBGpsBlock__GC0,
-logic__1779: VCU118RocketSystem__GC0,
-logic__8944: tracking_wrapper,
-logic__9342: tracking_wrapper,
-logic__6663: RocketTile__GCB0,
-INToRecFN_1: FPU__GB2,
-PLICClockSinkDomain: VCU118RocketSystem__GC0,
-logic__6014: RocketTile__GCB0,
-logic__7927: VCU118RocketSystem__GC0,
-logic__4382: FPU__GB1,
-logic__2272: DCache,
-logic__234: genesys2_rocket_top__GC0,
-logic__917: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__1255: VCU118RocketSystem__GC0,
-logic__1496: VCU118RocketSystem__GC0,
-logic__1351: VCU118RocketSystem__GC0,
-case__744: FPU__GB2,
-logic__3975: FPU__GB2,
-case__979: RocketTile__GCB0,
-reg__1261: tracking_wrapper,
-logic__156: genesys2_rocket_top__GC0,
-case__914: RocketTile__GCB0,
-case__421: VCU118RocketSystem__GC0,
-reg__641: FPU__GB1,
-logic__703: genesys2_rocket_top__GC0,
-case__201: genesys2_rocket_top__GC0,
-reg__257: VCU118RocketSystem__GC0,
-logic__9011: tracking_wrapper,
-logic__526: genesys2_rocket_top__GC0,
-logic__7117: VCU118RocketSystem__GC0,
-reg__372: DCache,
-logic__5552: RocketTile__GCB0,
-logic__1811: VCU118RocketSystem__GC0,
-logic__6659: RocketTile__GCB0,
-Queue2_TLBundleA_a32d64s2k1z3u: TilePRCIDomain__GC0,
-case__1343: APBGpsBlock__GC0,
-datapath__201: VCU118RocketSystem__GC0,
-reg__1064: VCU118RocketSystem__GC0,
-logic__7542: VCU118RocketSystem__GC0,
-logic__6554: RocketTile__GCB0,
-datapath__280: DCache,
-logic__6859: VCU118RocketSystem__GC0,
-signinv: RocketTile__GCB0,
-reg__222: VCU118RocketSystem__GC0,
-logic__2693: DCache,
-reg__1183: APBGpsBlock__GC0,
-logic__1643: VCU118RocketSystem__GC0,
-logic__2972: RocketTile__GCB0,
-logic__9209: tracking_wrapper,
-reg__533: FPU__GB2,
-case__136: genesys2_rocket_top__GC0,
-logic__5953: RocketTile__GCB0,
-dsp48e1__23: APBGpsBlock__GC0,
-logic__3057: RocketTile__GCB0,
-case__1441: APBGpsBlock__GC0,
-muxpart__169: RocketTile__GCB0,
-reg__1180: APBGpsBlock__GC0,
-reg__713: RocketTile__GCB0,
-case__1214: VCU118RocketSystem__GC0,
-logic__7781: VCU118RocketSystem__GC0,
-logic__3037: RocketTile__GCB0,
-datapath__354: FPU__GB2,
-logic__5548: RocketTile__GCB0,
-case__128: genesys2_rocket_top__GC0,
-logic__6927: VCU118RocketSystem__GC0,
-logic__6315: RocketTile__GCB0,
-logic__4634: FPU__GB1,
-case__1629: tracking_wrapper,
-logic__2817: DCache,
-extram__4: APBGpsBlock__GC0,
-reg__269: VCU118RocketSystem__GC0,
-reg__365: DCache,
-muxpart__59: genesys2_rocket_top__GC0,
-logic__5365: RocketTile__GCB0,
-logic__3220: RocketTile__GCB0,
-logic__1635: VCU118RocketSystem__GC0,
-logic__7583: VCU118RocketSystem__GC0,
-datapath__351: FPU__GB2,
-reg__1203: APBGpsBlock__GC0,
-logic__7244: VCU118RocketSystem__GC0,
-logic__8029: VCU118RocketSystem__GC0,
-reg__985: VCU118RocketSystem__GC0,
-reg__234: VCU118RocketSystem__GC0,
-logic__3124: RocketTile__GCB0,
-logic__6072: RocketTile__GCB0,
-reg__357: DCache,
-logic__6115: RocketTile__GCB0,
-logic__7843: VCU118RocketSystem__GC0,
-RVCExpander: RocketTile__GCB0,
-reg__1263: tracking_wrapper,
-logic__7013: VCU118RocketSystem__GC0,
-datapath__199: VCU118RocketSystem__GC0,
-logic__1182: VCU118RocketSystem__GC0,
-logic__2086: RocketTile__GCB0,
-case__1118: VCU118RocketSystem__GC0,
-logic__1205: VCU118RocketSystem__GC0,
-reg__343: DCache,
-reg__931: VCU118RocketSystem__GC0,
-reg__1430: TLToAPB,
-logic__9411: tracking_wrapper,
-logic__5597: RocketTile__GCB0,
-eth_rf_async_fifo: genesys2_rocket_top__GC0,
-logic__3320: FPU__GB1,
-reg__529: FPU__GB2,
-datapath__579: APBGpsBlock__GC0,
-logic__3237: RocketTile__GCB0,
-logic__5695: RocketTile__GCB0,
-logic__2644: DCache,
-reg__1223: tracking_wrapper,
-reg__1326: tracking_wrapper,
-logic__8368: APBGpsBlock__GC0,
-logic__6714: RocketTile__GCB0,
-NonSyncResetSynchronizerPrimitiveShiftReg_d3: TilePRCIDomain__GC0,
-reg__494: FPU__GB1,
-reg__800: RocketTile__GCB0,
-datapath__177: VCU118RocketSystem__GC0,
-logic__4002: FPU__GB2,
-muxpart__49: genesys2_rocket_top__GC0,
-logic__7242: VCU118RocketSystem__GC0,
-datapath__315: FPU__GB1,
-logic__7196: VCU118RocketSystem__GC0,
-logic__590: genesys2_rocket_top__GC0,
-logic__7294: VCU118RocketSystem__GC0,
-reg__42: genesys2_rocket_top__GC0,
-case__393: VCU118RocketSystem__GC0,
-logic__4047: FPU__GB2,
-logic__4387: FPU__GB1,
-datapath__691: tracking_wrapper,
-logic__7673: VCU118RocketSystem__GC0,
-logic__4900: FPU__GB2,
-logic__9313: tracking_wrapper,
-muxpart__234: FPU__GB0,
-logic__5352: RocketTile__GCB0,
-logic__1697: VCU118RocketSystem__GC0,
-DivSqrtRecFNToRaw_small: FPU__GB2,
-logic__4176: FPU__GB1,
-logic__8232: VCU118RocketSystem__GC0,
-logic__6829: VCU118RocketSystem__GC0,
-logic__4120: FPU__GB2,
-logic__3322: FPU__GB1,
-case__1722: tracking_wrapper,
-logic__4151: FPU__GB2,
-logic__3919: FPU__GB2,
-logic__1005: VCU118RocketSystem__GC0,
-datapath__28: genesys2_rocket_top__GC0,
-logic__3574: FPU__GB1,
-reg__1085: VCU118RocketSystem__GC0,
-reg__171: VCU118RocketSystem__GC0,
-case__1609: tracking_wrapper,
-reg__1050: VCU118RocketSystem__GC0,
-reg__778: RocketTile__GCB0,
-reg__653: FPU__GB1,
-logic__7195: VCU118RocketSystem__GC0,
-logic__511: genesys2_rocket_top__GC0,
-logic__7449: VCU118RocketSystem__GC0,
-case__1025: VCU118RocketSystem__GC0,
-logic__3869: FPU__GB2,
-logic__1302: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__145: genesys2_rocket_top__GC0,
-case__1059: VCU118RocketSystem__GC0,
-logic__5476: RocketTile__GCB0,
-logic__5959: RocketTile__GCB0,
-case__1618: tracking_wrapper,
-logic__7166: VCU118RocketSystem__GC0,
-logic__1477: VCU118RocketSystem__GC0,
-reg__1089: APBGpsBlock__GC0, tracking_wrapper,
-case__1576: tracking_wrapper,
-logic__2757: DCache,
-reg__5: genesys2_rocket_top__GC0,
-case__569: DCache,
-datapath__541: VCU118RocketSystem__GC0,
-logic__1676: VCU118RocketSystem__GC0,
-case__510: DCache,
-logic__986: VCU118RocketSystem__GC0,
-logic__6831: VCU118RocketSystem__GC0,
-logic__1427: VCU118RocketSystem__GC0,
-logic__9430: tracking_wrapper,
-logic__2510: RocketTile__GCB0, DCache,
-trck_top: tracking_wrapper,
-logic__1248: VCU118RocketSystem__GC0,
-reg__194: VCU118RocketSystem__GC0,
-reg__173: VCU118RocketSystem__GC0,
-muxpart__248: RocketTile__GCB0,
-reg__930: VCU118RocketSystem__GC0,
-logic__9460: tracking_wrapper,
-case__1739: TLToAPB,
-logic__168: genesys2_rocket_top__GC0,
-reg__499: FPU__GB1,
-logic__281: genesys2_rocket_top__GC0,
-logic__7104: VCU118RocketSystem__GC0,
-reg__887: VCU118RocketSystem__GC0,
-logic__2189: DCache,
-reg__1332: tracking_wrapper,
-logic__2605: DCache,
-logic__7295: VCU118RocketSystem__GC0,
-logic__6980: VCU118RocketSystem__GC0,
-logic__6015: RocketTile__GCB0,
-reg__950: VCU118RocketSystem__GC0,
-logic__2719: DCache,
-logic__1280: VCU118RocketSystem__GC0,
-logic__7434: VCU118RocketSystem__GC0,
-logic__3106: RocketTile__GCB0,
-TLWidthWidget8: VCU118RocketSystem__GC0,
-logic__5589: RocketTile__GCB0,
-case__417: VCU118RocketSystem__GC0,
-datapath__273: DCache,
-logic__4713: FPU__GB2,
-datapath__161: VCU118RocketSystem__GC0,
-reg__410: RocketTile__GCB0,
-case__197: genesys2_rocket_top__GC0,
-datapath__89: VCU118RocketSystem__GC0,
-logic__3801: FPU__GB2,
-case__582: RocketTile__GCB0,
-logic__5103: FPU__GB1,
-logic__8669: APBGpsBlock__GC0,
-logic__2410: DCache,
-logic__669: genesys2_rocket_top__GC0,
-logic__8941: tracking_wrapper,
-case__686: FPU__GB2,
-logic__6311: RocketTile__GCB0,
-case__1111: VCU118RocketSystem__GC0,
-logic__1145: VCU118RocketSystem__GC0,
-reg__1254: tracking_wrapper,
-logic__4467: FPU__GB1,
-datapath__504: VCU118RocketSystem__GC0,
-logic__4113: FPU__GB2,
-logic__5068: FPU__GB1,
-case__225: genesys2_rocket_top__GC0,
-case__766: FPU__GB2,
-logic__270: genesys2_rocket_top__GC0,
-logic__8976: tracking_wrapper,
-reg__350: DCache,
-logic__7253: VCU118RocketSystem__GC0,
-reg__671: RocketTile__GCB0,
-logic__3307: RocketTile__GCB0,
-datapath__572: APBGpsBlock__GC0,
-logic__7234: VCU118RocketSystem__GC0,
-dsp48e1__3: APBGpsBlock__GC0,
-logic__31: genesys2_rocket_top__GC0,
-logic__5199: RocketTile__GCB0,
-datapath__385: FPU__GB1,
-case__540: DCache,
-logic__1031: VCU118RocketSystem__GC0,
-logic__8192: VCU118RocketSystem__GC0,
-case__1135: VCU118RocketSystem__GC0,
-logic__7432: VCU118RocketSystem__GC0,
-logic__7317: VCU118RocketSystem__GC0,
-LevelGateway: VCU118RocketSystem__GC0,
-reg__175: VCU118RocketSystem__GC0,
-logic__5489: RocketTile__GCB0,
-muxpart__71: genesys2_rocket_top__GC0,
-reg__563: FPU__GB1,
-reg__1013: VCU118RocketSystem__GC0,
-reg__999: VCU118RocketSystem__GC0,
-case__639: RocketTile__GCB0,
-reg__1099: APBGpsBlock__GC0,
-case__665: FPU__GB2, FPU__GB1,
-reg__1127: APBGpsBlock__GC0,
-logic__9576: TLToAPB,
-reg__385: RocketTile__GCB0,
-reg__12: genesys2_rocket_top__GC0,
-logic__7021: VCU118RocketSystem__GC0,
-logic__9213: tracking_wrapper,
-datapath__236: VCU118RocketSystem__GC0,
-logic__3947: FPU__GB2,
-case__1423: APBGpsBlock__GC0,
-logic__5954: RocketTile__GCB0,
-case__213: genesys2_rocket_top__GC0,
-logic__7627: VCU118RocketSystem__GC0,
-case__537: DCache,
-logic__1611: VCU118RocketSystem__GC0,
-datapath__96: VCU118RocketSystem__GC0,
-reg__461: FPU__GB0,
-logic__7403: VCU118RocketSystem__GC0,
-logic__3585: FPU__GB1,
-muxpart__26: genesys2_rocket_top__GC0,
-logic__7577: VCU118RocketSystem__GC0,
-logic__4249: FPU__GB1,
-logic__3009: RocketTile__GCB0,
-logic__8031: VCU118RocketSystem__GC0,
-logic__44: genesys2_rocket_top__GC0,
-case__701: FPU__GB2,
-reg__1239: tracking_wrapper,
-logic__3507: FPU__GB1,
-reg__1279: tracking_wrapper,
-case__984: RocketTile__GCB0,
-logic__5357: RocketTile__GCB0,
-logic__3575: FPU__GB1,
-case__1268: APBGpsBlock__GC0,
-logic__3134: RocketTile__GCB0,
-logic__646: genesys2_rocket_top__GC0,
-logic__1523: VCU118RocketSystem__GC0,
-TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u: RocketTile__GCB0,
-case__1300: APBGpsBlock__GC0,
-logic__8091: VCU118RocketSystem__GC0,
-logic__7351: VCU118RocketSystem__GC0,
-reg__904: VCU118RocketSystem__GC0,
-logic__766: VCU118RocketSystem__GC0,
-datapath__137: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__768: FPU__GB2,
-case__1638: tracking_wrapper,
-case__1230: VCU118RocketSystem__GC0,
-logic__8433: APBGpsBlock__GC0,
-logic__9007: tracking_wrapper,
-logic__2869: DCache,
-datapath__267: DCache,
-logic__2182: DCache,
-logic__509: genesys2_rocket_top__GC0,
-case__1248: VCU118RocketSystem__GC0,
-case__1064: VCU118RocketSystem__GC0,
-reg__515: FPU__GB1,
-logic__6822: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_sbus_from_bus_named_fbus: VCU118RocketSystem__GC0,
-logic__7419: VCU118RocketSystem__GC0,
-datapath__655: tracking_wrapper,
-logic__2023: VCU118RocketSystem__GC0,
-reg__600: FPU__GB2,
-logic__5545: RocketTile__GCB0,
-logic__495: genesys2_rocket_top__GC0,
-reg__1125: APBGpsBlock__GC0,
-case__121: genesys2_rocket_top__GC0,
-muxpart__66: genesys2_rocket_top__GC0,
-case__822: RocketTile__GCB0,
-case__484: VCU118RocketSystem__GC0,
-muxpart__171: FPU__GB0,
-logic__730: genesys2_rocket_top__GC0,
-logic__5254: RocketTile__GCB0,
-logic__9055: tracking_wrapper,
-case__589: RocketTile__GCB0,
-case__143: genesys2_rocket_top__GC0,
-logic__4329: FPU__GB1,
-logic__6932: VCU118RocketSystem__GC0,
-case__470: VCU118RocketSystem__GC0,
-logic__1035: VCU118RocketSystem__GC0,
-dsp48e1__1: FPU__GB1,
-datapath__682: tracking_wrapper,
-logic__950: VCU118RocketSystem__GC0,
-case__1647: tracking_wrapper,
-reg__416: RocketTile__GCB0,
-logic__8694: APBGpsBlock__GC0,
-case__1557: tracking_wrapper,
-logic__8180: VCU118RocketSystem__GC0,
-case__794: FPU__GB1,
-logic__5447: RocketTile__GCB0,
-logic__3884: FPU__GB2,
-logic__5135: FPU__GB1,
-logic__7414: VCU118RocketSystem__GC0,
-logic__6777: VCU118RocketSystem__GC0,
-logic__772: VCU118RocketSystem__GC0,
-logic__4388: FPU__GB1,
-logic__5702: RocketTile__GCB0,
-datapath__463: RocketTile__GCB0,
-reg__311: VCU118RocketSystem__GC0,
-logic__4408: FPU__GB1,
-logic__3948: FPU__GB2,
-logic__9413: tracking_wrapper,
-case__1433: APBGpsBlock__GC0,
-logic__4924: FPU__GB1,
-logic__8803: APBGpsBlock__GC0,
-datapath__32: VCU118RocketSystem__GC0,
-FPUFMAPipe_l4_f64: FPU__GB1,
-logic__6832: VCU118RocketSystem__GC0,
-reg__228: VCU118RocketSystem__GC0,
-logic__5203: RocketTile__GCB0,
-reg__799: RocketTile__GCB0,
-logic__5701: RocketTile__GCB0,
-logic__1966: VCU118RocketSystem__GC0,
-logic__2870: DCache,
-logic__952: VCU118RocketSystem__GC0,
-reg__300: VCU118RocketSystem__GC0,
-reg__408: RocketTile__GCB0,
-datapath__405: FPU__GB2,
-logic__8123: VCU118RocketSystem__GC0,
-case__700: FPU__GB2,
-logic__8429: APBGpsBlock__GC0,
-case__443: VCU118RocketSystem__GC0,
-logic__6836: VCU118RocketSystem__GC0,
-Arbiter4_DCacheDataReq: DCache,
-case__1635: tracking_wrapper,
-logic__3718: FPU__GB2,
-datapath__265: DCache,
-case__628: RocketTile__GCB0,
-reg__1301: tracking_wrapper,
-logic__8547: APBGpsBlock__GC0,
-logic__3456: FPU__GB1,
-reg__263: VCU118RocketSystem__GC0,
-reg__241: VCU118RocketSystem__GC0,
-reg__1423: tracking_wrapper,
-reg__551: FPU__GB1,
-logic__2964: RocketTile__GCB0,
-case__1034: VCU118RocketSystem__GC0,
-logic__7057: VCU118RocketSystem__GC0,
-logic__8895: tracking_wrapper,
-keep__18: genesys2_rocket_top__GC0,
-Queue2_TLBundleD_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__878: VCU118RocketSystem__GC0,
-reg__195: VCU118RocketSystem__GC0,
-logic__8790: APBGpsBlock__GC0,
-reg__69: genesys2_rocket_top__GC0,
-logic__1041: VCU118RocketSystem__GC0,
-reg__1285: tracking_wrapper,
-case__1347: APBGpsBlock__GC0,
-logic__3095: RocketTile__GCB0,
-reg__1403: tracking_wrapper,
-logic__7741: VCU118RocketSystem__GC0,
-logic__4676: FPU__GB2,
-reg__1053: VCU118RocketSystem__GC0,
-reg__1029: VCU118RocketSystem__GC0,
-logic__7035: VCU118RocketSystem__GC0,
-reg__1376: tracking_wrapper,
-muxpart__239: FPU__GB2,
-case__1684: tracking_wrapper,
-case__1182: VCU118RocketSystem__GC0,
-logic__2292: DCache,
-TLInterconnectCoupler_pbus_to_fpga_uart: VCU118RocketSystem__GC0,
-logic__2507: RocketTile__GCB0, DCache,
-datapath__646: tracking_wrapper,
-datapath__127: VCU118RocketSystem__GC0,
-reg__727: RocketTile__GCB0,
-logic__2647: DCache,
-logic__4847: FPU__GB2,
-reg__1269: tracking_wrapper,
-logic__4868: FPU__GB2,
-counter: genesys2_rocket_top__GC0,
-reg__790: RocketTile__GCB0,
-case__1579: tracking_wrapper,
-reg__1177: APBGpsBlock__GC0,
-case__1017: VCU118RocketSystem__GC0,
-datapath__223: VCU118RocketSystem__GC0,
-logic__1520: VCU118RocketSystem__GC0,
-logic__6544: RocketTile__GCB0,
-reg__1260: tracking_wrapper,
-case__1659: tracking_wrapper,
-case__340: VCU118RocketSystem__GC0,
-datapath__430: RocketTile__GCB0,
-datapath__626: APBGpsBlock__GC0,
-logic__7438: VCU118RocketSystem__GC0,
-case__594: RocketTile__GCB0,
-logic__5609: RocketTile__GCB0,
-logic__4910: FPU__GB2,
-logic__315: genesys2_rocket_top__GC0,
-reg__975: VCU118RocketSystem__GC0,
-case__1307: APBGpsBlock__GC0,
-logic__7934: VCU118RocketSystem__GC0,
-logic__4857: FPU__GB2,
-case__723: FPU__GB1,
-AsyncResetSynchronizerShiftReg_w1_d3_i0: VCU118RocketSystem__GC0, APBGpsBlock__GC0,
-datapath__139: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__8034: VCU118RocketSystem__GC0,
-logic__7712: VCU118RocketSystem__GC0,
-logic__7246: VCU118RocketSystem__GC0,
-case__669: FPU__GB2,
-logic__5423: RocketTile__GCB0,
-logic__5980: RocketTile__GCB0,
-dsp48e1__4: APBGpsBlock__GC0,
-reg__548: FPU__GB1,
-logic__8781: APBGpsBlock__GC0,
-logic__9328: tracking_wrapper,
-logic__4432: FPU__GB1,
-logic__9317: tracking_wrapper,
-logic__536: genesys2_rocket_top__GC0,
-keep__6: genesys2_rocket_top__GC0,
-logic__7386: VCU118RocketSystem__GC0,
-reg__394: RocketTile__GCB0,
-datapath__54: VCU118RocketSystem__GC0,
-reg__1369: tracking_wrapper,
-muxpart__196: FPU__GB0,
-logic__7582: VCU118RocketSystem__GC0,
-reg__578: FPU__GB1,
-FPUDecoder: FPU__GB1,
-datapath__347: FPU__GB2,
-logic__5329: RocketTile__GCB0,
-logic__5831: RocketTile__GCB0,
-reg__504: FPU__GB1,
-logic__1467: VCU118RocketSystem__GC0,
-case__585: RocketTile__GCB0,
-reg__1339: tracking_wrapper,
-logic__5497: RocketTile__GCB0,
-logic__4858: FPU__GB2,
-logic__7838: VCU118RocketSystem__GC0,
-logic__2844: DCache,
-logic__2289: DCache,
-logic__1663: VCU118RocketSystem__GC0,
-case__1628: tracking_wrapper,
-logic__1297: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__3877: FPU__GB2,
-reg__323: DCache,
-datapath__532: VCU118RocketSystem__GC0,
-reg__270: VCU118RocketSystem__GC0,
-logic__5394: RocketTile__GCB0,
-case__757: FPU__GB2,
-logic__19: genesys2_rocket_top__GC0,
-muxpart__240: FPU__GB2,
-case__898: RocketTile__GCB0,
-logic__2750: DCache,
-case__50: genesys2_rocket_top__GC0,
-logic__800: VCU118RocketSystem__GC0,
-logic__3559: FPU__GB1,
-logic__7377: VCU118RocketSystem__GC0,
-case__442: VCU118RocketSystem__GC0,
-logic__356: genesys2_rocket_top__GC0,
-logic__5957: RocketTile__GCB0,
-muxpart__78: genesys2_rocket_top__GC0,
-logic__4887: FPU__GB2,
-logic__1799: VCU118RocketSystem__GC0,
-reg__668: RocketTile__GCB0,
-reg__647: FPU__GB1,
-case__198: genesys2_rocket_top__GC0,
-logic__5067: FPU__GB1,
-datapath__416: RocketTile__GCB0,
-logic__2452: DCache,
-logic__2188: DCache,
-logic__6294: RocketTile__GCB0,
-reg__879: VCU118RocketSystem__GC0,
-logic__765: VCU118RocketSystem__GC0,
-reg__1208: APBGpsBlock__GC0,
-datapath__6: genesys2_rocket_top__GC0,
-logic__6837: VCU118RocketSystem__GC0,
-reg__1059: VCU118RocketSystem__GC0,
-case__1116: VCU118RocketSystem__GC0,
-datapath__674: tracking_wrapper,
-logic__7118: VCU118RocketSystem__GC0,
-datapath__198: VCU118RocketSystem__GC0,
-logic__4093: FPU__GB2,
-logic__9303: tracking_wrapper,
-logic__8829: APBGpsBlock__GC0,
-reg__1374: tracking_wrapper,
-logic__2773: DCache,
-reg__1265: tracking_wrapper,
-logic__744: genesys2_rocket_top__GC0,
-case__140: genesys2_rocket_top__GC0,
-reg__1212: APBGpsBlock__GC0,
-Queue2_TLBundleA_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-case__1745: TLToAPB,
-logic__3517: FPU__GB1,
-case__981: RocketTile__GCB0,
-reg__798: RocketTile__GCB0,
-case__1146: VCU118RocketSystem__GC0,
-logic__9603: VCU118RocketSystem__GC0,
-muxpart__269: VCU118RocketSystem__GC0,
-case__429: VCU118RocketSystem__GC0,
-case__673: FPU__GB2,
-logic__6337: RocketTile__GCB0,
-logic__7252: VCU118RocketSystem__GC0,
-logic__2350: DCache,
-case__272: VCU118RocketSystem__GC0,
-case__644: FPU__GB0,
-reg__925: VCU118RocketSystem__GC0, APBGpsBlock__GC0,
-logic__1699: VCU118RocketSystem__GC0,
-logic__3460: FPU__GB1,
-logic__2907: DCache,
-logic__6656: RocketTile__GCB0,
-datapath__180: VCU118RocketSystem__GC0,
-logic__3808: FPU__GB2,
-case__359: VCU118RocketSystem__GC0,
-case__1566: tracking_wrapper,
-logic__7279: VCU118RocketSystem__GC0,
-reg__819: RocketTile__GCB0,
-logic__286: genesys2_rocket_top__GC0,
-reg__196: VCU118RocketSystem__GC0,
-logic__5234: RocketTile__GCB0,
-case__758: FPU__GB2,
-logic__9003: tracking_wrapper,
-logic__8179: VCU118RocketSystem__GC0,
-logic__3921: FPU__GB2,
-logic__782: VCU118RocketSystem__GC0,
-case__1538: tracking_wrapper,
-logic__3444: FPU__GB1,
-datapath__522: VCU118RocketSystem__GC0,
-reg__1061: VCU118RocketSystem__GC0,
-case__1092: VCU118RocketSystem__GC0,
-reg__751: RocketTile__GCB0,
-logic__8226: VCU118RocketSystem__GC0,
-logic__7014: VCU118RocketSystem__GC0,
-datapath__173: VCU118RocketSystem__GC0,
-datapath__143: VCU118RocketSystem__GC0,
-ResetCatchAndSync_d3: APBGpsBlock__GC0,
-logic__2888: DCache,
-IntSyncAsyncCrossingSink_n1x1: TilePRCIDomain__GC0,
-logic__940: VCU118RocketSystem__GC0,
-reg__1200: APBGpsBlock__GC0,
-logic__7194: VCU118RocketSystem__GC0,
-case__1589: tracking_wrapper,
-logic__2843: DCache,
-reg__908: VCU118RocketSystem__GC0,
-logic__1268: VCU118RocketSystem__GC0,
-case__1244: VCU118RocketSystem__GC0,
-case__1094: VCU118RocketSystem__GC0,
-datapath__605: APBGpsBlock__GC0,
-case__939: RocketTile__GCB0,
-logic__3483: FPU__GB1,
-datapath__680: tracking_wrapper,
-muxpart__195: FPU__GB0,
-logic__9371: tracking_wrapper,
-logic__9084: tracking_wrapper,
-logic__4874: FPU__GB2,
-logic__151: genesys2_rocket_top__GC0,
-reg__491: FPU__GB1,
-logic__1187: VCU118RocketSystem__GC0,
-extram__9: APBGpsBlock__GC0,
-logic__6134: RocketTile__GCB0,
-case__576: RocketTile__GCB0,
-logic__1530: VCU118RocketSystem__GC0,
-logic__4383: FPU__GB1,
-muxpart__39: genesys2_rocket_top__GC0,
-case__646: FPU__GB1,
-logic__515: genesys2_rocket_top__GC0,
-logic__7420: VCU118RocketSystem__GC0,
-logic__6935: VCU118RocketSystem__GC0,
-logic__4399: FPU__GB1,
-logic__4153: FPU__GB1,
-case__837: RocketTile__GCB0,
-reg__332: DCache,
-case__1690: tracking_wrapper,
-case__1678: tracking_wrapper,
-muxpart__19: genesys2_rocket_top__GC0,
-datapath__461: RocketTile__GCB0,
-logic__9088: tracking_wrapper,
-logic__4707: FPU__GB2,
-logic__7385: VCU118RocketSystem__GC0,
-logic__975: VCU118RocketSystem__GC0,
-logic__5344: RocketTile__GCB0,
-logic__2745: DCache,
-logic__9049: tracking_wrapper,
-case__185: genesys2_rocket_top__GC0,
-case__1199: VCU118RocketSystem__GC0,
-datapath__618: APBGpsBlock__GC0,
-muxpart__81: genesys2_rocket_top__GC0,
-logic__951: VCU118RocketSystem__GC0,
-case__106: genesys2_rocket_top__GC0,
-logic__1745: VCU118RocketSystem__GC0,
-logic__3269: RocketTile__GCB0,
-FPU__GB1: FPU__GB1,
-logic__5427: RocketTile__GCB0,
-logic__3324: FPU__GB1,
-logic__2708: DCache,
-case__1186: VCU118RocketSystem__GC0,
-logic__7819: VCU118RocketSystem__GC0,
-case__923: RocketTile__GCB0,
-logic__287: genesys2_rocket_top__GC0,
-case__1197: VCU118RocketSystem__GC0,
-reg__639: FPU__GB1,
-reg__792: RocketTile__GCB0,
-datapath__58: VCU118RocketSystem__GC0,
-logic__2800: DCache,
-case__1510: APBGpsBlock__GC0,
-logic__9602: TLToAPB,
-logic__9414: tracking_wrapper,
-dsp48e1__45: tracking_wrapper,
-reg__1273: tracking_wrapper,
-extram__3: RocketTile__GCB0,
-case__1424: APBGpsBlock__GC0,
-logic__3304: RocketTile__GCB0,
-reg__305: VCU118RocketSystem__GC0,
-logic__2307: DCache,
-logic__9050: tracking_wrapper,
-logic__4376: FPU__GB1,
-muxpart__9: genesys2_rocket_top__GC0,
-datapath__282: DCache,
-logic__3467: FPU__GB1,
-ClockGroupAggregator_sbus: VCU118RocketSystem__GC0,
-case__877: RocketTile__GCB0,
-logic__4593: FPU__GB2, FPU__GB1,
-reg__59: genesys2_rocket_top__GC0,
-logic__9459: tracking_wrapper,
-case__743: FPU__GB2,
-cordic_angle_lut: tracking_wrapper,
-case__1070: VCU118RocketSystem__GC0,
-datapath__669: tracking_wrapper,
-datapath__138: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__1297: tracking_wrapper,
-logic__5245: RocketTile__GCB0,
-logic__2455: DCache,
-datapath__338: FPU__GB2,
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/e/elab.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/e/elab.rtd
deleted file mode 100644
index 9cc8692..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/e/elab.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1220760385.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1220760385.rtd
deleted file mode 100644
index d80c9d5..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index 2104e02..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1294509424.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1294509424.rtd
deleted file mode 100644
index 12fc26e..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index 923167c..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/136113302.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/136113302.rtd
deleted file mode 100644
index 2148d26..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd
deleted file mode 100644
index fc12098..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1672436263.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1672436263.rtd
deleted file mode 100644
index 3b6edc3..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index 31b951b..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2438764479.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2438764479.rtd
deleted file mode 100644
index ea0c83e..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2438764479.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd
deleted file mode 100644
index 3eec4d5..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2610937407.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2610937407.rtd
deleted file mode 100644
index 5186ceb..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index e78ed36..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2737226844.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2737226844.rtd
deleted file mode 100644
index 747a6cd..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index e01b858..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2962621930.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2962621930.rtd
deleted file mode 100644
index 76be4bf..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index 4d91410..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3482045580.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3482045580.rtd
deleted file mode 100644
index d7093bd..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index 14fd955..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3990655999.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3990655999.rtd
deleted file mode 100644
index b384593..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3990655999.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd
deleted file mode 100644
index 79ad0b4..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/976197094.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/976197094.rtd
deleted file mode 100644
index dc3f05e..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd
deleted file mode 100644
index 376e6e4..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/global_name.straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/global_name.straps.rtd
deleted file mode 100644
index 6011ccb..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/instToEncGenName.map b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/instToEncGenName.map
deleted file mode 100644
index 70b3a2c..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/g/instToEncGenName.map
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0:2438764479
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/genesys2_rocket_top__GC0:3990655999
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/genomeDependencyGraph.out b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/genomeDependencyGraph.out
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/genomes.map b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/genomes.map
deleted file mode 100644
index 0315b46..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/genomes.map
+++ /dev/null
@@ -1,11 +0,0 @@
-FPU__GB0 5DAD0A60
-FPU__GB1 5F9D5100
-FPU__GB2 30286540
-RocketTile__GCB0 70535300
-DCache 319F2560
-TilePRCIDomain__GC0 3467DF00
-tracking_wrapper 3147BB20
-APBGpsBlock__GC0 6072B480
-TLToAPB 7048B120
-VCU118RocketSystem__GC0 4BC09200
-genesys2_rocket_top__GC0 316D2180
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/genomes.txt b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/genomes.txt
deleted file mode 100644
index 52ed2bc..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/genomes.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-FPU__GB0
-FPU__GB1
-FPU__GB2
-RocketTile__GCB0
-DCache
-TilePRCIDomain__GC0
-tracking_wrapper
-APBGpsBlock__GC0
-TLToAPB
-VCU118RocketSystem__GC0
-genesys2_rocket_top__GC0
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/parentModToGenomes.map b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/parentModToGenomes.map
deleted file mode 100644
index 48cd2be..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/parentModToGenomes.map
+++ /dev/null
@@ -1,8 +0,0 @@
-genesys2_rocket_top: FPU__GB1, TLToAPB, tracking_wrapper, genesys2_rocket_top__GC0, RocketTile__GCB0, DCache, FPU__GB0, APBGpsBlock__GC0, FPU__GB2, TilePRCIDomain__GC0, VCU118RocketSystem__GC0,
-VCU118RocketSystem: FPU__GB1, TLToAPB, tracking_wrapper, RocketTile__GCB0, DCache, FPU__GB0, APBGpsBlock__GC0, FPU__GB2, TilePRCIDomain__GC0, VCU118RocketSystem__GC0,
-FPGAGPSClockSinkDomain: TLToAPB, APBGpsBlock__GC0, tracking_wrapper,
-APBGpsBlock: APBGpsBlock__GC0, tracking_wrapper,
-TilePRCIDomain: TilePRCIDomain__GC0, RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-HierarchicalElementResetDomain: RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-RocketTile: RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-FPU: FPU__GB2, FPU__GB1, FPU__GB0,
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/synthNameToElabName.map b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/synthNameToElabName.map
deleted file mode 100644
index 17046f3..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/synthNameToElabName.map
+++ /dev/null
@@ -1,9211 +0,0 @@
-case__792: case__792
-logic__5758: logic__5758
-logic__6934: logic__6934
-logic__8485: logic__8485
-case__683: case__683
-case__1777: case__514
-logic__3335: logic__3335
-case__1540: case__1540
-logic__7309: logic__7309
-case__848: case__848
-muxpart__267: muxpart__267
-logic__8937: logic__8937
-logic__9398: logic__9398
-logic__619: logic__619
-case__414: case__414
-logic__1324: logic__1324
-logic__9639: logic__3599
-logic__9778: logic__2374
-reg__558: reg__558
-Repeater_TLBundleA_a29d32s2k1z3u: Repeater_TLBundleA_a29d32s2k1z3u
-logic__8303: logic__8303
-logic__9150: logic__9150
-logic__9677: logic__4520
-cordic_atan_one_stage__parameterized0: cordic_atan_one_stage__parameterized0
-logic__5474: logic__5474
-case__1497: case__1497
-reg__845: reg__845
-case__958: case__958
-case__1115: case__1115
-logic__5328: logic__5328
-logic__8158: logic__8158
-datapath__31: datapath__31
-case__1395: case__1395
-reg__468: reg__468
-reg__1514: reg__924
-logic__9970: logic__906
-logic__8678: logic__8678
-logic__4464: logic__4464
-logic__5359: logic__5359
-reg__1437: reg__869
-case__437: case__437
-logic__2221: logic__2221
-logic__6157: logic__6157
-logic__5164: logic__5164
-logic__6282: logic__6282
-datapath__209: datapath__209
-reg__576: reg__576
-logic__9638: logic__3610
-logic__9651: logic__4584
-logic__591: logic__591
-reg__227: reg__227
-reg__672: reg__672
-reg__748: reg__748
-reg__1415: reg__1415
-logic__6010: logic__6010
-logic__4405: logic__4405
-logic__5259: logic__5259
-reg__1500: reg__926
-case__1133: case__1133
-reg__1484: reg__925
-logic__510: logic__510
-logic__7206: logic__7206
-logic__9874: logic__911
-datapath__35: datapath__35
-reg__604: reg__604
-logic__8071: logic__8071
-logic__9300: logic__9300
-logic__115: logic__115
-logic__7916: logic__7916
-reg__848: reg__848
-logic__9356: logic__9356
-logic__7074: logic__7074
-logic__943: logic__943
-logic__3518: logic__3518
-logic__1518: logic__1518
-logic__4970: logic__4970
-case__989: case__989
-reg__1410: reg__1410
-datapath__675: datapath__675
-logic__6728: logic__6728
-datapath__200: datapath__200
-reg__1581: reg__926
-case__539: case__539
-logic__7427: logic__7427
-reg__1360: reg__1360
-logic__6150: logic__6150
-reg__462: reg__462
-case__748: case__748
-reg__1084: reg__1084
-reg__82: reg__82
-logic__1695: logic__1695
-reg__344: reg__344
-logic__6050: logic__6050
-cordic_atan_basic__parameterized0: cordic_atan_basic__parameterized0
-datapath__153: datapath__153
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__14: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__348: case__348
-logic__3224: logic__3224
-reg__711: reg__711
-logic__8025: logic__8025
-reg__459: reg__459
-logic__5073: logic__5073
-datapath__215: datapath__215
-DCache: DCache
-logic__4356: logic__4356
-logic__3047: logic__3047
-case__654: case__654
-datapath__293: datapath__293
-reg__1440: reg__122
-logic__9921: logic__6768
-logic__3504: logic__3504
-datapath__92: datapath__92
-reg__1521: reg__926
-logic__3503: logic__3503
-logic__4072: logic__4072
-logic__5945: logic__5945
-AsyncResetSynchronizerShiftReg_w1_d3_i0__3: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__208: logic__208
-logic__9186: logic__9186
-reg__1058: reg__1058
-logic__1886: logic__1886
-reg__207: reg__207
-datapath__637: datapath__637
-case__574: case__574
-case__1530: case__1530
-logic__4905: logic__4905
-logic__2598: logic__2598
-logic__8497: logic__8497
-logic__9085: logic__9085
-logic__5858: logic__5858
-reg__572: reg__572
-ResetCatchAndSync_d3__2: ResetCatchAndSync_d3
-logic__1681: logic__1681
-logic__6129: logic__6129
-case__1725: case__1725
-logic__4395: logic__4395
-logic__900: logic__900
-logic__3435: logic__3435
-logic__6077: logic__6077
-logic__8913: logic__8913
-logic__1952: logic__1952
-logic__3442: logic__3442
-logic__6639: logic__6639
-ram_2x77__3: ram_2x77
-reg__1251: reg__1251
-logic__9332: logic__9332
-logic__4317: logic__4317
-case__1301: case__1301
-logic__978: logic__978
-logic__9369: logic__9369
-sync__7: sync
-logic__1095: logic__1095
-logic__7239: logic__7239
-datapath__57: datapath__57
-logic__947: logic__947
-logic__9600: logic__9600
-case__1603: case__1603
-reg__420: reg__420
-logic__4635: logic__4635
-case__1346: case__1346
-logic__2464: logic__2464
-reg__1445: reg__203
-reg__998: reg__998
-IntToFP: IntToFP
-reg__192: reg__192
-FixedClockBroadcast_4: FixedClockBroadcast_4
-logic__4416: logic__4416
-reg__1588: reg__925
-logic__9113: logic__9113
-logic__2731: logic__2731
-reg__434: reg__434
-logic__4656: logic__4656
-reg__592: reg__592
-logic__197: logic__197
-datapath__764: datapath__121
-case__1597: case__1597
-case__36: case__36
-logic__1330: logic__1330
-reg__581: reg__581
-case__604: case__604
-logic__5920: logic__5920
-logic__9964: logic__917
-case__973: case__973
-reg__1143: reg__1143
-logic__5673: logic__5673
-datapath__611: datapath__611
-reg__527: reg__527
-reg__1077: reg__1077
-datapath__298: datapath__298
-logic__8883: logic__8883
-logic__1381: logic__1381
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__3: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-datapath__178: datapath__178
-case__545: case__545
-datapath__656: datapath__656
-logic__7144: logic__7144
-datapath__458: datapath__458
-logic__9078: logic__9078
-reg__415: reg__415
-reg__1024: reg__1024
-case__1328: case__1328
-reg__259: reg__259
-logic__4217: logic__4217
-case__1795: case__1610
-logic__7282: logic__7282
-case__651: case__651
-case__521: case__521
-logic__3316: logic__3316
-reg__333: reg__333
-logic__7200: logic__7200
-logic__1487: logic__1487
-reg__528: reg__528
-logic__8314: logic__8314
-logic__4737: logic__4737
-logic__6458: logic__6458
-logic__7381: logic__7381
-logic__2262: logic__2262
-logic__4985: logic__4985
-case__1082: case__1082
-logic__1682: logic__1682
-reg__200: reg__200
-acq_peak_srch: acq_peak_srch
-reg__1081: reg__1081
-logic__7412: logic__7412
-muxpart__382: muxpart__382
-reg__550: reg__550
-logic__3496: logic__3496
-case__184: case__184
-logic__6814: logic__6814
-case__1379: case__1379
-case__693: case__693
-logic__1293: logic__1293
-logic__5178: logic__5178
-case__921: case__921
-case__220: case__220
-reg__1379: reg__1379
-case__206: case__206
-reg__1493: reg__1062
-reg__984: reg__984
-logic__8284: logic__8284
-case__153: case__153
-datapath__230: datapath__230
-reg__1248: reg__1248
-counter__5: counter__5
-case__146: case__146
-case__1251: case__1251
-muxpart__212: muxpart__212
-reg__92: reg__92
-logic__2834: logic__2834
-logic__6076: logic__6076
-case__698: case__698
-case__900: case__900
-logic__906: logic__906
-logic__4360: logic__4360
-keep__32: keep__15
-reg__1331: reg__1331
-reg__832: reg__832
-logic__9937: logic__1594
-RecFNToRecFN: RecFNToRecFN
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__22: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-muxpart__161: muxpart__161
-logic__7792: logic__7792
-case__635: case__635
-logic__7202: logic__7202
-case__991: case__991
-case__260: case__260
-logic__9063: logic__9063
-logic__7852: logic__7852
-logic__2822: logic__2822
-logic__3356: logic__3356
-reg__492: reg__492
-case__712: case__712
-logic__7042: logic__7042
-reg__427: reg__427
-datapath__464: datapath__464
-logic__6780: logic__6780
-logic__3323: logic__3323
-logic__6803: logic__6803
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__15: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6830: logic__6830
-logic__7729: logic__7729
-case__1129: case__1129
-reg__361: reg__361
-reg__132: reg__132
-logic__2093: logic__2093
-datapath__278: datapath__278
-logic__7396: logic__7396
-reg__347: reg__347
-case__278: case__278
-logic__9793: logic__2327
-case__1495: case__1495
-datapath__226: datapath__226
-logic__8568: logic__8568
-reg__64: reg__64
-case__4: case__4
-datapath__289: datapath__289
-reg__315: reg__315
-case__328: case__328
-muxpart__301: muxpart__301
-logic__6075: logic__6075
-datapath__202: datapath__202
-reg__1144: reg__1144
-logic__3303: logic__3303
-reg__1490: reg__925
-reg__496: reg__496
-logic__8283: logic__8283
-logic__9905: logic__8884
-reg__1357: reg__1357
-logic__5568: logic__5568
-datapath__537: datapath__537
-datapath__472: datapath__472
-logic__7115: logic__7115
-reg__1204: reg__1204
-logic__3187: logic__3187
-logic__2868: logic__2868
-reg__793: reg__793
-logic__8113: logic__8113
-logic__7179: logic__7179
-case__1155: case__1155
-case__603: case__603
-reg__1034: reg__1034
-logic__6974: logic__6974
-logic__6821: logic__6821
-case__363: case__363
-datapath__99: datapath__99
-reg__884: reg__884
-TLFIFOFixer: TLFIFOFixer
-logic__9648: logic__4593
-reg__1319: reg__1319
-logic__7443: logic__7443
-reg__503: reg__503
-logic__6828: logic__6828
-logic__3: logic__3
-keep__14: keep__14
-logic__4304: logic__4304
-logic__5460: logic__5460
-MulAddRecFNToRaw_preMul: MulAddRecFNToRaw_preMul
-reg__1012: reg__1012
-reg__1166: reg__1166
-logic__4796: logic__4796
-logic__2887: logic__2887
-logic__7277: logic__7277
-case__57: case__57
-datapath__379: datapath__379
-case__1574: case__1574
-logic__9429: logic__9429
-logic__8425: logic__8425
-logic__9015: logic__9015
-reg__198: reg__198
-logic__1998: logic__1998
-logic__925: logic__925
-logic__6525: logic__6525
-case__1112: case__1112
-reg__202: reg__202
-logic__9931: logic__6768
-logic__4827: logic__4827
-case__1295: case__1295
-logic__3998: logic__3998
-logic__2257: logic__2257
-logic__8948: logic__8948
-logic__9907: logic__8882
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__24: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__1100: reg__1100
-datapath__437: datapath__437
-reg__1516: reg__925
-case__489: case__489
-case__797: case__797
-case__966: case__966
-logic__9609: logic__9609
-logic__1550: logic__1550
-muxpart__198: muxpart__198
-logic__9620: logic__3637
-logic__9508: logic__9508
-case__680: case__680
-logic__271: logic__271
-logic__1950: logic__1950
-reg__1549: reg__925
-logic__1030: logic__1030
-logic__3535: logic__3535
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__21: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-TLDebugModuleOuterAsync: TLDebugModuleOuterAsync
-cdc_fifo_gray: cdc_fifo_gray
-case__1477: case__1477
-TLWidthWidget8_1: TLWidthWidget8_1
-logic__131: logic__131
-case__1185: case__1185
-reg__288: reg__288
-ClockGroupAggregator_aggregator: ClockGroupAggregator_aggregator
-logic__6160: logic__6160
-logic__5151: logic__5151
-case__1202: case__1202
-logic__1862: logic__1862
-logic__9798: logic__2310
-reg__1597: reg__874
-case__117: case__117
-datapath__56: datapath__56
-logic__6751: logic__6751
-datapath__516: datapath__516
-logic__8428: logic__8428
-datapath__447: datapath__447
-case__912: case__912
-datapath__432: datapath__432
-datapath__627: datapath__627
-reg__717: reg__717
-reg__1032: reg__1032
-case__1329: case__1329
-logic__4436: logic__4436
-logic__9521: logic__9521
-reg__701: reg__701
-datapath__750: datapath__676
-case__1499: case__1499
-PMPChecker_s3__1: PMPChecker_s3
-logic__599: logic__599
-logic__9345: logic__9345
-reg__720: reg__720
-logic__9528: logic__9528
-RoundAnyRawFNToRecFN_4__1: RoundAnyRawFNToRecFN_4
-reg__213: reg__213
-logic__9383: logic__9383
-logic__5475: logic__5475
-datapath__510: datapath__510
-logic__3833: logic__3833
-case__1660: case__1660
-logic__3953: logic__3953
-logic__2515: logic__2515
-logic__8517: logic__8517
-keep__30: keep__14
-reg__279: reg__279
-logic__3636: logic__3636
-addsub__7: addsub__6
-logic__5316: logic__5316
-reg__1182: reg__1182
-logic__2716: logic__2716
-logic__6614: logic__6614
-logic__6096: logic__6096
-logic__6123: logic__6123
-reg__153: reg__153
-datapath__425: datapath__425
-reg__1133: reg__1133
-reg__749: reg__749
-logic__7421: logic__7421
-logic__5205: logic__5205
-case__751: case__751
-case__1435: case__1435
-logic__4448: logic__4448
-reg__677: reg__677
-logic__2109: logic__2109
-datapath__284: datapath__284
-logic__7258: logic__7258
-reg__98: reg__98
-logic__1806: logic__1806
-logic__7204: logic__7204
-reg__151: reg__151
-reg__396: reg__396
-logic__4391: logic__4391
-case__1724: case__1724
-rockettile_icache_data_arrays_512x32: rockettile_icache_data_arrays_512x32
-logic__7417: logic__7417
-datapath__204: datapath__204
-case__789: case__789
-reg__615: reg__615
-logic__2196: logic__2196
-reg__737: reg__737
-logic__1420: logic__1420
-logic__5332: logic__5332
-case__1224: case__1224
-logic__4866: logic__4866
-logic__2632: logic__2632
-logic__5093: logic__5093
-reg__368: reg__368
-Queue1_TLBundleA_a29d32s7k1z2u: Queue1_TLBundleA_a29d32s7k1z2u
-reg__1560: reg__926
-logic__6847: logic__6847
-logic__1656: logic__1656
-logic__9522: logic__9522
-reg__1402: reg__1402
-case__573: case__573
-case__1153: case__1153
-case__1124: case__1124
-logic__7250: logic__7250
-AsyncResetRegVec_w2_i0: AsyncResetRegVec_w2_i0
-datapath__250: datapath__250
-muxpart__214: muxpart__214
-case__994: case__994
-logic__4923: logic__4923
-muxpart__20: muxpart__20
-reg__336: reg__336
-logic__3358: logic__3358
-logic__7972: logic__7972
-logic__1348: logic__1348
-case__1803: case__308
-logic__4661: logic__4661
-logic__9554: logic__9554
-logic__3887: logic__3887
-logic__3021: logic__3021
-logic__9696: logic__2498
-datapath__391: datapath__391
-logic__700: logic__700
-reg__1318: reg__1318
-logic__6108: logic__6108
-case__942: case__942
-logic__6130: logic__6130
-logic__560: logic__560
-datapath__152: datapath__152
-logic__4638: logic__4638
-logic__1110: logic__1110
-acq_corr: acq_corr
-logic__631: logic__631
-reg__981: reg__981
-datapath__90: datapath__90
-datapath__467: datapath__467
-logic__5962: logic__5962
-logic__2467: logic__2467
-logic__3318: logic__3318
-case__1003: case__1003
-logic__5542: logic__5542
-logic__6863: logic__6863
-logic__3554: logic__3554
-reg__982: reg__982
-reg__1225: reg__1225
-logic__5092: logic__5092
-logic__2873: logic__2873
-logic__2530: logic__2530
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__33: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__5904: logic__5904
-reg__32: reg__32
-logic__5097: logic__5097
-logic__501: logic__501
-logic__1598: logic__1598
-logic__9909: logic__9518
-logic__3234: logic__3234
-logic__1045: logic__1045
-case__1601: case__1601
-case__1208: case__1208
-logic__6286: logic__6286
-logic__1794: logic__1794
-logic__4867: logic__4867
-datapath__275: datapath__275
-logic__877: logic__877
-logic__2818: logic__2818
-logic__8603: logic__8603
-datapath__206: datapath__206
-case__613: case__613
-double_ff_syn__parameterized0: double_ff_syn__parameterized0
-reg__1419: reg__1419
-datapath__320: datapath__320
-logic__1552: logic__1552
-reg__789: reg__789
-case__530: case__530
-logic__5115: logic__5115
-datapath__160: datapath__160
-logic__6023: logic__6023
-logic__1258: logic__1258
-logic__5876: logic__5876
-logic__317: logic__317
-logic__4741: logic__4741
-logic__4703: logic__4703
-TLFragmenter_bootrom: TLFragmenter_bootrom
-mult_46_15_61: mult_46_15_61
-logic__108: logic__108
-logic__1337: logic__1337
-logic__6040: logic__6040
-logic__217: logic__217
-case__771: case__771
-reg__475: reg__475
-logic__2583: logic__2583
-reg__325: reg__325
-reg__614: reg__614
-logic__8493: logic__8493
-datapath__445: datapath__445
-datapath__24: datapath__24
-reg__1162: reg__1162
-logic__5509: logic__5509
-logic__5327: logic__5327
-logic__7384: logic__7384
-AsyncResetSynchronizerShiftReg_w1_d3_i0__10: AsyncResetSynchronizerShiftReg_w1_d3_i0
-reg__1193: reg__1193
-reg__1096: reg__1096
-logic__4820: logic__4820
-reg__1039: reg__1039
-datapath__34: datapath__34
-case__1623: case__1623
-case__411: case__411
-logic__2881: logic__2881
-reg__1008: reg__1008
-rocket_bscan_dmi_tunnel: rocket_bscan_dmi_tunnel
-logic__9654: logic__4577
-logic__3351: logic__3351
-reg__1392: reg__1392
-datapath__574: datapath__574
-case__1716: case__1716
-TLBuffer_a32d64s2k1z4u: TLBuffer_a32d64s2k1z4u
-logic__1962: logic__1962
-case__978: case__978
-logic__7003: logic__7003
-logic__9683: logic__2530
-logic__5382: logic__5382
-case__440: case__440
-logic__4007: logic__4007
-logic__9637: logic__3611
-reg__519: reg__519
-case__1773: case__518
-logic__5481: logic__5481
-logic__7462: logic__7462
-logic__7177: logic__7177
-logic__1266: logic__1266
-reg__936: reg__936
-logic__6053: logic__6053
-datapath__158: datapath__158
-reg__362: reg__362
-datapath__448: datapath__448
-logic__7543: logic__7543
-case__336: case__336
-logic__4435: logic__4435
-reg__304: reg__304
-logic__6833: logic__6833
-logic__1478: logic__1478
-logic__9272: logic__9272
-datapath__604: datapath__604
-reg__1334: reg__1334
-dsp48e1__15: dsp48e1__15
-reg__725: reg__725
-case__740: case__740
-case__614: case__614
-reg__916: reg__916
-datapath__172: datapath__172
-datapath__671: datapath__671
-datapath__1: datapath__1
-logic__9196: logic__9196
-reg__398: reg__398
-logic__3774: logic__3774
-reg__1568: reg__924
-reg__740: reg__740
-logic__7793: logic__7793
-case__1010: case__1010
-ram_2x123: ram_2x123
-datapath__175: datapath__175
-reg__602: reg__602
-logic__2078: logic__2078
-logic__6025: logic__6025
-reg__505: reg__505
-reg__1128: reg__1128
-logic__7404: logic__7404
-logic__1315: logic__1315
-logic__8614: logic__8614
-logic__3343: logic__3343
-muxpart__193: muxpart__193
-reg__545: reg__545
-logic__53: logic__53
-reg__575: reg__575
-reg__1316: reg__1316
-logic__7450: logic__7450
-reg__1035: reg__1035
-logic__3352: logic__3352
-case__1291: case__1291
-bram__parameterized0: bram__parameterized0
-logic__5716: logic__5716
-logic__5038: logic__5038
-datapath__649: datapath__649
-logic__144: logic__144
-reg__861: reg__861
-logic__2538: logic__2538
-datapath__614: datapath__614
-logic__4872: logic__4872
-case__1237: case__1237
-case__354: case__354
-reg__669: reg__669
-logic__5256: logic__5256
-reg__945: reg__945
-case__831: case__831
-logic__699: logic__699
-logic__6638: logic__6638
-logic__796: logic__796
-reg__1491: reg__924
-logic__4704: logic__4704
-logic__8356: logic__8356
-reg__1066: reg__1066
-case__1535: case__1535
-datapath__723: datapath__382
-reg__1304: reg__1304
-logic__320: logic__320
-case__652: case__652
-logic__9944: logic__1150
-logic__3436: logic__3436
-logic__9799: logic__2307
-logic__7452: logic__7452
-reg__523: reg__523
-reg__1573: reg__925
-case__1781: case__510
-logic__3345: logic__3345
-reg__920: reg__920
-logic__5584: logic__5584
-logic__5984: logic__5984
-datapath__696: datapath__696
-case__1339: case__1339
-case__897: case__897
-logic__6541: logic__6541
-logic__3338: logic__3338
-datapath__288: datapath__288
-logic__9571: logic__9571
-logic__6708: logic__6708
-logic__5383: logic__5383
-reg__291: reg__291
-logic__4192: logic__4192
-reg__433: reg__433
-logic__8176: logic__8176
-reg__375: reg__375
-reg__1433: reg__1433
-logic__5017: logic__5017
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__27: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__116: case__116
-logic__1727: logic__1727
-case__1667: case__1667
-logic__3334: logic__3334
-reg__651: reg__651
-logic__7536: logic__7536
-case__347: case__347
-case__303: case__303
-logic__1336: logic__1336
-datapath__598: datapath__598
-logic__9402: logic__9402
-reg__526: reg__526
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__17: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__9567: logic__9567
-reg__750: reg__750
-case__853: case__853
-dsp48e1__27: dsp48e1__27
-IntSyncCrossingSource_n1x1__2: IntSyncCrossingSource_n1x1
-case__253: case__253
-case__1537: case__1537
-datapath__686: datapath__686
-logic__8207: logic__8207
-case__1364: case__1364
-logic__9777: logic__2375
-logic__4584: logic__4584
-logic__7287: logic__7287
-logic__5146: logic__5146
-logic__6610: logic__6610
-logic__7422: logic__7422
-logic__1502: logic__1502
-logic__7286: logic__7286
-case__469: case__469
-logic__4392: logic__4392
-reg__376: reg__376
-logic__1211: logic__1211
-reg__659: reg__659
-logic__3864: logic__3864
-logic__2011: logic__2011
-reg__1538: reg__924
-logic__5514: logic__5514
-datapath__342: datapath__342
-reg__1215: reg__1215
-datapath__397: datapath__397
-case__1093: case__1093
-logic__7700: logic__7700
-logic__7025: logic__7025
-case__1419: case__1419
-logic__6074: logic__6074
-logic__5458: logic__5458
-datapath__219: datapath__219
-logic__9727: logic__2520
-regfile_32x65: regfile_32x65
-logic__7498: logic__7498
-datapath__625: datapath__625
-logic__4445: logic__4445
-reg__857: reg__857
-reg__821: reg__821
-logic__1789: logic__1789
-case__435: case__435
-logic__3987: logic__3987
-datapath__659: datapath__659
-datapath__40: datapath__40
-datapath__115: datapath__115
-logic__2155: logic__2155
-reg__1088: reg__1088
-logic__9786: logic__2350
-logic__561: logic__561
-reg__1001: reg__1001
-ClockGroup: ClockGroup
-logic__3509: logic__3509
-reg__290: reg__290
-case__1085: case__1085
-logic__5016: logic__5016
-TLAtomicAutomata_pbus: TLAtomicAutomata_pbus
-datapath__706: datapath__706
-counter__34: counter__34
-logic__6941: logic__6941
-datapath__768: datapath__44
-logic__4066: logic__4066
-datapath__482: datapath__482
-reg__826: reg__826
-logic__7365: logic__7365
-logic__1127: logic__1127
-logic__8083: logic__8083
-case__249: case__249
-reg__583: reg__583
-reg__277: reg__277
-reg__1098: reg__1098
-logic__3888: logic__3888
-datapath__460: datapath__460
-case__1234: case__1234
-logic__6690: logic__6690
-logic__4078: logic__4078
-reg__694: reg__694
-case__476: case__476
-logic__8662: logic__8662
-dual_port_bram: dual_port_bram
-case__1744: case__1744
-datapath__666: datapath__666
-IBuf: IBuf
-logic__2045: logic__2045
-ClockGroup__3: ClockGroup
-logic__3018: logic__3018
-logic__2374: logic__2374
-sync__6: sync
-case__807: case__807
-reg__617: reg__617
-logic__121: logic__121
-case__1326: case__1326
-logic__3583: logic__3583
-logic__1142: logic__1142
-counter__18: counter__18
-code_loop_discriminator: code_loop_discriminator
-logic__6795: logic__6795
-logic__8953: logic__8953
-logic__9625: logic__3628
-logic__9794: logic__2322
-logic__1525: logic__1525
-RecFNToIN: RecFNToIN
-logic__3202: logic__3202
-logic__1731: logic__1731
-logic__9769: logic__2407
-reg__895: reg__895
-logic__2504: logic__2504
-reg__232: reg__232
-muxpart__226: muxpart__226
-case__957: case__957
-reg__73: reg__73
-logic__8026: logic__8026
-logic__8426: logic__8426
-logic__6295: logic__6295
-reg__652: reg__652
-logic__7143: logic__7143
-logic__3344: logic__3344
-reg__204: reg__204
-case__236: case__236
-muxpart__65: muxpart__65
-logic__8244: logic__8244
-reg__471: reg__471
-logic__880: logic__880
-reg__1065: reg__1065
-logic__9776: logic__2382
-case__1747: case__665
-datapath__713: datapath__713
-logic__4393: logic__4393
-logic__7235: logic__7235
-datapath__66: datapath__66
-case__1798: case__1607
-reg__844: reg__844
-reg__425: reg__425
-logic__6609: logic__6609
-logic__7189: logic__7189
-case__823: case__823
-logic__2008: logic__2008
-datapath__693: datapath__693
-logic__4362: logic__4362
-datapath__663: datapath__663
-logic__3756: logic__3756
-muxpart__6: muxpart__6
-logic__8972: logic__8972
-logic__2872: logic__2872
-addsub__1: addsub__1
-case__1397: case__1397
-logic__8473: logic__8473
-muxpart__149: muxpart__149
-logic__253: logic__253
-reg__302: reg__302
-case__1213: case__1213
-reg__324: reg__324
-logic__9270: logic__9270
-logic__8891: logic__8891
-logic__6590: logic__6590
-reg__795: reg__795
-case__892: case__892
-datapath__355: datapath__355
-logic__5061: logic__5061
-logic__7039: logic__7039
-case__1198: case__1198
-logic__5473: logic__5473
-case__1640: case__1640
-logic__8190: logic__8190
-case__1076: case__1076
-logic__1151: logic__1151
-logic__3100: logic__3100
-logic__4462: logic__4462
-logic__3891: logic__3891
-datapath__192: datapath__192
-case__317: case__317
-logic__5491: logic__5491
-logic__618: logic__618
-case__129: case__129
-case__1035: case__1035
-ifft_abs_sqr: ifft_abs_sqr
-case__719: case__719
-AsyncValidSync__15: AsyncValidSync
-logic__5925: logic__5925
-logic__9861: logic__2163
-logic__5993: logic__5993
-logic__1308: logic__1308
-case__1788: case__1617
-logic__243: logic__243
-reg__1368: reg__1368
-logic__183: logic__183
-datapath__603: datapath__603
-dsp48e1__2: dsp48e1__2
-reg__493: reg__493
-ClockCrossingReg_w55: ClockCrossingReg_w55
-logic__7598: logic__7598
-reg__535: reg__535
-reg__824: reg__824
-muxpart__261: muxpart__261
-logic__7357: logic__7357
-logic__9720: logic__2542
-logic__1521: logic__1521
-logic__5937: logic__5937
-logic__3463: logic__3463
-logic__4409: logic__4409
-muxpart__33: muxpart__33
-logic__1819: logic__1819
-logic__1426: logic__1426
-logic__8674: logic__8674
-logic__8107: logic__8107
-logic__9717: logic__2549
-logic__7690: logic__7690
-logic__7366: logic__7366
-case__294: case__294
-logic__8963: logic__8963
-case__1151: case__1151
-reg__403: reg__403
-reg__1503: reg__926
-logic__6946: logic__6946
-reg__93: reg__93
-logic__4916: logic__4916
-logic__7267: logic__7267
-reg__1387: reg__1387
-datapath__747: datapath__134
-reg__690: reg__690
-reg__87: reg__87
-datapath__499: datapath__499
-logic__1569: logic__1569
-case__296: case__296
-datapath__390: datapath__390
-case__366: case__366
-reg__712: reg__712
-case__1421: case__1421
-datapath__323: datapath__323
-Queue2_TLBundleA_a32d64s1k1z4u__1: Queue2_TLBundleA_a32d64s1k1z4u
-datapath__471: datapath__471
-logic__6022: logic__6022
-reg__953: reg__953
-logic__1359: logic__1359
-logic__3473: logic__3473
-logic__1924: logic__1924
-logic__9910: logic__9518
-case__1381: case__1381
-datapath__684: datapath__684
-keep__4: keep__4
-case__1114: case__1114
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__13: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-datapath__527: datapath__527
-case__1637: case__1637
-logic__1696: logic__1696
-datapath__331: datapath__331
-case__1188: case__1188
-logic__9934: logic__1600
-logic__4815: logic__4815
-dsp48e1__18: dsp48e1__18
-TLInterconnectCoupler_sbus_from_rockettile: TLInterconnectCoupler_sbus_from_rockettile
-logic__9200: logic__9200
-logic__2684: logic__2684
-logic__9386: logic__9386
-logic__9428: logic__9428
-logic__5992: logic__5992
-muxpart__152: muxpart__152
-logic__7742: logic__7742
-case__846: case__846
-reg__1006: reg__1006
-reg__1531: reg__925
-case__376: case__376
-reg__1407: reg__1407
-logic__9641: logic__3597
-reg__850: reg__850
-logic__2178: logic__2178
-logic__4410: logic__4410
-reg__274: reg__274
-case__8: case__8
-logic__7243: logic__7243
-TLInterconnectCoupler_cbus_to_rockettile: TLInterconnectCoupler_cbus_to_rockettile
-case__1394: case__1394
-datapath__474: datapath__474
-reg__1438: reg__124
-logic__4424: logic__4424
-logic__5703: logic__5703
-logic__6530: logic__6530
-counter__33: counter__33
-logic__3983: logic__3983
-case__1691: case__1691
-reg__387: reg__387
-reg__1147: reg__1147
-logic__5705: logic__5705
-logic__9354: logic__9354
-logic__86: logic__86
-datapath__193: datapath__193
-muxpart__70: muxpart__70
-case__883: case__883
-logic__1191: logic__1191
-logic__7844: logic__7844
-case__1157: case__1157
-logic__7588: logic__7588
-logic__5939: logic__5939
-reg__1266: reg__1266
-CLINTClockSinkDomain: CLINTClockSinkDomain
-Repeater_TLBundleA_a28d64s2k1z3u: Repeater_TLBundleA_a28d64s2k1z3u
-logic__6606: logic__6606
-logic__4426: logic__4426
-case__704: case__704
-case__1785: case__1620
-case__1163: case__1163
-logic__9440: logic__9440
-dsp48e1__40: dsp48e1__40
-logic__6924: logic__6924
-reg__360: reg__360
-logic__6729: logic__6729
-logic__8699: logic__8699
-case__1183: case__1183
-case__1754: case__657
-case__518: case__518
-logic__1265: logic__1265
-BreakpointUnit: BreakpointUnit
-case__689: case__689
-logic__5706: logic__5706
-logic__5909: logic__5909
-TLBuffer_a32d64s1k1z4u__1: TLBuffer_a32d64s1k1z4u
-logic__9652: logic__4583
-logic__9943: logic__1151
-logic__2968: logic__2968
-logic__7269: logic__7269
-logic__7066: logic__7066
-logic__3631: logic__3631
-logic__9026: logic__9026
-logic__5789: logic__5789
-case__1396: case__1396
-logic__3926: logic__3926
-logic__4980: logic__4980
-PLICFanIn: PLICFanIn
-logic__9298: logic__9298
-logic__9081: logic__9081
-dsp48e1__37: dsp48e1__37
-reg__319: reg__319
-reg__598: reg__598
-logic__8265: logic__8265
-logic__1166: logic__1166
-case__6: case__6
-logic__8302: logic__8302
-logic__1647: logic__1647
-case__1768: case__523
-reg__866: reg__866
-double_ff_syn: double_ff_syn
-logic__5793: logic__5793
-datapath__266: datapath__266
-logic__2199: logic__2199
-logic__6287: logic__6287
-RoundAnyRawFNToRecFN_2: RoundAnyRawFNToRecFN_2
-reg__1361: reg__1361
-logic__293: logic__293
-case__1526: case__1526
-logic__4873: logic__4873
-case__473: case__473
-logic__4412: logic__4412
-logic__5386: logic__5386
-logic__3812: logic__3812
-logic__5571: logic__5571
-logic__6017: logic__6017
-case__774: case__774
-logic__3341: logic__3341
-reg__1119: reg__1119
-logic__5244: logic__5244
-reg__1530: reg__926
-logic__5446: logic__5446
-case__1267: case__1267
-datapath__664: datapath__664
-reg__691: reg__691
-logic__5385: logic__5385
-logic__5657: logic__5657
-case__1586: case__1586
-case__492: case__492
-reg__117: reg__117
-logic__6176: logic__6176
-reg__1289: reg__1289
-logic__9077: logic__9077
-logic__1590: logic__1590
-logic__9614: logic__3653
-muxpart__191: muxpart__191
-logic__5942: logic__5942
-logic__4062: logic__4062
-reg__296: reg__296
-logic__2060: logic__2060
-logic__1233: logic__1233
-logic__9608: logic__9608
-case__960: case__960
-case__990: case__990
-logic__1666: logic__1666
-reg__825: reg__825
-case__788: case__788
-logic__3349: logic__3349
-reg__19: reg__19
-logic__1149: logic__1149
-reg__1340: reg__1340
-logic__6124: logic__6124
-logic__9820: logic__2254
-logic__4463: logic__4463
-reg__30: reg__30
-reg__1082: reg__1082
-logic__8863: logic__8863
-case__1030: case__1030
-case__624: case__624
-logic__7290: logic__7290
-datapath__51: datapath__51
-logic__56: logic__56
-case__1016: case__1016
-reg__758: reg__758
-logic__3135: logic__3135
-logic__3620: logic__3620
-datapath__155: datapath__155
-logic__3257: logic__3257
-case__684: case__684
-case__1648: case__1648
-logic__8138: logic__8138
-logic__7979: logic__7979
-logic__3755: logic__3755
-datapath__257: datapath__257
-logic__3915: logic__3915
-reg__742: reg__742
-reg__611: reg__611
-logic__124: logic__124
-datapath__310: datapath__310
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__4: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__726: reg__726
-reg__1309: reg__1309
-reg__1201: reg__1201
-case__720: case__720
-reg__1464: reg__1229
-logic__6035: logic__6035
-logic__7193: logic__7193
-logic__4700: logic__4700
-datapath__14: datapath__14
-logic__3430: logic__3430
-reg__407: reg__407
-case__901: case__901
-case__1738: case__1738
-case__1649: case__1649
-logic__4038: logic__4038
-logic__8869: logic__8869
-logic__4439: logic__4439
-extram__5: extram__5
-reg__1378: reg__1378
-logic__7597: logic__7597
-muxpart__238: muxpart__238
-logic__2672: logic__2672
-TLFragmenter_CLINT: TLFragmenter_CLINT
-case__629: case__629
-Queue2_TLBundleD_a32d8s1k1z4u: Queue2_TLBundleD_a32d8s1k1z4u
-datapath__116: datapath__116
-logic__9446: logic__9446
-logic__2556: logic__2556
-logic__5483: logic__5483
-logic__8050: logic__8050
-logic__1522: logic__1522
-reg__715: reg__715
-logic__9748: logic__2473
-logic__2825: logic__2825
-case__857: case__857
-logic__8901: logic__8901
-muxpart__29: muxpart__29
-logic__6619: logic__6619
-case__2: case__2
-logic__795: logic__795
-keep__40: keep__16
-logic__9749: logic__2470
-datapath__383: datapath__383
-datapath__387: datapath__387
-datapath__725: datapath__380
-logic__2943: logic__2943
-reg__1518: reg__926
-reg__872: reg__872
-datapath__442: datapath__442
-logic__5930: logic__5930
-datapath__239: datapath__239
-butterfly__parameterized1: butterfly__parameterized1
-logic__5599: logic__5599
-case__909: case__909
-datapath__352: datapath__352
-reg__190: reg__190
-case__1134: case__1134
-logic__7431: logic__7431
-case__379: case__379
-logic__3516: logic__3516
-case__764: case__764
-logic__3107: logic__3107
-logic__3448: logic__3448
-logic__5618: logic__5618
-logic__4050: logic__4050
-logic__4380: logic__4380
-logic__1850: logic__1850
-reg__142: reg__142
-case__1666: case__1666
-addsub__4: addsub__4
-logic__8567: logic__8567
-logic__2687: logic__2687
-reg__94: reg__94
-case__438: case__438
-case__355: case__355
-datapath__75: datapath__75
-datapath__519: datapath__519
-logic__8816: logic__8816
-logic__3617: logic__3617
-logic__1946: logic__1946
-reg__1171: reg__1171
-reg__570: reg__570
-logic__4310: logic__4310
-logic__1393: logic__1393
-case__334: case__334
-case__1783: case__1622
-logic__5384: logic__5384
-logic__4862: logic__4862
-logic__875: logic__875
-logic__4117: logic__4117
-logic__9062: logic__9062
-logic__1715: logic__1715
-keep__31: keep__16
-case__1071: case__1071
-datapath__159: datapath__159
-reg__419: reg__419
-muxpart__47: muxpart__47
-datapath__62: datapath__62
-VCU118RocketSystem__GC0: VCU118RocketSystem__GC0
-case__1473: case__1473
-logic__2415: logic__2415
-logic__149: logic__149
-muxpart__262: muxpart__262
-reg__239: reg__239
-logic__5033: logic__5033
-case__971: case__971
-keep__35: keep__15
-logic__3979: logic__3979
-reg__393: reg__393
-reg__273: reg__273
-reg__753: reg__753
-logic__6719: logic__6719
-logic__4708: logic__4708
-case__1229: case__1229
-datapath__384: datapath__384
-case__760: case__760
-datapath__456: datapath__456
-logic__649: logic__649
-logic__641: logic__641
-logic__1783: logic__1783
-datapath__135: datapath__135
-case__1808: case__303
-reg__791: reg__791
-datapath__724: datapath__381
-reg__757: reg__757
-case__1305: case__1305
-case__1650: case__1650
-reg__574: reg__574
-case__787: case__787
-case__1337: case__1337
-case__972: case__972
-case__1184: case__1184
-logic__9441: logic__9441
-logic__2489: logic__2489
-IntSyncCrossingSource_n1x2: IntSyncCrossingSource_n1x2
-reg__402: reg__402
-logic__9795: logic__2315
-case__1: case__1
-logic__5861: logic__5861
-datapath__277: datapath__277
-case__697: case__697
-case__949: case__949
-logic__1: logic__1
-case__410: case__410
-logic__2522: logic__2522
-logic__7609: logic__7609
-case__1474: case__1474
-logic__9872: logic__916
-reg__265: reg__265
-logic__5340: logic__5340
-case__1194: case__1194
-logic__4397: logic__4397
-logic__7877: logic__7877
-reg__716: reg__716
-logic__9382: logic__9382
-logic__8038: logic__8038
-logic__7005: logic__7005
-datapath__328: datapath__328
-case__1179: case__1179
-AsyncResetSynchronizerShiftReg_w1_d3_i0__1: AsyncResetSynchronizerShiftReg_w1_d3_i0
-datapath__676: datapath__676
-case__1062: case__1062
-logic__4929: logic__4929
-reg__90: reg__90
-logic__4977: logic__4977
-logic__2861: logic__2861
-logic__6838: logic__6838
-logic__794: logic__794
-extrom__5: extrom
-logic__7053: logic__7053
-reg__225: reg__225
-logic__8960: logic__8960
-logic__233: logic__233
-reg__1575: reg__926
-cdc_fifo_gray_dst: cdc_fifo_gray_dst
-reg__814: reg__814
-reg__223: reg__223
-logic__1973: logic__1973
-logic__2063: logic__2063
-reg__881: reg__881
-logic__6627: logic__6627
-reg__621: reg__621
-logic__5032: logic__5032
-reg__205: reg__205
-logic__1125: logic__1125
-logic__2315: logic__2315
-datapath__609: datapath__609
-logic__3885: logic__3885
-case__1287: case__1287
-case__876: case__876
-case__493: case__493
-logic__3599: logic__3599
-reg__217: reg__217
-logic__2894: logic__2894
-logic__7991: logic__7991
-reg__152: reg__152
-logic__4384: logic__4384
-case__1681: case__1681
-case__205: case__205
-reg__180: reg__180
-datapath__63: datapath__63
-reg__1602: reg__159
-logic__7864: logic__7864
-logic__9624: logic__3631
-Repeater_TLBundleA_a29d64s2k1z3u__1: Repeater_TLBundleA_a29d64s2k1z3u
-logic__1079: logic__1079
-reg__467: reg__467
-TLBusBypass: TLBusBypass
-logic__3635: logic__3635
-reg__568: reg__568
-logic__1303: logic__1303
-logic__3978: logic__3978
-case__832: case__832
-reg__1451: reg__1337
-muxpart__174: muxpart__174
-datapath__704: datapath__704
-case__1750: case__661
-reg__1229: reg__1229
-logic__6511: logic__6511
-RoundAnyRawFNToRecFN_3: RoundAnyRawFNToRecFN_3
-logic__2746: logic__2746
-case__1802: case__309
-logic__2898: logic__2898
-logic__399: logic__399
-case__1247: case__1247
-reg__438: reg__438
-extrom: extrom
-logic__9957: logic__1121
-Queue2_TLBundleD_a29d64s2k1z3u: Queue2_TLBundleD_a29d64s2k1z3u
-logic__9858: logic__2170
-logic__639: logic__639
-logic__5125: logic__5125
-logic__7826: logic__7826
-logic__5798: logic__5798
-logic__5028: logic__5028
-logic__7552: logic__7552
-case__346: case__346
-case__1260: case__1260
-reg__1450: reg__1338
-case__219: case__219
-case__951: case__951
-reg__1370: reg__1370
-reg__68: reg__68
-case__1219: case__1219
-logic__7909: logic__7909
-case__1018: case__1018
-logic__1355: logic__1355
-logic__9627: logic__3624
-FPToFP: FPToFP
-case__617: case__617
-muxpart__35: muxpart__35
-logic__9796: logic__2314
-logic__7933: logic__7933
-logic__1405: logic__1405
-bram: bram
-muxpart__150: muxpart__150
-logic__7058: logic__7058
-logic__972: logic__972
-logic__2781: logic__2781
-reg__322: reg__322
-case__1627: case__1627
-mult_30_25_55: mult_30_25_55
-logic__7564: logic__7564
-logic__1833: logic__1833
-logic__5320: logic__5320
-logic__7368: logic__7368
-case__844: case__844
-logic__6840: logic__6840
-logic__8516: logic__8516
-reg__390: reg__390
-reg__1617: reg__120
-reg__165: reg__165
-reg__1472: reg__1088
-reg__663: reg__663
-reg__637: reg__637
-reg__224: reg__224
-logic__5931: logic__5931
-logic__2671: logic__2671
-logic__8696: logic__8696
-Repeater_TLBundleA_a29d64s2k1z3u_2: Repeater_TLBundleA_a29d64s2k1z3u_2
-logic__5593: logic__5593
-muxpart__243: muxpart__243
-logic__1468: logic__1468
-case__1075: case__1075
-reg__1486: reg__1089
-logic__5142: logic__5142
-logic__1906: logic__1906
-datapath__710: datapath__710
-logic__4375: logic__4375
-case__191: case__191
-logic__7299: logic__7299
-case__367: case__367
-datapath__687: datapath__687
-logic__8090: logic__8090
-reg__888: reg__888
-case__391: case__391
-case__770: case__770
-logic__2367: logic__2367
-reg__977: reg__977
-logic__9216: logic__9216
-datapath__529: datapath__529
-logic__9314: logic__9314
-reg__571: reg__571
-logic__9719: logic__2547
-ram_2x77__1: ram_2x77
-reg__1103: reg__1103
-sync__5: sync
-logic__2225: logic__2225
-logic__1588: logic__1588
-logic__1481: logic__1481
-logic__7000: logic__7000
-logic__9611: logic__3676
-logic__9935: logic__1599
-case__672: case__672
-logic__1517: logic__1517
-case__291: case__291
-case__618: case__618
-reg__102: reg__102
-logic__1235: logic__1235
-logic__5263: logic__5263
-logic__9274: logic__9274
-case__1568: case__1568
-logic__7401: logic__7401
-logic__4385: logic__4385
-logic__3904: logic__3904
-muxpart__402: muxpart__162
-logic__8610: logic__8610
-datapath__577: datapath__577
-logic__6956: logic__6956
-logic__1841: logic__1841
-logic__9462: logic__9462
-logic__1451: logic__1451
-logic__4459: logic__4459
-datapath__732: datapath__267
-reg__721: reg__721
-logic__1787: logic__1787
-logic__4480: logic__4480
-logic__2664: logic__2664
-logic__3712: logic__3712
-reg__1130: reg__1130
-logic__2937: logic__2937
-reg__1570: reg__925
-reg__675: reg__675
-datapath__708: datapath__708
-logic__9147: logic__9147
-muxpart__197: muxpart__197
-reg__1359: reg__1359
-case__554: case__554
-logic__7178: logic__7178
-logic__4257: logic__4257
-case__433: case__433
-logic__9817: logic__2261
-logic__4378: logic__4378
-case__1069: case__1069
-case__1804: case__307
-datapath__639: datapath__639
-logic__5341: logic__5341
-reg__636: reg__636
-logic__7649: logic__7649
-logic__1752: logic__1752
-datapath__68: datapath__68
-reg__1526: reg__924
-logic__6970: logic__6970
-logic__5129: logic__5129
-reg__429: reg__429
-logic__9751: logic__2464
-rom__8: rom__8
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__1: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__8666: logic__8666
-logic__9919: logic__6768
-reg__391: reg__391
-reg__1590: reg__874
-case__1563: case__1563
-logic__9676: logic__4521
-logic__5373: logic__5373
-logic__9711: logic__2565
-reg__1294: reg__1294
-reg__1564: reg__925
-logic__1870: logic__1870
-logic__5625: logic__5625
-logic__3054: logic__3054
-logic__9747: logic__2474
-case__52: case__52
-case__798: case__798
-logic__3705: logic__3705
-logic__2495: logic__2495
-logic__8016: logic__8016
-case__384: case__384
-case__810: case__810
-logic__2355: logic__2355
-reg__907: reg__907
-comp_mult: comp_mult
-logic__6646: logic__6646
-reg__1537: reg__925
-logic__4367: logic__4367
-TLFragmenter_Debug: TLFragmenter_Debug
-datapath__370: datapath__370
-logic__4921: logic__4921
-logic__6352: logic__6352
-logic__1960: logic__1960
-logic__9938: logic__1593
-logic__4390: logic__4390
-case__1621: case__1621
-case__964: case__964
-logic__7883: logic__7883
-logic__7458: logic__7458
-datapath__552: datapath__552
-logic__5308: logic__5308
-logic__4914: logic__4914
-datapath__147: datapath__147
-datapath__141: datapath__141
-logic__9742: logic__2483
-logic__4333: logic__4333
-logic__946: logic__946
-logic__4470: logic__4470
-case__940: case__940
-logic__7889: logic__7889
-case__1372: case__1372
-logic__3520: logic__3520
-datapath__514: datapath__514
-logic__1983: logic__1983
-reg__1609: reg__152
-logic__4216: logic__4216
-logic__7769: logic__7769
-logic__2557: logic__2557
-reg__460: reg__460
-TLXbar_cbus_out_i1_o7_a32d64s2k1z4u: TLXbar_cbus_out_i1_o7_a32d64s2k1z4u
-logic__3172: logic__3172
-logic__6054: logic__6054
-case__1066: case__1066
-logic__1117: logic__1117
-case__29: case__29
-logic__788: logic__788
-logic__5621: logic__5621
-reg__51: reg__51
-reg__140: reg__140
-logic__7825: logic__7825
-case__1633: case__1633
-datapath__12: datapath__12
-logic__7367: logic__7367
-case__730: case__730
-logic__2726: logic__2726
-logic__3251: logic__3251
-logic__2585: logic__2585
-logic__9912: logic__8199
-reg__1427: reg__1427
-reg__585: reg__585
-muxpart__164: muxpart__164
-case__1711: case__1711
-logic__7024: logic__7024
-datapath__647: datapath__647
-reg__1382: reg__1382
-reg__1547: reg__924
-case__676: case__676
-logic__8775: logic__8775
-case__533: case__533
-reg__1567: reg__925
-case__745: case__745
-logic__363: logic__363
-reg__966: reg__966
-logic__9930: logic__6773
-logic__5928: logic__5928
-logic__3062: logic__3062
-logic__670: logic__670
-case__777: case__777
-logic__7922: logic__7922
-logic__3818: logic__3818
-logic__147: logic__147
-logic__6773: logic__6773
-logic__3861: logic__3861
-case__444: case__444
-case__517: case__517
-plusarg_reader: plusarg_reader
-muxpart__73: muxpart__73
-case__1612: case__1612
-logic__5847: logic__5847
-logic__9401: logic__9401
-reg__289: reg__289
-case__413: case__413
-reg__1425: reg__1425
-logic__6110: logic__6110
-logic__4212: logic__4212
-reg__969: reg__969
-logic__9948: logic__1142
-logic__5381: logic__5381
-logic__4587: logic__4587
-logic__5902: logic__5902
-case__460: case__460
-case__778: case__778
-logic__60: logic__60
-reg__1043: reg__1043
-logic__9205: logic__9205
-logic__556: logic__556
-case__910: case__910
-case__913: case__913
-case__1177: case__1177
-reg__729: reg__729
-case__59: case__59
-muxpart__228: muxpart__228
-logic__6113: logic__6113
-logic__4590: logic__4590
-logic__9866: logic__2154
-reg__1107: reg__1107
-datapath__568: datapath__568
-logic__1385: logic__1385
-logic__9564: logic__9564
-logic__5468: logic__5468
-logic__2395: logic__2395
-reg__935: reg__935
-case__1569: case__1569
-logic__546: logic__546
-datapath__486: datapath__486
-reg__138: reg__138
-datapath__489: datapath__489
-reg__174: reg__174
-case__762: case__762
-datapath__502: datapath__502
-TLWidthWidget8_1__2: TLWidthWidget8_1
-datapath__700: datapath__700
-logic__7387: logic__7387
-logic__1167: logic__1167
-case__1664: case__1664
-datapath__531: datapath__531
-datapath__515: datapath__515
-logic__2036: logic__2036
-logic__8017: logic__8017
-muxpart__229: muxpart__229
-logic__6996: logic__6996
-logic__6661: logic__6661
-case__19: case__19
-reg__1396: reg__1396
-logic__304: logic__304
-logic__2483: logic__2483
-reg__1049: reg__1049
-TLWidthWidget8_2: TLWidthWidget8_2
-case__13: case__13
-case__1591: case__1591
-case__780: case__780
-logic__7203: logic__7203
-dsp48e1__8: dsp48e1__8
-datapath__673: datapath__673
-logic__9806: logic__2288
-case__866: case__866
-TLXbar_dmixbar_i1_o2_a9d32s1k1z2u: TLXbar_dmixbar_i1_o2_a9d32s1k1z2u
-logic__6745: logic__6745
-logic__1121: logic__1121
-logic__9672: logic__4545
-logic__3582: logic__3582
-reg__1346: reg__1346
-logic__7672: logic__7672
-logic__1839: logic__1839
-reg__1477: reg__926
-case__1776: case__515
-logic__8365: logic__8365
-reg__1512: reg__926
-reg__718: reg__718
-case__1708: case__1708
-logic__9524: logic__9524
-logic__5922: logic__5922
-logic__9686: logic__2520
-reg__210: reg__210
-reg__620: reg__620
-reg__469: reg__469
-reg__775: reg__775
-case__865: case__865
-reg__894: reg__894
-datapath__422: datapath__422
-case__1686: case__1686
-keep__10: keep__10
-reg__231: reg__231
-logic__3576: logic__3576
-datapath__386: datapath__386
-dsp48e1__41: dsp48e1__41
-logic__719: logic__719
-reg__1574: reg__924
-logic__9779: logic__2373
-case__943: case__943
-eth_rf_core: eth_rf_core
-logic__7041: logic__7041
-logic__6125: logic__6125
-logic__5704: logic__5704
-case__593: case__593
-reg__436: reg__436
-case__1809: case__302
-logic__9744: logic__2479
-logic__9034: logic__9034
-reg__738: reg__738
-muxpart__380: muxpart__380
-muxpart__368: muxpart__368
-logic__5507: logic__5507
-datapath__290: datapath__290
-datapath__311: datapath__311
-logic__9923: logic__6768
-logic__2749: logic__2749
-logic__2566: logic__2566
-logic__392: logic__392
-case__1187: case__1187
-logic__9678: logic__4514
-logic__7604: logic__7604
-datapath__132: datapath__132
-logic__6501: logic__6501
-logic__5486: logic__5486
-reg__67: reg__67
-logic__7430: logic__7430
-gray_to_binary__1: gray_to_binary
-logic__2683: logic__2683
-case__710: case__710
-logic__2498: logic__2498
-TLInterconnectCoupler_cbus_to_debug: TLInterconnectCoupler_cbus_to_debug
-case__371: case__371
-reg__27: reg__27
-reg__377: reg__377
-NCO_carr: NCO_carr
-case__561: case__561
-logic__7446: logic__7446
-reg__49: reg__49
-logic__5267: logic__5267
-PMAChecker: PMAChecker
-datapath__120: datapath__120
-logic__845: logic__845
-case__1740: case__1740
-reg__1132: reg__1132
-case__826: case__826
-case__660: case__660
-muxpart__179: muxpart__179
-logic__6750: logic__6750
-datapath__279: datapath__279
-logic__4116: logic__4116
-reg__565: reg__565
-logic__7967: logic__7967
-datapath__465: datapath__465
-logic__5482: logic__5482
-logic__9526: logic__9526
-logic__4556: logic__4556
-case__487: case__487
-logic__4769: logic__4769
-logic__9741: logic__2486
-logic__373: logic__373
-logic__1660: logic__1660
-logic__5550: logic__5550
-counter__4: counter__4
-reg__498: reg__498
-case__1161: case__1161
-reg__1367: reg__1367
-logic__3558: logic__3558
-case__1778: case__513
-logic__6333: logic__6333
-logic__7610: logic__7610
-muxpart__25: muxpart__25
-logic__881: logic__881
-logic__3427: logic__3427
-datapath__677: datapath__677
-logic__5915: logic__5915
-logic__9863: logic__2159
-logic__1648: logic__1648
-logic__1459: logic__1459
-case__1144: case__1144
-logic__3038: logic__3038
-logic__1200: logic__1200
-logic__2560: logic__2560
-logic__7032: logic__7032
-logic__4305: logic__4305
-logic__6868: logic__6868
-logic__4396: logic__4396
-reg__1255: reg__1255
-datapath__606: datapath__606
-reg__399: reg__399
-logic__8184: logic__8184
-logic__5850: logic__5850
-logic__4909: logic__4909
-logic__2565: logic__2565
-logic__7087: logic__7087
-muxpart__36: muxpart__36
-reg__627: reg__627
-logic__6042: logic__6042
-reg__209: reg__209
-counter__35: counter__29
-logic__8048: logic__8048
-logic__5434: logic__5434
-reg__1411: reg__1411
-logic__4936: logic__4936
-reg__1076: reg__1076
-logic__7454: logic__7454
-case__953: case__953
-case__1296: case__1296
-case__552: case__552
-case__1555: case__1555
-logic__5366: logic__5366
-logic__9745: logic__2476
-logic__1161: logic__1161
-logic__1871: logic__1871
-reg__787: reg__787
-reg__852: reg__852
-logic__1942: logic__1942
-muxpart__236: muxpart__236
-logic__6633: logic__6633
-reg__14: reg__14
-case__836: case__836
-logic__7679: logic__7679
-logic__4913: logic__4913
-datapath__712: datapath__712
-case__1227: case__1227
-datapath__182: datapath__182
-logic__2762: logic__2762
-logic__2812: logic__2812
-case__568: case__568
-logic__985: logic__985
-logic__1262: logic__1262
-case__120: case__120
-logic__9743: logic__2480
-logic__5079: logic__5079
-rockettile_dcache_data_arrays_0_131072x64: rockettile_dcache_data_arrays_0_131072x64
-logic__8013: logic__8013
-logic__1662: logic__1662
-logic__1600: logic__1600
-datapath__431: datapath__431
-datapath__722: datapath__383
-logic__494: logic__494
-muxpart__217: muxpart__217
-logic__5448: logic__5448
-logic__3437: logic__3437
-IntSyncSyncCrossingSink_n1x1: IntSyncSyncCrossingSink_n1x1
-reg__1020: reg__1020
-logic__7756: logic__7756
-logic__1880: logic__1880
-logic__9736: logic__2501
-logic__7705: logic__7705
-logic__1388: logic__1388
-logic__8202: logic__8202
-reg__1196: reg__1196
-case__636: case__636
-logic__9864: logic__2156
-gray_to_binary: gray_to_binary
-reg__868: reg__868
-logic__513: logic__513
-logic__1599: logic__1599
-logic__9966: logic__915
-logic__1261: logic__1261
-logic__5744: logic__5744
-logic__1283: logic__1283
-logic__2621: logic__2621
-logic__4853: logic__4853
-case__1544: case__1544
-logic__5696: logic__5696
-logic__1177: logic__1177
-logic__2139: logic__2139
-reg__482: reg__482
-logic__7762: logic__7762
-logic__4381: logic__4381
-logic__229: logic__229
-case__295: case__295
-case__189: case__189
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__2: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__4801: logic__4801
-reg__948: reg__948
-datapath__249: datapath__249
-logic__5255: logic__5255
-datapath__382: datapath__382
-case__793: case__793
-DivSqrtRawFN_small: DivSqrtRawFN_small
-logic__8027: logic__8027
-reg__849: reg__849
-logic__4040: logic__4040
-logic__7435: logic__7435
-logic__1077: logic__1077
-logic__753: logic__753
-logic__3360: logic__3360
-logic__3673: logic__3673
-TLAsyncCrossingSink_a9d32s1k1z2u: TLAsyncCrossingSink_a9d32s1k1z2u
-logic__6278: logic__6278
-ram_2x77__4: ram_2x77
-logic__9670: logic__4552
-logic__2941: logic__2941
-reg__1253: reg__1253
-logic__3653: logic__3653
-logic__3188: logic__3188
-logic__8823: logic__8823
-reg__1576: reg__925
-logic__1961: logic__1961
-FPToInt: FPToInt
-logic__1748: logic__1748
-logic__9737: logic__2498
-case__1103: case__1103
-logic__1223: logic__1223
-case__961: case__961
-logic__7132: logic__7132
-logic__1551: logic__1551
-logic__3502: logic__3502
-logic__5963: logic__5963
-logic__7220: logic__7220
-reg__1535: reg__924
-case__1292: case__1292
-logic__3125: logic__3125
-logic__7285: logic__7285
-datapath__18: datapath__18
-logic__9843: logic__2203
-datapath__327: datapath__327
-case__147: case__147
-muxpart__53: muxpart__53
-logic__7197: logic__7197
-logic__1790: logic__1790
-logic__1589: logic__1589
-logic__4188: logic__4188
-logic__7276: logic__7276
-logic__1853: logic__1853
-muxpart__260: muxpart__260
-logic__9826: logic__2242
-datapath__720: datapath__321
-case__893: case__893
-logic__4035: logic__4035
-case__1501: case__1501
-keep__52: keep__11
-reg__1343: reg__1343
-case__1790: case__1615
-keep__11: keep__11
-reg__88: reg__88
-case__1128: case__1128
-case__775: case__775
-reg__256: reg__256
-case__516: case__516
-logic__8032: logic__8032
-reg__1123: reg__1123
-case__392: case__392
-datapath__496: datapath__496
-logic__1657: logic__1657
-case__344: case__344
-logic__2852: logic__2852
-case__1584: case__1584
-ram_2x123__1: ram_2x123
-logic__5377: logic__5377
-logic__2631: logic__2631
-logic__606: logic__606
-logic__1846: logic__1846
-logic__1575: logic__1575
-datapath__714: datapath__714
-reg__199: reg__199
-logic__4551: logic__4551
-reg__267: reg__267
-logic__5661: logic__5661
-reg__177: reg__177
-case__394: case__394
-datapath__571: datapath__571
-logic__6059: logic__6059
-logic__920: logic__920
-datapath__444: datapath__444
-logic__7978: logic__7978
-case__1527: case__1527
-logic__9439: logic__9439
-reg__741: reg__741
-muxpart__131: muxpart__131
-case__439: case__439
-case__320: case__320
-datapath__562: datapath__562
-reg__144: reg__144
-reg__395: reg__395
-logic__7318: logic__7318
-reg__1090: reg__1090
-logic__9586: logic__9586
-logic__4400: logic__4400
-logic__2313: logic__2313
-datapath__130: datapath__130
-datapath__317: datapath__317
-logic__5556: logic__5556
-logic__9577: logic__9577
-logic__4734: logic__4734
-reg__1236: reg__1236
-reg__865: reg__865
-logic__5059: logic__5059
-case__1392: case__1392
-case__728: case__728
-logic__9815: logic__2263
-logic__1619: logic__1619
-reg__994: reg__994
-reg__1579: reg__925
-reg__314: reg__314
-logic__3811: logic__3811
-datapath__410: datapath__410
-case__286: case__286
-case__275: case__275
-TLFpgaUART: TLFpgaUART
-case__555: case__555
-dsp48e1__39: dsp48e1__39
-datapath__591: datapath__591
-logic__4233: logic__4233
-datapath__276: datapath__276
-muxpart__75: muxpart__75
-logic__7395: logic__7395
-logic__6905: logic__6905
-reg__1073: reg__1073
-logic__1584: logic__1584
-logic__3610: logic__3610
-logic__8166: logic__8166
-reg__130: reg__130
-logic__2992: logic__2992
-muxpart__67: muxpart__67
-logic__4576: logic__4576
-logic__2670: logic__2670
-logic__9201: logic__9201
-logic__8108: logic__8108
-logic__5392: logic__5392
-dsp48e1__26: dsp48e1__26
-case__234: case__234
-muxpart__211: muxpart__211
-logic__6834: logic__6834
-logic__9400: logic__9400
-ram_2x78__1: ram_2x78
-datapath__607: datapath__607
-keep__28: keep__16
-logic__3111: logic__3111
-SystemBus: SystemBus
-reg__587: reg__587
-logic__6865: logic__6865
-logic__873: logic__873
-logic__2753: logic__2753
-case__1606: case__1606
-logic__9738: logic__2495
-logic__4640: logic__4640
-datapath__455: datapath__455
-reg__421: reg__421
-reg__1080: reg__1080
-logic__3551: logic__3551
-reg__783: reg__783
-logic__9163: logic__9163
-datapath__718: datapath__323
-logic__714: logic__714
-logic__9438: logic__9438
-muxpart__129: muxpart__129
-logic__142: logic__142
-datapath__758: datapath__668
-logic__5553: logic__5553
-reg__221: reg__221
-datapath__749: datapath__677
-case__316: case__316
-logic__9870: logic__2148
-logic__878: logic__878
-logic__3428: logic__3428
-logic__6758: logic__6758
-datapath__565: datapath__565
-logic__1404: logic__1404
-datapath__318: datapath__318
-logic__9942: logic__1152
-logic__6889: logic__6889
-case__138: case__138
-dsp48e1__20: dsp48e1__20
-PTW: PTW
-logic__5978: logic__5978
-case__305: case__305
-logic__1070: logic__1070
-logic__5525: logic__5525
-logic__6540: logic__6540
-logic__5219: logic__5219
-logic__8884: logic__8884
-datapath__652: datapath__652
-reg__84: reg__84
-dual_port_bram__parameterized1: dual_port_bram__parameterized1
-logic__9107: logic__9107
-muxpart__242: muxpart__242
-case__739: case__739
-logic__6051: logic__6051
-case__427: case__427
-reg__803: reg__803
-logic__8275: logic__8275
-logic__960: logic__960
-reg__1524: reg__926
-case__1039: case__1039
-logic__5411: logic__5411
-logic__9584: logic__9584
-reg__1164: reg__1164
-logic__4928: logic__4928
-datapath__602: datapath__602
-case__1204: case__1204
-ram__3: ram__3
-logic__8878: logic__8878
-logic__4777: logic__4777
-logic__8191: logic__8191
-AsyncValidSync__1: AsyncValidSync
-reg__1358: reg__1358
-logic__7298: logic__7298
-logic__4722: logic__4722
-reg__724: reg__724
-logic__712: logic__712
-case__1006: case__1006
-logic__2729: logic__2729
-logic__1493: logic__1493
-logic__8215: logic__8215
-logic__4687: logic__4687
-logic__964: logic__964
-case__496: case__496
-logic__269: logic__269
-logic__7654: logic__7654
-logic__9693: logic__2507
-logic__2963: logic__2963
-reg__397: reg__397
-logic__3506: logic__3506
-logic__6724: logic__6724
-logic__9714: logic__2556
-case__113: case__113
-logic__8868: logic__8868
-reg__1330: reg__1330
-datapath__774: datapath__38
-muxpart__165: muxpart__165
-case__666: case__666
-reg__689: reg__689
-logic__9718: logic__2548
-datapath__168: datapath__168
-case__1531: case__1531
-logic__4263: logic__4263
-datapath__643: datapath__643
-reg__216: reg__216
-reg__1322: reg__1322
-datapath__436: datapath__436
-logic__1446: logic__1446
-logic__642: logic__642
-reg__1510: reg__925
-case__1142: case__1142
-logic__9569: logic__9569
-reg__1042: reg__1042
-case__1104: case__1104
-logic__7293: logic__7293
-muxpart__18: muxpart__18
-datapath__408: datapath__408
-reg__149: reg__149
-logic__9959: logic__1117
-datapath__751: datapath__675
-case__1371: case__1371
-muxpart__168: muxpart__168
-logic__9344: logic__9344
-extram__6: extram__6
-datapath__179: datapath__179
-case__1787: case__1618
-reg__539: reg__539
-logic__13: logic__13
-reg__1063: reg__1063
-logic__9358: logic__9358
-reg__1593: reg__874
-logic__1604: logic__1604
-datapath__39: datapath__39
-case__501: case__501
-logic__8355: logic__8355
-muxpart__194: muxpart__194
-datapath__505: datapath__505
-datapath__133: datapath__133
-case__1061: case__1061
-ClockSinkDomain: ClockSinkDomain
-logic__4950: logic__4950
-case__235: case__235
-reg__1501: reg__925
-case__670: case__670
-reg__1480: reg__926
-AMOALU: AMOALU
-ClockGroupAggregator_pbus__1: ClockGroupAggregator_pbus
-datapath__736: datapath__263
-logic__2635: logic__2635
-reg__1424: reg__1424
-reg__564: reg__564
-case__1780: case__511
-datapath__52: datapath__52
-reg__337: reg__337
-reg__46: reg__46
-logic__8238: logic__8238
-case__839: case__839
-reg__356: reg__356
-logic__5023: logic__5023
-logic__6969: logic__6969
-case__290: case__290
-reg__851: reg__851
-case__1154: case__1154
-logic__1869: logic__1869
-logic__9512: logic__9512
-logic__9750: logic__2467
-case__1036: case__1036
-logic__6776: logic__6776
-reg__1324: reg__1324
-case__1262: case__1262
-logic__3256: logic__3256
-logic__2335: logic__2335
-logic__8762: logic__8762
-reg__63: reg__63
-logic__7173: logic__7173
-logic__2061: logic__2061
-datapath__71: datapath__71
-datapath__651: datapath__651
-logic__4178: logic__4178
-reg__137: reg__137
-logic__9664: logic__4558
-datapath__439: datapath__439
-logic__4300: logic__4300
-reg__700: reg__700
-keep__46: keep__11
-logic__4466: logic__4466
-datapath__131: datapath__131
-case__1732: case__1732
-reg__72: reg__72
-logic__1653: logic__1653
-logic__2548: logic__2548
-reg__579: reg__579
-logic__4281: logic__4281
-case__402: case__402
-logic__9730: logic__2517
-reg__441: reg__441
-logic__6651: logic__6651
-logic__9699: logic__2489
-logic__8419: logic__8419
-logic__8200: logic__8200
-reg__905: reg__905
-logic__1955: logic__1955
-logic__9927: logic__6768
-logic__1669: logic__1669
-logic__9578: logic__9578
-case__1559: case__1559
-logic__4982: logic__4982
-case__551: case__551
-ram_2x10: ram_2x10
-reg__882: reg__882
-case__512: case__512
-logic__4962: logic__4962
-datapath__306: datapath__306
-logic__6642: logic__6642
-logic__9395: logic__9395
-reg__1461: reg__1229
-logic__9316: logic__9316
-case__1140: case__1140
-reg__359: reg__359
-case__240: case__240
-datapath__443: datapath__443
-case__130: case__130
-logic__1483: logic__1483
-datapath__731: datapath__268
-logic__4474: logic__4474
-logic__1384: logic__1384
-datapath__616: datapath__616
-case__497: case__497
-logic__3260: logic__3260
-reg__696: reg__696
-logic__1460: logic__1460
-logic__6856: logic__6856
-datapath__227: datapath__227
-case__1050: case__1050
-logic__9217: logic__9217
-logic__2310: logic__2310
-case__598: case__598
-logic__8039: logic__8039
-logic__1034: logic__1034
-logic__7303: logic__7303
-case__1228: case__1228
-datapath__398: datapath__398
-reg__693: reg__693
-reg__1456: reg__1229
-case__1130: case__1130
-reg__805: reg__805
-logic__1594: logic__1594
-logic__3215: logic__3215
-logic__4981: logic__4981
-logic__1232: logic__1232
-logic__4248: logic__4248
-logic__3637: logic__3637
-reg__657: reg__657
-logic__7153: logic__7153
-muxpart__192: muxpart__192
-case__558: case__558
-case__16: case__16
-keep__34: keep__16
-reg__1030: reg__1030
-logic__3033: logic__3033
-case__155: case__155
-logic__2600: logic__2600
-logic__537: logic__537
-logic__5379: logic__5379
-Queue1_RegMapperInput_i23_m8: Queue1_RegMapperInput_i23_m8
-datapath__717: datapath__324
-logic__8763: logic__8763
-logic__4558: logic__4558
-datapath__546: datapath__546
-case__1054: case__1054
-logic__1865: logic__1865
-logic__5208: logic__5208
-logic__5686: logic__5686
-case__372: case__372
-dsp48e1__6: dsp48e1__6
-reg__470: reg__470
-case__230: case__230
-logic__3931: logic__3931
-reg__506: reg__506
-case__522: case__522
-logic__6662: logic__6662
-logic__1894: logic__1894
-reg__166: reg__166
-logic__8760: logic__8760
-reg__99: reg__99
-muxpart__159: muxpart__159
-case__722: case__722
-logic__722: logic__722
-logic__7853: logic__7853
-logic__321: logic__321
-case__1097: case__1097
-logic__713: logic__713
-logic__6949: logic__6949
-logic__9688: logic__2518
-reg__382: reg__382
-case__1098: case__1098
-logic__4258: logic__4258
-reg__562: reg__562
-AsyncResetRegVec_w1_i0__1: AsyncResetRegVec_w1_i0
-logic__4184: logic__4184
-reg__802: reg__802
-logic__987: logic__987
-logic__4899: logic__4899
-reg__1362: reg__1362
-logic__1987: logic__1987
-logic__1711: logic__1711
-logic__9596: logic__9596
-case__1782: case__509
-logic__2995: logic__2995
-case__1203: case__1203
-logic__3598: logic__3598
-case__406: case__406
-logic__5122: logic__5122
-logic__1126: logic__1126
-datapath__30: datapath__30
-logic__4401: logic__4401
-logic__8109: logic__8109
-case__536: case__536
-datapath__324: datapath__324
-case__1639: case__1639
-case__997: case__997
-logic__5582: logic__5582
-datapath__27: datapath__27
-logic__7378: logic__7378
-datapath__185: datapath__185
-logic__2235: logic__2235
-CSRFile: CSRFile
-case__141: case__141
-reg__284: reg__284
-logic__4180: logic__4180
-counter__14: counter__14
-muxpart__27: muxpart__27
-reg__262: reg__262
-reg__437: reg__437
-logic__4504: logic__4504
-case__1806: case__305
-RocketTile__GCB0: RocketTile__GCB0
-case__1205: case__1205
-logic__1868: logic__1868
-logic__3739: logic__3739
-datapath__623: datapath__623
-case__976: case__976
-logic__8399: logic__8399
-logic__7408: logic__7408
-SBToTL: SBToTL
-TLFpgaSPI: TLFpgaSPI
-reg__1044: reg__1044
-logic__6870: logic__6870
-logic__2446: logic__2446
-logic__5638: logic__5638
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__17: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__8958: logic__8958
-case__195: case__195
-reg__71: reg__71
-muxpart__50: muxpart__50
-case__428: case__428
-AsyncResetSynchronizerShiftReg_w1_d3_i0__5: AsyncResetSynchronizerShiftReg_w1_d3_i0
-reg__129: reg__129
-logic__2696: logic__2696
-datapath__107: datapath__107
-logic__9671: logic__4551
-logic__6816: logic__6816
-logic__2742: logic__2742
-logic__7405: logic__7405
-logic__9669: logic__4553
-case__947: case__947
-logic__7347: logic__7347
-case__622: case__622
-logic__1899: logic__1899
-logic__785: logic__785
-logic__5471: logic__5471
-datapath__775: datapath__37
-logic__9124: logic__9124
-datapath__300: datapath__300
-datapath__508: datapath__508
-datapath__473: datapath__473
-logic__5376: logic__5376
-reg__1046: reg__1046
-case__321: case__321
-reg__1195: reg__1195
-reg__58: reg__58
-case__61: case__61
-reg__340: reg__340
-logic__2614: logic__2614
-logic__135: logic__135
-case__1095: case__1095
-case__472: case__472
-logic__4179: logic__4179
-logic__6174: logic__6174
-logic__6947: logic__6947
-logic__6746: logic__6746
-case__312: case__312
-logic__738: logic__738
-case__23: case__23
-case__727: case__727
-muxpart__188: muxpart__188
-logic__7185: logic__7185
-logic__7400: logic__7400
-reg__6: reg__6
-logic__7268: logic__7268
-TLBuffer_a32d64s1k1z4u: TLBuffer_a32d64s1k1z4u
-case__1800: case__311
-logic__7628: logic__7628
-reg__353: reg__353
-case__655: case__655
-ram_2x115: ram_2x115
-logic__9721: logic__2538
-logic__7379: logic__7379
-cordic_angle_lut__parameterized0__1: cordic_angle_lut__parameterized0
-logic__58: logic__58
-logic__9023: logic__9023
-logic__7660: logic__7660
-reg__413: reg__413
-addsub__6: addsub__6
-logic__3216: logic__3216
-logic__4514: logic__4514
-logic__4963: logic__4963
-logic__1728: logic__1728
-logic__1723: logic__1723
-case__1810: case__301
-logic__2826: logic__2826
-reg__511: reg__511
-logic__5983: logic__5983
-logic__6593: logic__6593
-logic__4162: logic__4162
-logic__9675: logic__4522
-datapath__599: datapath__599
-RecFNToIN_1: RecFNToIN_1
-reg__352: reg__352
-logic__6903: logic__6903
-datapath__624: datapath__624
-muxpart__215: muxpart__215
-reg__1293: reg__1293
-datapath__307: datapath__307
-logic__6583: logic__6583
-case__941: case__941
-datapath__542: datapath__542
-datapath__167: datapath__167
-datapath__162: datapath__162
-reg__327: reg__327
-reg__958: reg__958
-case__449: case__449
-reg__552: reg__552
-logic__5425: logic__5425
-logic__6979: logic__6979
-logic__5046: logic__5046
-datapath__361: datapath__361
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__35: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__1031: case__1031
-case__375: case__375
-logic__835: logic__835
-case__142: case__142
-logic__2486: logic__2486
-logic__8182: logic__8182
-logic__6955: logic__6955
-reg__169: reg__169
-logic__666: logic__666
-reg__1124: reg__1124
-logic__4984: logic__4984
-logic__2816: logic__2816
-reg__1202: reg__1202
-logic__9946: logic__1146
-logic__1741: logic__1741
-logic__2679: logic__2679
-logic__9020: logic__9020
-logic__4932: logic__4932
-reg__924: reg__924
-logic__5717: logic__5717
-reg__746: reg__746
-logic__7255: logic__7255
-reg__910: reg__910
-reg__1611: reg__150
-logic__979: logic__979
-logic__9837: logic__2217
-reg__1475: reg__1088
-logic__6173: logic__6173
-logic__4316: logic__4316
-logic__7101: logic__7101
-logic__5693: logic__5693
-logic__8237: logic__8237
-logic__9384: logic__9384
-datapath__91: datapath__91
-ClockGroupAggregator_pbus: ClockGroupAggregator_pbus
-dsp48e1__30: dsp48e1__30
-logic__5972: logic__5972
-logic__7229: logic__7229
-logic__4407: logic__4407
-logic__5193: logic__5193
-logic__922: logic__922
-logic__2173: logic__2173
-logic__5472: logic__5472
-reg__490: reg__490
-logic__3972: logic__3972
-case__44: case__44
-case__1324: case__1324
-reg__128: reg__128
-logic__8832: logic__8832
-reg__370: reg__370
-logic__6041: logic__6041
-logic__9244: logic__9244
-case__419: case__419
-datapath__426: datapath__426
-logic__7706: logic__7706
-reg__706: reg__706
-logic__7142: logic__7142
-case__380: case__380
-reg__1146: reg__1146
-logic__5433: logic__5433
-ram__13: ram__1
-case__608: case__608
-logic__6451: logic__6451
-logic__6283: logic__6283
-logic__1257: logic__1257
-reg__155: reg__155
-logic__7576: logic__7576
-logic__1809: logic__1809
-reg__833: reg__833
-muxpart__173: muxpart__173
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__8: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__914: reg__914
-logic__6880: logic__6880
-case__1668: case__1668
-logic__150: logic__150
-case__241: case__241
-logic__9840: logic__2208
-logic__1581: logic__1581
-logic__5154: logic__5154
-logic__7120: logic__7120
-case__1645: case__1645
-case__1641: case__1641
-logic__4806: logic__4806
-case__834: case__834
-datapath__234: datapath__234
-muxpart__202: muxpart__202
-case__858: case__858
-logic__8037: logic__8037
-datapath__517: datapath__517
-logic__3319: logic__3319
-logic__4039: logic__4039
-case__306: case__306
-datapath__767: datapath__118
-logic__3354: logic__3354
-logic__1341: logic__1341
-case__1489: case__1489
-muxpart__170: muxpart__170
-accum_dump: accum_dump
-case__790: case__790
-logic__9058: logic__9058
-logic__7373: logic__7373
-reg__480: reg__480
-case__20: case__20
-case__1511: case__1511
-logic__8578: logic__8578
-logic__8167: logic__8167
-logic__961: logic__961
-logic__5940: logic__5940
-counter__10: counter__10
-logic__593: logic__593
-logic__206: logic__206
-reg__1033: reg__1033
-reg__666: reg__666
-case__703: case__703
-logic__6826: logic__6826
-reg__1446: reg__202
-logic__5048: logic__5048
-logic__6667: logic__6667
-logic__6515: logic__6515
-datapath__29: datapath__29
-logic__6896: logic__6896
-logic__1616: logic__1616
-case__1217: case__1217
-logic__1652: logic__1652
-logic__8785: logic__8785
-logic__218: logic__218
-logic__1455: logic__1455
-reg__971: reg__971
-logic__8112: logic__8112
-logic__3312: logic__3312
-logic__3480: logic__3480
-datapath__121: datapath__121
-muxpart__176: muxpart__176
-case__1611: case__1611
-logic__7750: logic__7750
-logic__4718: logic__4718
-datapath__702: datapath__702
-logic__5488: logic__5488
-reg__123: reg__123
-dsp48e1__32: dsp48e1__32
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__23: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__9359: logic__9359
-reg__495: reg__495
-reg__606: reg__606
-logic__3624: logic__3624
-case__43: case__43
-reg__1612: reg__149
-case__1554: case__1554
-TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u: TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u
-dsp48e1__12: dsp48e1__12
-case__37: case__37
-case__1206: case__1206
-signinv__1: signinv__1
-logic__1023: logic__1023
-reg__141: reg__141
-reg__967: reg__967
-logic__9018: logic__9018
-logic__2853: logic__2853
-logic__3112: logic__3112
-logic__4594: logic__4594
-logic__9814: logic__2268
-reg__560: reg__560
-muxpart__224: muxpart__224
-logic__5515: logic__5515
-datapath__374: datapath__374
-reg__1306: reg__1306
-logic__7394: logic__7394
-reg__127: reg__127
-reg__1211: reg__1211
-logic__4469: logic__4469
-case__1089: case__1089
-logic__1951: logic__1951
-AsyncValidSync__16: AsyncValidSync
-logic__893: logic__893
-logic__2245: logic__2245
-logic__5303: logic__5303
-case__480: case__480
-datapath__569: datapath__569
-logic__5948: logic__5948
-logic__3552: logic__3552
-logic__9877: logic__1303
-case__1380: case__1380
-logic__5544: logic__5544
-logic__4959: logic__4959
-logic__7858: logic__7858
-case__374: case__374
-logic__9972: logic__901
-logic__5581: logic__5581
-logic__9752: logic__2461
-reg__688: reg__688
-logic__1173: logic__1173
-logic__9896: logic__8885
-logic__2630: logic__2630
-logic__3911: logic__3911
-reg__253: reg__253
-case__741: case__741
-logic__9040: logic__9040
-case__735: case__735
-logic__7667: logic__7667
-case__28: case__28
-logic__2242: logic__2242
-reg__41: reg__41
-reg__354: reg__354
-logic__9703: logic__2479
-logic__372: logic__372
-logic__7033: logic__7033
-datapath__304: datapath__304
-reg__771: reg__771
-datapath__118: datapath__118
-logic__4969: logic__4969
-logic__3482: logic__3482
-AsyncQueueSink_TLBundleA_a9d32s1k1z2u: AsyncQueueSink_TLBundleA_a9d32s1k1z2u
-case__867: case__867
-extrom__1: extrom__1
-case__1078: case__1078
-logic__3184: logic__3184
-datapath__335: datapath__335
-muxpart__256: muxpart__256
-reg__858: reg__858
-datapath__197: datapath__197
-case__1436: case__1436
-logic__2279: logic__2279
-logic__9329: logic__9329
-logic__4443: logic__4443
-logic__1889: logic__1889
-reg__810: reg__810
-logic__9267: logic__9267
-reg__685: reg__685
-logic__9697: logic__2495
-reg__554: reg__554
-logic__7391: logic__7391
-datapath__321: datapath__321
-logic__6741: logic__6741
-datapath__217: datapath__217
-logic__7546: logic__7546
-datapath__679: datapath__679
-case__1658: case__1658
-logic__351: logic__351
-logic__6940: logic__6940
-PeripheryBus_cbus: PeripheryBus_cbus
-reg__463: reg__463
-reg__1045: reg__1045
-case__1119: case__1119
-logic__6170: logic__6170
-datapath__503: datapath__503
-reg__271: reg__271
-logic__8352: logic__8352
-logic__2776: logic__2776
-logic__9141: logic__9141
-case__527: case__527
-logic__4505: logic__4505
-logic__3044: logic__3044
-logic__3803: logic__3803
-ram__12: ram__4
-reg__1386: reg__1386
-logic__6998: logic__6998
-keep__45: keep__14
-case__1058: case__1058
-logic__812: logic__812
-logic__7226: logic__7226
-reg__873: reg__873
-logic__6684: logic__6684
-AsyncValidSync__12: AsyncValidSync
-logic__7145: logic__7145
-logic__4490: logic__4490
-logic__6760: logic__6760
-logic__210: logic__210
-reg__823: reg__823
-Queue2_TLBundleA_a14d64s2k1z4u: Queue2_TLBundleA_a14d64s2k1z4u
-logic__5932: logic__5932
-logic__2260: logic__2260
-logic__8910: logic__8910
-case__804: case__804
-muxpart__208: muxpart__208
-reg__121: reg__121
-case__1365: case__1365
-logic__9151: logic__9151
-case__886: case__886
-reg__1282: reg__1282
-logic__3082: logic__3082
-case__3: case__3
-logic__1245: logic__1245
-reg__170: reg__170
-logic__2690: logic__2690
-logic__4557: logic__4557
-logic__9844: logic__2200
-datapath__156: datapath__156
-case__1422: case__1422
-case__1041: case__1041
-reg__371: reg__371
-datapath__401: datapath__401
-datapath__459: datapath__459
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__36: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-FrontBus: FrontBus
-muxpart__233: muxpart__233
-logic__548: logic__548
-logic__4555: logic__4555
-case__1086: case__1086
-DivSqrtRawFN_small_1: DivSqrtRawFN_small_1
-case__1102: case__1102
-reg__1287: reg__1287
-case: case
-logic__1548: logic__1548
-reg__56: reg__56
-logic__6929: logic__6929
-reg__191: reg__191
-case__214: case__214
-logic__7571: logic__7571
-logic__6823: logic__6823
-reg__525: reg__525
-reg__801: reg__801
-case__924: case__924
-logic__9850: logic__2188
-logic__5495: logic__5495
-reg__1589: reg__924
-logic__3297: logic__3297
-logic__4473: logic__4473
-logic__6909: logic__6909
-logic__5393: logic__5393
-Repeater_TLBundleA_a17d64s2k1z3u: Repeater_TLBundleA_a17d64s2k1z3u
-datapath__745: datapath__136
-case__1065: case__1065
-LevelGateway__3: LevelGateway
-case__304: case__304
-muxpart__51: muxpart__51
-logic__6650: logic__6650
-reg__1551: reg__926
-logic__1150: logic__1150
-reg__1580: reg__924
-logic__7307: logic__7307
-logic__9962: logic__1109
-datapath__13: datapath__13
-logic__130: logic__130
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__25: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__3040: logic__3040
-logic__1774: logic__1774
-logic__965: logic__965
-logic__9643: logic__3588
-case__772: case__772
-logic__85: logic__85
-case__1055: case__1055
-reg__1345: reg__1345
-extrom__3: extrom
-logic__5846: logic__5846
-logic__8224: logic__8224
-reg__678: reg__678
-logic__5380: logic__5380
-IntSyncSyncCrossingSink_n1x2: IntSyncSyncCrossingSink_n1x2
-datapath__196: datapath__196
-reg__1233: reg__1233
-logic__2702: logic__2702
-reg__44: reg__44
-logic__6166: logic__6166
-muxpart__14: muxpart__14
-IntSyncCrossingSource_n1x1: IntSyncCrossingSource_n1x1
-logic__7640: logic__7640
-reg__303: reg__303
-muxpart__258: muxpart__258
-case__289: case__289
-muxpart__359: muxpart__359
-case__279: case__279
-muxpart__379: muxpart__379
-reg__1337: reg__1337
-logic__4931: logic__4931
-reg__1529: reg__924
-logic__6827: logic__6827
-datapath__136: datapath__136
-reg__388: reg__388
-logic__7428: logic__7428
-case__1513: case__1513
-reg__1163: reg__1163
-reg__530: reg__530
-case__1615: case__1615
-case__284: case__284
-logic__2413: logic__2413
-logic__9945: logic__1149
-logic__4265: logic__4265
-reg__1308: reg__1308
-logic__9653: logic__4578
-case__675: case__675
-logic__7322: logic__7322
-logic__5936: logic__5936
-logic__5691: logic__5691
-reg__295: reg__295
-datapath__112: datapath__112
-logic__7655: logic__7655
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__18: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__5407: logic__5407
-logic__1685: logic__1685
-logic__4403: logic__4403
-case__55: case__55
-logic__3016: logic__3016
-logic__8969: logic__8969
-reg__86: reg__86
-case__308: case__308
-logic__4748: logic__4748
-case__1626: case__1626
-logic__679: logic__679
-reg__1342: reg__1342
-logic__4352: logic__4352
-logic__9740: logic__2489
-reg__1509: reg__926
-reg__665: reg__665
-logic__6079: logic__6079
-logic__207: logic__207
-datapath__350: datapath__350
-case__1052: case__1052
-logic__7505: logic__7505
-logic__1278: logic__1278
-logic__2492: logic__2492
-counter__28: counter__28
-logic__9755: logic__2452
-reg__1017: reg__1017
-keep__25: keep__16
-logic__7186: logic__7186
-reg__1498: reg__925
-logic__1106: logic__1106
-reg__993: reg__993
-logic__7213: logic__7213
-reg__1176: reg__1176
-datapath__336: datapath__336
-case__202: case__202
-reg__29: reg__29
-Queue2_TLBundleD_a32d64s2k1z4u: Queue2_TLBundleD_a32d64s2k1z4u
-logic__558: logic__558
-reg__911: reg__911
-reg__1372: reg__1372
-datapath__612: datapath__612
-reg__507: reg__507
-logic__2977: logic__2977
-logic__4318: logic__4318
-muxpart__34: muxpart__34
-logic__5039: logic__5039
-logic__2701: logic__2701
-logic__779: logic__779
-case__525: case__525
-logic__9114: logic__9114
-datapath__657: datapath__657
-counter__9: counter__9
-logic__9580: logic__9580
-case__514: case__514
-case__1758: case__732
-logic__1615: logic__1615
-PMAChecker__2: PMAChecker
-datapath__72: datapath__72
-case__1572: case__1572
-logic__5949: logic__5949
-reg__650: reg__650
-logic__7537: logic__7537
-logic__5536: logic__5536
-logic__7876: logic__7876
-logic__7510: logic__7510
-datapath__479: datapath__479
-logic__1463: logic__1463
-case__451: case__451
-case__1432: case__1432
-reg__735: reg__735
-reg__524: reg__524
-ram__14: ram__1
-extrom__2: extrom__1
-dsp48e1__9: dsp48e1__9
-logic__3328: logic__3328
-logic__4089: logic__4089
-case__441: case__441
-reg__1028: reg__1028
-logic__5150: logic__5150
-afe_top: afe_top
-logic__7464: logic__7464
-logic__9562: logic__9562
-datapath__363: datapath__363
-logic__7955: logic__7955
-muxpart__230: muxpart__230
-logic__1674: logic__1674
-case__1370: case__1370
-logic__7360: logic__7360
-logic__3553: logic__3553
-reg__1606: reg__155
-reg__76: reg__76
-case__152: case__152
-logic__3165: logic__3165
-case__992: case__992
-reg__1274: reg__1274
-keep__55: keep__10
-logic__8249: logic__8249
-logic__7155: logic__7155
-case__1308: case__1308
-reg__201: reg__201
-reg__863: reg__863
-case__851: case__851
-muxpart__190: muxpart__190
-reg__902: reg__902
-case__424: case__424
-logic__624: logic__624
-logic__7175: logic__7175
-logic__1730: logic__1730
-TLXbar_sbus_i2_o1_a32d64s2k1z4u: TLXbar_sbus_i2_o1_a32d64s2k1z4u
-logic__42: logic__42
-reg__655: reg__655
-DCacheDataArray: DCacheDataArray
-logic__9873: logic__915
-case__993: case__993
-logic__5786: logic__5786
-case__208: case__208
-case__824: case__824
-logic__4108: logic__4108
-reg__1040: reg__1040
-datapath__707: datapath__707
-logic__2967: logic__2967
-muxpart__185: muxpart__185
-logic__8254: logic__8254
-case__333: case__333
-logic__6021: logic__6021
-logic__3916: logic__3916
-logic__1986: logic__1986
-fft_radix_2: fft_radix_2
-reg__369: reg__369
-logic__7082: logic__7082
-reg__612: reg__612
-logic__9634: logic__3614
-logic__2537: logic__2537
-datapath__540: datapath__540
-logic__7302: logic__7302
-reg__1432: reg__1432
-logic__9852: logic__2182
-logic__2254: logic__2254
-logic__4094: logic__4094
-datapath__252: datapath__252
-case__784: case__784
-logic__8023: logic__8023
-acq_wrapper: acq_wrapper
-datapath__477: datapath__477
-logic__2470: logic__2470
-logic__8420: logic__8420
-logic__8012: logic__8012
-case__457: case__457
-reg__1553: reg__924
-logic__3466: logic__3466
-logic__8503: logic__8503
-dsp48e1__31: dsp48e1__31
-muxpart__189: muxpart__189
-logic__6683: logic__6683
-logic__7945: logic__7945
-logic__9367: logic__9367
-case__880: case__880
-logic__4572: logic__4572
-logic__849: logic__849
-case__232: case__232
-case__556: case__556
-logic__9847: logic__2191
-logic__7139: logic__7139
-case__820: case__820
-logic__9712: logic__2560
-muxpart__133: muxpart__133
-logic__7028: logic__7028
-reg__822: reg__822
-reg__1185: reg__1185
-case__1608: case__1608
-reg__684: reg__684
-logic__1751: logic__1751
-datapath__286: datapath__286
-logic__2675: logic__2675
-case__399: case__399
-reg__1007: reg__1007
-AsyncValidSync__18: AsyncValidSync
-logic__2911: logic__2911
-logic__6620: logic__6620
-logic__8197: logic__8197
-logic__4394: logic__4394
-logic__3270: logic__3270
-reg__47: reg__47
-logic__7775: logic__7775
-ram__10: ram__1
-case__1599: case__1599
-reg__1444: reg__204
-logic__9357: logic__9357
-cordic_atan_basic__parameterized0__1: cordic_atan_basic__parameterized0
-logic__8181: logic__8181
-logic__871: logic__871
-datapath__245: datapath__245
-logic__4353: logic__4353
-logic__8582: logic__8582
-reg__582: reg__582
-logic__6765: logic__6765
-logic__1397: logic__1397
-logic__2985: logic__2985
-logic__613: logic__613
-reg__229: reg__229
-logic__2770: logic__2770
-reg__577: reg__577
-logic__1447: logic__1447
-reg__704: reg__704
-logic__3183: logic__3183
-case__1158: case__1158
-logic__5112: logic__5112
-logic__6825: logic__6825
-logic__993: logic__993
-logic__3034: logic__3034
-reg__60: reg__60
-muxpart__128: muxpart__128
-datapath__509: datapath__509
-case__1015: case__1015
-ram_2x124: ram_2x124
-reg__1323: reg__1323
-case__854: case__854
-datapath__44: datapath__44
-case__233: case__233
-ram__5: ram__5
-reg__573: reg__573
-case__210: case__210
-case__453: case__453
-logic__1744: logic__1744
-case__200: case__200
-TLROM: TLROM
-case__811: case__811
-logic__5527: logic__5527
-logic__7441: logic__7441
-case__592: case__592
-reg__996: reg__996
-logic__4330: logic__4330
-logic__2475: logic__2475
-logic__5369: logic__5369
-logic__9629: logic__3619
-case__1592: case__1592
-reg__24: reg__24
-logic__3826: logic__3826
-reg__124: reg__124
-case__1801: case__310
-reg__728: reg__728
-logic__816: logic__816
-case__1476: case__1476
-logic__4645: logic__4645
-reg__1069: reg__1069
-case__293: case__293
-reg__254: reg__254
-logic__180: logic__180
-logic__7448: logic__7448
-logic__1130: logic__1130
-case__1560: case__1560
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__1494: reg__926
-case__481: case__481
-logic__3561: logic__3561
-logic__6899: logic__6899
-case__562: case__562
-reg__146: reg__146
-logic__923: logic__923
-logic__9845: logic__2199
-logic__2622: logic__2622
-logic__4175: logic__4175
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__1: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__1455: reg__1333
-logic__9788: logic__2342
-logic__749: logic__749
-reg__101: reg__101
-logic__9731: logic__2516
-case__1122: case__1122
-logic__5484: logic__5484
-logic__8688: logic__8688
-datapath__449: datapath__449
-case__1218: case__1218
-logic__6782: logic__6782
-reg__1131: reg__1131
-datapath__299: datapath__299
-keep__5: keep__5
-logic__7009: logic__7009
-logic__9887: logic__9096
-reg__1404: reg__1404
-muxpart__31: muxpart__31
-muxpart__16: muxpart__16
-logic__9899: logic__8882
-DivSqrtRecFNToRaw_small_1: DivSqrtRecFNToRaw_small_1
-logic__4974: logic__4974
-logic__1636: logic__1636
-MulAddRecFNToRaw_postMul_1: MulAddRecFNToRaw_postMul_1
-logic__9604: logic__9604
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__1069: logic__1069
-case__1590: case__1590
-reg__734: reg__734
-logic__4422: logic__4422
-reg__384: reg__384
-datapath__523: datapath__523
-case__532: case__532
-case__717: case__717
-reg__870: reg__870
-case__60: case__60
-case__1241: case__1241
-reg__122: reg__122
-case__256: case__256
-logic__114: logic__114
-logic__7397: logic__7397
-logic__7849: logic__7849
-logic__5364: logic__5364
-reg__17: reg__17
-logic__8241: logic__8241
-datapath__229: datapath__229
-logic__5927: logic__5927
-logic__3261: logic__3261
-case__467: case__467
-logic__4639: logic__4639
-logic__4617: logic__4617
-logic__7283: logic__7283
-case__446: case__446
-logic__1419: logic__1419
-logic__1220: logic__1220
-butterfly: butterfly
-reg__1496: reg__924
-rom__4: rom__4
-muxpart__401: muxpart__163
-muxpart__203: muxpart__203
-logic__3342: logic__3342
-logic__1277: logic__1277
-case__1240: case__1240
-logic__3330: logic__3330
-case__590: case__590
-muxpart__231: muxpart__231
-datapath__512: datapath__512
-case__217: case__217
-logic__897: logic__897
-datapath__253: datapath__253
-reg__405: reg__405
-logic__4983: logic__4983
-logic__1861: logic__1861
-reg__214: reg__214
-logic__9610: logic__9610
-logic__3113: logic__3113
-reg__414: reg__414
-logic__47: logic__47
-logic__4421: logic__4421
-case__611: case__611
-muxpart__206: muxpart__206
-logic__7310: logic__7310
-logic__1254: logic__1254
-datapath__576: datapath__576
-logic__6862: logic__6862
-reg__681: reg__681
-ClockGroup__1: ClockGroup
-reg__813: reg__813
-muxpart__21: muxpart__21
-logic__1688: logic__1688
-datapath__553: datapath__553
-logic__7136: logic__7136
-logic__9797: logic__2313
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__12: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__1307: logic__1307
-logic__2582: logic__2582
-datapath__8: datapath__8
-datapath__584: datapath__584
-datapath__636: datapath__636
-logic__3856: logic__3856
-datapath__641: datapath__641
-case__248: case__248
-reg__1281: reg__1281
-datapath__337: datapath__337
-logic__7237: logic__7237
-reg__934: reg__934
-reg__589: reg__589
-logic__3314: logic__3314
-logic__5372: logic__5372
-datapath__274: datapath__274
-logic__2758: logic__2758
-logic__8585: logic__8585
-reg__607: reg__607
-PlusArgTimeout: PlusArgTimeout
-reg__1364: reg__1364
-muxpart__344: muxpart__344
-case__601: case__601
-case__1200: case__1200
-case__390: case__390
-datapath__469: datapath__469
-case__1420: case__1420
-muxpart__4: muxpart__4
-logic__1821: logic__1821
-logic__8329: logic__8329
-logic__790: logic__790
-logic__3957: logic__3957
-logic__2980: logic__2980
-logic__9311: logic__9311
-logic__5374: logic__5374
-datapath__381: datapath__381
-Arbiter8_DCacheMetadataReq: Arbiter8_DCacheMetadataReq
-reg__645: reg__645
-logic__9831: logic__2227
-case__1625: case__1625
-logic__1328: logic__1328
-logic__820: logic__820
-case__547: case__547
-case__1127: case__1127
-logic__3614: logic__3614
-dsp48e1__44: dsp48e1__44
-logic__4107: logic__4107
-logic__8907: logic__8907
-case__1226: case__1226
-logic__7723: logic__7723
-datapath__125: datapath__125
-reg__1231: reg__1231
-reg__843: reg__843
-logic__6011: logic__6011
-logic__5221: logic__5221
-logic__6506: logic__6506
-case__1528: case__1528
-logic__2209: logic__2209
-logic__3494: logic__3494
-logic__5440: logic__5440
-reg__1453: reg__1335
-logic__6085: logic__6085
-logic__9022: logic__9022
-logic__9875: logic__910
-logic__7121: logic__7121
-logic__3472: logic__3472
-case__436: case__436
-case__300: case__300
-logic__4269: logic__4269
-muxpart__80: muxpart__80
-ClockGroup__2: ClockGroup
-Arbiter3_LLWB: Arbiter3_LLWB
-logic__4374: logic__4374
-logic__8282: logic__8282
-logic__6156: logic__6156
-case__1233: case__1233
-extram__2: extram__2
-logic__5687: logic__5687
-datapath__539: datapath__539
-logic__6960: logic__6960
-reg__816: reg__816
-logic__3325: logic__3325
-logic__3074: logic__3074
-case__1475: case__1475
-logic__6500: logic__6500
-RocketALU: RocketALU
-ram_2x120: ram_2x120
-datapath__769: datapath__43
-logic__3555: logic__3555
-logic__4569: logic__4569
-datapath__756: datapath__670
-dsp48e1__34: dsp48e1__34
-logic__8287: logic__8287
-reg__1135: reg__1135
-logic__1793: logic__1793
-logic__1773: logic__1773
-AsyncValidSync__5: AsyncValidSync
-datapath__244: datapath__244
-TLFragmenter_PLIC: TLFragmenter_PLIC
-logic__7392: logic__7392
-logic__6637: logic__6637
-datapath__303: datapath__303
-reg__723: reg__723
-reg__23: reg__23
-logic__4943: logic__4943
-logic__8225: logic__8225
-logic__7547: logic__7547
-case__1506: case__1506
-case__773: case__773
-reg__923: reg__923
-logic__3880: logic__3880
-reg__1241: reg__1241
-logic__2931: logic__2931
-logic__6321: logic__6321
-logic__857: logic__857
-reg__662: reg__662
-logic__1570: logic__1570
-logic__4675: logic__4675
-datapath__47: datapath__47
-reg__1199: reg__1199
-logic__8605: logic__8605
-datapath__404: datapath__404
-logic__2518: logic__2518
-logic__4444: logic__4444
-logic__5933: logic__5933
-reg__96: reg__96
-logic__7997: logic__7997
-logic__7832: logic__7832
-logic__2049: logic__2049
-logic__647: logic__647
-logic__7043: logic__7043
-reg__917: reg__917
-logic__3159: logic__3159
-reg__781: reg__781
-logic__4398: logic__4398
-logic__7871: logic__7871
-logic__8328: logic__8328
-reg__484: reg__484
-reg__1596: reg__874
-logic__9642: logic__3591
-logic__751: logic__751
-reg__1188: reg__1188
-reg__538: reg__538
-datapath__759: datapath__537
-logic__9782: logic__2362
-reg__3: reg__3
-logic__955: logic__955
-datapath__260: datapath__260
-datapath__690: datapath__690
-logic__2250: logic__2250
-keep__8: keep__8
-datapath__715: datapath__715
-reg__1497: reg__926
-logic__2022: logic__2022
-case__302: case__302
-logic__9010: logic__9010
-reg__762: reg__762
-reg__111: reg__111
-logic__9849: logic__2189
-logic__2232: logic__2232
-logic__783: logic__783
-datapath__617: datapath__617
-case__123: case__123
-reg__283: reg__283
-counter__27: counter__27
-logic__188: logic__188
-reg__1608: reg__153
-case__828: case__828
-logic__9232: logic__9232
-logic__8889: logic__8889
-logic__7639: logic__7639
-logic__6748: logic__6748
-reg__1327: reg__1327
-case__520: case__520
-reg__1541: reg__924
-logic__6553: logic__6553
-datapath__534: datapath__534
-logic__4289: logic__4289
-case__1113: case__1113
-reg__772: reg__772
-logic__4954: logic__4954
-logic__7316: logic__7316
-extram__7: extram__7
-logic__4008: logic__4008
-reg__1341: reg__1341
-case__1117: case__1117
-datapath__760: datapath__162
-logic__1094: logic__1094
-reg__811: reg__811
-case__1236: case__1236
-case__747: case__747
-logic__5914: logic__5914
-LevelGateway__8: LevelGateway
-logic__1949: logic__1949
-datapath__364: datapath__364
-logic__3012: logic__3012
-logic__2584: logic__2584
-logic__5426: logic__5426
-datapath__224: datapath__224
-case__299: case__299
-logic__8784: logic__8784
-logic__5304: logic__5304
-muxpart__151: muxpart__151
-datapath__538: datapath__538
-case__1734: case__1734
-logic__718: logic__718
-reg__874: reg__874
-case__882: case__882
-case__247: case__247
-logic__8442: logic__8442
-logic__2516: logic__2516
-datapath__377: datapath__377
-reg__358: reg__358
-logic__4566: logic__4566
-logic__4491: logic__4491
-case__1056: case__1056
-logic__2680: logic__2680
-datapath__83: datapath__83
-logic__2152: logic__2152
-logic__6575: logic__6575
-logic__9882: logic__1293
-case__894: case__894
-logic__1124: logic__1124
-datapath__586: datapath__586
-reg__1038: reg__1038
-logic__1396: logic__1396
-reg__74: reg__74
-logic__7808: logic__7808
-counter__30: counter__30
-case__1539: case__1539
-datapath__3: datapath__3
-datapath__184: datapath__184
-logic__4999: logic__4999
-logic__7096: logic__7096
-case__1019: case__1019
-datapath__556: datapath__556
-muxpart__17: muxpart__17
-logic__5913: logic__5913
-case__830: case__830
-logic__2263: logic__2263
-case__926: case__926
-logic__1845: logic__1845
-case__1759: case__730
-datapath__748: datapath__133
-logic__7594: logic__7594
-datapath__771: datapath__41
-case__1437: case__1437
-datapath__291: datapath__291
-logic__4830: logic__4830
-reg__1238: reg__1238
-logic__4728: logic__4728
-case__180: case__180
-logic__2705: logic__2705
-TLError: TLError
-reg__432: reg__432
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__9: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__491: case__491
-reg__1252: reg__1252
-logic__2102: logic__2102
-reg__272: reg__272
-logic__5076: logic__5076
-datapath__326: datapath__326
-case__422: case__422
-logic__4043: logic__4043
-logic__6804: logic__6804
-logic__5172: logic__5172
-logic__6952: logic__6952
-case__1080: case__1080
-logic__6933: logic__6933
-logic__4379: logic__4379
-reg__1078: reg__1078
-logic__9520: logic__9520
-logic__5361: logic__5361
-logic__622: logic__622
-case__1159: case__1159
-logic__5916: logic__5916
-case__734: case__734
-datapath__64: datapath__64
-case__1172: case__1172
-logic__7026: logic__7026
-logic__8548: logic__8548
-case__519: case__519
-case__623: case__623
-reg__875: reg__875
-case__1718: case__1718
-datapath__110: datapath__110
-reg__828: reg__828
-reg__1454: reg__1334
-case__696: case__696
-logic__1732: logic__1732
-reg__243: reg__243
-case__911: case__911
-case__1593: case__1593
-case__1181: case__1181
-logic__9955: logic__1125
-cordic_atan_basic: cordic_atan_basic
-case__1121: case__1121
-logic__9427: logic__9427
-extram__1: extram__1
-case__1791: case__1614
-logic__520: logic__520
-case__1096: case__1096
-case__1028: case__1028
-logic__1073: logic__1073
-logic__7184: logic__7184
-logic__1605: logic__1605
-logic__2170: logic__2170
-MulAddRecFNPipe_l2_e8_s24: MulAddRecFNPipe_l2_e8_s24
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__15: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-RoundRawFNToRecFN_1__1: RoundRawFNToRecFN_1
-DivSqrtRecFN_small_1: DivSqrtRecFN_small_1
-mult_46_15_61__3: mult_46_15_61
-logic__953: logic__953
-logic__1810: logic__1810
-case__647: case__647
-reg__306: reg__306
-muxpart__160: muxpart__160
-logic__8022: logic__8022
-logic__3166: logic__3166
-case__1207: case__1207
-reg__676: reg__676
-case__950: case__950
-logic__7946: logic__7946
-logic__9096: logic__9096
-reg__1245: reg__1245
-logic__529: logic__529
-logic__7730: logic__7730
-logic__7645: logic__7645
-logic__7156: logic__7156
-logic__6893: logic__6893
-counter__25: counter__25
-logic__2030: logic__2030
-logic__2821: logic__2821
-logic__7251: logic__7251
-reg__1016: reg__1016
-reg__1441: reg__207
-logic__5827: logic__5827
-case__1170: case__1170
-logic__634: logic__634
-logic__6848: logic__6848
-logic__9951: logic__1131
-logic__3348: logic__3348
-datapath__716: datapath__325
-logic__7352: logic__7352
-logic__9835: logic__2221
-case__245: case__245
-reg__1314: reg__1314
-logic__4320: logic__4320
-logic__5363: logic__5363
-reg__110: reg__110
-mdio_rtl8211e_init: mdio_rtl8211e_init
-logic__6857: logic__6857
-logic__5952: logic__5952
-keep: keep
-logic__6869: logic__6869
-logic__9645: logic__4614
-reg__730: reg__730
-reg__667: reg__667
-logic__7151: logic__7151
-logic__850: logic__850
-reg__752: reg__752
-reg__1356: reg__1356
-logic__7372: logic__7372
-logic__4321: logic__4321
-logic__9519: logic__9519
-logic__3523: logic__3523
-double_ff_syn__3: double_ff_syn
-logic__892: logic__892
-reg__318: reg__318
-reg__1499: reg__924
-reg__435: reg__435
-logic__1084: logic__1084
-logic__5406: logic__5406
-datapath__481: datapath__481
-reg__1443: reg__205
-reg__154: reg__154
-reg__518: reg__518
-case__1201: case__1201
-logic__3827: logic__3827
-reg__428: reg__428
-reg__182: reg__182
-dsp48e1__14: dsp48e1__14
-counter__2: counter__2
-ram: ram
-reg__1168: reg__1168
-case__1263: case__1263
-logic__8947: logic__8947
-case__239: case__239
-logic__6757: logic__6757
-counter__23: counter__23
-logic__9865: logic__2155
-addsub__5: addsub__5
-case__459: case__459
-case__1588: case__1588
-case__207: case__207
-reg__1391: reg__1391
-logic__4578: logic__4578
-logic__610: logic__610
-logic__7067: logic__7067
-datapath__93: datapath__93
-sync__3: sync
-case__541: case__541
-logic__6798: logic__6798
-logic__6547: logic__6547
-logic__8057: logic__8057
-logic__3276: logic__3276
-logic__129: logic__129
-reg__710: reg__710
-logic__7172: logic__7172
-TLDebugModuleInner: TLDebugModuleInner
-logic__3830: logic__3830
-logic__1063: logic__1063
-datapath__312: datapath__312
-logic__5906: logic__5906
-case__1797: case__1608
-datapath__365: datapath__365
-case__1125: case__1125
-datapath__124: datapath__124
-logic__1583: logic__1583
-datapath__575: datapath__575
-reg__773: reg__773
-logic__3326: logic__3326
-logic__8049: logic__8049
-reg__1004: reg__1004
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__32: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__33: datapath__33
-logic__9129: logic__9129
-datapath__340: datapath__340
-reg__943: reg__943
-case__878: case__878
-logic__230: logic__230
-logic__625: logic__625
-dsp48e1__36: dsp48e1__36
-case__570: case__570
-logic__5362: logic__5362
-case__849: case__849
-logic__3537: logic__3537
-case__471: case__471
-datapath__451: datapath__451
-logic__4163: logic__4163
-logic__4389: logic__4389
-reg__125: reg__125
-logic: logic
-logic__4789: logic__4789
-logic__9566: logic__9566
-logic__3892: logic__3892
-reg__1613: reg__124
-logic__6668: logic__6668
-logic__9159: logic__9159
-reg__40: reg__40
-logic__9458: logic__9458
-logic__5149: logic__5149
-datapath__487: datapath__487
-logic__9355: logic__9355
-datapath__169: datapath__169
-datapath__154: datapath__154
-reg__446: reg__446
-reg__417: reg__417
-logic__5856: logic__5856
-case__462: case__462
-case__1148: case__1148
-reg__1000: reg__1000
-logic__1304: logic__1304
-reg__1160: reg__1160
-logic__2739: logic__2739
-case__160: case__160
-logic__8904: logic__8904
-reg__1591: reg__874
-logic__2620: logic__2620
-reg__1460: reg__1229
-case__929: case__929
-case__715: case__715
-reg__1280: reg__1280
-logic__3932: logic__3932
-logic__7228: logic__7228
-logic__9789: logic__2335
-logic__6153: logic__6153
-datapath__672: datapath__672
-logic__3313: logic__3313
-logic__8806: logic__8806
-datapath__438: datapath__438
-logic__6884: logic__6884
-logic__3327: logic__3327
-logic__8788: logic__8788
-logic__5535: logic__5535
-case__908: case__908
-logic__4415: logic__4415
-reg__1118: reg__1118
-reg__489: reg__489
-logic__9269: logic__9269
-case__563: case__563
-logic__4938: logic__4938
-reg__1062: reg__1062
-reg__557: reg__557
-muxpart__156: muxpart__156
-reg__983: reg__983
-logic__6759: logic__6759
-case__1400: case__1400
-reg__381: reg__381
-logic__959: logic__959
-logic__9801: logic__2295
-case__1761: case__728
-muxpart__381: muxpart__381
-reg__903: reg__903
-case__194: case__194
-logic__7170: logic__7170
-fft_radix_2__parameterized0: fft_radix_2__parameterized0
-reg__782: reg__782
-logic__6768: logic__6768
-logic__3332: logic__3332
-logic__4968: logic__4968
-reg__1093: reg__1093
-logic__2438: logic__2438
-logic__7002: logic__7002
-logic__6906: logic__6906
-datapath__183: datapath__183
-datapath__122: datapath__122
-logic__4253: logic__4253
-case__1624: case__1624
-logic__1578: logic__1578
-case__244: case__244
-logic__4653: logic__4653
-reg__293: reg__293
-logic__6146: logic__6146
-case__1508: case__1508
-case__755: case__755
-logic__7915: logic__7915
-reg__380: reg__380
-logic__2521: logic__2521
-logic__3819: logic__3819
-case__1005: case__1005
-logic__7406: logic__7406
-logic__6855: logic__6855
-case__609: case__609
-case__231: case__231
-logic__602: logic__602
-logic__5404: logic__5404
-logic__2625: logic__2625
-datapath__189: datapath__189
-NCO_code: NCO_code
-logic__1788: logic__1788
-logic__1505: logic__1505
-case__280: case__280
-datapath__76: datapath__76
-logic__3588: logic__3588
-datapath__26: datapath__26
-logic__7231: logic__7231
-logic__4949: logic__4949
-case__1298: case__1298
-logic__3272: logic__3272
-case__196: case__196
-AsyncQueueSink_TLBundleD_a9d32s1k1z2u: AsyncQueueSink_TLBundleD_a9d32s1k1z2u
-reg__743: reg__743
-case__1575: case__1575
-ITLB: ITLB
-sync__9: sync
-logic__4082: logic__4082
-case__1542: case__1542
-logic__3557: logic__3557
-reg__1384: reg__1384
-logic__6348: logic__6348
-case__1167: case__1167
-logic__1609: logic__1609
-case__1799: case__1606
-case__1110: case__1110
-datapath__518: datapath__518
-logic__1780: logic__1780
-logic__1854: logic__1854
-reg__1157: reg__1157
-logic__9632: logic__3616
-logic__4598: logic__4598
-logic__1430: logic__1430
-logic__87: logic__87
-reg__719: reg__719
-reg__949: reg__949
-logic__1118: logic__1118
-reg__230: reg__230
-logic__3053: logic__3053
-logic__7831: logic__7831
-logic__7751: logic__7751
-case__855: case__855
-reg__167: reg__167
-logic__4264: logic__4264
-logic__3797: logic__3797
-case__887: case__887
-reg__970: reg__970
-logic__7895: logic__7895
-reg__973: reg__973
-logic__6147: logic__6147
-logic__2991: logic__2991
-logic__5485: logic__5485
-logic__6701: logic__6701
-logic__7466: logic__7466
-logic__7399: logic__7399
-datapath__585: datapath__585
-logic__3346: logic__3346
-logic__6531: logic__6531
-logic__8047: logic__8047
-addsub__9: addsub__4
-logic__6052: logic__6052
-logic__337: logic__337
-dsp48e1__35: dsp48e1__35
-logic__7376: logic__7376
-datapath__36: datapath__36
-reg__1021: reg__1021
-logic__1620: logic__1620
-logic__2813: logic__2813
-reg__1194: reg__1194
-logic__4915: logic__4915
-logic__7201: logic__7201
-logic__554: logic__554
-logic__9857: logic__2171
-reg__20: reg__20
-logic__7222: logic__7222
-logic__6817: logic__6817
-logic__9542: logic__9542
-logic__9824: logic__2244
-dsp48e1__24: dsp48e1__24
-reg__1014: reg__1014
-reg__838: reg__838
-reg__1452: reg__1336
-logic__8028: logic__8028
-logic__5441: logic__5441
-logic__4294: logic__4294
-muxpart__126: muxpart__126
-muxpart__23: muxpart__23
-ClockCrossingReg_w43: ClockCrossingReg_w43
-reg__1267: reg__1267
-logic__2648: logic__2648
-logic__8236: logic__8236
-case__477: case__477
-logic__5293: logic__5293
-case__458: case__458
-datapath__95: datapath__95
-reg__1111: reg__1111
-reg__867: reg__867
-logic__5094: logic__5094
-reg__1365: reg__1365
-reg__956: reg__956
-datapath__766: datapath__119
-case__671: case__671
-case__1679: case__1679
-reg__426: reg__426
-logic__6867: logic__6867
-logic__6338: logic__6338
-logic__2227: logic__2227
-logic__5886: logic__5886
-logic__1155: logic__1155
-logic__7275: logic__7275
-logic__1267: logic__1267
-logic__628: logic__628
-case__1168: case__1168
-logic__2129: logic__2129
-logic__611: logic__611
-muxpart__48: muxpart__48
-reg__45: reg__45
-case__388: case__388
-logic__6618: logic__6618
-logic__3340: logic__3340
-logic__3017: logic__3017
-logic__8059: logic__8059
-reg__1594: reg__874
-logic__3475: logic__3475
-logic__9971: logic__905
-case__1565: case__1565
-reg__351: reg__351
-logic__9208: logic__9208
-dsp48e1__42: dsp48e1__42
-muxpart__181: muxpart__181
-logic__6114: logic__6114
-logic__1246: logic__1246
-case__1634: case__1634
-logic__3028: logic__3028
-logic__6296: logic__6296
-datapath__190: datapath__190
-dsp48e1__13: dsp48e1__13
-logic__9370: logic__9370
-datapath__19: datapath__19
-reg__644: reg__644
-logic__1603: logic__1603
-logic__8281: logic__8281
-logic__9925: logic__6768
-case__161: case__161
-case__1709: case__1709
-logic__3447: logic__3447
-ram__2: ram__2
-reg__1295: reg__1295
-logic__1160: logic__1160
-logic__3321: logic__3321
-logic__5202: logic__5202
-case__899: case__899
-muxpart__63: muxpart__63
-reg__1544: reg__924
-logic__9954: logic__1126
-case__274: case__274
-reg__837: reg__837
-logic__6640: logic__6640
-logic__8030: logic__8030
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__22: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-datapath__246: datapath__246
-datapath__772: datapath__40
-case__915: case__915
-logic__9724: logic__2530
-keep__53: keep__10
-logic__5713: logic__5713
-logic__7538: logic__7538
-logic__3907: logic__3907
-logic__4577: logic__4577
-muxpart__343: muxpart__343
-logic__1638: logic__1638
-datapath__145: datapath__145
-keep__21: keep__14
-keep__27: keep__14
-reg__1397: reg__1397
-logic__4652: logic__4652
-logic__2534: logic__2534
-logic__7034: logic__7034
-logic__2094: logic__2094
-logic__9372: logic__9372
-reg__83: reg__83
-logic__1980: logic__1980
-logic__1294: logic__1294
-logic__9911: logic__9518
-logic__8864: logic__8864
-FPU__GB2: FPU__GB2
-case__963: case__963
-datapath__741: datapath__140
-logic__3611: logic__3611
-logic__2917: logic__2917
-reg__770: reg__770
-reg__139: reg__139
-datapath__466: datapath__466
-logic__9963: logic__1106
-datapath__590: datapath__590
-reg__514: reg__514
-muxpart__28: muxpart__28
-reg__901: reg__901
-datapath__491: datapath__491
-reg__1137: reg__1137
-logic__3804: logic__3804
-logic__5938: logic__5938
-logic__7711: logic__7711
-logic__9423: logic__9423
-reg__386: reg__386
-logic__2458: logic__2458
-case__288: case__288
-logic__9926: logic__6773
-logic__4413: logic__4413
-case__41: case__41
-logic__8070: logic__8070
-case__1101: case__1101
-logic__5410: logic__5410
-counter__17: counter__17
-reg__754: reg__754
-datapath__507: datapath__507
-reg__699: reg__699
-cordic_atan_one_stage: cordic_atan_one_stage
-reg__57: reg__57
-logic__7111: logic__7111
-logic__1982: logic__1982
-logic__9397: logic__9397
-datapath__371: datapath__371
-case__310: case__310
-case__426: case__426
-case__746: case__746
-logic__7212: logic__7212
-case__543: case__543
-logic__4205: logic__4205
-keep__23: keep__15
-logic__331: logic__331
-logic__7263: logic__7263
-case__711: case__711
-reg__938: reg__938
-reg__708: reg__708
-logic__5958: logic__5958
-logic__6009: logic__6009
-case__109: case__109
-logic__7364: logic__7364
-logic__3870: logic__3870
-logic__2434: logic__2434
-logic__661: logic__661
-reg__968: reg__968
-muxpart__377: muxpart__377
-reg__1246: reg__1246
-case__1259: case__1259
-case__27: case__27
-logic__3246: logic__3246
-logic__9785: logic__2353
-logic__248: logic__248
-case__14: case__14
-reg__992: reg__992
-logic__6763: logic__6763
-logic__1804: logic__1804
-logic__5944: logic__5944
-logic__1965: logic__1965
-logic__9189: logic__9189
-logic__7837: logic__7837
-logic__3032: logic__3032
-reg__946: reg__946
-logic__1131: logic__1131
-logic__754: logic__754
-logic__5305: logic__5305
-case__586: case__586
-case__1299: case__1299
-logic__6344: logic__6344
-muxpart__54: muxpart__54
-datapath__548: datapath__548
-datapath__441: datapath__441
-case__1807: case__304
-muxpart__345: muxpart__345
-logic__2046: logic__2046
-logic__1573: logic__1573
-logic__8874: logic__8874
-ram_2x99: ram_2x99
-case__389: case__389
-ram__7: ram__7
-reg__18: reg__18
-logic__1535: logic__1535
-logic__1086: logic__1086
-reg__632: reg__632
-logic__4425: logic__4425
-logic__3946: logic__3946
-case__126: case__126
-case__1753: case__658
-logic__3734: logic__3734
-logic__3886: logic__3886
-case__181: case__181
-reg__623: reg__623
-logic__2422: logic__2422
-reg__106: reg__106
-logic__934: logic__934
-logic__854: logic__854
-logic__1608: logic__1608
-logic__7684: logic__7684
-reg__613: reg__613
-logic__9787: logic__2347
-logic__6140: logic__6140
-logic__3060: logic__3060
-logic__4559: logic__4559
-TLFragmenter_FPGAUART: TLFragmenter_FPGAUART
-case__132: case__132
-case__708: case__708
-datapath__73: datapath__73
-reg__707: reg__707
-reg__238: reg__238
-logic__1524: logic__1524
-reg__133: reg__133
-logic__1988: logic__1988
-muxpart__378: muxpart__378
-logic__259: logic__259
-case__1340: case__1340
-logic__9330: logic__9330
-reg__1041: reg__1041
-reg__1272: reg__1272
-logic__9628: logic__3620
-reg__561: reg__561
-case__648: case__648
-gray_to_binary__3: gray_to_binary
-logic__9667: logic__4555
-case__1026: case__1026
-spill_register: spill_register
-logic__3657: logic__3657
-case__633: case__633
-logic__250: logic__250
-keep__3: keep__3
-logic__1840: logic__1840
-reg__178: reg__178
-case__327: case__327
-reg__1161: reg__1161
-case__1180: case__1180
-case__871: case__871
-reg__913: reg__913
-TLBuffer_a14d64s2k1z4u: TLBuffer_a14d64s2k1z4u
-case__1106: case__1106
-logic__7116: logic__7116
-logic__6871: logic__6871
-reg__1117: reg__1117
-logic__2414: logic__2414
-logic__5409: logic__5409
-datapath__292: datapath__292
-case__158: case__158
-logic__9673: logic__4532
-reg__486: reg__486
-datapath__271: datapath__271
-datapath__15: datapath__15
-reg__345: reg__345
-logic__4468: logic__4468
-reg__1052: reg__1052
-reg__383: reg__383
-logic__1733: logic__1733
-logic__3005: logic__3005
-logic__7086: logic__7086
-case__799: case__799
-logic__9529: logic__9529
-logic__3123: logic__3123
-logic__8400: logic__8400
-logic__5960: logic__5960
-logic__2433: logic__2433
-logic__5198: logic__5198
-case__595: case__595
-datapath__251: datapath__251
-reg__1416: reg__1416
-logic__1001: logic__1001
-AsyncValidSync__4: AsyncValidSync
-logic__8508: logic__8508
-logic__6711: logic__6711
-muxpart__210: muxpart__210
-case__229: case__229
-logic__2641: logic__2641
-muxpart__24: muxpart__24
-datapath__500: datapath__500
-logic__8819: logic__8819
-datapath__309: datapath__309
-case__1685: case__1685
-reg__100: reg__100
-case__1770: case__521
-logic__3832: logic__3832
-logic__3119: logic__3119
-logic__6055: logic__6055
-datapath__396: datapath__396
-dsp48e1__19: dsp48e1__19
-reg__409: reg__409
-case__682: case__682
-logic__4404: logic__4404
-acq_ca_gen: acq_ca_gen
-reg__363: reg__363
-logic__9158: logic__9158
-logic__9090: logic__9090
-rom__7: rom__7
-reg__513: reg__513
-reg__947: reg__947
-case__1285: case__1285
-logic__7696: logic__7696
-logic__5375: logic__5375
-case__1192: case__1192
-logic__4476: logic__4476
-logic__2553: logic__2553
-reg__401: reg__401
-datapath__424: datapath__424
-reg__1242: reg__1242
-case__1008: case__1008
-logic__9622: logic__3635
-AsyncResetRegVec_w1_i0__2: AsyncResetRegVec_w1_i0
-logic__9261: logic__9261
-logic__771: logic__771
-logic__9661: logic__4561
-case__625: case__625
-reg__1383: reg__1383
-reg__1482: reg__924
-case__895: case__895
-logic__2214: logic__2214
-logic__1580: logic__1580
-datapath__372: datapath__372
-logic__1413: logic__1413
-logic__3070: logic__3070
-logic__2001: logic__2001
-logic__9771: logic__2395
-logic__6754: logic__6754
-logic__6957: logic__6957
-logic__2777: logic__2777
-logic__3855: logic__3855
-datapath__45: datapath__45
-logic__9152: logic__9152
-logic__5207: logic__5207
-logic__9973: logic__900
-logic__5055: logic__5055
-datapath__483: datapath__483
-case__1481: case__1481
-datapath__285: datapath__285
-logic__2769: logic__2769
-logic__1610: logic__1610
-logic__7300: logic__7300
-logic__9698: logic__2492
-case__1073: case__1073
-reg__697: reg__697
-PMPChecker_s2: PMPChecker_s2
-reg__1222: reg__1222
-reg__609: reg__609
-logic__9100: logic__9100
-reg__546: reg__546
-case__577: case__577
-datapath__80: datapath__80
-logic__2476: logic__2476
-case__1210: case__1210
-logic__9505: logic__9505
-datapath__412: datapath__412
-logic__7423: logic__7423
-logic__1593: logic__1593
-logic__4417: logic__4417
-logic__612: logic__612
-logic__7960: logic__7960
-logic__935: logic__935
-logic__2602: logic__2602
-reg__1209: reg__1209
-logic__3536: logic__3536
-logic__9565: logic__9565
-reg__601: reg__601
-datapath__645: datapath__645
-logic__5296: logic__5296
-logic__3613: logic__3613
-case__188: case__188
-logic__140: logic__140
-logic__8274: logic__8274
-logic__824: logic__824
-logic__4651: logic__4651
-reg__972: reg__972
-logic__3513: logic__3513
-datapath__554: datapath__554
-logic__1784: logic__1784
-reg__444: reg__444
-muxpart__383: muxpart__383
-logic__2090: logic__2090
-reg__312: reg__312
-logic__7045: logic__7045
-reg__187: reg__187
-reg__856: reg__856
-reg__1585: reg__925
-logic__1334: logic__1334
-logic__3717: logic__3717
-case__596: case__596
-keep__16: keep__16
-muxpart__207: muxpart__207
-logic__5119: logic__5119
-logic__2143: logic__2143
-logic__3429: logic__3429
-case__779: case__779
-logic__4104: logic__4104
-datapath__535: datapath__535
-logic__1623: logic__1623
-muxpart__72: muxpart__72
-datapath__308: datapath__308
-double_ff_syn__5: double_ff_syn
-logic__4029: logic__4029
-reg__540: reg__540
-logic__4095: logic__4095
-case__1143: case__1143
-logic__9920: logic__6773
-datapath__213: datapath__213
-datapath__166: datapath__166
-case__461: case__461
-logic__6917: logic__6917
-reg__896: reg__896
-muxpart__200: muxpart__200
-logic__6939: logic__6939
-logic__4298: logic__4298
-logic__5041: logic__5041
-case__1665: case__1665
-case__529: case__529
-case__1269: case__1269
-datapath__446: datapath__446
-logic__9518: logic__9518
-case__466: case__466
-double_ff_syn__1: double_ff_syn
-logic__9273: logic__9273
-reg__886: reg__886
-reg__248: reg__248
-logic__7022: logic__7022
-logic__6877: logic__6877
-logic__6796: logic__6796
-logic__8792: logic__8792
-reg__1003: reg__1003
-reg__208: reg__208
-logic__9886: logic__9100
-logic__2382: logic__2382
-logic__4837: logic__4837
-reg__745: reg__745
-reg__1104: reg__1104
-logic__8673: logic__8673
-muxpart__360: muxpart__360
-case__729: case__729
-case__879: case__879
-logic__9014: logic__9014
-logic__5619: logic__5619
-logic__8171: logic__8171
-logic__254: logic__254
-reg__682: reg__682
-logic__1309: logic__1309
-case__706: case__706
-logic__1239: logic__1239
-reg__520: reg__520
-logic__5991: logic__5991
-reg__150: reg__150
-logic__4181: logic__4181
-logic__7559: logic__7559
-case__1505: case__1505
-logic__1352: logic__1352
-logic__997: logic__997
-logic__834: logic__834
-logic__6083: logic__6083
-reg__1141: reg__1141
-datapath__313: datapath__313
-datapath__678: datapath__678
-muxpart__32: muxpart__32
-case__490: case__490
-logic__1992: logic__1992
-logic__1930: logic__1930
-logic__9385: logic__9385
-logic__4196: logic__4196
-logic__1019: logic__1019
-reg__1421: reg__1421
-logic__3699: logic__3699
-logic__1276: logic__1276
-case__7: case__7
-logic__3853: logic__3853
-case__896: case__896
-reg__1037: reg__1037
-reg__897: reg__897
-datapath__341: datapath__341
-case__475: case__475
-datapath__402: datapath__402
-logic__8056: logic__8056
-logic__7622: logic__7622
-logic__2243: logic__2243
-muxpart__12: muxpart__12
-case__1009: case__1009
-logic__1977: logic__1977
-logic__5018: logic__5018
-reg__1317: reg__1317
-logic__6951: logic__6951
-case__463: case__463
-reg__188: reg__188
-logic__1080: logic__1080
-logic__750: logic__750
-reg__509: reg__509
-logic__1755: logic__1755
-reg__1258: reg__1258
-logic__5601: logic__5601
-datapath__683: datapath__683
-reg__739: reg__739
-logic__5049: logic__5049
-logic__5279: logic__5279
-reg__1313: reg__1313
-reg__1344: reg__1344
-logic__6948: logic__6948
-logic__2650: logic__2650
-logic__7093: logic__7093
-RoundAnyRawFNToRecFN: RoundAnyRawFNToRecFN
-reg__1244: reg__1244
-case__1398: case__1398
-reg__1067: reg__1067
-muxpart__237: muxpart__237
-case__504: case__504
-muxpart__41: muxpart__41
-RoundRawFNToRecFN: RoundRawFNToRecFN
-logic__9851: logic__2185
-logic__173: logic__173
-logic__1273: logic__1273
-case__1617: case__1617
-reg__28: reg__28
-logic__288: logic__288
-case__685: case__685
-logic__3850: logic__3850
-logic__8966: logic__8966
-logic__3050: logic__3050
-reg__85: reg__85
-logic__5428: logic__5428
-case__970: case__970
-addsub__3: addsub__3
-logic__7521: logic__7521
-case__1541: case__1541
-reg__1467: reg__1087
-datapath__644: datapath__644
-logic__9916: logic__6773
-reg__1399: reg__1399
-case__1288: case__1288
-logic__9709: logic__2582
-logic__3245: logic__3245
-logic__6904: logic__6904
-datapath__348: datapath__348
-datapath__164: datapath__164
-case__112: case__112
-case__485: case__485
-reg__389: reg__389
-logic__5681: logic__5681
-logic__1234: logic__1234
-logic__2375: logic__2375
-logic__6811: logic__6811
-LevelGateway__9: LevelGateway
-case__407: case__407
-logic__5796: logic__5796
-logic__5551: logic__5551
-case__186: case__186
-case__329: case__329
-logic__3039: logic__3039
-logic__2370: logic__2370
-case__982: case__982
-datapath__685: datapath__685
-logic__4130: logic__4130
-case__995: case__995
-reg__1105: reg__1105
-case__325: case__325
-case__228: case__228
-case__1479: case__1479
-logic__2649: logic__2649
-case__1532: case__1532
-reg__1068: reg__1068
-case__640: case__640
-logic__4250: logic__4250
-logic__2096: logic__2096
-logic__4520: logic__4520
-logic__4206: logic__4206
-logic__4051: logic__4051
-logic__3930: logic__3930
-reg__298: reg__298
-Queue1_TLBundleA_a14d64s2k1z4u: Queue1_TLBundleA_a14d64s2k1z4u
-logic__844: logic__844
-datapath__484: datapath__484
-reg__622: reg__622
-logic__5547: logic__5547
-logic__8940: logic__8940
-reg__976: reg__976
-logic__7389: logic__7389
-logic__8353: logic__8353
-datapath__668: datapath__668
-logic__8683: logic__8683
-logic__9901: logic__8884
-reg__488: reg__488
-reg__147: reg__147
-datapath__423: datapath__423
-case__1585: case__1585
-reg__268: reg__268
-case__1439: case__1439
-logic__1671: logic__1671
-datapath__119: datapath__119
-logic__5229: logic__5229
-logic__5520: logic__5520
-ClockGroupAggregator_cbus: ClockGroupAggregator_cbus
-logic__604: logic__604
-reg__890: reg__890
-reg__1276: reg__1276
-logic__4786: logic__4786
-case__1391: case__1391
-logic__4123: logic__4123
-logic__9017: logic__9017
-logic__6671: logic__6671
-reg__1354: reg__1354
-reg__862: reg__862
-case__643: case__643
-case__1620: case__1620
-logic__9813: logic__2271
-counter__13: counter__13
-case__415: case__415
-reg__346: reg__346
-reg__965: reg__965
-logic__6874: logic__6874
-logic__1416: logic__1416
-datapath__697: datapath__697
-reg__990: reg__990
-logic__1022: logic__1022
-case__802: case__802
-case__1440: case__1440
-logic__9825: logic__2243
-datapath__129: datapath__129
-logic__5533: logic__5533
-case__1165: case__1165
-logic__1042: logic__1042
-reg__1175: reg__1175
-case__1342: case__1342
-reg__840: reg__840
-case__642: case__642
-reg__1178: reg__1178
-logic__8951: logic__8951
-datapath__333: datapath__333
-logic__112: logic__112
-reg__162: reg__162
-logic__3619: logic__3619
-logic__9243: logic__9243
-reg__97: reg__97
-datapath__272: datapath__272
-case__190: case__190
-logic__393: logic__393
-reg__1092: reg__1092
-case__221: case__221
-logic__7270: logic__7270
-logic__1013: logic__1013
-reg__250: reg__250
-case__873: case__873
-case__938: case__938
-logic__8810: logic__8810
-reg__474: reg__474
-logic__266: logic__266
-logic__7558: logic__7558
-case__1561: case__1561
-logic__6643: logic__6643
-FixedClockBroadcast_1__1: FixedClockBroadcast_1
-logic__9889: logic__9089
-TLXbar_pbus_out_i1_o3_a29d64s2k1z3u: TLXbar_pbus_out_i1_o3_a29d64s2k1z3u
-case__1663: case__1663
-logic__1078: logic__1078
-datapath__10: datapath__10
-logic__9461: logic__9461
-case__716: case__716
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__20: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__895: logic__895
-case__725: case__725
-case__1120: case__1120
-logic__1018: logic__1018
-reg__885: reg__885
-logic__2461: logic__2461
-logic__9823: logic__2245
-IntXbar_i1_o1: IntXbar_i1_o1
-logic__3860: logic__3860
-logic__5200: logic__5200
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__18: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__8330: logic__8330
-TLBuffer_a32d64s2k1z3u: TLBuffer_a32d64s2k1z3u
-datapath__544: datapath__544
-logic__6080: logic__6080
-reg__1300: reg__1300
-case__259: case__259
-reg__483: reg__483
-case__695: case__695
-AsyncResetSynchronizerShiftReg_w1_d3_i0__11: AsyncResetSynchronizerShiftReg_w1_d3_i0
-muxpart__77: muxpart__77
-case__1091: case__1091
-reg__703: reg__703
-case__1721: case__1721
-case__954: case__954
-rom: rom
-case__691: case__691
-logic__9953: logic__1127
-reg__1347: reg__1347
-reg__15: reg__15
-logic__2862: logic__2862
-logic__3025: logic__3025
-logic__3178: logic__3178
-logic__5600: logic__5600
-logic__5549: logic__5549
-reg__1234: reg__1234
-logic__7393: logic__7393
-muxpart__209: muxpart__209
-reg__1485: reg__924
-logic__9902: logic__8883
-logic__4888: logic__4888
-logic__1454: logic__1454
-datapath__378: datapath__378
-muxpart__37: muxpart__37
-case__707: case__707
-datapath__101: datapath__101
-case__1363: case__1363
-logic__3695: logic__3695
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__20: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__774: reg__774
-case__890: case__890
-case__352: case__352
-datapath__368: datapath__368
-case__1741: case__1741
-logic__8412: logic__8412
-logic__5534: logic__5534
-logic__8472: logic__8472
-logic__6172: logic__6172
-rockettile_icache_data_arrays_512x32__1: rockettile_icache_data_arrays_512x32
-logic__3788: logic__3788
-datapath__709: datapath__709
-logic__8934: logic__8934
-logic__4646: logic__4646
-muxpart__46: muxpart__46
-case__1390: case__1390
-muxpart__232: muxpart__232
-logic__9733: logic__2510
-PMPChecker_s3: PMPChecker_s3
-case__610: case__610
-reg__605: reg__605
-logic__4560: logic__4560
-case__1774: case__517
-logic__2031: logic__2031
-logic__9618: logic__3643
-logic__9763: logic__2427
-reg__34: reg__34
-logic__200: logic__200
-logic__8931: logic__8931
-logic__4309: logic__4309
-AsyncValidSync__13: AsyncValidSync
-muxpart__153: muxpart__153
-logic__9331: logic__9331
-case__1040: case__1040
-logic__1389: logic__1389
-logic__6154: logic__6154
-datapath__176: datapath__176
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__16: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__49: case__49
-logic__686: logic__686
-case__1081: case__1081
-case__1727: case__1727
-logic__6596: logic__6596
-logic__1670: logic__1670
-case__1336: case__1336
-reg__543: reg__543
-reg__508: reg__508
-logic__4782: logic__4782
-logic__7813: logic__7813
-case__1286: case__1286
-logic__915: logic__915
-case__925: case__925
-case__242: case__242
-case__738: case__738
-logic__9726: logic__2521
-logic__5155: logic__5155
-logic__7621: logic__7621
-case__311: case__311
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__19: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-datapath__613: datapath__613
-case__105: case__105
-logic__3004: logic__3004
-logic__650: logic__650
-datapath__735: datapath__264
-reg__276: reg__276
-case__523: case__523
-case__809: case__809
-logic__3329: logic__3329
-case__1534: case__1534
-case__736: case__736
-case__1252: case__1252
-logic__1526: logic__1526
-reg__1393: reg__1393
-reg__148: reg__148
-logic__982: logic__982
-reg__500: reg__500
-case__667: case__667
-logic__4785: logic__4785
-reg__1284: reg__1284
-datapath__485: datapath__485
-logic__9679: logic__4511
-case__319: case__319
-datapath__360: datapath__360
-case__115: case__115
-TLBuffer_a29d64s2k1z3u__1: TLBuffer_a29d64s2k1z3u
-case__1536: case__1536
-logic__9772: logic__2394
-logic__15: logic__15
-logic__825: logic__825
-reg__1515: reg__926
-muxpart__172: muxpart__172
-case__224: case__224
-logic__7192: logic__7192
-logic__9803: logic__2293
-reg__1026: reg__1026
-reg__1420: reg__1420
-logic__1740: logic__1740
-case__785: case__785
-logic__1009: logic__1009
-logic__2519: logic__2519
-logic__9590: logic__9590
-case__1646: case__1646
-logic__9802: logic__2294
-logic__2016: logic__2016
-counter__32: counter__32
-logic__9607: logic__9607
-case__448: case__448
-case__928: case__928
-logic__3531: logic__3531
-reg__827: reg__827
-logic__4732: logic__4732
-logic__59: logic__59
-reg__1114: reg__1114
-reg__78: reg__78
-case__616: case__616
-logic__8276: logic__8276
-datapath__470: datapath__470
-reg__355: reg__355
-muxpart__40: muxpart__40
-logic__7939: logic__7939
-case__398: case__398
-case__349: case__349
-reg__105: reg__105
-logic__4402: logic__4402
-counter__22: counter__22
-case__1760: case__729
-logic__502: logic__502
-reg__679: reg__679
-reg__1320: reg__1320
-datapath__661: datapath__661
-TLBuffer_a29d64s2k1z3u: TLBuffer_a29d64s2k1z3u
-logic__2638: logic__2638
-logic__7100: logic__7100
-reg__1218: reg__1218
-logic__2148: logic__2148
-keep__41: keep__15
-logic__5611: logic__5611
-logic__8348: logic__8348
-logic__9903: logic__8882
-logic__1214: logic__1214
-datapath__270: datapath__270
-reg__722: reg__722
-reg__853: reg__853
-logic__2788: logic__2788
-case__482: case__482
-logic__1927: logic__1927
-case__627: case__627
-reg__1011: reg__1011
-logic__4848: logic__4848
-case__996: case__996
-logic__4532: logic__4532
-datapath__43: datapath__43
-logic__2226: logic__2226
-logic__3510: logic__3510
-logic__9236: logic__9236
-logic__8196: logic__8196
-reg__643: reg__643
-logic__3225: logic__3225
-logic__1876: logic__1876
-datapath__753: datapath__673
-datapath__287: datapath__287
-logic__9268: logic__9268
-logic__6988: logic__6988
-logic__8579: logic__8579
-logic__7187: logic__7187
-logic__2353: logic__2353
-logic__2021: logic__2021
-logic__4427: logic__4427
-logic__9193: logic__9193
-reg__510: reg__510
-logic__8504: logic__8504
-datapath__322: datapath__322
-reg__747: reg__747
-case__1543: case__1543
-case__1556: case__1556
-logic__3315: logic__3315
-reg__25: reg__25
-logic__7348: logic__7348
-logic__792: logic__792
-logic__1637: logic__1637
-muxpart__158: muxpart__158
-logic__9690: logic__2516
-case__1264: case__1264
-logic__4465: logic__4465
-reg__1268: reg__1268
-reg__1546: reg__925
-case__283: case__283
-case__664: case__664
-case__767: case__767
-case__503: case__503
-logic__9891: logic__9085
-case__690: case__690
-reg__89: reg__89
-logic__8043: logic__8043
-TLXbar_pbus_in_i1_o1_a29d64s2k1z3u: TLXbar_pbus_in_i1_o1_a29d64s2k1z3u
-logic__133: logic__133
-reg__763: reg__763
-reg__933: reg__933
-logic__6682: logic__6682
-case__26: case__26
-logic__9157: logic__9157
-datapath__367: datapath__367
-case__931: case__931
-twiddle_ram: twiddle_ram
-case__509: case__509
-reg__1483: reg__926
-reg__804: reg__804
-logic__6092: logic__6092
-case__212: case__212
-logic__1197: logic__1197
-logic__9665: logic__4557
-reg__1414: reg__1414
-case__450: case__450
-logic__222: logic__222
-case__1486: case__1486
-case__528: case__528
-reg__1381: reg__1381
-logic__2387: logic__2387
-reg__597: reg__597
-logic__4319: logic__4319
-logic__512: logic__512
-logic__8066: logic__8066
-logic__2218: logic__2218
-reg__664: reg__664
-reg__1303: reg__1303
-reg__1097: reg__1097
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__7: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__6030: logic__6030
-logic__9830: logic__2232
-logic__9046: logic__9046
-case__1622: case__1622
-datapath__261: datapath__261
-case__17: case__17
-logic__9658: logic__4569
-logic__9558: logic__9558
-case__149: case__149
-datapath__148: datapath__148
-reg__1172: reg__1172
-reg__854: reg__854
-Queue2_TLBundleA_a29d64s2k1z3u__1: Queue2_TLBundleA_a29d64s2k1z3u
-logic__9967: logic__911
-logic__5459: logic__5459
-case__656: case__656
-datapath__339: datapath__339
-logic__5685: logic__5685
-logic__6024: logic__6024
-reg__1408: reg__1408
-logic__4101: logic__4101
-logic__1571: logic__1571
-case__1771: case__520
-reg__449: reg__449
-logic__4553: logic__4553
-case__621: case__621
-logic__727: logic__727
-logic__1186: logic__1186
-case__162: case__162
-case__495: case__495
-case__1330: case__1330
-datapath__420: datapath__420
-logic__5532: logic__5532
-reg__1565: reg__924
-logic__8501: logic__8501
-reg__456: reg__456
-logic__3035: logic__3035
-case__1675: case__1675
-logic__6497: logic__6497
-logic__9841: logic__2207
-reg__442: reg__442
-logic__8320: logic__8320
-logic__1572: logic__1572
-datapath__17: datapath__17
-logic__6722: logic__6722
-case__281: case__281
-datapath__366: datapath__366
-reg__1466: reg__1088
-logic__4098: logic__4098
-logic__2875: logic__2875
-datapath__325: datapath__325
-muxpart__167: muxpart__167
-case__1060: case__1060
-logic__910: logic__910
-logic__8326: logic__8326
-logic__6744: logic__6744
-logic__9561: logic__9561
-reg__788: reg__788
-logic__6676: logic__6676
-case__1243: case__1243
-logic__9115: logic__9115
-logic__9933: logic__6768
-logic__1576: logic__1576
-logic__9463: logic__9463
-logic__4361: logic__4361
-logic__107: logic__107
-case__1496: case__1496
-reg__809: reg__809
-muxpart__384: muxpart__384
-case__1714: case__1714
-logic__2295: logic__2295
-muxpart__295: muxpart__295
-logic__3618: logic__3618
-case__1037: case__1037
-logic__8680: logic__8680
-logic__767: logic__767
-datapath__344: datapath__344
-muxpart__180: muxpart__180
-reg__266: reg__266
-case__506: case__506
-logic__2394: logic__2394
-logic__8255: logic__8255
-case__653: case__653
-reg__1505: reg__924
-logic__6781: logic__6781
-logic__6691: logic__6691
-reg__168: reg__168
-logic__1083: logic__1083
-reg__1351: reg__1351
-case__1297: case__1297
-reg__1511: reg__924
-logic__4339: logic__4339
-logic__9780: logic__2370
-case__1221: case__1221
-logic__2244: logic__2244
-logic__5935: logic__5935
-CompareRecFN: CompareRecFN
-case__122: case__122
-case__468: case__468
-ResetCatchAndSync_d3__3: ResetCatchAndSync_d3
-logic__5246: logic__5246
-case__557: case__557
-logic__5985: logic__5985
-reg__501: reg__501
-logic__3002: logic__3002
-logic__6632: logic__6632
-logic__9616: logic__3649
-rom__3: rom__3
-logic__5264: logic__5264
-logic__3013: logic__3013
-counter__12: counter__12
-datapath__506: datapath__506
-logic__1136: logic__1136
-dsp48e1__11: dsp48e1__11
-logic__9700: logic__2486
-logic__5628: logic__5628
-reg__547: reg__547
-logic__5487: logic__5487
-reg__831: reg__831
-logic__8970: logic__8970
-logic__1038: logic__1038
-logic__804: logic__804
-datapath__547: datapath__547
-case__597: case__597
-logic__3616: logic__3616
-logic__3794: logic__3794
-logic__4521: logic__4521
-logic__1719: logic__1719
-logic__8922: logic__8922
-logic__7227: logic__7227
-logic__1201: logic__1201
-case__872: case__872
-logic__1531: logic__1531
-logic__4948: logic__4948
-logic__2782: logic__2782
-reg__1543: reg__925
-logic__8778: logic__8778
-logic__4419: logic__4419
-reg__536: reg__536
-case__1805: case__306
-logic__916: logic__916
-logic__6664: logic__6664
-logic__7004: logic__7004
-case__1512: case__1512
-logic__2203: logic__2203
-reg__997: reg__997
-keep__36: keep__14
-datapath__498: datapath__498
-logic__4749: logic__4749
-case__889: case__889
-logic__7528: logic__7528
-TLAsyncCrossingSource_a9d32s1k1z2u: TLAsyncCrossingSource_a9d32s1k1z2u
-dual_port_ram: dual_port_ram
-case__432: case__432
-logic__911: logic__911
-dual_port_bram__parameterized0: dual_port_bram__parameterized0
-logic__7757: logic__7757
-reg__1315: reg__1315
-AsyncResetRegVec_w1_i0: AsyncResetRegVec_w1_i0
-case__370: case__370
-case__1373: case__1373
-logic__4878: logic__4878
-case__1671: case__1671
-logic__2103: logic__2103
-reg__310: reg__310
-case__474: case__474
-logic__1633: logic__1633
-logic__1085: logic__1085
-reg__1259: reg__1259
-logic__2285: logic__2285
-datapath__555: datapath__555
-logic__1904: logic__1904
-logic__6565: logic__6565
-logic__3357: logic__3357
-reg__892: reg__892
-keep__20: keep__15
-reg__760: reg__760
-logic__389: logic__389
-logic__1181: logic__1181
-logic__930: logic__930
-case__630: case__630
-logic__5669: logic__5669
-case__361: case__361
-logic__5: logic__5
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__10: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__818: case__818
-logic__4649: logic__4649
-logic__7247: logic__7247
-logic__9299: logic__9299
-logic__2948: logic__2948
-logic__9915: logic__8196
-case__313: case__313
-logic__6081: logic__6081
-logic__6696: logic__6696
-reg__1380: reg__1380
-logic__662: logic__662
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__11: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__7774: logic__7774
-OptimizationBarrier_TLBEntryData: OptimizationBarrier_TLBEntryData
-case__583: case__583
-case__835: case__835
-logic__4783: logic__4783
-muxpart__163: muxpart__163
-logic__3175: logic__3175
-reg__842: reg__842
-reg__54: reg__54
-logic__6028: logic__6028
-logic__7363: logic__7363
-case__1029: case__1029
-logic__9846: logic__2196
-logic__5503: logic__5503
-case__544: case__544
-logic__1152: logic__1152
-logic__7319: logic__7319
-logic__4259: logic__4259
-reg__1569: reg__926
-reg__478: reg__478
-logic__5070: logic__5070
-case__164: case__164
-logic__5926: logic__5926
-datapath__427: datapath__427
-logic__1229: logic__1229
-case__1793: case__1612
-logic__7633: logic__7633
-logic__7211: logic__7211
-logic__9922: logic__6773
-case__842: case__842
-logic__6721: logic__6721
-logic__4315: logic__4315
-logic__7215: logic__7215
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__34: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__315: case__315
-counter__31: counter__31
-OptimizationBarrier_TLBEntryData__1: OptimizationBarrier_TLBEntryData
-logic__7358: logic__7358
-reg__912: reg__912
-reg__1087: reg__1087
-case__39: case__39
-reg__987: reg__987
-logic__1279: logic__1279
-logic__5955: logic__5955
-reg__846: reg__846
-nav_solve_timer: nav_solve_timer
-logic__9144: logic__9144
-logic__326: logic__326
-case__1256: case__1256
-case__1344: case__1344
-reg__61: reg__61
-sample_counter: sample_counter
-butterfly__parameterized0: butterfly__parameterized0
-logic__9636: logic__3612
-FixedClockBroadcast_5: FixedClockBroadcast_5
-logic__4256: logic__4256
-logic__235: logic__235
-case__905: case__905
-logic__1020: logic__1020
-case__1294: case__1294
-keep__42: keep__14
-reg__1528: reg__925
-case__1072: case__1072
-logic__2076: logic__2076
-logic__3262: logic__3262
-muxpart__241: muxpart__241
-logic__1729: logic__1729
-logic__3041: logic__3041
-logic__9341: logic__9341
-datapath__754: datapath__672
-case__1105: case__1105
-case__801: case__801
-logic__7221: logic__7221
-logic__3139: logic__3139
-datapath__222: datapath__222
-case__845: case__845
-logic__1027: logic__1027
-datapath__314: datapath__314
-logic__6720: logic__6720
-logic__8601: logic__8601
-case__1051: case__1051
-datapath__596: datapath__596
-datapath__357: datapath__357
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__12: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__1563: reg__926
-logic__2815: logic__2815
-logic__9457: logic__9457
-logic__161: logic__161
-reg__591: reg__591
-case__282: case__282
-logic__3716: logic__3716
-case__1596: case__1596
-case__203: case__203
-logic__1433: logic__1433
-datapath__570: datapath__570
-logic__5943: logic__5943
-logic__7440: logic__7440
-reg__1257: reg__1257
-LevelGateway__4: LevelGateway
-logic__6068: logic__6068
-case__765: case__765
-logic__9681: logic__2537
-reg__616: reg__616
-logic__717: logic__717
-datapath__528: datapath__528
-logic__9559: logic__9559
-logic__4368: logic__4368
-logic__9659: logic__4566
-logic__3294: logic__3294
-AsyncResetSynchronizerShiftReg_w1_d3_i0__4: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__4552: logic__4552
-logic__894: logic__894
-case__1191: case__1191
-logic__2552: logic__2552
-keep__7: keep__7
-reg__512: reg__512
-reg__1145: reg__1145
-TLXbar_cbus_in_i1_o1_a32d64s2k1z4u: TLXbar_cbus_in_i1_o1_a32d64s2k1z4u
-reg__1156: reg__1156
-case__337: case__337
-logic__5260: logic__5260
-datapath__16: datapath__16
-case__1338: case__1338
-logic__4998: logic__4998
-logic__6502: logic__6502
-logic__5857: logic__5857
-case__56: case__56
-dsp48e1__46: dsp48e1__46
-logic__838: logic__838
-logic__9828: logic__2236
-logic__1383: logic__1383
-logic__1099: logic__1099
-logic__9555: logic__9555
-logic__4418: logic__4418
-logic__8102: logic__8102
-datapath__243: datapath__243
-logic__3432: logic__3432
-logic__8089: logic__8089
-logic__9888: logic__9090
-reg__1115: reg__1115
-datapath__302: datapath__302
-logic__6989: logic__6989
-logic__890: logic__890
-reg__537: reg__537
-case__1504: case__1504
-logic__4200: logic__4200
-logic__7223: logic__7223
-datapath__207: datapath__207
-case__425: case__425
-reg__341: reg__341
-logic__1442: logic__1442
-logic__8809: logic__8809
-case__1046: case__1046
-reg__451: reg__451
-logic__396: logic__396
-reg__744: reg__744
-logic__4081: logic__4081
-AsyncValidSync__7: AsyncValidSync
-datapath__149: datapath__149
-logic__9924: logic__6773
-logic__6584: logic__6584
-logic__4508: logic__4508
-case__526: case__526
-logic__9052: logic__9052
-logic__9827: logic__2239
-logic__9415: logic__9415
-logic__7218: logic__7218
-case__479: case__479
-TLFragmenter_FPGAUART__1: TLFragmenter_FPGAUART
-reg__181: reg__181
-datapath__694: datapath__694
-rom__1: rom__1
-bootromClockSinkDomain: bootromClockSinkDomain
-logic__6507: logic__6507
-reg__559: reg__559
-logic__7763: logic__7763
-logic__1981: logic__1981
-case__362: case__362
-logic__2163: logic__2163
-logic__2402: logic__2402
-logic__5617: logic__5617
-datapath__545: datapath__545
-logic__7371: logic__7371
-logic__7174: logic__7174
-logic__3501: logic__3501
-logic__8033: logic__8033
-logic__8765: logic__8765
-logic__6060: logic__6060
-reg__400: reg__400
-case__478: case__478
-logic__6665: logic__6665
-logic__4787: logic__4787
-datapath__413: datapath__413
-datapath__620: datapath__620
-logic__4500: logic__4500
-datapath__42: datapath__42
-logic__1340: logic__1340
-reg__219: reg__219
-keep__29: keep__15
-logic__5710: logic__5710
-case__223: case__223
-case__581: case__581
-logic__5065: logic__5065
-muxpart__7: muxpart__7
-logic__1820: logic__1820
-logic__9881: logic__1294
-case__159: case__159
-case__150: case__150
-logic__7459: logic__7459
-logic__3426: logic__3426
-case__637: case__637
-reg__282: reg__282
-logic__7814: logic__7814
-case__1726: case__1726
-case__965: case__965
-reg__765: reg__765
-logic__2549: logic__2549
-logic__4349: logic__4349
-logic__8198: logic__8198
-case__1578: case__1578
-case__269: case__269
-datapath__108: datapath__108
-sync__8: sync
-case__1683: case__1683
-datapath__134: datapath__134
-logic__4614: logic__4614
-logic__6762: logic__6762
-TLInterconnectCoupler_pbus_to_gps: TLInterconnectCoupler_pbus_to_gps
-logic__6058: logic__6058
-logic__4942: logic__4942
-logic__4420: logic__4420
-logic__9956: logic__1124
-case__1431: case__1431
-logic__607: logic__607
-case__455: case__455
-logic__9936: logic__1598
-reg__455: reg__455
-reg__1056: reg__1056
-reg__1047: reg__1047
-reg__1142: reg__1142
-logic__6505: logic__6505
-logic__9842: logic__2206
-RoundAnyRawFNToRecFN_4: RoundAnyRawFNToRecFN_4
-logic__2761: logic__2761
-logic__7135: logic__7135
-TLInterconnectCoupler_pbus_to_fpga_uart__1: TLInterconnectCoupler_pbus_to_fpga_uart
-logic__4655: logic__4655
-logic__4573: logic__4573
-muxpart__213: muxpart__213
-logic__8218: logic__8218
-logic__1689: logic__1689
-case__1742: case__1742
-case__814: case__814
-logic__2910: logic__2910
-logic__2790: logic__2790
-logic__9145: logic__9145
-case__1147: case__1147
-reg__378: reg__378
-logic__6681: logic__6681
-case__791: case__791
-logic__7359: logic__7359
-reg__1457: reg__1229
-ram__11: ram__2
-reg__1247: reg__1247
-reg__367: reg__367
-logic__9781: logic__2367
-reg__1458: reg__1229
-reg__114: reg__114
-logic__6039: logic__6039
-logic__2430: logic__2430
-case__1020: case__1020
-datapath__560: datapath__560
-mult_46_15_61__1: mult_46_15_61
-reg__317: reg__317
-logic__8663: logic__8663
-logic__3793: logic__3793
-case__125: case__125
-reg__784: reg__784
-reg__1395: reg__1395
-reg__928: reg__928
-reg__628: reg__628
-datapath__415: datapath__415
-reg__316: reg__316
-logic__3709: logic__3709
-logic__303: logic__303
-logic__88: logic__88
-logic__1925: logic__1925
-datapath__296: datapath__296
-keep__13: keep__13
-TLInterconnectCoupler_cbus_to_plic: TLInterconnectCoupler_cbus_to_plic
-datapath__594: datapath__594
-logic__4499: logic__4499
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__9: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-Queue1_RegMapperInput_i9_m8: Queue1_RegMapperInput_i9_m8
-logic__2162: logic__2162
-reg__1226: reg__1226
-reg__1506: reg__926
-logic__7380: logic__7380
-datapath__170: datapath__170
-counter__26: counter__26
-reg__255: reg__255
-reg__1150: reg__1150
-datapath__407: datapath__407
-logic__9426: logic__9426
-TLInterconnectCoupler_fbus_from_debug_sb: TLInterconnectCoupler_fbus_from_debug_sb
-logic__5003: logic__5003
-logic__2206: logic__2206
-logic__9425: logic__9425
-case__927: case__927
-logic__3711: logic__3711
-case__431: case__431
-logic__6031: logic__6031
-reg__1587: reg__926
-counter__29: counter__29
-logic__4802: logic__4802
-case__447: case__447
-logic__4215: logic__4215
-datapath__102: datapath__102
-logic__3581: logic__3581
-reg__163: reg__163
-case__1616: case__1616
-logic__5424: logic__5424
-case__606: case__606
-logic__1443: logic__1443
-logic__1803: logic__1803
-reg__1155: reg__1155
-logic__5022: logic__5022
-case__753: case__753
-logic__8189: logic__8189
-logic__5457: logic__5457
-counter__16: counter__16
-case__1225: case__1225
-reg__1479: reg__924
-reg__1601: reg__240
-logic__2814: logic__2814
-acq_top: acq_top
-logic__9723: logic__2534
-logic__1499: logic__1499
-reg__1165: reg__1165
-reg__1406: reg__1406
-logic__9862: logic__2162
-case__40: case__40
-logic__870: logic__870
-case__1682: case__1682
-datapath__259: datapath__259
-tracking_wrapper: tracking_wrapper
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__30: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-CLINT: CLINT
-reg__709: reg__709
-reg__1075: reg__1075
-logic__1259: logic__1259
-reg__379: reg__379
-case__786: case__786
-muxpart__264: muxpart__264
-reg__1224: reg__1224
-logic__6677: logic__6677
-logic__4920: logic__4920
-logic__6027: logic__6027
-reg__549: reg__549
-logic__2064: logic__2064
-keep__19: keep__16
-datapath__242: datapath__242
-case__1749: case__663
-reg__22: reg__22
-logic__4690: logic__4690
-logic__2113: logic__2113
-logic__5929: logic__5929
-logic__7718: logic__7718
-logic__7271: logic__7271
-logic__1202: logic__1202
-datapath__65: datapath__65
-lock_detector: lock_detector
-logic__1822: logic__1822
-logic__3271: logic__3271
-Queue2_TLBundleA_a32d64s1k1z4u: Queue2_TLBundleA_a32d64s1k1z4u
-logic__1247: logic__1247
-logic__8560: logic__8560
-logic__8971: logic__8971
-logic__4493: logic__4493
-datapath__738: datapath__43
-logic__4350: logic__4350
-logic__4666: logic__4666
-reg__1349: reg__1349
-logic__4693: logic__4693
-logic__4006: logic__4006
-logic__9898: logic__8883
-case__694: case__694
-TLInterconnectCoupler_cbus_to_bootrom: TLInterconnectCoupler_cbus_to_bootrom
-logic__1874: logic__1874
-reg__477: reg__477
-logic__6599: logic__6599
-case__1619: case__1619
-sync__4: sync
-logic__196: logic__196
-reg__246: reg__246
-logic__9585: logic__9585
-case__127: case__127
-case__678: case__678
-case__638: case__638
-case__531: case__531
-logic__4129: logic__4129
-logic__2926: logic__2926
-logic__5526: logic__5526
-logic__5692: logic__5692
-case__1772: case__519
-case__32: case__32
-case__612: case__612
-reg__1292: reg__1292
-logic__4898: logic__4898
-logic__1847: logic__1847
-logic__9615: logic__3652
-reg__1025: reg__1025
-logic__1918: logic__1918
-datapath__595: datapath__595
-counter__3: counter__3
-case__1123: case__1123
-case__650: case__650
-logic__216: logic__216
-reg__780: reg__780
-logic__9647: logic__4594
-logic__7374: logic__7374
-reg__1122: reg__1122
-reg__1398: reg__1398
-logic__4351: logic__4351
-logic__5153: logic__5153
-case__1145: case__1145
-reg__1348: reg__1348
-logic__8496: logic__8496
-logic__5700: logic__5700
-logic__8925: logic__8925
-logic__2884: logic__2884
-logic__7238: logic__7238
-case__808: case__808
-logic__2068: logic__2068
-datapath__762: datapath__160
-logic__3030: logic__3030
-reg__588: reg__588
-logic__9044: logic__9044
-logic__5315: logic__5315
-logic__8325: logic__8325
-reg__481: reg__481
-logic__2730: logic__2730
-logic__5500: logic__5500
-case__412: case__412
-case__1079: case__1079
-reg__1507: reg__925
-case__494: case__494
-reg__245: reg__245
-case__591: case__591
-logic__6105: logic__6105
-datapath__87: datapath__87
-case__1325: case__1325
-reg__1373: reg__1373
-case__343: case__343
-reg__1192: reg__1192
-logic__3777: logic__3777
-logic__1737: logic__1737
-reg__1149: reg__1149
-logic__7954: logic__7954
-case__679: case__679
-logic__4496: logic__4496
-logic__8336: logic__8336
-case__702: case__702
-reg__366: reg__366
-logic__598: logic__598
-logic__8492: logic__8492
-logic__9368: logic__9368
-logic__4997: logic__4997
-logic__2137: logic__2137
-muxpart__68: muxpart__68
-logic__3498: logic__3498
-case__819: case__819
-datapath__468: datapath__468
-datapath__411: datapath__411
-reg__242: reg__242
-logic__4090: logic__4090
-logic__7456: logic__7456
-logic__9597: logic__9597
-reg__404: reg__404
-case__781: case__781
-reg__991: reg__991
-logic__6576: logic__6576
-keep__24: keep__14
-reg__1558: reg__925
-reg__1288: reg__1288
-case__1723: case__1723
-logic__8600: logic__8600
-case__204: case__204
-logic__8035: logic__8035
-case__1389: case__1389
-logic__4363: logic__4363
-logic__305: logic__305
-datapath__699: datapath__699
-logic__7274: logic__7274
-datapath__188: datapath__188
-logic__9897: logic__8884
-logic__4565: logic__4565
-reg__1198: reg__1198
-OptimizationBarrier_TLBEntryData__2: OptimizationBarrier_TLBEntryData
-logic__2517: logic__2517
-datapath__648: datapath__648
-datapath__228: datapath__228
-logic__2006: logic__2006
-logic__9958: logic__1118
-muxpart__376: muxpart__376
-datapath__521: datapath__521
-logic__6835: logic__6835
-logic__3569: logic__3569
-case__1564: case__1564
-datapath__41: datapath__41
-logic__9104: logic__9104
-logic__5887: logic__5887
-reg__218: reg__218
-reg__348: reg__348
-case__246: case__246
-logic__9004: logic__9004
-LevelGateway__6: LevelGateway
-case__1367: case__1367
-logic__4475: logic__4475
-logic__4141: logic__4141
-datapath__241: datapath__241
-reg__1070: reg__1070
-case__1290: case__1290
-logic__4277: logic__4277
-case__404: case__404
-reg__1557: reg__926
-logic__2169: logic__2169
-reg__608: reg__608
-logic__8369: logic__8369
-logic__283: logic__283
-datapath__171: datapath__171
-reg__692: reg__692
-logic__3795: logic__3795
-datapath__356: datapath__356
-case__209: case__209
-datapath__86: datapath__86
-logic__7425: logic__7425
-datapath__231: datapath__231
-reg__1129: reg__1129
-case__933: case__933
-case__721: case__721
-reg__197: reg__197
-reg__135: reg__135
-logic__1823: logic__1823
-case__331: case__331
-datapath__269: datapath__269
-rom__2: rom__2
-case__888: case__888
-reg__286: reg__286
-reg__567: reg__567
-logic__5508: logic__5508
-TLBuffer_a32d64s1k1z4u_1: TLBuffer_a32d64s1k1z4u_1
-muxpart__227: muxpart__227
-logic__2480: logic__2480
-AsyncResetSynchronizerShiftReg_w1_d3_i0__8: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__9525: logic__9525
-datapath__631: datapath__631
-logic__5414: logic__5414
-logic__5956: logic__5956
-reg__1009: reg__1009
-reg__522: reg__522
-datapath__258: datapath__258
-datapath__703: datapath__703
-AsyncResetSynchronizerShiftReg_w1_d3_i0__2: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__9396: logic__9396
-reg__1325: reg__1325
-logic__5439: logic__5439
-datapath__589: datapath__589
-case__1426: case__1426
-muxpart__10: muxpart__10
-logic__9045: logic__9045
-logic__3302: logic__3302
-logic__4561: logic__4561
-logic__5934: logic__5934
-logic__2077: logic__2077
-reg__143: reg__143
-logic__6104: logic__6104
-reg__979: reg__979
-case__330: case__330
-logic__8214: logic__8214
-logic__5187: logic__5187
-datapath__211: datapath__211
-logic__1665: logic__1665
-logic__3700: logic__3700
-logic__3425: logic__3425
-case__382: case__382
-logic__3751: logic__3751
-case__1156: case__1156
-reg__880: reg__880
-logic__6327: logic__6327
-logic__6163: logic__6163
-case__1509: case__1509
-datapath__587: datapath__587
-logic__9716: logic__2552
-logic__7308: logic__7308
-reg__473: reg__473
-case__1580: case__1580
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__11: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__1048: reg__1048
-AsyncValidSync__14: AsyncValidSync
-datapath__203: datapath__203
-reg__1191: reg__1191
-logic__5907: logic__5907
-logic__9848: logic__2190
-case__579: case__579
-logic__8815: logic__8815
-case__1484: case__1484
-case__817: case__817
-muxpart__166: muxpart__166
-logic__4164: logic__4164
-case__357: case__357
-logic__6747: logic__6747
-APBGpsBlock__GC0: APBGpsBlock__GC0
-logic__6961: logic__6961
-Queue2_TLBundleD_a29d64s2k1z3u__1: Queue2_TLBundleD_a29d64s2k1z3u
-reg__1592: reg__874
-case__705: case__705
-reg__252: reg__252
-case__257: case__257
-logic__2728: logic__2728
-logic__4791: logic__4791
-logic__5620: logic__5620
-logic__357: logic__357
-case__1087: case__1087
-case__350: case__350
-dsp48e1__28: dsp48e1__28
-case__724: case__724
-case__1231: case__1231
-datapath__37: datapath__37
-reg__702: reg__702
-logic__7447: logic__7447
-logic__7065: logic__7065
-logic__4414: logic__4414
-logic__6534: logic__6534
-logic__1347: logic__1347
-case__408: case__408
-logic__3497: logic__3497
-case__1222: case__1222
-datapath__495: datapath__495
-logic__6680: logic__6680
-logic__9722: logic__2537
-reg__1027: reg__1027
-logic__7361: logic__7361
-datapath__254: datapath__254
-reg__584: reg__584
-reg__1079: reg__1079
-case__1000: case__1000
-logic__148: logic__148
-logic__6155: logic__6155
-logic__2181: logic__2181
-AsyncValidSync__17: AsyncValidSync
-logic__4892: logic__4892
-logic__6918: logic__6918
-case__1375: case__1375
-AsyncQueueSource_TLBundleA_a9d32s1k1z2u: AsyncQueueSource_TLBundleA_a9d32s1k1z2u
-logic__9657: logic__4572
-reg__179: reg__179
-datapath__97: datapath__97
-logic__8185: logic__8185
-cos2x: cos2x
-reg__1539: reg__926
-logic__2055: logic__2055
-case__508: case__508
-case__1676: case__1676
-reg__1189: reg__1189
-twiddle_ram__1: twiddle_ram
-TilePRCIDomain__GC0: TilePRCIDomain__GC0
-datapath__695: datapath__695
-reg__687: reg__687
-reg__877: reg__877
-logic__6343: logic__6343
-logic__9511: logic__9511
-logic__9906: logic__8883
-logic__4758: logic__4758
-case__1088: case__1088
-reg__464: reg__464
-logic__9871: logic__917
-logic__8761: logic__8761
-case__599: case__599
-logic__4990: logic__4990
-logic__1288: logic__1288
-case__199: case__199
-case__182: case__182
-reg__1517: reg__924
-datapath__262: datapath__262
-DTLB__1: DTLB
-logic__7436: logic__7436
-case__524: case__524
-logic__4494: logic__4494
-reg__331: reg__331
-logic__9818: logic__2260
-logic__2032: logic__2032
-logic__826: logic__826
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__4: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__7044: logic__7044
-logic__1401: logic__1401
-logic__839: logic__839
-case__1485: case__1485
-logic__1527: logic__1527
-logic__4881: logic__4881
-muxpart__257: muxpart__257
-datapath__163: datapath__163
-case__1595: case__1595
-logic__1329: logic__1329
-logic__9644: logic__4617
-logic__7388: logic__7388
-logic__8219: logic__8219
-logic__5979: logic__5979
-logic__7413: logic__7413
-logic__2354: logic__2354
-case__46: case__46
-case__1195: case__1195
-reg__1426: reg__1426
-logic__752: logic__752
-reg__593: reg__593
-case__1687: case__1687
-logic__7122: logic__7122
-logic__956: logic__956
-case__263: case__263
-reg__1321: reg__1321
-case__254: case__254
-reg__640: reg__640
-case__1038: case__1038
-datapath__247: datapath__247
-logic__5240: logic__5240
-datapath__332: datapath__332
-logic__2138: logic__2138
-muxpart__184: muxpart__184
-logic__5417: logic__5417
-logic__2520: logic__2520
-muxpart__44: muxpart__44
-logic__2104: logic__2104
-logic__3061: logic__3061
-logic__7437: logic__7437
-reg__686: reg__686
-reg__39: reg__39
-reg__212: reg__212
-reg__893: reg__893
-logic__1423: logic__1423
-logic__5216: logic__5216
-datapath__395: datapath__395
-case__713: case__713
-case__955: case__955
-logic__5574: logic__5574
-logic__1111: logic__1111
-reg__285: reg__285
-logic__921: logic__921
-reg__1243: reg__1243
-logic__9791: logic__2333
-logic__6131: logic__6131
-logic__9262: logic__9262
-case__488: case__488
-logic__2275: logic__2275
-datapath__462: datapath__462
-case__505: case__505
-reg__226: reg__226
-logic__8183: logic__8183
-logic__7940: logic__7940
-logic__6764: logic__6764
-logic__7015: logic__7015
-logic__5201: logic__5201
-reg__1: reg__1
-case__452: case__452
-ram_2x77__2: ram_2x77
-logic__5052: logic__5052
-logic__4844: logic__4844
-logic__6043: logic__6043
-case__1090: case__1090
-reg__1434: reg__1434
-case__1502: case__1502
-logic__4506: logic__4506
-case__118: case__118
-datapath__114: datapath__114
-counter__8: counter__8
-case__856: case__856
-reg__961: reg__961
-logic__3560: logic__3560
-reg__62: reg__62
-logic__9575: logic__9575
-counter__6: counter__6
-logic__8438: logic__8438
-logic__3339: logic__3339
-logic__1064: logic__1064
-reg__1275: reg__1275
-case__1109: case__1109
-logic__4852: logic__4852
-logic__6715: logic__6715
-logic__3431: logic__3431
-logic__8337: logic__8337
-logic__7390: logic__7390
-logic__1538: logic__1538
-case__267: case__267
-case__1610: case__1610
-datapath__123: datapath__123
-case__572: case__572
-logic__9662: logic__4560
-datapath__743: datapath__138
-case__1027: case__1027
-case__918: case__918
-logic__9805: logic__2289
-logic__4152: logic__4152
-reg__1148: reg__1148
-logic__6658: logic__6658
-reg__900: reg__900
-logic__8172: logic__8172
-datapath__622: datapath__622
-logic__6615: logic__6615
-case__108: case__108
-logic__9346: logic__9346
-logic__3528: logic__3528
-case__1211: case__1211
-logic__84: logic__84
-datapath__524: datapath__524
-logic__1516: logic__1516
-muxpart__219: muxpart__219
-reg__11: reg__11
-logic__1896: logic__1896
-logic__1614: logic__1614
-logic__2954: logic__2954
-reg__544: reg__544
-case__151: case__151
-datapath__218: datapath__218
-datapath__633: datapath__633
-logic__2362: logic__2362
-case__216: case__216
-datapath__550: datapath__550
-logic__1936: logic__1936
-logic__6807: logic__6807
-rf_31x64: rf_31x64
-case__919: case__919
-logic__6520: logic__6520
-logic__1331: logic__1331
-logic__2407: logic__2407
-reg__942: reg__942
-datapath__181: datapath__181
-reg__1401: reg__1401
-logic__9800: logic__2302
-reg__115: reg__115
-spill_register_flushable: spill_register_flushable
-case__988: case__988
-logic__5128: logic__5128
-logic__7996: logic__7996
-logic__7444: logic__7444
-logic__8870: logic__8870
-logic__2007: logic__2007
-logic__6660: logic__6660
-reg__1578: reg__926
-case__1417: case__1417
-logic__3754: logic__3754
-case__385: case__385
-datapath__619: datapath__619
-case__1796: case__1609
-logic__4489: logic__4489
-logic__7402: logic__7402
-case__430: case__430
-logic__7984: logic__7984
-case__360: case__360
-reg__1310: reg__1310
-logic__4647: logic__4647
-datapath__103: datapath__103
-logic__6133: logic__6133
-ShiftQueue: ShiftQueue
-logic__4747: logic__4747
-logic__5901: logic__5901
-datapath__113: datapath__113
-case__135: case__135
-logic__5209: logic__5209
-logic__7001: logic__7001
-case__369: case__369
-logic__2449: logic__2449
-case__500: case__500
-logic__7460: logic__7460
-logic__1284: logic__1284
-reg__596: reg__596
-case__1239: case__1239
-datapath__629: datapath__629
-reg__756: reg__756
-case__975: case__975
-logic__7928: logic__7928
-case__875: case__875
-logic__5175: logic__5175
-logic__786: logic__786
-datapath__475: datapath__475
-reg__31: reg__31
-ram__8: ram__8
-fft_radix_2__parameterized1: fft_radix_2__parameterized1
-logic__3784: logic__3784
-logic__3099: logic__3099
-logic__4895: logic__4895
-logic__2778: logic__2778
-case__183: case__183
-logic__9530: logic__9530
-case__559: case__559
-logic__1890: logic__1890
-logic__5251: logic__5251
-logic__7870: logic__7870
-logic__9892: logic__9084
-reg__1481: reg__925
-logic__3477: logic__3477
-reg__786: reg__786
-muxpart__76: muxpart__76
-ClockCrossingReg_w15: ClockCrossingReg_w15
-reg__21: reg__21
-logic__7052: logic__7052
-reg__731: reg__731
-datapath__345: datapath__345
-logic__8345: logic__8345
-reg__1533: reg__926
-case__307: case__307
-case__1074: case__1074
-case__750: case__750
-muxpart__254: muxpart__254
-logic__898: logic__898
-case__631: case__631
-case__1369: case__1369
-TLXbar_fbus_i1_o1_a32d64s1k1z4u: TLXbar_fbus_i1_o1_a32d64s1k1z4u
-logic__9666: logic__4556
-logic__9069: logic__9069
-logic__7442: logic__7442
-logic__1855: logic__1855
-case__335: case__335
-logic__3236: logic__3236
-logic__9856: logic__2172
-case__838: case__838
-keep__39: keep__14
-logic__8267: logic__8267
-case__1763: case__726
-logic__8333: logic__8333
-muxpart__385: muxpart__385
-logic__2603: logic__2603
-logic__7126: logic__7126
-logic__3519: logic__3519
-logic__7: logic__7
-reg__817: reg__817
-case__222: case__222
-logic__3078: logic__3078
-case__1430: case__1430
-logic__3495: logic__3495
-logic__9739: logic__2492
-logic__733: logic__733
-logic__7083: logic__7083
-reg__906: reg__906
-reg__779: reg__779
-reg__338: reg__338
-logic__3003: logic__3003
-logic__1664: logic__1664
-datapath__151: datapath__151
-datapath__711: datapath__711
-logic__132: logic__132
-logic__5546: logic__5546
-logic__9613: logic__3657
-logic__61: logic__61
-logic__1931: logic__1931
-logic__9947: logic__1145
-AsyncResetSynchronizerShiftReg_w1_d3_i0__7: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__6592: logic__6592
-case__1024: case__1024
-reg__834: reg__834
-case__1048: case__1048
-logic__7006: logic__7006
-logic__4488: logic__4488
-case__1427: case__1427
-reg__1023: reg__1023
-logic__7910: logic__7910
-datapath__543: datapath__543
-case__18: case__18
-case__1190: case__1190
-datapath__765: datapath__120
-case__397: case__397
-muxpart__245: muxpart__245
-case__1160: case__1160
-logic__7207: logic__7207
-logic__2105: logic__2105
-logic__2294: logic__2294
-datapath__530: datapath__530
-case__841: case__841
-muxpart__244: muxpart__244
-case__553: case__553
-logic__9904: logic__8885
-logic__6931: logic__6931
-reg__172: reg__172
-logic__4908: logic__4908
-datapath__551: datapath__551
-logic__872: logic__872
-logic__4: logic__4
-reg__1214: reg__1214
-reg__1262: reg__1262
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__5: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__7152: logic__7152
-datapath__566: datapath__566
-logic__7181: logic__7181
-case__1614: case__1614
-logic__3209: logic__3209
-reg__542: reg__542
-case__119: case__119
-logic__7159: logic__7159
-case__409: case__409
-ram_2x78: ram_2x78
-datapath__104: datapath__104
-muxpart__266: muxpart__266
-logic__6733: logic__6733
-logic__9410: logic__9410
-reg__1366: reg__1366
-logic__6930: logic__6930
-logic__7900: logic__7900
-reg__1232: reg__1232
-logic__18: logic__18
-case__277: case__277
-case__881: case__881
-logic__6037: logic__6037
-case__987: case__987
-logic__5683: logic__5683
-reg__922: reg__922
-logic__2217: logic__2217
-muxpart__157: muxpart__157
-logic__134: logic__134
-logic__6611: logic__6611
-reset_synch: reset_synch
-logic__7407: logic__7407
-logic__9804: logic__2292
-case__1334: case__1334
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__3: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__673: reg__673
-reg__1604: reg__157
-logic__9021: logic__9021
-sync__2: sync
-reg__1106: reg__1106
-logic__9059: logic__9059
-logic__6621: logic__6621
-reg__185: reg__185
-reg__1471: reg__1089
-logic__3508: logic__3508
-reg__53: reg__53
-logic__2042: logic__2042
-case__243: case__243
-logic__7301: logic__7301
-logic__3514: logic__3514
-logic__2236: logic__2236
-logic__9467: logic__9467
-logic__9: logic__9
-eth_rf_genesys2: eth_rf_genesys2
-logic__8684: logic__8684
-case__131: case__131
-logic__7768: logic__7768
-case__1712: case__1712
-case__502: case__502
-logic__5919: logic__5919
-logic__7453: logic__7453
-logic__6805: logic__6805
-case__1594: case__1594
-logic__9387: logic__9387
-logic__8890: logic__8890
-reg__1615: reg__122
-logic__4937: logic__4937
-logic__5826: logic__5826
-logic__6802: logic__6802
-reg__189: reg__189
-reg__1010: reg__1010
-case__1529: case__1529
-logic__8188: logic__8188
-reg__955: reg__955
-logic__3298: logic__3298
-muxpart__52: muxpart__52
-logic__2029: logic__2029
-logic__3201: logic__3201
-datapath__492: datapath__492
-logic__4234: logic__4234
-logic__50: logic__50
-logic__1875: logic__1875
-reg__939: reg__939
-reg__466: reg__466
-logic__3268: logic__3268
-reg__203: reg__203
-logic__5253: logic__5253
-dsp48e1__29: dsp48e1__29
-logic__7786: logic__7786
-reg__260: reg__260
-case__1587: case__1587
-logic__6049: logic__6049
-datapath__238: datapath__238
-reg__339: reg__339
-logic__5987: logic__5987
-logic__9630: logic__3618
-datapath__316: datapath__316
-logic__2051: logic__2051
-logic__4788: logic__4788
-logic__6577: logic__6577
-logic__3445: logic__3445
-logic__497: logic__497
-FixedClockBroadcast_1: FixedClockBroadcast_1
-logic__3632: logic__3632
-logic__544: logic__544
-logic__3612: logic__3612
-logic__3696: logic__3696
-reg__52: reg__52
-logic__3591: logic__3591
-reg__1227: reg__1227
-case__47: case__47
-case__309: case__309
-logic__5852: logic__5852
-logic__6858: logic__6858
-case__133: case__133
-logic__1236: logic__1236
-logic__2942: logic__2942
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__6: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__2741: logic__2741
-case__1713: case__1713
-datapath__419: datapath__419
-reg__1584: reg__926
-logic__6841: logic__6841
-logic__6753: logic__6753
-logic__8690: logic__8690
-case__1257: case__1257
-logic__2754: logic__2754
-logic__4347: logic__4347
-muxpart__130: muxpart__130
-muxpart__43: muxpart__43
-case__980: case__980
-logic__5358: logic__5358
-logic__2097: logic__2097
-case__936: case__936
-logic__194: logic__194
-case__114: case__114
-logic__1096: logic__1096
-logic__8885: logic__8885
-logic__4209: logic__4209
-logic__7261: logic__7261
-datapath__726: datapath__273
-logic__2185: logic__2185
-logic__9668: logic__4554
-reg__1542: reg__926
-AsyncValidSync__23: AsyncValidSync
-cordic_angle_lut__parameterized0: cordic_angle_lut__parameterized0
-muxpart__62: muxpart__62
-reg__326: reg__326
-dsp48e1__43: dsp48e1__43
-reg__233: reg__233
-case__903: case__903
-logic__6082: logic__6082
-case__38: case__38
-logic__8075: logic__8075
-logic__5616: logic__5616
-case__1632: case__1632
-reg__1220: reg__1220
-muxpart__42: muxpart__42
-reg__1116: reg__1116
-logic__6718: logic__6718
-logic__1827: logic__1827
-logic__8174: logic__8174
-dsp48e1__25: dsp48e1__25
-logic__7124: logic__7124
-logic__2065: logic__2065
-datapath__55: datapath__55
-logic__6038: logic__6038
-gray_to_binary__2: gray_to_binary
-reg__447: reg__447
-datapath__665: datapath__665
-logic__1519: logic__1519
-logic__1100: logic__1100
-logic__7311: logic__7311
-Queue1_RegMapperInput_i9_m8__1: Queue1_RegMapperInput_i9_m8
-case__752: case__752
-logic__6276: logic__6276
-datapath__536: datapath__536
-case__378: case__378
-case__377: case__377
-logic__8687: logic__8687
-logic__988: logic__988
-reg__1086: reg__1086
-reg__1495: reg__925
-case__1327: case__1327
-logic__888: logic__888
-dsp48e1__17: dsp48e1__17
-logic__6792: logic__6792
-reg__1091: reg__1091
-case__110: case__110
-reg__164: reg__164
-logic__3471: logic__3471
-logic__552: logic__552
-datapath__157: datapath__157
-extram__10: extram__3
-reg__633: reg__633
-case__356: case__356
-case__1524: case__1524
-case__1341: case__1341
-logic__6702: logic__6702
-case__1303: case__1303
-reg__624: reg__624
-case__681: case__681
-logic__874: logic__874
-reg__215: reg__215
-case__511: case__511
-reg__1210: reg__1210
-logic__9327: logic__9327
-logic__4643: logic__4643
-logic__9792: logic__2330
-reg__281: reg__281
-case__268: case__268
-logic__1093: logic__1093
-datapath__50: datapath__50
-reg__555: reg__555
-reg__654: reg__654
-logic__6812: logic__6812
-logic__1515: logic__1515
-datapath__281: datapath__281
-logic__7461: logic__7461
-logic__5239: logic__5239
-logic__4406: logic__4406
-case__538: case__538
-case__187: case__187
-trck_cntrl: trck_cntrl
-logic__6084: logic__6084
-IntSyncCrossingSource_n1x1__1: IntSyncCrossingSource_n1x1
-reg__1051: reg__1051
-logic__116: logic__116
-logic__178: logic__178
-logic__4472: logic__4472
-reg__453: reg__453
-logic__9589: logic__9589
-reg__807: reg__807
-case__1438: case__1438
-logic__4823: logic__4823
-logic__5353: logic__5353
-logic__191: logic__191
-logic__9756: logic__2449
-case__843: case__843
-rom__6: rom__6
-case__1043: case__1043
-logic__7259: logic__7259
-logic__143: logic__143
-logic__43: logic__43
-logic__5982: logic__5982
-case__1728: case__1728
-logic__9707: logic__2473
-logic__5194: logic__5194
-logic__4484: logic__4484
-reg__1019: reg__1019
-reg__1522: reg__925
-datapath__740: datapath__41
-logic__5100: logic__5100
-logic__5828: logic__5828
-logic__1174: logic__1174
-FixedClockBroadcast_3: FixedClockBroadcast_3
-reg__1449: reg__1339
-logic__1323: logic__1323
-reg__126: reg__126
-datapath__403: datapath__403
-datapath__294: datapath__294
-logic__384: logic__384
-logic__1513: logic__1513
-muxpart__263: muxpart__263
-logic__6810: logic__6810
-case__977: case__977
-case__1232: case__1232
-logic__7455: logic__7455
-case__342: case__342
-logic__3235: logic__3235
-case__1216: case__1216
-logic__8036: logic__8036
-case__1680: case__1680
-reg__1335: reg__1335
-case__969: case__969
-logic__6797: logic__6797
-logic__4023: logic__4023
-case__1792: case__1613
-logic__4755: logic__4755
-logic__6: logic__6
-reg__1353: reg__1353
-keep__15: keep__15
-logic__348: logic__348
-datapath__240: datapath__240
-case__946: case__946
-case__1715: case__1715
-logic__6334: logic__6334
-reg__7: reg__7
-logic__5986: logic__5986
-logic__1528: logic__1528
-reg__134: reg__134
-logic__9235: logic__9235
-logic__8011: logic__8011
-logic__8888: logic__8888
-reg__95: reg__95
-logic__14: logic__14
-sync: sync
-datapath__319: datapath__319
-logic__5107: logic__5107
-reg__424: reg__424
-reg__841: reg__841
-logic__8324: logic__8324
-reg__1599: reg__242
-case__1630: case__1630
-case__632: case__632
-logic__6997: logic__6997
-logic__9918: logic__6773
-AsyncQueueSource_DebugInternalBundle: AsyncQueueSource_DebugInternalBundle
-logic__1090: logic__1090
-reg__1228: reg__1228
-logic__7410: logic__7410
-logic__2901: logic__2901
-logic__9694: logic__2504
-case__821: case__821
-logic__5543: logic__5543
-logic__2373: logic__2373
-logic__6749: logic__6749
-case__1333: case__1333
-logic__9708: logic__2583
-logic__4583: logic__4583
-logic__167: logic__167
-case__542: case__542
-reg__569: reg__569
-muxpart__358: muxpart__358
-logic__7433: logic__7433
-logic__9089: logic__9089
-datapath__701: datapath__701
-case__930: case__930
-reg__342: reg__342
-divider__parameterized0: divider__parameterized0
-case__619: case__619
-logic__4991: logic__4991
-logic__905: logic__905
-logic__3288: logic__3288
-reg__161: reg__161
-logic__9819: logic__2257
-case__1692: case__1692
-logic__1514: logic__1514
-datapath__513: datapath__513
-case__341: case__341
-reg__835: reg__835
-logic__1362: logic__1362
-logic__1905: logic__1905
-case__761: case__761
-logic__6761: logic__6761
-reg__836: reg__836
-divider: divider
-muxpart__61: muxpart__61
-reg__806: reg__806
-case__634: case__634
-case__266: case__266
-case__499: case__499
-logic__1325: logic__1325
-logic__5010: logic__5010
-TLAtomicAutomata_cbus: TLAtomicAutomata_cbus
-logic__64: logic__64
-muxpart__55: muxpart__55
-logic__7565: logic__7565
-reg__103: reg__103
-datapath__755: datapath__671
-reg__797: reg__797
-reg__1336: reg__1336
-logic__4717: logic__4717
-reg__1550: reg__924
-reg__334: reg__334
-logic__5677: logic__5677
-logic__9591: logic__9591
-dsp48e1__47: dsp48e1__47
-datapath__392: datapath__392
-case__1755: case__656
-reg__422: reg__422
-reg__48: reg__48
-reg__118: reg__118
-logic__9746: logic__2475
-logic__7292: logic__7292
-logic__7031: logic__7031
-reg__674: reg__674
-datapath__232: datapath__232
-logic__2678: logic__2678
-datapath__369: datapath__369
-case__1719: case__1719
-logic__8916: logic__8916
-logic__8559: logic__8559
-logic__3895: logic__3895
-case__1162: case__1162
-logic__6649: logic__6649
-dsp48e1__5: dsp48e1__5
-logic__122: logic__122
-reg__1074: reg__1074
-case__1331: case__1331
-logic__9312: logic__9312
-case__571: case__571
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__7: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__944: reg__944
-datapath__476: datapath__476
-logic__5291: logic__5291
-case__137: case__137
-logic__4286: logic__4286
-reg__978: reg__978
-logic__7411: logic__7411
-logic__9523: logic__9523
-logic__5910: logic__5910
-reg__1371: reg__1371
-logic__7985: logic__7985
-reg__294: reg__294
-case__1764: case__725
-logic__1287: logic__1287
-reg__1151: reg__1151
-reg__450: reg__450
-logic__1549: logic__1549
-counter__21: counter__21
-logic__3481: logic__3481
-logic__9758: logic__2443
-logic__4733: logic__4733
-logic__5528: logic__5528
-logic__6670: logic__6670
-reg__855: reg__855
-case__345: case__345
-reg__1469: reg__1088
-logic__9832: logic__2226
-logic__3785: logic__3785
-logic__1464: logic__1464
-logic__808: logic__808
-logic__9456: logic__9456
-logic__1146: logic__1146
-case__763: case__763
-reg__764: reg__764
-case__904: case__904
-ram__1: ram__1
-case__1736: case__1736
-logic__9807: logic__2285
-logic__5339: logic__5339
-case__1189: case__1189
-case__192: case__192
-datapath__98: datapath__98
-logic__5653: logic__5653
-logic__2736: logic__2736
-case__968: case__968
-case__1717: case__1717
-reg__1036: reg__1036
-logic__7059: logic__7059
-logic__2667: logic__2667
-logic__2390: logic__2390
-reg__517: reg__517
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__8: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__9315: logic__9315
-logic__8957: logic__8957
-logic__8580: logic__8580
-reg__193: reg__193
-logic__1692: logic__1692
-reg__328: reg__328
-logic__4662: logic__4662
-reg__423: reg__423
-logic__9913: logic__8198
-case__227: case__227
-datapath__454: datapath__454
-datapath__561: datapath__561
-logic__358: logic__358
-case__139: case__139
-reg__1240: reg__1240
-logic__7398: logic__7398
-reg__452: reg__452
-logic__632: logic__632
-PeripheryBus_pbus: PeripheryBus_pbus
-logic__9579: logic__9579
-case__607: case__607
-muxpart__246: muxpart__246
-reg__957: reg__957
-logic__6655: logic__6655
-logic__6925: logic__6925
-datapath__453: datapath__453
-case__1137: case__1137
-case__1562: case__1562
-reg__321: reg__321
-case__1053: case__1053
-logic__4183: logic__4183
-logic__4679: logic__4679
-logic__2156: logic__2156
-reg__349: reg__349
-case__1293: case__1293
-reg__909: reg__909
-logic__1795: logic__1795
-logic__971: logic__971
-logic__4019: logic__4019
-logic__1450: logic__1450
-case__251: case__251
-logic__4996: logic__4996
-reg__1561: reg__925
-reg__646: reg__646
-rom__5: rom__5
-datapath__82: datapath__82
-case__1014: case__1014
-logic__3835: logic__3835
-logic__7951: logic__7951
-datapath__494: datapath__494
-reg__1173: reg__1173
-reg__136: reg__136
-TLWidthWidget8_1__1: TLWidthWidget8_1
-reg__329: reg__329
-case__1033: case__1033
-logic__8882: logic__8882
-logic__6919: logic__6919
-INToRecFN: INToRecFN
-logic__9612: logic__3673
-logic__1165: logic__1165
-reg__247: reg__247
-logic__8679: logic__8679
-datapath__268: datapath__268
-logic__1910: logic__1910
-case__1376: case__1376
-case__1573: case__1573
-logic__9759: logic__2438
-logic__4726: logic__4726
-logic__789: logic__789
-logic__7973: logic__7973
-logic__7904: logic__7904
-logic__7685: logic__7685
-case__1677: case__1677
-logic__9775: logic__2387
-reg__309: reg__309
-logic__2261: logic__2261
-logic__2089: logic__2089
-case__1643: case__1643
-datapath__353: datapath__353
-reg__418: reg__418
-logic__7048: logic__7048
-reg__275: reg__275
-reg__796: reg__796
-case__661: case__661
-logic__6806: logic__6806
-extram__8: extram__8
-logic__8327: logic__8327
-muxpart__8: muxpart__8
-logic__938: logic__938
-reg__1290: reg__1290
-reg__131: reg__131
-logic__4554: logic__4554
-counter__1: counter__1
-keep__48: keep__11
-logic__8175: logic__8175
-logic__5975: logic__5975
-datapath__150: datapath__150
-case__825: case__825
-logic__7648: logic__7648
-case__1047: case__1047
-logic__5004: logic__5004
-case__1571: case__1571
-counter__20: counter__20
-case__847: case__847
-logic__4345: logic__4345
-logic__4851: logic__4851
-logic__2619: logic__2619
-case__1636: case__1636
-logic__1456: logic__1456
-reg__443: reg__443
-reg__237: reg__237
-reg__553: reg__553
-logic__1836: logic__1836
-case__166: case__166
-Repeater_TLBundleA_a26d64s2k1z3u: Repeater_TLBundleA_a26d64s2k1z3u
-reg__532: reg__532
-logic__5477: logic__5477
-logic__5521: logic__5521
-logic__3871: logic__3871
-logic__9853: logic__2181
-Queue2_TLBundleA_a29d64s2k1z3u: Queue2_TLBundleA_a29d64s2k1z3u
-reg__1488: reg__1087
-logic__4136: logic__4136
-FPU__GB0: FPU__GB0
-logic__3333: logic__3333
-datapath__38: datapath__38
-case__1164: case__1164
-MulAddRecFNPipe_l2_e11_s53: MulAddRecFNPipe_l2_e11_s53
-muxpart__58: muxpart__58
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__23: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__134: case__134
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__13: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__358: case__358
-datapath__70: datapath__70
-logic__8919: logic__8919
-logic__5699: logic__5699
-reg__1328: reg__1328
-reg__91: reg__91
-logic__9556: logic__9556
-logic__9808: logic__2280
-logic__4971: logic__4971
-datapath__126: datapath__126
-reg__516: reg__516
-reg__1057: reg__1057
-ram_2x120__1: ram_2x120
-reg__430: reg__430
-logic__4135: logic__4135
-logic__7154: logic__7154
-logic__6987: logic__6987
-case__1007: case__1007
-logic__2208: logic__2208
-logic__1017: logic__1017
-datapath__375: datapath__375
-MulDiv: MulDiv
-case__1487: case__1487
-logic__9917: logic__6768
-logic__2661: logic__2661
-muxpart__60: muxpart__60
-logic__9563: logic__9563
-logic__1529: logic__1529
-logic__3488: logic__3488
-logic__4781: logic__4781
-case__381: case__381
-muxpart__177: muxpart__177
-logic__5871: logic__5871
-logic__9816: logic__2262
-logic__9027: logic__9027
-logic__3283: logic__3283
-logic__638: logic__638
-RoundRawFNToRecFN_1: RoundRawFNToRecFN_1
-case__215: case__215
-case__1250: case__1250
-case__1032: case__1032
-logic__8360: logic__8360
-logic__2082: logic__2082
-logic__3217: logic__3217
-reg__556: reg__556
-logic__2839: logic__2839
-ResetCatchAndSync_d3__1: ResetCatchAndSync_d3
-logic__2944: logic__2944
-IntSyncCrossingSource_n1x1_Registered: IntSyncCrossingSource_n1x1_Registered
-rockettile_icache_tag_array_0_64x21: rockettile_icache_tag_array_0_64x21
-logic__8213: logic__8213
-logic__3512: logic__3512
-logic__1553: logic__1553
-ErrorDeviceWrapper: ErrorDeviceWrapper
-datapath__632: datapath__632
-case__1004: case__1004
-reg__1429: reg__1429
-logic__9894: logic__9078
-reg__1022: reg__1022
-logic__1344: logic__1344
-logic__8227: logic__8227
-reg__220: reg__220
-logic__8617: logic__8617
-logic__2121: logic__2121
-logic__9732: logic__2515
-logic__9810: logic__2278
-datapath__109: datapath__109
-logic__4507: logic__4507
-logic__5501: logic__5501
-logic__123: logic__123
-logic__7146: logic__7146
-logic__1318: logic__1318
-logic__9761: logic__2433
-reg__1136: reg__1136
-reg: reg
-logic__7416: logic__7416
-logic__7023: logic__7023
-logic__9682: logic__2534
-genesys2_rocket_top__GC0: genesys2_rocket_top__GC0
-case__1126: case__1126
-logic__3980: logic__3980
-logic__514: logic__514
-reg__626: reg__626
-logic__5783: logic__5783
-logic__4727: logic__4727
-reg__485: reg__485
-logic__3652: logic__3652
-logic__9790: logic__2334
-reg__1333: reg__1333
-reg__43: reg__43
-logic__1967: logic__1967
-case__783: case__783
-Arbiter2_Valid_PTWReq: Arbiter2_Valid_PTWReq
-HellaCacheArbiter: HellaCacheArbiter
-logic__8956: logic__8956
-case__1607: case__1607
-logic__7230: logic__7230
-reg__929: reg__929
-reg__1181: reg__1181
-reg__1174: reg__1174
-logic__2108: logic__2108
-logic__989: logic__989
-logic__8695: logic__8695
-reg__211: reg__211
-twiddle_ram__2: twiddle_ram
-logic__5106: logic__5106
-case__699: case__699
-ICache: ICache
-logic__7691: logic__7691
-case__252: case__252
-reg__661: reg__661
-keep__54: keep__11
-logic__3189: logic__3189
-reg__1095: reg__1095
-logic__851: logic__851
-reg__1299: reg__1299
-logic__4654: logic__4654
-datapath__564: datapath__564
-logic__4697: logic__4697
-logic__5270: logic__5270
-reg__766: reg__766
-reg__642: reg__642
-logic__3487: logic__3487
-logic__4195: logic__4195
-logic__2819: logic__2819
-logic__7078: logic__7078
-logic__6809: logic__6809
-addsub__8: addsub__5
-reg__776: reg__776
-datapath__480: datapath__480
-case__776: case__776
-logic__9949: logic__1136
-muxpart__216: muxpart__216
-datapath__580: datapath__580
-reg__625: reg__625
-logic__5836: logic__5836
-logic__54: logic__54
-muxpart__79: muxpart__79
-logic__1490: logic__1490
-logic__4364: logic__4364
-logic__4843: logic__4843
-reg__1291: reg__1291
-reg__1468: reg__1089
-logic__6138: logic__6138
-logic__9118: logic__9118
-logic__4738: logic__4738
-datapath__526: datapath__526
-reg__261: reg__261
-reg__116: reg__116
-case__1083: case__1083
-logic__1563: logic__1563
-logic__2166: logic__2166
-reg__454: reg__454
-logic__1564: logic__1564
-case__756: case__756
-logic__7424: logic__7424
-logic__7036: logic__7036
-reg__1072: reg__1072
-logic__1911: logic__1911
-reg__184: reg__184
-case__868: case__868
-logic__2172: logic__2172
-case__859: case__859
-AsyncQueueSink_DebugInternalBundle: AsyncQueueSink_DebugInternalBundle
-reg__235: reg__235
-logic__4299: logic__4299
-logic__6688: logic__6688
-logic__5688: logic__5688
-logic__6326: logic__6326
-reg__157: reg__157
-logic__9969: logic__907
-case__1733: case__1733
-logic__5903: logic__5903
-logic__4479: logic__4479
-case__1042: case__1042
-logic__9766: logic__2414
-logic__2333: logic__2333
-case__1063: case__1063
-logic__7465: logic__7465
-reg__186: reg__186
-reg__635: reg__635
-datapath__421: datapath__421
-muxpart__69: muxpart__69
-logic__6902: logic__6902
-case__351: case__351
-logic__5083: logic__5083
-case__580: case__580
-reg__1217: reg__1217
-case__1478: case__1478
-reg__1158: reg__1158
-logic__6591: logic__6591
-datapath__583: datapath__583
-logic__5529: logic__5529
-case__1746: case__1746
-logic__1074: logic__1074
-logic__924: logic__924
-logic__6644: logic__6644
-datapath__389: datapath__389
-case__1108: case__1108
-logic__9318: logic__9318
-datapath__376: datapath__376
-logic__4807: logic__4807
-datapath__4: datapath__4
-reg__869: reg__869
-logic__5947: logic__5947
-reg__1071: reg__1071
-logic__9705: logic__2475
-logic__6654: logic__6654
-logic__5066: logic__5066
-case__373: case__373
-case__323: case__323
-dsp48e1: dsp48e1
-logic__3628: logic__3628
-logic__6536: logic__6536
-logic__6175: logic__6175
-case__998: case__998
-datapath__256: datapath__256
-logic__5604: logic__5604
-reg__1112: reg__1112
-datapath__452: datapath__452
-logic__9680: logic__2538
-case__1784: case__1621
-case__1604: case__1604
-logic__5797: logic__5797
-logic__5898: logic__5898
-cacode_gen_trck: cacode_gen_trck
-logic__7570: logic__7570
-logic__7903: logic__7903
-logic__9424: logic__9424
-case__937: case__937
-datapath__493: datapath__493
-reg__1237: reg__1237
-logic__9715: logic__2553
-logic__9821: logic__2253
-case__944: case__944
-logic__9399: logic__9399
-reg__373: reg__373
-datapath__721: datapath__384
-logic__5284: logic__5284
-case__1284: case__1284
-logic__9373: logic__9373
-logic__9570: logic__9570
-reg__670: reg__670
-logic__6026: logic__6026
-reg__445: reg__445
-datapath__670: datapath__670
-logic__9197: logic__9197
-logic__3337: logic__3337
-reg__926: reg__926
-logic__1358: logic__1358
-logic__5395: logic__5395
-logic__4774: logic__4774
-logic__3086: logic__3086
-logic__7882: logic__7882
-datapath__578: datapath__578
-logic__5281: logic__5281
-logic__6928: logic__6928
-logic__1089: logic__1089
-muxpart__218: muxpart__218
-logic__863: logic__863
-case__1577: case__1577
-case__1600: case__1600
-case__983: case__983
-logic__889: logic__889
-case__1735: case__1735
-logic__2083: logic__2083
-muxpart__205: muxpart__205
-TLDebugModule: TLDebugModule
-reg__1213: reg__1213
-logic__5235: logic__5235
-logic__2820: logic__2820
-logic__9649: logic__4590
-logic__5977: logic__5977
-reg__77: reg__77
-logic__3854: logic__3854
-case__1149: case__1149
-logic__5252: logic__5252
-case__869: case__869
-logic__6647: logic__6647
-logic__6535: logic__6535
-logic__8051: logic__8051
-datapath__742: datapath__139
-logic__4308: logic__4308
-datapath__582: datapath__582
-logic__7369: logic__7369
-logic__3578: logic__3578
-logic__3565: logic__3565
-datapath__373: datapath__373
-logic__2159: logic__2159
-muxpart__187: muxpart__187
-logic__9039: logic__9039
-datapath__733: datapath__266
-muxpart__13: muxpart__13
-reg__599: reg__599
-logic__3205: logic__3205
-logic__2005: logic__2005
-logic__2280: logic__2280
-logic__7291: logic__7291
-case__1757: case__733
-logic__6999: logic__6999
-logic__2017: logic__2017
-logic__5908: logic__5908
-reg__634: reg__634
-reg__1002: reg__1002
-logic__6537: logic__6537
-case__154: case__154
-case__401: case__401
-logic__4301: logic__4301
-logic__6689: logic__6689
-logic__5496: logic__5496
-logic__901: logic__901
-logic__6349: logic__6349
-case__148: case__148
-reg__1566: reg__926
-logic__4346: logic__4346
-logic__830: logic__830
-case__1306: case__1306
-logic__6132: logic__6132
-case__1631: case__1631
-TLFragmenter_FPGAGPS: TLFragmenter_FPGAGPS
-SynchronizerShiftReg_w1_d3: SynchronizerShiftReg_w1_d3
-logic__1319: logic__1319
-logic__2955: logic__2955
-case__815: case__815
-case__1173: case__1173
-keep__44: keep__15
-case__1748: case__664
-logic__1816: logic__1816
-reg__411: reg__411
-logic__603: logic__603
-logic__3710: logic__3710
-datapath__417: datapath__417
-reg__1060: reg__1060
-reg__883: reg__883
-case__386: case__386
-datapath__511: datapath__511
-logic__3584: logic__3584
-reg__595: reg__595
-logic__9030: logic__9030
-datapath__400: datapath__400
-logic__5167: logic__5167
-logic__3284: logic__3284
-logic__2018: logic__2018
-TLWidthWidget8_3: TLWidthWidget8_3
-case__1223: case__1223
-logic__6881: logic__6881
-case__264: case__264
-DMIToTL: DMIToTL
-case__258: case__258
-logic__343: logic__343
-signinv__2: signinv__2
-muxpart__56: muxpart__56
-case__800: case__800
-logic__8044: logic__8044
-case__403: case__403
-logic__7418: logic__7418
-logic__5921: logic__5921
-logic__4775: logic__4775
-reg__1054: reg__1054
-case__250: case__250
-logic__793: logic__793
-case__564: case__564
-reg__964: reg__964
-TLFIFOFixer_2: TLFIFOFixer_2
-reg__1179: reg__1179
-case__769: case__769
-case__434: case__434
-counter__19: counter__19
-reg__580: reg__580
-logic__6034: logic__6034
-logic__8604: logic__8604
-logic__5964: logic__5964
-reg__1534: reg__925
-AsyncQueueSource_TLBundleD_a9d32s1k1z2u: AsyncQueueSource_TLBundleD_a9d32s1k1z2u
-case__1209: case__1209
-reg__891: reg__891
-reg__1605: reg__156
-logic__5391: logic__5391
-case__806: case__806
-logic__2443: logic__2443
-case__1393: case__1393
-Rocket: Rocket
-case__663: case__663
-logic__7150: logic__7150
-logic__1321: logic__1321
-muxpart__11: muxpart__11
-logic__8273: logic__8273
-case__813: case__813
-logic__163: logic__163
-datapath__525: datapath__525
-logic__9374: logic__9374
-logic__9340: logic__9340
-logic__2960: logic__2960
-Frontend: Frontend
-reg__658: reg__658
-case__314: case__314
-logic__2190: logic__2190
-reg__1412: reg__1412
-reg__55: reg__55
-logic__2904: logic__2904
-logic__743: logic__743
-logic__1339: logic__1339
-case__1323: case__1323
-reg__705: reg__705
-logic__9032: logic__9032
-logic__3094: logic__3094
-datapath__533: datapath__533
-AsyncValidSync__10: AsyncValidSync
-datapath__191: datapath__191
-logic__4759: logic__4759
-logic__532: logic__532
-logic__1132: logic__1132
-reg__301: reg__301
-logic__7362: logic__7362
-reg__768: reg__768
-logic__6277: logic__6277
-case__1429: case__1429
-reg__1363: reg__1363
-logic__4523: logic__4523
-logic__4142: logic__4142
-reg__1015: reg__1015
-reg__412: reg__412
-AsyncValidSync__20: AsyncValidSync
-logic__9263: logic__9263
-case__21: case__21
-reg__1307: reg__1307
-reg__313: reg__313
-case__578: case__578
-datapath__22: datapath__22
-logic__7157: logic__7157
-logic__5565: logic__5565
-dsp48e1__7: dsp48e1__7
-logic__9019: logic__9019
-reg__1250: reg__1250
-logic__4344: logic__4344
-case__546: case__546
-logic__3090: logic__3090
-reg__26: reg__26
-counter__11: counter__11
-addsub: addsub
-logic__9617: logic__3646
-logic__7075: logic__7075
-logic__1162: logic__1162
-datapath__59: datapath__59
-reg__940: reg__940
-logic__550: logic__550
-reg__36: reg__36
-logic__7027: logic__7027
-case__1220: case__1220
-logic__7780: logic__7780
-datapath__359: datapath__359
-logic__5989: logic__5989
-muxpart__223: muxpart__223
-case__1023: case__1023
-case__1242: case__1242
-reg__1428: reg__1428
-reg__158: reg__158
-datapath__737: datapath__44
-logic__891: logic__891
-datapath__329: datapath__329
-datapath__658: datapath__658
-logic__3476: logic__3476
-case__301: case__301
-logic__8693: logic__8693
-reg__1249: reg__1249
-logic__5405: logic__5405
-case__318: case__318
-reg__1409: reg__1409
-logic__9784: logic__2354
-logic__2: logic__2
-reg__871: reg__871
-logic__1409: logic__1409
-datapath__9: datapath__9
-logic__1577: logic__1577
-logic__6100: logic__6100
-logic__4199: logic__4199
-logic__6992: logic__6992
-extladd: extladd
-Repeater_TLBundleA_a32d64s2k1z3u: Repeater_TLBundleA_a32d64s2k1z3u
-logic__3275: logic__3275
-case__1482: case__1482
-TLBuffer_a32d64s2k1z4u_1: TLBuffer_a32d64s2k1z4u_1
-logic__3105: logic__3105
-reg__963: reg__963
-reg__733: reg__733
-muxpart__154: muxpart__154
-case__649: case__649
-logic__2711: logic__2711
-logic__3036: logic__3036
-logic__1926: logic__1926
-TLFIFOFixer_1: TLFIFOFixer_1
-case__1302: case__1302
-datapath__399: datapath__399
-case__932: case__932
-reg__1221: reg__1221
-dsp48e1__33: dsp48e1__33
-logic__1579: logic__1579
-case__874: case__874
-case__1602: case__1602
-logic__2740: logic__2740
-logic__6950: logic__6950
-datapath__248: datapath__248
-logic__5171: logic__5171
-logic__7171: logic__7171
-datapath__237: datapath__237
-logic__2288: logic__2288
-case__860: case__860
-logic__4773: logic__4773
-reg__995: reg__995
-datapath__630: datapath__630
-logic__5971: logic__5971
-datapath__739: datapath__42
-dsp48e1__38: dsp48e1__38
-logic__7530: logic__7530
-reg__534: reg__534
-mult_46_15_61__2: mult_46_15_61
-logic__6524: logic__6524
-counter__7: counter__7
-logic__8248: logic__8248
-case__298: case__298
-muxpart__15: muxpart__15
-reg__374: reg__374
-datapath__567: datapath__567
-case__1266: case__1266
-logic__9885: logic__1287
-case__1731: case__1731
-case__1669: case__1669
-sync__1: sync
-datapath__5: datapath__5
-logic__9950: logic__1132
-datapath__428: datapath__428
-logic__7079: logic__7079
-logic__8441: logic__8441
-case__916: case__916
-logic__9729: logic__2518
-case__549: case__549
-datapath__770: datapath__42
-reg__736: reg__736
-AsyncValidSync__9: AsyncValidSync
-datapath__601: datapath__601
-datapath__757: datapath__669
-TLDebugModuleOuter: TLDebugModuleOuter
-logic__9568: logic__9568
-reg__586: reg__586
-case__1249: case__1249
-counter__24: counter__24
-logic__5143: logic__5143
-reg__1532: reg__924
-datapath__621: datapath__621
-logic__1824: logic__1824
-logic__2293: logic__2293
-logic__3317: logic__3317
-muxpart__155: muxpart__155
-logic__4177: logic__4177
-reg__156: reg__156
-datapath__608: datapath__608
-logic__9908: logic__8888
-logic__720: logic__720
-logic__7236: logic__7236
-logic__896: logic__896
-logic__9239: logic__9239
-logic__9809: logic__2279
-case__948: case__948
-logic__2878: logic__2878
-case__812: case__812
-case__1254: case__1254
-logic__5976: logic__5976
-logic__5895: logic__5895
-datapath__593: datapath__593
-logic__1217: logic__1217
-logic__9073: logic__9073
-case__1077: case__1077
-case__986: case__986
-reg__755: reg__755
-logic__4303: logic__4303
-logic__8018: logic__8018
-reg__2: reg__2
-reg__954: reg__954
-logic__9271: logic__9271
-case__565: case__565
-datapath__450: datapath__450
-datapath__638: datapath__638
-logic__6126: logic__6126
-datapath__187: datapath__187
-logic__5905: logic__5905
-logic__2547: logic__2547
-reg__541: reg__541
-muxpart__64: muxpart__64
-logic__1634: logic__1634
-logic__9859: logic__2169
-datapath__84: datapath__84
-logic__9500: logic__9500
-logic__1661: logic__1661
-datapath__615: datapath__615
-logic__2100: logic__2100
-reg__1377: reg__1377
-case__833: case__833
-datapath__235: datapath__235
-logic__6512: logic__6512
-logic__5461: logic__5461
-logic__5399: logic__5399
-logic__3527: logic__3527
-logic__300: logic__300
-logic__128: logic__128
-FPGAUARTClockSinkDomain: FPGAUARTClockSinkDomain
-datapath__698: datapath__698
-reg__767: reg__767
-logic__5047: logic__5047
-case__1752: case__659
-datapath__343: datapath__343
-logic__2604: logic__2604
-datapath__773: datapath__39
-logic__9895: logic__9077
-reg__448: reg__448
-logic__5271: logic__5271
-logic__6666: logic__6666
-AsyncResetSynchronizerShiftReg_w1_d3_i0__12: AsyncResetSynchronizerShiftReg_w1_d3_i0
-reg__603: reg__603
-logic__3200: logic__3200
-logic__594: logic__594
-logic__8928: logic__8928
-reg__1375: reg__1375
-logic__8021: logic__8021
-logic__7603: logic__7603
-reg__249: reg__249
-logic__6723: logic__6723
-datapath__165: datapath__165
-reg__1525: reg__925
-logic__1817: logic__1817
-logic__8500: logic__8500
-datapath__610: datapath__610
-reg__594: reg__594
-logic__3556: logic__3556
-logic__3625: logic__3625
-logic__5204: logic__5204
-logic__1539: logic__1539
-reg__1390: reg__1390
-logic__4922: logic__4922
-case__1012: case__1012
-reg__1523: reg__924
-logic__3540: logic__3540
-case__156: case__156
-logic__7110: logic__7110
-datapath__46: datapath__46
-case__53: case__53
-logic__109: logic__109
-logic__7787: logic__7787
-logic__5348: logic__5348
-case__687: case__687
-logic__7990: logic__7990
-logic__1895: logic__1895
-case__795: case__795
-datapath__210: datapath__210
-logic__7158: logic__7158
-logic__1909: logic__1909
-logic__4428: logic__4428
-reg__761: reg__761
-reg__649: reg__649
-logic__605: logic__605
-logic__1338: logic__1338
-datapath__105: datapath__105
-logic__9601: logic__9601
-datapath__263: datapath__263
-muxpart__183: muxpart__183
-logic__7529: logic__7529
-reg__113: reg__113
-reg__1562: reg__924
-logic__5516: logic__5516
-datapath__2: datapath__2
-logic__848: logic__848
-muxpart__199: muxpart__199
-logic__6679: logic__6679
-case__270: case__270
-case__1141: case__1141
-logic__1322: logic__1322
-logic__6813: logic__6813
-reg__820: reg__820
-case__605: case__605
-logic__643: logic__643
-logic__3233: logic__3233
-logic__7205: logic__7205
-logic__5438: logic__5438
-logic__5946: logic__5946
-logic__3676: logic__3676
-logic__2914: logic__2914
-reg__112: reg__112
-logic__5792: logic__5792
-ram__6: ram__6
-logic__2715: logic__2715
-logic__3834: logic__3834
-reg__13: reg__13
-logic__7661: logic__7661
-case__1582: case__1582
-logic__9704: logic__2476
-logic__2171: logic__2171
-datapath__283: datapath__283
-logic__264: logic__264
-logic__3649: logic__3649
-logic__5062: logic__5062
-TLInterconnectCoupler_cbus_to_bus_named_pbus: TLInterconnectCoupler_cbus_to_bus_named_pbus
-case__626: case__626
-logic__6557: logic__6557
-datapath__728: datapath__271
-logic__7210: logic__7210
-logic__6730: logic__6730
-datapath__635: datapath__635
-logic__4377: logic__4377
-reg__1422: reg__1422
-logic__3446: logic__3446
-logic__2334: logic__2334
-logic__1382: logic__1382
-logic__8952: logic__8952
-case__1374: case__1374
-case__1662: case__1662
-logic__9774: logic__2390
-case__5: case__5
-logic__9691: logic__2515
-case__1766: case__525
-case__550: case__550
-logic__7284: logic__7284
-reg__1235: reg__1235
-logic__5973: logic__5973
-logic__5040: logic__5040
-reg__619: reg__619
-datapath__662: datapath__662
-reg__183: reg__183
-logic__8571: logic__8571
-logic__791: logic__791
-case__548: case__548
-case__1245: case__1245
-muxpart__220: muxpart__220
-logic__4650: logic__4650
-logic__3758: logic__3758
-reg__109: reg__109
-reg__1385: reg__1385
-TLFragmenter_1: TLFragmenter_1
-logic__5292: logic__5292
-logic__7553: logic__7553
-logic__9695: logic__2501
-case__1769: case__522
-datapath__225: datapath__225
-logic__3058: logic__3058
-logic__7865: logic__7865
-reg__292: reg__292
-logic__6738: logic__6738
-reg__794: reg__794
-logic__5116: logic__5116
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__2: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__1167: reg__1167
-datapath__457: datapath__457
-FPUFMAPipe_l3_f32: FPUFMAPipe_l3_f32
-case__464: case__464
-reg__1519: reg__925
-logic__3984: logic__3984
-case__584: case__584
-logic__3577: logic__3577
-logic__6029: logic__6029
-logic__9326: logic__9326
-mult_53_53_106: mult_53_53_106
-case__1581: case__1581
-case__1710: case__1710
-reg__1600: reg__241
-logic__3238: logic__3238
-logic__5002: logic__5002
-reg__1296: reg__1296
-logic__7589: logic__7589
-case__365: case__365
-logic__1260: logic__1260
-reg__440: reg__440
-reg__1005: reg__1005
-reg__1577: reg__924
-logic__7262: logic__7262
-logic__1226: logic__1226
-logic__5562: logic__5562
-logic__6071: logic__6071
-logic__7370: logic__7370
-case__1480: case__1480
-reg__590: reg__590
-mult_66_66_66: mult_66_66_66
-counter__15: counter__15
-logic__592: logic__592
-case__297: case__297
-case__816: case__816
-logic__7020: logic__7020
-keep__43: keep__16
-LevelGateway__5: LevelGateway
-logic__6641: logic__6641
-reg__889: reg__889
-datapath__100: datapath__100
-logic__4776: logic__4776
-case__400: case__400
-logic__4840: logic__4840
-datapath__295: datapath__295
-reg__918: reg__918
-logic__4086: logic__4086
-logic__6562: logic__6562
-TLBusBypassBar: TLBusBypassBar
-case__1002: case__1002
-logic__879: logic__879
-reg__815: reg__815
-case__1107: case__1107
-logic__3722: logic__3722
-logic__6036: logic__6036
-datapath__297: datapath__297
-logic__4471: logic__4471
-case__1100: case__1100
-logic__4711: logic__4711
-reg__1476: reg__1087
-reg__1474: reg__1089
-logic__726: logic__726
-keep__9: keep__9
-reg__1536: reg__926
-logic__9689: logic__2517
-logic__5649: logic__5649
-case__566: case__566
-case__165: case__165
-case__1174: case__1174
-reg__839: reg__839
-logic__1945: logic__1945
-logic__6513: logic__6513
-logic__6842: logic__6842
-reg__497: reg__497
-datapath__418: datapath__418
-case__1428: case__1428
-logic__9883: logic__1292
-muxpart__204: muxpart__204
-bit_gen: bit_gen
-logic__4822: logic__4822
-datapath__346: datapath__346
-logic__3759: logic__3759
-case__276: case__276
-case__659: case__659
-logic__4760: logic__4760
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__6: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__939: logic__939
-logic__4648: logic__4648
-logic__2601: logic__2601
-logic__7798: logic__7798
-case__674: case__674
-logic__4712: logic__4712
-reg__244: reg__244
-logic__9685: logic__2521
-logic__2833: logic__2833
-logic__1335: logic__1335
-logic__9031: logic__9031
-logic__1558: logic__1558
-logic__7961: logic__7961
-datapath__60: datapath__60
-logic__4780: logic__4780
-logic__7634: logic__7634
-logic__5988: logic__5988
-reg__785: reg__785
-reg__1439: reg__123
-datapath__25: datapath__25
-reg__1463: reg__1229
-logic__7527: logic__7527
-reg__278: reg__278
-logic__8774: logic__8774
-reg__1405: reg__1405
-logic__4770: logic__4770
-case__1794: case__1611
-reg__1572: reg__926
-logic__1703: logic__1703
-logic__2874: logic__2874
-logic__2062: logic__2062
-logic__3029: logic__3029
-case__292: case__292
-logic__9702: logic__2480
-reg__33: reg__33
-datapath__67: datapath__67
-logic__4784: logic__4784
-logic__5974: logic__5974
-logic__3101: logic__3101
-muxpart__162: muxpart__162
-logic__4930: logic__4930
-logic__8201: logic__8201
-logic__7353: logic__7353
-case__324: case__324
-muxpart__38: muxpart__38
-datapath__650: datapath__650
-logic__5868: logic__5868
-logic__7306: logic__7306
-reg__1083: reg__1083
-logic__5490: logic__5490
-logic__876: logic__876
-logic__8700: logic__8700
-logic__5069: logic__5069
-muxpart__259: muxpart__259
-case__62: case__62
-logic__3118: logic__3118
-reg__1169: reg__1169
-logic__6559: logic__6559
-logic__7859: logic__7859
-logic__7504: logic__7504
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__21: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6636: logic__6636
-logic__9770: logic__2402
-reg__898: reg__898
-logic__3457: logic__3457
-logic__2200: logic__2200
-reg__656: reg__656
-logic__8195: logic__8195
-case__405: case__405
-logic__5577: logic__5577
-muxpart__5: muxpart__5
-reg__952: reg__952
-logic__1180: logic__1180
-reg__566: reg__566
-reg__1256: reg__1256
-reg__1352: reg__1352
-logic__9343: logic__9343
-muxpart__22: muxpart__22
-logic__7123: logic__7123
-extrom__4: extrom__1
-case__1751: case__660
-logic__2797: logic__2797
-logic__3129: logic__3129
-logic__4752: logic__4752
-reg__680: reg__680
-case__658: case__658
-reg__1431: reg__1431
-logic__9301: logic__9301
-logic__10: logic__10
-reg__1504: reg__925
-logic__2330: logic__2330
-logic__1932: logic__1932
-reg__108: reg__108
-case__1377: case__1377
-logic__7439: logic__7439
-logic__6808: logic__6808
-case__339: case__339
-logic__8024: logic__8024
-case__507: case__507
-logic__3831: logic__3831
-case__383: case__383
-case__959: case__959
-case__862: case__862
-sample_align: sample_align
-case__935: case__935
-logic__8973: logic__8973
-logic__6517: logic__6517
-datapath__186: datapath__186
-logic__4182: logic__4182
-logic__3898: logic__3898
-DivSqrtRecFN_small: DivSqrtRecFN_small
-case__1762: case__727
-logic__3130: logic__3130
-logic__8299: logic__8299
-logic__4819: logic__4819
-case__1368: case__1368
-reg__439: reg__439
-reg__648: reg__648
-case__732: case__732
-datapath__81: datapath__81
-logic__9033: logic__9033
-reg__915: reg__915
-logic__1974: logic__1974
-logic__333: logic__333
-datapath__61: datapath__61
-LevelGateway__7: LevelGateway
-logic__6678: logic__6678
-case__255: case__255
-dsp48e1__22: dsp48e1__22
-reg__1305: reg__1305
-datapath__440: datapath__440
-datapath__478: datapath__478
-logic__1484: logic__1484
-logic__9783: logic__2355
-muxpart__74: muxpart__74
-logic__7382: logic__7382
-case__1425: case__1425
-logic__2050: logic__2050
-case__1674: case__1674
-logic__3515: logic__3515
-muxpart__255: muxpart__255
-reg__1394: reg__1394
-case__1558: case__1558
-logic__5840: logic__5840
-reg__1159: reg__1159
-reg__1126: reg__1126
-logic__5684: logic__5684
-logic__9757: logic__2446
-logic__9884: logic__1288
-logic__9156: logic__9156
-reg__919: reg__919
-logic__1244: logic__1244
-reg__406: reg__406
-logic__7445: logic__7445
-logic__195: logic__195
-logic__860: logic__860
-logic__3350: logic__3350
-datapath__144: datapath__144
-case__759: case__759
-logic__9706: logic__2474
-datapath__23: datapath__23
-reg__1286: reg__1286
-logic__7426: logic__7426
-reg__1338: reg__1338
-logic__2101: logic__2101
-logic__8262: logic__8262
-logic__9212: logic__9212
-reg__1527: reg__926
-datapath__233: datapath__233
-datapath__94: datapath__94
-datapath__334: datapath__334
-reg__392: reg__392
-logic__665: logic__665
-reg__962: reg__962
-logic__9650: logic__4587
-reg__145: reg__145
-datapath__600: datapath__600
-extladd__1: extladd__1
-logic__1482: logic__1482
-logic__4357: logic__4357
-case__1507: case__1507
-MulAddRecFNToRaw_postMul: MulAddRecFNToRaw_postMul
-logic__5152: logic__5152
-TLError_1: TLError_1
-reg__921: reg__921
-case__1493: case__1493
-logic__4889: logic__4889
-case__454: case__454
-logic__9051: logic__9051
-case__226: case__226
-datapath__205: datapath__205
-TLInterconnectCoupler_sbus_to_bus_named_cbus: TLInterconnectCoupler_sbus_to_bus_named_cbus
-keep__1: keep__1
-logic__6815: logic__6815
-logic__6602: logic__6602
-datapath__497: datapath__497
-datapath__660: datapath__660
-logic__5278: logic__5278
-logic__2117: logic__2117
-logic__2743: logic__2743
-RoundAnyRawFNToRecFN_1: RoundAnyRawFNToRecFN_1
-logic__3573: logic__3573
-logic__2811: logic__2811
-reg__364: reg__364
-logic__5867: logic__5867
-logic__6135: logic__6135
-case__265: case__265
-logic__4522: logic__4522
-logic__8206: logic__8206
-datapath__146: datapath__146
-logic__298: logic__298
-datapath__667: datapath__667
-logic__7735: logic__7735
-logic__2133: logic__2133
-reg__1586: reg__924
-datapath__744: datapath__137
-case__967: case__967
-muxpart__30: muxpart__30
-logic__6981: logic__6981
-case__1730: case__1730
-logic__5280: logic__5280
-extladd__2: extladd__2
-logic__7176: logic__7176
-reg__251: reg__251
-LF_code: LF_code
-datapath__305: datapath__305
-case__456: case__456
-datapath__435: datapath__435
-logic__7699: logic__7699
-case__922: case__922
-case__852: case__852
-logic__2191: logic__2191
-datapath__194: datapath__194
-case__513: case__513
-logic__9501: logic__9501
-reg__308: reg__308
-logic__9855: logic__2173
-logic__2153: logic__2153
-case__483: case__483
-ram_2x77: ram_2x77
-logic__9016: logic__9016
-case__273: case__273
-datapath__520: datapath__520
-reg__932: reg__932
-case__465: case__465
-reg__714: reg__714
-logic__8141: logic__8141
-reg__81: reg__81
-logic__5559: logic__5559
-case__1767: case__524
-logic__9204: logic__9204
-logic__2474: logic__2474
-datapath__220: datapath__220
-datapath__573: datapath__573
-logic__2427: logic__2427
-reg__876: reg__876
-logic__3359: logic__3359
-case__22: case__22
-case__850: case__850
-datapath__174: datapath__174
-reg__1207: reg__1207
-IntXbar_i3_o1: IntXbar_i3_o1
-reg__35: reg__35
-logic__7097: logic__7097
-datapath__255: datapath__255
-case__602: case__602
-keep__26: keep__15
-logic__2871: logic__2871
-datapath__69: datapath__69
-case__1045: case__1045
-logic__5981: logic__5981
-reg__1442: reg__206
-logic__4790: logic__4790
-muxpart__225: muxpart__225
-logic__6275: logic__6275
-DTLB: DTLB
-logic__5317: logic__5317
-logic__4497: logic__4497
-logic__6648: logic__6648
-reg__1554: reg__926
-reg__1216: reg__1216
-datapath__393: datapath__393
-case__1246: case__1246
-logic__4917: logic__4917
-logic__2342: logic__2342
-logic__5824: logic__5824
-datapath__558: datapath__558
-logic__2239: logic__2239
-keep__2: keep__2
-logic__9833: logic__2225
-reg__1559: reg__924
-muxpart__57: muxpart__57
-case__1605: case__1605
-AsyncValidSync__3: AsyncValidSync
-reg__1140: reg__1140
-case__498: case__498
-datapath__128: datapath__128
-case__677: case__677
-logic__6653: logic__6653
-case__332: case__332
-logic__7219: logic__7219
-reg__431: reg__431
-logic__4340: logic__4340
-logic__4927: logic__4927
-logic__4501: logic__4501
-reg__830: reg__830
-case__1366: case__1366
-muxpart__127: muxpart__127
-case__322: case__322
-reg__1277: reg__1277
-logic__9914: logic__8197
-reg__1329: reg__1329
-logic__9527: logic__9527
-logic__1893: logic__1893
-Repeater_TLBundleA_a12d64s2k1z3u: Repeater_TLBundleA_a12d64s2k1z3u
-reg__980: reg__980
-logic__3778: logic__3778
-case__1021: case__1021
-case__395: case__395
-logic__9560: logic__9560
-muxpart__175: muxpart__175
-logic__8092: logic__8092
-TLToAPB: TLToAPB
-reg__732: reg__732
-logic__6016: logic__6016
-logic__4083: logic__4083
-logic__8484: logic__8484
-reg__1094: reg__1094
-logic__2765: logic__2765
-logic__6339: logic__6339
-case__1689: case__1689
-logic__6866: logic__6866
-reg__320: reg__320
-case__1672: case__1672
-case__1169: case__1169
-logic__1698: logic__1698
-Repeater_TLBundleA_a29d64s2k1z3u: Repeater_TLBundleA_a29d64s2k1z3u
-logic__8212: logic__8212
-case__1099: case__1099
-datapath__301: datapath__301
-datapath__490: datapath__490
-case__945: case__945
-logic__695: logic__695
-logic__2789: logic__2789
-datapath__688: datapath__688
-case__1503: case__1503
-logic__6652: logic__6652
-logic__6843: logic__6843
-logic__4792: logic__4792
-logic__9753: logic__2458
-logic__5951: logic__5951
-logic__9961: logic__1110
-dsp48e1__10: dsp48e1__10
-muxpart__247: muxpart__247
-datapath__640: datapath__640
-logic__8764: logic__8764
-dsp48e1__21: dsp48e1__21
-case__803: case__803
-logic__1021: logic__1021
-muxpart__221: muxpart__221
-case__1131: case__1131
-logic__7278: logic__7278
-reg__472: reg__472
-logic__2930: logic__2930
-divider_fsm: divider_fsm
-logic__9869: logic__2151
-logic__5845: logic__5845
-logic__1651: logic__1651
-logic__2052: logic__2052
-logic__7616: logic__7616
-reg__937: reg__937
-cdc_fifo_gray_src: cdc_fifo_gray_src
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__31: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__78: datapath__78
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__28: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-muxpart__319: muxpart__319
-case__829: case__829
-case__1729: case__1729
-logic__8341: logic__8341
-logic__3920: logic__3920
-reg__335: reg__335
-logic__8959: logic__8959
-logic__7966: logic__7966
-logic__4644: logic__4644
-logic__7315: logic__7315
-reg__829: reg__829
-logic__7921: logic__7921
-logic__1101: logic__1101
-logic__3474: logic__3474
-logic__8898: logic__8898
-logic__7071: logic__7071
-logic__2984: logic__2984
-case__1212: case__1212
-case__1193: case__1193
-case__1150: case__1150
-logic__7254: logic__7254
-logic__3881: logic__3881
-datapath__221: datapath__221
-logic__3331: logic__3331
-case__1049: case__1049
-logic__7343: logic__7343
-reg__502: reg__502
-case__645: case__645
-reg__1492: reg__1063
-reg__1489: reg__926
-logic__2599: logic__2599
-logic__310: logic__310
-reg__1400: reg__1400
-logic__3280: logic__3280
-logic__2479: logic__2479
-datapath__48: datapath__48
-case__1500: case__1500
-logic__1707: logic__1707
-datapath__729: datapath__270
-logic__6033: logic__6033
-logic__7807: logic__7807
-logic__3059: logic__3059
-muxpart__45: muxpart__45
-reg__1520: reg__924
-logic__5941: logic__5941
-datapath__488: datapath__488
-logic__907: logic__907
-reg__618: reg__618
-case__1171: case__1171
-logic__5844: logic__5844
-logic__3796: logic__3796
-logic__899: logic__899
-case__1707: case__1707
-logic__5694: logic__5694
-logic__1320: logic__1320
-logic__3643: logic__3643
-case__742: case__742
-datapath__21: datapath__21
-logic__6785: logic__6785
-reg__1571: reg__924
-case__1235: case__1235
-reg__465: reg__465
-case__35: case__35
-logic__8293: logic__8293
-reg__104: reg__104
-logic__6558: logic__6558
-reg__1502: reg__924
-logic__1734: logic__1734
-logic__3355: logic__3355
-logic__7180: logic__7180
-reg__1435: reg__1435
-logic__8411: logic__8411
-logic__6088: logic__6088
-logic__9880: logic__1297
-case__1138: case__1138
-reg__206: reg__206
-logic__4481: logic__4481
-logic__787: logic__787
-logic__6657: logic__6657
-reg__1618: reg__119
-logic__8581: logic__8581
-TLDebugModuleInnerAsync: TLDebugModuleInnerAsync
-reg__1436: reg__869
-logic__7119: logic__7119
-datapath__195: datapath__195
-case__271: case__271
-datapath__106: datapath__106
-case__805: case__805
-logic__2727: logic__2727
-logic__5990: logic__5990
-logic__9412: logic__9412
-reg__264: reg__264
-case__368: case__368
-logic__9146: logic__9146
-datapath__433: datapath__433
-logic__4429: logic__4429
-case__211: case__211
-logic__8892: logic__8892
-logic__9968: logic__910
-logic__8672: logic__8672
-logic__7820: logic__7820
-datapath__654: datapath__654
-logic__5825: logic__5825
-reg__297: reg__297
-logic__2314: logic__2314
-logic__1024: logic__1024
-ram__4: ram__4
-reg__610: reg__610
-logic__3597: logic__3597
-case__285: case__285
-reg__16: reg__16
-LevelGateway__2: LevelGateway
-logic__2224: logic__2224
-logic__7134: logic__7134
-reg__812: reg__812
-datapath__53: datapath__53
-logic__7040: logic__7040
-case__575: case__575
-reg__864: reg__864
-logic__7415: logic__7415
-reg__240: reg__240
-logic__9240: logic__9240
-logic__4511: logic__4511
-logic__4423: logic__4423
-logic__2851: logic__2851
-logic__2473: logic__2473
-case__1067: case__1067
-case__560: case__560
-reg__859: reg__859
-datapath__7: datapath__7
-case__1176: case__1176
-datapath__642: datapath__642
-muxpart__182: muxpart__182
-reg__1190: reg__1190
-reg__899: reg__899
-case__641: case__641
-case__668: case__668
-logic__6139: logic__6139
-case__262: case__262
-logic__5510: logic__5510
-reg__330: reg__330
-logic__8: logic__8
-case__1743: case__1743
-muxpart__251: muxpart__251
-logic__623: logic__623
-reg__70: reg__70
-case__353: case__353
-logic__9765: logic__2415
-logic__7260: logic__7260
-datapath__216: datapath__216
-logic__9635: logic__3613
-case__338: case__338
-logic__4492: logic__4492
-logic__6734: logic__6734
-case__885: case__885
-logic__3971: logic__3971
-logic__3443: logic__3443
-TLWidthWidget1: TLWidthWidget1
-logic__966: logic__966
-datapath__592: datapath__592
-case__1673: case__1673
-case__726: case__726
-case__34: case__34
-logic__9517: logic__9517
-case__418: case__418
-logic__2897: logic__2897
-case__1378: case__1378
-logic__5176: logic__5176
-reg__1283: reg__1283
-case__163: case__163
-datapath__734: datapath__265
-addsub__2: addsub__2
-logic__2002: logic__2002
-case__1022: case__1022
-case__956: case__956
-logic__5598: logic__5598
-logic__3757: logic__3757
-FPGASPIClockSinkDomain: FPGASPIClockSinkDomain
-logic__9928: logic__6773
-reg__1595: reg__874
-logic__6508: logic__6508
-case__884: case__884
-logic__9773: logic__2393
-case__985: case__985
-AsyncResetSynchronizerShiftReg_w1_d3_i0__6: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__8624: logic__8624
-logic__6032: logic__6032
-logic__9302: logic__9302
-logic__2125: logic__2125
-logic__2586: logic__2586
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__10: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-Queue1_TLBundleD_a29d32s7k1z2u: Queue1_TLBundleD_a29d32s7k1z2u
-logic__6735: logic__6735
-logic__5134: logic__5134
-case__1068: case__1068
-logic__6673: logic__6673
-case__1013: case__1013
-logic__1292: logic__1292
-logic__778: logic__778
-reg__1197: reg__1197
-logic__6794: logic__6794
-logic__2095: logic__2095
-datapath__380: datapath__380
-logic__6109: logic__6109
-logic__2835: logic__2835
-reg__1465: reg__1089
-case__1418: case__1418
-case__107: case__107
-datapath__406: datapath__406
-muxpart__235: muxpart__235
-datapath__634: datapath__634
-logic__4941: logic__4941
-logic__775: logic__775
-logic__5841: logic__5841
-keep__12: keep__12
-logic__4461: logic__4461
-case__907: case__907
-reg__698: reg__698
-logic__5707: logic__5707
-logic__6143: logic__6143
-logic__887: logic__887
-logic__9900: logic__8885
-reg__258: reg__258
-reg__119: reg__119
-datapath__628: datapath__628
-logic__4189: logic__4189
-logic__5206: logic__5206
-datapath__74: datapath__74
-case__1789: case__1616
-TLWidthWidget8_4: TLWidthWidget8_4
-logic__7133: logic__7133
-case__1335: case__1335
-case__1084: case__1084
-datapath__719: datapath__322
-logic__3646: logic__3646
-acq_nco_carr: acq_nco_carr
-ScratchpadSlavePort: ScratchpadSlavePort
-logic__3521: logic__3521
-logic__9960: logic__1111
-logic__4498: logic__4498
-logic__7495: logic__7495
-logic__3522: logic__3522
-logic__4682: logic__4682
-logic__4354: logic__4354
-datapath: datapath
-reg__974: reg__974
-case__974: case__974
-case__906: case__906
-case__1166: case__1166
-logic__5961: logic__5961
-logic__3750: logic__3750
-logic__3066: logic__3066
-logic__4046: logic__4046
-logic__1921: logic__1921
-logic__8058: logic__8058
-reg__759: reg__759
-keep__38: keep__15
-logic__6926: logic__6926
-logic__4156: logic__4156
-case__24: case__24
-logic__4667: logic__4667
-logic__7112: logic__7112
-logic__2322: logic__2322
-logic__2268: logic__2268
-logic__4262: logic__4262
-logic__9735: logic__2504
-reg__299: reg__299
-logic__2347: logic__2347
-reg__476: reg__476
-case__445: case__445
-logic__7894: logic__7894
-logic__7409: logic__7409
-case__600: case__600
-logic__9153: logic__9153
-logic__5060: logic__5060
-case__111: case__111
-logic__6839: logic__6839
-logic__4683: logic__4683
-case__58: case__58
-logic__7802: logic__7802
-logic__7615: logic__7615
-reg__808: reg__808
-reg__1556: reg__924
-case__261: case__261
-logic__3484: logic__3484
-case__620: case__620
-reg__176: reg__176
-case__193: case__193
-logic__7801: logic__7801
-reg__50: reg__50
-logic__496: logic__496
-logic__118: logic__118
-reg__521: reg__521
-case__782: case__782
-datapath__85: datapath__85
-logic__8513: logic__8513
-logic__3566: logic__3566
-logic__6073: logic__6073
-binary_to_gray__1: binary_to_gray
-logic__9713: logic__2557
-logic__1298: logic__1298
-case__1044: case__1044
-muxpart__186: muxpart__186
-logic__2725: logic__2725
-logic__113: logic__113
-case__1583: case__1583
-logic__4355: logic__4355
-case__587: case__587
-logic__5637: logic__5637
-logic__7375: logic__7375
-logic__1796: logic__1796
-logic__3779: logic__3779
-logic__2542: logic__2542
-logic__169: logic__169
-logic__9621: logic__3636
-logic__5682: logic__5682
-reg__458: reg__458
-logic__7429: logic__7429
-logic__3229: logic__3229
-reg__959: reg__959
-reg__1607: reg__154
-logic__2501: logic__2501
-logic__2151: logic__2151
-case__396: case__396
-reg__236: reg__236
-case__861: case__861
-logic__6078: logic__6078
-logic__3708: logic__3708
-datapath__581: datapath__581
-datapath__11: datapath__11
-case__1011: case__1011
-TLPLIC: TLPLIC
-logic__6818: logic__6818
-reg__1302: reg__1302
-datapath__763: datapath__159
-logic__8979: logic__8979
-logic__4009: logic__4009
-logic__1574: logic__1574
-case__1570: case__1570
-logic__3642: logic__3642
-logic__4052: logic__4052
-datapath__214: datapath__214
-case__692: case__692
-AsyncValidSync__6: AsyncValidSync
-muxpart__375: muxpart__375
-extram: extram
-logic__2981: logic__2981
-logic__3524: logic__3524
-logic__5583: logic__5583
-logic__5950: logic__5950
-datapath__746: datapath__135
-muxpart__222: muxpart__222
-case__218: case__218
-reg__986: reg__986
-reg__1350: reg__1350
-case__1688: case__1688
-datapath__653: datapath__653
-datapath__730: datapath__269
-case__864: case__864
-reg__1113: reg__1113
-reg__479: reg__479
-reg__1473: reg__1087
-logic__6923: logic__6923
-datapath__111: datapath__111
-reg__1311: reg__1311
-logic__9812: logic__2272
-logic__2278: logic__2278
-reg__1447: reg__1341
-case__567: case__567
-LF_carr: LF_carr
-logic__7539: logic__7539
-reg__941: reg__941
-logic__9000: logic__9000
-logic__8800: logic__8800
-reg__1555: reg__925
-logic__1805: logic__1805
-muxpart: muxpart
-logic__5408: logic__5408
-reg__1018: reg__1018
-logic__5851: logic__5851
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__29: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-keep__50: keep__11
-logic__1917: logic__1917
-logic__6514: logic__6514
-case__1498: case__1498
-logic__2154: logic__2154
-case__588: case__588
-logic__9868: logic__2152
-case__144: case__144
-case__840: case__840
-case__157: case__157
-logic__7678: logic__7678
-logic__4386: logic__4386
-logic__6550: logic__6550
-logic__336: logic__336
-case__387: case__387
-logic__9940: logic__1160
-case__1492: case__1492
-logic__4126: logic__4126
-reg__1614: reg__123
-reg__860: reg__860
-case__920: case__920
-case__238: case__238
-case__1345: case__1345
-logic__7105: logic__7105
-logic__9725: logic__2522
-logic__6669: logic__6669
-datapath__49: datapath__49
-case__1737: case__1737
-case__1332: case__1332
-case__1265: case__1265
-reg__80: reg__80
-logic__3701: logic__3701
-reg__75: reg__75
-reg__769: reg__769
-logic__8266: logic__8266
-logic__7062: logic__7062
-logic__3223: logic__3223
-reg__629: reg__629
-reg__951: reg__951
-logic__3336: logic__3336
-logic__5258: logic__5258
-reg__79: reg__79
-case__615: case__615
-case__714: case__714
-logic__8074: logic__8074
-logic__7457: logic__7457
-logic__7344: logic__7344
-case__1001: case__1001
-logic__3353: logic__3353
-logic__2744: logic__2744
-logic__4765: logic__4765
-datapath__388: datapath__388
-case__718: case__718
-logic__8288: logic__8288
-logic__8867: logic__8867
-logic__4460: logic__4460
-logic__7314: logic__7314
-case__1613: case__1613
-case__749: case__749
-datapath__349: datapath__349
-case__416: case__416
-reg__1278: reg__1278
-reg__777: reg__777
-TLBuffer_a32d64s2k1z3u_1: TLBuffer_a32d64s2k1z3u_1
-logic__7451: logic__7451
-logic__9140: logic__9140
-logic__3694: logic__3694
-reg__487: reg__487
-logic__4833: logic__4833
-datapath__20: datapath__20
-case__891: case__891
-case__952: case__952
-datapath__597: datapath__597
-datapath__692: datapath__692
-logic__2302: logic__2302
-logic__4348: logic__4348
-case__1136: case__1136
-reg__1298: reg__1298
-case__326: case__326
-logic__4816: logic__4816
-reg__638: reg__638
-logic__7125: logic__7125
-logic__3301: logic__3301
-logic__1675: logic__1675
-reg__818: reg__818
-reg__107: reg__107
-logic__648: logic__648
-case__420: case__420
-logic__5220: logic__5220
-reg__457: reg__457
-case__796: case__796
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__5: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__5965: logic__5965
-logic__4336: logic__4336
-case__1304: case__1304
-logic__3912: logic__3912
-logic__6312: logic__6312
-logic__3780: logic__3780
-logic__3802: logic__3802
-datapath__563: datapath__563
-case__1598: case__1598
-logic__8173: logic__8173
-reg__1548: reg__926
-case__515: case__515
-case__124: case__124
-datapath__142: datapath__142
-reg__1610: reg__151
-logic__9623: logic__3632
-case__733: case__733
-logic__7266: logic__7266
-datapath__77: datapath__77
-reg__1134: reg__1134
-logic__9663: logic__4559
-logic__7888: logic__7888
-logic__7463: logic__7463
-datapath__208: datapath__208
-logic__276: logic__276
-reg__631: reg__631
-logic__9854: logic__2178
-logic__5465: logic__5465
-logic__7717: logic__7717
-logic__1412: logic__1412
-case__962: case__962
-logic__8296: logic__8296
-case__1178: case__1178
-logic__6984: logic__6984
-logic__7747: logic__7747
-logic__4955: logic__4955
-reg__1312: reg__1312
-logic__7245: logic__7245
-case__30: case__30
-reg__1459: reg__1229
-reg__1230: reg__1230
-logic__2207: logic__2207
-logic__8277: logic__8277
-case__1289: case__1289
-logic__4545: logic__4545
-datapath__559: datapath__559
-logic__6171: logic__6171
-logic__2327: logic__2327
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__16: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-binary_to_gray: binary_to_gray
-case__688: case__688
-logic__1109: logic__1109
-double_ff_syn__2: double_ff_syn
-datapath__358: datapath__358
-case__1139: case__1139
-AsyncValidSync: AsyncValidSync
-logic__6801: logic__6801
-logic__5624: logic__5624
-datapath__681: datapath__681
-logic__3615: logic__3615
-logic__6824: logic__6824
-reg__1219: reg__1219
-MulAddRecFNToRaw_preMul_1: MulAddRecFNToRaw_preMul_1
-logic__7149: logic__7149
-dsp48e1__16: dsp48e1__16
-logic__9822: logic__2250
-logic__1582: logic__1582
-datapath__362: datapath__362
-logic__8321: logic__8321
-datapath__79: datapath__79
-logic__2999: logic__2999
-case__287: case__287
-reg__927: reg__927
-reg__1184: reg__1184
-datapath__414: datapath__414
-logic__4411: logic__4411
-case__1152: case__1152
-logic__9764: logic__2422
-logic__6585: logic__6585
-logic__5257: logic__5257
-datapath__212: datapath__212
-logic__757: logic__757
-logic__2720: logic__2720
-case__535: case__535
-case__1786: case__1619
-logic__4768: logic__4768
-muxpart__178: muxpart__178
-logic__9043: logic__9043
-keep__51: keep__10
-datapath__761: datapath__161
-logic__5378: logic__5378
-reg__4: reg__4
-reg__988: reg__988
-reg__287: reg__287
-reg__120: reg__120
-datapath__117: datapath__117
-logic__954: logic__954
-keep__17: keep__17
-case__1057: case__1057
-logic__1818: logic__1818
-datapath__689: datapath__689
-case__1215: case__1215
-logic__5084: logic__5084
-logic__4302: logic__4302
-case__827: case__827
-datapath__588: datapath__588
-datapath__394: datapath__394
-case__1567: case__1567
-reg__531: reg__531
-reg__695: reg__695
-reg__1583: reg__924
-logic__886: logic__886
-reg__683: reg__683
-case__1779: case__512
-logic__2891: logic__2891
-reg__1154: reg__1154
-case__1175: case__1175
-case__1132: case__1132
-reg__160: reg__160
-case__423: case__423
-case__364: case__364
-case__934: case__934
-logic__7214: logic__7214
-reg__280: reg__280
-Repeater_TLBundleD_a32d64s1k1z4u: Repeater_TLBundleD_a32d64s1k1z4u
-case__1483: case__1483
-logic__2838: logic__2838
-logic__5665: logic__5665
-datapath__264: datapath__264
-reg__1031: reg__1031
-logic__3117: logic__3117
-logic__6018: logic__6018
-logic__2932: logic__2932
-logic__6672: logic__6672
-logic__784: logic__784
-logic__3347: logic__3347
-datapath__549: datapath__549
-logic__4680: logic__4680
-AsyncValidSync__2: AsyncValidSync
-logic__7724: logic__7724
-datapath__501: datapath__501
-reg__159: reg__159
-logic__7666: logic__7666
-logic__9867: logic__2153
-datapath__88: datapath__88
-reg__1170: reg__1170
-logic__3152: logic__3152
-logic__9557: logic__9557
-case__1362: case__1362
-reg__630: reg__630
-case__486: case__486
-logic__2854: logic__2854
-datapath__330: datapath__330
-logic__9879: logic__1298
-reg__1413: reg__1413
-reg__1055: reg__1055
-logic__4495: logic__4495
-reg__660: reg__660
-logic__3564: logic__3564
-logic__7188: logic__7188
-ram__15: ram
-logic__6279: logic__6279
-logic__7383: logic__7383
-logic__2253: logic__2253
-logic__2271: logic__2271
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__26: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6793: logic__6793
-logic__4793: logic__4793
-logic__5236: logic__5236
-case__1399: case__1399
-muxpart__201: muxpart__201
-logic__1208: logic__1208
-logic__3511: logic__3511
-RoundAnyRawFNToRecFN__1: RoundAnyRawFNToRecFN
-reg__847: reg__847
-case__657: case__657
-case__863: case__863
-Queue2_TLBundleD_a32d64s1k1z4u__1: Queue2_TLBundleD_a32d64s1k1z4u
-logic__5177: logic__5177
-reg__1264: reg__1264
-logic__8199: logic__8199
-reg__1508: reg__924
-logic__6864: logic__6864
-case__999: case__999
-reg__1355: reg__1355
-logic__3505: logic__3505
-datapath__557: datapath__557
-reg__307: reg__307
-logic__5163: logic__5163
-reg__10: reg__10
-reg__960: reg__960
-logic__1800: logic__1800
-logic__4877: logic__4877
-TLInterconnectCoupler_cbus_to_clint: TLInterconnectCoupler_cbus_to_clint
-logic__9633: logic__3615
-reg__989: reg__989
-logic__6752: logic__6752
-datapath__705: datapath__705
-logic__9655: logic__4576
-datapath__140: datapath__140
-logic__6645: logic__6645
-logic__7736: logic__7736
-case__237: case__237
-case__534: case__534
-logic__3031: logic__3031
-logic__2393: logic__2393
-reg__1108: reg__1108
-logic__1779: logic__1779
-logic__8944: logic__8944
-logic__9342: logic__9342
-logic__6663: logic__6663
-INToRecFN_1: INToRecFN_1
-PLICClockSinkDomain: PLICClockSinkDomain
-logic__6014: logic__6014
-logic__7927: logic__7927
-logic__4382: logic__4382
-logic__2272: logic__2272
-logic__234: logic__234
-logic__917: logic__917
-case__1255: case__1255
-logic__1496: logic__1496
-logic__1351: logic__1351
-case__744: case__744
-logic__3975: logic__3975
-case__979: case__979
-reg__1261: reg__1261
-logic__156: logic__156
-case__914: case__914
-case__421: case__421
-reg__641: reg__641
-logic__703: logic__703
-case__201: case__201
-reg__257: reg__257
-logic__9011: logic__9011
-logic__526: logic__526
-logic__7117: logic__7117
-reg__372: reg__372
-AsyncValidSync__22: AsyncValidSync
-logic__5552: logic__5552
-logic__1811: logic__1811
-reg__1603: reg__158
-logic__6659: logic__6659
-case__1343: case__1343
-Queue2_TLBundleA_a32d64s2k1z3u: Queue2_TLBundleA_a32d64s2k1z3u
-datapath__201: datapath__201
-reg__1064: reg__1064
-logic__7542: logic__7542
-logic__6554: logic__6554
-datapath__280: datapath__280
-logic__6859: logic__6859
-signinv: signinv
-reg__222: reg__222
-reg__1183: reg__1183
-logic__2693: logic__2693
-logic__1643: logic__1643
-logic__2972: logic__2972
-logic__9209: logic__9209
-reg__533: reg__533
-case__136: case__136
-keep__37: keep__16
-logic__9829: logic__2235
-dsp48e1__23: dsp48e1__23
-logic__5953: logic__5953
-case__1441: case__1441
-logic__3057: logic__3057
-reg__1180: reg__1180
-muxpart__169: muxpart__169
-logic__9952: logic__1130
-reg__713: reg__713
-case__1214: case__1214
-logic__7781: logic__7781
-logic__3037: logic__3037
-datapath__354: datapath__354
-logic__5548: logic__5548
-case__128: case__128
-logic__6927: logic__6927
-logic__6315: logic__6315
-logic__4634: logic__4634
-case__1629: case__1629
-logic__2817: logic__2817
-extram__4: extram__4
-reg__269: reg__269
-reg__365: reg__365
-muxpart__59: muxpart__59
-logic__5365: logic__5365
-logic__3220: logic__3220
-logic__1635: logic__1635
-logic__9768: logic__2410
-logic__7583: logic__7583
-datapath__351: datapath__351
-reg__1203: reg__1203
-logic__7244: logic__7244
-logic__8029: logic__8029
-reg__985: reg__985
-reg__234: reg__234
-logic__3124: logic__3124
-logic__6072: logic__6072
-reg__357: reg__357
-logic__9834: logic__2224
-logic__6115: logic__6115
-logic__7843: logic__7843
-RVCExpander: RVCExpander
-reg__1263: reg__1263
-logic__7013: logic__7013
-datapath__199: datapath__199
-logic__1182: logic__1182
-logic__2086: logic__2086
-case__1118: case__1118
-logic__9890: logic__9088
-logic__1205: logic__1205
-reg__343: reg__343
-reg__931: reg__931
-reg__1430: reg__1430
-logic__9411: logic__9411
-logic__5597: logic__5597
-eth_rf_async_fifo: eth_rf_async_fifo
-datapath__579: datapath__579
-logic__3320: logic__3320
-reg__529: reg__529
-logic__9640: logic__3598
-logic__3237: logic__3237
-logic__5695: logic__5695
-logic__2644: logic__2644
-reg__1223: reg__1223
-reg__1326: reg__1326
-logic__8368: logic__8368
-logic__6714: logic__6714
-NonSyncResetSynchronizerPrimitiveShiftReg_d3: NonSyncResetSynchronizerPrimitiveShiftReg_d3
-reg__494: reg__494
-reg__800: reg__800
-datapath__177: datapath__177
-logic__9684: logic__2522
-logic__4002: logic__4002
-muxpart__49: muxpart__49
-logic__7242: logic__7242
-datapath__315: datapath__315
-logic__7196: logic__7196
-logic__590: logic__590
-logic__7294: logic__7294
-reg__42: reg__42
-case__393: case__393
-keep__22: keep__16
-logic__4047: logic__4047
-logic__4387: logic__4387
-datapath__691: datapath__691
-logic__7673: logic__7673
-logic__4900: logic__4900
-logic__9313: logic__9313
-muxpart__234: muxpart__234
-logic__5352: logic__5352
-logic__1697: logic__1697
-DivSqrtRecFNToRaw_small: DivSqrtRecFNToRaw_small
-logic__4176: logic__4176
-logic__8232: logic__8232
-logic__9660: logic__4565
-logic__6829: logic__6829
-logic__4120: logic__4120
-logic__9878: logic__1302
-logic__3322: logic__3322
-case__1722: case__1722
-logic__4151: logic__4151
-logic__3919: logic__3919
-logic__1005: logic__1005
-datapath__28: datapath__28
-logic__3574: logic__3574
-reg__1085: reg__1085
-reg__171: reg__171
-reg__1487: reg__1088
-case__1609: case__1609
-reg__1050: reg__1050
-reg__778: reg__778
-reg__653: reg__653
-logic__7195: logic__7195
-logic__511: logic__511
-logic__7449: logic__7449
-case__1025: case__1025
-logic__1302: logic__1302
-logic__3869: logic__3869
-case__145: case__145
-case__1059: case__1059
-logic__5476: logic__5476
-logic__5959: logic__5959
-logic__9893: logic__9081
-case__1618: case__1618
-logic__7166: logic__7166
-logic__1477: logic__1477
-reg__1089: reg__1089
-case__1576: case__1576
-logic__9876: logic__1304
-logic__2757: logic__2757
-reg__5: reg__5
-case__569: case__569
-datapath__541: datapath__541
-logic__1676: logic__1676
-case__510: case__510
-logic__986: logic__986
-logic__9646: logic__4598
-logic__6831: logic__6831
-logic__1427: logic__1427
-logic__9430: logic__9430
-logic__2510: logic__2510
-trck_top: trck_top
-logic__1248: logic__1248
-AsyncValidSync__11: AsyncValidSync
-reg__194: reg__194
-reg__173: reg__173
-muxpart__248: muxpart__248
-reg__930: reg__930
-logic__9460: logic__9460
-case__1739: case__1739
-logic__168: logic__168
-reg__499: reg__499
-logic__281: logic__281
-logic__7104: logic__7104
-reg__887: reg__887
-logic__2189: logic__2189
-reg__1332: reg__1332
-logic__2605: logic__2605
-logic__7295: logic__7295
-logic__6980: logic__6980
-logic__6015: logic__6015
-reg__950: reg__950
-logic__2719: logic__2719
-logic__1280: logic__1280
-logic__7434: logic__7434
-logic__3106: logic__3106
-TLWidthWidget8: TLWidthWidget8
-logic__5589: logic__5589
-case__417: case__417
-datapath__273: datapath__273
-logic__4713: logic__4713
-datapath__161: datapath__161
-reg__410: reg__410
-case__197: case__197
-datapath__89: datapath__89
-logic__3801: logic__3801
-case__582: case__582
-logic__5103: logic__5103
-logic__8669: logic__8669
-PMAChecker__1: PMAChecker
-logic__2410: logic__2410
-logic__669: logic__669
-logic__8941: logic__8941
-case__686: case__686
-logic__6311: logic__6311
-case__1111: case__1111
-reg__1545: reg__926
-logic__9929: logic__6768
-logic__1145: logic__1145
-reg__1616: reg__121
-reg__1254: reg__1254
-logic__4467: logic__4467
-datapath__504: datapath__504
-logic__4113: logic__4113
-cordic_atan_one_stage__parameterized0__1: cordic_atan_one_stage__parameterized0
-logic__5068: logic__5068
-case__225: case__225
-case__766: case__766
-logic__270: logic__270
-logic__8976: logic__8976
-reg__350: reg__350
-logic__7253: logic__7253
-reg__671: reg__671
-datapath__572: datapath__572
-logic__3307: logic__3307
-logic__9656: logic__4573
-logic__7234: logic__7234
-dsp48e1__3: dsp48e1__3
-logic__31: logic__31
-logic__5199: logic__5199
-datapath__385: datapath__385
-case__540: case__540
-logic__1031: logic__1031
-logic__8192: logic__8192
-case__1135: case__1135
-logic__7432: logic__7432
-logic__7317: logic__7317
-LevelGateway: LevelGateway
-reg__175: reg__175
-logic__5489: logic__5489
-muxpart__71: muxpart__71
-reg__563: reg__563
-reg__1013: reg__1013
-reg__999: reg__999
-case__639: case__639
-reg__1099: reg__1099
-case__665: case__665
-reg__1127: reg__1127
-logic__9576: logic__9576
-reg__385: reg__385
-reg__12: reg__12
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__14: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__7021: logic__7021
-logic__9213: logic__9213
-datapath__236: datapath__236
-case__1423: case__1423
-logic__3947: logic__3947
-logic__5954: logic__5954
-case__213: case__213
-logic__7627: logic__7627
-case__537: case__537
-logic__1611: logic__1611
-datapath__96: datapath__96
-case__1756: case__734
-reg__461: reg__461
-logic__7403: logic__7403
-reg__1598: reg__874
-case__1775: case__516
-logic__3585: logic__3585
-muxpart__26: muxpart__26
-logic__7577: logic__7577
-logic__4249: logic__4249
-logic__3009: logic__3009
-logic__8031: logic__8031
-logic__44: logic__44
-logic__9932: logic__6773
-case__701: case__701
-reg__1239: reg__1239
-logic__3507: logic__3507
-reg__1279: reg__1279
-case__984: case__984
-logic__5357: logic__5357
-double_ff_syn__4: double_ff_syn
-logic__9692: logic__2510
-logic__3575: logic__3575
-case__1268: case__1268
-logic__3134: logic__3134
-logic__646: logic__646
-AsyncResetSynchronizerShiftReg_w1_d3_i0__9: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__1523: logic__1523
-TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u: TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u
-case__1300: case__1300
-logic__8091: logic__8091
-logic__7351: logic__7351
-reg__904: reg__904
-datapath__137: datapath__137
-logic__766: logic__766
-case__768: case__768
-case__1638: case__1638
-case__1230: case__1230
-logic__8433: logic__8433
-logic__9007: logic__9007
-logic__2869: logic__2869
-datapath__267: datapath__267
-logic__9728: logic__2519
-logic__2182: logic__2182
-logic__509: logic__509
-case__1248: case__1248
-case__1064: case__1064
-reg__515: reg__515
-case__1765: case__724
-logic__6822: logic__6822
-TLInterconnectCoupler_sbus_from_bus_named_fbus: TLInterconnectCoupler_sbus_from_bus_named_fbus
-logic__7419: logic__7419
-logic__9674: logic__4523
-datapath__655: datapath__655
-logic__2023: logic__2023
-keep__49: keep__10
-reg__600: reg__600
-logic__5545: logic__5545
-logic__495: logic__495
-reg__1125: reg__1125
-case__121: case__121
-muxpart__66: muxpart__66
-case__822: case__822
-reg__1470: reg__1087
-case__484: case__484
-muxpart__171: muxpart__171
-logic__9811: logic__2275
-logic__730: logic__730
-logic__5254: logic__5254
-logic__9055: logic__9055
-case__589: case__589
-case__143: case__143
-logic__4329: logic__4329
-logic__6932: logic__6932
-case__470: case__470
-logic__1035: logic__1035
-dsp48e1__1: dsp48e1__1
-datapath__682: datapath__682
-logic__9631: logic__3617
-ram__9: ram__1
-logic__9734: logic__2507
-logic__950: logic__950
-case__1647: case__1647
-reg__416: reg__416
-logic__8694: logic__8694
-case__1557: case__1557
-logic__8180: logic__8180
-case__794: case__794
-logic__5447: logic__5447
-logic__3884: logic__3884
-logic__5135: logic__5135
-logic__7414: logic__7414
-logic__6777: logic__6777
-logic__9965: logic__916
-logic__772: logic__772
-logic__4388: logic__4388
-logic__9860: logic__2166
-logic__5702: logic__5702
-datapath__463: datapath__463
-reg__311: reg__311
-logic__4408: logic__4408
-logic__3948: logic__3948
-case__1433: case__1433
-logic__9413: logic__9413
-logic__4924: logic__4924
-logic__8803: logic__8803
-datapath__32: datapath__32
-FPUFMAPipe_l4_f64: FPUFMAPipe_l4_f64
-logic__6832: logic__6832
-reg__228: reg__228
-logic__5203: logic__5203
-reg__799: reg__799
-logic__5701: logic__5701
-logic__9839: logic__2209
-logic__1966: logic__1966
-logic__2870: logic__2870
-logic__952: logic__952
-reg__300: reg__300
-reg__408: reg__408
-datapath__405: datapath__405
-logic__8123: logic__8123
-case__700: case__700
-logic__8429: logic__8429
-case__443: case__443
-keep__33: keep__14
-logic__6836: logic__6836
-Arbiter4_DCacheDataReq: Arbiter4_DCacheDataReq
-case__1635: case__1635
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__19: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__3718: logic__3718
-datapath__265: datapath__265
-logic__9836: logic__2218
-case__628: case__628
-logic__8547: logic__8547
-reg__1301: reg__1301
-logic__3456: logic__3456
-reg__263: reg__263
-reg__241: reg__241
-reg__1423: reg__1423
-reg__551: reg__551
-logic__2964: logic__2964
-case__1034: case__1034
-logic__7057: logic__7057
-logic__8895: logic__8895
-keep__18: keep__18
-Queue2_TLBundleD_a32d64s1k1z4u: Queue2_TLBundleD_a32d64s1k1z4u
-reg__878: reg__878
-reg__195: reg__195
-logic__8790: logic__8790
-logic__9687: logic__2519
-reg__69: reg__69
-logic__1041: logic__1041
-case__1347: case__1347
-reg__1285: reg__1285
-logic__3095: logic__3095
-reg__1403: reg__1403
-logic__7741: logic__7741
-logic__4676: logic__4676
-datapath__727: datapath__272
-reg__1053: reg__1053
-reg__1029: reg__1029
-logic__7035: logic__7035
-reg__1376: reg__1376
-muxpart__239: muxpart__239
-case__1684: case__1684
-case__1182: case__1182
-logic__2292: logic__2292
-TLInterconnectCoupler_pbus_to_fpga_uart: TLInterconnectCoupler_pbus_to_fpga_uart
-logic__2507: logic__2507
-datapath__646: datapath__646
-datapath__127: datapath__127
-reg__727: reg__727
-logic__2647: logic__2647
-logic__4847: logic__4847
-reg__1582: reg__925
-reg__1269: reg__1269
-logic__4868: logic__4868
-counter: counter
-reg__790: reg__790
-logic__9767: logic__2413
-case__1579: case__1579
-reg__1177: reg__1177
-case__1017: case__1017
-datapath__223: datapath__223
-logic__1520: logic__1520
-logic__6544: logic__6544
-reg__1260: reg__1260
-case__1659: case__1659
-case__340: case__340
-datapath__430: datapath__430
-datapath__626: datapath__626
-logic__9939: logic__1161
-logic__7438: logic__7438
-case__594: case__594
-logic__5609: logic__5609
-reg__1552: reg__925
-logic__4910: logic__4910
-logic__315: logic__315
-reg__975: reg__975
-case__1307: case__1307
-logic__7934: logic__7934
-AsyncValidSync__19: AsyncValidSync
-logic__4857: logic__4857
-case__723: case__723
-AsyncResetSynchronizerShiftReg_w1_d3_i0: AsyncResetSynchronizerShiftReg_w1_d3_i0
-datapath__139: datapath__139
-logic__8034: logic__8034
-logic__7712: logic__7712
-logic__7246: logic__7246
-case__669: case__669
-logic__5423: logic__5423
-logic__5980: logic__5980
-logic__8781: logic__8781
-dsp48e1__4: dsp48e1__4
-reg__548: reg__548
-logic__9328: logic__9328
-logic__4432: logic__4432
-logic__9317: logic__9317
-logic__536: logic__536
-keep__6: keep__6
-logic__7386: logic__7386
-logic__9762: logic__2430
-reg__394: reg__394
-datapath__54: datapath__54
-reg__1369: reg__1369
-muxpart__196: muxpart__196
-logic__7582: logic__7582
-reg__578: reg__578
-FPUDecoder: FPUDecoder
-datapath__347: datapath__347
-logic__5329: logic__5329
-logic__5831: logic__5831
-reg__504: reg__504
-logic__1467: logic__1467
-case__585: case__585
-reg__1339: reg__1339
-logic__5497: logic__5497
-logic__4858: logic__4858
-logic__7838: logic__7838
-logic__2844: logic__2844
-logic__2289: logic__2289
-logic__1663: logic__1663
-case__1628: case__1628
-logic__1297: logic__1297
-logic__3877: logic__3877
-logic__9941: logic__1155
-reg__323: reg__323
-datapath__532: datapath__532
-reg__270: reg__270
-logic__5394: logic__5394
-case__757: case__757
-logic__19: logic__19
-Queue2_TLBundleD_a29d64s2k1z3u__2: Queue2_TLBundleD_a29d64s2k1z3u
-muxpart__240: muxpart__240
-case__898: case__898
-logic__2750: logic__2750
-case__50: case__50
-logic__800: logic__800
-reg__1462: reg__1229
-logic__3559: logic__3559
-logic__7377: logic__7377
-case__442: case__442
-logic__356: logic__356
-logic__5957: logic__5957
-muxpart__78: muxpart__78
-logic__4887: logic__4887
-reg__1448: reg__1340
-logic__1799: logic__1799
-reg__668: reg__668
-reg__647: reg__647
-case__198: case__198
-logic__5067: logic__5067
-datapath__416: datapath__416
-logic__9760: logic__2434
-logic__2452: logic__2452
-logic__2188: logic__2188
-logic__6294: logic__6294
-AsyncValidSync__8: AsyncValidSync
-reg__879: reg__879
-logic__765: logic__765
-reg__1208: reg__1208
-datapath__6: datapath__6
-reg__1513: reg__925
-logic__6837: logic__6837
-reg__1059: reg__1059
-case__1116: case__1116
-datapath__674: datapath__674
-logic__7118: logic__7118
-datapath__198: datapath__198
-logic__4093: logic__4093
-logic__9303: logic__9303
-logic__8829: logic__8829
-reg__1374: reg__1374
-logic__2773: logic__2773
-reg__1265: reg__1265
-logic__744: logic__744
-case__140: case__140
-reg__1212: reg__1212
-Queue2_TLBundleA_a32d64s2k1z4u: Queue2_TLBundleA_a32d64s2k1z4u
-case__1745: case__1745
-reg__1478: reg__925
-logic__9701: logic__2483
-logic__3517: logic__3517
-case__981: case__981
-reg__798: reg__798
-case__1146: case__1146
-logic__9603: logic__9603
-muxpart__269: muxpart__269
-case__429: case__429
-case__673: case__673
-logic__6337: logic__6337
-RoundRawFNToRecFN__1: RoundRawFNToRecFN
-logic__7252: logic__7252
-logic__2350: logic__2350
-case__272: case__272
-case__644: case__644
-reg__925: reg__925
-LevelGateway__1: LevelGateway
-logic__1699: logic__1699
-logic__3460: logic__3460
-logic__2907: logic__2907
-logic__6656: logic__6656
-datapath__180: datapath__180
-logic__3808: logic__3808
-case__359: case__359
-case__1566: case__1566
-datapath__752: datapath__674
-logic__7279: logic__7279
-reg__819: reg__819
-logic__286: logic__286
-reg__196: reg__196
-logic__5234: logic__5234
-case__758: case__758
-logic__9003: logic__9003
-logic__8179: logic__8179
-logic__3921: logic__3921
-logic__782: logic__782
-case__1538: case__1538
-logic__3444: logic__3444
-datapath__522: datapath__522
-reg__1061: reg__1061
-case__1092: case__1092
-reg__751: reg__751
-logic__8226: logic__8226
-logic__7014: logic__7014
-datapath__173: datapath__173
-datapath__143: datapath__143
-ResetCatchAndSync_d3: ResetCatchAndSync_d3
-logic__2888: logic__2888
-IntSyncAsyncCrossingSink_n1x1: IntSyncAsyncCrossingSink_n1x1
-logic__940: logic__940
-reg__1200: reg__1200
-logic__9710: logic__2566
-logic__7194: logic__7194
-case__1589: case__1589
-logic__2843: logic__2843
-reg__908: reg__908
-logic__1268: logic__1268
-case__1244: case__1244
-case__1094: case__1094
-datapath__605: datapath__605
-case__939: case__939
-logic__3483: logic__3483
-datapath__680: datapath__680
-muxpart__195: muxpart__195
-logic__9371: logic__9371
-logic__9084: logic__9084
-logic__4874: logic__4874
-logic__151: logic__151
-reg__491: reg__491
-logic__1187: logic__1187
-extram__9: extram__9
-logic__6134: logic__6134
-case__576: case__576
-logic__1530: logic__1530
-logic__4383: logic__4383
-muxpart__39: muxpart__39
-case__646: case__646
-logic__515: logic__515
-logic__7420: logic__7420
-logic__6935: logic__6935
-logic__4399: logic__4399
-logic__4153: logic__4153
-case__837: case__837
-reg__332: reg__332
-case__1690: case__1690
-case__1678: case__1678
-muxpart__19: muxpart__19
-datapath__461: datapath__461
-logic__9088: logic__9088
-logic__4707: logic__4707
-logic__7385: logic__7385
-logic__975: logic__975
-logic__5344: logic__5344
-logic__2745: logic__2745
-logic__9049: logic__9049
-case__185: case__185
-case__1199: case__1199
-datapath__618: datapath__618
-muxpart__81: muxpart__81
-logic__951: logic__951
-case__106: case__106
-logic__9619: logic__3642
-logic__1745: logic__1745
-logic__3269: logic__3269
-FPU__GB1: FPU__GB1
-logic__9754: logic__2455
-logic__5427: logic__5427
-AsyncValidSync__21: AsyncValidSync
-logic__3324: logic__3324
-logic__2708: logic__2708
-case__1186: case__1186
-logic__7819: logic__7819
-Queue2_TLBundleD_a32d64s2k1z4u__1: Queue2_TLBundleD_a32d64s2k1z4u
-case__923: case__923
-logic__287: logic__287
-reg__1540: reg__925
-keep__47: keep__10
-case__1197: case__1197
-reg__639: reg__639
-logic__9838: logic__2214
-reg__792: reg__792
-datapath__58: datapath__58
-case__1510: case__1510
-logic__2800: logic__2800
-logic__9602: logic__9602
-logic__9414: logic__9414
-dsp48e1__45: dsp48e1__45
-reg__1273: reg__1273
-extram__3: extram__3
-case__1424: case__1424
-logic__9626: logic__3625
-logic__3304: logic__3304
-reg__305: reg__305
-logic__2307: logic__2307
-logic__9050: logic__9050
-logic__4376: logic__4376
-muxpart__9: muxpart__9
-datapath__282: datapath__282
-logic__3467: logic__3467
-ClockGroupAggregator_sbus: ClockGroupAggregator_sbus
-case__877: case__877
-logic__4593: logic__4593
-reg__59: reg__59
-logic__9459: logic__9459
-case__743: case__743
-cordic_angle_lut: cordic_angle_lut
-case__1070: case__1070
-datapath__669: datapath__669
-datapath__138: datapath__138
-reg__1297: reg__1297
-logic__5245: logic__5245
-logic__2455: logic__2455
-datapath__338: datapath__338
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2ECDAC80.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2ECDAC80.rtd
deleted file mode 100644
index 1bd878f..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2ECDAC80.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2ECDB620.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2ECDB620.rtd
deleted file mode 100644
index 6930eb1..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2ECDB620.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2F5B08C0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2F5B08C0.rtd
deleted file mode 100644
index 3af5b1e..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2F5B08C0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2F8EB1C0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2F8EB1C0.rtd
deleted file mode 100644
index 67788c5..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/2F8EB1C0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/3159FDC0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/3159FDC0.rtd
deleted file mode 100644
index 9a79151..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/3159FDC0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/462CC640.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/462CC640.rtd
deleted file mode 100644
index 65aba22..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/462CC640.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/46327200.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/46327200.rtd
deleted file mode 100644
index a4b9cd5..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/46327200.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/46408120.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/46408120.rtd
deleted file mode 100644
index 99d0036..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/46408120.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/56B868A0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/56B868A0.rtd
deleted file mode 100644
index 6178fef..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/56B868A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/57156320.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/57156320.rtd
deleted file mode 100644
index 3fd3663..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/57156320.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/611E74A0.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/611E74A0.rtd
deleted file mode 100644
index 8da4156..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/611E74A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/design.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/design.rtd
deleted file mode 100644
index be11783..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/files.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/files.rtd
deleted file mode 100644
index 19449f9..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/files.rtd
+++ /dev/null
@@ -1,13 +0,0 @@
-design.rtd
-straps.rtd
-2ECDAC80.rtd
-2ECDB620.rtd
-2F5B08C0.rtd
-3159FDC0.rtd
-611E74A0.rtd
-57156320.rtd
-56B868A0.rtd
-46327200.rtd
-462CC640.rtd
-46408120.rtd
-2F8EB1C0.rtd
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/straps.rtd b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/straps.rtd
deleted file mode 100644
index 3b2360b..0000000
Binary files a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/topModuleToGenome.map b/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/topModuleToGenome.map
deleted file mode 100644
index dc79c5e..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/1309558296/u/topModuleToGenome.map
+++ /dev/null
@@ -1,10 +0,0 @@
-TilePRCIDomain: TilePRCIDomain__GC0, HierarchicalElementResetDomain,
-APBGpsBlock: APBGpsBlock__GC0, tracking_wrapper,
-TLToAPB: TLToAPB,
-HierarchicalElementResetDomain: RocketTile,
-tracking_wrapper: tracking_wrapper,
-FPU: FPU__GB2, FPU__GB1, FPU__GB0,
-DCache: DCache,
-RocketTile: RocketTile__GCB0, FPU, DCache,
-FPGAGPSClockSinkDomain: TLToAPB, APBGpsBlock,
-VCU118RocketSystem: VCU118RocketSystem__GC0, FPGAGPSClockSinkDomain, TilePRCIDomain,
diff --git a/.Xil/Vivado-198675-onur/incrSyn/soln.nlo b/.Xil/Vivado-198675-onur/incrSyn/soln.nlo
deleted file mode 100644
index 13af484..0000000
--- a/.Xil/Vivado-198675-onur/incrSyn/soln.nlo
+++ /dev/null
@@ -1 +0,0 @@
-1 -2
diff --git a/.Xil/Vivado-198675-onur/wt/synthesis.wdf b/.Xil/Vivado-198675-onur/wt/synthesis.wdf
deleted file mode 100644
index ad709fa..0000000
--- a/.Xil/Vivado-198675-onur/wt/synthesis.wdf
+++ /dev/null
@@ -1,52 +0,0 @@
-version:1
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b333235746666673930302d32:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:67656e65737973325f726f636b65745f746f70:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d53594e544845534953:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7668646c5f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66696c65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f77:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f775f73657474696e6773:64656661756c743a3a6e6f6e65:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c75745f63617363616465:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d676c6f62616c5f726574696d696e67:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30333a323973:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:333339332e3232374d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313737322e3039384d42:00:00
-eof:261825688
diff --git a/.Xil/Vivado-198675-onur/wt/synthesis_details.wdf b/.Xil/Vivado-198675-onur/wt/synthesis_details.wdf
deleted file mode 100644
index 78f8d66..0000000
--- a/.Xil/Vivado-198675-onur/wt/synthesis_details.wdf
+++ /dev/null
@@ -1,3 +0,0 @@
-version:1
-73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
-eof:2511430288
diff --git a/.Xil/Vivado-303406-onur/.lpr b/.Xil/Vivado-303406-onur/.lpr
deleted file mode 100644
index 04ef66e..0000000
--- a/.Xil/Vivado-303406-onur/.lpr
+++ /dev/null
@@ -1,7 +0,0 @@
-
-
-
-
-
-
-
diff --git a/.Xil/Vivado-303406-onur/elab.rtd b/.Xil/Vivado-303406-onur/elab.rtd
deleted file mode 100644
index afb9773..0000000
Binary files a/.Xil/Vivado-303406-onur/elab.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/equivDumpFile.info b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/equivDumpFile.info
deleted file mode 100644
index 5f2df82..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/equivDumpFile.info
+++ /dev/null
@@ -1,5 +0,0 @@
-/u_rocket/VCU118RocketSystem__GC0#79:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#0
-/u_rocket/VCU118RocketSystem__GC0#80:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#1
-/u_rocket/VCU118RocketSystem__GC0#293:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#405
-/u_rocket/VCU118RocketSystem__GC0#291:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#403
-/u_rocket/VCU118RocketSystem__GC0#292:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#404
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1220760385.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1220760385.rtd
deleted file mode 100644
index d582400..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index 64b8acd..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1294509424.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1294509424.rtd
deleted file mode 100644
index 0c885d8..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index 59e394a..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/136113302.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/136113302.rtd
deleted file mode 100644
index 69c8194..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd
deleted file mode 100644
index e026d75..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1672436263.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1672436263.rtd
deleted file mode 100644
index bba2996..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index f4a941e..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2610937407.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2610937407.rtd
deleted file mode 100644
index f848f34..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index da2f215..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2737226844.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2737226844.rtd
deleted file mode 100644
index 191784b..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index ceaea62..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2962621930.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2962621930.rtd
deleted file mode 100644
index 41232ab..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index 36bbb68..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2996647647.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2996647647.rtd
deleted file mode 100644
index 9e5c684..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2996647647.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2996647647.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2996647647.rtd.straps.rtd
deleted file mode 100644
index e09d8b5..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2996647647.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2996647647.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2996647647.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2996647647.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2996647647.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/2996647647.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3315205705.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3315205705.rtd
deleted file mode 100644
index d56bfd9..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3315205705.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3315205705.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3315205705.rtd.straps.rtd
deleted file mode 100644
index 1bd2bc0..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3315205705.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3315205705.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3315205705.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3315205705.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3315205705.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3315205705.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3482045580.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3482045580.rtd
deleted file mode 100644
index d6049f2..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index 655b3c0..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3990655999.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3990655999.rtd
deleted file mode 100644
index f831c5d..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3990655999.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd
deleted file mode 100644
index 942c773..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/976197094.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/976197094.rtd
deleted file mode 100644
index 3714ef8..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd
deleted file mode 100644
index 964ef29..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/global_name.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/global_name.straps.rtd
deleted file mode 100644
index d51433e..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/instToEncGenName.map b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/instToEncGenName.map
deleted file mode 100644
index e4130a3..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/g/instToEncGenName.map
+++ /dev/null
@@ -1,20 +0,0 @@
-/genesys2_rocket_top__GC0:3990655999
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GCB1:3315205705
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GCB0:2996647647
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/genomeDependencyGraph.out b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/genomeDependencyGraph.out
deleted file mode 100644
index 824c640..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/genomeDependencyGraph.out
+++ /dev/null
@@ -1,53 +0,0 @@
-GENOME NON_GENOME PIN 406: GENOME NON_GENOME PIN 0
-GENOME NON_GENOME PIN 0: GENOME NON_GENOME PIN 406
-GENOME NON_GENOME PIN 407: GENOME NON_GENOME PIN 1
-GENOME NON_GENOME PIN 1: GENOME NON_GENOME PIN 407
-GENOME NON_GENOME PIN 805: GENOME NON_GENOME PIN 403
-GENOME NON_GENOME PIN 403: GENOME NON_GENOME PIN 805
-GENOME NON_GENOME PIN 806: GENOME NON_GENOME PIN 404
-GENOME NON_GENOME PIN 404: GENOME NON_GENOME PIN 806
-GENOME NON_GENOME PIN 807: GENOME NON_GENOME PIN 405
-GENOME NON_GENOME PIN 405: GENOME NON_GENOME PIN 807
-GENOME NON_GENOME PIN 102: GENOME NON_GENOME PIN 45
-GENOME NON_GENOME PIN 45: GENOME NON_GENOME PIN 102
-INST genesys2_rocket_top__GC0 PIN 44: INST NON_GENOME PIN 113 TYPE 1 GENOME genesys2_rocket_top__GC0 PIN 44
-INST TLToAPB PIN 119: INST VCU118RocketSystem__GC0 PIN 83 TYPE 5
-INST TLToAPB PIN 120: INST VCU118RocketSystem__GC0 PIN 84 TYPE 5
-INST TLToAPB PIN 121: INST VCU118RocketSystem__GC0 PIN 85 TYPE 5
-INST TLToAPB PIN 122: INST VCU118RocketSystem__GC0 PIN 86 TYPE 5
-INST TLToAPB PIN 123: INST VCU118RocketSystem__GC0 PIN 87 TYPE 5
-INST TLToAPB PIN 162: INST VCU118RocketSystem__GC0 PIN 126 TYPE 5
-INST TLToAPB PIN 163: INST VCU118RocketSystem__GC0 PIN 127 TYPE 5
-INST TLToAPB PIN 164: INST VCU118RocketSystem__GC0 PIN 128 TYPE 5
-INST TLToAPB PIN 165: INST VCU118RocketSystem__GC0 PIN 129 TYPE 5
-INST TLToAPB PIN 166: INST VCU118RocketSystem__GC0 PIN 130 TYPE 5
-INST TLToAPB PIN 167: INST VCU118RocketSystem__GC0 PIN 131 TYPE 5
-INST TLToAPB PIN 168: INST VCU118RocketSystem__GC0 PIN 132 TYPE 5
-INST TLToAPB PIN 169: INST VCU118RocketSystem__GC0 PIN 133 TYPE 5
-INST TLToAPB PIN 170: INST VCU118RocketSystem__GC0 PIN 134 TYPE 5
-INST TLToAPB PIN 171: INST VCU118RocketSystem__GC0 PIN 135 TYPE 5
-INST TLToAPB PIN 172: INST VCU118RocketSystem__GC0 PIN 136 TYPE 5
-INST TLToAPB PIN 205: INST VCU118RocketSystem__GC0 PIN 169 TYPE 5
-INST TilePRCIDomain__GC0 PIN 728: INST VCU118RocketSystem__GC0 PIN 289 TYPE 5
-INST TilePRCIDomain__GC0 PIN 808: INST RocketTile__GCB0 PIN 74 TYPE 5
-INST VCU118RocketSystem__GC0 PIN 79: INST TilePRCIDomain__GC0 PIN 0 TYPE 3 INST FPU__GB0 PIN 301 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST DCache PIN 338 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 80: INST TilePRCIDomain__GC0 PIN 1 TYPE 3 INST FPU__GB1 PIN 323 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST DCache PIN 339 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 293: INST TilePRCIDomain__GC0 PIN 405 TYPE 3 INST RocketTile__GCB0 PIN 1114 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 291: INST TilePRCIDomain__GC0 PIN 403 TYPE 3 INST RocketTile__GCB0 PIN 1115 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 292: INST TilePRCIDomain__GC0 PIN 404 TYPE 3 INST RocketTile__GCB0 PIN 1116 TYPE 4
-INST TLToAPB PIN 2: INST VCU118RocketSystem__GC0 PIN 500 TYPE 0 GENOME TLToAPB PIN 2
-INST TLToAPB PIN 3: INST VCU118RocketSystem__GC0 PIN 501 TYPE 0 GENOME TLToAPB PIN 3
-INST TLToAPB PIN 5: INST VCU118RocketSystem__GC0 PIN 503 TYPE 0 GENOME TLToAPB PIN 5
-INST TLToAPB PIN 6: INST VCU118RocketSystem__GC0 PIN 504 TYPE 0 GENOME TLToAPB PIN 6
-INST TLToAPB PIN 16: INST VCU118RocketSystem__GC0 PIN 514 TYPE 0 GENOME TLToAPB PIN 16
-INST TilePRCIDomain__GC0 PIN 218: INST VCU118RocketSystem__GC0 PIN 561 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 218
-INST TilePRCIDomain__GC0 PIN 219: INST VCU118RocketSystem__GC0 PIN 562 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 219
-INST TilePRCIDomain__GC0 PIN 284: INST VCU118RocketSystem__GC0 PIN 627 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 284
-INST TilePRCIDomain__GC0 PIN 0: GENOME TilePRCIDomain__GC0 PIN 0
-INST TilePRCIDomain__GC0 PIN 1: GENOME TilePRCIDomain__GC0 PIN 1
-INST TilePRCIDomain__GC0 PIN 403: GENOME TilePRCIDomain__GC0 PIN 403
-INST TilePRCIDomain__GC0 PIN 404: GENOME TilePRCIDomain__GC0 PIN 404
-INST TilePRCIDomain__GC0 PIN 405: GENOME TilePRCIDomain__GC0 PIN 405
-INST TilePRCIDomain__GC0 PIN 805: INST VCU118RocketSystem__GC0 PIN 291 TYPE 5
-INST TilePRCIDomain__GC0 PIN 806: INST VCU118RocketSystem__GC0 PIN 292 TYPE 5
-INST TilePRCIDomain__GC0 PIN 807: INST VCU118RocketSystem__GC0 PIN 293 TYPE 5
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/genomes.map b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/genomes.map
deleted file mode 100644
index b6ec85d..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/genomes.map
+++ /dev/null
@@ -1,12 +0,0 @@
-FPU__GB0 82AC8E00
-FPU__GB1 85310880
-FPU__GB2 83F79C80
-RocketTile__GCB0 58CD6940
-DCache 58C70140
-TilePRCIDomain__GC0 58B23700
-tracking_wrapper 58C35EE0
-APBGpsBlock__GCB0 86F57440
-APBGpsBlock__GCB1 85272BE0
-TLToAPB 97F14C40
-VCU118RocketSystem__GC0 581830E0
-genesys2_rocket_top__GC0 5720EAA0
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/53F669E0.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/53F669E0.rtd
deleted file mode 100644
index 8c59654..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/53F669E0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/57A39820.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/57A39820.rtd
deleted file mode 100644
index f511f9a..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/57A39820.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/58AE7C20.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/58AE7C20.rtd
deleted file mode 100644
index 7d8a14b..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/58AE7C20.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/5988A760.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/5988A760.rtd
deleted file mode 100644
index 504ebf7..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/5988A760.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/5AE1E420.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/5AE1E420.rtd
deleted file mode 100644
index d7471b6..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/5AE1E420.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/5B8FEC00.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/5B8FEC00.rtd
deleted file mode 100644
index 9a4d773..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/5B8FEC00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7A5CCD00.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7A5CCD00.rtd
deleted file mode 100644
index b0713af..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7A5CCD00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7C364560.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7C364560.rtd
deleted file mode 100644
index d1c0f71..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7C364560.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7F2F87A0.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7F2F87A0.rtd
deleted file mode 100644
index 4705a7d..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7F2F87A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7F2F9A00.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7F2F9A00.rtd
deleted file mode 100644
index 214b3b7..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/7F2F9A00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/8B672100.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/8B672100.rtd
deleted file mode 100644
index 338c7b8..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/8B672100.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/9710DC80.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/9710DC80.rtd
deleted file mode 100644
index e139451..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/9710DC80.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/design.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/design.rtd
deleted file mode 100644
index b0bd05c..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/files.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/files.rtd
deleted file mode 100644
index 20fb801..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/files.rtd
+++ /dev/null
@@ -1,14 +0,0 @@
-design.rtd
-straps.rtd
-5AE1E420.rtd
-57A39820.rtd
-5988A760.rtd
-8B672100.rtd
-7A5CCD00.rtd
-7F2F87A0.rtd
-53F669E0.rtd
-7F2F9A00.rtd
-5B8FEC00.rtd
-58AE7C20.rtd
-7C364560.rtd
-9710DC80.rtd
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/straps.rtd
deleted file mode 100644
index 6f85a85..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/uniqInferGenToOrigInferGen.map b/.Xil/Vivado-303406-onur/incrSyn/1309558296/a/uniqInferGenToOrigInferGen.map
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/genomeDependencyGraph.out b/.Xil/Vivado-303406-onur/incrSyn/1309558296/genomeDependencyGraph.out
deleted file mode 100644
index c3483c6..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/genomeDependencyGraph.out
+++ /dev/null
@@ -1,908 +0,0 @@
-GENOME NON_GENOME PIN 406: GENOME NON_GENOME PIN 0
-GENOME NON_GENOME PIN 0: GENOME NON_GENOME PIN 406
-GENOME NON_GENOME PIN 407: GENOME NON_GENOME PIN 1
-GENOME NON_GENOME PIN 1: GENOME NON_GENOME PIN 407
-GENOME NON_GENOME PIN 805: GENOME NON_GENOME PIN 403 GENOME NON_GENOME PIN 867
-GENOME NON_GENOME PIN 403: GENOME NON_GENOME PIN 805 GENOME NON_GENOME PIN 465
-GENOME NON_GENOME PIN 806: GENOME NON_GENOME PIN 404 GENOME NON_GENOME PIN 744
-GENOME NON_GENOME PIN 404: GENOME NON_GENOME PIN 806
-GENOME NON_GENOME PIN 807: GENOME NON_GENOME PIN 405
-GENOME NON_GENOME PIN 405: GENOME NON_GENOME PIN 807
-GENOME NON_GENOME PIN 102: GENOME NON_GENOME PIN 45
-GENOME NON_GENOME PIN 45: GENOME NON_GENOME PIN 102 GENOME NON_GENOME PIN 1288
-INST genesys2_rocket_top__GC0 PIN 44: INST NON_GENOME PIN 113 TYPE 1 GENOME genesys2_rocket_top__GC0 PIN 44
-INST TLToAPB PIN 119: INST VCU118RocketSystem__GC0 PIN 83 TYPE 5
-INST TLToAPB PIN 120: INST VCU118RocketSystem__GC0 PIN 84 TYPE 5
-INST TLToAPB PIN 121: INST VCU118RocketSystem__GC0 PIN 85 TYPE 5
-INST TLToAPB PIN 122: INST VCU118RocketSystem__GC0 PIN 86 TYPE 5
-INST TLToAPB PIN 123: INST VCU118RocketSystem__GC0 PIN 87 TYPE 5
-INST TLToAPB PIN 162: INST VCU118RocketSystem__GC0 PIN 126 TYPE 5
-INST TLToAPB PIN 163: INST VCU118RocketSystem__GC0 PIN 127 TYPE 5
-INST TLToAPB PIN 164: INST VCU118RocketSystem__GC0 PIN 128 TYPE 5
-INST TLToAPB PIN 165: INST VCU118RocketSystem__GC0 PIN 129 TYPE 5
-INST TLToAPB PIN 166: INST VCU118RocketSystem__GC0 PIN 130 TYPE 5
-INST TLToAPB PIN 167: INST VCU118RocketSystem__GC0 PIN 131 TYPE 5
-INST TLToAPB PIN 168: INST VCU118RocketSystem__GC0 PIN 132 TYPE 5
-INST TLToAPB PIN 169: INST VCU118RocketSystem__GC0 PIN 133 TYPE 5
-INST TLToAPB PIN 170: INST VCU118RocketSystem__GC0 PIN 134 TYPE 5
-INST TLToAPB PIN 171: INST VCU118RocketSystem__GC0 PIN 135 TYPE 5
-INST TLToAPB PIN 172: INST VCU118RocketSystem__GC0 PIN 136 TYPE 5
-INST TLToAPB PIN 205: INST VCU118RocketSystem__GC0 PIN 169 TYPE 5
-INST TilePRCIDomain__GC0 PIN 728: INST VCU118RocketSystem__GC0 PIN 289 TYPE 5
-INST TilePRCIDomain__GC0 PIN 808: INST RocketTile__GCB0 PIN 74 TYPE 5
-INST VCU118RocketSystem__GC0 PIN 79: INST TilePRCIDomain__GC0 PIN 0 TYPE 3 INST FPU__GB0 PIN 301 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST DCache PIN 338 TYPE 4 GENOME VCU118RocketSystem__GC0 PIN 79
-INST VCU118RocketSystem__GC0 PIN 80: INST TilePRCIDomain__GC0 PIN 1 TYPE 3 INST FPU__GB1 PIN 323 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST DCache PIN 339 TYPE 4 GENOME VCU118RocketSystem__GC0 PIN 80
-INST VCU118RocketSystem__GC0 PIN 293: INST TilePRCIDomain__GC0 PIN 405 TYPE 3 INST RocketTile__GCB0 PIN 1114 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 291: INST TilePRCIDomain__GC0 PIN 403 TYPE 3 INST RocketTile__GCB0 PIN 1115 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 292: INST TilePRCIDomain__GC0 PIN 404 TYPE 3 INST RocketTile__GCB0 PIN 1116 TYPE 4
-INST TLToAPB PIN 2: INST VCU118RocketSystem__GC0 PIN 500 TYPE 0 GENOME TLToAPB PIN 2
-INST TLToAPB PIN 3: INST VCU118RocketSystem__GC0 PIN 501 TYPE 0 GENOME TLToAPB PIN 3
-INST TLToAPB PIN 5: INST VCU118RocketSystem__GC0 PIN 503 TYPE 0 GENOME TLToAPB PIN 5
-INST TLToAPB PIN 6: INST VCU118RocketSystem__GC0 PIN 504 TYPE 0 GENOME TLToAPB PIN 6
-INST TLToAPB PIN 16: INST VCU118RocketSystem__GC0 PIN 514 TYPE 0 GENOME TLToAPB PIN 16
-INST TilePRCIDomain__GC0 PIN 218: INST VCU118RocketSystem__GC0 PIN 561 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 218
-INST TilePRCIDomain__GC0 PIN 219: INST VCU118RocketSystem__GC0 PIN 562 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 219
-INST TilePRCIDomain__GC0 PIN 284: INST VCU118RocketSystem__GC0 PIN 627 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 284
-INST TilePRCIDomain__GC0 PIN 0: GENOME TilePRCIDomain__GC0 PIN 0
-INST TilePRCIDomain__GC0 PIN 1: GENOME TilePRCIDomain__GC0 PIN 1
-INST TilePRCIDomain__GC0 PIN 403: GENOME TilePRCIDomain__GC0 PIN 403
-INST TilePRCIDomain__GC0 PIN 404: GENOME TilePRCIDomain__GC0 PIN 404
-INST TilePRCIDomain__GC0 PIN 405: GENOME TilePRCIDomain__GC0 PIN 405
-INST TilePRCIDomain__GC0 PIN 805: INST VCU118RocketSystem__GC0 PIN 291 TYPE 5
-INST TilePRCIDomain__GC0 PIN 806: INST VCU118RocketSystem__GC0 PIN 292 TYPE 5
-INST TilePRCIDomain__GC0 PIN 807: INST VCU118RocketSystem__GC0 PIN 293 TYPE 5
-INST APBGpsBlock__GCB1 PIN 384: INST TLToAPB PIN 52 TYPE 5
-INST APBGpsBlock__GCB1 PIN 386: INST TLToAPB PIN 83 TYPE 5
-INST APBGpsBlock__GCB1 PIN 387: INST TLToAPB PIN 84 TYPE 5
-INST APBGpsBlock__GCB1 PIN 388: INST TLToAPB PIN 85 TYPE 5
-INST APBGpsBlock__GCB1 PIN 389: INST TLToAPB PIN 86 TYPE 5
-INST APBGpsBlock__GCB1 PIN 390: INST TLToAPB PIN 87 TYPE 5
-INST APBGpsBlock__GCB1 PIN 391: INST TLToAPB PIN 88 TYPE 5
-INST APBGpsBlock__GCB1 PIN 392: INST TLToAPB PIN 89 TYPE 5
-INST APBGpsBlock__GCB1 PIN 393: INST TLToAPB PIN 90 TYPE 5
-INST APBGpsBlock__GCB1 PIN 394: INST TLToAPB PIN 91 TYPE 5
-INST APBGpsBlock__GCB1 PIN 395: INST TLToAPB PIN 92 TYPE 5
-INST APBGpsBlock__GCB1 PIN 396: INST TLToAPB PIN 93 TYPE 5
-INST APBGpsBlock__GCB1 PIN 397: INST TLToAPB PIN 94 TYPE 5
-INST APBGpsBlock__GCB1 PIN 398: INST TLToAPB PIN 95 TYPE 5
-INST APBGpsBlock__GCB1 PIN 399: INST TLToAPB PIN 96 TYPE 5
-INST APBGpsBlock__GCB1 PIN 400: INST TLToAPB PIN 97 TYPE 5
-INST APBGpsBlock__GCB1 PIN 401: INST TLToAPB PIN 98 TYPE 5
-INST APBGpsBlock__GCB1 PIN 402: INST TLToAPB PIN 99 TYPE 5
-INST APBGpsBlock__GCB1 PIN 403: INST TLToAPB PIN 100 TYPE 5
-INST APBGpsBlock__GCB1 PIN 404: INST TLToAPB PIN 101 TYPE 5
-INST APBGpsBlock__GCB1 PIN 405: INST TLToAPB PIN 102 TYPE 5
-INST APBGpsBlock__GCB1 PIN 406: INST TLToAPB PIN 103 TYPE 5
-INST APBGpsBlock__GCB1 PIN 407: INST TLToAPB PIN 104 TYPE 5
-INST APBGpsBlock__GCB1 PIN 408: INST TLToAPB PIN 105 TYPE 5
-INST APBGpsBlock__GCB1 PIN 409: INST TLToAPB PIN 106 TYPE 5
-INST APBGpsBlock__GCB1 PIN 410: INST TLToAPB PIN 107 TYPE 5
-INST APBGpsBlock__GCB1 PIN 411: INST TLToAPB PIN 108 TYPE 5
-INST APBGpsBlock__GCB1 PIN 412: INST TLToAPB PIN 109 TYPE 5
-INST APBGpsBlock__GCB0 PIN 277: INST TLToAPB PIN 52 TYPE 5
-INST NON_GENOME PIN 62: INST VCU118RocketSystem__GC0 PIN 171 TYPE 3 INST tracking_wrapper PIN 36 TYPE 4 INST APBGpsBlock__GCB0 PIN 247 TYPE 4 INST APBGpsBlock__GCB1 PIN 370 TYPE 4 INST TLToAPB PIN 115 TYPE 4
-INST NON_GENOME PIN 63: INST VCU118RocketSystem__GC0 PIN 172 TYPE 3 INST APBGpsBlock__GCB0 PIN 320 TYPE 4 INST APBGpsBlock__GCB1 PIN 368 TYPE 4 INST TLToAPB PIN 116 TYPE 4
-INST APBGpsBlock__GCB1 PIN 39: INST APBGpsBlock__GCB0 PIN 246 TYPE 0 GENOME APBGpsBlock__GCB1 PIN 39
-INST tracking_wrapper PIN 51: INST TLToAPB PIN 52 TYPE 5
-INST tracking_wrapper PIN 85: INST APBGpsBlock__GCB0 PIN 35 TYPE 5
-INST tracking_wrapper PIN 86: INST APBGpsBlock__GCB1 PIN 32 TYPE 5
-INST NON_GENOME PIN 66: INST VCU118RocketSystem__GC0 PIN 79 TYPE 3 INST DCache PIN 338 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB0 PIN 301 TYPE 4 INST TilePRCIDomain__GC0 PIN 406 TYPE 4
-INST NON_GENOME PIN 67: INST VCU118RocketSystem__GC0 PIN 80 TYPE 3 INST DCache PIN 339 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST FPU__GB1 PIN 323 TYPE 4 INST TilePRCIDomain__GC0 PIN 407 TYPE 4
-INST RocketTile__GCB0 PIN 1244: INST TilePRCIDomain__GC0 PIN 7 TYPE 5
-INST RocketTile__GCB0 PIN 1245: INST TilePRCIDomain__GC0 PIN 8 TYPE 5
-INST RocketTile__GCB0 PIN 1251: INST TilePRCIDomain__GC0 PIN 14 TYPE 5
-INST RocketTile__GCB0 PIN 1650: INST DCache PIN 336 TYPE 5
-INST RocketTile__GCB0 PIN 1651: INST DCache PIN 337 TYPE 5
-INST DCache PIN 342: INST RocketTile__GCB0 PIN 2 TYPE 5
-INST DCache PIN 349: INST RocketTile__GCB0 PIN 9 TYPE 5
-INST TilePRCIDomain__GC0 PIN 5: INST RocketTile__GCB0 PIN 3 TYPE 3 INST DCache PIN 343 TYPE 4
-INST TilePRCIDomain__GC0 PIN 6: INST RocketTile__GCB0 PIN 4 TYPE 3 INST DCache PIN 344 TYPE 4
-INST TilePRCIDomain__GC0 PIN 9: INST RocketTile__GCB0 PIN 5 TYPE 3 INST DCache PIN 345 TYPE 4
-INST TilePRCIDomain__GC0 PIN 10: INST RocketTile__GCB0 PIN 6 TYPE 3 INST DCache PIN 346 TYPE 4
-INST TilePRCIDomain__GC0 PIN 11: INST RocketTile__GCB0 PIN 7 TYPE 3 INST DCache PIN 347 TYPE 4
-INST TilePRCIDomain__GC0 PIN 12: INST RocketTile__GCB0 PIN 8 TYPE 3 INST DCache PIN 348 TYPE 4
-INST TilePRCIDomain__GC0 PIN 16: INST RocketTile__GCB0 PIN 10 TYPE 3 INST DCache PIN 350 TYPE 4
-INST TilePRCIDomain__GC0 PIN 17: INST RocketTile__GCB0 PIN 11 TYPE 3 INST DCache PIN 351 TYPE 4
-INST TilePRCIDomain__GC0 PIN 18: INST RocketTile__GCB0 PIN 12 TYPE 3 INST DCache PIN 352 TYPE 4
-INST TilePRCIDomain__GC0 PIN 19: INST RocketTile__GCB0 PIN 13 TYPE 3 INST DCache PIN 353 TYPE 4
-INST TilePRCIDomain__GC0 PIN 20: INST RocketTile__GCB0 PIN 14 TYPE 3 INST DCache PIN 354 TYPE 4
-INST TilePRCIDomain__GC0 PIN 21: INST RocketTile__GCB0 PIN 15 TYPE 3 INST DCache PIN 355 TYPE 4
-INST TilePRCIDomain__GC0 PIN 22: INST RocketTile__GCB0 PIN 16 TYPE 3 INST DCache PIN 356 TYPE 4
-INST TilePRCIDomain__GC0 PIN 23: INST RocketTile__GCB0 PIN 17 TYPE 3 INST DCache PIN 357 TYPE 4
-INST TilePRCIDomain__GC0 PIN 24: INST RocketTile__GCB0 PIN 18 TYPE 3 INST DCache PIN 358 TYPE 4
-INST TilePRCIDomain__GC0 PIN 25: INST RocketTile__GCB0 PIN 19 TYPE 3 INST DCache PIN 359 TYPE 4
-INST TilePRCIDomain__GC0 PIN 26: INST RocketTile__GCB0 PIN 20 TYPE 3 INST DCache PIN 360 TYPE 4
-INST TilePRCIDomain__GC0 PIN 27: INST RocketTile__GCB0 PIN 21 TYPE 3 INST DCache PIN 361 TYPE 4
-INST TilePRCIDomain__GC0 PIN 28: INST RocketTile__GCB0 PIN 22 TYPE 3 INST DCache PIN 362 TYPE 4
-INST TilePRCIDomain__GC0 PIN 29: INST RocketTile__GCB0 PIN 23 TYPE 3 INST DCache PIN 363 TYPE 4
-INST TilePRCIDomain__GC0 PIN 30: INST RocketTile__GCB0 PIN 24 TYPE 3 INST DCache PIN 364 TYPE 4
-INST TilePRCIDomain__GC0 PIN 31: INST RocketTile__GCB0 PIN 25 TYPE 3 INST DCache PIN 365 TYPE 4
-INST TilePRCIDomain__GC0 PIN 32: INST RocketTile__GCB0 PIN 26 TYPE 3 INST DCache PIN 366 TYPE 4
-INST TilePRCIDomain__GC0 PIN 33: INST RocketTile__GCB0 PIN 27 TYPE 3 INST DCache PIN 367 TYPE 4
-INST TilePRCIDomain__GC0 PIN 34: INST RocketTile__GCB0 PIN 28 TYPE 3 INST DCache PIN 368 TYPE 4
-INST TilePRCIDomain__GC0 PIN 35: INST RocketTile__GCB0 PIN 29 TYPE 3 INST DCache PIN 369 TYPE 4
-INST TilePRCIDomain__GC0 PIN 36: INST RocketTile__GCB0 PIN 30 TYPE 3 INST DCache PIN 370 TYPE 4
-INST TilePRCIDomain__GC0 PIN 37: INST RocketTile__GCB0 PIN 31 TYPE 3 INST DCache PIN 371 TYPE 4
-INST TilePRCIDomain__GC0 PIN 38: INST RocketTile__GCB0 PIN 32 TYPE 3 INST DCache PIN 372 TYPE 4
-INST TilePRCIDomain__GC0 PIN 39: INST RocketTile__GCB0 PIN 33 TYPE 3 INST DCache PIN 373 TYPE 4
-INST TilePRCIDomain__GC0 PIN 40: INST RocketTile__GCB0 PIN 34 TYPE 3 INST DCache PIN 374 TYPE 4
-INST TilePRCIDomain__GC0 PIN 41: INST RocketTile__GCB0 PIN 35 TYPE 3 INST DCache PIN 375 TYPE 4
-INST TilePRCIDomain__GC0 PIN 42: INST RocketTile__GCB0 PIN 36 TYPE 3 INST DCache PIN 376 TYPE 4
-INST TilePRCIDomain__GC0 PIN 43: INST RocketTile__GCB0 PIN 37 TYPE 3 INST DCache PIN 377 TYPE 4
-INST TilePRCIDomain__GC0 PIN 44: INST RocketTile__GCB0 PIN 38 TYPE 3 INST DCache PIN 378 TYPE 4
-INST TilePRCIDomain__GC0 PIN 45: INST RocketTile__GCB0 PIN 39 TYPE 3 INST DCache PIN 379 TYPE 4
-INST TilePRCIDomain__GC0 PIN 46: INST RocketTile__GCB0 PIN 40 TYPE 3 INST DCache PIN 380 TYPE 4
-INST TilePRCIDomain__GC0 PIN 47: INST RocketTile__GCB0 PIN 41 TYPE 3 INST DCache PIN 381 TYPE 4
-INST TilePRCIDomain__GC0 PIN 48: INST RocketTile__GCB0 PIN 42 TYPE 3 INST DCache PIN 382 TYPE 4
-INST TilePRCIDomain__GC0 PIN 49: INST RocketTile__GCB0 PIN 43 TYPE 3 INST DCache PIN 383 TYPE 4
-INST TilePRCIDomain__GC0 PIN 50: INST RocketTile__GCB0 PIN 44 TYPE 3 INST DCache PIN 384 TYPE 4
-INST TilePRCIDomain__GC0 PIN 51: INST RocketTile__GCB0 PIN 45 TYPE 3 INST DCache PIN 385 TYPE 4
-INST TilePRCIDomain__GC0 PIN 52: INST RocketTile__GCB0 PIN 46 TYPE 3 INST DCache PIN 386 TYPE 4
-INST TilePRCIDomain__GC0 PIN 53: INST RocketTile__GCB0 PIN 47 TYPE 3 INST DCache PIN 387 TYPE 4
-INST TilePRCIDomain__GC0 PIN 54: INST RocketTile__GCB0 PIN 48 TYPE 3 INST DCache PIN 388 TYPE 4
-INST TilePRCIDomain__GC0 PIN 55: INST RocketTile__GCB0 PIN 49 TYPE 3 INST DCache PIN 389 TYPE 4
-INST TilePRCIDomain__GC0 PIN 56: INST RocketTile__GCB0 PIN 50 TYPE 3 INST DCache PIN 390 TYPE 4
-INST TilePRCIDomain__GC0 PIN 57: INST RocketTile__GCB0 PIN 51 TYPE 3 INST DCache PIN 391 TYPE 4
-INST TilePRCIDomain__GC0 PIN 58: INST RocketTile__GCB0 PIN 52 TYPE 3 INST DCache PIN 392 TYPE 4
-INST TilePRCIDomain__GC0 PIN 59: INST RocketTile__GCB0 PIN 53 TYPE 3 INST DCache PIN 393 TYPE 4
-INST TilePRCIDomain__GC0 PIN 60: INST RocketTile__GCB0 PIN 54 TYPE 3 INST DCache PIN 394 TYPE 4
-INST TilePRCIDomain__GC0 PIN 61: INST RocketTile__GCB0 PIN 55 TYPE 3 INST DCache PIN 395 TYPE 4
-INST TilePRCIDomain__GC0 PIN 62: INST RocketTile__GCB0 PIN 56 TYPE 3 INST DCache PIN 396 TYPE 4
-INST TilePRCIDomain__GC0 PIN 63: INST RocketTile__GCB0 PIN 57 TYPE 3 INST DCache PIN 397 TYPE 4
-INST TilePRCIDomain__GC0 PIN 64: INST RocketTile__GCB0 PIN 58 TYPE 3 INST DCache PIN 398 TYPE 4
-INST TilePRCIDomain__GC0 PIN 65: INST RocketTile__GCB0 PIN 59 TYPE 3 INST DCache PIN 399 TYPE 4
-INST TilePRCIDomain__GC0 PIN 66: INST RocketTile__GCB0 PIN 60 TYPE 3 INST DCache PIN 400 TYPE 4
-INST TilePRCIDomain__GC0 PIN 67: INST RocketTile__GCB0 PIN 61 TYPE 3 INST DCache PIN 401 TYPE 4
-INST TilePRCIDomain__GC0 PIN 68: INST RocketTile__GCB0 PIN 62 TYPE 3 INST DCache PIN 402 TYPE 4
-INST TilePRCIDomain__GC0 PIN 69: INST RocketTile__GCB0 PIN 63 TYPE 3 INST DCache PIN 403 TYPE 4
-INST TilePRCIDomain__GC0 PIN 70: INST RocketTile__GCB0 PIN 64 TYPE 3 INST DCache PIN 404 TYPE 4
-INST TilePRCIDomain__GC0 PIN 71: INST RocketTile__GCB0 PIN 65 TYPE 3 INST DCache PIN 405 TYPE 4
-INST TilePRCIDomain__GC0 PIN 72: INST RocketTile__GCB0 PIN 66 TYPE 3 INST DCache PIN 406 TYPE 4
-INST TilePRCIDomain__GC0 PIN 73: INST RocketTile__GCB0 PIN 67 TYPE 3 INST DCache PIN 407 TYPE 4
-INST TilePRCIDomain__GC0 PIN 74: INST RocketTile__GCB0 PIN 68 TYPE 3 INST DCache PIN 408 TYPE 4
-INST TilePRCIDomain__GC0 PIN 75: INST RocketTile__GCB0 PIN 69 TYPE 3 INST DCache PIN 409 TYPE 4
-INST TilePRCIDomain__GC0 PIN 76: INST RocketTile__GCB0 PIN 70 TYPE 3 INST DCache PIN 410 TYPE 4
-INST TilePRCIDomain__GC0 PIN 77: INST RocketTile__GCB0 PIN 71 TYPE 3 INST DCache PIN 411 TYPE 4
-INST TilePRCIDomain__GC0 PIN 78: INST RocketTile__GCB0 PIN 72 TYPE 3 INST DCache PIN 412 TYPE 4
-INST TilePRCIDomain__GC0 PIN 79: INST RocketTile__GCB0 PIN 73 TYPE 3 INST DCache PIN 413 TYPE 4
-INST RocketTile__GCB0 PIN 324: INST RocketTile__GCB0 PIN 325 TYPE 2 INST DCache PIN 465 TYPE 4
-INST RocketTile__GCB0 PIN 315: INST RocketTile__GCB0 PIN 326 TYPE 2 INST DCache PIN 466 TYPE 4
-INST RocketTile__GCB0 PIN 403: INST RocketTile__GCB0 PIN 465 TYPE 2 INST DCache PIN 605 TYPE 4
-INST RocketTile__GCB0 PIN 466: INST DCache PIN 606 TYPE 1 GENOME RocketTile__GCB0 PIN 466
-INST RocketTile__GCB0 PIN 467: INST DCache PIN 607 TYPE 1 GENOME RocketTile__GCB0 PIN 467
-INST RocketTile__GCB0 PIN 470: INST RocketTile__GCB0 PIN 532 TYPE 2 INST DCache PIN 672 TYPE 4
-INST RocketTile__GCB0 PIN 533: INST DCache PIN 673 TYPE 1 GENOME RocketTile__GCB0 PIN 533
-INST RocketTile__GCB0 PIN 534: INST DCache PIN 674 TYPE 1 GENOME RocketTile__GCB0 PIN 534
-INST RocketTile__GCB0 PIN 537: INST RocketTile__GCB0 PIN 599 TYPE 2 INST DCache PIN 739 TYPE 4
-INST RocketTile__GCB0 PIN 600: INST DCache PIN 740 TYPE 1 GENOME RocketTile__GCB0 PIN 600
-INST RocketTile__GCB0 PIN 601: INST DCache PIN 741 TYPE 1 GENOME RocketTile__GCB0 PIN 601
-INST RocketTile__GCB0 PIN 604: INST RocketTile__GCB0 PIN 666 TYPE 2 INST DCache PIN 806 TYPE 4
-INST RocketTile__GCB0 PIN 667: INST DCache PIN 807 TYPE 1 GENOME RocketTile__GCB0 PIN 667
-INST RocketTile__GCB0 PIN 668: INST DCache PIN 808 TYPE 1 GENOME RocketTile__GCB0 PIN 668
-INST RocketTile__GCB0 PIN 671: INST RocketTile__GCB0 PIN 733 TYPE 2 INST DCache PIN 873 TYPE 4
-INST RocketTile__GCB0 PIN 734: INST DCache PIN 874 TYPE 1 GENOME RocketTile__GCB0 PIN 734
-INST RocketTile__GCB0 PIN 735: INST DCache PIN 875 TYPE 1 GENOME RocketTile__GCB0 PIN 735
-INST RocketTile__GCB0 PIN 738: INST RocketTile__GCB0 PIN 800 TYPE 2 INST DCache PIN 940 TYPE 4
-INST RocketTile__GCB0 PIN 801: INST DCache PIN 941 TYPE 1 GENOME RocketTile__GCB0 PIN 801
-INST RocketTile__GCB0 PIN 802: INST DCache PIN 942 TYPE 1 GENOME RocketTile__GCB0 PIN 802
-INST RocketTile__GCB0 PIN 805: INST RocketTile__GCB0 PIN 867 TYPE 2 INST DCache PIN 1007 TYPE 4
-INST RocketTile__GCB0 PIN 868: INST DCache PIN 1008 TYPE 1 GENOME RocketTile__GCB0 PIN 868
-INST RocketTile__GCB0 PIN 869: INST DCache PIN 1009 TYPE 1 GENOME RocketTile__GCB0 PIN 869
-INST RocketTile__GCB0 PIN 872: INST RocketTile__GCB0 PIN 934 TYPE 2 INST DCache PIN 1074 TYPE 4
-INST RocketTile__GCB0 PIN 935: INST DCache PIN 1075 TYPE 1 GENOME RocketTile__GCB0 PIN 935
-INST RocketTile__GCB0 PIN 936: INST DCache PIN 1076 TYPE 1 GENOME RocketTile__GCB0 PIN 936
-INST DCache PIN 7: INST RocketTile__GCB0 PIN 1125 TYPE 0 GENOME DCache PIN 7
-INST DCache PIN 8: INST RocketTile__GCB0 PIN 1126 TYPE 0 GENOME DCache PIN 8
-INST DCache PIN 43: INST RocketTile__GCB0 PIN 1161 TYPE 0 GENOME DCache PIN 43
-INST DCache PIN 44: INST RocketTile__GCB0 PIN 1162 TYPE 0 GENOME DCache PIN 44
-INST DCache PIN 45: INST RocketTile__GCB0 PIN 1163 TYPE 0 GENOME DCache PIN 45
-INST DCache PIN 46: INST RocketTile__GCB0 PIN 1164 TYPE 0 GENOME DCache PIN 46
-INST DCache PIN 330: INST RocketTile__GCB0 PIN 1644 TYPE 0 GENOME DCache PIN 330
-INST DCache PIN 331: INST RocketTile__GCB0 PIN 1645 TYPE 0 GENOME DCache PIN 331
-INST FPU__GB2 PIN 317: INST FPU__GB1 PIN 162 TYPE 5
-INST FPU__GB2 PIN 323: INST FPU__GB1 PIN 137 TYPE 5
-INST FPU__GB2 PIN 393: INST FPU__GB1 PIN 1 TYPE 5
-INST FPU__GB2 PIN 171: INST FPU__GB1 PIN 525 TYPE 0 GENOME FPU__GB2 PIN 171
-INST FPU__GB2 PIN 172: INST FPU__GB1 PIN 526 TYPE 0 GENOME FPU__GB2 PIN 172
-INST FPU__GB2 PIN 173: INST FPU__GB1 PIN 527 TYPE 0 GENOME FPU__GB2 PIN 173
-INST FPU__GB2 PIN 174: INST FPU__GB1 PIN 528 TYPE 0 GENOME FPU__GB2 PIN 174
-INST FPU__GB2 PIN 306: INST FPU__GB1 PIN 531 TYPE 0 GENOME FPU__GB2 PIN 306
-INST FPU__GB2 PIN 307: INST FPU__GB1 PIN 532 TYPE 0 GENOME FPU__GB2 PIN 307
-INST FPU__GB2 PIN 308: INST FPU__GB1 PIN 533 TYPE 0 GENOME FPU__GB2 PIN 308
-INST DCache PIN 124: INST RocketTile__GCB0 PIN 1040 TYPE 3 INST FPU__GB1 PIN 641 TYPE 4
-INST DCache PIN 125: INST RocketTile__GCB0 PIN 1041 TYPE 3 INST FPU__GB1 PIN 642 TYPE 4
-INST DCache PIN 126: INST RocketTile__GCB0 PIN 1042 TYPE 3 INST FPU__GB1 PIN 643 TYPE 4
-INST DCache PIN 127: INST RocketTile__GCB0 PIN 1043 TYPE 3 INST FPU__GB1 PIN 644 TYPE 4
-INST DCache PIN 128: INST RocketTile__GCB0 PIN 1044 TYPE 3 INST FPU__GB1 PIN 645 TYPE 4
-INST DCache PIN 199: INST RocketTile__GCB0 PIN 1045 TYPE 3 INST FPU__GB1 PIN 646 TYPE 4
-INST DCache PIN 200: INST RocketTile__GCB0 PIN 1046 TYPE 3 INST FPU__GB1 PIN 647 TYPE 4
-INST DCache PIN 201: INST RocketTile__GCB0 PIN 1047 TYPE 3 INST FPU__GB1 PIN 648 TYPE 4
-INST DCache PIN 202: INST RocketTile__GCB0 PIN 1048 TYPE 3 INST FPU__GB1 PIN 649 TYPE 4
-INST DCache PIN 203: INST RocketTile__GCB0 PIN 1049 TYPE 3 INST FPU__GB1 PIN 650 TYPE 4
-INST DCache PIN 204: INST RocketTile__GCB0 PIN 1050 TYPE 3 INST FPU__GB1 PIN 651 TYPE 4
-INST DCache PIN 205: INST RocketTile__GCB0 PIN 1051 TYPE 3 INST FPU__GB1 PIN 652 TYPE 4
-INST DCache PIN 206: INST RocketTile__GCB0 PIN 1052 TYPE 3 INST FPU__GB1 PIN 653 TYPE 4
-INST DCache PIN 207: INST RocketTile__GCB0 PIN 1053 TYPE 3 INST FPU__GB1 PIN 654 TYPE 4
-INST DCache PIN 208: INST RocketTile__GCB0 PIN 1054 TYPE 3 INST FPU__GB1 PIN 655 TYPE 4
-INST DCache PIN 209: INST RocketTile__GCB0 PIN 1055 TYPE 3 INST FPU__GB1 PIN 656 TYPE 4
-INST DCache PIN 210: INST RocketTile__GCB0 PIN 1056 TYPE 3 INST FPU__GB1 PIN 657 TYPE 4
-INST DCache PIN 211: INST RocketTile__GCB0 PIN 1057 TYPE 3 INST FPU__GB1 PIN 658 TYPE 4
-INST DCache PIN 212: INST RocketTile__GCB0 PIN 1058 TYPE 3 INST FPU__GB1 PIN 659 TYPE 4
-INST DCache PIN 213: INST RocketTile__GCB0 PIN 1059 TYPE 3 INST FPU__GB1 PIN 660 TYPE 4
-INST DCache PIN 214: INST RocketTile__GCB0 PIN 1060 TYPE 3 INST FPU__GB1 PIN 661 TYPE 4
-INST DCache PIN 215: INST RocketTile__GCB0 PIN 1061 TYPE 3 INST FPU__GB1 PIN 662 TYPE 4
-INST DCache PIN 216: INST RocketTile__GCB0 PIN 1062 TYPE 3 INST FPU__GB1 PIN 663 TYPE 4
-INST DCache PIN 217: INST RocketTile__GCB0 PIN 1063 TYPE 3 INST FPU__GB1 PIN 664 TYPE 4
-INST DCache PIN 218: INST RocketTile__GCB0 PIN 1064 TYPE 3 INST FPU__GB1 PIN 665 TYPE 4
-INST DCache PIN 219: INST RocketTile__GCB0 PIN 1065 TYPE 3 INST FPU__GB1 PIN 666 TYPE 4
-INST DCache PIN 220: INST RocketTile__GCB0 PIN 1066 TYPE 3 INST FPU__GB1 PIN 667 TYPE 4
-INST DCache PIN 221: INST RocketTile__GCB0 PIN 1067 TYPE 3 INST FPU__GB1 PIN 668 TYPE 4
-INST DCache PIN 222: INST RocketTile__GCB0 PIN 1068 TYPE 3 INST FPU__GB1 PIN 669 TYPE 4
-INST DCache PIN 223: INST RocketTile__GCB0 PIN 1069 TYPE 3 INST FPU__GB1 PIN 670 TYPE 4
-INST DCache PIN 224: INST RocketTile__GCB0 PIN 1070 TYPE 3 INST FPU__GB1 PIN 671 TYPE 4
-INST DCache PIN 225: INST RocketTile__GCB0 PIN 1071 TYPE 3 INST FPU__GB1 PIN 672 TYPE 4
-INST DCache PIN 226: INST RocketTile__GCB0 PIN 1072 TYPE 3 INST FPU__GB1 PIN 673 TYPE 4
-INST DCache PIN 227: INST RocketTile__GCB0 PIN 1073 TYPE 3 INST FPU__GB1 PIN 674 TYPE 4
-INST DCache PIN 228: INST RocketTile__GCB0 PIN 1074 TYPE 3 INST FPU__GB1 PIN 675 TYPE 4
-INST DCache PIN 229: INST RocketTile__GCB0 PIN 1075 TYPE 3 INST FPU__GB1 PIN 676 TYPE 4
-INST DCache PIN 230: INST RocketTile__GCB0 PIN 1076 TYPE 3 INST FPU__GB1 PIN 677 TYPE 4
-INST DCache PIN 231: INST RocketTile__GCB0 PIN 1077 TYPE 3 INST FPU__GB1 PIN 678 TYPE 4
-INST DCache PIN 232: INST RocketTile__GCB0 PIN 1078 TYPE 3 INST FPU__GB1 PIN 679 TYPE 4
-INST DCache PIN 233: INST RocketTile__GCB0 PIN 1079 TYPE 3 INST FPU__GB1 PIN 680 TYPE 4
-INST DCache PIN 234: INST RocketTile__GCB0 PIN 1080 TYPE 3 INST FPU__GB1 PIN 681 TYPE 4
-INST DCache PIN 235: INST RocketTile__GCB0 PIN 1081 TYPE 3 INST FPU__GB1 PIN 682 TYPE 4
-INST DCache PIN 236: INST RocketTile__GCB0 PIN 1082 TYPE 3 INST FPU__GB1 PIN 683 TYPE 4
-INST DCache PIN 237: INST RocketTile__GCB0 PIN 1083 TYPE 3 INST FPU__GB1 PIN 684 TYPE 4
-INST DCache PIN 238: INST RocketTile__GCB0 PIN 1084 TYPE 3 INST FPU__GB1 PIN 685 TYPE 4
-INST DCache PIN 239: INST RocketTile__GCB0 PIN 1085 TYPE 3 INST FPU__GB1 PIN 686 TYPE 4
-INST DCache PIN 240: INST RocketTile__GCB0 PIN 1086 TYPE 3 INST FPU__GB1 PIN 687 TYPE 4
-INST DCache PIN 241: INST RocketTile__GCB0 PIN 1087 TYPE 3 INST FPU__GB1 PIN 688 TYPE 4
-INST DCache PIN 242: INST RocketTile__GCB0 PIN 1088 TYPE 3 INST FPU__GB1 PIN 689 TYPE 4
-INST DCache PIN 243: INST RocketTile__GCB0 PIN 1089 TYPE 3 INST FPU__GB1 PIN 690 TYPE 4
-INST DCache PIN 244: INST RocketTile__GCB0 PIN 1090 TYPE 3 INST FPU__GB1 PIN 691 TYPE 4
-INST DCache PIN 245: INST RocketTile__GCB0 PIN 1091 TYPE 3 INST FPU__GB1 PIN 692 TYPE 4
-INST DCache PIN 246: INST RocketTile__GCB0 PIN 1092 TYPE 3 INST FPU__GB1 PIN 693 TYPE 4
-INST DCache PIN 247: INST RocketTile__GCB0 PIN 1093 TYPE 3 INST FPU__GB1 PIN 694 TYPE 4
-INST DCache PIN 248: INST RocketTile__GCB0 PIN 1094 TYPE 3 INST FPU__GB1 PIN 695 TYPE 4
-INST DCache PIN 249: INST RocketTile__GCB0 PIN 1095 TYPE 3 INST FPU__GB1 PIN 696 TYPE 4
-INST DCache PIN 250: INST RocketTile__GCB0 PIN 1096 TYPE 3 INST FPU__GB1 PIN 697 TYPE 4
-INST DCache PIN 251: INST RocketTile__GCB0 PIN 1097 TYPE 3 INST FPU__GB1 PIN 698 TYPE 4
-INST DCache PIN 252: INST RocketTile__GCB0 PIN 1098 TYPE 3 INST FPU__GB1 PIN 699 TYPE 4
-INST DCache PIN 253: INST RocketTile__GCB0 PIN 1099 TYPE 3 INST FPU__GB1 PIN 700 TYPE 4
-INST DCache PIN 254: INST RocketTile__GCB0 PIN 1100 TYPE 3 INST FPU__GB1 PIN 701 TYPE 4
-INST DCache PIN 255: INST RocketTile__GCB0 PIN 1101 TYPE 3 INST FPU__GB1 PIN 702 TYPE 4
-INST DCache PIN 256: INST RocketTile__GCB0 PIN 1102 TYPE 3 INST FPU__GB1 PIN 703 TYPE 4
-INST DCache PIN 257: INST RocketTile__GCB0 PIN 1103 TYPE 3 INST FPU__GB1 PIN 704 TYPE 4
-INST DCache PIN 258: INST RocketTile__GCB0 PIN 1104 TYPE 3 INST FPU__GB1 PIN 705 TYPE 4
-INST DCache PIN 259: INST RocketTile__GCB0 PIN 1105 TYPE 3 INST FPU__GB1 PIN 706 TYPE 4
-INST DCache PIN 260: INST RocketTile__GCB0 PIN 1106 TYPE 3 INST FPU__GB1 PIN 707 TYPE 4
-INST DCache PIN 261: INST RocketTile__GCB0 PIN 1107 TYPE 3 INST FPU__GB1 PIN 708 TYPE 4
-INST DCache PIN 262: INST RocketTile__GCB0 PIN 1108 TYPE 3 INST FPU__GB1 PIN 709 TYPE 4
-INST DCache PIN 132: INST RocketTile__GCB0 PIN 1039 TYPE 3 INST FPU__GB1 PIN 710 TYPE 4
-INST RocketTile__GCB0 PIN 198: INST TilePRCIDomain__GC0 PIN 531 TYPE 0 GENOME RocketTile__GCB0 PIN 198
-INST RocketTile__GCB0 PIN 202: INST TilePRCIDomain__GC0 PIN 732 TYPE 0 GENOME RocketTile__GCB0 PIN 202
-INST RocketTile__GCB0 PIN 203: INST TilePRCIDomain__GC0 PIN 733 TYPE 0 GENOME RocketTile__GCB0 PIN 203
-INST VCU118RocketSystem__GC0 PIN 331: INST NON_GENOME PIN 34 TYPE 0 GENOME VCU118RocketSystem__GC0 PIN 331
-INST VCU118RocketSystem__GC0 PIN 334: INST VCU118RocketSystem__GC0 PIN 335 TYPE 2 INST NON_GENOME PIN 46 TYPE 4 INST VCU118RocketSystem__GC0 PIN 336 TYPE 2 INST NON_GENOME PIN 47 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 344: INST VCU118RocketSystem__GC0 PIN 345 TYPE 2 INST NON_GENOME PIN 56 TYPE 4 INST VCU118RocketSystem__GC0 PIN 346 TYPE 2 INST NON_GENOME PIN 57 TYPE 4
-INST RocketTile__GCB0 PIN 2: GENOME RocketTile__GCB0 PIN 2
-INST RocketTile__GCB0 PIN 3: GENOME RocketTile__GCB0 PIN 3
-INST RocketTile__GCB0 PIN 4: GENOME RocketTile__GCB0 PIN 4
-INST RocketTile__GCB0 PIN 5: GENOME RocketTile__GCB0 PIN 5
-INST RocketTile__GCB0 PIN 6: GENOME RocketTile__GCB0 PIN 6
-INST RocketTile__GCB0 PIN 7: GENOME RocketTile__GCB0 PIN 7
-INST RocketTile__GCB0 PIN 8: GENOME RocketTile__GCB0 PIN 8
-INST RocketTile__GCB0 PIN 9: GENOME RocketTile__GCB0 PIN 9
-INST RocketTile__GCB0 PIN 10: GENOME RocketTile__GCB0 PIN 10
-INST RocketTile__GCB0 PIN 11: GENOME RocketTile__GCB0 PIN 11
-INST RocketTile__GCB0 PIN 12: GENOME RocketTile__GCB0 PIN 12
-INST RocketTile__GCB0 PIN 13: GENOME RocketTile__GCB0 PIN 13
-INST RocketTile__GCB0 PIN 14: GENOME RocketTile__GCB0 PIN 14
-INST RocketTile__GCB0 PIN 15: GENOME RocketTile__GCB0 PIN 15
-INST RocketTile__GCB0 PIN 16: GENOME RocketTile__GCB0 PIN 16
-INST RocketTile__GCB0 PIN 17: GENOME RocketTile__GCB0 PIN 17
-INST RocketTile__GCB0 PIN 18: GENOME RocketTile__GCB0 PIN 18
-INST RocketTile__GCB0 PIN 19: GENOME RocketTile__GCB0 PIN 19
-INST RocketTile__GCB0 PIN 20: GENOME RocketTile__GCB0 PIN 20
-INST RocketTile__GCB0 PIN 21: GENOME RocketTile__GCB0 PIN 21
-INST RocketTile__GCB0 PIN 22: GENOME RocketTile__GCB0 PIN 22
-INST RocketTile__GCB0 PIN 23: GENOME RocketTile__GCB0 PIN 23
-INST RocketTile__GCB0 PIN 24: GENOME RocketTile__GCB0 PIN 24
-INST RocketTile__GCB0 PIN 25: GENOME RocketTile__GCB0 PIN 25
-INST RocketTile__GCB0 PIN 26: GENOME RocketTile__GCB0 PIN 26
-INST RocketTile__GCB0 PIN 27: GENOME RocketTile__GCB0 PIN 27
-INST RocketTile__GCB0 PIN 28: GENOME RocketTile__GCB0 PIN 28
-INST RocketTile__GCB0 PIN 29: GENOME RocketTile__GCB0 PIN 29
-INST RocketTile__GCB0 PIN 30: GENOME RocketTile__GCB0 PIN 30
-INST RocketTile__GCB0 PIN 31: GENOME RocketTile__GCB0 PIN 31
-INST RocketTile__GCB0 PIN 32: GENOME RocketTile__GCB0 PIN 32
-INST RocketTile__GCB0 PIN 33: GENOME RocketTile__GCB0 PIN 33
-INST RocketTile__GCB0 PIN 34: GENOME RocketTile__GCB0 PIN 34
-INST RocketTile__GCB0 PIN 35: GENOME RocketTile__GCB0 PIN 35
-INST RocketTile__GCB0 PIN 36: GENOME RocketTile__GCB0 PIN 36
-INST RocketTile__GCB0 PIN 37: GENOME RocketTile__GCB0 PIN 37
-INST RocketTile__GCB0 PIN 38: GENOME RocketTile__GCB0 PIN 38
-INST RocketTile__GCB0 PIN 39: GENOME RocketTile__GCB0 PIN 39
-INST RocketTile__GCB0 PIN 40: GENOME RocketTile__GCB0 PIN 40
-INST RocketTile__GCB0 PIN 41: GENOME RocketTile__GCB0 PIN 41
-INST RocketTile__GCB0 PIN 42: GENOME RocketTile__GCB0 PIN 42
-INST RocketTile__GCB0 PIN 43: GENOME RocketTile__GCB0 PIN 43
-INST RocketTile__GCB0 PIN 44: GENOME RocketTile__GCB0 PIN 44
-INST RocketTile__GCB0 PIN 45: GENOME RocketTile__GCB0 PIN 45
-INST RocketTile__GCB0 PIN 46: GENOME RocketTile__GCB0 PIN 46
-INST RocketTile__GCB0 PIN 47: GENOME RocketTile__GCB0 PIN 47
-INST RocketTile__GCB0 PIN 48: GENOME RocketTile__GCB0 PIN 48
-INST RocketTile__GCB0 PIN 49: GENOME RocketTile__GCB0 PIN 49
-INST RocketTile__GCB0 PIN 50: GENOME RocketTile__GCB0 PIN 50
-INST RocketTile__GCB0 PIN 51: GENOME RocketTile__GCB0 PIN 51
-INST RocketTile__GCB0 PIN 52: GENOME RocketTile__GCB0 PIN 52
-INST RocketTile__GCB0 PIN 53: GENOME RocketTile__GCB0 PIN 53
-INST RocketTile__GCB0 PIN 54: GENOME RocketTile__GCB0 PIN 54
-INST RocketTile__GCB0 PIN 55: GENOME RocketTile__GCB0 PIN 55
-INST RocketTile__GCB0 PIN 56: GENOME RocketTile__GCB0 PIN 56
-INST RocketTile__GCB0 PIN 57: GENOME RocketTile__GCB0 PIN 57
-INST RocketTile__GCB0 PIN 58: GENOME RocketTile__GCB0 PIN 58
-INST RocketTile__GCB0 PIN 59: GENOME RocketTile__GCB0 PIN 59
-INST RocketTile__GCB0 PIN 60: GENOME RocketTile__GCB0 PIN 60
-INST RocketTile__GCB0 PIN 61: GENOME RocketTile__GCB0 PIN 61
-INST RocketTile__GCB0 PIN 62: GENOME RocketTile__GCB0 PIN 62
-INST RocketTile__GCB0 PIN 63: GENOME RocketTile__GCB0 PIN 63
-INST RocketTile__GCB0 PIN 64: GENOME RocketTile__GCB0 PIN 64
-INST RocketTile__GCB0 PIN 65: GENOME RocketTile__GCB0 PIN 65
-INST RocketTile__GCB0 PIN 66: GENOME RocketTile__GCB0 PIN 66
-INST RocketTile__GCB0 PIN 67: GENOME RocketTile__GCB0 PIN 67
-INST RocketTile__GCB0 PIN 68: GENOME RocketTile__GCB0 PIN 68
-INST RocketTile__GCB0 PIN 69: GENOME RocketTile__GCB0 PIN 69
-INST RocketTile__GCB0 PIN 70: GENOME RocketTile__GCB0 PIN 70
-INST RocketTile__GCB0 PIN 71: GENOME RocketTile__GCB0 PIN 71
-INST RocketTile__GCB0 PIN 72: GENOME RocketTile__GCB0 PIN 72
-INST RocketTile__GCB0 PIN 73: GENOME RocketTile__GCB0 PIN 73
-INST RocketTile__GCB0 PIN 74: GENOME RocketTile__GCB0 PIN 74
-INST RocketTile__GCB0 PIN 325: GENOME RocketTile__GCB0 PIN 325
-INST RocketTile__GCB0 PIN 326: GENOME RocketTile__GCB0 PIN 326
-INST RocketTile__GCB0 PIN 465: GENOME RocketTile__GCB0 PIN 465
-INST RocketTile__GCB0 PIN 532: GENOME RocketTile__GCB0 PIN 532
-INST RocketTile__GCB0 PIN 599: GENOME RocketTile__GCB0 PIN 599
-INST RocketTile__GCB0 PIN 666: GENOME RocketTile__GCB0 PIN 666
-INST RocketTile__GCB0 PIN 733: GENOME RocketTile__GCB0 PIN 733
-INST RocketTile__GCB0 PIN 800: GENOME RocketTile__GCB0 PIN 800
-INST RocketTile__GCB0 PIN 867: GENOME RocketTile__GCB0 PIN 867
-INST RocketTile__GCB0 PIN 934: GENOME RocketTile__GCB0 PIN 934
-INST RocketTile__GCB0 PIN 1037: GENOME RocketTile__GCB0 PIN 1037
-INST RocketTile__GCB0 PIN 1038: GENOME RocketTile__GCB0 PIN 1038
-INST RocketTile__GCB0 PIN 1039: GENOME RocketTile__GCB0 PIN 1039
-INST RocketTile__GCB0 PIN 1040: GENOME RocketTile__GCB0 PIN 1040
-INST RocketTile__GCB0 PIN 1041: GENOME RocketTile__GCB0 PIN 1041
-INST RocketTile__GCB0 PIN 1042: GENOME RocketTile__GCB0 PIN 1042
-INST RocketTile__GCB0 PIN 1043: GENOME RocketTile__GCB0 PIN 1043
-INST RocketTile__GCB0 PIN 1044: GENOME RocketTile__GCB0 PIN 1044
-INST RocketTile__GCB0 PIN 1045: GENOME RocketTile__GCB0 PIN 1045
-INST RocketTile__GCB0 PIN 1046: GENOME RocketTile__GCB0 PIN 1046
-INST RocketTile__GCB0 PIN 1047: GENOME RocketTile__GCB0 PIN 1047
-INST RocketTile__GCB0 PIN 1048: GENOME RocketTile__GCB0 PIN 1048
-INST RocketTile__GCB0 PIN 1049: GENOME RocketTile__GCB0 PIN 1049
-INST RocketTile__GCB0 PIN 1050: GENOME RocketTile__GCB0 PIN 1050
-INST RocketTile__GCB0 PIN 1051: GENOME RocketTile__GCB0 PIN 1051
-INST RocketTile__GCB0 PIN 1052: GENOME RocketTile__GCB0 PIN 1052
-INST RocketTile__GCB0 PIN 1053: GENOME RocketTile__GCB0 PIN 1053
-INST RocketTile__GCB0 PIN 1054: GENOME RocketTile__GCB0 PIN 1054
-INST RocketTile__GCB0 PIN 1055: GENOME RocketTile__GCB0 PIN 1055
-INST RocketTile__GCB0 PIN 1056: GENOME RocketTile__GCB0 PIN 1056
-INST RocketTile__GCB0 PIN 1057: GENOME RocketTile__GCB0 PIN 1057
-INST RocketTile__GCB0 PIN 1058: GENOME RocketTile__GCB0 PIN 1058
-INST RocketTile__GCB0 PIN 1059: GENOME RocketTile__GCB0 PIN 1059
-INST RocketTile__GCB0 PIN 1060: GENOME RocketTile__GCB0 PIN 1060
-INST RocketTile__GCB0 PIN 1061: GENOME RocketTile__GCB0 PIN 1061
-INST RocketTile__GCB0 PIN 1062: GENOME RocketTile__GCB0 PIN 1062
-INST RocketTile__GCB0 PIN 1063: GENOME RocketTile__GCB0 PIN 1063
-INST RocketTile__GCB0 PIN 1064: GENOME RocketTile__GCB0 PIN 1064
-INST RocketTile__GCB0 PIN 1065: GENOME RocketTile__GCB0 PIN 1065
-INST RocketTile__GCB0 PIN 1066: GENOME RocketTile__GCB0 PIN 1066
-INST RocketTile__GCB0 PIN 1067: GENOME RocketTile__GCB0 PIN 1067
-INST RocketTile__GCB0 PIN 1068: GENOME RocketTile__GCB0 PIN 1068
-INST RocketTile__GCB0 PIN 1069: GENOME RocketTile__GCB0 PIN 1069
-INST RocketTile__GCB0 PIN 1070: GENOME RocketTile__GCB0 PIN 1070
-INST RocketTile__GCB0 PIN 1071: GENOME RocketTile__GCB0 PIN 1071
-INST RocketTile__GCB0 PIN 1072: GENOME RocketTile__GCB0 PIN 1072
-INST RocketTile__GCB0 PIN 1073: GENOME RocketTile__GCB0 PIN 1073
-INST RocketTile__GCB0 PIN 1074: GENOME RocketTile__GCB0 PIN 1074
-INST RocketTile__GCB0 PIN 1075: GENOME RocketTile__GCB0 PIN 1075
-INST RocketTile__GCB0 PIN 1076: GENOME RocketTile__GCB0 PIN 1076
-INST RocketTile__GCB0 PIN 1077: GENOME RocketTile__GCB0 PIN 1077
-INST RocketTile__GCB0 PIN 1078: GENOME RocketTile__GCB0 PIN 1078
-INST RocketTile__GCB0 PIN 1079: GENOME RocketTile__GCB0 PIN 1079
-INST RocketTile__GCB0 PIN 1080: GENOME RocketTile__GCB0 PIN 1080
-INST RocketTile__GCB0 PIN 1081: GENOME RocketTile__GCB0 PIN 1081
-INST RocketTile__GCB0 PIN 1082: GENOME RocketTile__GCB0 PIN 1082
-INST RocketTile__GCB0 PIN 1083: GENOME RocketTile__GCB0 PIN 1083
-INST RocketTile__GCB0 PIN 1084: GENOME RocketTile__GCB0 PIN 1084
-INST RocketTile__GCB0 PIN 1085: GENOME RocketTile__GCB0 PIN 1085
-INST RocketTile__GCB0 PIN 1086: GENOME RocketTile__GCB0 PIN 1086
-INST RocketTile__GCB0 PIN 1087: GENOME RocketTile__GCB0 PIN 1087
-INST RocketTile__GCB0 PIN 1088: GENOME RocketTile__GCB0 PIN 1088
-INST RocketTile__GCB0 PIN 1089: GENOME RocketTile__GCB0 PIN 1089
-INST RocketTile__GCB0 PIN 1090: GENOME RocketTile__GCB0 PIN 1090
-INST RocketTile__GCB0 PIN 1091: GENOME RocketTile__GCB0 PIN 1091
-INST RocketTile__GCB0 PIN 1092: GENOME RocketTile__GCB0 PIN 1092
-INST RocketTile__GCB0 PIN 1093: GENOME RocketTile__GCB0 PIN 1093
-INST RocketTile__GCB0 PIN 1094: GENOME RocketTile__GCB0 PIN 1094
-INST RocketTile__GCB0 PIN 1095: GENOME RocketTile__GCB0 PIN 1095
-INST RocketTile__GCB0 PIN 1096: GENOME RocketTile__GCB0 PIN 1096
-INST RocketTile__GCB0 PIN 1097: GENOME RocketTile__GCB0 PIN 1097
-INST RocketTile__GCB0 PIN 1098: GENOME RocketTile__GCB0 PIN 1098
-INST RocketTile__GCB0 PIN 1099: GENOME RocketTile__GCB0 PIN 1099
-INST RocketTile__GCB0 PIN 1100: GENOME RocketTile__GCB0 PIN 1100
-INST RocketTile__GCB0 PIN 1101: GENOME RocketTile__GCB0 PIN 1101
-INST RocketTile__GCB0 PIN 1102: GENOME RocketTile__GCB0 PIN 1102
-INST RocketTile__GCB0 PIN 1103: GENOME RocketTile__GCB0 PIN 1103
-INST RocketTile__GCB0 PIN 1104: GENOME RocketTile__GCB0 PIN 1104
-INST RocketTile__GCB0 PIN 1105: GENOME RocketTile__GCB0 PIN 1105
-INST RocketTile__GCB0 PIN 1106: GENOME RocketTile__GCB0 PIN 1106
-INST RocketTile__GCB0 PIN 1107: GENOME RocketTile__GCB0 PIN 1107
-INST RocketTile__GCB0 PIN 1108: GENOME RocketTile__GCB0 PIN 1108
-INST RocketTile__GCB0 PIN 1125: GENOME RocketTile__GCB0 PIN 1125
-INST RocketTile__GCB0 PIN 1126: GENOME RocketTile__GCB0 PIN 1126
-INST RocketTile__GCB0 PIN 1161: GENOME RocketTile__GCB0 PIN 1161
-INST RocketTile__GCB0 PIN 1162: GENOME RocketTile__GCB0 PIN 1162
-INST RocketTile__GCB0 PIN 1163: GENOME RocketTile__GCB0 PIN 1163
-INST RocketTile__GCB0 PIN 1164: GENOME RocketTile__GCB0 PIN 1164
-INST RocketTile__GCB0 PIN 1644: GENOME RocketTile__GCB0 PIN 1644
-INST RocketTile__GCB0 PIN 1645: GENOME RocketTile__GCB0 PIN 1645
-GENOME NON_GENOME PIN 1241: GENOME NON_GENOME PIN 2
-GENOME NON_GENOME PIN 2: GENOME NON_GENOME PIN 1241
-GENOME NON_GENOME PIN 1242: GENOME NON_GENOME PIN 3
-GENOME NON_GENOME PIN 3: GENOME NON_GENOME PIN 1242
-GENOME NON_GENOME PIN 1243: GENOME NON_GENOME PIN 4
-GENOME NON_GENOME PIN 4: GENOME NON_GENOME PIN 1243
-GENOME NON_GENOME PIN 1246: GENOME NON_GENOME PIN 5
-GENOME NON_GENOME PIN 5: GENOME NON_GENOME PIN 1246
-GENOME NON_GENOME PIN 1247: GENOME NON_GENOME PIN 6
-GENOME NON_GENOME PIN 6: GENOME NON_GENOME PIN 1247
-GENOME NON_GENOME PIN 1248: GENOME NON_GENOME PIN 7
-GENOME NON_GENOME PIN 7: GENOME NON_GENOME PIN 1248
-GENOME NON_GENOME PIN 1249: GENOME NON_GENOME PIN 8
-GENOME NON_GENOME PIN 8: GENOME NON_GENOME PIN 1249
-GENOME NON_GENOME PIN 1252: GENOME NON_GENOME PIN 9
-GENOME NON_GENOME PIN 9: GENOME NON_GENOME PIN 1252
-GENOME NON_GENOME PIN 1253: GENOME NON_GENOME PIN 10
-GENOME NON_GENOME PIN 10: GENOME NON_GENOME PIN 1253
-GENOME NON_GENOME PIN 1254: GENOME NON_GENOME PIN 11
-GENOME NON_GENOME PIN 11: GENOME NON_GENOME PIN 1254
-GENOME NON_GENOME PIN 1255: GENOME NON_GENOME PIN 12
-GENOME NON_GENOME PIN 12: GENOME NON_GENOME PIN 1255
-GENOME NON_GENOME PIN 1256: GENOME NON_GENOME PIN 13
-GENOME NON_GENOME PIN 13: GENOME NON_GENOME PIN 1256
-GENOME NON_GENOME PIN 1257: GENOME NON_GENOME PIN 14
-GENOME NON_GENOME PIN 14: GENOME NON_GENOME PIN 1257
-GENOME NON_GENOME PIN 1258: GENOME NON_GENOME PIN 15
-GENOME NON_GENOME PIN 15: GENOME NON_GENOME PIN 1258
-GENOME NON_GENOME PIN 1259: GENOME NON_GENOME PIN 16
-GENOME NON_GENOME PIN 16: GENOME NON_GENOME PIN 1259
-GENOME NON_GENOME PIN 1260: GENOME NON_GENOME PIN 17
-GENOME NON_GENOME PIN 17: GENOME NON_GENOME PIN 1260
-GENOME NON_GENOME PIN 1261: GENOME NON_GENOME PIN 18
-GENOME NON_GENOME PIN 18: GENOME NON_GENOME PIN 1261
-GENOME NON_GENOME PIN 1262: GENOME NON_GENOME PIN 19
-GENOME NON_GENOME PIN 19: GENOME NON_GENOME PIN 1262
-GENOME NON_GENOME PIN 1263: GENOME NON_GENOME PIN 20
-GENOME NON_GENOME PIN 20: GENOME NON_GENOME PIN 1263
-GENOME NON_GENOME PIN 1264: GENOME NON_GENOME PIN 21
-GENOME NON_GENOME PIN 21: GENOME NON_GENOME PIN 1264
-GENOME NON_GENOME PIN 1265: GENOME NON_GENOME PIN 22
-GENOME NON_GENOME PIN 22: GENOME NON_GENOME PIN 1265
-GENOME NON_GENOME PIN 1266: GENOME NON_GENOME PIN 23
-GENOME NON_GENOME PIN 23: GENOME NON_GENOME PIN 1266
-GENOME NON_GENOME PIN 1267: GENOME NON_GENOME PIN 24
-GENOME NON_GENOME PIN 24: GENOME NON_GENOME PIN 1267
-GENOME NON_GENOME PIN 1268: GENOME NON_GENOME PIN 25
-GENOME NON_GENOME PIN 25: GENOME NON_GENOME PIN 1268
-GENOME NON_GENOME PIN 1269: GENOME NON_GENOME PIN 26
-GENOME NON_GENOME PIN 26: GENOME NON_GENOME PIN 1269
-GENOME NON_GENOME PIN 1270: GENOME NON_GENOME PIN 27
-GENOME NON_GENOME PIN 27: GENOME NON_GENOME PIN 1270
-GENOME NON_GENOME PIN 1271: GENOME NON_GENOME PIN 28
-GENOME NON_GENOME PIN 28: GENOME NON_GENOME PIN 1271
-GENOME NON_GENOME PIN 1272: GENOME NON_GENOME PIN 29
-GENOME NON_GENOME PIN 29: GENOME NON_GENOME PIN 1272
-GENOME NON_GENOME PIN 1273: GENOME NON_GENOME PIN 30
-GENOME NON_GENOME PIN 30: GENOME NON_GENOME PIN 1273
-GENOME NON_GENOME PIN 1274: GENOME NON_GENOME PIN 31
-GENOME NON_GENOME PIN 31: GENOME NON_GENOME PIN 1274
-GENOME NON_GENOME PIN 1275: GENOME NON_GENOME PIN 32
-GENOME NON_GENOME PIN 32: GENOME NON_GENOME PIN 1275
-GENOME NON_GENOME PIN 1276: GENOME NON_GENOME PIN 33
-GENOME NON_GENOME PIN 33: GENOME NON_GENOME PIN 1276
-GENOME NON_GENOME PIN 1277: GENOME NON_GENOME PIN 34
-GENOME NON_GENOME PIN 34: GENOME NON_GENOME PIN 1277
-GENOME NON_GENOME PIN 1278: GENOME NON_GENOME PIN 35
-GENOME NON_GENOME PIN 35: GENOME NON_GENOME PIN 1278
-GENOME NON_GENOME PIN 1279: GENOME NON_GENOME PIN 36
-GENOME NON_GENOME PIN 36: GENOME NON_GENOME PIN 1279
-GENOME NON_GENOME PIN 1280: GENOME NON_GENOME PIN 37
-GENOME NON_GENOME PIN 37: GENOME NON_GENOME PIN 1280
-GENOME NON_GENOME PIN 1281: GENOME NON_GENOME PIN 38
-GENOME NON_GENOME PIN 38: GENOME NON_GENOME PIN 1281
-GENOME NON_GENOME PIN 1282: GENOME NON_GENOME PIN 39
-GENOME NON_GENOME PIN 39: GENOME NON_GENOME PIN 1282
-GENOME NON_GENOME PIN 1283: GENOME NON_GENOME PIN 40
-GENOME NON_GENOME PIN 40: GENOME NON_GENOME PIN 1283
-GENOME NON_GENOME PIN 1284: GENOME NON_GENOME PIN 41
-GENOME NON_GENOME PIN 41: GENOME NON_GENOME PIN 1284
-GENOME NON_GENOME PIN 1285: GENOME NON_GENOME PIN 42
-GENOME NON_GENOME PIN 42: GENOME NON_GENOME PIN 1285
-GENOME NON_GENOME PIN 1286: GENOME NON_GENOME PIN 43
-GENOME NON_GENOME PIN 43: GENOME NON_GENOME PIN 1286
-GENOME NON_GENOME PIN 1287: GENOME NON_GENOME PIN 44
-GENOME NON_GENOME PIN 44: GENOME NON_GENOME PIN 1287
-GENOME NON_GENOME PIN 1288: GENOME NON_GENOME PIN 45
-GENOME NON_GENOME PIN 1289: GENOME NON_GENOME PIN 46
-GENOME NON_GENOME PIN 46: GENOME NON_GENOME PIN 1289
-GENOME NON_GENOME PIN 1290: GENOME NON_GENOME PIN 47
-GENOME NON_GENOME PIN 47: GENOME NON_GENOME PIN 1290
-GENOME NON_GENOME PIN 1291: GENOME NON_GENOME PIN 48
-GENOME NON_GENOME PIN 48: GENOME NON_GENOME PIN 1291
-GENOME NON_GENOME PIN 1292: GENOME NON_GENOME PIN 49
-GENOME NON_GENOME PIN 49: GENOME NON_GENOME PIN 1292
-GENOME NON_GENOME PIN 1293: GENOME NON_GENOME PIN 50
-GENOME NON_GENOME PIN 50: GENOME NON_GENOME PIN 1293
-GENOME NON_GENOME PIN 1294: GENOME NON_GENOME PIN 51
-GENOME NON_GENOME PIN 51: GENOME NON_GENOME PIN 1294
-GENOME NON_GENOME PIN 1295: GENOME NON_GENOME PIN 52
-GENOME NON_GENOME PIN 52: GENOME NON_GENOME PIN 1295
-GENOME NON_GENOME PIN 1296: GENOME NON_GENOME PIN 53
-GENOME NON_GENOME PIN 53: GENOME NON_GENOME PIN 1296
-GENOME NON_GENOME PIN 1297: GENOME NON_GENOME PIN 54
-GENOME NON_GENOME PIN 54: GENOME NON_GENOME PIN 1297
-GENOME NON_GENOME PIN 1298: GENOME NON_GENOME PIN 55
-GENOME NON_GENOME PIN 55: GENOME NON_GENOME PIN 1298
-GENOME NON_GENOME PIN 1299: GENOME NON_GENOME PIN 56
-GENOME NON_GENOME PIN 56: GENOME NON_GENOME PIN 1299
-GENOME NON_GENOME PIN 1300: GENOME NON_GENOME PIN 57
-GENOME NON_GENOME PIN 57: GENOME NON_GENOME PIN 1300
-GENOME NON_GENOME PIN 1301: GENOME NON_GENOME PIN 58
-GENOME NON_GENOME PIN 58: GENOME NON_GENOME PIN 1301
-GENOME NON_GENOME PIN 1302: GENOME NON_GENOME PIN 59
-GENOME NON_GENOME PIN 59: GENOME NON_GENOME PIN 1302
-GENOME NON_GENOME PIN 1303: GENOME NON_GENOME PIN 60
-GENOME NON_GENOME PIN 60: GENOME NON_GENOME PIN 1303
-GENOME NON_GENOME PIN 1304: GENOME NON_GENOME PIN 61
-GENOME NON_GENOME PIN 61: GENOME NON_GENOME PIN 1304
-GENOME NON_GENOME PIN 1305: GENOME NON_GENOME PIN 62
-GENOME NON_GENOME PIN 62: GENOME NON_GENOME PIN 1305
-GENOME NON_GENOME PIN 1306: GENOME NON_GENOME PIN 63
-GENOME NON_GENOME PIN 63: GENOME NON_GENOME PIN 1306
-GENOME NON_GENOME PIN 1307: GENOME NON_GENOME PIN 64
-GENOME NON_GENOME PIN 64: GENOME NON_GENOME PIN 1307
-GENOME NON_GENOME PIN 1308: GENOME NON_GENOME PIN 65
-GENOME NON_GENOME PIN 65: GENOME NON_GENOME PIN 1308
-GENOME NON_GENOME PIN 1309: GENOME NON_GENOME PIN 66
-GENOME NON_GENOME PIN 66: GENOME NON_GENOME PIN 1309
-GENOME NON_GENOME PIN 1310: GENOME NON_GENOME PIN 67
-GENOME NON_GENOME PIN 67: GENOME NON_GENOME PIN 1310
-GENOME NON_GENOME PIN 1311: GENOME NON_GENOME PIN 68
-GENOME NON_GENOME PIN 68: GENOME NON_GENOME PIN 1311
-GENOME NON_GENOME PIN 1312: GENOME NON_GENOME PIN 69
-GENOME NON_GENOME PIN 69: GENOME NON_GENOME PIN 1312
-GENOME NON_GENOME PIN 1313: GENOME NON_GENOME PIN 70
-GENOME NON_GENOME PIN 70: GENOME NON_GENOME PIN 1313
-GENOME NON_GENOME PIN 1314: GENOME NON_GENOME PIN 71
-GENOME NON_GENOME PIN 71: GENOME NON_GENOME PIN 1314
-GENOME NON_GENOME PIN 1315: GENOME NON_GENOME PIN 72
-GENOME NON_GENOME PIN 72: GENOME NON_GENOME PIN 1315
-GENOME NON_GENOME PIN 1316: GENOME NON_GENOME PIN 73
-GENOME NON_GENOME PIN 73: GENOME NON_GENOME PIN 1316
-GENOME NON_GENOME PIN 83: GENOME NON_GENOME PIN 119 GENOME NON_GENOME PIN 120
-GENOME NON_GENOME PIN 119: GENOME NON_GENOME PIN 83
-GENOME NON_GENOME PIN 120: GENOME NON_GENOME PIN 83
-GENOME NON_GENOME PIN 324: GENOME NON_GENOME PIN 315 GENOME NON_GENOME PIN 325
-GENOME NON_GENOME PIN 315: GENOME NON_GENOME PIN 324 GENOME NON_GENOME PIN 326
-GENOME NON_GENOME PIN 325: GENOME NON_GENOME PIN 324
-GENOME NON_GENOME PIN 326: GENOME NON_GENOME PIN 315
-GENOME NON_GENOME PIN 465: GENOME NON_GENOME PIN 403 GENOME NON_GENOME PIN 464
-GENOME NON_GENOME PIN 470: GENOME NON_GENOME PIN 532
-GENOME NON_GENOME PIN 532: GENOME NON_GENOME PIN 470
-GENOME NON_GENOME PIN 537: GENOME NON_GENOME PIN 599
-GENOME NON_GENOME PIN 599: GENOME NON_GENOME PIN 537
-GENOME NON_GENOME PIN 604: GENOME NON_GENOME PIN 666
-GENOME NON_GENOME PIN 666: GENOME NON_GENOME PIN 604
-GENOME NON_GENOME PIN 671: GENOME NON_GENOME PIN 733
-GENOME NON_GENOME PIN 733: GENOME NON_GENOME PIN 671
-GENOME NON_GENOME PIN 738: GENOME NON_GENOME PIN 800
-GENOME NON_GENOME PIN 800: GENOME NON_GENOME PIN 738
-GENOME NON_GENOME PIN 867: GENOME NON_GENOME PIN 805
-GENOME NON_GENOME PIN 872: GENOME NON_GENOME PIN 934
-GENOME NON_GENOME PIN 934: GENOME NON_GENOME PIN 872
-GENOME NON_GENOME PIN 1445: GENOME NON_GENOME PIN 1038
-GENOME NON_GENOME PIN 1038: GENOME NON_GENOME PIN 1445
-GENOME NON_GENOME PIN 1446: GENOME NON_GENOME PIN 1039
-GENOME NON_GENOME PIN 1039: GENOME NON_GENOME PIN 1446
-GENOME NON_GENOME PIN 1438: GENOME NON_GENOME PIN 1040
-GENOME NON_GENOME PIN 1040: GENOME NON_GENOME PIN 1438
-GENOME NON_GENOME PIN 1439: GENOME NON_GENOME PIN 1041
-GENOME NON_GENOME PIN 1041: GENOME NON_GENOME PIN 1439
-GENOME NON_GENOME PIN 1440: GENOME NON_GENOME PIN 1042
-GENOME NON_GENOME PIN 1042: GENOME NON_GENOME PIN 1440
-GENOME NON_GENOME PIN 1441: GENOME NON_GENOME PIN 1043
-GENOME NON_GENOME PIN 1043: GENOME NON_GENOME PIN 1441
-GENOME NON_GENOME PIN 1442: GENOME NON_GENOME PIN 1044
-GENOME NON_GENOME PIN 1044: GENOME NON_GENOME PIN 1442
-GENOME NON_GENOME PIN 1513: GENOME NON_GENOME PIN 1045
-GENOME NON_GENOME PIN 1045: GENOME NON_GENOME PIN 1513
-GENOME NON_GENOME PIN 1514: GENOME NON_GENOME PIN 1046
-GENOME NON_GENOME PIN 1046: GENOME NON_GENOME PIN 1514
-GENOME NON_GENOME PIN 1515: GENOME NON_GENOME PIN 1047
-GENOME NON_GENOME PIN 1047: GENOME NON_GENOME PIN 1515
-GENOME NON_GENOME PIN 1516: GENOME NON_GENOME PIN 1048
-GENOME NON_GENOME PIN 1048: GENOME NON_GENOME PIN 1516
-GENOME NON_GENOME PIN 1517: GENOME NON_GENOME PIN 1049
-GENOME NON_GENOME PIN 1049: GENOME NON_GENOME PIN 1517
-GENOME NON_GENOME PIN 1518: GENOME NON_GENOME PIN 1050
-GENOME NON_GENOME PIN 1050: GENOME NON_GENOME PIN 1518
-GENOME NON_GENOME PIN 1519: GENOME NON_GENOME PIN 1051
-GENOME NON_GENOME PIN 1051: GENOME NON_GENOME PIN 1519
-GENOME NON_GENOME PIN 1520: GENOME NON_GENOME PIN 1052
-GENOME NON_GENOME PIN 1052: GENOME NON_GENOME PIN 1520
-GENOME NON_GENOME PIN 1521: GENOME NON_GENOME PIN 1053
-GENOME NON_GENOME PIN 1053: GENOME NON_GENOME PIN 1521
-GENOME NON_GENOME PIN 1522: GENOME NON_GENOME PIN 1054
-GENOME NON_GENOME PIN 1054: GENOME NON_GENOME PIN 1522
-GENOME NON_GENOME PIN 1523: GENOME NON_GENOME PIN 1055
-GENOME NON_GENOME PIN 1055: GENOME NON_GENOME PIN 1523
-GENOME NON_GENOME PIN 1524: GENOME NON_GENOME PIN 1056
-GENOME NON_GENOME PIN 1056: GENOME NON_GENOME PIN 1524
-GENOME NON_GENOME PIN 1525: GENOME NON_GENOME PIN 1057
-GENOME NON_GENOME PIN 1057: GENOME NON_GENOME PIN 1525
-GENOME NON_GENOME PIN 1526: GENOME NON_GENOME PIN 1058
-GENOME NON_GENOME PIN 1058: GENOME NON_GENOME PIN 1526
-GENOME NON_GENOME PIN 1527: GENOME NON_GENOME PIN 1059
-GENOME NON_GENOME PIN 1059: GENOME NON_GENOME PIN 1527
-GENOME NON_GENOME PIN 1528: GENOME NON_GENOME PIN 1060
-GENOME NON_GENOME PIN 1060: GENOME NON_GENOME PIN 1528
-GENOME NON_GENOME PIN 1529: GENOME NON_GENOME PIN 1061
-GENOME NON_GENOME PIN 1061: GENOME NON_GENOME PIN 1529
-GENOME NON_GENOME PIN 1530: GENOME NON_GENOME PIN 1062
-GENOME NON_GENOME PIN 1062: GENOME NON_GENOME PIN 1530
-GENOME NON_GENOME PIN 1531: GENOME NON_GENOME PIN 1063
-GENOME NON_GENOME PIN 1063: GENOME NON_GENOME PIN 1531
-GENOME NON_GENOME PIN 1532: GENOME NON_GENOME PIN 1064
-GENOME NON_GENOME PIN 1064: GENOME NON_GENOME PIN 1532
-GENOME NON_GENOME PIN 1533: GENOME NON_GENOME PIN 1065
-GENOME NON_GENOME PIN 1065: GENOME NON_GENOME PIN 1533
-GENOME NON_GENOME PIN 1534: GENOME NON_GENOME PIN 1066
-GENOME NON_GENOME PIN 1066: GENOME NON_GENOME PIN 1534
-GENOME NON_GENOME PIN 1535: GENOME NON_GENOME PIN 1067
-GENOME NON_GENOME PIN 1067: GENOME NON_GENOME PIN 1535
-GENOME NON_GENOME PIN 1536: GENOME NON_GENOME PIN 1068
-GENOME NON_GENOME PIN 1068: GENOME NON_GENOME PIN 1536
-GENOME NON_GENOME PIN 1537: GENOME NON_GENOME PIN 1069
-GENOME NON_GENOME PIN 1069: GENOME NON_GENOME PIN 1537
-GENOME NON_GENOME PIN 1538: GENOME NON_GENOME PIN 1070
-GENOME NON_GENOME PIN 1070: GENOME NON_GENOME PIN 1538
-GENOME NON_GENOME PIN 1539: GENOME NON_GENOME PIN 1071
-GENOME NON_GENOME PIN 1071: GENOME NON_GENOME PIN 1539
-GENOME NON_GENOME PIN 1540: GENOME NON_GENOME PIN 1072
-GENOME NON_GENOME PIN 1072: GENOME NON_GENOME PIN 1540
-GENOME NON_GENOME PIN 1541: GENOME NON_GENOME PIN 1073
-GENOME NON_GENOME PIN 1073: GENOME NON_GENOME PIN 1541
-GENOME NON_GENOME PIN 1542: GENOME NON_GENOME PIN 1074
-GENOME NON_GENOME PIN 1074: GENOME NON_GENOME PIN 1542 GENOME NON_GENOME PIN 1012
-GENOME NON_GENOME PIN 1543: GENOME NON_GENOME PIN 1075
-GENOME NON_GENOME PIN 1075: GENOME NON_GENOME PIN 1543
-GENOME NON_GENOME PIN 1544: GENOME NON_GENOME PIN 1076
-GENOME NON_GENOME PIN 1076: GENOME NON_GENOME PIN 1544
-GENOME NON_GENOME PIN 1545: GENOME NON_GENOME PIN 1077
-GENOME NON_GENOME PIN 1077: GENOME NON_GENOME PIN 1545
-GENOME NON_GENOME PIN 1546: GENOME NON_GENOME PIN 1078
-GENOME NON_GENOME PIN 1078: GENOME NON_GENOME PIN 1546
-GENOME NON_GENOME PIN 1547: GENOME NON_GENOME PIN 1079
-GENOME NON_GENOME PIN 1079: GENOME NON_GENOME PIN 1547
-GENOME NON_GENOME PIN 1548: GENOME NON_GENOME PIN 1080
-GENOME NON_GENOME PIN 1080: GENOME NON_GENOME PIN 1548
-GENOME NON_GENOME PIN 1549: GENOME NON_GENOME PIN 1081
-GENOME NON_GENOME PIN 1081: GENOME NON_GENOME PIN 1549
-GENOME NON_GENOME PIN 1550: GENOME NON_GENOME PIN 1082
-GENOME NON_GENOME PIN 1082: GENOME NON_GENOME PIN 1550
-GENOME NON_GENOME PIN 1551: GENOME NON_GENOME PIN 1083
-GENOME NON_GENOME PIN 1083: GENOME NON_GENOME PIN 1551
-GENOME NON_GENOME PIN 1552: GENOME NON_GENOME PIN 1084
-GENOME NON_GENOME PIN 1084: GENOME NON_GENOME PIN 1552
-GENOME NON_GENOME PIN 1553: GENOME NON_GENOME PIN 1085
-GENOME NON_GENOME PIN 1085: GENOME NON_GENOME PIN 1553
-GENOME NON_GENOME PIN 1554: GENOME NON_GENOME PIN 1086
-GENOME NON_GENOME PIN 1086: GENOME NON_GENOME PIN 1554
-GENOME NON_GENOME PIN 1555: GENOME NON_GENOME PIN 1087
-GENOME NON_GENOME PIN 1087: GENOME NON_GENOME PIN 1555
-GENOME NON_GENOME PIN 1556: GENOME NON_GENOME PIN 1088
-GENOME NON_GENOME PIN 1088: GENOME NON_GENOME PIN 1556
-GENOME NON_GENOME PIN 1557: GENOME NON_GENOME PIN 1089
-GENOME NON_GENOME PIN 1089: GENOME NON_GENOME PIN 1557
-GENOME NON_GENOME PIN 1558: GENOME NON_GENOME PIN 1090
-GENOME NON_GENOME PIN 1090: GENOME NON_GENOME PIN 1558
-GENOME NON_GENOME PIN 1559: GENOME NON_GENOME PIN 1091
-GENOME NON_GENOME PIN 1091: GENOME NON_GENOME PIN 1559
-GENOME NON_GENOME PIN 1560: GENOME NON_GENOME PIN 1092
-GENOME NON_GENOME PIN 1092: GENOME NON_GENOME PIN 1560
-GENOME NON_GENOME PIN 1561: GENOME NON_GENOME PIN 1093
-GENOME NON_GENOME PIN 1093: GENOME NON_GENOME PIN 1561
-GENOME NON_GENOME PIN 1562: GENOME NON_GENOME PIN 1094
-GENOME NON_GENOME PIN 1094: GENOME NON_GENOME PIN 1562
-GENOME NON_GENOME PIN 1563: GENOME NON_GENOME PIN 1095
-GENOME NON_GENOME PIN 1095: GENOME NON_GENOME PIN 1563
-GENOME NON_GENOME PIN 1564: GENOME NON_GENOME PIN 1096
-GENOME NON_GENOME PIN 1096: GENOME NON_GENOME PIN 1564
-GENOME NON_GENOME PIN 1565: GENOME NON_GENOME PIN 1097
-GENOME NON_GENOME PIN 1097: GENOME NON_GENOME PIN 1565
-GENOME NON_GENOME PIN 1566: GENOME NON_GENOME PIN 1098
-GENOME NON_GENOME PIN 1098: GENOME NON_GENOME PIN 1566
-GENOME NON_GENOME PIN 1567: GENOME NON_GENOME PIN 1099
-GENOME NON_GENOME PIN 1099: GENOME NON_GENOME PIN 1567
-GENOME NON_GENOME PIN 1568: GENOME NON_GENOME PIN 1100
-GENOME NON_GENOME PIN 1100: GENOME NON_GENOME PIN 1568
-GENOME NON_GENOME PIN 1569: GENOME NON_GENOME PIN 1101
-GENOME NON_GENOME PIN 1101: GENOME NON_GENOME PIN 1569
-GENOME NON_GENOME PIN 1570: GENOME NON_GENOME PIN 1102
-GENOME NON_GENOME PIN 1102: GENOME NON_GENOME PIN 1570
-GENOME NON_GENOME PIN 1571: GENOME NON_GENOME PIN 1103
-GENOME NON_GENOME PIN 1103: GENOME NON_GENOME PIN 1571
-GENOME NON_GENOME PIN 1572: GENOME NON_GENOME PIN 1104
-GENOME NON_GENOME PIN 1104: GENOME NON_GENOME PIN 1572
-GENOME NON_GENOME PIN 1573: GENOME NON_GENOME PIN 1105
-GENOME NON_GENOME PIN 1105: GENOME NON_GENOME PIN 1573
-GENOME NON_GENOME PIN 1574: GENOME NON_GENOME PIN 1106
-GENOME NON_GENOME PIN 1106: GENOME NON_GENOME PIN 1574
-GENOME NON_GENOME PIN 1575: GENOME NON_GENOME PIN 1107
-GENOME NON_GENOME PIN 1107: GENOME NON_GENOME PIN 1575
-GENOME NON_GENOME PIN 1576: GENOME NON_GENOME PIN 1108
-GENOME NON_GENOME PIN 1108: GENOME NON_GENOME PIN 1576
-INST RocketTile__GCB0 PIN 1241: INST TilePRCIDomain__GC0 PIN 4 TYPE 5
-INST RocketTile__GCB0 PIN 1242: INST TilePRCIDomain__GC0 PIN 5 TYPE 5
-INST RocketTile__GCB0 PIN 1252: INST TilePRCIDomain__GC0 PIN 15 TYPE 5
-INST RocketTile__GCB0 PIN 1445: INST DCache PIN 131 TYPE 5
-INST RocketTile__GCB0 PIN 1446: INST DCache PIN 132 TYPE 5
-INST RocketTile__GCB0 PIN 82: INST TilePRCIDomain__GC0 PIN 415 TYPE 0 GENOME RocketTile__GCB0 PIN 82
-INST RocketTile__GCB0 PIN 121: INST TilePRCIDomain__GC0 PIN 454 TYPE 0 GENOME RocketTile__GCB0 PIN 121
-INST RocketTile__GCB0 PIN 122: INST TilePRCIDomain__GC0 PIN 455 TYPE 0 GENOME RocketTile__GCB0 PIN 122
-INST DCache PIN 131: GENOME DCache PIN 131
-INST DCache PIN 336: GENOME DCache PIN 336
-INST DCache PIN 337: GENOME DCache PIN 337
-INST DCache PIN 465: GENOME DCache PIN 465 INST RocketTile__GCB0 PIN 324 TYPE 5
-INST DCache PIN 464: GENOME DCache PIN 464
-INST DCache PIN 466: GENOME DCache PIN 466 INST RocketTile__GCB0 PIN 315 TYPE 5
-INST DCache PIN 455: GENOME DCache PIN 455
-INST DCache PIN 605: GENOME DCache PIN 605 INST RocketTile__GCB0 PIN 403 TYPE 5
-INST DCache PIN 543: GENOME DCache PIN 543
-INST DCache PIN 606: GENOME DCache PIN 606
-INST DCache PIN 607: GENOME DCache PIN 607
-INST DCache PIN 672: GENOME DCache PIN 672 INST RocketTile__GCB0 PIN 470 TYPE 5
-INST DCache PIN 610: GENOME DCache PIN 610
-INST DCache PIN 673: GENOME DCache PIN 673
-INST DCache PIN 674: GENOME DCache PIN 674
-INST DCache PIN 739: GENOME DCache PIN 739 INST RocketTile__GCB0 PIN 537 TYPE 5
-INST DCache PIN 677: GENOME DCache PIN 677
-INST DCache PIN 740: GENOME DCache PIN 740
-INST DCache PIN 741: GENOME DCache PIN 741
-INST DCache PIN 806: GENOME DCache PIN 806 INST RocketTile__GCB0 PIN 604 TYPE 5
-INST DCache PIN 744: GENOME DCache PIN 744
-INST DCache PIN 807: GENOME DCache PIN 807
-INST DCache PIN 808: GENOME DCache PIN 808
-INST DCache PIN 873: GENOME DCache PIN 873 INST RocketTile__GCB0 PIN 671 TYPE 5
-INST DCache PIN 811: GENOME DCache PIN 811
-INST DCache PIN 874: GENOME DCache PIN 874
-INST DCache PIN 875: GENOME DCache PIN 875
-INST DCache PIN 940: GENOME DCache PIN 940 INST RocketTile__GCB0 PIN 738 TYPE 5
-INST DCache PIN 878: GENOME DCache PIN 878
-INST DCache PIN 941: GENOME DCache PIN 941
-INST DCache PIN 942: GENOME DCache PIN 942
-INST DCache PIN 1007: GENOME DCache PIN 1007 INST RocketTile__GCB0 PIN 805 TYPE 5
-INST DCache PIN 945: GENOME DCache PIN 945
-INST DCache PIN 1008: GENOME DCache PIN 1008
-INST DCache PIN 1009: GENOME DCache PIN 1009
-INST DCache PIN 1074: GENOME DCache PIN 1074 INST RocketTile__GCB0 PIN 872 TYPE 5
-INST DCache PIN 1012: GENOME DCache PIN 1012
-INST DCache PIN 1075: GENOME DCache PIN 1075
-INST DCache PIN 1076: GENOME DCache PIN 1076
-GENOME NON_GENOME PIN 464: GENOME NON_GENOME PIN 465
-GENOME NON_GENOME PIN 455: GENOME NON_GENOME PIN 466
-GENOME NON_GENOME PIN 466: GENOME NON_GENOME PIN 455
-GENOME NON_GENOME PIN 543: GENOME NON_GENOME PIN 605
-GENOME NON_GENOME PIN 605: GENOME NON_GENOME PIN 543
-GENOME NON_GENOME PIN 610: GENOME NON_GENOME PIN 672
-GENOME NON_GENOME PIN 672: GENOME NON_GENOME PIN 610
-GENOME NON_GENOME PIN 677: GENOME NON_GENOME PIN 739
-GENOME NON_GENOME PIN 739: GENOME NON_GENOME PIN 677
-GENOME NON_GENOME PIN 744: GENOME NON_GENOME PIN 806
-GENOME NON_GENOME PIN 811: GENOME NON_GENOME PIN 873
-GENOME NON_GENOME PIN 873: GENOME NON_GENOME PIN 811
-GENOME NON_GENOME PIN 878: GENOME NON_GENOME PIN 940
-GENOME NON_GENOME PIN 940: GENOME NON_GENOME PIN 878
-GENOME NON_GENOME PIN 945: GENOME NON_GENOME PIN 1007
-GENOME NON_GENOME PIN 1007: GENOME NON_GENOME PIN 945
-GENOME NON_GENOME PIN 1012: GENOME NON_GENOME PIN 1074
-INST VCU118RocketSystem__GC0 PIN 83: GENOME VCU118RocketSystem__GC0 PIN 83
-INST VCU118RocketSystem__GC0 PIN 84: GENOME VCU118RocketSystem__GC0 PIN 84
-INST VCU118RocketSystem__GC0 PIN 85: GENOME VCU118RocketSystem__GC0 PIN 85
-INST VCU118RocketSystem__GC0 PIN 86: GENOME VCU118RocketSystem__GC0 PIN 86
-INST VCU118RocketSystem__GC0 PIN 87: GENOME VCU118RocketSystem__GC0 PIN 87
-INST VCU118RocketSystem__GC0 PIN 126: GENOME VCU118RocketSystem__GC0 PIN 126
-INST VCU118RocketSystem__GC0 PIN 127: GENOME VCU118RocketSystem__GC0 PIN 127
-INST VCU118RocketSystem__GC0 PIN 128: GENOME VCU118RocketSystem__GC0 PIN 128
-INST VCU118RocketSystem__GC0 PIN 129: GENOME VCU118RocketSystem__GC0 PIN 129
-INST VCU118RocketSystem__GC0 PIN 130: GENOME VCU118RocketSystem__GC0 PIN 130
-INST VCU118RocketSystem__GC0 PIN 131: GENOME VCU118RocketSystem__GC0 PIN 131
-INST VCU118RocketSystem__GC0 PIN 132: GENOME VCU118RocketSystem__GC0 PIN 132
-INST VCU118RocketSystem__GC0 PIN 133: GENOME VCU118RocketSystem__GC0 PIN 133
-INST VCU118RocketSystem__GC0 PIN 134: GENOME VCU118RocketSystem__GC0 PIN 134
-INST VCU118RocketSystem__GC0 PIN 135: GENOME VCU118RocketSystem__GC0 PIN 135
-INST VCU118RocketSystem__GC0 PIN 136: GENOME VCU118RocketSystem__GC0 PIN 136
-INST VCU118RocketSystem__GC0 PIN 169: GENOME VCU118RocketSystem__GC0 PIN 169
-INST VCU118RocketSystem__GC0 PIN 171: GENOME VCU118RocketSystem__GC0 PIN 171
-INST VCU118RocketSystem__GC0 PIN 172: GENOME VCU118RocketSystem__GC0 PIN 172
-INST VCU118RocketSystem__GC0 PIN 289: GENOME VCU118RocketSystem__GC0 PIN 289
-INST VCU118RocketSystem__GC0 PIN 335: GENOME VCU118RocketSystem__GC0 PIN 335
-INST VCU118RocketSystem__GC0 PIN 336: GENOME VCU118RocketSystem__GC0 PIN 336
-INST VCU118RocketSystem__GC0 PIN 345: GENOME VCU118RocketSystem__GC0 PIN 345
-INST VCU118RocketSystem__GC0 PIN 346: GENOME VCU118RocketSystem__GC0 PIN 346
-INST VCU118RocketSystem__GC0 PIN 500: GENOME VCU118RocketSystem__GC0 PIN 500
-INST VCU118RocketSystem__GC0 PIN 501: GENOME VCU118RocketSystem__GC0 PIN 501
-INST VCU118RocketSystem__GC0 PIN 503: GENOME VCU118RocketSystem__GC0 PIN 503
-INST VCU118RocketSystem__GC0 PIN 504: GENOME VCU118RocketSystem__GC0 PIN 504
-INST VCU118RocketSystem__GC0 PIN 514: GENOME VCU118RocketSystem__GC0 PIN 514
-INST VCU118RocketSystem__GC0 PIN 561: GENOME VCU118RocketSystem__GC0 PIN 561
-INST VCU118RocketSystem__GC0 PIN 562: GENOME VCU118RocketSystem__GC0 PIN 562
-INST VCU118RocketSystem__GC0 PIN 627: GENOME VCU118RocketSystem__GC0 PIN 627
-GENOME NON_GENOME PIN 371: GENOME NON_GENOME PIN 79
-GENOME NON_GENOME PIN 79: GENOME NON_GENOME PIN 371
-GENOME NON_GENOME PIN 372: GENOME NON_GENOME PIN 80
-GENOME NON_GENOME PIN 80: GENOME NON_GENOME PIN 372
-GENOME NON_GENOME PIN 367: GENOME NON_GENOME PIN 171
-GENOME NON_GENOME PIN 171: GENOME NON_GENOME PIN 367
-GENOME NON_GENOME PIN 368: GENOME NON_GENOME PIN 172
-GENOME NON_GENOME PIN 172: GENOME NON_GENOME PIN 368
-GENOME NON_GENOME PIN 334: GENOME NON_GENOME PIN 335 GENOME NON_GENOME PIN 336
-GENOME NON_GENOME PIN 335: GENOME NON_GENOME PIN 334
-GENOME NON_GENOME PIN 336: GENOME NON_GENOME PIN 334
-GENOME NON_GENOME PIN 344: GENOME NON_GENOME PIN 345 GENOME NON_GENOME PIN 346
-GENOME NON_GENOME PIN 345: GENOME NON_GENOME PIN 344
-GENOME NON_GENOME PIN 346: GENOME NON_GENOME PIN 344
-INST FPU__GB1 PIN 1: GENOME FPU__GB1 PIN 1
-INST FPU__GB1 PIN 137: GENOME FPU__GB1 PIN 137
-INST FPU__GB1 PIN 162: GENOME FPU__GB1 PIN 162
-INST FPU__GB1 PIN 525: GENOME FPU__GB1 PIN 525
-INST FPU__GB1 PIN 526: GENOME FPU__GB1 PIN 526
-INST FPU__GB1 PIN 527: GENOME FPU__GB1 PIN 527
-INST FPU__GB1 PIN 528: GENOME FPU__GB1 PIN 528
-INST FPU__GB1 PIN 531: GENOME FPU__GB1 PIN 531
-INST FPU__GB1 PIN 532: GENOME FPU__GB1 PIN 532
-INST FPU__GB1 PIN 533: GENOME FPU__GB1 PIN 533
-GENOME NON_GENOME PIN 536: GENOME NON_GENOME PIN 146
-GENOME NON_GENOME PIN 146: GENOME NON_GENOME PIN 536
-INST TilePRCIDomain__GC0 PIN 4: GENOME TilePRCIDomain__GC0 PIN 4
-INST TilePRCIDomain__GC0 PIN 7: GENOME TilePRCIDomain__GC0 PIN 7
-INST TilePRCIDomain__GC0 PIN 8: GENOME TilePRCIDomain__GC0 PIN 8
-INST TilePRCIDomain__GC0 PIN 14: GENOME TilePRCIDomain__GC0 PIN 14
-INST TilePRCIDomain__GC0 PIN 15: GENOME TilePRCIDomain__GC0 PIN 15
-INST TilePRCIDomain__GC0 PIN 415: GENOME TilePRCIDomain__GC0 PIN 415
-INST TilePRCIDomain__GC0 PIN 454: GENOME TilePRCIDomain__GC0 PIN 454
-INST TilePRCIDomain__GC0 PIN 455: GENOME TilePRCIDomain__GC0 PIN 455
-INST TilePRCIDomain__GC0 PIN 531: GENOME TilePRCIDomain__GC0 PIN 531
-INST TilePRCIDomain__GC0 PIN 732: GENOME TilePRCIDomain__GC0 PIN 732
-INST TilePRCIDomain__GC0 PIN 733: GENOME TilePRCIDomain__GC0 PIN 733
-INST APBGpsBlock__GCB0 PIN 35: GENOME APBGpsBlock__GCB0 PIN 35
-INST APBGpsBlock__GCB0 PIN 246: GENOME APBGpsBlock__GCB0 PIN 246
-INST TLToAPB PIN 52: GENOME TLToAPB PIN 52
-INST FPU__GB2 PIN 1: INST FPU__GB1 PIN 146 TYPE 3 INST RocketTile__GCB0 PIN 1654 TYPE 4
-INST RocketTile__GCB0 PIN 83: INST RocketTile__GCB0 PIN 119 TYPE 2 INST TilePRCIDomain__GC0 PIN 452 TYPE 4 INST RocketTile__GCB0 PIN 120 TYPE 2 INST TilePRCIDomain__GC0 PIN 453 TYPE 4
-INST RocketTile__GCB0 PIN 119: GENOME RocketTile__GCB0 PIN 119
-INST RocketTile__GCB0 PIN 120: GENOME RocketTile__GCB0 PIN 120
-INST TilePRCIDomain__GC0 PIN 452: GENOME TilePRCIDomain__GC0 PIN 452 INST RocketTile__GCB0 PIN 83 TYPE 5
-INST TilePRCIDomain__GC0 PIN 416: GENOME TilePRCIDomain__GC0 PIN 416
-INST TilePRCIDomain__GC0 PIN 453: GENOME TilePRCIDomain__GC0 PIN 453 INST RocketTile__GCB0 PIN 83 TYPE 5
-GENOME NON_GENOME PIN 416: GENOME NON_GENOME PIN 452 GENOME NON_GENOME PIN 453
-GENOME NON_GENOME PIN 452: GENOME NON_GENOME PIN 416
-GENOME NON_GENOME PIN 453: GENOME NON_GENOME PIN 416
-INST FPU__GB1 PIN 146: GENOME FPU__GB1 PIN 146
-INST FPU__GB1 PIN 536: INST FPU__GB2 PIN 1 TYPE 5
-DISSOLVE_GENOME: GENOME tracking_wrapper
-INST TilePRCIDomain__GC0 PIN 204: INST VCU118RocketSystem__GC0 PIN 496 TYPE 0
-INST TilePRCIDomain__GC0 PIN 208: INST VCU118RocketSystem__GC0 PIN 551 TYPE 0
-INST TilePRCIDomain__GC0 PIN 212: INST VCU118RocketSystem__GC0 PIN 555 TYPE 0
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/equivDumpFile.info b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/equivDumpFile.info
deleted file mode 100644
index 21e5042..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/equivDumpFile.info
+++ /dev/null
@@ -1,157 +0,0 @@
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#5:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#3
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#6:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#4
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#9:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#5
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#10:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#6
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#11:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#7
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#12:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#8
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#16:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#10
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#17:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#11
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#18:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#12
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#19:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#13
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#20:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#14
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#21:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#15
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#22:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#16
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#23:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#17
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#24:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#18
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#25:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#19
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#26:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#20
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#27:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#21
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#28:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#22
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#29:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#23
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#30:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#24
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#31:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#25
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#32:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#26
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#33:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#27
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#34:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#28
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#35:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#29
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#36:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#30
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#37:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#31
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#38:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#32
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#39:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#33
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#40:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#34
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#41:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#35
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#42:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#36
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#43:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#37
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#44:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#38
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#45:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#39
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#46:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#40
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#47:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#41
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#48:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#42
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#49:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#43
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#50:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#44
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#51:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#45
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#52:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#46
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#53:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#47
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#54:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#48
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#55:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#49
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#56:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#50
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#57:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#51
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#58:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#52
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#59:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#53
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#60:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#54
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#61:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#55
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#62:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#56
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#63:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#57
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#64:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#58
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#65:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#59
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#66:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#60
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#67:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#61
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#68:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#62
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#69:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#63
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#70:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#64
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#71:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#65
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#72:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#66
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#73:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#67
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#74:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#68
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#75:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#69
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#76:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#70
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#77:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#71
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#78:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#72
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#79:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#73
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#324:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#325
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#315:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#326
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#403:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#465
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#470:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#532
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#537:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#599
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#604:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#666
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#671:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#733
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#738:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#800
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#805:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#867
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#872:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#934
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#124:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1040
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#125:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1041
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#126:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1042
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#127:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1043
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#128:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1044
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#199:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1045
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#200:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1046
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#201:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1047
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#202:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1048
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#203:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1049
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#204:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1050
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#205:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1051
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#206:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1052
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#207:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1053
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#208:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1054
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#209:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1055
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#210:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1056
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#211:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1057
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#212:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1058
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#213:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1059
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#214:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1060
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#215:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1061
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#216:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1062
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#217:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1063
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#218:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1064
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#219:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1065
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#220:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1066
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#221:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1067
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#222:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1068
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#223:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1069
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#224:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1070
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#225:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1071
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#226:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1072
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#227:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1073
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#228:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1074
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#229:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1075
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#230:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1076
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#231:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1077
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#232:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1078
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#233:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1079
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#234:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1080
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#235:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1081
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#236:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1082
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#237:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1083
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#238:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1084
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#239:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1085
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#240:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1086
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#241:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1087
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#242:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1088
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#243:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1089
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#244:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1090
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#245:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1091
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#246:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1092
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#247:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1093
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#248:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1094
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#249:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1095
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#250:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1096
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#251:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1097
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#252:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1098
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#253:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1099
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#254:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1100
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#255:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1101
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#256:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1102
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#257:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1103
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#258:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1104
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#259:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1105
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#260:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1106
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#261:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1107
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#262:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1108
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#132:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1039
-/u_rocket/VCU118RocketSystem__GC0#334:/u_rocket/VCU118RocketSystem__GC0#335
-/u_rocket/VCU118RocketSystem__GC0#334:/u_rocket/VCU118RocketSystem__GC0#336
-/u_rocket/VCU118RocketSystem__GC0#344:/u_rocket/VCU118RocketSystem__GC0#345
-/u_rocket/VCU118RocketSystem__GC0#344:/u_rocket/VCU118RocketSystem__GC0#346
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2#1:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1#146
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#83:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#119
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#83:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#120
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1220760385.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1220760385.rtd
deleted file mode 100644
index a9561fa..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index 8fa2153..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1294509424.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1294509424.rtd
deleted file mode 100644
index 974b907..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index 55bf7ae..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/136113302.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/136113302.rtd
deleted file mode 100644
index 7c10b3a..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd
deleted file mode 100644
index 78088a5..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1672436263.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1672436263.rtd
deleted file mode 100644
index 30a671d..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index 6a8caf4..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2610937407.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2610937407.rtd
deleted file mode 100644
index 5a6a262..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index 1269de3..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2737226844.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2737226844.rtd
deleted file mode 100644
index 8cf3c30..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index c6794bf..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2962621930.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2962621930.rtd
deleted file mode 100644
index 14a5679..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index 552b0a2..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2996647647.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2996647647.rtd
deleted file mode 100644
index c3a0468..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2996647647.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2996647647.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2996647647.rtd.straps.rtd
deleted file mode 100644
index f9a0480..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2996647647.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2996647647.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2996647647.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2996647647.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2996647647.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/2996647647.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3315205705.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3315205705.rtd
deleted file mode 100644
index 808349f..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3315205705.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3315205705.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3315205705.rtd.straps.rtd
deleted file mode 100644
index 85ca4cb..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3315205705.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3315205705.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3315205705.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3315205705.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3315205705.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3315205705.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3482045580.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3482045580.rtd
deleted file mode 100644
index 1c18af0..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index 6fd1d4e..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3990655999.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3990655999.rtd
deleted file mode 100644
index 7d5dda0..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3990655999.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd
deleted file mode 100644
index 33bb221..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/976197094.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/976197094.rtd
deleted file mode 100644
index fce4728..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd
deleted file mode 100644
index 6a1e214..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/global_name.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/global_name.straps.rtd
deleted file mode 100644
index cd831d9..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/instToEncGenName.map b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/instToEncGenName.map
deleted file mode 100644
index 2eb5ca4..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/g/instToEncGenName.map
+++ /dev/null
@@ -1,20 +0,0 @@
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
-/genesys2_rocket_top__GC0:3990655999
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GCB1:3315205705
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GCB0:2996647647
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/stitchPoint.lst b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/stitchPoint.lst
deleted file mode 100644
index b3b8212..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/stitchPoint.lst
+++ /dev/null
@@ -1,20 +0,0 @@
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GCB1
-/u_rocket/VCU118RocketSystem__GC0
-/u_rocket/fpga_gps_domain/tl2apb
-/u_rocket/fpga_gps_domain/dev/tracking_8
-/u_rocket/fpga_gps_domain/dev/tracking_7
-/u_rocket/fpga_gps_domain/dev/tracking_6
-/u_rocket/fpga_gps_domain/dev/tracking_5
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1
-/u_rocket/fpga_gps_domain/dev/tracking_4
-/u_rocket/fpga_gps_domain/dev/tracking_3
-/u_rocket/fpga_gps_domain/dev/tracking_2
-/genesys2_rocket_top__GC0
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2
-/u_rocket/fpga_gps_domain/dev/tracking_1
-/u_rocket/fpga_gps_domain/dev/tracking_0
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GCB0
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/53F669E0.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/53F669E0.rtd
deleted file mode 100644
index ae80697..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/53F669E0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/57A39820.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/57A39820.rtd
deleted file mode 100644
index 84fee9c..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/57A39820.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/58AE7C20.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/58AE7C20.rtd
deleted file mode 100644
index 81a7427..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/58AE7C20.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/5988A760.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/5988A760.rtd
deleted file mode 100644
index fdeaac8..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/5988A760.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/5AE1E420.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/5AE1E420.rtd
deleted file mode 100644
index 2a22fde..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/5AE1E420.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/5B8FEC00.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/5B8FEC00.rtd
deleted file mode 100644
index 5e59867..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/5B8FEC00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7A5CCD00.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7A5CCD00.rtd
deleted file mode 100644
index 93f163b..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7A5CCD00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7C364560.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7C364560.rtd
deleted file mode 100644
index 9a404df..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7C364560.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7F2F87A0.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7F2F87A0.rtd
deleted file mode 100644
index 5e548d6..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7F2F87A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7F2F9A00.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7F2F9A00.rtd
deleted file mode 100644
index db5402b..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/7F2F9A00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/8B672100.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/8B672100.rtd
deleted file mode 100644
index 7f74373..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/8B672100.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/9710DC80.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/9710DC80.rtd
deleted file mode 100644
index 2337e20..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/9710DC80.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/design.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/design.rtd
deleted file mode 100644
index 78ba572..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/files.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/files.rtd
deleted file mode 100644
index 20fb801..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/files.rtd
+++ /dev/null
@@ -1,14 +0,0 @@
-design.rtd
-straps.rtd
-5AE1E420.rtd
-57A39820.rtd
-5988A760.rtd
-8B672100.rtd
-7A5CCD00.rtd
-7F2F87A0.rtd
-53F669E0.rtd
-7F2F9A00.rtd
-5B8FEC00.rtd
-58AE7C20.rtd
-7C364560.rtd
-9710DC80.rtd
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/straps.rtd
deleted file mode 100644
index af02a48..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/uniqInferGenToOrigInferGen.map b/.Xil/Vivado-303406-onur/incrSyn/1309558296/o/uniqInferGenToOrigInferGen.map
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/childModToGenomes.map b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/childModToGenomes.map
deleted file mode 100644
index a39786a..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/childModToGenomes.map
+++ /dev/null
@@ -1,8252 +0,0 @@
-logic__4194: FPU__GB2,
-logic__1893: RocketTile__GCB0, DCache,
-case__94: VCU118RocketSystem__GC0,
-logic__289: VCU118RocketSystem__GC0,
-logic__2492: RocketTile__GCB0,
-case__1134: APBGpsBlock__GCB1,
-logic__5519: RocketTile__GCB0,
-logic__793: VCU118RocketSystem__GC0,
-case__482: FPU__GB2,
-reg__1136: tracking_wrapper,
-logic__4428: FPU__GB1,
-RoundAnyRawFNToRecFN_3: FPU__GB1,
-logic__948: VCU118RocketSystem__GC0,
-case__1543: APBGpsBlock__GCB0,
-reg__651: RocketTile__GCB0,
-datapath__655: tracking_wrapper,
-logic__7861: APBGpsBlock__GCB1,
-reg__1170: tracking_wrapper,
-logic__6824: VCU118RocketSystem__GC0,
-logic__7186: VCU118RocketSystem__GC0,
-logic__6791: VCU118RocketSystem__GC0,
-logic__7270: VCU118RocketSystem__GC0,
-reg__439: FPU__GB2,
-logic__5028: RocketTile__GCB0,
-case__1358: tracking_wrapper,
-case__219: VCU118RocketSystem__GC0,
-logic__6473: VCU118RocketSystem__GC0,
-logic__1263: VCU118RocketSystem__GC0,
-reg__462: FPU__GB1,
-logic__5359: RocketTile__GCB0,
-reg__1194: tracking_wrapper,
-reg__1243: tracking_wrapper,
-case__1366: tracking_wrapper,
-datapath__358: FPU__GB2, FPU__GB1,
-ram__2: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__378: FPU__GB0,
-case__206: VCU118RocketSystem__GC0,
-logic__8793: tracking_wrapper,
-reg__903: VCU118RocketSystem__GC0,
-case__824: VCU118RocketSystem__GC0,
-case__454: FPU__GB1,
-dual_port_bram__parameterized0: APBGpsBlock__GCB1,
-logic__4615: RocketTile__GCB0,
-reg__731: RocketTile__GCB0,
-logic__6946: VCU118RocketSystem__GC0,
-case__1195: APBGpsBlock__GCB1,
-logic__8082: APBGpsBlock__GCB1,
-muxpart__228: tracking_wrapper,
-case__479: FPU__GB2,
-logic__6483: VCU118RocketSystem__GC0,
-logic__6025: RocketTile__GCB0,
-CLINT: VCU118RocketSystem__GC0,
-case__488: FPU__GB2,
-logic__5360: RocketTile__GCB0,
-logic__2439: RocketTile__GCB0,
-logic__8434: tracking_wrapper,
-reg__83: VCU118RocketSystem__GC0,
-reg__789: VCU118RocketSystem__GC0,
-datapath__286: RocketTile__GCB0,
-reg__896: VCU118RocketSystem__GC0,
-logic__6952: VCU118RocketSystem__GC0,
-reg__803: VCU118RocketSystem__GC0,
-logic__3532: FPU__GB1,
-datapath__265: RocketTile__GCB0,
-logic__6818: VCU118RocketSystem__GC0,
-logic__6567: VCU118RocketSystem__GC0,
-reg__206: VCU118RocketSystem__GC0,
-reg__622: RocketTile__GCB0,
-datapath__446: RocketTile__GCB0,
-case__170: VCU118RocketSystem__GC0,
-case__161: VCU118RocketSystem__GC0,
-logic__3495: FPU__GB2,
-AsyncQueueSource_DebugInternalBundle: VCU118RocketSystem__GC0,
-reg__883: VCU118RocketSystem__GC0,
-logic__1178: VCU118RocketSystem__GC0,
-datapath__595: APBGpsBlock__GCB1,
-reg__1244: tracking_wrapper,
-datapath__84: VCU118RocketSystem__GC0,
-reg__49: VCU118RocketSystem__GC0,
-comp_mult: APBGpsBlock__GCB1,
-logic__9300: APBGpsBlock__GCB0,
-logic__6512: VCU118RocketSystem__GC0,
-datapath__121: VCU118RocketSystem__GC0,
-datapath__551: APBGpsBlock__GCB1,
-reg__419: FPU__GB1,
-logic__8283: tracking_wrapper,
-datapath__399: RocketTile__GCB0,
-logic__6386: VCU118RocketSystem__GC0,
-case__611: FPU__GB1,
-logic__3584: FPU__GB1,
-muxpart__10: DCache,
-reg__863: VCU118RocketSystem__GC0,
-logic__3945: FPU__GB2, FPU__GB1,
-reg__556: FPU__GB1,
-logic__2155: DCache,
-case__980: VCU118RocketSystem__GC0,
-reg__573: FPU__GB1,
-logic__508: VCU118RocketSystem__GC0,
-logic__124: VCU118RocketSystem__GC0,
-logic__2567: RocketTile__GCB0,
-logic__2123: DCache,
-muxpart__96: RocketTile__GCB0,
-logic__4362: FPU__GB1,
-datapath__280: RocketTile__GCB0,
-logic__3445: FPU__GB2,
-logic__7998: APBGpsBlock__GCB1,
-logic__4274: FPU__GB2,
-logic__9172: APBGpsBlock__GCB0,
-muxpart__301: APBGpsBlock__GCB0,
-logic__6472: VCU118RocketSystem__GC0,
-logic__7967: APBGpsBlock__GCB1,
-logic__4850: RocketTile__GCB0,
-logic__3934: FPU__GB2, FPU__GB1,
-logic__1186: VCU118RocketSystem__GC0,
-case__781: RocketTile__GCB0,
-logic__4731: RocketTile__GCB0,
-case__1278: APBGpsBlock__GCB1,
-logic__8717: tracking_wrapper,
-case__920: VCU118RocketSystem__GC0,
-logic__3457: FPU__GB2,
-reg__1219: tracking_wrapper,
-logic__4534: RocketTile__GCB0,
-reg__157: VCU118RocketSystem__GC0,
-case__1067: APBGpsBlock__GCB1,
-reg__834: VCU118RocketSystem__GC0,
-case__1386: tracking_wrapper,
-reg__284: DCache,
-signinv: RocketTile__GCB0,
-logic__3235: FPU__GB2,
-case__806: VCU118RocketSystem__GC0,
-reg__900: VCU118RocketSystem__GC0,
-reg__870: VCU118RocketSystem__GC0,
-logic__4168: FPU__GB2,
-case__1660: APBGpsBlock__GCB0,
-case__841: VCU118RocketSystem__GC0,
-logic__1791: DCache,
-logic__4427: FPU__GB1,
-datapath__193: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_pbus_to_fpga_uart: VCU118RocketSystem__GC0,
-case__1052: VCU118RocketSystem__GC0,
-logic__5048: RocketTile__GCB0,
-reg__557: FPU__GB1,
-logic__3351: FPU__GB2,
-logic__3804: FPU__GB1,
-logic__6020: RocketTile__GCB0,
-reg__881: VCU118RocketSystem__GC0,
-logic__5324: RocketTile__GCB0,
-datapath__247: DCache,
-case__363: DCache,
-logic__1875: RocketTile__GCB0, DCache,
-datapath__677: tracking_wrapper,
-reg__80: VCU118RocketSystem__GC0,
-logic__4699: RocketTile__GCB0,
-datapath__454: RocketTile__GCB0,
-logic__6572: VCU118RocketSystem__GC0,
-case__825: VCU118RocketSystem__GC0,
-reg__99: VCU118RocketSystem__GC0,
-ram__7: TilePRCIDomain__GC0,
-case__162: VCU118RocketSystem__GC0,
-logic__9155: APBGpsBlock__GCB0,
-logic__240: VCU118RocketSystem__GC0,
-reg__513: FPU__GB2,
-logic__5542: RocketTile__GCB0,
-logic__2121: DCache,
-case__1018: VCU118RocketSystem__GC0,
-logic__6251: VCU118RocketSystem__GC0,
-logic__1649: DCache,
-reg__617: RocketTile__GCB0,
-logic__9344: APBGpsBlock__GCB0,
-TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u: RocketTile__GCB0,
-muxpart__73: FPU__GB0,
-muxpart__26: FPU__GB0,
-case__905: VCU118RocketSystem__GC0,
-reg__809: VCU118RocketSystem__GC0,
-case__855: VCU118RocketSystem__GC0,
-logic__4770: RocketTile__GCB0,
-logic__4361: FPU__GB1,
-TLFragmenter_CLINT: VCU118RocketSystem__GC0,
-reg__322: RocketTile__GCB0,
-logic__1076: VCU118RocketSystem__GC0,
-logic__516: VCU118RocketSystem__GC0,
-logic__5654: RocketTile__GCB0,
-logic__4397: FPU__GB1,
-logic__6468: VCU118RocketSystem__GC0,
-logic__5361: RocketTile__GCB0,
-logic__7073: VCU118RocketSystem__GC0,
-logic__918: VCU118RocketSystem__GC0,
-logic__6539: VCU118RocketSystem__GC0,
-reg__989: VCU118RocketSystem__GC0,
-logic__4639: RocketTile__GCB0,
-keep__25: APBGpsBlock__GCB0,
-reg__544: FPU__GB1,
-datapath__718: APBGpsBlock__GCB0,
-logic__7891: APBGpsBlock__GCB1,
-case__385: RocketTile__GCB0,
-case__1179: APBGpsBlock__GCB1,
-logic__4790: RocketTile__GCB0,
-counter__16: APBGpsBlock__GCB1,
-datapath__441: RocketTile__GCB0,
-datapath__698: APBGpsBlock__GCB0,
-logic__3805: FPU__GB1,
-reg__1359: APBGpsBlock__GCB0,
-reg__1450: TLToAPB,
-reg__751: RocketTile__GCB0,
-case__1305: APBGpsBlock__GCB1,
-logic__4069: FPU__GB2,
-logic__2084: DCache,
-datapath__210: VCU118RocketSystem__GC0,
-logic__8654: tracking_wrapper,
-logic__8850: tracking_wrapper,
-reg__354: RocketTile__GCB0,
-logic__8786: tracking_wrapper,
-reg__588: RocketTile__GCB0,
-case__765: RocketTile__GCB0,
-logic__4682: RocketTile__GCB0,
-logic__2371: RocketTile__GCB0,
-logic__2854: FPU__GB1,
-case__1677: APBGpsBlock__GCB0,
-datapath__616: APBGpsBlock__GCB1,
-case__843: VCU118RocketSystem__GC0,
-case__446: FPU__GB0,
-cdc_fifo_gray_src: tracking_wrapper,
-logic__8538: tracking_wrapper,
-logic__3172: FPU__GB2,
-logic__3935: FPU__GB2, FPU__GB1,
-TLBuffer_a32d64s1k1z4u_1: RocketTile__GCB0,
-logic__935: VCU118RocketSystem__GC0,
-case__46: VCU118RocketSystem__GC0,
-logic__3899: FPU__GB2, FPU__GB1,
-reg__658: RocketTile__GCB0,
-case__876: VCU118RocketSystem__GC0,
-datapath__389: FPU__GB1,
-reg__1397: APBGpsBlock__GCB0,
-logic__6941: VCU118RocketSystem__GC0,
-logic__6591: VCU118RocketSystem__GC0,
-case__953: VCU118RocketSystem__GC0,
-case__19: genesys2_rocket_top__GC0,
-reg__44: VCU118RocketSystem__GC0,
-reg__1451: TLToAPB,
-reg__1441: APBGpsBlock__GCB0,
-logic__6252: VCU118RocketSystem__GC0,
-reg__247: DCache,
-datapath__542: APBGpsBlock__GCB1,
-logic__6090: RocketTile__GCB0,
-logic__4156: FPU__GB2,
-logic__6418: VCU118RocketSystem__GC0,
-logic__1172: VCU118RocketSystem__GC0,
-logic__6622: VCU118RocketSystem__GC0,
-reg__831: VCU118RocketSystem__GC0,
-muxpart__111: RocketTile__GCB0,
-reg__356: RocketTile__GCB0,
-logic__1619: DCache,
-logic__7607: VCU118RocketSystem__GC0,
-reg__389: FPU__GB0,
-TLFpgaUART: VCU118RocketSystem__GC0,
-datapath__123: VCU118RocketSystem__GC0,
-reg__1023: APBGpsBlock__GCB1,
-logic__9338: APBGpsBlock__GCB0,
-logic__6026: RocketTile__GCB0,
-logic__304: VCU118RocketSystem__GC0,
-case__138: VCU118RocketSystem__GC0,
-reg__1192: tracking_wrapper,
-reg__413: FPU__GB1,
-logic__4396: FPU__GB1,
-datapath__363: FPU__GB1,
-case__351: DCache,
-reg__1029: APBGpsBlock__GCB1,
-dsp48e1__2: APBGpsBlock__GCB1,
-logic__6162: VCU118RocketSystem__GC0,
-case__1167: APBGpsBlock__GCB1,
-logic__3840: FPU__GB1,
-logic__4745: RocketTile__GCB0,
-case__346: DCache,
-logic__2518: RocketTile__GCB0,
-reg__1227: tracking_wrapper,
-logic__9170: APBGpsBlock__GCB0,
-case__691: RocketTile__GCB0,
-logic__3095: FPU__GB2,
-logic__7315: VCU118RocketSystem__GC0,
-logic__7106: VCU118RocketSystem__GC0,
-case__1142: APBGpsBlock__GCB1,
-reg__364: RocketTile__GCB0,
-case__629: RocketTile__GCB0,
-logic__2814: FPU__GB1,
-datapath__300: FPU__GB2, FPU__GB1,
-case__1277: APBGpsBlock__GCB1,
-logic__762: VCU118RocketSystem__GC0,
-logic__5483: RocketTile__GCB0,
-datapath__31: VCU118RocketSystem__GC0,
-reg__786: VCU118RocketSystem__GC0,
-logic__5430: RocketTile__GCB0,
-logic__6833: VCU118RocketSystem__GC0,
-logic__456: VCU118RocketSystem__GC0,
-logic__6313: VCU118RocketSystem__GC0,
-logic__8734: tracking_wrapper,
-logic__1113: VCU118RocketSystem__GC0,
-datapath__23: VCU118RocketSystem__GC0,
-datapath__382: FPU__GB2,
-logic__3762: FPU__GB1,
-case__1300: APBGpsBlock__GCB1,
-logic__8806: tracking_wrapper,
-logic__4126: FPU__GB2,
-logic__8406: tracking_wrapper,
-logic__7655: VCU118RocketSystem__GC0,
-logic__6625: VCU118RocketSystem__GC0,
-logic__2961: FPU__GB1,
-reg__182: VCU118RocketSystem__GC0,
-logic__6093: RocketTile__GCB0,
-logic__5452: RocketTile__GCB0,
-logic__5419: RocketTile__GCB0,
-reg__605: RocketTile__GCB0,
-muxpart__48: FPU__GB0,
-logic__1386: VCU118RocketSystem__GC0,
-logic__4757: RocketTile__GCB0,
-reg__1352: APBGpsBlock__GCB0,
-muxpart__313: APBGpsBlock__GCB0,
-reg__746: RocketTile__GCB0,
-logic__8959: APBGpsBlock__GCB0,
-logic__4888: RocketTile__GCB0,
-reg__718: RocketTile__GCB0,
-logic__6611: VCU118RocketSystem__GC0,
-reg__1422: APBGpsBlock__GCB0,
-logic__8392: tracking_wrapper,
-datapath__292: FPU__GB1,
-logic__2862: FPU__GB1,
-logic__3214: FPU__GB2,
-case__1406: tracking_wrapper,
-logic__6347: VCU118RocketSystem__GC0,
-logic__4418: FPU__GB1,
-case__713: RocketTile__GCB0,
-logic__9187: APBGpsBlock__GCB0,
-reg__1239: tracking_wrapper,
-reg__677: RocketTile__GCB0,
-logic__2993: FPU__GB2, FPU__GB1,
-logic__4040: FPU__GB2,
-logic__6785: VCU118RocketSystem__GC0,
-logic__4288: FPU__GB2,
-logic__7310: VCU118RocketSystem__GC0,
-logic__2063: DCache,
-logic__85: genesys2_rocket_top__GC0,
-logic__2026: DCache,
-logic__3930: FPU__GB2, FPU__GB1,
-logic__2322: DCache,
-case__226: VCU118RocketSystem__GC0,
-logic__755: VCU118RocketSystem__GC0,
-logic__1824: DCache,
-logic__7037: VCU118RocketSystem__GC0,
-logic__3113: FPU__GB2,
-case__521: FPU__GB1,
-logic__344: VCU118RocketSystem__GC0,
-logic__2122: DCache,
-logic__5283: RocketTile__GCB0,
-logic__4303: FPU__GB1,
-reg__520: FPU__GB2,
-logic__1219: VCU118RocketSystem__GC0,
-logic__3767: FPU__GB1,
-logic__4771: RocketTile__GCB0,
-reg__5: genesys2_rocket_top__GC0,
-TLWidthWidget8_3: VCU118RocketSystem__GC0,
-reg__1130: APBGpsBlock__GCB0,
-logic__2655: RocketTile__GCB0,
-logic__2881: FPU__GB1,
-datapath__620: APBGpsBlock__GCB0,
-case__369: DCache,
-logic__4631: RocketTile__GCB0,
-logic__6600: VCU118RocketSystem__GC0,
-reg__1356: APBGpsBlock__GCB0,
-logic__7339: VCU118RocketSystem__GC0,
-logic__632: VCU118RocketSystem__GC0,
-logic__717: VCU118RocketSystem__GC0,
-reg__804: VCU118RocketSystem__GC0,
-logic__9286: APBGpsBlock__GCB0,
-case__949: VCU118RocketSystem__GC0,
-case__279: VCU118RocketSystem__GC0,
-logic__3712: FPU__GB1,
-reg__1340: tracking_wrapper,
-reg__741: RocketTile__GCB0,
-case__1311: APBGpsBlock__GCB1,
-muxpart__312: APBGpsBlock__GCB0,
-logic__9192: APBGpsBlock__GCB0,
-logic__947: VCU118RocketSystem__GC0,
-reg__95: VCU118RocketSystem__GC0,
-case__41: VCU118RocketSystem__GC0,
-datapath__727: APBGpsBlock__GCB0,
-logic__6754: VCU118RocketSystem__GC0,
-datapath__458: RocketTile__GCB0,
-muxpart__8: VCU118RocketSystem__GC0,
-logic__265: VCU118RocketSystem__GC0,
-logic__2599: RocketTile__GCB0,
-logic__4864: RocketTile__GCB0,
-logic__7590: VCU118RocketSystem__GC0,
-datapath__100: VCU118RocketSystem__GC0,
-datapath__131: VCU118RocketSystem__GC0,
-logic__3354: FPU__GB2,
-case__1014: VCU118RocketSystem__GC0,
-datapath__524: VCU118RocketSystem__GC0,
-TLAtomicAutomata_pbus: VCU118RocketSystem__GC0,
-extram__7: APBGpsBlock__GCB1,
-case__587: FPU__GB1,
-logic__8403: tracking_wrapper,
-genesys2_rocket_top__GC0: genesys2_rocket_top__GC0,
-case__829: VCU118RocketSystem__GC0,
-case__297: RocketTile__GCB0,
-case__1653: APBGpsBlock__GCB0,
-logic__8547: tracking_wrapper,
-reg__1200: tracking_wrapper,
-reg__656: RocketTile__GCB0,
-case__13: genesys2_rocket_top__GC0,
-case__508: FPU__GB1,
-logic__4447: FPU__GB1,
-reg__468: FPU__GB1,
-reg__545: FPU__GB1,
-reg__341: RocketTile__GCB0,
-case__1409: tracking_wrapper,
-case__962: VCU118RocketSystem__GC0,
-logic__8211: APBGpsBlock__GCB1,
-datapath__621: tracking_wrapper,
-logic__5363: RocketTile__GCB0,
-reg__1006: APBGpsBlock__GCB1,
-datapath__656: tracking_wrapper,
-logic__9110: APBGpsBlock__GCB0,
-logic__4446: FPU__GB1,
-case__783: RocketTile__GCB0,
-logic__6141: VCU118RocketSystem__GC0,
-datapath__184: VCU118RocketSystem__GC0,
-reg__488: FPU__GB1,
-logic__2144: DCache,
-logic__3271: FPU__GB2,
-case__1525: tracking_wrapper,
-case__1621: APBGpsBlock__GCB0,
-datapath__433: RocketTile__GCB0,
-logic__5095: RocketTile__GCB0,
-logic__9154: APBGpsBlock__GCB0,
-case__867: VCU118RocketSystem__GC0,
-logic__6023: RocketTile__GCB0,
-logic__1287: VCU118RocketSystem__GC0,
-logic__8404: tracking_wrapper,
-logic__5362: RocketTile__GCB0,
-case__1452: tracking_wrapper,
-logic__6769: VCU118RocketSystem__GC0,
-case__270: VCU118RocketSystem__GC0,
-logic__6280: VCU118RocketSystem__GC0,
-logic__460: VCU118RocketSystem__GC0,
-logic__6617: VCU118RocketSystem__GC0,
-logic__8548: tracking_wrapper,
-case__1387: tracking_wrapper,
-case__125: VCU118RocketSystem__GC0,
-case__84: VCU118RocketSystem__GC0,
-logic__2502: RocketTile__GCB0,
-logic__7741: APBGpsBlock__GCB1,
-datapath__422: RocketTile__GCB0,
-logic__6057: RocketTile__GCB0,
-datapath__344: FPU__GB1,
-datapath__75: VCU118RocketSystem__GC0,
-datapath__651: tracking_wrapper,
-datapath__627: tracking_wrapper,
-case__960: VCU118RocketSystem__GC0,
-logic__3884: FPU__GB1,
-reg__1009: APBGpsBlock__GCB1,
-logic__6217: VCU118RocketSystem__GC0,
-reg__394: FPU__GB0,
-reg__983: VCU118RocketSystem__GC0,
-logic__7563: VCU118RocketSystem__GC0,
-logic__4111: FPU__GB2,
-reg__388: FPU__GB0,
-logic__5298: RocketTile__GCB0,
-Queue2_TLBundleA_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__3233: FPU__GB2,
-ClockCrossingReg_w55: VCU118RocketSystem__GC0,
-datapath__13: VCU118RocketSystem__GC0,
-datapath__541: APBGpsBlock__GCB1,
-logic__885: VCU118RocketSystem__GC0,
-case__1223: APBGpsBlock__GCB1,
-dsp48e1__15: APBGpsBlock__GCB1,
-datapath__729: APBGpsBlock__GCB0,
-case__337: DCache,
-logic__3937: FPU__GB2, FPU__GB1,
-reg__1082: APBGpsBlock__GCB1,
-reg__1319: tracking_wrapper,
-logic__7589: VCU118RocketSystem__GC0,
-case__1006: VCU118RocketSystem__GC0,
-logic__5036: RocketTile__GCB0,
-datapath__255: DCache,
-logic__7156: VCU118RocketSystem__GC0,
-case__1177: APBGpsBlock__GCB1,
-logic__4167: FPU__GB2,
-datapath__476: VCU118RocketSystem__GC0,
-dsp48e1__30: tracking_wrapper,
-SynchronizerShiftReg_w1_d3: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__494: FPU__GB2,
-reg__343: RocketTile__GCB0,
-logic__6541: VCU118RocketSystem__GC0,
-reg__1111: APBGpsBlock__GCB1,
-logic__654: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__643: tracking_wrapper,
-logic__3032: FPU__GB2, FPU__GB1,
-logic__6763: VCU118RocketSystem__GC0,
-case__1326: APBGpsBlock__GCB1,
-reg__655: RocketTile__GCB0,
-logic__144: VCU118RocketSystem__GC0,
-logic__8252: APBGpsBlock__GCB1,
-logic__7189: VCU118RocketSystem__GC0,
-logic__9147: APBGpsBlock__GCB0,
-datapath__598: APBGpsBlock__GCB1,
-logic__7415: VCU118RocketSystem__GC0,
-case__137: VCU118RocketSystem__GC0,
-datapath__308: FPU__GB2,
-muxpart__232: tracking_wrapper,
-logic__2694: FPU__GB1,
-logic__6488: VCU118RocketSystem__GC0,
-logic__6248: VCU118RocketSystem__GC0,
-logic__1657: DCache,
-reg__1453: TLToAPB,
-logic__9239: APBGpsBlock__GCB0,
-logic__886: VCU118RocketSystem__GC0,
-case__910: VCU118RocketSystem__GC0,
-logic__1034: VCU118RocketSystem__GC0,
-reg__1366: APBGpsBlock__GCB0,
-datapath__367: FPU__GB2,
-logic__2054: DCache,
-reg__417: FPU__GB1,
-logic__6958: VCU118RocketSystem__GC0,
-reg__423: FPU__GB1,
-counter: genesys2_rocket_top__GC0,
-logic__6205: VCU118RocketSystem__GC0,
-logic__7821: APBGpsBlock__GCB1,
-datapath__237: RocketTile__GCB0,
-case__635: RocketTile__GCB0,
-logic__6926: VCU118RocketSystem__GC0,
-case__357: DCache,
-reg__250: DCache,
-logic__3386: FPU__GB2,
-logic__2726: FPU__GB1,
-logic__6819: VCU118RocketSystem__GC0,
-reg__845: VCU118RocketSystem__GC0,
-acq_ca_gen: APBGpsBlock__GCB1,
-logic__3770: FPU__GB1,
-logic__8801: tracking_wrapper,
-reg__1007: APBGpsBlock__GCB1,
-case__58: VCU118RocketSystem__GC0,
-reg__358: RocketTile__GCB0,
-logic__2885: FPU__GB1,
-case__1424: tracking_wrapper,
-case__601: FPU__GB1,
-reg__1358: APBGpsBlock__GCB0,
-case__758: RocketTile__GCB0,
-logic__2640: RocketTile__GCB0,
-reg__785: VCU118RocketSystem__GC0,
-FixedClockBroadcast_5: VCU118RocketSystem__GC0,
-reg__1228: tracking_wrapper,
-logic__2133: DCache,
-case__919: VCU118RocketSystem__GC0,
-reg__562: FPU__GB1,
-case__789: VCU118RocketSystem__GC0,
-logic__8360: tracking_wrapper,
-logic__7265: VCU118RocketSystem__GC0,
-logic__6537: VCU118RocketSystem__GC0,
-case__988: VCU118RocketSystem__GC0,
-logic__7580: VCU118RocketSystem__GC0,
-case__210: VCU118RocketSystem__GC0,
-datapath__136: VCU118RocketSystem__GC0,
-logic__4911: RocketTile__GCB0,
-counter__5: VCU118RocketSystem__GC0,
-double_ff_syn__parameterized1: tracking_wrapper,
-logic__4579: RocketTile__GCB0,
-muxpart__20: FPU__GB0,
-logic__5415: RocketTile__GCB0,
-logic__4867: RocketTile__GCB0,
-logic__706: VCU118RocketSystem__GC0,
-logic__384: VCU118RocketSystem__GC0,
-logic__4865: RocketTile__GCB0,
-reg__60: VCU118RocketSystem__GC0,
-case__586: FPU__GB1,
-logic__2562: RocketTile__GCB0,
-case__135: VCU118RocketSystem__GC0,
-logic__7303: VCU118RocketSystem__GC0,
-case__847: VCU118RocketSystem__GC0,
-datapath__647: tracking_wrapper,
-reg__1081: APBGpsBlock__GCB1,
-logic__7292: VCU118RocketSystem__GC0,
-reg__884: VCU118RocketSystem__GC0,
-reg__300: RocketTile__GCB0,
-TilePRCIDomain__GC0: TilePRCIDomain__GC0,
-logic__5969: RocketTile__GCB0,
-logic__6638: VCU118RocketSystem__GC0,
-logic__6188: VCU118RocketSystem__GC0,
-logic__675: VCU118RocketSystem__GC0,
-case__143: VCU118RocketSystem__GC0,
-IntSyncSyncCrossingSink_n1x1: TilePRCIDomain__GC0,
-logic__355: VCU118RocketSystem__GC0,
-logic__2137: DCache,
-logic__6219: VCU118RocketSystem__GC0,
-logic__3137: FPU__GB2,
-logic__4968: RocketTile__GCB0,
-logic__367: VCU118RocketSystem__GC0,
-logic__2351: RocketTile__GCB0,
-logic__2737: FPU__GB1,
-logic__4195: FPU__GB2,
-logic__1626: DCache,
-logic__3777: FPU__GB1,
-reg__962: VCU118RocketSystem__GC0,
-logic__6647: VCU118RocketSystem__GC0,
-logic__5970: RocketTile__GCB0,
-reg__241: DCache,
-logic__3939: FPU__GB2, FPU__GB1,
-case__979: VCU118RocketSystem__GC0,
-logic__8484: tracking_wrapper,
-case__23: VCU118RocketSystem__GC0,
-logic__9198: APBGpsBlock__GCB0,
-logic__4869: RocketTile__GCB0,
-case__743: RocketTile__GCB0,
-logic__7252: VCU118RocketSystem__GC0,
-logic__6803: VCU118RocketSystem__GC0,
-logic__696: VCU118RocketSystem__GC0,
-logic__5307: RocketTile__GCB0,
-logic__4300: FPU__GB2,
-case__780: RocketTile__GCB0,
-logic__1419: VCU118RocketSystem__GC0,
-reg__1279: tracking_wrapper,
-case__1237: APBGpsBlock__GCB1,
-muxpart__60: FPU__GB0,
-reg__1211: tracking_wrapper,
-logic__6659: VCU118RocketSystem__GC0,
-logic__244: VCU118RocketSystem__GC0,
-logic__2538: RocketTile__GCB0,
-reg__57: VCU118RocketSystem__GC0,
-logic__103: VCU118RocketSystem__GC0,
-logic__9146: APBGpsBlock__GCB0,
-logic__2739: FPU__GB1,
-logic__7421: VCU118RocketSystem__GC0,
-logic__8820: tracking_wrapper,
-reg__1291: tracking_wrapper,
-reg__757: RocketTile__GCB0,
-case__675: RocketTile__GCB0,
-logic__4027: FPU__GB2,
-logic__1169: VCU118RocketSystem__GC0,
-reg__270: DCache,
-ram__4: VCU118RocketSystem__GC0,
-dsp48e1__19: APBGpsBlock__GCB1,
-muxpart__74: FPU__GB0,
-logic__5352: RocketTile__GCB0,
-logic__8804: tracking_wrapper,
-reg__1378: APBGpsBlock__GCB0,
-TLWidthWidget8_4: VCU118RocketSystem__GC0,
-logic__6964: VCU118RocketSystem__GC0,
-case__906: VCU118RocketSystem__GC0,
-datapath__91: VCU118RocketSystem__GC0,
-logic__4431: FPU__GB1,
-logic__4894: RocketTile__GCB0,
-logic__7860: APBGpsBlock__GCB1,
-logic__2845: FPU__GB1,
-reg__594: RocketTile__GCB0,
-case__1285: APBGpsBlock__GCB1,
-reg__144: VCU118RocketSystem__GC0,
-logic__8466: tracking_wrapper,
-case__620: RocketTile__GCB0,
-logic__3430: FPU__GB2,
-logic__8979: APBGpsBlock__GCB0,
-logic__3822: FPU__GB1,
-reg__200: VCU118RocketSystem__GC0,
-reg__1086: APBGpsBlock__GCB1,
-logic__8068: APBGpsBlock__GCB1,
-logic__5522: RocketTile__GCB0,
-RVCExpander: RocketTile__GCB0,
-muxpart__229: tracking_wrapper,
-case__737: RocketTile__GCB0,
-reg__504: FPU__GB2,
-logic__7813: APBGpsBlock__GCB1,
-datapath__425: RocketTile__GCB0,
-reg__1182: tracking_wrapper,
-logic__8367: tracking_wrapper,
-case__602: FPU__GB1,
-logic__472: VCU118RocketSystem__GC0,
-logic__8709: tracking_wrapper,
-datapath__150: VCU118RocketSystem__GC0,
-datapath__251: DCache,
-reg__700: RocketTile__GCB0,
-logic__4019: FPU__GB1,
-datapath__619: APBGpsBlock__GCB1,
-reg__1047: APBGpsBlock__GCB1,
-reg__1368: APBGpsBlock__GCB0,
-logic__6052: RocketTile__GCB0,
-logic__6838: VCU118RocketSystem__GC0,
-reg__171: VCU118RocketSystem__GC0,
-reg__202: VCU118RocketSystem__GC0,
-logic__8405: tracking_wrapper,
-reg__925: VCU118RocketSystem__GC0,
-logic__9341: APBGpsBlock__GCB1,
-case__141: VCU118RocketSystem__GC0,
-case__255: VCU118RocketSystem__GC0,
-keep__1: APBGpsBlock__GCB1, tracking_wrapper,
-logic__6392: VCU118RocketSystem__GC0,
-case__191: VCU118RocketSystem__GC0,
-logic__4106: FPU__GB2,
-reg__864: VCU118RocketSystem__GC0,
-logic__1377: VCU118RocketSystem__GC0,
-case__562: FPU__GB2,
-case__139: VCU118RocketSystem__GC0,
-counter__14: APBGpsBlock__GCB1,
-logic__5673: RocketTile__GCB0,
-case__1654: APBGpsBlock__GCB0,
-logic__3769: FPU__GB1,
-reg__1330: tracking_wrapper,
-case__1178: APBGpsBlock__GCB1,
-reg__1223: tracking_wrapper,
-datapath__369: FPU__GB2,
-logic__917: VCU118RocketSystem__GC0,
-logic__7135: VCU118RocketSystem__GC0,
-case__864: VCU118RocketSystem__GC0,
-logic__7992: APBGpsBlock__GCB1,
-datapath__533: APBGpsBlock__GCB1,
-counter__17: APBGpsBlock__GCB0,
-datapath__588: APBGpsBlock__GCB1,
-datapath__24: VCU118RocketSystem__GC0,
-case__981: VCU118RocketSystem__GC0,
-logic__1275: VCU118RocketSystem__GC0,
-logic__5230: RocketTile__GCB0,
-logic__397: VCU118RocketSystem__GC0,
-logic__6032: RocketTile__GCB0,
-logic__9153: APBGpsBlock__GCB0,
-logic__5502: RocketTile__GCB0,
-logic__6059: RocketTile__GCB0,
-TLFragmenter_FPGAUART: VCU118RocketSystem__GC0,
-logic__2852: FPU__GB1,
-logic__2374: RocketTile__GCB0,
-case__29: VCU118RocketSystem__GC0,
-case__298: RocketTile__GCB0,
-logic__6747: VCU118RocketSystem__GC0,
-reg__783: VCU118RocketSystem__GC0,
-muxpart__5: VCU118RocketSystem__GC0,
-logic__1462: RocketTile__GCB0,
-reg__601: RocketTile__GCB0,
-counter__29: APBGpsBlock__GCB0,
-datapath__447: RocketTile__GCB0,
-logic__375: VCU118RocketSystem__GC0,
-logic__4180: FPU__GB2,
-case__929: VCU118RocketSystem__GC0,
-datapath__633: tracking_wrapper,
-logic__904: VCU118RocketSystem__GC0,
-case__404: RocketTile__GCB0,
-logic__6695: VCU118RocketSystem__GC0,
-logic__2503: RocketTile__GCB0,
-reg__523: FPU__GB2,
-logic__6469: VCU118RocketSystem__GC0,
-logic__8421: tracking_wrapper,
-logic__3332: FPU__GB2,
-datapath__529: APBGpsBlock__GCB1,
-datapath__514: VCU118RocketSystem__GC0,
-logic__477: VCU118RocketSystem__GC0,
-datapath__239: RocketTile__GCB0,
-FPToInt: FPU__GB2,
-logic__7253: VCU118RocketSystem__GC0,
-case__814: VCU118RocketSystem__GC0,
-case__1107: APBGpsBlock__GCB1,
-case__1064: APBGpsBlock__GCB1,
-case__714: RocketTile__GCB0,
-case__119: VCU118RocketSystem__GC0,
-logic__5413: RocketTile__GCB0,
-reg__1236: tracking_wrapper,
-logic__31: genesys2_rocket_top__GC0,
-logic__7175: VCU118RocketSystem__GC0,
-logic__9221: APBGpsBlock__GCB0,
-datapath__305: FPU__GB2,
-logic__5351: RocketTile__GCB0,
-logic__7439: VCU118RocketSystem__GC0,
-logic__6361: VCU118RocketSystem__GC0,
-DTLB: DCache,
-case__837: VCU118RocketSystem__GC0,
-reg__797: VCU118RocketSystem__GC0,
-logic__234: VCU118RocketSystem__GC0,
-logic__3089: FPU__GB2,
-case__933: VCU118RocketSystem__GC0,
-logic__5989: RocketTile__GCB0,
-logic__3938: FPU__GB2, FPU__GB1,
-reg__657: RocketTile__GCB0,
-logic__7601: VCU118RocketSystem__GC0,
-logic__7384: VCU118RocketSystem__GC0,
-reg__1161: tracking_wrapper,
-datapath__721: APBGpsBlock__GCB0,
-logic__9186: APBGpsBlock__GCB0,
-logic__3362: FPU__GB2,
-case__493: FPU__GB2,
-case__88: VCU118RocketSystem__GC0,
-reg__886: VCU118RocketSystem__GC0,
-reg__401: FPU__GB0,
-logic__956: VCU118RocketSystem__GC0,
-logic__2999: FPU__GB2, FPU__GB1,
-logic__4185: FPU__GB2,
-logic__6639: VCU118RocketSystem__GC0,
-logic__5071: RocketTile__GCB0,
-reg__1238: tracking_wrapper,
-datapath__739: VCU118RocketSystem__GC0,
-reg__853: VCU118RocketSystem__GC0,
-logic__7048: VCU118RocketSystem__GC0,
-logic__610: VCU118RocketSystem__GC0,
-case__394: RocketTile__GCB0,
-logic__8891: tracking_wrapper,
-logic__9361: TLToAPB,
-muxpart__167: APBGpsBlock__GCB1,
-logic__3771: FPU__GB1,
-case__522: FPU__GB1,
-datapath__49: VCU118RocketSystem__GC0,
-reg__382: FPU__GB0,
-case__650: RocketTile__GCB0,
-datapath__189: VCU118RocketSystem__GC0,
-logic__7901: APBGpsBlock__GCB1,
-case__441: RocketTile__GCB0,
-acq_nco_carr: APBGpsBlock__GCB1,
-logic__8892: tracking_wrapper,
-logic__2554: RocketTile__GCB0,
-reg__440: FPU__GB2,
-logic__6244: VCU118RocketSystem__GC0,
-reg__1019: APBGpsBlock__GCB1,
-logic__9293: APBGpsBlock__GCB0,
-logic__4761: RocketTile__GCB0,
-reg__137: VCU118RocketSystem__GC0,
-logic__7385: VCU118RocketSystem__GC0,
-logic__5903: RocketTile__GCB0,
-logic__7669: VCU118RocketSystem__GC0,
-logic__9332: APBGpsBlock__GCB0,
-FPToFP: FPU__GB1,
-logic__6703: VCU118RocketSystem__GC0,
-logic__4880: RocketTile__GCB0,
-logic__3021: FPU__GB2, FPU__GB1,
-case__1054: VCU118RocketSystem__GC0,
-reg__98: VCU118RocketSystem__GC0,
-PlusArgTimeout: RocketTile__GCB0,
-reg__500: FPU__GB2,
-case__1362: tracking_wrapper,
-reg__127: VCU118RocketSystem__GC0,
-logic__5447: RocketTile__GCB0,
-logic__5412: RocketTile__GCB0,
-reg__86: VCU118RocketSystem__GC0,
-logic__317: VCU118RocketSystem__GC0,
-logic__5545: RocketTile__GCB0,
-reg__981: VCU118RocketSystem__GC0,
-logic__4222: FPU__GB2,
-logic__1352: VCU118RocketSystem__GC0,
-logic__3760: FPU__GB1,
-case__373: DCache,
-logic__1088: VCU118RocketSystem__GC0,
-pps_core: APBGpsBlock__GCB0,
-case__295: RocketTile__GCB0,
-logic__1784: DCache,
-keep__16: APBGpsBlock__GCB0,
-logic__6822: VCU118RocketSystem__GC0,
-logic__703: VCU118RocketSystem__GC0,
-logic__1771: DCache,
-logic__4306: FPU__GB1,
-logic__8152: APBGpsBlock__GCB1,
-counter__10: APBGpsBlock__GCB1,
-reg__315: RocketTile__GCB0,
-keep__26: APBGpsBlock__GCB0,
-logic__5353: RocketTile__GCB0,
-logic__6389: VCU118RocketSystem__GC0,
-case__1164: APBGpsBlock__GCB1,
-logic__2323: DCache,
-logic__4635: RocketTile__GCB0,
-reg__1018: APBGpsBlock__GCB1,
-logic__5658: RocketTile__GCB0,
-muxpart__9: VCU118RocketSystem__GC0,
-logic__6852: VCU118RocketSystem__GC0,
-logic__6820: VCU118RocketSystem__GC0,
-muxpart__55: FPU__GB0,
-reg__637: RocketTile__GCB0,
-logic__2595: RocketTile__GCB0,
-logic__862: VCU118RocketSystem__GC0,
-logic__3594: FPU__GB1,
-logic__2109: DCache,
-dual_port_ram: APBGpsBlock__GCB1,
-datapath__272: RocketTile__GCB0,
-reg__436: FPU__GB2,
-logic__1648: DCache,
-logic__574: VCU118RocketSystem__GC0,
-case__606: FPU__GB1,
-logic__6062: RocketTile__GCB0,
-reg__216: VCU118RocketSystem__GC0,
-logic__2808: FPU__GB1,
-logic__7078: VCU118RocketSystem__GC0,
-reg__1303: tracking_wrapper,
-logic__1109: VCU118RocketSystem__GC0,
-reg__1040: APBGpsBlock__GCB1,
-case__1421: tracking_wrapper,
-case__610: FPU__GB1,
-datapath__190: VCU118RocketSystem__GC0,
-logic__4941: RocketTile__GCB0,
-case__604: FPU__GB1,
-logic__2894: FPU__GB1,
-reg__532: FPU__GB1,
-logic__6825: VCU118RocketSystem__GC0,
-logic__7955: APBGpsBlock__GCB1,
-datapath__652: tracking_wrapper,
-keep__29: APBGpsBlock__GCB0,
-logic__9207: APBGpsBlock__GCB0,
-logic__3243: FPU__GB2,
-datapath__505: VCU118RocketSystem__GC0,
-logic__2289: DCache,
-logic__6619: VCU118RocketSystem__GC0,
-reg__564: FPU__GB1,
-logic__7373: VCU118RocketSystem__GC0,
-logic__6109: TilePRCIDomain__GC0,
-logic__4347: FPU__GB1,
-case__514: FPU__GB1,
-logic__4532: RocketTile__GCB0,
-datapath__578: APBGpsBlock__GCB1,
-logic__4887: RocketTile__GCB0,
-logic__6056: RocketTile__GCB0,
-keep__27: APBGpsBlock__GCB0,
-datapath__413: RocketTile__GCB0,
-case__1011: VCU118RocketSystem__GC0,
-reg__999: APBGpsBlock__GCB1, tracking_wrapper,
-logic__2809: FPU__GB1,
-logic__3571: FPU__GB1,
-case__1005: VCU118RocketSystem__GC0,
-reg__82: VCU118RocketSystem__GC0,
-logic__3014: FPU__GB2, FPU__GB1,
-logic__1535: DCache,
-logic__9218: APBGpsBlock__GCB0,
-logic__4308: FPU__GB1,
-logic__6845: VCU118RocketSystem__GC0,
-logic__2099: DCache,
-case__321: DCache,
-logic__9205: APBGpsBlock__GCB0,
-logic__7431: VCU118RocketSystem__GC0,
-datapath__402: RocketTile__GCB0,
-muxpart__206: APBGpsBlock__GCB0,
-logic__7201: VCU118RocketSystem__GC0,
-datapath__641: tracking_wrapper,
-case__379: RocketTile__GCB0,
-logic__5061: RocketTile__GCB0,
-logic__707: VCU118RocketSystem__GC0,
-reg__593: RocketTile__GCB0,
-datapath__432: RocketTile__GCB0,
-case__419: RocketTile__GCB0,
-logic__5723: RocketTile__GCB0,
-reg__730: RocketTile__GCB0,
-logic__8630: tracking_wrapper,
-logic__8732: tracking_wrapper,
-datapath__612: APBGpsBlock__GCB1,
-logic__4226: FPU__GB2,
-logic__6374: VCU118RocketSystem__GC0,
-reg__1159: tracking_wrapper,
-logic__4076: FPU__GB2,
-logic__4543: RocketTile__GCB0,
-logic__2168: DCache,
-logic__1162: VCU118RocketSystem__GC0,
-reg__1143: tracking_wrapper,
-logic__2608: RocketTile__GCB0,
-logic__6634: VCU118RocketSystem__GC0,
-logic__4990: RocketTile__GCB0,
-logic__2964: FPU__GB1,
-logic__8194: APBGpsBlock__GCB1,
-logic__2880: FPU__GB1,
-reg__1399: APBGpsBlock__GCB0,
-case__489: FPU__GB2,
-reg__1459: genesys2_rocket_top__GC0,
-logic__6707: VCU118RocketSystem__GC0,
-logic__6267: VCU118RocketSystem__GC0,
-logic__5694: RocketTile__GCB0,
-ram_2x124: VCU118RocketSystem__GC0,
-logic__3766: FPU__GB1,
-case__775: RocketTile__GCB0,
-datapath__67: VCU118RocketSystem__GC0,
-reg__1055: APBGpsBlock__GCB1,
-RoundAnyRawFNToRecFN_4: FPU__GB2, FPU__GB1,
-logic__4623: RocketTile__GCB0,
-case__117: VCU118RocketSystem__GC0,
-trck_top: tracking_wrapper,
-logic__4353: FPU__GB1,
-reg__737: RocketTile__GCB0,
-reg__1301: tracking_wrapper,
-muxpart__15: RocketTile__GCB0,
-logic__7712: APBGpsBlock__GCB1,
-datapath__575: APBGpsBlock__GCB1,
-logic__1430: RocketTile__GCB0,
-logic__4789: RocketTile__GCB0,
-logic__767: VCU118RocketSystem__GC0,
-case__1126: APBGpsBlock__GCB1,
-datapath__73: VCU118RocketSystem__GC0,
-logic__7321: VCU118RocketSystem__GC0,
-logic__5237: RocketTile__GCB0,
-logic__3336: FPU__GB2,
-logic__6618: VCU118RocketSystem__GC0,
-logic__2160: DCache,
-logic__4289: FPU__GB2,
-logic__7788: APBGpsBlock__GCB1,
-muxpart__64: FPU__GB0,
-logic__3535: FPU__GB1,
-reg__396: FPU__GB0,
-datapath__47: VCU118RocketSystem__GC0,
-logic__9139: APBGpsBlock__GCB0,
-reg__899: VCU118RocketSystem__GC0,
-case__71: VCU118RocketSystem__GC0,
-case__603: FPU__GB1,
-logic__6158: VCU118RocketSystem__GC0,
-logic__9109: APBGpsBlock__GCB0,
-logic__7169: VCU118RocketSystem__GC0,
-logic__2936: FPU__GB1,
-muxpart__108: RocketTile__GCB0,
-double_ff_syn: APBGpsBlock__GCB1, tracking_wrapper,
-logic__4551: RocketTile__GCB0,
-logic__8762: tracking_wrapper,
-case__1015: VCU118RocketSystem__GC0,
-logic__6319: VCU118RocketSystem__GC0,
-logic__5358: RocketTile__GCB0,
-case__1425: tracking_wrapper,
-case__1105: APBGpsBlock__GCB1,
-logic__2943: FPU__GB1,
-reg__841: VCU118RocketSystem__GC0,
-datapath__7: VCU118RocketSystem__GC0,
-datapath__337: FPU__GB1,
-case__1483: tracking_wrapper,
-logic__262: VCU118RocketSystem__GC0,
-logic__14: genesys2_rocket_top__GC0,
-logic__3118: FPU__GB2,
-logic__5539: RocketTile__GCB0,
-datapath__720: APBGpsBlock__GCB0,
-logic__9290: APBGpsBlock__GCB1, APBGpsBlock__GCB0,
-case__278: VCU118RocketSystem__GC0,
-datapath__700: APBGpsBlock__GCB0,
-logic__3765: FPU__GB1,
-case__607: FPU__GB1,
-logic__4134: FPU__GB2,
-case__1227: APBGpsBlock__GCB1,
-logic__3055: FPU__GB2, FPU__GB1,
-reg__398: FPU__GB0,
-logic__7637: VCU118RocketSystem__GC0,
-logic__949: VCU118RocketSystem__GC0,
-reg__893: VCU118RocketSystem__GC0,
-logic__602: VCU118RocketSystem__GC0,
-case__31: VCU118RocketSystem__GC0,
-logic__6705: VCU118RocketSystem__GC0,
-logic__6336: VCU118RocketSystem__GC0,
-case__1099: APBGpsBlock__GCB1,
-logic__258: VCU118RocketSystem__GC0,
-logic__5420: RocketTile__GCB0,
-logic__4866: RocketTile__GCB0,
-case__1611: APBGpsBlock__GCB0,
-reg__798: VCU118RocketSystem__GC0,
-case__140: VCU118RocketSystem__GC0,
-reg__1283: tracking_wrapper,
-logic__6741: VCU118RocketSystem__GC0,
-logic__3803: FPU__GB1,
-logic__6457: VCU118RocketSystem__GC0,
-case__280: VCU118RocketSystem__GC0,
-logic__90: genesys2_rocket_top__GC0,
-datapath__8: VCU118RocketSystem__GC0,
-case__1416: tracking_wrapper,
-datapath__426: RocketTile__GCB0,
-logic__7406: VCU118RocketSystem__GC0,
-reg__933: VCU118RocketSystem__GC0,
-logic__6651: VCU118RocketSystem__GC0,
-logic__2970: FPU__GB2, FPU__GB1,
-muxpart__308: APBGpsBlock__GCB0,
-reg__988: VCU118RocketSystem__GC0,
-ram__5: VCU118RocketSystem__GC0,
-logic__4684: RocketTile__GCB0,
-reg__213: VCU118RocketSystem__GC0,
-reg__1091: APBGpsBlock__GCB1,
-sync: tracking_wrapper,
-logic__2859: FPU__GB1,
-reg__534: FPU__GB1,
-logic__3673: FPU__GB1,
-logic__3091: FPU__GB2,
-FPUFMAPipe_l3_f32: FPU__GB1,
-case__1228: APBGpsBlock__GCB1,
-case__1226: APBGpsBlock__GCB1,
-logic__4836: RocketTile__GCB0,
-logic__8278: tracking_wrapper,
-reg__1386: APBGpsBlock__GCB0,
-reg__372: FPU__GB0,
-logic__1463: RocketTile__GCB0,
-logic__4420: FPU__GB1,
-logic__2681: RocketTile__GCB0,
-logic__6854: VCU118RocketSystem__GC0,
-logic__6840: VCU118RocketSystem__GC0,
-reg__1127: APBGpsBlock__GCB0,
-datapath__473: VCU118RocketSystem__GC0,
-reg__920: VCU118RocketSystem__GC0,
-logic__9354: TLToAPB,
-datapath__97: VCU118RocketSystem__GC0,
-dsp48e1__12: APBGpsBlock__GCB1,
-logic__109: VCU118RocketSystem__GC0,
-logic__2395: RocketTile__GCB0,
-logic__3388: FPU__GB2,
-case__481: FPU__GB2,
-logic__3088: FPU__GB2,
-reg__1056: APBGpsBlock__GCB1,
-logic__4528: RocketTile__GCB0,
-logic__6033: RocketTile__GCB0,
-logic__3209: FPU__GB2,
-logic__6113: VCU118RocketSystem__GC0,
-reg__66: VCU118RocketSystem__GC0,
-logic__4660: RocketTile__GCB0,
-RocketTile__GCB0: RocketTile__GCB0,
-logic__6654: VCU118RocketSystem__GC0,
-counter__30: APBGpsBlock__GCB0,
-logic__8332: tracking_wrapper,
-logic__7022: VCU118RocketSystem__GC0,
-logic__1286: VCU118RocketSystem__GC0,
-muxpart__193: APBGpsBlock__GCB1,
-reg__1314: tracking_wrapper,
-logic__9176: APBGpsBlock__GCB0,
-logic__3747: FPU__GB1,
-logic__2718: FPU__GB1,
-logic__6044: RocketTile__GCB0,
-logic__6977: VCU118RocketSystem__GC0,
-reg__522: FPU__GB2,
-case__567: FPU__GB2,
-logic__8777: tracking_wrapper,
-logic__2391: RocketTile__GCB0,
-case__303: RocketTile__GCB0,
-TLDebugModuleInner: VCU118RocketSystem__GC0,
-logic__8943: APBGpsBlock__GCB0,
-logic__3176: FPU__GB2,
-case__1423: tracking_wrapper,
-logic__2461: RocketTile__GCB0,
-logic__9144: APBGpsBlock__GCB0,
-logic__2213: DCache,
-reg__1404: APBGpsBlock__GCB0,
-logic__6821: VCU118RocketSystem__GC0,
-case__731: RocketTile__GCB0,
-reg__559: FPU__GB1,
-logic__3385: FPU__GB2,
-logic__3729: FPU__GB1,
-logic__2887: FPU__GB1,
-logic__7021: VCU118RocketSystem__GC0,
-datapath__108: VCU118RocketSystem__GC0,
-logic__5325: RocketTile__GCB0,
-datapath__408: RocketTile__GCB0,
-logic__4760: RocketTile__GCB0,
-logic__1722: DCache,
-logic__3695: FPU__GB1,
-reg__973: VCU118RocketSystem__GC0,
-keep__13: APBGpsBlock__GCB0,
-logic__5280: RocketTile__GCB0,
-logic__3418: FPU__GB2,
-twiddle_ram: APBGpsBlock__GCB1,
-logic__4912: RocketTile__GCB0,
-case__1610: APBGpsBlock__GCB0,
-logic__548: VCU118RocketSystem__GC0,
-logic__4573: RocketTile__GCB0,
-datapath__288: FPU__GB1,
-case__854: VCU118RocketSystem__GC0,
-logic__4727: RocketTile__GCB0,
-case__1601: APBGpsBlock__GCB0,
-reg__36: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__1050: VCU118RocketSystem__GC0,
-logic__1295: VCU118RocketSystem__GC0,
-logic__2863: FPU__GB1,
-logic__6789: VCU118RocketSystem__GC0,
-datapath__448: RocketTile__GCB0,
-logic__5281: RocketTile__GCB0,
-reg__519: FPU__GB2,
-logic__3764: FPU__GB1,
-logic__2977: FPU__GB2, FPU__GB1,
-logic__1699: DCache,
-logic__3868: FPU__GB1,
-logic__9367: TLToAPB,
-keep__19: APBGpsBlock__GCB0,
-reg__993: VCU118RocketSystem__GC0,
-case__523: FPU__GB1,
-datapath__212: VCU118RocketSystem__GC0,
-logic__8191: APBGpsBlock__GCB1,
-logic__8849: tracking_wrapper,
-case__45: VCU118RocketSystem__GC0,
-logic__2217: DCache,
-case__676: RocketTile__GCB0,
-reg__699: RocketTile__GCB0,
-logic__8050: APBGpsBlock__GCB1,
-logic__4788: RocketTile__GCB0,
-datapath__232: VCU118RocketSystem__GC0,
-logic__8915: APBGpsBlock__GCB0,
-logic__4586: RocketTile__GCB0,
-logic__2855: FPU__GB1,
-logic__2723: FPU__GB1,
-reg__850: VCU118RocketSystem__GC0,
-reg__223: VCU118RocketSystem__GC0,
-logic__4764: RocketTile__GCB0,
-reg__412: FPU__GB1,
-ram_2x78: VCU118RocketSystem__GC0,
-datapath__55: VCU118RocketSystem__GC0,
-muxpart__216: tracking_wrapper,
-logic__9288: APBGpsBlock__GCB0,
-case__1028: VCU118RocketSystem__GC0,
-datapath__187: VCU118RocketSystem__GC0,
-case__190: VCU118RocketSystem__GC0,
-case__762: RocketTile__GCB0,
-datapath__262: DCache,
-datapath__666: tracking_wrapper,
-logic__5439: RocketTile__GCB0,
-logic__7259: VCU118RocketSystem__GC0,
-logic__3460: FPU__GB2,
-logic__1782: DCache,
-case__179: VCU118RocketSystem__GC0,
-logic__254: VCU118RocketSystem__GC0,
-logic__905: VCU118RocketSystem__GC0,
-logic__7969: APBGpsBlock__GCB1,
-case__553: FPU__GB2,
-logic__6063: RocketTile__GCB0,
-reg__271: DCache,
-datapath__287: FPU__GB1,
-case__1233: APBGpsBlock__GCB1,
-reg__1383: APBGpsBlock__GCB0,
-reg__846: VCU118RocketSystem__GC0,
-case__1066: APBGpsBlock__GCB1,
-logic__8776: tracking_wrapper,
-case__1430: tracking_wrapper,
-logic__1190: VCU118RocketSystem__GC0,
-logic__6814: VCU118RocketSystem__GC0,
-datapath__430: RocketTile__GCB0,
-datapath__716: APBGpsBlock__GCB0,
-logic__3387: FPU__GB2,
-logic__3492: FPU__GB2,
-reg__1157: tracking_wrapper,
-logic__4976: RocketTile__GCB0,
-case__1679: TLToAPB,
-logic__2730: FPU__GB1,
-logic__7653: VCU118RocketSystem__GC0,
-logic__6828: VCU118RocketSystem__GC0,
-logic__6411: VCU118RocketSystem__GC0,
-reg__1230: tracking_wrapper,
-logic__3782: FPU__GB1,
-reg__1112: APBGpsBlock__GCB1,
-logic__4765: RocketTile__GCB0,
-logic__4485: FPU__GB1,
-TLFragmenter_FPGAGPS: VCU118RocketSystem__GC0,
-logic__7956: APBGpsBlock__GCB1,
-logic__4117: FPU__GB2,
-logic__4522: RocketTile__GCB0,
-logic__1192: VCU118RocketSystem__GC0,
-reg__184: VCU118RocketSystem__GC0,
-reg__568: FPU__GB1,
-logic__4171: FPU__GB2,
-logic__7636: VCU118RocketSystem__GC0,
-reg__1405: APBGpsBlock__GCB0,
-reg__691: RocketTile__GCB0,
-case__559: FPU__GB2,
-logic__1538: DCache,
-counter__33: APBGpsBlock__GCB0,
-datapath__52: VCU118RocketSystem__GC0,
-reg__1203: tracking_wrapper,
-case__1232: APBGpsBlock__GCB1,
-logic__3563: FPU__GB1,
-case__154: VCU118RocketSystem__GC0,
-case__75: VCU118RocketSystem__GC0,
-logic__5894: RocketTile__GCB0,
-reg__1217: tracking_wrapper,
-logic__1012: VCU118RocketSystem__GC0,
-logic__1234: VCU118RocketSystem__GC0,
-case__32: VCU118RocketSystem__GC0,
-logic__4079: FPU__GB2,
-logic__3641: FPU__GB1,
-logic__7225: VCU118RocketSystem__GC0,
-case__469: FPU__GB2,
-logic__4913: RocketTile__GCB0,
-logic__476: VCU118RocketSystem__GC0,
-logic__6583: VCU118RocketSystem__GC0,
-datapath__76: VCU118RocketSystem__GC0,
-case__653: RocketTile__GCB0,
-datapath__535: APBGpsBlock__GCB1,
-logic__9268: APBGpsBlock__GCB0,
-logic__5434: RocketTile__GCB0,
-logic__9384: genesys2_rocket_top__GC0,
-muxpart__18: FPU__GB0,
-datapath__325: FPU__GB2,
-logic__4034: FPU__GB2,
-case__770: RocketTile__GCB0,
-reg__514: FPU__GB2,
-case__430: RocketTile__GCB0,
-logic__7432: VCU118RocketSystem__GC0,
-muxpart__94: RocketTile__GCB0,
-logic__2346: RocketTile__GCB0,
-case__287: VCU118RocketSystem__GC0,
-datapath__530: APBGpsBlock__GCB1,
-logic__4137: FPU__GB2,
-case__757: RocketTile__GCB0,
-logic__3414: FPU__GB2,
-case__214: VCU118RocketSystem__GC0,
-reg__1321: tracking_wrapper,
-case__1623: APBGpsBlock__GCB0,
-muxpart__53: FPU__GB0,
-datapath__147: VCU118RocketSystem__GC0,
-datapath__215: VCU118RocketSystem__GC0,
-logic__104: VCU118RocketSystem__GC0,
-reg__1174: tracking_wrapper,
-datapath__203: VCU118RocketSystem__GC0,
-datapath__708: APBGpsBlock__GCB0,
-case__172: VCU118RocketSystem__GC0,
-logic__6249: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_sbus_from_rockettile: VCU118RocketSystem__GC0,
-case__1200: APBGpsBlock__GCB1,
-muxpart__226: tracking_wrapper,
-logic__7036: VCU118RocketSystem__GC0,
-case__794: VCU118RocketSystem__GC0,
-logic__4486: FPU__GB1,
-case__1678: APBGpsBlock__GCB1,
-reg__889: VCU118RocketSystem__GC0,
-IntSyncCrossingSource_n1x1_Registered: VCU118RocketSystem__GC0,
-reg__958: VCU118RocketSystem__GC0,
-reg__1434: APBGpsBlock__GCB0,
-datapath__496: VCU118RocketSystem__GC0,
-case__211: VCU118RocketSystem__GC0,
-logic__2136: DCache,
-datapath__600: APBGpsBlock__GCB1,
-muxpart__39: FPU__GB0,
-counter__21: tracking_wrapper,
-logic__8706: tracking_wrapper,
-logic__2976: FPU__GB2, FPU__GB1,
-reg__1396: APBGpsBlock__GCB0,
-logic__1525: DCache,
-case__1691: VCU118RocketSystem__GC0,
-reg__218: VCU118RocketSystem__GC0,
-datapath__25: VCU118RocketSystem__GC0,
-logic__6159: VCU118RocketSystem__GC0,
-logic__8972: APBGpsBlock__GCB0,
-logic__3462: FPU__GB2,
-logic__1376: VCU118RocketSystem__GC0,
-reg__1036: APBGpsBlock__GCB1,
-reg__1409: APBGpsBlock__GCB0,
-reg__374: FPU__GB0,
-logic__2654: RocketTile__GCB0,
-datapath__364: FPU__GB2,
-logic__3187: FPU__GB2,
-case__285: VCU118RocketSystem__GC0,
-datapath__546: APBGpsBlock__GCB1,
-case__376: RocketTile__GCB0,
-logic__7009: VCU118RocketSystem__GC0,
-reg__950: VCU118RocketSystem__GC0,
-logic__301: VCU118RocketSystem__GC0,
-case__857: VCU118RocketSystem__GC0,
-logic__4793: RocketTile__GCB0,
-logic__7554: VCU118RocketSystem__GC0,
-reg__1041: APBGpsBlock__GCB1,
-logic__3940: FPU__GB2, FPU__GB1,
-logic__8272: tracking_wrapper,
-case__518: FPU__GB1,
-logic__9360: TLToAPB,
-logic__4342: FPU__GB1,
-logic__3678: FPU__GB1,
-reg__1426: APBGpsBlock__GCB0,
-reg__1175: tracking_wrapper,
-logic__1629: DCache,
-case__885: VCU118RocketSystem__GC0,
-reg__879: VCU118RocketSystem__GC0,
-logic__3761: FPU__GB1,
-logic__1743: DCache,
-logic__8313: tracking_wrapper,
-logic__7675: VCU118RocketSystem__GC0,
-logic__6520: VCU118RocketSystem__GC0,
-reg__813: VCU118RocketSystem__GC0,
-datapath__285: RocketTile__GCB0,
-logic__663: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__296: FPU__GB1,
-logic__3656: FPU__GB1,
-datapath__126: VCU118RocketSystem__GC0,
-datapath__80: VCU118RocketSystem__GC0,
-case__434: RocketTile__GCB0,
-logic__1191: VCU118RocketSystem__GC0,
-logic__7948: APBGpsBlock__GCB1,
-reg__570: FPU__GB1,
-datapath__732: APBGpsBlock__GCB0,
-logic__2563: RocketTile__GCB0,
-SystemBus: VCU118RocketSystem__GC0,
-case__577: FPU__GB1,
-reg__1038: APBGpsBlock__GCB1,
-nav_solve_timer: tracking_wrapper,
-logic__6982: VCU118RocketSystem__GC0,
-reg__1449: TLToAPB,
-logic__1296: VCU118RocketSystem__GC0,
-case__1069: APBGpsBlock__GCB1,
-logic__2614: RocketTile__GCB0,
-logic__8858: tracking_wrapper,
-logic__6479: VCU118RocketSystem__GC0,
-case__570: FPU__GB2,
-logic__974: VCU118RocketSystem__GC0,
-logic__3754: FPU__GB1,
-addsub__5: tracking_wrapper,
-case__746: RocketTile__GCB0,
-logic__5056: RocketTile__GCB0,
-logic__1508: RocketTile__GCB0,
-datapath__714: APBGpsBlock__GCB0,
-logic__7584: VCU118RocketSystem__GC0,
-datapath__468: VCU118RocketSystem__GC0,
-logic__337: VCU118RocketSystem__GC0,
-case__890: VCU118RocketSystem__GC0,
-reg__882: VCU118RocketSystem__GC0,
-logic__492: VCU118RocketSystem__GC0,
-logic__4236: FPU__GB2,
-logic__5518: RocketTile__GCB0,
-logic__1231: VCU118RocketSystem__GC0,
-reg__511: FPU__GB2,
-case__301: RocketTile__GCB0,
-logic__9353: TLToAPB,
-reg__1260: tracking_wrapper,
-case__1547: APBGpsBlock__GCB0,
-reg__121: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__77: VCU118RocketSystem__GC0,
-case__1031: VCU118RocketSystem__GC0,
-reg__360: RocketTile__GCB0,
-case__764: RocketTile__GCB0,
-logic__2241: DCache,
-reg__1414: APBGpsBlock__GCB0,
-logic__5402: RocketTile__GCB0,
-case__1539: APBGpsBlock__GCB0,
-logic__4348: FPU__GB1,
-logic__3473: FPU__GB2,
-logic__5891: RocketTile__GCB0,
-logic__9102: APBGpsBlock__GCB0,
-CLINTClockSinkDomain: VCU118RocketSystem__GC0,
-case__1280: APBGpsBlock__GCB1,
-datapath__564: APBGpsBlock__GCB1,
-reg__644: RocketTile__GCB0,
-logic__5350: RocketTile__GCB0,
-case__199: VCU118RocketSystem__GC0,
-case__209: VCU118RocketSystem__GC0,
-logic__1878: RocketTile__GCB0, DCache,
-case__1045: VCU118RocketSystem__GC0,
-logic__1157: VCU118RocketSystem__GC0,
-reg__1206: tracking_wrapper,
-case__649: RocketTile__GCB0,
-datapath__148: VCU118RocketSystem__GC0,
-reg__670: RocketTile__GCB0,
-logic__9182: APBGpsBlock__GCB0,
-logic__5675: RocketTile__GCB0,
-logic__4972: RocketTile__GCB0,
-case__657: RocketTile__GCB0,
-logic__4476: FPU__GB1,
-datapath__110: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__383: FPU__GB2,
-logic__779: VCU118RocketSystem__GC0,
-reg__1452: TLToAPB,
-datapath__703: APBGpsBlock__GCB0,
-logic__6318: VCU118RocketSystem__GC0,
-logic__2682: RocketTile__GCB0,
-reg__652: RocketTile__GCB0,
-logic__8084: APBGpsBlock__GCB1,
-logic__4925: RocketTile__GCB0,
-logic__2296: DCache,
-reg__945: VCU118RocketSystem__GC0,
-logic__916: VCU118RocketSystem__GC0,
-logic__7144: VCU118RocketSystem__GC0,
-logic__383: VCU118RocketSystem__GC0,
-logic__5224: RocketTile__GCB0,
-logic__7241: VCU118RocketSystem__GC0,
-logic__2193: DCache,
-ClockGroupAggregator_pbus: VCU118RocketSystem__GC0,
-logic__5890: RocketTile__GCB0,
-reg__1085: APBGpsBlock__GCB1,
-case__262: VCU118RocketSystem__GC0,
-datapath__527: APBGpsBlock__GCB1,
-reg__1446: APBGpsBlock__GCB0,
-logic__2023: DCache,
-reg__205: VCU118RocketSystem__GC0,
-logic__1159: VCU118RocketSystem__GC0,
-case__142: VCU118RocketSystem__GC0,
-case__974: VCU118RocketSystem__GC0,
-datapath__151: VCU118RocketSystem__GC0,
-case__121: VCU118RocketSystem__GC0,
-logic__9164: APBGpsBlock__GCB0,
-reg__1095: APBGpsBlock__GCB1,
-logic__557: VCU118RocketSystem__GC0,
-reg__323: RocketTile__GCB0,
-logic__9169: APBGpsBlock__GCB0,
-logic__1927: DCache,
-logic__6504: VCU118RocketSystem__GC0,
-logic__5893: RocketTile__GCB0,
-reg__946: VCU118RocketSystem__GC0,
-reg__885: VCU118RocketSystem__GC0,
-logic__1067: VCU118RocketSystem__GC0,
-muxpart__88: FPU__GB2,
-logic__345: VCU118RocketSystem__GC0,
-reg__1168: tracking_wrapper,
-logic__3698: FPU__GB1,
-datapath__58: VCU118RocketSystem__GC0,
-logic__137: VCU118RocketSystem__GC0,
-logic__5293: RocketTile__GCB0,
-datapath__301: FPU__GB2, FPU__GB1,
-datapath__669: tracking_wrapper,
-logic__1209: VCU118RocketSystem__GC0,
-case__159: VCU118RocketSystem__GC0,
-reg__151: VCU118RocketSystem__GC0,
-datapath__521: VCU118RocketSystem__GC0,
-logic__4905: RocketTile__GCB0,
-logic__3138: FPU__GB2,
-logic__7220: VCU118RocketSystem__GC0,
-reg__574: FPU__GB1,
-logic__7480: VCU118RocketSystem__GC0,
-case__1026: VCU118RocketSystem__GC0,
-case__498: FPU__GB2,
-logic__5305: RocketTile__GCB0,
-logic__2713: FPU__GB1,
-datapath__332: FPU__GB2,
-datapath__258: DCache,
-logic__3134: FPU__GB2,
-muxpart__109: RocketTile__GCB0,
-logic__7708: VCU118RocketSystem__GC0,
-case__761: RocketTile__GCB0,
-logic__4014: FPU__GB1,
-case__405: RocketTile__GCB0,
-reg__304: RocketTile__GCB0,
-AsyncQueueSource_TLBundleA_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-keep__36: APBGpsBlock__GCB0,
-case__1492: tracking_wrapper,
-logic__2568: RocketTile__GCB0,
-datapath__14: VCU118RocketSystem__GC0,
-logic__6776: VCU118RocketSystem__GC0,
-reg__390: FPU__GB0,
-logic__3763: FPU__GB1,
-logic__7736: APBGpsBlock__GCB1,
-logic__4837: RocketTile__GCB0,
-logic__6702: VCU118RocketSystem__GC0,
-case__831: VCU118RocketSystem__GC0,
-reg__1090: APBGpsBlock__GCB1,
-reg__1373: APBGpsBlock__GCB0,
-logic__954: VCU118RocketSystem__GC0,
-logic__4170: FPU__GB2,
-case__784: RocketTile__GCB0,
-case__1345: tracking_wrapper,
-muxpart__104: RocketTile__GCB0,
-logic__8708: tracking_wrapper,
-logic__1066: VCU118RocketSystem__GC0,
-logic__1336: VCU118RocketSystem__GC0,
-logic__6017: RocketTile__GCB0,
-logic__3808: FPU__GB1,
-case__1391: tracking_wrapper,
-case__1556: APBGpsBlock__GCB0,
-reg__926: VCU118RocketSystem__GC0,
-logic__6035: RocketTile__GCB0,
-logic__6184: VCU118RocketSystem__GC0,
-case__600: FPU__GB1,
-logic__2333: DCache,
-reg__970: VCU118RocketSystem__GC0,
-datapath__246: DCache,
-case__590: FPU__GB1,
-reg__1008: APBGpsBlock__GCB1,
-case__1396: tracking_wrapper,
-case__386: RocketTile__GCB0,
-logic__1357: VCU118RocketSystem__GC0,
-datapath__208: VCU118RocketSystem__GC0,
-reg__1411: APBGpsBlock__GCB0,
-logic__8075: APBGpsBlock__GCB1,
-logic__7936: APBGpsBlock__GCB1,
-reg__904: VCU118RocketSystem__GC0,
-datapath__664: tracking_wrapper,
-logic__5065: RocketTile__GCB0,
-logic__4382: FPU__GB1,
-reg__507: FPU__GB2,
-case__1631: APBGpsBlock__GCB0,
-logic__6761: VCU118RocketSystem__GC0,
-case__1165: APBGpsBlock__GCB1,
-reg__1272: tracking_wrapper,
-Repeater_TLBundleA_a17d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__1756: DCache,
-double_ff_syn__parameterized0: tracking_wrapper,
-logic__8286: tracking_wrapper,
-case__674: RocketTile__GCB0,
-reg__621: RocketTile__GCB0,
-reg__563: FPU__GB1,
-case__173: VCU118RocketSystem__GC0,
-logic__8603: tracking_wrapper,
-muxpart__16: RocketTile__GCB0,
-case__722: RocketTile__GCB0,
-reg__959: VCU118RocketSystem__GC0,
-muxpart__91: FPU__GB1,
-logic__592: VCU118RocketSystem__GC0,
-logic__8778: tracking_wrapper,
-reg__1196: tracking_wrapper,
-logic__8166: APBGpsBlock__GCB1,
-reg__1289: tracking_wrapper,
-case__1022: VCU118RocketSystem__GC0,
-reg__1372: APBGpsBlock__GCB0,
-case__367: DCache,
-logic__6069: RocketTile__GCB0,
-TLXbar_sbus_i2_o1_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__281: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4508: FPU__GB1,
-logic__2046: DCache,
-logic__7872: APBGpsBlock__GCB1,
-addsub__3: tracking_wrapper,
-logic__5438: RocketTile__GCB0,
-case__133: VCU118RocketSystem__GC0,
-muxpart__300: APBGpsBlock__GCB0,
-case__735: RocketTile__GCB0,
-reg__1209: tracking_wrapper,
-MulAddRecFNToRaw_preMul_1: FPU__GB1,
-logic__3167: FPU__GB2,
-reg__1133: tracking_wrapper,
-logic__644: VCU118RocketSystem__GC0,
-logic__6320: VCU118RocketSystem__GC0,
-logic__9277: APBGpsBlock__GCB0,
-reg__941: VCU118RocketSystem__GC0,
-case__243: VCU118RocketSystem__GC0,
-reg__890: VCU118RocketSystem__GC0,
-datapath__485: VCU118RocketSystem__GC0,
-logic__4907: RocketTile__GCB0,
-logic__8818: tracking_wrapper,
-logic__532: VCU118RocketSystem__GC0,
-case__415: RocketTile__GCB0,
-datapath__319: FPU__GB2,
-logic__4763: RocketTile__GCB0,
-logic__8276: tracking_wrapper,
-logic__8759: tracking_wrapper,
-muxpart__223: tracking_wrapper,
-datapath__116: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__1370: VCU118RocketSystem__GC0,
-ram_2x120: VCU118RocketSystem__GC0,
-logic__3461: FPU__GB2,
-logic__5336: RocketTile__GCB0,
-logic__2856: FPU__GB1,
-logic__5289: RocketTile__GCB0,
-reg__160: VCU118RocketSystem__GC0,
-logic__8532: tracking_wrapper,
-case__1038: VCU118RocketSystem__GC0,
-reg__491: FPU__GB1,
-reg__1187: tracking_wrapper,
-case__1343: tracking_wrapper,
-logic__2383: RocketTile__GCB0,
-muxpart__115: VCU118RocketSystem__GC0,
-logic__1030: VCU118RocketSystem__GC0,
-logic__2343: RocketTile__GCB0,
-case__702: RocketTile__GCB0,
-logic__498: VCU118RocketSystem__GC0,
-reg__539: FPU__GB1,
-reg__952: VCU118RocketSystem__GC0,
-logic__6830: VCU118RocketSystem__GC0,
-muxpart__103: RocketTile__GCB0,
-case__898: VCU118RocketSystem__GC0,
-TLDebugModuleOuterAsync: VCU118RocketSystem__GC0,
-logic__8176: APBGpsBlock__GCB1,
-logic__7687: VCU118RocketSystem__GC0,
-logic__6760: VCU118RocketSystem__GC0,
-logic__6322: VCU118RocketSystem__GC0,
-case__332: DCache,
-logic__8837: tracking_wrapper,
-logic__7576: VCU118RocketSystem__GC0,
-logic__2680: RocketTile__GCB0,
-reg__425: FPU__GB1,
-case__892: VCU118RocketSystem__GC0,
-case__258: VCU118RocketSystem__GC0,
-case__1314: APBGpsBlock__GCB1,
-logic__4744: RocketTile__GCB0,
-logic__7561: VCU118RocketSystem__GC0,
-datapath__711: APBGpsBlock__GCB0,
-logic__3933: FPU__GB2, FPU__GB1,
-logic__3725: FPU__GB1,
-logic__2531: RocketTile__GCB0,
-logic__7438: VCU118RocketSystem__GC0,
-logic__3806: FPU__GB1,
-logic__1003: VCU118RocketSystem__GC0,
-ram_2x123: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__8151: APBGpsBlock__GCB1,
-logic__5326: RocketTile__GCB0,
-reg__953: VCU118RocketSystem__GC0,
-logic__8354: tracking_wrapper,
-logic__8731: tracking_wrapper,
-logic__8443: tracking_wrapper,
-cordic_angle_lut: tracking_wrapper,
-reg__256: DCache,
-logic__6836: VCU118RocketSystem__GC0,
-logic__288: VCU118RocketSystem__GC0,
-logic__1305: VCU118RocketSystem__GC0,
-logic__1857: RocketTile__GCB0, DCache,
-logic__3628: FPU__GB1,
-logic__7190: VCU118RocketSystem__GC0,
-logic__6796: VCU118RocketSystem__GC0,
-datapath__263: RocketTile__GCB0,
-logic__3357: FPU__GB2,
-logic__9295: APBGpsBlock__GCB0,
-logic__7691: VCU118RocketSystem__GC0,
-logic__1290: VCU118RocketSystem__GC0,
-reg__1035: APBGpsBlock__GCB1,
-reg__296: RocketTile__GCB0,
-logic__5337: RocketTile__GCB0,
-datapath__70: VCU118RocketSystem__GC0,
-logic__7276: VCU118RocketSystem__GC0,
-logic__6328: VCU118RocketSystem__GC0,
-logic__4988: RocketTile__GCB0,
-datapath__330: FPU__GB2,
-case__333: DCache,
-case__1059: APBGpsBlock__GCB1,
-reg__1132: tracking_wrapper,
-case__475: FPU__GB2,
-datapath__493: VCU118RocketSystem__GC0,
-logic__1815: DCache,
-reg__1310: tracking_wrapper,
-logic__1568: DCache,
-logic__4787: RocketTile__GCB0,
-dsp48e1__34: tracking_wrapper,
-case__1665: APBGpsBlock__GCB0,
-logic__5086: RocketTile__GCB0,
-TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u: RocketTile__GCB0,
-logic__660: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__646: VCU118RocketSystem__GC0,
-case__1527: APBGpsBlock__GCB0,
-reg__399: FPU__GB0,
-datapath__81: VCU118RocketSystem__GC0,
-logic__9365: TLToAPB,
-case__40: VCU118RocketSystem__GC0,
-logic__5205: RocketTile__GCB0,
-datapath__135: VCU118RocketSystem__GC0,
-datapath__177: VCU118RocketSystem__GC0,
-datapath__142: VCU118RocketSystem__GC0,
-logic__8279: tracking_wrapper,
-reg__359: RocketTile__GCB0,
-reg__1046: APBGpsBlock__GCB1,
-BreakpointUnit: RocketTile__GCB0,
-case__1395: tracking_wrapper,
-case__1196: APBGpsBlock__GCB1,
-case__132: VCU118RocketSystem__GC0,
-case__1034: VCU118RocketSystem__GC0,
-case__1182: APBGpsBlock__GCB1,
-logic__1802: DCache,
-case__497: FPU__GB2,
-logic__9333: APBGpsBlock__GCB1,
-logic__6253: VCU118RocketSystem__GC0,
-logic__7055: VCU118RocketSystem__GC0,
-reg__720: RocketTile__GCB0,
-logic__5355: RocketTile__GCB0,
-datapath__320: FPU__GB2,
-case__91: VCU118RocketSystem__GC0,
-case__1413: tracking_wrapper,
-logic__6534: VCU118RocketSystem__GC0,
-logic__7663: VCU118RocketSystem__GC0,
-reg__1401: APBGpsBlock__GCB0,
-logic__3136: FPU__GB2,
-case__26: VCU118RocketSystem__GC0,
-case__821: VCU118RocketSystem__GC0,
-case__503: FPU__GB2,
-datapath__149: VCU118RocketSystem__GC0,
-logic__2223: DCache,
-logic__1350: VCU118RocketSystem__GC0,
-case__257: VCU118RocketSystem__GC0,
-datapath__728: APBGpsBlock__GCB0,
-logic__6849: VCU118RocketSystem__GC0,
-case__1490: tracking_wrapper,
-case__480: FPU__GB2,
-case__1450: tracking_wrapper,
-reg__1189: tracking_wrapper,
-datapath__128: VCU118RocketSystem__GC0,
-reg__543: FPU__GB1,
-logic__6310: VCU118RocketSystem__GC0,
-logic__1632: DCache,
-logic__9108: APBGpsBlock__GCB0,
-logic__9265: APBGpsBlock__GCB0,
-logic__6680: VCU118RocketSystem__GC0,
-reg__1261: tracking_wrapper,
-logic__4120: FPU__GB2,
-logic__6531: VCU118RocketSystem__GC0,
-logic__277: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__242: DCache,
-logic__8204: APBGpsBlock__GCB1,
-case__1363: tracking_wrapper,
-datapath__269: RocketTile__GCB0,
-logic__7418: VCU118RocketSystem__GC0,
-case__651: RocketTile__GCB0,
-logic__9188: APBGpsBlock__GCB0,
-logic__6559: VCU118RocketSystem__GC0,
-logic__718: VCU118RocketSystem__GC0,
-logic__1572: DCache,
-logic__331: VCU118RocketSystem__GC0,
-reg__319: RocketTile__GCB0,
-case__1473: tracking_wrapper,
-case__330: DCache,
-logic__6047: RocketTile__GCB0,
-logic__5323: RocketTile__GCB0,
-logic__1230: VCU118RocketSystem__GC0,
-reg__1385: APBGpsBlock__GCB0,
-case__195: VCU118RocketSystem__GC0,
-case__728: RocketTile__GCB0,
-logic__6757: VCU118RocketSystem__GC0,
-logic__7361: VCU118RocketSystem__GC0,
-logic__6614: VCU118RocketSystem__GC0,
-logic__1464: RocketTile__GCB0,
-datapath__165: VCU118RocketSystem__GC0,
-CSRFile: RocketTile__GCB0,
-reg__1393: APBGpsBlock__GCB0,
-reg__422: FPU__GB1,
-logic__1554: DCache,
-reg__1284: tracking_wrapper,
-case__509: FPU__GB1,
-logic__6782: VCU118RocketSystem__GC0,
-case__491: FPU__GB2,
-logic__2944: FPU__GB1,
-case__723: RocketTile__GCB0,
-logic__669: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7454: VCU118RocketSystem__GC0,
-PLICFanIn: VCU118RocketSystem__GC0,
-reg__842: VCU118RocketSystem__GC0,
-case__1689: TLToAPB,
-case__203: VCU118RocketSystem__GC0,
-reg__1010: APBGpsBlock__GCB1,
-logic__3036: FPU__GB2, FPU__GB1,
-datapath__557: APBGpsBlock__GCB1,
-logic__6428: VCU118RocketSystem__GC0,
-datapath__85: VCU118RocketSystem__GC0,
-logic__202: VCU118RocketSystem__GC0,
-logic__4900: RocketTile__GCB0,
-datapath__146: VCU118RocketSystem__GC0,
-datapath__626: tracking_wrapper,
-datapath__517: VCU118RocketSystem__GC0,
-case__1144: APBGpsBlock__GCB1,
-case__227: VCU118RocketSystem__GC0,
-reg__445: FPU__GB2,
-counter__35: APBGpsBlock__GCB0,
-reg__23: VCU118RocketSystem__GC0,
-logic__4022: FPU__GB2,
-logic__1641: DCache,
-logic__6152: VCU118RocketSystem__GC0,
-logic__4533: RocketTile__GCB0,
-logic__6402: VCU118RocketSystem__GC0,
-muxpart__51: FPU__GB0,
-logic__3205: FPU__GB2,
-datapath__309: FPU__GB2,
-reg__75: VCU118RocketSystem__GC0,
-datapath__556: APBGpsBlock__GCB1,
-reg__910: VCU118RocketSystem__GC0,
-case__597: FPU__GB1,
-logic__2129: DCache,
-IBuf: RocketTile__GCB0,
-datapath__260: DCache,
-datapath__449: RocketTile__GCB0,
-logic__5306: RocketTile__GCB0,
-logic__3561: FPU__GB1,
-logic__833: VCU118RocketSystem__GC0,
-case__395: RocketTile__GCB0,
-logic__8600: tracking_wrapper,
-reg__525: FPU__GB2,
-logic__2095: DCache,
-logic__3708: FPU__GB1,
-muxpart__117: VCU118RocketSystem__GC0,
-logic__6289: VCU118RocketSystem__GC0,
-logic__517: VCU118RocketSystem__GC0,
-logic__7615: VCU118RocketSystem__GC0,
-datapath__509: VCU118RocketSystem__GC0,
-logic__614: VCU118RocketSystem__GC0,
-datapath__6: VCU118RocketSystem__GC0,
-case__1096: APBGpsBlock__GCB1,
-logic__3487: FPU__GB2,
-divider__parameterized0: tracking_wrapper,
-logic__168: VCU118RocketSystem__GC0,
-logic__4956: RocketTile__GCB0,
-reg__1096: APBGpsBlock__GCB1,
-reg__974: VCU118RocketSystem__GC0,
-logic__546: VCU118RocketSystem__GC0,
-logic__3588: FPU__GB1,
-logic__5887: RocketTile__GCB0,
-case__402: RocketTile__GCB0,
-logic__9106: APBGpsBlock__GCB0,
-reg__124: VCU118RocketSystem__GC0,
-reg__228: VCU118RocketSystem__GC0,
-case__194: VCU118RocketSystem__GC0,
-RoundRawFNToRecFN: FPU__GB2, FPU__GB1,
-logic__6478: VCU118RocketSystem__GC0,
-case__268: VCU118RocketSystem__GC0,
-logic__642: VCU118RocketSystem__GC0,
-logic__4128: FPU__GB2,
-logic__3860: FPU__GB1,
-datapath__211: VCU118RocketSystem__GC0,
-reg__643: RocketTile__GCB0,
-dsp48e1__29: tracking_wrapper,
-counter__38: VCU118RocketSystem__GC0,
-logic__312: VCU118RocketSystem__GC0,
-case__1422: tracking_wrapper,
-logic__7973: APBGpsBlock__GCB1,
-keep__4: tracking_wrapper,
-reg__1097: APBGpsBlock__GCB1,
-reg__538: FPU__GB1,
-reg__1124: APBGpsBlock__GCB0,
-reg__123: VCU118RocketSystem__GC0,
-datapath__331: FPU__GB2,
-reg__1377: APBGpsBlock__GCB0,
-case__1420: tracking_wrapper,
-logic__2339: DCache,
-case__16: genesys2_rocket_top__GC0,
-case__182: VCU118RocketSystem__GC0,
-case__916: VCU118RocketSystem__GC0,
-cordic_atan_basic__parameterized0: tracking_wrapper,
-datapath__736: APBGpsBlock__GCB0,
-case__1056: VCU118RocketSystem__GC0,
-logic__624: VCU118RocketSystem__GC0,
-case__1357: tracking_wrapper,
-datapath__439: RocketTile__GCB0,
-logic__9115: APBGpsBlock__GCB0,
-logic__483: VCU118RocketSystem__GC0,
-keep__17: APBGpsBlock__GCB0,
-datapath__691: APBGpsBlock__GCB0,
-logic__8805: tracking_wrapper,
-datapath__705: APBGpsBlock__GCB0,
-case__1530: APBGpsBlock__GCB0,
-case__1630: APBGpsBlock__GCB0,
-reg__286: DCache,
-reg__820: VCU118RocketSystem__GC0,
-reg__909: VCU118RocketSystem__GC0,
-datapath__345: FPU__GB1,
-reg__326: RocketTile__GCB0,
-reg__1001: APBGpsBlock__GCB1, tracking_wrapper,
-reg__1000: APBGpsBlock__GCB1, tracking_wrapper,
-logic__6383: VCU118RocketSystem__GC0,
-datapath__79: VCU118RocketSystem__GC0,
-reg__347: RocketTile__GCB0,
-reg__361: RocketTile__GCB0,
-reg__690: RocketTile__GCB0,
-logic__1565: DCache,
-reg__1207: tracking_wrapper,
-logic__8410: tracking_wrapper,
-reg__1350: APBGpsBlock__GCB0,
-case__952: VCU118RocketSystem__GC0,
-datapath__342: FPU__GB1,
-case__1528: APBGpsBlock__GCB0,
-logic__6797: VCU118RocketSystem__GC0,
-mult_32_27_59: APBGpsBlock__GCB0,
-logic__4320: FPU__GB1,
-datapath__497: VCU118RocketSystem__GC0,
-reg__784: VCU118RocketSystem__GC0,
-logic__7413: VCU118RocketSystem__GC0,
-reg__136: VCU118RocketSystem__GC0,
-case__1368: tracking_wrapper,
-logic__6753: VCU118RocketSystem__GC0,
-logic__9252: APBGpsBlock__GCB0,
-dsp48e1__13: APBGpsBlock__GCB1,
-datapath__637: tracking_wrapper,
-case__1071: APBGpsBlock__GCB1,
-muxpart__59: FPU__GB0,
-datapath__715: APBGpsBlock__GCB0,
-logic__7309: VCU118RocketSystem__GC0,
-logic__5999: RocketTile__GCB0,
-logic__3052: FPU__GB2, FPU__GB1,
-case__928: VCU118RocketSystem__GC0,
-case__788: VCU118RocketSystem__GC0,
-logic__3814: FPU__GB1,
-case__986: VCU118RocketSystem__GC0,
-ram_2x115: TilePRCIDomain__GC0,
-reg__1002: APBGpsBlock__GCB1,
-TLInterconnectCoupler_cbus_to_bus_named_pbus: VCU118RocketSystem__GC0,
-logic__9096: APBGpsBlock__GCB0,
-case__912: VCU118RocketSystem__GC0,
-acq_top: APBGpsBlock__GCB1,
-logic__2873: FPU__GB1,
-reg__1171: tracking_wrapper,
-case__1044: VCU118RocketSystem__GC0,
-datapath__475: VCU118RocketSystem__GC0,
-case__1090: APBGpsBlock__GCB1,
-reg__133: VCU118RocketSystem__GC0,
-reg__1216: tracking_wrapper,
-logic__3924: FPU__GB2, FPU__GB1,
-muxpart__106: RocketTile__GCB0,
-case__1235: APBGpsBlock__GCB1,
-reg__435: FPU__GB2,
-logic__5406: RocketTile__GCB0,
-case__865: VCU118RocketSystem__GC0,
-datapath__470: VCU118RocketSystem__GC0,
-case__426: RocketTile__GCB0,
-logic__1711: DCache,
-case__360: DCache,
-muxpart__63: FPU__GB0,
-logic__5315: RocketTile__GCB0,
-reg__348: RocketTile__GCB0,
-logic__9167: APBGpsBlock__GCB0,
-RoundAnyRawFNToRecFN_1: FPU__GB2,
-case__1242: APBGpsBlock__GCB1,
-logic__6412: VCU118RocketSystem__GC0,
-datapath__163: VCU118RocketSystem__GC0,
-case__63: VCU118RocketSystem__GC0,
-reg__26: VCU118RocketSystem__GC0,
-logic__8911: APBGpsBlock__GCB0,
-datapath__654: tracking_wrapper,
-tracking_wrapper: tracking_wrapper,
-dual_port_bram__parameterized1: APBGpsBlock__GCB1,
-logic__7892: APBGpsBlock__GCB1,
-logic__8981: APBGpsBlock__GCB0,
-logic__7297: VCU118RocketSystem__GC0,
-case__584: FPU__GB2,
-reg__102: VCU118RocketSystem__GC0,
-logic__2110: DCache,
-logic__3871: FPU__GB1,
-logic__4165: FPU__GB2,
-reg__1361: APBGpsBlock__GCB0,
-logic__1110: VCU118RocketSystem__GC0,
-case__177: VCU118RocketSystem__GC0,
-case__1130: APBGpsBlock__GCB1,
-datapath__639: tracking_wrapper,
-logic__5718: RocketTile__GCB0,
-logic__1244: VCU118RocketSystem__GC0,
-reg__450: FPU__GB2,
-datapath__390: FPU__GB1,
-logic__7490: VCU118RocketSystem__GC0,
-logic__5467: RocketTile__GCB0,
-logic__6585: VCU118RocketSystem__GC0,
-datapath__318: FPU__GB2,
-logic__2823: FPU__GB1,
-case__886: VCU118RocketSystem__GC0,
-logic__601: VCU118RocketSystem__GC0,
-logic__553: VCU118RocketSystem__GC0,
-reg__376: FPU__GB0,
-logic__1401: VCU118RocketSystem__GC0,
-logic__5072: RocketTile__GCB0,
-logic__5322: RocketTile__GCB0,
-logic__6453: VCU118RocketSystem__GC0,
-reg__951: VCU118RocketSystem__GC0,
-reg__373: FPU__GB0,
-case__184: VCU118RocketSystem__GC0,
-logic__5137: RocketTile__GCB0,
-datapath__271: RocketTile__GCB0,
-reg__1169: tracking_wrapper,
-case__24: VCU118RocketSystem__GC0,
-logic__2218: DCache,
-logic__7333: VCU118RocketSystem__GC0,
-reg__1079: APBGpsBlock__GCB1,
-case__950: VCU118RocketSystem__GC0,
-logic__9148: APBGpsBlock__GCB0,
-reg__745: RocketTile__GCB0,
-logic__6499: VCU118RocketSystem__GC0,
-reg__849: VCU118RocketSystem__GC0,
-case__1053: VCU118RocketSystem__GC0,
-counter__34: APBGpsBlock__GCB0,
-reg__268: DCache,
-case__1684: TLToAPB,
-case__200: VCU118RocketSystem__GC0,
-case__546: FPU__GB2,
-logic__983: VCU118RocketSystem__GC0,
-logic__7757: APBGpsBlock__GCB1,
-logic__9171: APBGpsBlock__GCB0,
-datapath__532: APBGpsBlock__GCB1,
-logic__66: genesys2_rocket_top__GC0,
-reg__854: VCU118RocketSystem__GC0,
-logic__290: VCU118RocketSystem__GC0,
-logic__5003: RocketTile__GCB0,
-case__856: VCU118RocketSystem__GC0,
-dsp48e1__37: tracking_wrapper,
-case__782: RocketTile__GCB0,
-extrom: APBGpsBlock__GCB1,
-Arbiter2_Valid_PTWReq: RocketTile__GCB0,
-logic__552: VCU118RocketSystem__GC0,
-case__411: RocketTile__GCB0,
-logic__3596: FPU__GB1,
-logic__6108: TilePRCIDomain__GC0,
-logic__2436: RocketTile__GCB0,
-logic__5294: RocketTile__GCB0,
-logic__4322: FPU__GB2,
-logic__1611: DCache,
-reg__303: RocketTile__GCB0,
-reg__975: VCU118RocketSystem__GC0,
-logic__7054: VCU118RocketSystem__GC0,
-case__732: RocketTile__GCB0,
-logic__7721: APBGpsBlock__GCB1,
-extladd__1: tracking_wrapper,
-reg__1349: APBGpsBlock__GCB0,
-case__246: VCU118RocketSystem__GC0,
-case__544: FPU__GB2,
-logic__3883: FPU__GB1,
-reg__869: VCU118RocketSystem__GC0,
-datapath__243: DCache,
-datapath__268: RocketTile__GCB0,
-reg__930: VCU118RocketSystem__GC0,
-logic__1349: VCU118RocketSystem__GC0,
-bram: APBGpsBlock__GCB1,
-logic__5837: RocketTile__GCB0,
-reg__1392: APBGpsBlock__GCB0,
-case__519: FPU__GB1,
-datapath__610: APBGpsBlock__GCB1,
-case__68: VCU118RocketSystem__GC0,
-reg__370: FPU__GB0,
-AsyncResetSynchronizerShiftReg_w1_d3_i0: VCU118RocketSystem__GC0, APBGpsBlock__GCB1, APBGpsBlock__GCB0,
-logic__4786: RocketTile__GCB0,
-muxpart__303: APBGpsBlock__GCB0,
-logic__2252: DCache,
-logic__4247: FPU__GB2,
-AsyncQueueSink_DebugInternalBundle: VCU118RocketSystem__GC0,
-logic__9373: TLToAPB,
-counter__23: tracking_wrapper,
-logic__6755: VCU118RocketSystem__GC0,
-reg__174: VCU118RocketSystem__GC0,
-logic__7873: APBGpsBlock__GCB1,
-logic__2673: RocketTile__GCB0,
-reg__1011: APBGpsBlock__GCB1,
-case__1461: tracking_wrapper,
-logic__2283: DCache,
-logic__9296: APBGpsBlock__GCB0,
-datapath__401: RocketTile__GCB0,
-logic__9159: APBGpsBlock__GCB0,
-logic__5661: RocketTile__GCB0,
-case__763: RocketTile__GCB0,
-datapath__252: DCache,
-muxpart__233: tracking_wrapper,
-logic__5265: RocketTile__GCB0,
-logic__3465: FPU__GB2,
-logic__539: VCU118RocketSystem__GC0,
-logic__3591: FPU__GB1,
-logic__2196: DCache,
-logic__1945: DCache,
-reg__146: VCU118RocketSystem__GC0,
-logic__3515: FPU__GB2,
-case__466: FPU__GB2, FPU__GB1,
-reg__342: RocketTile__GCB0,
-logic__9231: APBGpsBlock__GCB0,
-case__377: RocketTile__GCB0,
-reg__251: DCache,
-muxpart__70: FPU__GB0,
-Arbiter3_LLWB: RocketTile__GCB0,
-logic__1102: VCU118RocketSystem__GC0,
-counter__7: APBGpsBlock__GCB1,
-logic__8787: tracking_wrapper,
-logic__6542: VCU118RocketSystem__GC0,
-case__693: RocketTile__GCB0,
-logic__4507: FPU__GB1,
-logic__5956: RocketTile__GCB0,
-logic__2049: DCache,
-logic__9195: APBGpsBlock__GCB0,
-reg__987: VCU118RocketSystem__GC0,
-reg__796: VCU118RocketSystem__GC0,
-case__149: VCU118RocketSystem__GC0,
-reg__88: VCU118RocketSystem__GC0,
-logic__3746: FPU__GB1,
-case__1128: APBGpsBlock__GCB1,
-case__809: VCU118RocketSystem__GC0,
-reg__173: VCU118RocketSystem__GC0,
-logic__3790: FPU__GB1,
-logic__1405: VCU118RocketSystem__GC0,
-logic__8422: tracking_wrapper,
-logic__7424: VCU118RocketSystem__GC0,
-logic__338: VCU118RocketSystem__GC0,
-logic__3719: FPU__GB1,
-logic__5314: RocketTile__GCB0,
-logic__272: VCU118RocketSystem__GC0,
-Queue2_TLBundleA_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__2222: DCache,
-bit_gen: tracking_wrapper,
-case__442: RocketTile__GCB0,
-logic__5553: RocketTile__GCB0,
-logic__4817: RocketTile__GCB0,
-logic__7743: APBGpsBlock__GCB1,
-logic__3163: FPU__GB2,
-reg__1403: APBGpsBlock__GCB0,
-logic__5083: RocketTile__GCB0,
-case__1312: APBGpsBlock__GCB1,
-logic__5089: RocketTile__GCB0,
-logic__884: VCU118RocketSystem__GC0,
-logic__7123: VCU118RocketSystem__GC0,
-logic__6326: VCU118RocketSystem__GC0,
-logic__7993: APBGpsBlock__GCB1,
-logic__8851: tracking_wrapper,
-case__473: FPU__GB2,
-case__909: VCU118RocketSystem__GC0,
-case__112: VCU118RocketSystem__GC0,
-reg__293: RocketTile__GCB0,
-logic__9380: genesys2_rocket_top__GC0,
-reg__929: VCU118RocketSystem__GC0,
-logic__6842: VCU118RocketSystem__GC0,
-logic__6400: VCU118RocketSystem__GC0,
-datapath__431: RocketTile__GCB0,
-reg__672: RocketTile__GCB0,
-logic__1928: DCache,
-logic__892: VCU118RocketSystem__GC0,
-logic__1578: DCache,
-logic__3031: FPU__GB2, FPU__GB1,
-logic__6835: VCU118RocketSystem__GC0,
-datapath__506: VCU118RocketSystem__GC0,
-logic__4131: FPU__GB2,
-reg__189: VCU118RocketSystem__GC0,
-case__1220: APBGpsBlock__GCB1,
-case__1544: APBGpsBlock__GCB0,
-case__939: VCU118RocketSystem__GC0,
-case__1306: APBGpsBlock__GCB1,
-logic__3007: FPU__GB2, FPU__GB1,
-logic__6633: VCU118RocketSystem__GC0,
-case__1332: APBGpsBlock__GCB1,
-logic__6194: VCU118RocketSystem__GC0,
-reg__126: VCU118RocketSystem__GC0,
-case__455: FPU__GB1,
-case__1437: tracking_wrapper,
-case__624: RocketTile__GCB0,
-reg__158: VCU118RocketSystem__GC0,
-logic__1702: DCache,
-logic__1759: DCache,
-reg__424: FPU__GB1,
-keep__15: APBGpsBlock__GCB0,
-case__1013: VCU118RocketSystem__GC0,
-logic__8162: APBGpsBlock__GCB1,
-logic__4062: FPU__GB2,
-logic__7830: APBGpsBlock__GCB1,
-logic__6117: VCU118RocketSystem__GC0,
-logic__8169: APBGpsBlock__GCB1,
-case__1369: tracking_wrapper,
-reg__1445: APBGpsBlock__GCB0,
-logic__2805: FPU__GB1,
-logic__1294: VCU118RocketSystem__GC0,
-logic__5551: RocketTile__GCB0,
-logic__8273: tracking_wrapper,
-logic__3724: FPU__GB1,
-logic__2733: FPU__GB1,
-logic__3381: FPU__GB2,
-case__1632: APBGpsBlock__GCB0,
-logic__2105: DCache,
-datapath__591: APBGpsBlock__GCB1,
-case__734: RocketTile__GCB0,
-case__1494: tracking_wrapper,
-Repeater_TLBundleA_a32d64s2k1z3u: RocketTile__GCB0,
-reg__1103: APBGpsBlock__GCB1,
-reg__1418: APBGpsBlock__GCB0,
-reg__990: VCU118RocketSystem__GC0,
-case__1023: VCU118RocketSystem__GC0,
-reg__832: VCU118RocketSystem__GC0,
-logic__4055: FPU__GB2,
-logic__8440: tracking_wrapper,
-case__525: FPU__GB2, FPU__GB1,
-reg__698: RocketTile__GCB0,
-reg__811: VCU118RocketSystem__GC0,
-logic__1683: DCache,
-case__660: RocketTile__GCB0,
-case__105: VCU118RocketSystem__GC0,
-reg__542: FPU__GB1,
-logic__2728: FPU__GB1,
-datapath__483: VCU118RocketSystem__GC0,
-logic__5070: RocketTile__GCB0,
-logic__2836: FPU__GB1,
-case__830: VCU118RocketSystem__GC0,
-case__54: VCU118RocketSystem__GC0,
-logic__2001: DCache,
-extram__1: RocketTile__GCB0,
-logic__1103: VCU118RocketSystem__GC0,
-reg__148: VCU118RocketSystem__GC0,
-reg__1146: tracking_wrapper,
-reg__119: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__777: TilePRCIDomain__GC0,
-logic__8689: tracking_wrapper,
-logic__5421: RocketTile__GCB0,
-logic__4557: RocketTile__GCB0,
-datapath__250: DCache,
-case__1229: APBGpsBlock__GCB1,
-logic__6850: VCU118RocketSystem__GC0,
-logic__2989: FPU__GB2, FPU__GB1,
-datapath__51: VCU118RocketSystem__GC0,
-logic__2305: DCache,
-logic__3277: FPU__GB2,
-reg__1089: APBGpsBlock__GCB1,
-logic__6740: VCU118RocketSystem__GC0,
-logic__3402: FPU__GB2,
-reg__954: VCU118RocketSystem__GC0,
-logic__6574: VCU118RocketSystem__GC0,
-logic__4054: FPU__GB2,
-logic__8528: tracking_wrapper,
-reg__654: RocketTile__GCB0,
-logic__6998: VCU118RocketSystem__GC0,
-case__820: VCU118RocketSystem__GC0,
-logic__1779: DCache,
-logic__1520: DCache,
-logic__6098: RocketTile__GCB0,
-datapath__642: tracking_wrapper,
-case__918: VCU118RocketSystem__GC0,
-logic__1311: VCU118RocketSystem__GC0,
-ClockGroup: VCU118RocketSystem__GC0,
-logic__2192: DCache,
-datapath__706: APBGpsBlock__GCB0,
-logic__1587: DCache,
-logic__2903: FPU__GB1,
-logic__4774: RocketTile__GCB0,
-reg__1208: tracking_wrapper,
-logic__3874: FPU__GB1,
-logic__1477: RocketTile__GCB0,
-logic__6749: VCU118RocketSystem__GC0,
-case__1418: tracking_wrapper,
-logic__6601: VCU118RocketSystem__GC0,
-ITLB: RocketTile__GCB0,
-reg__1394: APBGpsBlock__GCB0,
-datapath__59: VCU118RocketSystem__GC0,
-case__688: RocketTile__GCB0,
-reg__8: genesys2_rocket_top__GC0,
-logic__5437: RocketTile__GCB0,
-logic__7715: APBGpsBlock__GCB1,
-datapath__550: APBGpsBlock__GCB1,
-logic__2409: RocketTile__GCB0,
-reg__503: FPU__GB2,
-case__768: RocketTile__GCB0,
-datapath__679: tracking_wrapper,
-logic__674: VCU118RocketSystem__GC0,
-datapath__622: tracking_wrapper,
-reg__196: VCU118RocketSystem__GC0,
-case__350: DCache,
-logic__6771: VCU118RocketSystem__GC0,
-logic__1096: VCU118RocketSystem__GC0,
-reg__1071: APBGpsBlock__GCB1,
-reg__1402: APBGpsBlock__GCB0,
-logic__7740: APBGpsBlock__GCB1,
-TLFpgaSPI: VCU118RocketSystem__GC0,
-logic__2009: DCache,
-logic__6097: RocketTile__GCB0,
-logic__5416: RocketTile__GCB0,
-logic__257: VCU118RocketSystem__GC0,
-logic__7436: VCU118RocketSystem__GC0,
-case__1605: APBGpsBlock__GCB0,
-case__1065: APBGpsBlock__GCB1,
-logic__9136: APBGpsBlock__GCB0,
-cos2x: tracking_wrapper,
-logic__6827: VCU118RocketSystem__GC0,
-logic__8220: APBGpsBlock__GCB1,
-reg__444: FPU__GB2,
-logic__6484: VCU118RocketSystem__GC0,
-case__1667: APBGpsBlock__GCB0,
-muxpart__34: FPU__GB0,
-case__145: VCU118RocketSystem__GC0,
-logic__8198: APBGpsBlock__GCB1,
-reg__825: VCU118RocketSystem__GC0,
-reg__362: RocketTile__GCB0,
-case__1429: tracking_wrapper,
-accum_dump: tracking_wrapper,
-case__387: RocketTile__GCB0,
-case__846: VCU118RocketSystem__GC0,
-logic__704: VCU118RocketSystem__GC0,
-case__1646: APBGpsBlock__GCB0,
-case__795: VCU118RocketSystem__GC0,
-case__1282: APBGpsBlock__GCB1,
-logic__146: VCU118RocketSystem__GC0,
-logic__5334: RocketTile__GCB0,
-logic__6751: VCU118RocketSystem__GC0,
-logic__3232: FPU__GB2,
-logic__6631: VCU118RocketSystem__GC0,
-muxpart__298: APBGpsBlock__GCB0,
-datapath__735: APBGpsBlock__GCB0,
-logic__7316: VCU118RocketSystem__GC0,
-case__940: VCU118RocketSystem__GC0,
-logic__7714: APBGpsBlock__GCB1,
-logic__3730: FPU__GB1,
-logic__2231: DCache,
-case__520: FPU__GB1,
-reg__116: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__85: VCU118RocketSystem__GC0,
-logic__1179: VCU118RocketSystem__GC0,
-logic__201: VCU118RocketSystem__GC0,
-reg__56: VCU118RocketSystem__GC0,
-logic__673: VCU118RocketSystem__GC0,
-case__1086: APBGpsBlock__GCB1,
-reg__217: VCU118RocketSystem__GC0,
-reg__1320: tracking_wrapper,
-logic__2051: DCache,
-case__467: FPU__GB1,
-logic__1168: VCU118RocketSystem__GC0,
-logic__6051: RocketTile__GCB0,
-logic__5407: RocketTile__GCB0,
-logic__7033: VCU118RocketSystem__GC0,
-case__110: VCU118RocketSystem__GC0,
-logic__2115: DCache,
-datapath__282: RocketTile__GCB0,
-case__622: RocketTile__GCB0,
-logic__9236: APBGpsBlock__GCB0,
-case__860: VCU118RocketSystem__GC0,
-logic__8623: tracking_wrapper,
-reg__978: VCU118RocketSystem__GC0,
-logic__2853: FPU__GB1,
-reg__449: FPU__GB2,
-logic__4514: FPU__GB1,
-datapath__157: VCU118RocketSystem__GC0,
-datapath__36: VCU118RocketSystem__GC0,
-datapath__398: RocketTile__GCB0,
-logic__9193: APBGpsBlock__GCB0,
-logic__6195: VCU118RocketSystem__GC0,
-case__249: VCU118RocketSystem__GC0,
-logic__626: VCU118RocketSystem__GC0,
-case__680: RocketTile__GCB0,
-case__14: genesys2_rocket_top__GC0,
-reg__1360: APBGpsBlock__GCB0,
-logic__8344: tracking_wrapper,
-case__796: VCU118RocketSystem__GC0,
-case__1488: tracking_wrapper,
-datapath__341: FPU__GB1,
-logic__9118: APBGpsBlock__GCB0,
-reg__70: VCU118RocketSystem__GC0,
-logic__2729: FPU__GB1,
-case__618: RocketTile__GCB0,
-logic__6826: VCU118RocketSystem__GC0,
-reg__769: RocketTile__GCB0,
-logic__1006: VCU118RocketSystem__GC0,
-logic__595: VCU118RocketSystem__GC0,
-datapath__615: APBGpsBlock__GCB1,
-logic__789: VCU118RocketSystem__GC0,
-reg__1348: APBGpsBlock__GCB0,
-reg__772: RocketTile__GCB0,
-reg__860: VCU118RocketSystem__GC0,
-reg__198: VCU118RocketSystem__GC0,
-logic__7232: VCU118RocketSystem__GC0,
-case__692: RocketTile__GCB0,
-case__1470: tracking_wrapper,
-logic__6200: VCU118RocketSystem__GC0,
-logic__721: VCU118RocketSystem__GC0,
-logic__205: VCU118RocketSystem__GC0,
-logic__3153: FPU__GB2,
-logic__52: genesys2_rocket_top__GC0,
-logic__1916: RocketTile__GCB0, DCache,
-logic__6112: VCU118RocketSystem__GC0,
-muxpart__299: APBGpsBlock__GCB0,
-reg__410: FPU__GB1,
-datapath__583: APBGpsBlock__GCB1,
-muxpart__1: genesys2_rocket_top__GC0,
-TLBusBypass: VCU118RocketSystem__GC0,
-reg__1092: APBGpsBlock__GCB1,
-case__742: RocketTile__GCB0,
-logic__7417: VCU118RocketSystem__GC0,
-reg__1448: TLToAPB,
-reg__1080: APBGpsBlock__GCB1,
-logic__17: genesys2_rocket_top__GC0,
-reg__150: VCU118RocketSystem__GC0,
-muxpart__40: FPU__GB0,
-case__359: DCache,
-case__1534: APBGpsBlock__GCB0,
-logic__7379: VCU118RocketSystem__GC0,
-muxpart__31: FPU__GB0,
-reg__1371: APBGpsBlock__GCB0,
-logic__5422: RocketTile__GCB0,
-logic__8853: tracking_wrapper,
-logic__3977: FPU__GB2, FPU__GB1,
-logic__4096: FPU__GB2,
-logic__319: VCU118RocketSystem__GC0,
-reg__527: FPU__GB1,
-datapath__471: VCU118RocketSystem__GC0,
-logic__4886: RocketTile__GCB0,
-reg__252: DCache,
-datapath__347: FPU__GB1,
-logic__250: VCU118RocketSystem__GC0,
-case__1294: APBGpsBlock__GCB1,
-logic__5312: RocketTile__GCB0,
-ram_2x77: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7588: VCU118RocketSystem__GC0,
-ClockCrossingReg_w15: VCU118RocketSystem__GC0,
-reg__48: VCU118RocketSystem__GC0,
-logic__4922: RocketTile__GCB0,
-case__1037: VCU118RocketSystem__GC0,
-logic__1502: RocketTile__GCB0,
-reg__868: VCU118RocketSystem__GC0,
-case__221: VCU118RocketSystem__GC0,
-reg__407: FPU__GB1,
-logic__8358: tracking_wrapper,
-logic__6103: TilePRCIDomain__GC0,
-reg__1102: APBGpsBlock__GCB1,
-case__619: RocketTile__GCB0,
-logic__6043: RocketTile__GCB0,
-reg__310: RocketTile__GCB0,
-logic__7412: VCU118RocketSystem__GC0,
-reg__1245: tracking_wrapper,
-reg__47: VCU118RocketSystem__GC0,
-reg__1382: APBGpsBlock__GCB0,
-logic__3239: FPU__GB2,
-logic__6494: VCU118RocketSystem__GC0,
-rocket_bscan_dmi_tunnel: genesys2_rocket_top__GC0,
-case__414: RocketTile__GCB0,
-logic__1830: DCache,
-datapath__234: VCU118RocketSystem__GC0,
-datapath__437: RocketTile__GCB0,
-case__1393: tracking_wrapper,
-logic__5405: RocketTile__GCB0,
-logic__320: VCU118RocketSystem__GC0,
-reg__724: RocketTile__GCB0,
-reg__1144: tracking_wrapper,
-reg__550: FPU__GB1,
-logic__7632: VCU118RocketSystem__GC0,
-case__216: VCU118RocketSystem__GC0,
-logic__8289: tracking_wrapper,
-logic__2651: RocketTile__GCB0,
-reg__1416: APBGpsBlock__GCB0,
-logic__6126: VCU118RocketSystem__GC0,
-logic__950: VCU118RocketSystem__GC0,
-logic__8788: tracking_wrapper,
-logic__4587: RocketTile__GCB0,
-logic__1017: VCU118RocketSystem__GC0,
-datapath__589: APBGpsBlock__GCB1,
-reg__1288: tracking_wrapper,
-datapath__635: tracking_wrapper,
-muxpart__102: RocketTile__GCB0,
-reg__1458: genesys2_rocket_top__GC0,
-logic__7643: VCU118RocketSystem__GC0,
-logic__6212: VCU118RocketSystem__GC0,
-logic__2896: FPU__GB1,
-logic__9112: APBGpsBlock__GCB0,
-datapath__539: APBGpsBlock__GCB1,
-logic__4035: FPU__GB2,
-logic__3726: FPU__GB1,
-logic__8749: tracking_wrapper,
-reg__1044: APBGpsBlock__GCB1,
-logic__6011: RocketTile__GCB0,
-logic__2667: RocketTile__GCB0,
-datapath__717: APBGpsBlock__GCB0,
-logic__4935: RocketTile__GCB0,
-logic__5394: RocketTile__GCB0,
-case__504: FPU__GB1,
-reg__837: VCU118RocketSystem__GC0, APBGpsBlock__GCB1, APBGpsBlock__GCB0,
-datapath__34: VCU118RocketSystem__GC0,
-datapath__667: tracking_wrapper,
-logic__1523: DCache,
-logic__6589: VCU118RocketSystem__GC0,
-reg__219: VCU118RocketSystem__GC0,
-logic__2381: RocketTile__GCB0,
-logic__829: VCU118RocketSystem__GC0,
-logic__5078: RocketTile__GCB0,
-case__677: RocketTile__GCB0,
-reg__1425: APBGpsBlock__GCB0,
-logic__4293: FPU__GB2,
-logic__7690: VCU118RocketSystem__GC0,
-logic__1278: VCU118RocketSystem__GC0,
-case__665: RocketTile__GCB0,
-case__1674: APBGpsBlock__GCB1,
-logic__6698: VCU118RocketSystem__GC0,
-logic__1486: RocketTile__GCB0,
-logic__2955: FPU__GB1,
-case__1149: APBGpsBlock__GCB1,
-logic__1445: RocketTile__GCB0,
-logic__3530: FPU__GB2,
-logic__2677: RocketTile__GCB0,
-reg__62: VCU118RocketSystem__GC0,
-logic__4181: FPU__GB2,
-logic__2581: RocketTile__GCB0,
-logic__1045: VCU118RocketSystem__GC0,
-logic__5396: RocketTile__GCB0,
-reg__963: VCU118RocketSystem__GC0,
-logic__7240: VCU118RocketSystem__GC0,
-case__1378: tracking_wrapper,
-Queue1_TLBundleD_a29d32s7k1z2u: TLToAPB,
-logic__2734: FPU__GB1,
-logic__5223: RocketTile__GCB0,
-case__380: RocketTile__GCB0,
-logic__5509: RocketTile__GCB0,
-logic__4231: FPU__GB2,
-reg__1115: APBGpsBlock__GCB1,
-logic__5062: RocketTile__GCB0,
-datapath__553: APBGpsBlock__GCB1,
-reg__1074: APBGpsBlock__GCB1,
-AsyncResetRegVec_w1_i0: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__3087: FPU__GB2,
-logic__6663: VCU118RocketSystem__GC0,
-logic__2994: FPU__GB2, FPU__GB1,
-logic__4441: FPU__GB1,
-case__352: DCache,
-reg__1190: tracking_wrapper,
-datapath__724: APBGpsBlock__GCB0,
-reg__1237: tracking_wrapper,
-keep__5: tracking_wrapper,
-case__852: VCU118RocketSystem__GC0,
-datapath__276: RocketTile__GCB0,
-logic__6492: VCU118RocketSystem__GC0,
-logic__8402: tracking_wrapper,
-logic__5004: RocketTile__GCB0,
-logic__6765: VCU118RocketSystem__GC0,
-logic__3893: FPU__GB2, FPU__GB1,
-reg__210: VCU118RocketSystem__GC0,
-datapath__544: APBGpsBlock__GCB1,
-counter__32: APBGpsBlock__GCB0,
-logic__4624: RocketTile__GCB0,
-logic__7151: VCU118RocketSystem__GC0,
-logic__9378: TLToAPB,
-logic__5073: RocketTile__GCB0,
-datapath__469: VCU118RocketSystem__GC0,
-reg__414: FPU__GB1,
-case__421: RocketTile__GCB0,
-logic__1851: RocketTile__GCB0, DCache,
-logic__6216: VCU118RocketSystem__GC0,
-logic__2195: DCache,
-logic__3735: FPU__GB1,
-logic__1612: DCache,
-case__580: FPU__GB1,
-case__956: VCU118RocketSystem__GC0,
-case__1176: APBGpsBlock__GCB1,
-case__840: VCU118RocketSystem__GC0,
-logic__7968: APBGpsBlock__GCB1,
-case__1516: tracking_wrapper,
-logic__8747: tracking_wrapper,
-logic__6493: VCU118RocketSystem__GC0,
-datapath__494: VCU118RocketSystem__GC0,
-logic__2266: DCache,
-case__694: RocketTile__GCB0,
-logic__407: VCU118RocketSystem__GC0,
-reg__1256: tracking_wrapper,
-datapath__334: FPU__GB2,
-case__623: RocketTile__GCB0,
-logic__6038: RocketTile__GCB0,
-case__382: RocketTile__GCB0,
-reg__816: VCU118RocketSystem__GC0,
-case__1465: tracking_wrapper,
-case__1016: VCU118RocketSystem__GC0,
-case__985: VCU118RocketSystem__GC0,
-logic__5510: RocketTile__GCB0,
-logic__1447: RocketTile__GCB0,
-logic__3291: FPU__GB2,
-logic__152: VCU118RocketSystem__GC0,
-logic__9125: APBGpsBlock__GCB0,
-logic__4923: RocketTile__GCB0,
-logic__95: genesys2_rocket_top__GC0,
-reg__685: RocketTile__GCB0,
-logic__6371: VCU118RocketSystem__GC0,
-logic__445: VCU118RocketSystem__GC0,
-logic__7409: VCU118RocketSystem__GC0,
-datapath__154: VCU118RocketSystem__GC0,
-reg__642: RocketTile__GCB0,
-logic__1061: VCU118RocketSystem__GC0,
-logic__7477: VCU118RocketSystem__GC0,
-reg__97: VCU118RocketSystem__GC0,
-muxpart__191: APBGpsBlock__GCB1,
-TLFIFOFixer_2: VCU118RocketSystem__GC0,
-reg__638: RocketTile__GCB0,
-case__250: VCU118RocketSystem__GC0,
-reg__168: VCU118RocketSystem__GC0,
-datapath__577: APBGpsBlock__GCB1,
-logic__4979: RocketTile__GCB0,
-logic__7573: VCU118RocketSystem__GC0,
-case__911: VCU118RocketSystem__GC0,
-reg__852: VCU118RocketSystem__GC0,
-logic__7881: APBGpsBlock__GCB1,
-logic__9178: APBGpsBlock__GCB0,
-reg__416: FPU__GB1,
-logic__8703: tracking_wrapper,
-logic__5914: RocketTile__GCB0,
-logic__8535: tracking_wrapper,
-case__802: VCU118RocketSystem__GC0,
-logic__1329: VCU118RocketSystem__GC0,
-logic__526: VCU118RocketSystem__GC0,
-case__954: VCU118RocketSystem__GC0,
-logic__6843: VCU118RocketSystem__GC0,
-logic__6222: VCU118RocketSystem__GC0,
-logic__2877: FPU__GB1,
-logic__8488: tracking_wrapper,
-reg__143: VCU118RocketSystem__GC0,
-reg__128: VCU118RocketSystem__GC0,
-reg__477: FPU__GB1,
-case__1402: tracking_wrapper,
-case__427: RocketTile__GCB0,
-logic__5082: RocketTile__GCB0,
-reg__7: genesys2_rocket_top__GC0,
-logic__5328: RocketTile__GCB0,
-reg__1229: tracking_wrapper,
-logic__4164: FPU__GB2,
-logic__252: VCU118RocketSystem__GC0,
-logic__1596: DCache,
-dsp48e1__32: tracking_wrapper,
-case__1656: APBGpsBlock__GCB0,
-reg__281: DCache,
-logic__3182: FPU__GB2,
-logic__7087: VCU118RocketSystem__GC0,
-case__1097: APBGpsBlock__GCB1,
-case__406: RocketTile__GCB0,
-Queue2_TLBundleA_a32d64s2k1z3u: TilePRCIDomain__GC0,
-logic__4904: RocketTile__GCB0,
-case__224: VCU118RocketSystem__GC0,
-case__1681: TLToAPB,
-reg__1406: APBGpsBlock__GCB0,
-case__1286: APBGpsBlock__GCB1,
-muxpart__318: APBGpsBlock__GCB0,
-reg__595: RocketTile__GCB0,
-IntSyncSyncCrossingSink_n1x2: TilePRCIDomain__GC0,
-logic__859: VCU118RocketSystem__GC0,
-datapath__466: TilePRCIDomain__GC0,
-logic__3156: FPU__GB2,
-case__1633: APBGpsBlock__GCB0,
-case__316: DCache,
-logic__5532: RocketTile__GCB0,
-reg__269: DCache,
-case__425: RocketTile__GCB0,
-datapath__737: TLToAPB,
-reg__1354: APBGpsBlock__GCB0,
-cacode_gen_trck: tracking_wrapper,
-case__201: VCU118RocketSystem__GC0,
-logic__4531: RocketTile__GCB0,
-logic__6031: RocketTile__GCB0,
-case__987: VCU118RocketSystem__GC0,
-logic__8002: APBGpsBlock__GCB1,
-logic__2876: FPU__GB1,
-reg__29: VCU118RocketSystem__GC0,
-case__1482: tracking_wrapper,
-datapath__477: VCU118RocketSystem__GC0,
-case__921: VCU118RocketSystem__GC0,
-reg__225: VCU118RocketSystem__GC0,
-case__1537: APBGpsBlock__GCB0,
-logic__5175: RocketTile__GCB0,
-logic__2232: DCache,
-logic__4327: FPU__GB1,
-logic__5886: RocketTile__GCB0,
-logic__6489: VCU118RocketSystem__GC0,
-logic__1264: VCU118RocketSystem__GC0,
-counter__6: VCU118RocketSystem__GC0,
-logic__1029: VCU118RocketSystem__GC0,
-logic__9376: TLToAPB,
-reg__1088: APBGpsBlock__GCB1,
-logic__2933: FPU__GB1,
-FPGAUARTClockSinkDomain: VCU118RocketSystem__GC0,
-datapath__35: VCU118RocketSystem__GC0,
-CompareRecFN: FPU__GB2,
-logic__462: VCU118RocketSystem__GC0,
-logic__7463: VCU118RocketSystem__GC0,
-reg__199: VCU118RocketSystem__GC0,
-logic__4600: RocketTile__GCB0,
-TLXbar_pbus_out_i1_o4_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__6024: RocketTile__GCB0,
-reg__381: FPU__GB0,
-logic__1418: VCU118RocketSystem__GC0,
-case__79: VCU118RocketSystem__GC0,
-reg__894: VCU118RocketSystem__GC0,
-reg__484: FPU__GB1,
-case__729: RocketTile__GCB0,
-case__697: RocketTile__GCB0,
-logic__7829: APBGpsBlock__GCB1,
-IntXbar_i3_o1: RocketTile__GCB0,
-reg__107: VCU118RocketSystem__GC0,
-logic__6107: TilePRCIDomain__GC0,
-keep__31: APBGpsBlock__GCB0,
-reg__1390: APBGpsBlock__GCB0,
-signinv__1: VCU118RocketSystem__GC0,
-reg__876: VCU118RocketSystem__GC0,
-logic__1843: RocketTile__GCB0, DCache,
-case__443: RocketTile__GCB0,
-logic__6834: VCU118RocketSystem__GC0,
-logic__194: VCU118RocketSystem__GC0,
-datapath__614: APBGpsBlock__GCB1,
-logic__4805: RocketTile__GCB0,
-logic__8163: APBGpsBlock__GCB1,
-case__1649: APBGpsBlock__GCB0,
-logic__8335: tracking_wrapper,
-logic__1604: DCache,
-case__1315: APBGpsBlock__GCB1,
-reg__1027: APBGpsBlock__GCB1,
-logic__8748: tracking_wrapper,
-logic__1640: DCache,
-logic__2249: DCache,
-logic__4978: RocketTile__GCB0,
-datapath__241: DCache,
-reg__1205: tracking_wrapper,
-case__1629: APBGpsBlock__GCB0,
-logic__3359: FPU__GB2,
-reg__795: VCU118RocketSystem__GC0,
-logic__8944: APBGpsBlock__GCB0,
-reg__913: VCU118RocketSystem__GC0,
-case__941: VCU118RocketSystem__GC0,
-case__776: RocketTile__GCB0,
-logic__8407: tracking_wrapper,
-reg__599: RocketTile__GCB0,
-logic__6317: VCU118RocketSystem__GC0,
-datapath__69: VCU118RocketSystem__GC0,
-datapath__33: VCU118RocketSystem__GC0,
-logic__6930: VCU118RocketSystem__GC0,
-case__851: VCU118RocketSystem__GC0,
-reg__791: VCU118RocketSystem__GC0,
-logic__1331: VCU118RocketSystem__GC0,
-reg__1298: tracking_wrapper,
-logic__8830: tracking_wrapper,
-logic__5390: RocketTile__GCB0,
-case__1613: APBGpsBlock__GCB0,
-reg__1163: tracking_wrapper,
-logic__4895: RocketTile__GCB0,
-logic__826: VCU118RocketSystem__GC0,
-logic__2700: FPU__GB1,
-logic__4246: FPU__GB2,
-logic__5327: RocketTile__GCB0,
-logic__4162: FPU__GB2,
-reg__1391: APBGpsBlock__GCB0,
-reg__482: FPU__GB1,
-logic__3135: FPU__GB2,
-logic__6650: VCU118RocketSystem__GC0,
-datapath__487: VCU118RocketSystem__GC0,
-logic__888: VCU118RocketSystem__GC0,
-logic__1033: VCU118RocketSystem__GC0,
-logic__6191: VCU118RocketSystem__GC0,
-logic__1238: VCU118RocketSystem__GC0,
-datapath__140: VCU118RocketSystem__GC0,
-case__440: RocketTile__GCB0,
-logic__5432: RocketTile__GCB0,
-case__955: VCU118RocketSystem__GC0,
-reg__533: FPU__GB1,
-logic__3084: FPU__GB2,
-logic__321: VCU118RocketSystem__GC0,
-logic__1420: VCU118RocketSystem__GC0,
-case__1309: APBGpsBlock__GCB1,
-datapath__593: APBGpsBlock__GCB1,
-logic__8634: tracking_wrapper,
-case__908: VCU118RocketSystem__GC0,
-logic__4929: RocketTile__GCB0,
-case__772: RocketTile__GCB0,
-logic__2804: FPU__GB1,
-reg__1012: APBGpsBlock__GCB1,
-logic__6656: VCU118RocketSystem__GC0,
-reg__1420: APBGpsBlock__GCB0,
-counter__20: tracking_wrapper,
-logic__2895: FPU__GB1,
-logic__2867: FPU__GB1,
-AsyncQueueSink_TLBundleD_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__8341: tracking_wrapper,
-logic__2886: FPU__GB1,
-datapath__451: RocketTile__GCB0,
-reg__1327: tracking_wrapper,
-logic__5017: RocketTile__GCB0,
-logic__6823: VCU118RocketSystem__GC0,
-case__560: FPU__GB2,
-reg__680: RocketTile__GCB0,
-logic__69: genesys2_rocket_top__GC0,
-logic__4851: RocketTile__GCB0,
-logic__2194: DCache,
-reg__161: VCU118RocketSystem__GC0,
-case__197: VCU118RocketSystem__GC0,
-reg__580: RocketTile__GCB0,
-logic__6012: RocketTile__GCB0,
-datapath__284: RocketTile__GCB0,
-logic__6129: VCU118RocketSystem__GC0,
-TLBuffer_a32d64s2k1z3u: RocketTile__GCB0,
-logic__3175: FPU__GB2,
-datapath__554: APBGpsBlock__GCB1,
-reg__908: VCU118RocketSystem__GC0,
-case__1138: APBGpsBlock__GCB1,
-keep__35: APBGpsBlock__GCB0,
-reg__2: genesys2_rocket_top__GC0,
-case__922: VCU118RocketSystem__GC0,
-logic__4807: RocketTile__GCB0,
-logic__547: VCU118RocketSystem__GC0,
-logic__5295: RocketTile__GCB0,
-logic__6947: VCU118RocketSystem__GC0,
-reg__480: FPU__GB1,
-reg__118: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__3727: FPU__GB1,
-logic__430: VCU118RocketSystem__GC0,
-TLAsyncCrossingSource_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-reg__911: VCU118RocketSystem__GC0,
-case__260: VCU118RocketSystem__GC0,
-logic__6070: RocketTile__GCB0,
-case__755: RocketTile__GCB0,
-logic__2473: RocketTile__GCB0,
-reg__1176: tracking_wrapper,
-datapath__28: VCU118RocketSystem__GC0,
-logic__2069: DCache,
-logic__6193: VCU118RocketSystem__GC0,
-logic__6832: VCU118RocketSystem__GC0,
-logic__6227: VCU118RocketSystem__GC0,
-case__750: RocketTile__GCB0,
-reg__1048: APBGpsBlock__GCB1,
-logic__3595: FPU__GB1,
-logic__9122: APBGpsBlock__GCB0,
-case__349: DCache,
-logic__7500: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_cbus_to_plic: VCU118RocketSystem__GC0,
-logic__2480: RocketTile__GCB0,
-reg__1428: APBGpsBlock__GCB0,
-logic__2701: FPU__GB1,
-case__1021: VCU118RocketSystem__GC0,
-logic__6829: VCU118RocketSystem__GC0,
-logic__1274: VCU118RocketSystem__GC0,
-logic__4773: RocketTile__GCB0,
-logic__9161: APBGpsBlock__GCB0,
-logic__3694: FPU__GB1,
-logic__2910: FPU__GB1,
-reg__1270: tracking_wrapper,
-case__1382: tracking_wrapper,
-datapath__682: tracking_wrapper,
-datapath__270: RocketTile__GCB0,
-case__513: FPU__GB1,
-reg__997: VCU118RocketSystem__GC0,
-logic__5938: RocketTile__GCB0,
-datapath__46: VCU118RocketSystem__GC0,
-logic__2072: DCache,
-logic__6886: VCU118RocketSystem__GC0,
-logic__3270: FPU__GB2,
-reg__497: FPU__GB2,
-reg__1447: APBGpsBlock__GCB0,
-reg__540: FPU__GB2,
-logic__6015: RocketTile__GCB0,
-datapath__415: RocketTile__GCB0,
-logic__7884: APBGpsBlock__GCB1,
-reg__859: VCU118RocketSystem__GC0,
-Queue2_TLBundleA_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__1262: VCU118RocketSystem__GC0,
-reg__1370: APBGpsBlock__GCB0,
-case__1041: VCU118RocketSystem__GC0,
-reg__316: RocketTile__GCB0,
-reg__140: VCU118RocketSystem__GC0,
-case__627: RocketTile__GCB0,
-logic__7174: VCU118RocketSystem__GC0,
-reg__4: genesys2_rocket_top__GC0,
-reg__46: VCU118RocketSystem__GC0,
-logic__8652: tracking_wrapper,
-logic__2736: FPU__GB1,
-case__810: VCU118RocketSystem__GC0,
-logic__6021: RocketTile__GCB0,
-case__1474: tracking_wrapper,
-logic__8149: APBGpsBlock__GCB1,
-reg__1158: tracking_wrapper,
-datapath__617: APBGpsBlock__GCB1,
-case__749: RocketTile__GCB0,
-logic__3757: FPU__GB1,
-case__33: VCU118RocketSystem__GC0,
-case__801: VCU118RocketSystem__GC0,
-reg__428: FPU__GB1,
-logic__5731: RocketTile__GCB0,
-case__4: genesys2_rocket_top__GC0,
-logic__4321: FPU__GB2,
-logic__9379: VCU118RocketSystem__GC0,
-logic__7606: VCU118RocketSystem__GC0,
-logic__6290: VCU118RocketSystem__GC0,
-reg__742: RocketTile__GCB0,
-reg__1025: APBGpsBlock__GCB1,
-reg__1440: APBGpsBlock__GCB0,
-case__6: genesys2_rocket_top__GC0,
-reg__139: VCU118RocketSystem__GC0,
-logic__2932: FPU__GB1,
-logic__3901: FPU__GB2, FPU__GB1,
-case__1380: tracking_wrapper,
-reg__645: RocketTile__GCB0,
-Queue2_TLBundleA_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-datapath__500: VCU118RocketSystem__GC0,
-datapath__457: RocketTile__GCB0,
-case__283: VCU118RocketSystem__GC0,
-logic__9103: APBGpsBlock__GCB0,
-butterfly__parameterized0: APBGpsBlock__GCB1,
-reg__201: VCU118RocketSystem__GC0,
-case__345: DCache,
-logic__5665: RocketTile__GCB0,
-logic__5457: RocketTile__GCB0,
-logic__1391: VCU118RocketSystem__GC0,
-datapath__445: RocketTile__GCB0,
-case__447: FPU__GB1,
-reg__464: FPU__GB1,
-logic__2663: RocketTile__GCB0,
-ClockCrossingReg_w43: VCU118RocketSystem__GC0,
-reg__1016: APBGpsBlock__GCB1,
-logic__7447: VCU118RocketSystem__GC0,
-logic__6748: VCU118RocketSystem__GC0,
-case__163: VCU118RocketSystem__GC0,
-datapath__66: VCU118RocketSystem__GC0,
-logic__528: VCU118RocketSystem__GC0,
-counter__39: genesys2_rocket_top__GC0,
-case__348: DCache,
-logic__1848: RocketTile__GCB0, DCache,
-logic__4299: FPU__GB2,
-logic__4206: FPU__GB2,
-logic__9285: APBGpsBlock__GCB0,
-logic__2691: RocketTile__GCB0,
-reg__922: VCU118RocketSystem__GC0,
-logic__1434: RocketTile__GCB0,
-case__1298: APBGpsBlock__GCB1,
-case__165: VCU118RocketSystem__GC0,
-logic__6756: VCU118RocketSystem__GC0,
-DCache: DCache,
-datapath__115: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__736: RocketTile__GCB0,
-reg__774: RocketTile__GCB0,
-muxpart__14: DCache,
-logic__6384: VCU118RocketSystem__GC0,
-case__689: RocketTile__GCB0,
-reg__255: DCache,
-datapath__254: DCache,
-logic__4827: RocketTile__GCB0,
-reg__1140: tracking_wrapper,
-logic__598: VCU118RocketSystem__GC0,
-logic__2124: DCache,
-logic__3731: FPU__GB1,
-case__1180: APBGpsBlock__GCB1,
-logic__5533: RocketTile__GCB0,
-case__581: FPU__GB1,
-logic__4161: FPU__GB2,
-datapath__455: RocketTile__GCB0,
-reg__792: VCU118RocketSystem__GC0,
-Queue1_RegMapperInput_i23_m8: VCU118RocketSystem__GC0,
-case__858: VCU118RocketSystem__GC0,
-logic__1148: VCU118RocketSystem__GC0,
-case__1068: APBGpsBlock__GCB1,
-case__901: VCU118RocketSystem__GC0,
-logic__7642: VCU118RocketSystem__GC0,
-case__996: VCU118RocketSystem__GC0,
-datapath__486: VCU118RocketSystem__GC0,
-datapath__462: RocketTile__GCB0,
-logic__2212: DCache,
-reg__288: DCache,
-case__451: FPU__GB1,
-TLDebugModuleInnerAsync: VCU118RocketSystem__GC0,
-reg__165: VCU118RocketSystem__GC0,
-rom__7: tracking_wrapper,
-reg__85: VCU118RocketSystem__GC0,
-logic__1890: RocketTile__GCB0, DCache,
-logic__8832: tracking_wrapper,
-reg__675: RocketTile__GCB0,
-reg__529: FPU__GB1,
-logic__9158: APBGpsBlock__GCB0,
-logic__2478: RocketTile__GCB0,
-logic__3677: FPU__GB1,
-case__1170: APBGpsBlock__GCB1,
-datapath__118: VCU118RocketSystem__GC0,
-case__1370: tracking_wrapper,
-datapath__86: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_sbus_to_bus_named_cbus: VCU118RocketSystem__GC0,
-case__334: DCache,
-keep__10: APBGpsBlock__GCB0,
-logic__8653: tracking_wrapper,
-logic__1143: VCU118RocketSystem__GC0,
-rom__6: tracking_wrapper,
-logic__1208: VCU118RocketSystem__GC0,
-dsp48e1__10: APBGpsBlock__GCB1,
-case__461: FPU__GB2, FPU__GB1,
-logic__7650: VCU118RocketSystem__GC0,
-reg__212: VCU118RocketSystem__GC0,
-logic__4148: FPU__GB2,
-logic__408: VCU118RocketSystem__GC0,
-logic__2419: RocketTile__GCB0,
-logic__4471: FPU__GB1,
-logic__4245: FPU__GB2,
-logic__2835: FPU__GB1,
-logic__2004: DCache,
-logic__6758: VCU118RocketSystem__GC0,
-logic__7729: APBGpsBlock__GCB1,
-logic__650: VCU118RocketSystem__GC0,
-reg__332: RocketTile__GCB0,
-logic__4614: RocketTile__GCB0,
-logic__8704: tracking_wrapper,
-reg__610: RocketTile__GCB0,
-logic__2214: DCache,
-logic__8936: APBGpsBlock__GCB0,
-reg__696: RocketTile__GCB0,
-MulAddRecFNPipe_l2_e8_s24: FPU__GB1,
-case__274: VCU118RocketSystem__GC0,
-logic__4175: FPU__GB2,
-logic__5550: RocketTile__GCB0,
-logic__9174: APBGpsBlock__GCB0,
-case__790: VCU118RocketSystem__GC0,
-TLXbar_pbus_in_i1_o1_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__8596: tracking_wrapper,
-logic__9177: APBGpsBlock__GCB0,
-logic__7437: VCU118RocketSystem__GC0,
-case__42: VCU118RocketSystem__GC0,
-datapath__109: VCU118RocketSystem__GC0,
-datapath__133: VCU118RocketSystem__GC0,
-reg__1202: tracking_wrapper,
-reg__1421: APBGpsBlock__GCB0,
-logic__8908: tracking_wrapper,
-case__1027: VCU118RocketSystem__GC0,
-logic__4876: RocketTile__GCB0,
-reg__1415: APBGpsBlock__GCB0,
-reg__512: FPU__GB2,
-reg__800: VCU118RocketSystem__GC0,
-case__1025: VCU118RocketSystem__GC0,
-logic__8758: tracking_wrapper,
-reg__1312: tracking_wrapper,
-logic__2693: FPU__GB1,
-reg__451: FPU__GB1,
-logic__7360: VCU118RocketSystem__GC0,
-logic__261: VCU118RocketSystem__GC0,
-logic__3872: FPU__GB1,
-logic__3709: FPU__GB1,
-case__48: VCU118RocketSystem__GC0,
-logic__2992: FPU__GB2, FPU__GB1,
-logic__9179: APBGpsBlock__GCB0,
-datapath__294: FPU__GB1,
-case__409: RocketTile__GCB0,
-case__897: VCU118RocketSystem__GC0,
-reg__278: DCache,
-reg__587: RocketTile__GCB0,
-logic__6924: VCU118RocketSystem__GC0,
-logic__627: VCU118RocketSystem__GC0,
-reg__25: VCU118RocketSystem__GC0,
-case__344: DCache,
-logic__3514: FPU__GB2,
-logic__1614: DCache,
-logic__2545: RocketTile__GCB0,
-datapath__376: FPU__GB2,
-logic__2250: DCache,
-logic__7800: APBGpsBlock__GCB1,
-logic__3079: FPU__GB2,
-case__261: VCU118RocketSystem__GC0,
-logic__690: VCU118RocketSystem__GC0,
-counter__9: APBGpsBlock__GCB1,
-case__1608: APBGpsBlock__GCB0,
-case__592: FPU__GB1,
-logic__8298: tracking_wrapper,
-logic__5998: RocketTile__GCB0,
-logic__9339: APBGpsBlock__GCB0,
-case__1548: APBGpsBlock__GCB0,
-logic__6554: VCU118RocketSystem__GC0,
-reg__393: FPU__GB0,
-logic__3734: FPU__GB1,
-logic__5876: RocketTile__GCB0,
-logic__7258: VCU118RocketSystem__GC0,
-datapath__474: VCU118RocketSystem__GC0,
-logic__2253: DCache,
-reg__10: genesys2_rocket_top__GC0,
-IntSyncCrossingSource_n1x2: VCU118RocketSystem__GC0,
-datapath__56: VCU118RocketSystem__GC0,
-muxpart__307: APBGpsBlock__GCB0,
-logic__6547: VCU118RocketSystem__GC0,
-case__938: VCU118RocketSystem__GC0,
-logic__3129: FPU__GB2,
-case__1658: APBGpsBlock__GCB0,
-logic__4908: RocketTile__GCB0,
-datapath__162: VCU118RocketSystem__GC0,
-logic__5484: RocketTile__GCB0,
-reg__487: FPU__GB1,
-case__1333: APBGpsBlock__GCB1,
-logic__5418: RocketTile__GCB0,
-reg__827: VCU118RocketSystem__GC0,
-case__887: VCU118RocketSystem__GC0,
-datapath__472: VCU118RocketSystem__GC0,
-logic__599: VCU118RocketSystem__GC0,
-reg__814: VCU118RocketSystem__GC0,
-case__543: FPU__GB2,
-logic__6454: VCU118RocketSystem__GC0,
-datapath__64: VCU118RocketSystem__GC0,
-case__1552: APBGpsBlock__GCB0,
-datapath__166: VCU118RocketSystem__GC0,
-keep__39: APBGpsBlock__GCB0,
-logic__1258: VCU118RocketSystem__GC0,
-logic__2148: DCache,
-reg__649: RocketTile__GCB0,
-logic__5429: RocketTile__GCB0,
-case__678: RocketTile__GCB0,
-reg__1287: tracking_wrapper,
-datapath__316: FPU__GB2,
-reg__806: VCU118RocketSystem__GC0,
-reg__141: VCU118RocketSystem__GC0,
-logic__1531: DCache,
-logic__4482: FPU__GB1,
-muxpart__13: DCache,
-case__515: FPU__GB1,
-reg__763: RocketTile__GCB0,
-logic__322: VCU118RocketSystem__GC0,
-logic__7414: VCU118RocketSystem__GC0,
-logic__1222: VCU118RocketSystem__GC0,
-logic__5321: RocketTile__GCB0,
-logic__6706: VCU118RocketSystem__GC0,
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1: VCU118RocketSystem__GC0,
-case__1365: tracking_wrapper,
-reg__457: FPU__GB1,
-reg__760: RocketTile__GCB0,
-logic__7343: VCU118RocketSystem__GC0,
-datapath__403: RocketTile__GCB0,
-reg__1398: APBGpsBlock__GCB0,
-datapath__400: RocketTile__GCB0,
-logic__6793: VCU118RocketSystem__GC0,
-reg__762: RocketTile__GCB0,
-logic__8005: APBGpsBlock__GCB1,
-logic__6037: RocketTile__GCB0,
-logic__6847: VCU118RocketSystem__GC0,
-logic__7042: VCU118RocketSystem__GC0,
-datapath__98: VCU118RocketSystem__GC0,
-case__44: VCU118RocketSystem__GC0,
-case__1514: tracking_wrapper,
-case__549: FPU__GB2,
-logic__7713: APBGpsBlock__GCB1,
-case__636: RocketTile__GCB0,
-logic__5919: RocketTile__GCB0,
-case__593: FPU__GB1,
-reg__579: RocketTile__GCB0,
-muxpart__27: FPU__GB0,
-logic__1210: VCU118RocketSystem__GC0,
-logic__1065: VCU118RocketSystem__GC0,
-logic__2931: FPU__GB1,
-logic__605: VCU118RocketSystem__GC0,
-case__310: DCache,
-logic__697: VCU118RocketSystem__GC0,
-reg__739: RocketTile__GCB0,
-reg__73: VCU118RocketSystem__GC0,
-logic__5454: RocketTile__GCB0,
-logic__5993: RocketTile__GCB0,
-case__1669: APBGpsBlock__GCB0,
-logic__6452: VCU118RocketSystem__GC0,
-logic__9301: APBGpsBlock__GCB0,
-logic__9273: APBGpsBlock__GCB0,
-logic__2899: FPU__GB1,
-case__1519: tracking_wrapper,
-case__322: DCache,
-logic__5923: RocketTile__GCB0,
-logic__7322: VCU118RocketSystem__GC0,
-logic__1032: VCU118RocketSystem__GC0,
-logic__9340: APBGpsBlock__GCB0,
-logic__1265: VCU118RocketSystem__GC0,
-logic__631: VCU118RocketSystem__GC0,
-logic__2579: RocketTile__GCB0,
-logic__5388: RocketTile__GCB0,
-logic__1367: VCU118RocketSystem__GC0,
-datapath__290: FPU__GB1,
-logic__1399: VCU118RocketSystem__GC0,
-logic__3090: FPU__GB2,
-case__273: VCU118RocketSystem__GC0,
-logic__3294: FPU__GB2,
-reg__1252: tracking_wrapper,
-logic__1092: VCU118RocketSystem__GC0,
-reg__1061: APBGpsBlock__GCB1,
-logic__7207: VCU118RocketSystem__GC0,
-reg__181: VCU118RocketSystem__GC0,
-logic__1763: DCache,
-case__767: RocketTile__GCB0,
-reg__187: VCU118RocketSystem__GC0,
-datapath__209: VCU118RocketSystem__GC0,
-case__679: RocketTile__GCB0,
-logic__6223: VCU118RocketSystem__GC0,
-datapath__227: VCU118RocketSystem__GC0,
-PTW: RocketTile__GCB0,
-logic__4028: FPU__GB2,
-reg__979: VCU118RocketSystem__GC0,
-logic__894: VCU118RocketSystem__GC0,
-muxpart__83: FPU__GB0,
-reg__459: FPU__GB1,
-case__869: VCU118RocketSystem__GC0,
-TLBuffer_a32d64s2k1z4u_1: VCU118RocketSystem__GC0,
-logic__493: VCU118RocketSystem__GC0,
-logic__5318: RocketTile__GCB0,
-logic__9355: TLToAPB,
-case__1284: APBGpsBlock__GCB1,
-rom__1: APBGpsBlock__GCB1,
-logic__5333: RocketTile__GCB0,
-datapath__57: VCU118RocketSystem__GC0,
-reg__1162: tracking_wrapper,
-reg__848: VCU118RocketSystem__GC0,
-case__1559: APBGpsBlock__GCB0,
-reg__470: FPU__GB1,
-case__7: genesys2_rocket_top__GC0,
-case__1127: APBGpsBlock__GCB1,
-logic__440: VCU118RocketSystem__GC0,
-logic__4899: RocketTile__GCB0,
-reg__279: DCache,
-case__1538: APBGpsBlock__GCB0,
-datapath__434: RocketTile__GCB0,
-case__464: FPU__GB2, FPU__GB1,
-logic__808: VCU118RocketSystem__GC0,
-logic__749: VCU118RocketSystem__GC0,
-logic__123: VCU118RocketSystem__GC0,
-reg__1003: APBGpsBlock__GCB1,
-logic__2935: FPU__GB1,
-reg__686: RocketTile__GCB0,
-reg__496: FPU__GB2,
-logic__8153: APBGpsBlock__GCB1,
-logic__1739: DCache,
-cdc_fifo_gray: tracking_wrapper,
-datapath__125: VCU118RocketSystem__GC0,
-case__59: VCU118RocketSystem__GC0,
-reg__942: VCU118RocketSystem__GC0,
-case__1557: APBGpsBlock__GCB0,
-logic__6132: VCU118RocketSystem__GC0,
-muxpart__35: FPU__GB0,
-case__613: RocketTile__GCB0,
-datapath__460: RocketTile__GCB0,
-case__1485: tracking_wrapper,
-reg__1135: tracking_wrapper,
-logic__1214: VCU118RocketSystem__GC0,
-logic__1196: VCU118RocketSystem__GC0,
-reg__368: RocketTile__GCB0,
-logic__182: VCU118RocketSystem__GC0,
-reg__1357: APBGpsBlock__GCB0,
-logic__38: genesys2_rocket_top__GC0,
-logic__813: VCU118RocketSystem__GC0,
-logic__3733: FPU__GB1,
-reg__147: VCU118RocketSystem__GC0,
-logic__271: VCU118RocketSystem__GC0,
-logic__6016: RocketTile__GCB0,
-logic__309: VCU118RocketSystem__GC0,
-logic__3274: FPU__GB2,
-reg__949: VCU118RocketSystem__GC0,
-rom__4: APBGpsBlock__GCB1,
-logic__3887: FPU__GB1,
-logic__130: VCU118RocketSystem__GC0,
-logic__7935: APBGpsBlock__GCB1,
-datapath__145: VCU118RocketSystem__GC0,
-datapath__392: RocketTile__GCB0,
-logic__6197: VCU118RocketSystem__GC0,
-datapath__219: VCU118RocketSystem__GC0,
-datapath__283: RocketTile__GCB0,
-logic__8909: APBGpsBlock__GCB0,
-case__1625: APBGpsBlock__GCB0,
-case__343: DCache,
-logic__9183: APBGpsBlock__GCB0,
-datapath__538: APBGpsBlock__GCB1,
-case__533: FPU__GB2, FPU__GB1,
-logic__3681: FPU__GB1,
-logic__2: genesys2_rocket_top__GC0,
-reg__994: VCU118RocketSystem__GC0,
-logic__9343: APBGpsBlock__GCB1,
-logic__1724: DCache,
-case__1685: TLToAPB,
-logic__6311: VCU118RocketSystem__GC0,
-logic__3902: FPU__GB2, FPU__GB1,
-logic__2441: RocketTile__GCB0,
-logic__4439: FPU__GB1,
-muxpart__4: genesys2_rocket_top__GC0,
-muxpart__3: genesys2_rocket_top__GC0,
-logic__4874: RocketTile__GCB0,
-logic__1776: DCache,
-logic__6410: VCU118RocketSystem__GC0,
-logic__1662: DCache,
-logic__4980: RocketTile__GCB0,
-case__1000: VCU118RocketSystem__GC0,
-logic__8541: tracking_wrapper,
-logic__6527: VCU118RocketSystem__GC0,
-logic__1691: DCache,
-case__907: VCU118RocketSystem__GC0,
-logic__253: VCU118RocketSystem__GC0,
-logic__4683: RocketTile__GCB0,
-counter__22: tracking_wrapper,
-logic__3559: FPU__GB1,
-case__972: VCU118RocketSystem__GC0,
-counter__2: VCU118RocketSystem__GC0,
-logic__2230: DCache,
-logic__9156: APBGpsBlock__GCB0,
-case__739: RocketTile__GCB0,
-logic__3266: FPU__GB2,
-TLFragmenter_bootrom: VCU118RocketSystem__GC0,
-reg__916: VCU118RocketSystem__GC0,
-case__748: RocketTile__GCB0,
-logic__1593: DCache,
-logic__5403: RocketTile__GCB0,
-reg__1407: APBGpsBlock__GCB0,
-reg__1164: tracking_wrapper,
-case__1135: APBGpsBlock__GCB1,
-case__1004: VCU118RocketSystem__GC0,
-logic__5332: RocketTile__GCB0,
-muxpart__66: FPU__GB0,
-logic__5941: RocketTile__GCB0,
-datapath__650: tracking_wrapper,
-logic__7422: VCU118RocketSystem__GC0,
-case__836: VCU118RocketSystem__GC0,
-logic__6312: VCU118RocketSystem__GC0,
-logic__2087: DCache,
-case__717: RocketTile__GCB0,
-logic__4646: RocketTile__GCB0,
-datapath__484: VCU118RocketSystem__GC0,
-reg__186: VCU118RocketSystem__GC0,
-case__664: RocketTile__GCB0,
-case__1447: tracking_wrapper,
-logic__710: VCU118RocketSystem__GC0,
-logic__186: VCU118RocketSystem__GC0,
-reg__438: FPU__GB2,
-logic__7237: VCU118RocketSystem__GC0,
-AsyncResetRegVec_w2_i0: VCU118RocketSystem__GC0,
-datapath__17: VCU118RocketSystem__GC0,
-logic__2204: DCache,
-logic__1993: DCache,
-case__66: VCU118RocketSystem__GC0,
-logic__134: VCU118RocketSystem__GC0,
-case__1231: APBGpsBlock__GCB1,
-case__571: FPU__GB1,
-TLError_1: VCU118RocketSystem__GC0,
-case__266: VCU118RocketSystem__GC0,
-logic__1097: VCU118RocketSystem__GC0,
-logic__5713: RocketTile__GCB0,
-muxpart__38: FPU__GB0,
-logic__1400: VCU118RocketSystem__GC0,
-logic__2954: FPU__GB1,
-logic__7405: VCU118RocketSystem__GC0,
-logic__8691: tracking_wrapper,
-reg__110: VCU118RocketSystem__GC0,
-logic__5489: RocketTile__GCB0,
-logic__6211: VCU118RocketSystem__GC0,
-ClockSinkDomain: VCU118RocketSystem__GC0,
-datapath__723: APBGpsBlock__GCB0,
-case__1546: APBGpsBlock__GCB0,
-logic__4032: FPU__GB2,
-case__403: RocketTile__GCB0,
-case__472: FPU__GB2,
-logic__2485: RocketTile__GCB0,
-case__1400: tracking_wrapper,
-logic__2712: FPU__GB1,
-datapath__221: VCU118RocketSystem__GC0,
-logic__8081: APBGpsBlock__GCB1,
-reg__752: RocketTile__GCB0,
-logic__7671: VCU118RocketSystem__GC0,
-logic__4438: FPU__GB1,
-muxpart__44: FPU__GB0,
-datapath__186: VCU118RocketSystem__GC0,
-logic__2050: DCache,
-logic__4613: RocketTile__GCB0,
-reg__379: FPU__GB0,
-logic__8775: tracking_wrapper,
-logic__4566: RocketTile__GCB0,
-case__244: VCU118RocketSystem__GC0,
-datapath__709: APBGpsBlock__GCB0,
-keep__11: APBGpsBlock__GCB0,
-case__185: VCU118RocketSystem__GC0,
-reg__203: VCU118RocketSystem__GC0,
-logic__4854: RocketTile__GCB0,
-case__417: RocketTile__GCB0,
-case__307: RocketTile__GCB0,
-fft_radix_2: APBGpsBlock__GCB1,
-reg__947: VCU118RocketSystem__GC0,
-reg__1331: tracking_wrapper,
-logic__2934: FPU__GB1,
-reg__295: RocketTile__GCB0,
-case__17: genesys2_rocket_top__GC0,
-logic__7118: VCU118RocketSystem__GC0,
-logic__2043: DCache,
-reg__1255: tracking_wrapper,
-case__1628: APBGpsBlock__GCB0,
-case: genesys2_rocket_top__GC0,
-case__81: VCU118RocketSystem__GC0,
-reg__1269: tracking_wrapper,
-case__490: FPU__GB2,
-logic__6766: VCU118RocketSystem__GC0,
-logic__7880: APBGpsBlock__GCB1,
-case__43: VCU118RocketSystem__GC0,
-logic__7427: VCU118RocketSystem__GC0,
-logic__8949: APBGpsBlock__GCB0,
-logic__3260: FPU__GB2,
-logic__2846: FPU__GB1,
-reg__1129: APBGpsBlock__GCB0,
-logic__3972: FPU__GB2, FPU__GB1,
-logic__2233: DCache,
-logic__6306: VCU118RocketSystem__GC0,
-logic__452: VCU118RocketSystem__GC0,
-logic__4202: FPU__GB2,
-case__1648: APBGpsBlock__GCB0,
-logic__5310: RocketTile__GCB0,
-logic__1594: DCache,
-reg__923: VCU118RocketSystem__GC0,
-case__67: VCU118RocketSystem__GC0,
-reg__971: VCU118RocketSystem__GC0,
-logic__1164: VCU118RocketSystem__GC0,
-logic__239: VCU118RocketSystem__GC0,
-case__1103: APBGpsBlock__GCB1,
-logic__6431: VCU118RocketSystem__GC0,
-datapath__391: RocketTile__GCB0,
-logic__3078: FPU__GB2,
-case__1048: VCU118RocketSystem__GC0,
-logic__207: VCU118RocketSystem__GC0,
-logic__5460: RocketTile__GCB0,
-logic__8847: tracking_wrapper,
-logic__461: VCU118RocketSystem__GC0,
-case__951: VCU118RocketSystem__GC0,
-logic__856: VCU118RocketSystem__GC0,
-logic__9123: APBGpsBlock__GCB0,
-reg__64: VCU118RocketSystem__GC0,
-reg__111: VCU118RocketSystem__GC0,
-datapath__646: tracking_wrapper,
-logic__6986: VCU118RocketSystem__GC0,
-reg__452: FPU__GB1,
-logic__1661: DCache,
-case__889: VCU118RocketSystem__GC0,
-logic__1894: RocketTile__GCB0, DCache,
-logic__6459: VCU118RocketSystem__GC0,
-logic__267: VCU118RocketSystem__GC0,
-case__1509: tracking_wrapper,
-case__1638: APBGpsBlock__GCB0,
-reg__1222: tracking_wrapper,
-logic__4983: RocketTile__GCB0,
-logic__6124: VCU118RocketSystem__GC0,
-logic__2276: DCache,
-logic__8359: tracking_wrapper,
-datapath__169: VCU118RocketSystem__GC0,
-logic__1799: DCache,
-addsub__2: tracking_wrapper,
-logic__2169: DCache,
-logic__7139: VCU118RocketSystem__GC0,
-logic__6174: VCU118RocketSystem__GC0,
-logic__390: VCU118RocketSystem__GC0,
-logic__1926: DCache,
-reset_synch: tracking_wrapper,
-logic__2851: FPU__GB1,
-logic__8626: tracking_wrapper,
-reg__934: VCU118RocketSystem__GC0,
-reg__355: RocketTile__GCB0,
-logic__882: VCU118RocketSystem__GC0,
-logic__8072: APBGpsBlock__GCB1,
-muxpart__87: FPU__GB2,
-logic__6041: RocketTile__GCB0,
-case__1477: tracking_wrapper,
-logic__6314: VCU118RocketSystem__GC0,
-reg__1063: APBGpsBlock__GCB1,
-logic__3855: FPU__GB1,
-muxpart__192: APBGpsBlock__GCB1,
-reg__16: genesys2_rocket_top__GC0,
-reg__705: RocketTile__GCB0,
-logic__6368: VCU118RocketSystem__GC0,
-case__1484: tracking_wrapper,
-reg__1439: APBGpsBlock__GCB0,
-logic__3022: FPU__GB2, FPU__GB1,
-muxpart__105: RocketTile__GCB0,
-reg__729: RocketTile__GCB0,
-logic__2411: RocketTile__GCB0,
-reg__1347: APBGpsBlock__GCB0,
-reg__701: RocketTile__GCB0,
-logic__6746: VCU118RocketSystem__GC0,
-logic__6019: RocketTile__GCB0,
-case__53: VCU118RocketSystem__GC0,
-logic__4754: RocketTile__GCB0,
-logic__5504: RocketTile__GCB0,
-logic__9124: APBGpsBlock__GCB0,
-reg__515: FPU__GB2,
-logic__1909: RocketTile__GCB0, DCache,
-case__39: VCU118RocketSystem__GC0,
-logic__6415: VCU118RocketSystem__GC0,
-logic__6199: VCU118RocketSystem__GC0,
-logic__1072: VCU118RocketSystem__GC0,
-muxpart__36: FPU__GB0,
-logic__6648: VCU118RocketSystem__GC0,
-reg__704: RocketTile__GCB0,
-logic__1762: DCache,
-logic__5926: RocketTile__GCB0,
-case__1555: APBGpsBlock__GCB0,
-datapath__668: tracking_wrapper,
-logic__5081: RocketTile__GCB0,
-logic__8854: tracking_wrapper,
-reg__782: VCU118RocketSystem__GC0,
-case__61: VCU118RocketSystem__GC0,
-logic__4097: FPU__GB2,
-case__157: VCU118RocketSystem__GC0,
-datapath__273: RocketTile__GCB0,
-logic__2735: FPU__GB1,
-logic__6540: VCU118RocketSystem__GC0,
-logic__6022: RocketTile__GCB0,
-logic__306: VCU118RocketSystem__GC0,
-logic__771: VCU118RocketSystem__GC0,
-IntSyncCrossingSource_n1x1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6036: RocketTile__GCB0,
-datapath__410: RocketTile__GCB0,
-muxpart__79: FPU__GB0,
-reg__467: FPU__GB1,
-logic__6366: VCU118RocketSystem__GC0,
-reg__787: VCU118RocketSystem__GC0,
-case__144: VCU118RocketSystem__GC0,
-datapath__599: APBGpsBlock__GCB1,
-reg__1277: tracking_wrapper,
-reg__1282: tracking_wrapper,
-reg__977: VCU118RocketSystem__GC0,
-logic__6257: VCU118RocketSystem__GC0,
-logic__2810: FPU__GB1,
-logic__7662: VCU118RocketSystem__GC0,
-logic__9138: APBGpsBlock__GCB0,
-case__423: RocketTile__GCB0,
-case__398: RocketTile__GCB0,
-muxpart__230: tracking_wrapper,
-logic__2906: FPU__GB1,
-logic__2197: DCache,
-logic__5123: RocketTile__GCB0,
-logic__5881: RocketTile__GCB0,
-logic__2826: FPU__GB1,
-logic__6233: VCU118RocketSystem__GC0,
-logic__2449: RocketTile__GCB0,
-reg__790: VCU118RocketSystem__GC0,
-case__1438: tracking_wrapper,
-reg__120: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__8197: APBGpsBlock__GCB1,
-logic__1424: VCU118RocketSystem__GC0,
-TLFragmenter_1: RocketTile__GCB0,
-logic__6608: VCU118RocketSystem__GC0,
-logic__4529: RocketTile__GCB0,
-logic__1490: RocketTile__GCB0,
-case__335: DCache,
-logic__4670: RocketTile__GCB0,
-logic__5235: RocketTile__GCB0,
-logic__47: genesys2_rocket_top__GC0,
-case__1166: APBGpsBlock__GCB1,
-muxpart__89: FPU__GB2,
-reg__350: RocketTile__GCB0,
-logic__4260: FPU__GB2,
-logic__242: VCU118RocketSystem__GC0,
-MulAddRecFNToRaw_postMul_1: FPU__GB1,
-logic__7410: VCU118RocketSystem__GC0,
-muxpart__207: APBGpsBlock__GCB0,
-logic__8635: tracking_wrapper,
-datapath__21: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__1431: tracking_wrapper,
-logic__1731: DCache,
-logic__8533: tracking_wrapper,
-logic__9196: APBGpsBlock__GCB0,
-logic__6167: VCU118RocketSystem__GC0,
-reg__1015: APBGpsBlock__GCB1,
-reg__624: RocketTile__GCB0,
-logic__2659: RocketTile__GCB0,
-logic__6801: VCU118RocketSystem__GC0,
-reg__549: FPU__GB1,
-datapath__528: APBGpsBlock__GCB1,
-TLBusBypassBar: VCU118RocketSystem__GC0,
-reg__678: RocketTile__GCB0,
-logic__7560: VCU118RocketSystem__GC0,
-logic__7061: VCU118RocketSystem__GC0,
-reg__1177: tracking_wrapper,
-muxpart__25: FPU__GB0,
-case__438: RocketTile__GCB0,
-datapath__111: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__1304: tracking_wrapper,
-logic__1355: VCU118RocketSystem__GC0,
-reg__541: FPU__GB1,
-logic__7168: VCU118RocketSystem__GC0,
-case__126: VCU118RocketSystem__GC0,
-logic__895: VCU118RocketSystem__GC0,
-logic__9140: APBGpsBlock__GCB0,
-reg__856: VCU118RocketSystem__GC0,
-datapath__592: APBGpsBlock__GCB1,
-case__1374: tracking_wrapper,
-case__1238: APBGpsBlock__GCB1,
-logic__5288: RocketTile__GCB0,
-datapath__306: FPU__GB2,
-case__372: DCache,
-case__1619: APBGpsBlock__GCB0,
-logic__4045: FPU__GB2,
-case__914: VCU118RocketSystem__GC0,
-datapath__74: VCU118RocketSystem__GC0,
-reg__409: FPU__GB1,
-sample_counter: APBGpsBlock__GCB0,
-PLICClockSinkDomain: VCU118RocketSystem__GC0,
-case__22: VCU118RocketSystem__GC0,
-logic__3265: FPU__GB2,
-reg__324: RocketTile__GCB0,
-logic__5885: RocketTile__GCB0,
-case__1468: tracking_wrapper,
-logic__724: VCU118RocketSystem__GC0,
-logic__6127: VCU118RocketSystem__GC0,
-datapath__580: APBGpsBlock__GCB1,
-logic__5535: RocketTile__GCB0,
-logic__4144: FPU__GB2,
-logic__8078: APBGpsBlock__GCB1,
-reg__455: FPU__GB1,
-datapath__559: APBGpsBlock__GCB1,
-logic__5372: RocketTile__GCB0,
-logic__4595: RocketTile__GCB0,
-logic__8814: tracking_wrapper,
-case__848: VCU118RocketSystem__GC0,
-logic__6183: VCU118RocketSystem__GC0,
-reg__1315: tracking_wrapper,
-logic__3850: FPU__GB1,
-logic__6128: VCU118RocketSystem__GC0,
-case__393: RocketTile__GCB0,
-case__741: RocketTile__GCB0,
-logic__6985: VCU118RocketSystem__GC0,
-logic__4199: FPU__GB2,
-reg__170: VCU118RocketSystem__GC0,
-reg__1093: APBGpsBlock__GCB1,
-logic__5277: RocketTile__GCB0,
-logic__6029: RocketTile__GCB0,
-logic__6430: VCU118RocketSystem__GC0,
-logic__929: VCU118RocketSystem__GC0,
-case__410: RocketTile__GCB0,
-case__754: RocketTile__GCB0,
-logic__8476: tracking_wrapper,
-logic__4741: RocketTile__GCB0,
-logic__6925: VCU118RocketSystem__GC0,
-reg__915: VCU118RocketSystem__GC0,
-logic__3956: FPU__GB2, FPU__GB1,
-logic__4599: RocketTile__GCB0,
-case__1532: APBGpsBlock__GCB0,
-case__572: FPU__GB2,
-case__269: VCU118RocketSystem__GC0,
-keep__34: APBGpsBlock__GCB0,
-logic__9130: APBGpsBlock__GCB0,
-case__315: DCache,
-logic__5084: RocketTile__GCB0,
-reg__626: RocketTile__GCB0,
-logic__3867: FPU__GB1,
-logic__3505: FPU__GB2,
-datapath__631: tracking_wrapper,
-logic__6670: VCU118RocketSystem__GC0,
-case__181: VCU118RocketSystem__GC0,
-datapath__120: VCU118RocketSystem__GC0,
-reg__1147: tracking_wrapper,
-case__787: VCU118RocketSystem__GC0,
-case__1442: tracking_wrapper,
-logic__7084: VCU118RocketSystem__GC0,
-logic__6641: VCU118RocketSystem__GC0,
-reg__43: VCU118RocketSystem__GC0,
-logic__2360: RocketTile__GCB0,
-keep__6: tracking_wrapper,
-case__365: DCache,
-logic__7888: APBGpsBlock__GCB1,
-logic__3931: FPU__GB2, FPU__GB1,
-reg__177: VCU118RocketSystem__GC0,
-logic__1577: DCache,
-logic__7411: VCU118RocketSystem__GC0,
-logic__8940: APBGpsBlock__GCB0,
-datapath__124: VCU118RocketSystem__GC0,
-cordic_atan_one_stage: tracking_wrapper,
-case__891: VCU118RocketSystem__GC0,
-reg__14: genesys2_rocket_top__GC0,
-reg__980: VCU118RocketSystem__GC0,
-logic__9297: APBGpsBlock__GCB0,
-logic__6681: VCU118RocketSystem__GC0,
-logic__686: VCU118RocketSystem__GC0,
-reg__1062: APBGpsBlock__GCB1,
-datapath__281: RocketTile__GCB0,
-logic__2624: RocketTile__GCB0,
-datapath__350: FPU__GB1,
-case__640: RocketTile__GCB0,
-logic__6997: VCU118RocketSystem__GC0,
-logic__5955: RocketTile__GCB0,
-logic__7664: VCU118RocketSystem__GC0,
-logic__533: VCU118RocketSystem__GC0,
-logic__5458: RocketTile__GCB0,
-logic__6898: VCU118RocketSystem__GC0,
-case__347: DCache,
-logic__9289: APBGpsBlock__GCB0,
-logic__1842: RocketTile__GCB0, DCache,
-case__563: FPU__GB2,
-logic__7587: VCU118RocketSystem__GC0,
-logic__4232: FPU__GB2,
-datapath__249: DCache,
-logic__5284: RocketTile__GCB0,
-datapath__569: APBGpsBlock__GCB1,
-logic__6671: VCU118RocketSystem__GC0,
-logic__6125: VCU118RocketSystem__GC0,
-logic__7787: APBGpsBlock__GCB1,
-reg__646: RocketTile__GCB0,
-case__449: FPU__GB1,
-datapath__674: tracking_wrapper,
-logic__2167: DCache,
-logic__1335: VCU118RocketSystem__GC0,
-muxpart__309: APBGpsBlock__GCB0,
-reg__957: VCU118RocketSystem__GC0,
-logic__6780: VCU118RocketSystem__GC0,
-logic__9152: APBGpsBlock__GCB0,
-reg__483: FPU__GB1,
-RecFNToIN_1: FPU__GB2,
-reg__100: VCU118RocketSystem__GC0,
-case__487: FPU__GB2,
-logic__5910: RocketTile__GCB0,
-logic__3358: FPU__GB2,
-case__1471: tracking_wrapper,
-case__686: RocketTile__GCB0,
-datapath__417: RocketTile__GCB0,
-datapath__565: APBGpsBlock__GCB1,
-logic__8427: tracking_wrapper,
-logic__6305: VCU118RocketSystem__GC0,
-logic__5428: RocketTile__GCB0,
-logic__2990: FPU__GB2, FPU__GB1,
-logic__22: genesys2_rocket_top__GC0,
-reg__901: VCU118RocketSystem__GC0,
-logic__725: VCU118RocketSystem__GC0,
-logic__6784: VCU118RocketSystem__GC0,
-case__401: RocketTile__GCB0,
-logic__3682: FPU__GB1,
-case__1462: tracking_wrapper,
-datapath__738: TLToAPB,
-logic__4758: RocketTile__GCB0,
-logic__7226: VCU118RocketSystem__GC0,
-logic__2842: FPU__GB1,
-case__1620: APBGpsBlock__GCB0,
-logic__3642: FPU__GB1,
-logic__2248: DCache,
-case__254: VCU118RocketSystem__GC0,
-datapath__65: VCU118RocketSystem__GC0,
-FPU__GB0: FPU__GB0,
-case__251: VCU118RocketSystem__GC0,
-case__942: VCU118RocketSystem__GC0,
-logic__6176: VCU118RocketSystem__GC0,
-logic__6202: VCU118RocketSystem__GC0,
-logic__4906: RocketTile__GCB0,
-logic__7613: VCU118RocketSystem__GC0,
-muxpart__52: FPU__GB0,
-case__444: RocketTile__GCB0,
-reg__1059: APBGpsBlock__GCB1,
-logic__2094: DCache,
-case__539: FPU__GB2,
-datapath__570: APBGpsBlock__GCB1,
-logic__5344: RocketTile__GCB0,
-logic__6446: VCU118RocketSystem__GC0,
-datapath__152: VCU118RocketSystem__GC0,
-logic__371: VCU118RocketSystem__GC0,
-logic__1273: VCU118RocketSystem__GC0,
-logic__5728: RocketTile__GCB0,
-logic__1380: VCU118RocketSystem__GC0,
-reg__582: RocketTile__GCB0,
-case__609: FPU__GB1,
-logic__914: VCU118RocketSystem__GC0,
-reg__132: VCU118RocketSystem__GC0,
-muxpart__23: FPU__GB0,
-datapath__106: VCU118RocketSystem__GC0,
-case__1560: APBGpsBlock__GCB0,
-sample_align: APBGpsBlock__GCB0,
-logic__4364: FPU__GB1,
-datapath__197: VCU118RocketSystem__GC0,
-extrom__1: APBGpsBlock__GCB1,
-case__733: RocketTile__GCB0,
-logic__8319: tracking_wrapper,
-logic__6189: VCU118RocketSystem__GC0,
-case__1202: APBGpsBlock__GCB1,
-logic__4932: RocketTile__GCB0,
-reg__465: FPU__GB1,
-case__1551: APBGpsBlock__GCB0,
-logic__3638: FPU__GB1,
-logic__8292: tracking_wrapper,
-logic__4223: FPU__GB2,
-datapath__555: APBGpsBlock__GCB1,
-case__1373: tracking_wrapper,
-logic__8391: tracking_wrapper,
-logic__4585: RocketTile__GCB0,
-logic__1827: DCache,
-case__526: FPU__GB2, FPU__GB1,
-reg__912: VCU118RocketSystem__GC0,
-logic__2962: FPU__GB1,
-divider: tracking_wrapper,
-case__576: FPU__GB1,
-reg__353: RocketTile__GCB0,
-datapath__279: RocketTile__GCB0,
-case__578: FPU__GB1,
-logic__7716: APBGpsBlock__GCB1,
-reg__561: FPU__GB1,
-case__468: FPU__GB2,
-logic__276: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7991: APBGpsBlock__GCB1,
-case__1109: APBGpsBlock__GCB1,
-case__1440: tracking_wrapper,
-logic__8420: tracking_wrapper,
-logic__4581: RocketTile__GCB0,
-logic__518: VCU118RocketSystem__GC0,
-case__57: VCU118RocketSystem__GC0,
-case__556: FPU__GB2,
-logic__7748: APBGpsBlock__GCB1,
-reg__778: TilePRCIDomain__GC0,
-case__175: VCU118RocketSystem__GC0,
-reg__1087: APBGpsBlock__GCB1,
-logic__5514: RocketTile__GCB0,
-reg__1276: tracking_wrapper,
-reg__183: VCU118RocketSystem__GC0,
-reg__77: VCU118RocketSystem__GC0,
-logic__5343: RocketTile__GCB0,
-reg__330: RocketTile__GCB0,
-case__1371: tracking_wrapper,
-logic__241: VCU118RocketSystem__GC0,
-case__1554: APBGpsBlock__GCB0,
-logic__3562: FPU__GB1,
-logic__9197: APBGpsBlock__GCB0,
-reg__267: DCache,
-reg__261: DCache,
-logic__1512: RocketTile__GCB0,
-logic__4675: RocketTile__GCB0,
-logic__2991: FPU__GB2, FPU__GB1,
-reg__1285: tracking_wrapper,
-case__150: VCU118RocketSystem__GC0,
-logic__7478: VCU118RocketSystem__GC0,
-case__1276: APBGpsBlock__GCB1,
-logic__5536: RocketTile__GCB0,
-logic__4251: FPU__GB2,
-case__166: VCU118RocketSystem__GC0,
-logic__8903: tracking_wrapper,
-logic__5338: RocketTile__GCB0,
-case__302: RocketTile__GCB0,
-logic__3180: FPU__GB2,
-logic__2260: DCache,
-datapath__159: VCU118RocketSystem__GC0,
-datapath__673: tracking_wrapper,
-logic__2240: DCache,
-logic__2010: DCache,
-logic__3256: FPU__GB2,
-reg__597: RocketTile__GCB0,
-logic__1039: VCU118RocketSystem__GC0,
-logic__5954: RocketTile__GCB0,
-logic__3851: FPU__GB1,
-logic__1216: VCU118RocketSystem__GC0,
-logic__8931: APBGpsBlock__GCB0,
-case__575: FPU__GB1,
-TLFIFOFixer_1: VCU118RocketSystem__GC0,
-logic__2498: RocketTile__GCB0,
-logic__6837: VCU118RocketSystem__GC0,
-reg__32: VCU118RocketSystem__GC0,
-datapath__321: FPU__GB2,
-logic__2118: DCache,
-reg__1456: TLToAPB,
-logic__3327: FPU__GB2,
-reg__793: VCU118RocketSystem__GC0,
-logic__2090: DCache,
-reg__576: FPU__GB1,
-logic__6599: VCU118RocketSystem__GC0,
-case__1093: APBGpsBlock__GCB1,
-logic__4598: RocketTile__GCB0,
-logic__6342: VCU118RocketSystem__GC0,
-logic__8150: APBGpsBlock__GCB1,
-case__325: DCache,
-case__756: RocketTile__GCB0,
-reg__969: VCU118RocketSystem__GC0,
-case__1491: tracking_wrapper,
-logic__1224: VCU118RocketSystem__GC0,
-case__390: RocketTile__GCB0,
-logic__628: VCU118RocketSystem__GC0,
-logic__6844: VCU118RocketSystem__GC0,
-case__817: VCU118RocketSystem__GC0,
-logic__3741: FPU__GB1,
-case__894: VCU118RocketSystem__GC0,
-logic__5313: RocketTile__GCB0,
-reg__1060: APBGpsBlock__GCB1,
-case__845: VCU118RocketSystem__GC0,
-logic__6292: VCU118RocketSystem__GC0,
-logic__4960: RocketTile__GCB0,
-case__1517: tracking_wrapper,
-logic__4046: FPU__GB2,
-logic__6068: RocketTile__GCB0,
-case__253: VCU118RocketSystem__GC0,
-case__512: FPU__GB1,
-logic__7670: VCU118RocketSystem__GC0,
-case__277: VCU118RocketSystem__GC0,
-logic__4172: FPU__GB2,
-case__902: VCU118RocketSystem__GC0,
-logic__5727: RocketTile__GCB0,
-reg__948: VCU118RocketSystem__GC0,
-logic__4893: RocketTile__GCB0,
-reg__280: DCache,
-logic__2417: RocketTile__GCB0,
-reg__38: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__1171: APBGpsBlock__GCB1,
-logic__4252: FPU__GB2,
-counter__36: APBGpsBlock__GCB0,
-reg__631: RocketTile__GCB0,
-case__1224: APBGpsBlock__GCB1,
-logic__8607: tracking_wrapper,
-reg__475: FPU__GB1,
-logic__7586: VCU118RocketSystem__GC0,
-case__358: DCache,
-logic__7905: APBGpsBlock__GCB1,
-reg__1017: APBGpsBlock__GCB1,
-logic__7725: APBGpsBlock__GCB1,
-logic__6000: RocketTile__GCB0,
-case__1222: APBGpsBlock__GCB1,
-datapath__435: RocketTile__GCB0,
-datapath__315: FPU__GB2,
-reg__673: RocketTile__GCB0,
-logic__6662: VCU118RocketSystem__GC0,
-reg__1343: APBGpsBlock__GCB0,
-logic__5494: RocketTile__GCB0,
-case__709: RocketTile__GCB0,
-logic__6848: VCU118RocketSystem__GC0,
-logic__195: VCU118RocketSystem__GC0,
-reg__493: FPU__GB1,
-logic__341: VCU118RocketSystem__GC0,
-reg__273: DCache,
-logic__5316: RocketTile__GCB0,
-logic__9292: APBGpsBlock__GCB0,
-case__1019: VCU118RocketSystem__GC0,
-logic__3880: FPU__GB1,
-logic__8217: APBGpsBlock__GCB1,
-datapath__576: APBGpsBlock__GCB1,
-logic__3869: FPU__GB1,
-logic__1751: DCache,
-logic__3531: FPU__GB2,
-logic__9194: APBGpsBlock__GCB0,
-logic__865: VCU118RocketSystem__GC0,
-logic__9337: APBGpsBlock__GCB0,
-datapath__414: RocketTile__GCB0,
-logic__8450: tracking_wrapper,
-logic__2706: FPU__GB1,
-Repeater_TLBundleA_a28d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__8346: tracking_wrapper,
-logic__5511: RocketTile__GCB0,
-reg__1329: tracking_wrapper,
-logic__2437: RocketTile__GCB0,
-reg__89: VCU118RocketSystem__GC0,
-case__304: RocketTile__GCB0,
-datapath__699: APBGpsBlock__GCB0,
-case__1558: APBGpsBlock__GCB0,
-reg__991: VCU118RocketSystem__GC0,
-logic__991: VCU118RocketSystem__GC0,
-datapath__395: RocketTile__GCB0,
-datapath__63: VCU118RocketSystem__GC0,
-logic__6575: VCU118RocketSystem__GC0,
-datapath__623: tracking_wrapper,
-case__1618: APBGpsBlock__GCB0,
-logic__6682: VCU118RocketSystem__GC0,
-logic__4030: FPU__GB2,
-logic__3483: FPU__GB2,
-reg__59: VCU118RocketSystem__GC0,
-case__470: FPU__GB2,
-datapath__453: RocketTile__GCB0,
-case__773: RocketTile__GCB0,
-logic__82: genesys2_rocket_top__GC0,
-logic__1452: RocketTile__GCB0,
-logic__8067: APBGpsBlock__GCB1,
-case__18: genesys2_rocket_top__GC0,
-datapath__412: RocketTile__GCB0,
-logic__4555: RocketTile__GCB0,
-reg__125: VCU118RocketSystem__GC0,
-logic__6630: VCU118RocketSystem__GC0,
-reg__858: VCU118RocketSystem__GC0,
-ClockGroupAggregator_sbus: VCU118RocketSystem__GC0,
-reg__179: VCU118RocketSystem__GC0,
-logic__232: VCU118RocketSystem__GC0,
-case__28: VCU118RocketSystem__GC0,
-logic__540: VCU118RocketSystem__GC0,
-reg__291: RocketTile__GCB0,
-datapath__359: FPU__GB2, FPU__GB1,
-logic__4092: FPU__GB2,
-logic__9143: APBGpsBlock__GCB0,
-ram__3: VCU118RocketSystem__GC0,
-reg__1101: APBGpsBlock__GCB1,
-muxpart__61: FPU__GB0,
-case__389: RocketTile__GCB0,
-logic__5884: RocketTile__GCB0,
-logic__176: VCU118RocketSystem__GC0,
-logic__502: VCU118RocketSystem__GC0,
-reg__28: VCU118RocketSystem__GC0,
-reg__723: RocketTile__GCB0,
-case__585: FPU__GB2,
-muxpart__86: FPU__GB1,
-rf_31x64: RocketTile__GCB0,
-reg__535: FPU__GB1,
-logic__1601: DCache,
-case__959: VCU118RocketSystem__GC0,
-logic__3234: FPU__GB2,
-logic__6642: VCU118RocketSystem__GC0,
-logic__4742: RocketTile__GCB0,
-datapath__175: VCU118RocketSystem__GC0,
-reg__581: RocketTile__GCB0,
-logic__2040: DCache,
-case__116: VCU118RocketSystem__GC0,
-case__439: RocketTile__GCB0,
-logic__1671: DCache,
-logic__7970: APBGpsBlock__GCB1,
-case__690: RocketTile__GCB0,
-case__1616: APBGpsBlock__GCB0,
-logic__9356: TLToAPB,
-reg__344: RocketTile__GCB0,
-reg__918: VCU118RocketSystem__GC0,
-logic__5513: RocketTile__GCB0,
-reg__578: FPU__GB1,
-reg__1167: tracking_wrapper,
-logic__1299: VCU118RocketSystem__GC0,
-logic__583: VCU118RocketSystem__GC0,
-datapath__94: VCU118RocketSystem__GC0,
-logic__1744: DCache,
-logic__531: VCU118RocketSystem__GC0,
-logic__2161: DCache,
-logic__1043: VCU118RocketSystem__GC0,
-logic__5389: RocketTile__GCB0,
-case__1029: VCU118RocketSystem__GC0,
-logic__4086: FPU__GB2,
-logic__853: VCU118RocketSystem__GC0,
-case__1303: APBGpsBlock__GCB1,
-logic__7529: VCU118RocketSystem__GC0,
-logic__3824: FPU__GB1,
-reg__169: VCU118RocketSystem__GC0,
-reg__11: genesys2_rocket_top__GC0,
-logic__5335: RocketTile__GCB0,
-logic__3732: FPU__GB1,
-logic__4155: FPU__GB2,
-logic__6315: VCU118RocketSystem__GC0,
-logic__6131: VCU118RocketSystem__GC0,
-dsp48e1__38: tracking_wrapper,
-logic__8577: tracking_wrapper,
-logic__1451: RocketTile__GCB0,
-case__1008: VCU118RocketSystem__GC0,
-logic__8178: APBGpsBlock__GCB1,
-logic__459: VCU118RocketSystem__GC0,
-datapath__314: FPU__GB2,
-logic__3845: FPU__GB1,
-logic__6414: VCU118RocketSystem__GC0,
-logic__3966: FPU__GB2, FPU__GB1,
-logic__8955: APBGpsBlock__GCB0,
-logic__1351: VCU118RocketSystem__GC0,
-reg__92: VCU118RocketSystem__GC0,
-datapath__5: genesys2_rocket_top__GC0,
-case__884: VCU118RocketSystem__GC0,
-RecFNToIN: FPU__GB2,
-logic__8088: APBGpsBlock__GCB1,
-logic__6027: RocketTile__GCB0,
-logic__3629: FPU__GB1,
-reg__298: RocketTile__GCB0,
-datapath__78: VCU118RocketSystem__GC0,
-logic__7602: VCU118RocketSystem__GC0,
-logic__71: genesys2_rocket_top__GC0,
-logic__6388: VCU118RocketSystem__GC0,
-logic__2897: FPU__GB1,
-logic__79: genesys2_rocket_top__GC0,
-case__400: RocketTile__GCB0,
-logic__7328: VCU118RocketSystem__GC0,
-logic__172: VCU118RocketSystem__GC0,
-logic__3823: FPU__GB1,
-logic__7625: VCU118RocketSystem__GC0,
-logic__7349: VCU118RocketSystem__GC0,
-logic__1068: VCU118RocketSystem__GC0,
-reg__615: RocketTile__GCB0,
-logic__5534: RocketTile__GCB0,
-datapath__418: RocketTile__GCB0,
-case__554: FPU__GB2,
-logic__5007: RocketTile__GCB0,
-logic__6186: VCU118RocketSystem__GC0,
-reg__517: FPU__GB2,
-reg__383: FPU__GB0,
-reg__935: VCU118RocketSystem__GC0,
-case__51: VCU118RocketSystem__GC0,
-logic__2963: FPU__GB1,
-case__460: FPU__GB2, FPU__GB1,
-logic__2057: DCache,
-logic__1026: VCU118RocketSystem__GC0,
-reg__567: FPU__GB1,
-logic__3213: FPU__GB2,
-logic__868: VCU118RocketSystem__GC0,
-datapath__562: APBGpsBlock__GCB1,
-reg__1137: tracking_wrapper,
-logic__5463: RocketTile__GCB0,
-logic__3557: FPU__GB1,
-logic__3612: FPU__GB1,
-logic__1663: DCache,
-logic__4756: RocketTile__GCB0,
-logic__4310: FPU__GB1,
-logic__8203: APBGpsBlock__GCB1,
-logic__8976: APBGpsBlock__GCB0,
-logic__2066: DCache,
-case__148: VCU118RocketSystem__GC0,
-PeripheryBus_cbus: VCU118RocketSystem__GC0,
-reg__329: RocketTile__GCB0,
-APBGpsBlock__GCB0: APBGpsBlock__GCB0,
-logic__5052: RocketTile__GCB0,
-reg__411: FPU__GB1,
-logic__3096: FPU__GB2,
-reg__207: VCU118RocketSystem__GC0,
-case__169: VCU118RocketSystem__GC0,
-reg__76: VCU118RocketSystem__GC0,
-reg__715: RocketTile__GCB0,
-logic__3637: FPU__GB1,
-logic__3815: FPU__GB1,
-reg__1295: tracking_wrapper,
-logic__8592: tracking_wrapper,
-logic__7355: VCU118RocketSystem__GC0,
-logic__1387: VCU118RocketSystem__GC0,
-case__193: VCU118RocketSystem__GC0,
-case__1092: APBGpsBlock__GCB1,
-logic__8512: tracking_wrapper,
-reg__1268: tracking_wrapper,
-reg__653: RocketTile__GCB0,
-case__217: VCU118RocketSystem__GC0,
-case__878: VCU118RocketSystem__GC0,
-logic__6688: VCU118RocketSystem__GC0,
-ram_2x10: VCU118RocketSystem__GC0,
-logic__4513: FPU__GB1,
-case__993: VCU118RocketSystem__GC0,
-muxpart__47: FPU__GB0,
-logic__8817: tracking_wrapper,
-logic__6918: VCU118RocketSystem__GC0,
-logic__4826: RocketTile__GCB0,
-reg__369: RocketTile__GCB0,
-logic__3847: FPU__GB1,
-case__1609: APBGpsBlock__GCB0,
-logic__625: VCU118RocketSystem__GC0,
-logic__2708: FPU__GB1,
-case__1024: VCU118RocketSystem__GC0,
-logic__6407: VCU118RocketSystem__GC0,
-keep: APBGpsBlock__GCB1, tracking_wrapper,
-logic__571: VCU118RocketSystem__GC0,
-logic__883: VCU118RocketSystem__GC0,
-logic__1980: DCache,
-logic__5287: RocketTile__GCB0,
-logic__6750: VCU118RocketSystem__GC0,
-reg__1258: tracking_wrapper,
-logic__685: VCU118RocketSystem__GC0,
-logic__1398: VCU118RocketSystem__GC0,
-reg__103: VCU118RocketSystem__GC0,
-reg__1076: APBGpsBlock__GCB1,
-case__1088: APBGpsBlock__GCB1,
-muxpart__304: APBGpsBlock__GCB0,
-datapath__479: VCU118RocketSystem__GC0,
-case__1091: APBGpsBlock__GCB1,
-logic__70: genesys2_rocket_top__GC0,
-reg__1183: tracking_wrapper,
-logic__4582: RocketTile__GCB0,
-logic__4328: FPU__GB1,
-logic__3508: FPU__GB2,
-logic__363: VCU118RocketSystem__GC0,
-reg__1364: APBGpsBlock__GCB0,
-reg__321: RocketTile__GCB0,
-case__805: VCU118RocketSystem__GC0,
-logic__5716: RocketTile__GCB0,
-logic__580: VCU118RocketSystem__GC0,
-datapath__572: APBGpsBlock__GCB1,
-case__1480: tracking_wrapper,
-logic__8970: APBGpsBlock__GCB0,
-logic__6291: VCU118RocketSystem__GC0,
-logic__148: VCU118RocketSystem__GC0,
-datapath__428: RocketTile__GCB0,
-ram: VCU118RocketSystem__GC0,
-logic__6646: VCU118RocketSystem__GC0,
-reg__1362: APBGpsBlock__GCB0,
-logic__5937: RocketTile__GCB0,
-reg__895: VCU118RocketSystem__GC0,
-reg__112: VCU118RocketSystem__GC0,
-reg__258: DCache,
-logic__2132: DCache,
-muxpart__231: tracking_wrapper,
-case__1104: APBGpsBlock__GCB1,
-dsp48e1__22: APBGpsBlock__GCB1,
-logic__6787: VCU118RocketSystem__GC0,
-case__868: VCU118RocketSystem__GC0,
-case__1661: APBGpsBlock__GCB0,
-datapath__229: VCU118RocketSystem__GC0,
-logic__4855: RocketTile__GCB0,
-logic__2120: DCache,
-reg__400: FPU__GB0,
-logic__5909: RocketTile__GCB0,
-logic__938: VCU118RocketSystem__GC0,
-logic__659: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2080: DCache,
-logic__987: VCU118RocketSystem__GC0,
-reg__1110: APBGpsBlock__GCB1,
-logic__9180: APBGpsBlock__GCB0,
-datapath__681: tracking_wrapper,
-case__370: DCache,
-logic__4530: RocketTile__GCB0,
-logic__4998: RocketTile__GCB0,
-case__338: DCache,
-keep__2: tracking_wrapper,
-case__96: VCU118RocketSystem__GC0,
-logic__8539: tracking_wrapper,
-logic__2938: FPU__GB1,
-reg__728: RocketTile__GCB0,
-reg__944: VCU118RocketSystem__GC0,
-case__1: genesys2_rocket_top__GC0,
-logic__4237: FPU__GB2,
-reg__780: VCU118RocketSystem__GC0,
-logic__1324: VCU118RocketSystem__GC0,
-logic__1099: VCU118RocketSystem__GC0,
-logic__3863: FPU__GB1,
-muxpart__45: FPU__GB0,
-case__903: VCU118RocketSystem__GC0,
-logic__6268: VCU118RocketSystem__GC0,
-reg__964: VCU118RocketSystem__GC0,
-logic__5461: RocketTile__GCB0,
-reg__302: RocketTile__GCB0,
-logic__6588: VCU118RocketSystem__GC0,
-logic__600: VCU118RocketSystem__GC0,
-logic__2602: RocketTile__GCB0,
-muxpart__77: FPU__GB0,
-case__725: RocketTile__GCB0,
-case__1405: tracking_wrapper,
-datapath__618: APBGpsBlock__GCB1,
-logic__3680: FPU__GB1,
-logic__4672: RocketTile__GCB0,
-reg__1296: tracking_wrapper,
-logic: genesys2_rocket_top__GC0,
-logic__8388: tracking_wrapper,
-reg__749: RocketTile__GCB0,
-logic__4309: FPU__GB1,
-logic__4546: RocketTile__GCB0,
-logic__6187: VCU118RocketSystem__GC0,
-butterfly: APBGpsBlock__GCB1,
-reg__612: RocketTile__GCB0,
-reg__1293: tracking_wrapper,
-logic__5410: RocketTile__GCB0,
-logic__7093: VCU118RocketSystem__GC0,
-SBToTL: VCU118RocketSystem__GC0,
-logic__4632: RocketTile__GCB0,
-logic__4889: RocketTile__GCB0,
-logic__8816: tracking_wrapper,
-logic__2347: RocketTile__GCB0,
-logic__1255: VCU118RocketSystem__GC0,
-case__745: RocketTile__GCB0,
-logic__3363: FPU__GB2,
-reg__461: FPU__GB1,
-logic__1716: DCache,
-logic__5064: RocketTile__GCB0,
-datapath__222: VCU118RocketSystem__GC0,
-case__1035: VCU118RocketSystem__GC0,
-case__1682: TLToAPB,
-reg__6: genesys2_rocket_top__GC0,
-logic__2191: DCache,
-logic__6136: VCU118RocketSystem__GC0,
-logic__4634: RocketTile__GCB0,
-reg__1457: VCU118RocketSystem__GC0,
-logic__6809: VCU118RocketSystem__GC0,
-datapath__352: FPU__GB1,
-case__52: VCU118RocketSystem__GC0,
-reg__1324: tracking_wrapper,
-logic__3743: FPU__GB1,
-logic__1913: RocketTile__GCB0, DCache,
-case__1602: APBGpsBlock__GCB0,
-logic__8472: tracking_wrapper,
-logic__4315: FPU__GB1,
-logic__645: VCU118RocketSystem__GC0,
-rom__3: APBGpsBlock__GCB1,
-reg__584: RocketTile__GCB0,
-reg__299: RocketTile__GCB0,
-datapath__317: FPU__GB2,
-case__639: RocketTile__GCB0,
-logic__1783: DCache,
-dsp48e1__7: APBGpsBlock__GCB1,
-logic__4091: FPU__GB2,
-reg__867: VCU118RocketSystem__GC0,
-datapath__26: VCU118RocketSystem__GC0,
-datapath__523: VCU118RocketSystem__GC0,
-logic__5356: RocketTile__GCB0,
-reg__1232: tracking_wrapper,
-logic__7304: VCU118RocketSystem__GC0,
-logic__3422: FPU__GB2,
-case__1666: APBGpsBlock__GCB0,
-logic__8339: tracking_wrapper,
-logic__78: genesys2_rocket_top__GC0,
-keep__9: APBGpsBlock__GCB0,
-reg__35: VCU118RocketSystem__GC0,
-reg__927: VCU118RocketSystem__GC0,
-datapath__153: VCU118RocketSystem__GC0,
-logic__4087: FPU__GB2,
-logic__5963: RocketTile__GCB0,
-datapath__730: APBGpsBlock__GCB0,
-logic__3264: FPU__GB2,
-logic__6210: VCU118RocketSystem__GC0,
-logic__6123: VCU118RocketSystem__GC0,
-logic__4329: FPU__GB1,
-datapath__105: VCU118RocketSystem__GC0,
-logic__5455: RocketTile__GCB0,
-reg__1417: APBGpsBlock__GCB0,
-acq_peak_srch: APBGpsBlock__GCB1,
-reg__681: RocketTile__GCB0,
-logic__8061: APBGpsBlock__GCB1,
-logic__1944: DCache,
-logic__2119: DCache,
-dsp48e1__4: APBGpsBlock__GCB1,
-dsp48e1__5: APBGpsBlock__GCB1,
-datapath__293: FPU__GB1,
-logic__1494: RocketTile__GCB0,
-reg__290: DCache,
-logic__3858: FPU__GB1,
-case__457: FPU__GB2, FPU__GB1,
-case__596: FPU__GB1,
-logic__7195: VCU118RocketSystem__GC0,
-logic__694: VCU118RocketSystem__GC0,
-datapath__216: VCU118RocketSystem__GC0,
-reg__339: RocketTile__GCB0,
-logic__2566: RocketTile__GCB0,
-logic__3736: FPU__GB1,
-keep__12: APBGpsBlock__GCB0,
-logic__3936: FPU__GB2, FPU__GB1,
-logic__6427: VCU118RocketSystem__GC0,
-logic__939: VCU118RocketSystem__GC0,
-case__964: VCU118RocketSystem__GC0,
-logic__6396: VCU118RocketSystem__GC0,
-muxpart__310: APBGpsBlock__GCB0,
-logic__7372: VCU118RocketSystem__GC0,
-logic__1821: DCache,
-logic__8722: tracking_wrapper,
-datapath__624: tracking_wrapper,
-case__292: RocketTile__GCB0,
-logic__2952: FPU__GB1,
-datapath__340: FPU__GB1,
-case__176: VCU118RocketSystem__GC0,
-logic__2479: RocketTile__GCB0,
-logic__5459: RocketTile__GCB0,
-datapath__675: tracking_wrapper,
-logic__2199: DCache,
-case__524: FPU__GB1,
-case__963: VCU118RocketSystem__GC0,
-logic__4915: RocketTile__GCB0,
-logic__3877: FPU__GB1,
-case__1344: tracking_wrapper,
-DivSqrtRawFN_small: FPU__GB2,
-case__842: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a29d64s2k1z3u_3: VCU118RocketSystem__GC0,
-logic__3259: FPU__GB2,
-logic__4608: RocketTile__GCB0,
-reg__1172: tracking_wrapper,
-case__1607: APBGpsBlock__GCB0,
-logic__2704: FPU__GB1,
-logic__9157: APBGpsBlock__GCB0,
-logic__4671: RocketTile__GCB0,
-case__130: VCU118RocketSystem__GC0,
-Queue1_TLBundleA_a29d32s7k1z2u: TLToAPB,
-case__465: FPU__GB2, FPU__GB1,
-reg__679: RocketTile__GCB0,
-case__1636: APBGpsBlock__GCB0,
-logic__4411: FPU__GB1,
-case__436: RocketTile__GCB0,
-muxpart__32: FPU__GB0,
-reg__164: VCU118RocketSystem__GC0,
-case__35: VCU118RocketSystem__GC0,
-datapath__353: FPU__GB1,
-case__247: VCU118RocketSystem__GC0,
-logic__8765: tracking_wrapper,
-logic__2267: DCache,
-datapath__289: FPU__GB1,
-rom__5: APBGpsBlock__GCB1,
-reg__647: RocketTile__GCB0,
-datapath__29: VCU118RocketSystem__GC0,
-logic__387: VCU118RocketSystem__GC0,
-logic__1050: VCU118RocketSystem__GC0,
-case__164: VCU118RocketSystem__GC0,
-logic__451: VCU118RocketSystem__GC0,
-logic__2996: FPU__GB2, FPU__GB1,
-case__1036: VCU118RocketSystem__GC0,
-logic__8815: tracking_wrapper,
-logic__4542: RocketTile__GCB0,
-logic__7348: VCU118RocketSystem__GC0,
-reg__375: FPU__GB0,
-logic__5308: RocketTile__GCB0,
-reg__924: VCU118RocketSystem__GC0,
-case__1141: APBGpsBlock__GCB1,
-reg__1123: APBGpsBlock__GCB0,
-dsp48e1__6: APBGpsBlock__GCB1,
-logic__1836: DCache,
-logic__6101: RocketTile__GCB0,
-logic__705: VCU118RocketSystem__GC0,
-reg__727: RocketTile__GCB0,
-datapath__695: APBGpsBlock__GCB0,
-counter__12: APBGpsBlock__GCB1,
-logic__3133: FPU__GB2,
-logic__3509: FPU__GB2,
-logic__6409: VCU118RocketSystem__GC0,
-logic__3781: FPU__GB1,
-logic__8733: tracking_wrapper,
-case__1051: VCU118RocketSystem__GC0,
-reg__209: VCU118RocketSystem__GC0,
-logic__748: VCU118RocketSystem__GC0,
-reg__263: DCache,
-logic__3876: FPU__GB1,
-logic__6321: VCU118RocketSystem__GC0,
-datapath__230: VCU118RocketSystem__GC0,
-logic__7124: VCU118RocketSystem__GC0,
-muxpart__75: FPU__GB0,
-reg__756: RocketTile__GCB0,
-case__591: FPU__GB1,
-mult_30_25_55: tracking_wrapper,
-logic__2429: RocketTile__GCB0,
-reg__607: RocketTile__GCB0,
-case__904: VCU118RocketSystem__GC0,
-logic__6422: VCU118RocketSystem__GC0,
-logic__4927: RocketTile__GCB0,
-datapath__630: tracking_wrapper,
-reg__692: RocketTile__GCB0,
-logic__2705: FPU__GB1,
-reg__744: RocketTile__GCB0,
-case__612: FPU__GB1,
-case__1627: APBGpsBlock__GCB0,
-logic__5933: RocketTile__GCB0,
-reg__936: VCU118RocketSystem__GC0,
-logic__2058: DCache,
-datapath__467: TilePRCIDomain__GC0,
-case__936: VCU118RocketSystem__GC0,
-logic__4317: FPU__GB1,
-case__853: VCU118RocketSystem__GC0,
-logic__5879: RocketTile__GCB0,
-extram__6: APBGpsBlock__GCB1,
-datapath__384: FPU__GB1,
-reg__13: genesys2_rocket_top__GC0,
-logic__7067: VCU118RocketSystem__GC0,
-logic__8506: tracking_wrapper,
-ram_2x99: VCU118RocketSystem__GC0,
-signinv__2: APBGpsBlock__GCB1,
-logic__5085: RocketTile__GCB0,
-reg__380: FPU__GB0,
-reg__180: VCU118RocketSystem__GC0,
-case__1087: APBGpsBlock__GCB1,
-logic__6099: RocketTile__GCB0,
-logic__5487: RocketTile__GCB0,
-logic__7162: VCU118RocketSystem__GC0,
-logic__3263: FPU__GB2,
-logic__3073: FPU__GB1,
-reg__754: RocketTile__GCB0,
-logic__4926: RocketTile__GCB0,
-reg__536: FPU__GB1,
-case__64: VCU118RocketSystem__GC0,
-datapath__657: tracking_wrapper,
-logic__5462: RocketTile__GCB0,
-logic__6213: VCU118RocketSystem__GC0,
-datapath__687: tracking_wrapper,
-reg__1138: tracking_wrapper,
-logic__9173: APBGpsBlock__GCB0,
-logic__6931: VCU118RocketSystem__GC0,
-reg__940: VCU118RocketSystem__GC0,
-case__1221: APBGpsBlock__GCB1,
-logic__5505: RocketTile__GCB0,
-datapath__50: VCU118RocketSystem__GC0,
-case__93: VCU118RocketSystem__GC0,
-case__816: VCU118RocketSystem__GC0,
-logic__984: VCU118RocketSystem__GC0,
-logic__2270: DCache,
-reg__9: genesys2_rocket_top__GC0,
-case__1411: tracking_wrapper,
-logic__1471: RocketTile__GCB0,
-logic__8707: tracking_wrapper,
-logic__411: VCU118RocketSystem__GC0,
-datapath__295: FPU__GB1,
-logic__7570: VCU118RocketSystem__GC0,
-logic__2410: RocketTile__GCB0,
-logic__4930: RocketTile__GCB0,
-case__598: FPU__GB1,
-logic__3838: FPU__GB1,
-reg__3: genesys2_rocket_top__GC0,
-datapath__277: RocketTile__GCB0,
-reg__351: RocketTile__GCB0,
-datapath__373: FPU__GB2,
-logic__3613: FPU__GB1,
-logic__759: VCU118RocketSystem__GC0,
-logic__3739: FPU__GB1,
-reg__847: VCU118RocketSystem__GC0,
-logic__7129: VCU118RocketSystem__GC0,
-logic__2334: DCache,
-logic__2616: RocketTile__GCB0,
-case__462: FPU__GB2, FPU__GB1,
-reg__287: DCache,
-case__1147: APBGpsBlock__GCB1,
-reg__1166: tracking_wrapper,
-logic__8257: APBGpsBlock__GCB0,
-reg__689: RocketTile__GCB0,
-datapath__504: VCU118RocketSystem__GC0,
-datapath__248: DCache,
-case__1606: APBGpsBlock__GCB0,
-reg__357: RocketTile__GCB0,
-case__1398: tracking_wrapper,
-reg__761: RocketTile__GCB0,
-case__1062: APBGpsBlock__GCB1,
-logic__786: VCU118RocketSystem__GC0,
-datapath__245: DCache,
-case__895: VCU118RocketSystem__GC0,
-logic__9160: APBGpsBlock__GCB0,
-INToRecFN: FPU__GB2,
-reg__919: VCU118RocketSystem__GC0,
-logic__1237: VCU118RocketSystem__GC0,
-logic__643: VCU118RocketSystem__GC0,
-APBGpsBlock__GCB1: APBGpsBlock__GCB1,
-reg__833: VCU118RocketSystem__GC0,
-case__300: RocketTile__GCB0,
-case__1481: tracking_wrapper,
-logic__2141: DCache,
-logic__318: VCU118RocketSystem__GC0,
-logic__467: VCU118RocketSystem__GC0,
-muxpart__42: FPU__GB0,
-logic__3585: FPU__GB1,
-datapath__361: FPU__GB2, FPU__GB1,
-logic__404: VCU118RocketSystem__GC0,
-datapath__684: tracking_wrapper,
-logic__820: VCU118RocketSystem__GC0,
-reg__995: VCU118RocketSystem__GC0,
-case__1441: tracking_wrapper,
-reg__12: genesys2_rocket_top__GC0,
-case__86: VCU118RocketSystem__GC0,
-logic__6800: VCU118RocketSystem__GC0,
-case__89: VCU118RocketSystem__GC0,
-reg__404: FPU__GB1,
-logic__6573: VCU118RocketSystem__GC0,
-logic__3789: FPU__GB1,
-reg__871: VCU118RocketSystem__GC0,
-reg__114: VCU118RocketSystem__GC0,
-logic__9166: APBGpsBlock__GCB0,
-logic__101: genesys2_rocket_top__GC0,
-logic__6296: VCU118RocketSystem__GC0,
-logic__3298: FPU__GB2,
-case__823: VCU118RocketSystem__GC0,
-case__614: RocketTile__GCB0,
-logic__2978: FPU__GB2, FPU__GB1,
-logic__3560: FPU__GB1,
-case__11: genesys2_rocket_top__GC0,
-logic__7423: VCU118RocketSystem__GC0,
-logic__8173: APBGpsBlock__GCB1,
-logic__2496: RocketTile__GCB0,
-logic__8451: tracking_wrapper,
-logic__6808: VCU118RocketSystem__GC0,
-logic__6562: VCU118RocketSystem__GC0,
-mult_46_15_61: APBGpsBlock__GCB1,
-logic__881: VCU118RocketSystem__GC0,
-logic__3310: FPU__GB2,
-logic__6781: VCU118RocketSystem__GC0,
-case__815: VCU118RocketSystem__GC0,
-reg__1126: APBGpsBlock__GCB0,
-logic__8348: tracking_wrapper,
-reg__641: RocketTile__GCB0,
-reg__773: RocketTile__GCB0,
-logic__7817: APBGpsBlock__GCB1,
-logic__8534: tracking_wrapper,
-logic__6387: VCU118RocketSystem__GC0,
-case__205: VCU118RocketSystem__GC0,
-reg__1180: tracking_wrapper,
-case__267: VCU118RocketSystem__GC0,
-reg__162: VCU118RocketSystem__GC0,
-case__529: FPU__GB2, FPU__GB1,
-muxpart__143: APBGpsBlock__GCB1,
-logic__3164: FPU__GB2,
-logic__6805: VCU118RocketSystem__GC0,
-logic__5666: RocketTile__GCB0,
-reg__1225: tracking_wrapper,
-reg__81: VCU118RocketSystem__GC0,
-datapath__343: FPU__GB1,
-reg__230: VCU118RocketSystem__GC0,
-reg__1026: APBGpsBlock__GCB1,
-reg__1250: tracking_wrapper,
-case__1427: tracking_wrapper,
-logic__2000: DCache,
-logic__3326: FPU__GB2,
-logic__7577: VCU118RocketSystem__GC0,
-logic__969: VCU118RocketSystem__GC0,
-logic__2997: FPU__GB2, FPU__GB1,
-case__828: VCU118RocketSystem__GC0,
-afe_top: APBGpsBlock__GCB0,
-logic__443: VCU118RocketSystem__GC0,
-reg__707: RocketTile__GCB0,
-datapath__93: VCU118RocketSystem__GC0,
-reg__1039: APBGpsBlock__GCB1,
-datapath__429: RocketTile__GCB0,
-reg__485: FPU__GB1,
-reg__41: VCU118RocketSystem__GC0,
-logic__243: VCU118RocketSystem__GC0,
-logic__3740: FPU__GB1,
-logic__3993: FPU__GB2, FPU__GB1,
-case__74: VCU118RocketSystem__GC0,
-case__1449: tracking_wrapper,
-reg__648: RocketTile__GCB0,
-logic__4083: FPU__GB2,
-logic__6609: VCU118RocketSystem__GC0,
-case__813: VCU118RocketSystem__GC0,
-logic__3811: FPU__GB1,
-reg__1400: APBGpsBlock__GCB0,
-logic__9145: APBGpsBlock__GCB0,
-datapath__174: VCU118RocketSystem__GC0,
-bram__parameterized0: APBGpsBlock__GCB1,
-logic__4588: RocketTile__GCB0,
-logic__9189: APBGpsBlock__GCB0,
-logic__5971: RocketTile__GCB0,
-reg__307: RocketTile__GCB0,
-logic__4708: RocketTile__GCB0,
-case__716: RocketTile__GCB0,
-dsp48e1__11: APBGpsBlock__GCB1,
-case__1377: tracking_wrapper,
-logic__3579: FPU__GB1,
-datapath__333: FPU__GB2,
-muxpart__67: FPU__GB0,
-reg__660: RocketTile__GCB0,
-logic__5274: RocketTile__GCB0,
-reg__629: RocketTile__GCB0,
-case__896: VCU118RocketSystem__GC0,
-logic__8180: APBGpsBlock__GCB1,
-reg__537: FPU__GB1,
-case__626: RocketTile__GCB0,
-datapath__355: FPU__GB1,
-mult_64_48_112: APBGpsBlock__GCB0,
-reg__195: VCU118RocketSystem__GC0,
-case__1136: APBGpsBlock__GCB1,
-counter__28: APBGpsBlock__GCB0,
-counter__25: tracking_wrapper,
-case__1549: APBGpsBlock__GCB0,
-logic__1301: VCU118RocketSystem__GC0,
-case__599: FPU__GB1,
-logic__7626: VCU118RocketSystem__GC0,
-logic__6673: VCU118RocketSystem__GC0,
-logic__6102: TilePRCIDomain__GC0,
-logic__2438: RocketTile__GCB0,
-logic__4550: RocketTile__GCB0,
-reg__907: VCU118RocketSystem__GC0,
-reg__266: DCache,
-logic__2635: RocketTile__GCB0,
-logic__4013: FPU__GB1,
-logic__9200: APBGpsBlock__GCB0,
-case__1061: APBGpsBlock__GCB1,
-ram__8: VCU118RocketSystem__GC0,
-logic__9162: APBGpsBlock__GCB0,
-logic__7495: VCU118RocketSystem__GC0,
-logic__6028: RocketTile__GCB0,
-logic__2104: DCache,
-logic__1884: RocketTile__GCB0, DCache,
-logic__6067: RocketTile__GCB0,
-reg__308: RocketTile__GCB0,
-datapath__545: APBGpsBlock__GCB1,
-case__1526: APBGpsBlock__GCB0,
-logic__7595: VCU118RocketSystem__GC0,
-reg__1045: APBGpsBlock__GCB1,
-case__859: VCU118RocketSystem__GC0,
-fft_radix_2__parameterized0: APBGpsBlock__GCB1,
-logic__8658: tracking_wrapper,
-logic__449: VCU118RocketSystem__GC0,
-logic__3206: FPU__GB2,
-case__1535: APBGpsBlock__GCB0,
-muxpart__107: RocketTile__GCB0,
-logic__5456: RocketTile__GCB0,
-logic__2714: FPU__GB1,
-logic__6593: VCU118RocketSystem__GC0,
-logic__316: VCU118RocketSystem__GC0,
-reg__1052: APBGpsBlock__GCB1,
-logic__3843: FPU__GB1,
-PMAChecker: RocketTile__GCB0, DCache,
-logic__3305: FPU__GB2,
-logic__8792: tracking_wrapper,
-logic__5286: RocketTile__GCB0,
-PeripheryBus_pbus: VCU118RocketSystem__GC0,
-case__1479: tracking_wrapper,
-logic__7420: VCU118RocketSystem__GC0,
-logic__6739: VCU118RocketSystem__GC0,
-logic__3885: FPU__GB1,
-logic__7367: VCU118RocketSystem__GC0,
-logic__1704: DCache,
-datapath__71: VCU118RocketSystem__GC0,
-logic__9366: TLToAPB,
-reg__1104: APBGpsBlock__GCB1,
-logic__7676: VCU118RocketSystem__GC0,
-logic__7661: VCU118RocketSystem__GC0,
-logic__2821: FPU__GB1,
-logic__2400: RocketTile__GCB0,
-logic__2604: RocketTile__GCB0,
-logic__385: VCU118RocketSystem__GC0,
-logic__5503: RocketTile__GCB0,
-logic__1429: VCU118RocketSystem__GC0,
-logic__6916: VCU118RocketSystem__GC0,
-logic__521: VCU118RocketSystem__GC0,
-logic__5662: RocketTile__GCB0,
-logic__821: VCU118RocketSystem__GC0,
-logic__9191: APBGpsBlock__GCB0,
-logic__4401: FPU__GB1,
-reg__117: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__3419: FPU__GB2,
-reg__955: VCU118RocketSystem__GC0,
-logic__6590: VCU118RocketSystem__GC0,
-reg__1067: APBGpsBlock__GCB1,
-logic__7733: APBGpsBlock__GCB1,
-keep__24: APBGpsBlock__GCB0,
-case__65: VCU118RocketSystem__GC0,
-logic__5339: RocketTile__GCB0,
-case__871: VCU118RocketSystem__GC0,
-logic__127: VCU118RocketSystem__GC0,
-case__238: VCU118RocketSystem__GC0,
-logic__623: VCU118RocketSystem__GC0,
-case__20: genesys2_rocket_top__GC0,
-reg__586: RocketTile__GCB0,
-datapath__396: RocketTile__GCB0,
-datapath__404: RocketTile__GCB0,
-datapath__722: APBGpsBlock__GCB0,
-case__342: DCache,
-logic__6048: RocketTile__GCB0,
-logic__6598: VCU118RocketSystem__GC0,
-logic__2254: DCache,
-reg__721: RocketTile__GCB0,
-logic__2311: DCache,
-datapath__560: APBGpsBlock__GCB1,
-logic__4838: RocketTile__GCB0,
-reg__938: VCU118RocketSystem__GC0,
-muxpart__43: FPU__GB0,
-logic__7342: VCU118RocketSystem__GC0,
-keep__22: APBGpsBlock__GCB0,
-logic__4023: FPU__GB2,
-case__1436: tracking_wrapper,
-logic__2930: FPU__GB1,
-logic__4338: FPU__GB1,
-logic__9142: APBGpsBlock__GCB0,
-case__158: VCU118RocketSystem__GC0,
-case__1304: APBGpsBlock__GCB1,
-datapath__266: RocketTile__GCB0,
-datapath__346: FPU__GB1,
-logic__2710: FPU__GB1,
-case__101: VCU118RocketSystem__GC0,
-counter__26: tracking_wrapper,
-Queue1_TLBundleA_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__3742: FPU__GB1,
-logic__5292: RocketTile__GCB0,
-case__617: RocketTile__GCB0,
-logic__1320: VCU118RocketSystem__GC0,
-case__1381: tracking_wrapper,
-logic__4839: RocketTile__GCB0,
-reg__185: VCU118RocketSystem__GC0,
-logic__8948: APBGpsBlock__GCB0,
-logic__3267: FPU__GB2,
-logic__6133: VCU118RocketSystem__GC0,
-logic__5247: RocketTile__GCB0,
-logic__4212: FPU__GB2,
-datapath__201: VCU118RocketSystem__GC0,
-logic__160: VCU118RocketSystem__GC0,
-reg__521: FPU__GB2,
-case__881: VCU118RocketSystem__GC0,
-logic__1054: VCU118RocketSystem__GC0,
-logic__1676: DCache,
-logic__6792: VCU118RocketSystem__GC0,
-case__500: FPU__GB2,
-logic__4316: FPU__GB1,
-logic__2697: FPU__GB1,
-logic__6304: VCU118RocketSystem__GC0,
-case__542: FPU__GB2,
-logic__2327: DCache,
-reg__829: VCU118RocketSystem__GC0,
-reg__1249: tracking_wrapper,
-logic__4072: FPU__GB2,
-reg__454: FPU__GB1,
-logic__4720: RocketTile__GCB0,
-reg__108: VCU118RocketSystem__GC0,
-case__476: FPU__GB2,
-logic__5395: RocketTile__GCB0,
-logic__4633: RocketTile__GCB0,
-case__804: VCU118RocketSystem__GC0,
-reg__1309: tracking_wrapper,
-reg__193: VCU118RocketSystem__GC0,
-case__708: RocketTile__GCB0,
-logic__1124: VCU118RocketSystem__GC0,
-logic__1863: RocketTile__GCB0, DCache,
-logic__3015: FPU__GB2, FPU__GB1,
-Repeater_TLBundleA_a26d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__979: VCU118RocketSystem__GC0,
-datapath__92: VCU118RocketSystem__GC0,
-logic__7010: VCU118RocketSystem__GC0,
-logic__6198: VCU118RocketSystem__GC0,
-reg__363: RocketTile__GCB0,
-logic__4861: RocketTile__GCB0,
-reg__385: FPU__GB0,
-datapath__525: APBGpsBlock__GCB1,
-case__1467: tracking_wrapper,
-datapath__48: VCU118RocketSystem__GC0,
-case__314: DCache,
-case__747: RocketTile__GCB0,
-reg__265: DCache,
-logic__4383: FPU__GB2,
-reg__138: VCU118RocketSystem__GC0,
-TLFIFOFixer: VCU118RocketSystem__GC0,
-logic__8066: APBGpsBlock__GCB1,
-datapath__235: VCU118RocketSystem__GC0,
-logic__8060: APBGpsBlock__GCB1,
-logic__7079: VCU118RocketSystem__GC0,
-logic__2967: FPU__GB2, FPU__GB1,
-logic__2945: FPU__GB1,
-case__272: VCU118RocketSystem__GC0,
-logic__1854: RocketTile__GCB0, DCache,
-case__540: FPU__GB2,
-logic__1892: RocketTile__GCB0, DCache,
-case__120: VCU118RocketSystem__GC0,
-logic__4375: FPU__GB1,
-datapath__196: VCU118RocketSystem__GC0,
-logic__714: VCU118RocketSystem__GC0,
-reg__662: RocketTile__GCB0,
-logic__5075: RocketTile__GCB0,
-logic__9352: TLToAPB,
-datapath__597: APBGpsBlock__GCB1,
-logic__5309: RocketTile__GCB0,
-reg__823: VCU118RocketSystem__GC0,
-reg__52: VCU118RocketSystem__GC0,
-case__616: RocketTile__GCB0,
-logic__1869: RocketTile__GCB0, DCache,
-logic__8437: tracking_wrapper,
-logic__1433: RocketTile__GCB0,
-case__778: RocketTile__GCB0,
-logic__1411: VCU118RocketSystem__GC0,
-case__486: FPU__GB2,
-extram__3: APBGpsBlock__GCB1,
-logic__6992: VCU118RocketSystem__GC0,
-case__299: RocketTile__GCB0,
-reg__566: FPU__GB1,
-case__1012: VCU118RocketSystem__GC0,
-datapath__181: VCU118RocketSystem__GC0,
-case__448: FPU__GB1,
-logic__4619: RocketTile__GCB0,
-reg__706: RocketTile__GCB0,
-logic__4931: RocketTile__GCB0,
-logic__139: VCU118RocketSystem__GC0,
-reg__687: RocketTile__GCB0,
-logic__1796: DCache,
-case__114: VCU118RocketSystem__GC0,
-reg__40: VCU118RocketSystem__GC0,
-datapath__1: genesys2_rocket_top__GC0,
-reg__972: VCU118RocketSystem__GC0,
-logic__3873: FPU__GB1,
-datapath__683: tracking_wrapper,
-logic__6040: RocketTile__GCB0,
-logic__3229: FPU__GB2,
-logic__1120: VCU118RocketSystem__GC0,
-case__183: VCU118RocketSystem__GC0,
-reg__524: FPU__GB2,
-logic__4879: RocketTile__GCB0,
-logic__586: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a29d32s2k1z3u: VCU118RocketSystem__GC0,
-datapath__625: tracking_wrapper,
-muxpart__92: FPU__GB1,
-logic__7594: VCU118RocketSystem__GC0,
-case__1125: APBGpsBlock__GCB1,
-logic__6545: VCU118RocketSystem__GC0,
-case__1101: APBGpsBlock__GCB1,
-datapath__180: VCU118RocketSystem__GC0,
-reg__433: FPU__GB1,
-logic__6139: VCU118RocketSystem__GC0,
-case__1341: tracking_wrapper,
-logic__64: genesys2_rocket_top__GC0,
-case__122: VCU118RocketSystem__GC0,
-logic__1613: DCache,
-logic__4341: FPU__GB1,
-logic__3683: FPU__GB1,
-reg__552: FPU__GB1,
-logic__2720: FPU__GB1,
-case__976: VCU118RocketSystem__GC0,
-logic__3841: FPU__GB1,
-reg__224: VCU118RocketSystem__GC0,
-logic__5067: RocketTile__GCB0,
-datapath__335: FPU__GB2,
-logic__5320: RocketTile__GCB0,
-reg__1072: APBGpsBlock__GCB1,
-logic__5529: RocketTile__GCB0,
-datapath__244: DCache,
-NCO_code: tracking_wrapper,
-case__630: RocketTile__GCB0,
-logic__1031: VCU118RocketSystem__GC0,
-case__1384: tracking_wrapper,
-logic__6569: VCU118RocketSystem__GC0,
-logic__747: VCU118RocketSystem__GC0,
-logic__5549: RocketTile__GCB0,
-reg__335: RocketTile__GCB0,
-logic__6927: VCU118RocketSystem__GC0,
-logic__1847: RocketTile__GCB0, DCache,
-logic__1654: DCache,
-case__129: VCU118RocketSystem__GC0,
-logic__871: VCU118RocketSystem__GC0,
-reg__1160: tracking_wrapper,
-logic__6050: RocketTile__GCB0,
-logic__5712: RocketTile__GCB0,
-case__1513: tracking_wrapper,
-reg__516: FPU__GB2,
-logic__5517: RocketTile__GCB0,
-reg__1280: tracking_wrapper,
-datapath__88: VCU118RocketSystem__GC0,
-logic__2960: FPU__GB1,
-logic__2641: RocketTile__GCB0,
-logic__8469: tracking_wrapper,
-reg__238: DCache,
-logic__238: VCU118RocketSystem__GC0,
-case__1550: APBGpsBlock__GCB0,
-reg__61: VCU118RocketSystem__GC0,
-case__672: RocketTile__GCB0,
-muxpart__17: RocketTile__GCB0,
-logic__5401: RocketTile__GCB0,
-logic__3474: FPU__GB2,
-reg__738: RocketTile__GCB0,
-case__1686: TLToAPB,
-reg__1224: tracking_wrapper,
-logic__3198: FPU__GB2,
-logic__142: VCU118RocketSystem__GC0,
-datapath__10: VCU118RocketSystem__GC0,
-logic__7959: APBGpsBlock__GCB1,
-logic__2201: DCache,
-logic__9316: APBGpsBlock__GCB0,
-datapath__336: FPU__GB2,
-logic__1964: DCache,
-logic__6759: VCU118RocketSystem__GC0,
-logic__1121: VCU118RocketSystem__GC0,
-datapath__424: RocketTile__GCB0,
-reg__1148: tracking_wrapper,
-logic__6080: RocketTile__GCB0,
-keep__37: APBGpsBlock__GCB0,
-reg__54: VCU118RocketSystem__GC0,
-case__1328: APBGpsBlock__GCB1,
-datapath__478: VCU118RocketSystem__GC0,
-case__383: RocketTile__GCB0,
-reg__711: RocketTile__GCB0,
-reg__1153: tracking_wrapper,
-reg__726: RocketTile__GCB0,
-TLToAPB: TLToAPB,
-logic__3996: FPU__GB2, FPU__GB1,
-logic__4024: FPU__GB2,
-logic__4356: FPU__GB1,
-reg__758: RocketTile__GCB0,
-logic__1356: VCU118RocketSystem__GC0,
-ClockGroupAggregator_cbus: VCU118RocketSystem__GC0,
-datapath__274: RocketTile__GCB0,
-logic__3325: FPU__GB2,
-reg__1218: tracking_wrapper,
-reg__1083: APBGpsBlock__GCB1,
-reg__1181: tracking_wrapper,
-logic__6667: VCU118RocketSystem__GC0,
-logic__5962: RocketTile__GCB0,
-logic__8529: tracking_wrapper,
-datapath__442: RocketTile__GCB0,
-keep__3: tracking_wrapper,
-logic__7247: VCU118RocketSystem__GC0,
-logic__915: VCU118RocketSystem__GC0,
-logic__3679: FPU__GB1,
-rom: VCU118RocketSystem__GC0,
-logic__490: VCU118RocketSystem__GC0,
-logic__2957: FPU__GB1,
-logic__4977: RocketTile__GCB0,
-logic__8325: tracking_wrapper,
-logic__944: VCU118RocketSystem__GC0,
-logic__4241: FPU__GB2,
-datapath__734: APBGpsBlock__GCB0,
-logic__3568: FPU__GB1,
-datapath__144: VCU118RocketSystem__GC0,
-reg__1128: APBGpsBlock__GCB0,
-logic__4938: RocketTile__GCB0,
-logic__1547: DCache,
-reg__336: RocketTile__GCB0,
-reg__984: VCU118RocketSystem__GC0,
-dsp48e1__27: APBGpsBlock__GCB1,
-case__738: RocketTile__GCB0,
-logic__8465: tracking_wrapper,
-reg__429: FPU__GB1,
-logic__6839: VCU118RocketSystem__GC0,
-case__1234: APBGpsBlock__GCB1,
-case__655: RocketTile__GCB0,
-case__1356: tracking_wrapper,
-case__1419: tracking_wrapper,
-case__160: VCU118RocketSystem__GC0,
-logic__5215: RocketTile__GCB0,
-muxpart__62: FPU__GB0,
-datapath__558: APBGpsBlock__GCB1,
-reg__1410: APBGpsBlock__GCB0,
-logic__6357: VCU118RocketSystem__GC0,
-logic__5880: RocketTile__GCB0,
-case__608: FPU__GB1,
-case__721: RocketTile__GCB0,
-reg__1311: tracking_wrapper,
-reg__917: VCU118RocketSystem__GC0,
-Queue2_TLBundleD_a32d8s1k1z4u: VCU118RocketSystem__GC0,
-logic__3309: FPU__GB2,
-logic__5367: RocketTile__GCB0,
-logic__6258: VCU118RocketSystem__GC0,
-logic__1482: RocketTile__GCB0,
-datapath__37: VCU118RocketSystem__GC0,
-logic__7681: VCU118RocketSystem__GC0,
-logic__2426: RocketTile__GCB0,
-logic__2686: RocketTile__GCB0,
-logic__8950: APBGpsBlock__GCB0,
-reg__571: FPU__GB1,
-logic__4636: RocketTile__GCB0,
-case__189: VCU118RocketSystem__GC0,
-case__353: DCache,
-reg__74: VCU118RocketSystem__GC0,
-logic__2719: FPU__GB1,
-extram__2: RocketTile__GCB0,
-case__326: DCache,
-ram__6: RocketTile__GCB0,
-case__945: VCU118RocketSystem__GC0,
-case__207: VCU118RocketSystem__GC0,
-datapath__119: VCU118RocketSystem__GC0,
-logic__1432: RocketTile__GCB0,
-logic__6467: VCU118RocketSystem__GC0,
-case__87: VCU118RocketSystem__GC0,
-reg__87: VCU118RocketSystem__GC0,
-logic__2940: FPU__GB1,
-logic__5920: RocketTile__GCB0,
-logic__6196: VCU118RocketSystem__GC0,
-logic__1020: VCU118RocketSystem__GC0,
-case__212: VCU118RocketSystem__GC0,
-reg__453: FPU__GB1,
-logic__4169: FPU__GB2,
-reg__37: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6218: VCU118RocketSystem__GC0,
-case__833: VCU118RocketSystem__GC0,
-logic__1249: VCU118RocketSystem__GC0,
-case__1192: APBGpsBlock__GCB1,
-logic__5266: RocketTile__GCB0,
-logic__2397: RocketTile__GCB0,
-reg__1152: tracking_wrapper,
-rockettile_icache_tag_array_0_64x21: RocketTile__GCB0,
-case__1414: tracking_wrapper,
-case__98: VCU118RocketSystem__GC0,
-case__1346: tracking_wrapper,
-reg__277: DCache,
-logic__1245: VCU118RocketSystem__GC0,
-logic__5364: RocketTile__GCB0,
-case__872: VCU118RocketSystem__GC0,
-case__615: RocketTile__GCB0,
-reg__176: VCU118RocketSystem__GC0,
-case__340: DCache,
-case__799: VCU118RocketSystem__GC0,
-case__740: RocketTile__GCB0,
-case__97: VCU118RocketSystem__GC0,
-case__1476: tracking_wrapper,
-logic__1040: VCU118RocketSystem__GC0,
-logic__3839: FPU__GB1,
-reg__486: FPU__GB1,
-ClockGroupAggregator_aggregator: VCU118RocketSystem__GC0,
-logic__4105: FPU__GB2,
-logic__6934: VCU118RocketSystem__GC0,
-logic__634: VCU118RocketSystem__GC0,
-datapath__584: APBGpsBlock__GCB1,
-logic__2725: FPU__GB1,
-reg__661: RocketTile__GCB0,
-reg__1346: APBGpsBlock__GCB0,
-logic__6790: VCU118RocketSystem__GC0,
-reg__1253: tracking_wrapper,
-datapath__114: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-muxpart__71: FPU__GB0,
-logic__8492: tracking_wrapper,
-reg__222: VCU118RocketSystem__GC0,
-reg__840: VCU118RocketSystem__GC0,
-case__827: VCU118RocketSystem__GC0,
-reg__39: VCU118RocketSystem__GC0,
-HellaCacheArbiter: RocketTile__GCB0,
-reg__1214: tracking_wrapper,
-case__1408: tracking_wrapper,
-case__700: RocketTile__GCB0,
-logic__3911: FPU__GB2, FPU__GB1,
-logic__4856: RocketTile__GCB0,
-logic__3555: FPU__GB1,
-reg__346: RocketTile__GCB0,
-reg__1246: tracking_wrapper,
-case__1334: APBGpsBlock__GCB1,
-logic__4041: FPU__GB2,
-case__275: VCU118RocketSystem__GC0,
-case__228: VCU118RocketSystem__GC0,
-datapath__242: DCache,
-logic__1936: DCache,
-datapath__632: tracking_wrapper,
-case__900: VCU118RocketSystem__GC0,
-datapath__278: RocketTile__GCB0,
-datapath__658: tracking_wrapper,
-case__1199: APBGpsBlock__GCB1,
-case__569: FPU__GB2,
-logic__3785: FPU__GB1,
-reg__1432: APBGpsBlock__GCB0,
-logic__6603: VCU118RocketSystem__GC0,
-logic__1742: DCache,
-case__1340: tracking_wrapper,
-case__1404: tracking_wrapper,
-datapath__183: VCU118RocketSystem__GC0,
-logic__1507: RocketTile__GCB0,
-logic__1891: RocketTile__GCB0, DCache,
-logic__6664: VCU118RocketSystem__GC0,
-reg__548: FPU__GB1,
-case__499: FPU__GB2,
-logic__4625: RocketTile__GCB0,
-reg__78: VCU118RocketSystem__GC0,
-logic__3684: FPU__GB1,
-logic__6533: VCU118RocketSystem__GC0,
-dsp48e1__18: APBGpsBlock__GCB1,
-keep__7: tracking_wrapper,
-reg__1443: APBGpsBlock__GCB0,
-logic__8270: tracking_wrapper,
-logic__8433: tracking_wrapper,
-logic__6752: VCU118RocketSystem__GC0,
-TLFragmenter_Debug: VCU118RocketSystem__GC0,
-logic__4963: RocketTile__GCB0,
-logic__2825: FPU__GB1,
-logic__106: VCU118RocketSystem__GC0,
-logic__2617: RocketTile__GCB0,
-datapath__464: TilePRCIDomain__GC0,
-logic__4440: FPU__GB1,
-datapath__182: VCU118RocketSystem__GC0,
-logic__955: VCU118RocketSystem__GC0,
-logic__639: VCU118RocketSystem__GC0,
-reg__53: VCU118RocketSystem__GC0,
-reg__1049: APBGpsBlock__GCB1,
-logic__8461: tracking_wrapper,
-AsyncValidSync: VCU118RocketSystem__GC0,
-case__1529: APBGpsBlock__GCB0,
-logic__9336: APBGpsBlock__GCB0,
-logic__1623: DCache,
-counter__15: APBGpsBlock__GCB1,
-reg__1233: tracking_wrapper,
-case__899: VCU118RocketSystem__GC0,
-logic__7947: APBGpsBlock__GCB1,
-case__1531: APBGpsBlock__GCB0,
-logic__3425: FPU__GB2,
-RocketALU: RocketTile__GCB0,
-logic__9372: TLToAPB,
-logic__6474: VCU118RocketSystem__GC0,
-logic__568: VCU118RocketSystem__GC0,
-logic__1550: DCache,
-datapath__526: APBGpsBlock__GCB1,
-case__284: VCU118RocketSystem__GC0,
-logic__8255: APBGpsBlock__GCB1,
-case__720: RocketTile__GCB0,
-datapath__701: APBGpsBlock__GCB0,
-reg__386: FPU__GB0,
-logic__3962: FPU__GB2, FPU__GB1,
-case__174: VCU118RocketSystem__GC0,
-case__368: DCache,
-Frontend: RocketTile__GCB0,
-logic__2721: FPU__GB1,
-reg__420: FPU__GB1,
-case__568: FPU__GB2,
-logic__5074: RocketTile__GCB0,
-reg__1075: APBGpsBlock__GCB1,
-reg__297: RocketTile__GCB0,
-logic__5304: RocketTile__GCB0,
-reg__68: VCU118RocketSystem__GC0,
-logic__7756: APBGpsBlock__GCB1,
-reg__965: VCU118RocketSystem__GC0,
-logic__6523: VCU118RocketSystem__GC0,
-logic__237: VCU118RocketSystem__GC0,
-logic__2901: FPU__GB1,
-logic__5092: RocketTile__GCB0,
-logic__5032: RocketTile__GCB0,
-case__361: DCache,
-logic__8361: tracking_wrapper,
-reg__311: RocketTile__GCB0,
-logic__2707: FPU__GB1,
-datapath__419: RocketTile__GCB0,
-logic__7327: VCU118RocketSystem__GC0,
-case__583: FPU__GB1,
-reg__1042: APBGpsBlock__GCB1,
-case__1533: APBGpsBlock__GCB0,
-RoundRawFNToRecFN_1: FPU__GB2, FPU__GB1,
-logic__8329: tracking_wrapper,
-case__180: VCU118RocketSystem__GC0,
-datapath__659: tracking_wrapper,
-logic__1152: VCU118RocketSystem__GC0,
-logic__8188: APBGpsBlock__GCB1,
-logic__4840: RocketTile__GCB0,
-case__1281: APBGpsBlock__GCB1,
-case__306: RocketTile__GCB0,
-logic__1022: VCU118RocketSystem__GC0,
-case__147: VCU118RocketSystem__GC0,
-reg__1387: APBGpsBlock__GCB0,
-case__291: RocketTile__GCB0,
-datapath__579: APBGpsBlock__GCB1,
-datapath__465: TilePRCIDomain__GC0,
-logic__4307: FPU__GB1,
-case__798: VCU118RocketSystem__GC0,
-logic__305: VCU118RocketSystem__GC0,
-case__670: RocketTile__GCB0,
-logic__3350: FPU__GB2,
-logic__6503: VCU118RocketSystem__GC0,
-logic__6419: VCU118RocketSystem__GC0,
-datapath__481: VCU118RocketSystem__GC0,
-datapath__602: APBGpsBlock__GCB1,
-muxpart__95: RocketTile__GCB0,
-reg__887: VCU118RocketSystem__GC0,
-logic__3556: FPU__GB1,
-datapath__409: RocketTile__GCB0,
-datapath__480: VCU118RocketSystem__GC0,
-reg__191: VCU118RocketSystem__GC0,
-reg__872: VCU118RocketSystem__GC0,
-logic__3173: FPU__GB2,
-logic__3844: FPU__GB1,
-logic__6687: VCU118RocketSystem__GC0,
-case__1375: tracking_wrapper,
-logic__3955: FPU__GB2, FPU__GB1,
-case__1030: VCU118RocketSystem__GC0,
-logic__4638: RocketTile__GCB0,
-datapath__2: genesys2_rocket_top__GC0,
-reg__1034: APBGpsBlock__GCB1,
-logic__7462: VCU118RocketSystem__GC0,
-logic__8087: APBGpsBlock__GCB1,
-datapath__275: RocketTile__GCB0,
-logic__283: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__8966: APBGpsBlock__GCB0,
-logic__8438: tracking_wrapper,
-case__698: RocketTile__GCB0,
-logic__701: VCU118RocketSystem__GC0,
-reg__1020: APBGpsBlock__GCB1,
-reg__448: FPU__GB2,
-muxpart__37: FPU__GB0,
-logic__3900: FPU__GB2, FPU__GB1,
-reg__575: FPU__GB1,
-reg__892: VCU118RocketSystem__GC0,
-reg__600: RocketTile__GCB0,
-logic__5365: RocketTile__GCB0,
-logic__1446: RocketTile__GCB0,
-case__1451: tracking_wrapper,
-reg__1438: APBGpsBlock__GCB0,
-muxpart__57: FPU__GB0,
-TLPLIC: VCU118RocketSystem__GC0,
-reg__1264: tracking_wrapper,
-logic__2014: DCache,
-logic__7088: VCU118RocketSystem__GC0,
-logic__6142: VCU118RocketSystem__GC0,
-reg__819: VCU118RocketSystem__GC0,
-logic__6178: VCU118RocketSystem__GC0,
-case__1132: APBGpsBlock__GCB1,
-logic__9255: APBGpsBlock__GCB0,
-logic__1101: VCU118RocketSystem__GC0,
-case__1139: APBGpsBlock__GCB1,
-logic__9331: APBGpsBlock__GCB0,
-datapath__571: APBGpsBlock__GCB1,
-case__839: VCU118RocketSystem__GC0,
-ScratchpadSlavePort: RocketTile__GCB0,
-logic__8735: tracking_wrapper,
-reg__259: DCache,
-logic__4059: FPU__GB2,
-reg__1286: tracking_wrapper,
-case__727: RocketTile__GCB0,
-logic__1458: RocketTile__GCB0,
-datapath__130: VCU118RocketSystem__GC0,
-reg__702: RocketTile__GCB0,
-logic__3687: FPU__GB1,
-reg__596: RocketTile__GCB0,
-logic__497: VCU118RocketSystem__GC0,
-logic__1682: DCache,
-case__1240: APBGpsBlock__GCB1,
-case__1518: tracking_wrapper,
-logic__4294: FPU__GB2,
-logic__5830: RocketTile__GCB0,
-logic__6602: VCU118RocketSystem__GC0,
-logic__6413: VCU118RocketSystem__GC0,
-logic__6546: VCU118RocketSystem__GC0,
-logic__6286: VCU118RocketSystem__GC0,
-datapath__53: VCU118RocketSystem__GC0,
-case__975: VCU118RocketSystem__GC0,
-logic__1866: RocketTile__GCB0, DCache,
-logic__8012: APBGpsBlock__GCB1,
-logic__6276: VCU118RocketSystem__GC0,
-logic__6143: VCU118RocketSystem__GC0,
-logic__3174: FPU__GB2,
-case__104: VCU118RocketSystem__GC0,
-keep__8: tracking_wrapper,
-reg__163: VCU118RocketSystem__GC0,
-reg__1431: APBGpsBlock__GCB0,
-logic__8415: tracking_wrapper,
-trck_cntrl: tracking_wrapper,
-muxpart__2: genesys2_rocket_top__GC0,
-logic__6045: RocketTile__GCB0,
-logic__1173: VCU118RocketSystem__GC0,
-case__1193: APBGpsBlock__GCB1,
-dsp48e1__43: tracking_wrapper,
-reg__623: RocketTile__GCB0,
-datapath__87: VCU118RocketSystem__GC0,
-reg__1328: tracking_wrapper,
-reg__305: RocketTile__GCB0,
-case__541: FPU__GB2,
-datapath__257: DCache,
-logic__1315: VCU118RocketSystem__GC0,
-logic__7814: APBGpsBlock__GCB1,
-keep__23: APBGpsBlock__GCB0,
-reg__233: RocketTile__GCB0,
-logic__9185: APBGpsBlock__GCB0,
-logic__7555: VCU118RocketSystem__GC0,
-case__937: VCU118RocketSystem__GC0,
-reg__318: RocketTile__GCB0,
-case__1600: APBGpsBlock__GCB0,
-logic__6892: VCU118RocketSystem__GC0,
-logic__444: VCU118RocketSystem__GC0,
-logic__3688: FPU__GB1,
-reg__1248: tracking_wrapper,
-logic__7028: VCU118RocketSystem__GC0,
-logic__3190: FPU__GB2,
-case__450: FPU__GB1,
-logic__4153: FPU__GB2,
-logic__3240: FPU__GB2,
-datapath__327: FPU__GB2,
-case__55: VCU118RocketSystem__GC0,
-logic__4687: RocketTile__GCB0,
-case__72: VCU118RocketSystem__GC0,
-datapath__179: VCU118RocketSystem__GC0,
-logic__8690: tracking_wrapper,
-case__235: VCU118RocketSystem__GC0,
-logic__4462: FPU__GB0,
-reg__985: VCU118RocketSystem__GC0,
-datapath__103: VCU118RocketSystem__GC0,
-case__431: RocketTile__GCB0,
-case__1397: tracking_wrapper,
-logic__1058: VCU118RocketSystem__GC0,
-logic__2396: RocketTile__GCB0,
-logic__9234: APBGpsBlock__GCB0,
-logic__8364: tracking_wrapper,
-reg__768: RocketTile__GCB0,
-reg__245: DCache,
-muxpart__311: APBGpsBlock__GCB0,
-case__994: VCU118RocketSystem__GC0,
-datapath__299: FPU__GB2, FPU__GB1,
-TLInterconnectCoupler_cbus_to_rockettile: VCU118RocketSystem__GC0,
-case__236: VCU118RocketSystem__GC0,
-logic__2893: FPU__GB1,
-case__420: RocketTile__GCB0,
-logic__5231: RocketTile__GCB0,
-logic__6917: VCU118RocketSystem__GC0,
-logic__3689: FPU__GB1,
-logic__6564: VCU118RocketSystem__GC0,
-logic__3158: FPU__GB2,
-logic__6487: VCU118RocketSystem__GC0,
-logic__1703: DCache,
-logic__3290: FPU__GB2,
-logic__8662: tracking_wrapper,
-logic__8971: APBGpsBlock__GCB0,
-logic__6256: VCU118RocketSystem__GC0,
-logic__5705: RocketTile__GCB0,
-logic__4472: FPU__GB1,
-logic__6075: RocketTile__GCB0,
-logic__6626: VCU118RocketSystem__GC0,
-case__1009: VCU118RocketSystem__GC0,
-datapath__68: VCU118RocketSystem__GC0,
-logic__4740: RocketTile__GCB0,
-logic__2902: FPU__GB1,
-logic__2915: FPU__GB1,
-case__336: DCache,
-logic__2020: DCache,
-reg__603: RocketTile__GCB0,
-logic__4556: RocketTile__GCB0,
-logic__1374: VCU118RocketSystem__GC0,
-logic__6841: VCU118RocketSystem__GC0,
-logic__2251: DCache,
-reg__478: FPU__GB1,
-reg__862: VCU118RocketSystem__GC0,
-datapath__512: VCU118RocketSystem__GC0,
-case__152: VCU118RocketSystem__GC0,
-logic__3286: FPU__GB2,
-logic__5916: RocketTile__GCB0,
-datapath__40: VCU118RocketSystem__GC0,
-logic__9342: APBGpsBlock__GCB1,
-reg__650: RocketTile__GCB0,
-logic__5722: RocketTile__GCB0,
-datapath__725: APBGpsBlock__GCB0,
-logic__4216: FPU__GB2,
-logic__4962: RocketTile__GCB0,
-reg__1424: APBGpsBlock__GCB0,
-reg__526: FPU__GB1,
-case__218: VCU118RocketSystem__GC0,
-logic__6426: VCU118RocketSystem__GC0,
-logic__1223: VCU118RocketSystem__GC0,
-datapath__4: genesys2_rocket_top__GC0,
-datapath__510: VCU118RocketSystem__GC0,
-reg__1193: tracking_wrapper,
-reg__337: RocketTile__GCB0,
-logic__7015: VCU118RocketSystem__GC0,
-datapath__548: APBGpsBlock__GCB1,
-case__925: VCU118RocketSystem__GC0,
-logic__7826: APBGpsBlock__GCB1,
-datapath__39: VCU118RocketSystem__GC0,
-case__309: RocketTile__GCB0,
-reg__192: VCU118RocketSystem__GC0,
-logic__577: VCU118RocketSystem__GC0,
-reg__781: VCU118RocketSystem__GC0,
-reg__145: VCU118RocketSystem__GC0,
-datapath__713: APBGpsBlock__GCB0,
-logic__977: VCU118RocketSystem__GC0,
-datapath__16: VCU118RocketSystem__GC0,
-reg__1114: APBGpsBlock__GCB1,
-datapath__534: APBGpsBlock__GCB1,
-case__819: VCU118RocketSystem__GC0,
-case__282: VCU118RocketSystem__GC0,
-logic__3875: FPU__GB1,
-logic__5340: RocketTile__GCB0,
-logic__6657: VCU118RocketSystem__GC0,
-logic__1466: RocketTile__GCB0,
-datapath__297: FPU__GB1,
-datapath__463: RocketTile__GCB0,
-logic__4425: FPU__GB1,
-logic__4458: FPU__GB1,
-logic__8852: tracking_wrapper,
-datapath__516: VCU118RocketSystem__GC0,
-logic__1044: VCU118RocketSystem__GC0,
-logic__850: VCU118RocketSystem__GC0,
-logic__5411: RocketTile__GCB0,
-reg__976: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_cbus_to_bootrom: VCU118RocketSystem__GC0,
-logic__4266: FPU__GB2,
-logic__6163: VCU118RocketSystem__GC0,
-logic__4772: RocketTile__GCB0,
-reg__1419: APBGpsBlock__GCB0,
-logic__1318: VCU118RocketSystem__GC0,
-logic__5479: RocketTile__GCB0,
-logic__1474: RocketTile__GCB0,
-case__1640: APBGpsBlock__GCB0,
-logic__8554: tracking_wrapper,
-logic__8503: tracking_wrapper,
-logic__2157: DCache,
-logic__388: VCU118RocketSystem__GC0,
-reg__1367: APBGpsBlock__GCB0,
-TLBuffer_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4026: FPU__GB2,
-logic__3496: FPU__GB2,
-reg__740: RocketTile__GCB0,
-datapath__491: VCU118RocketSystem__GC0,
-logic__4944: RocketTile__GCB0,
-reg__1274: tracking_wrapper,
-reg__1254: tracking_wrapper,
-reg__843: VCU118RocketSystem__GC0,
-logic__7471: VCU118RocketSystem__GC0,
-logic__7282: VCU118RocketSystem__GC0,
-case__1659: APBGpsBlock__GCB0,
-datapath__45: VCU118RocketSystem__GC0,
-logic__6234: VCU118RocketSystem__GC0,
-case__437: RocketTile__GCB0,
-reg__633: RocketTile__GCB0,
-logic__4818: RocketTile__GCB0,
-datapath__427: RocketTile__GCB0,
-logic__5400: RocketTile__GCB0,
-logic__2474: RocketTile__GCB0,
-case__124: VCU118RocketSystem__GC0,
-logic__7501: VCU118RocketSystem__GC0,
-logic__2420: RocketTile__GCB0,
-reg__694: RocketTile__GCB0,
-logic__141: VCU118RocketSystem__GC0,
-logic__5066: RocketTile__GCB0,
-reg__775: RocketTile__GCB0,
-logic__3248: FPU__GB2,
-logic__2491: RocketTile__GCB0,
-datapath__604: APBGpsBlock__GCB1,
-case__501: FPU__GB2,
-logic__2824: FPU__GB1,
-reg__105: VCU118RocketSystem__GC0,
-case__1089: APBGpsBlock__GCB1,
-logic__4637: RocketTile__GCB0,
-logic__7099: VCU118RocketSystem__GC0,
-reg__328: RocketTile__GCB0,
-datapath__498: VCU118RocketSystem__GC0,
-datapath__176: VCU118RocketSystem__GC0,
-reg__282: DCache,
-case__701: RocketTile__GCB0,
-logic__6577: VCU118RocketSystem__GC0,
-logic__2937: FPU__GB1,
-logic__8932: APBGpsBlock__GCB0,
-reg__45: VCU118RocketSystem__GC0,
-logic__5408: RocketTile__GCB0,
-logic__4296: FPU__GB2,
-reg__1107: APBGpsBlock__GCB1,
-datapath__291: FPU__GB1,
-logic__6408: VCU118RocketSystem__GC0,
-logic__5162: RocketTile__GCB0,
-logic__3753: FPU__GB1,
-logic__4578: RocketTile__GCB0,
-datapath__644: tracking_wrapper,
-case__511: FPU__GB1,
-datapath__54: VCU118RocketSystem__GC0,
-logic__946: VCU118RocketSystem__GC0,
-case__477: FPU__GB2,
-datapath__356: FPU__GB1,
-logic__6100: RocketTile__GCB0,
-reg__235: DCache,
-case__1168: APBGpsBlock__GCB1,
-logic__2423: RocketTile__GCB0,
-case__502: FPU__GB2,
-case__1385: tracking_wrapper,
-logic__1723: DCache,
-logic__9168: APBGpsBlock__GCB0,
-reg__473: FPU__GB1,
-case__1523: tracking_wrapper,
-logic__658: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__146: VCU118RocketSystem__GC0,
-reg__1281: tracking_wrapper,
-logic__6581: VCU118RocketSystem__GC0,
-reg__50: VCU118RocketSystem__GC0,
-reg__759: RocketTile__GCB0,
-reg__1: genesys2_rocket_top__GC0,
-logic__1558: DCache,
-logic__6338: VCU118RocketSystem__GC0,
-logic__5975: RocketTile__GCB0,
-reg__713: RocketTile__GCB0,
-case__661: RocketTile__GCB0,
-logic__8432: tracking_wrapper,
-datapath__515: VCU118RocketSystem__GC0,
-case__1297: APBGpsBlock__GCB1,
-dsp48e1__20: APBGpsBlock__GCB1,
-logic__4154: FPU__GB2,
-LF_code: tracking_wrapper,
-logic__8631: tracking_wrapper,
-logic__6544: VCU118RocketSystem__GC0,
-logic__3784: FPU__GB1,
-datapath__233: VCU118RocketSystem__GC0,
-reg__221: VCU118RocketSystem__GC0,
-datapath__574: APBGpsBlock__GCB1,
-logic__2874: FPU__GB1,
-case__474: FPU__GB2,
-datapath__32: VCU118RocketSystem__GC0,
-case__111: VCU118RocketSystem__GC0,
-dsp48e1__16: APBGpsBlock__GCB1,
-datapath__354: FPU__GB1,
-muxpart__93: FPU__GB1,
-logic__4209: FPU__GB2,
-logic__2413: RocketTile__GCB0,
-logic__1521: DCache,
-logic__2342: RocketTile__GCB0,
-reg__874: VCU118RocketSystem__GC0,
-reg__1427: APBGpsBlock__GCB0,
-datapath__566: APBGpsBlock__GCB1,
-reg__716: RocketTile__GCB0,
-logic__2378: RocketTile__GCB0,
-logic__6806: VCU118RocketSystem__GC0,
-OptimizationBarrier_TLBEntryData: RocketTile__GCB0, DCache,
-logic__6375: VCU118RocketSystem__GC0,
-logic__8495: tracking_wrapper,
-reg__750: RocketTile__GCB0,
-ErrorDeviceWrapper: VCU118RocketSystem__GC0,
-logic__231: VCU118RocketSystem__GC0,
-logic__2257: DCache,
-logic__5475: RocketTile__GCB0,
-logic__7989: APBGpsBlock__GCB1,
-reg__240: DCache,
-logic__6543: VCU118RocketSystem__GC0,
-reg__794: VCU118RocketSystem__GC0,
-case__113: VCU118RocketSystem__GC0,
-reg__1134: tracking_wrapper,
-case__530: FPU__GB2, FPU__GB1,
-logic__4350: FPU__GB2,
-logic__6563: VCU118RocketSystem__GC0,
-datapath__200: VCU118RocketSystem__GC0,
-logic__3827: FPU__GB1,
-logic__2891: FPU__GB1,
-logic__6775: VCU118RocketSystem__GC0,
-reg__466: FPU__GB1,
-case__341: DCache,
-logic__7885: APBGpsBlock__GCB1,
-case__3: genesys2_rocket_top__GC0,
-case__1302: APBGpsBlock__GCB1,
-case__1047: VCU118RocketSystem__GC0,
-datapath__707: APBGpsBlock__GCB0,
-logic__8663: tracking_wrapper,
-datapath__122: VCU118RocketSystem__GC0,
-datapath__259: DCache,
-logic__2866: FPU__GB1,
-logic__4820: RocketTile__GCB0,
-reg__434: FPU__GB1,
-datapath__567: APBGpsBlock__GCB1,
-case__927: VCU118RocketSystem__GC0,
-datapath__726: APBGpsBlock__GCB0,
-logic__4494: FPU__GB1,
-logic__8821: tracking_wrapper,
-datapath__649: tracking_wrapper,
-case__1401: tracking_wrapper,
-case__516: FPU__GB1,
-reg__1333: tracking_wrapper,
-datapath__385: FPU__GB1,
-logic__1390: VCU118RocketSystem__GC0,
-logic__4759: RocketTile__GCB0,
-logic__1321: VCU118RocketSystem__GC0,
-logic__7445: VCU118RocketSystem__GC0,
-logic__156: VCU118RocketSystem__GC0,
-reg__430: FPU__GB1,
-case__861: VCU118RocketSystem__GC0,
-datapath__113: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2807: FPU__GB1,
-case__991: VCU118RocketSystem__GC0,
-logic__3159: FPU__GB2,
-logic__1064: VCU118RocketSystem__GC0,
-logic__5488: RocketTile__GCB0,
-extladd__2: tracking_wrapper,
-logic__1872: RocketTile__GCB0, DCache,
-logic__1559: DCache,
-keep__21: APBGpsBlock__GCB0,
-case__1651: APBGpsBlock__GCB0,
-reg__585: RocketTile__GCB0,
-logic__5311: RocketTile__GCB0,
-logic__6432: VCU118RocketSystem__GC0,
-reg__1100: APBGpsBlock__GCB1,
-reg__441: FPU__GB2,
-logic__6243: VCU118RocketSystem__GC0,
-logic__9345: TLToAPB,
-logic__8580: tracking_wrapper,
-logic__2075: DCache,
-datapath__628: tracking_wrapper,
-logic__9097: APBGpsBlock__GCB0,
-reg__830: VCU118RocketSystem__GC0,
-logic__5936: RocketTile__GCB0,
-logic__6768: VCU118RocketSystem__GC0,
-logic__1180: VCU118RocketSystem__GC0,
-case__943: VCU118RocketSystem__GC0,
-logic__1342: VCU118RocketSystem__GC0,
-datapath__608: APBGpsBlock__GCB1,
-logic__3210: FPU__GB2,
-logic__2316: DCache,
-logic__8829: tracking_wrapper,
-datapath__15: VCU118RocketSystem__GC0,
-datapath__388: FPU__GB1,
-logic__2703: FPU__GB1,
-logic__1375: VCU118RocketSystem__GC0,
-logic__1647: DCache,
-logic__775: VCU118RocketSystem__GC0,
-case__327: DCache,
-logic__2715: FPU__GB1,
-case__422: RocketTile__GCB0,
-logic__1084: VCU118RocketSystem__GC0,
-logic__8599: tracking_wrapper,
-logic__6959: VCU118RocketSystem__GC0,
-reg__589: RocketTile__GCB0,
-logic__5329: RocketTile__GCB0,
-logic__1455: RocketTile__GCB0,
-case__1003: VCU118RocketSystem__GC0,
-case__222: VCU118RocketSystem__GC0,
-case__1146: APBGpsBlock__GCB1,
-logic__2662: RocketTile__GCB0,
-datapath__12: VCU118RocketSystem__GC0,
-reg__211: VCU118RocketSystem__GC0,
-logic__1803: DCache,
-reg__69: VCU118RocketSystem__GC0,
-muxpart__90: FPU__GB2,
-logic__3003: FPU__GB2, FPU__GB1,
-muxpart__46: FPU__GB0,
-logic__7043: VCU118RocketSystem__GC0,
-logic__1293: VCU118RocketSystem__GC0,
-logic__812: VCU118RocketSystem__GC0,
-case__1181: APBGpsBlock__GCB1,
-reg__325: RocketTile__GCB0,
-logic__901: VCU118RocketSystem__GC0,
-datapath__377: FPU__GB2,
-case__970: VCU118RocketSystem__GC0,
-case__958: VCU118RocketSystem__GC0,
-case__1432: tracking_wrapper,
-logic__778: VCU118RocketSystem__GC0,
-logic__145: VCU118RocketSystem__GC0,
-datapath__561: APBGpsBlock__GCB1,
-datapath__552: APBGpsBlock__GCB1,
-reg__1231: tracking_wrapper,
-logic__3632: FPU__GB1,
-reg__104: VCU118RocketSystem__GC0,
-logic__214: VCU118RocketSystem__GC0,
-muxpart__54: FPU__GB0,
-logic__6655: VCU118RocketSystem__GC0,
-TLFragmenter_PLIC: VCU118RocketSystem__GC0,
-datapath__178: VCU118RocketSystem__GC0,
-datapath__672: tracking_wrapper,
-logic__72: genesys2_rocket_top__GC0,
-reg__190: VCU118RocketSystem__GC0,
-logic__4642: RocketTile__GCB0,
-logic__6221: VCU118RocketSystem__GC0,
-logic__2822: FPU__GB1,
-reg__489: FPU__GB1,
-muxpart__6: VCU118RocketSystem__GC0,
-logic__4762: RocketTile__GCB0,
-logic__2418: RocketTile__GCB0,
-logic__4853: RocketTile__GCB0,
-logic__3299: FPU__GB2,
-reg__1212: tracking_wrapper,
-logic__5319: RocketTile__GCB0,
-case__1635: APBGpsBlock__GCB0,
-logic__1608: DCache,
-reg__851: VCU118RocketSystem__GC0,
-logic__976: VCU118RocketSystem__GC0,
-case__835: VCU118RocketSystem__GC0,
-case__1403: tracking_wrapper,
-case__290: RocketTile__GCB0,
-logic__2892: FPU__GB1,
-logic__1185: VCU118RocketSystem__GC0,
-logic__4825: RocketTile__GCB0,
-logic__8277: tracking_wrapper,
-case__408: RocketTile__GCB0,
-case__931: VCU118RocketSystem__GC0,
-datapath__360: FPU__GB2, FPU__GB1,
-datapath__405: RocketTile__GCB0,
-muxpart__11: DCache,
-case__381: RocketTile__GCB0,
-datapath__488: VCU118RocketSystem__GC0,
-reg__779: TilePRCIDomain__GC0,
-dsp48e1__14: APBGpsBlock__GCB1,
-case__1108: APBGpsBlock__GCB1,
-logic__1901: RocketTile__GCB0, DCache,
-logic__2615: RocketTile__GCB0,
-logic__2263: DCache,
-logic__7094: VCU118RocketSystem__GC0,
-logic__6592: VCU118RocketSystem__GC0,
-logic__2453: RocketTile__GCB0,
-case__1553: APBGpsBlock__GCB0,
-case__1604: APBGpsBlock__GCB0,
-reg__153: VCU118RocketSystem__GC0,
-logic__286: VCU118RocketSystem__GC0,
-logic__6853: VCU118RocketSystem__GC0,
-datapath__688: tracking_wrapper,
-logic__1560: DCache,
-reg__1242: tracking_wrapper,
-logic__5414: RocketTile__GCB0,
-logic__4163: FPU__GB2,
-datapath__312: FPU__GB2,
-reg__986: VCU118RocketSystem__GC0,
-logic__3486: FPU__GB2,
-logic__5299: RocketTile__GCB0,
-case__202: VCU118RocketSystem__GC0,
-logic__6498: VCU118RocketSystem__GC0,
-datapath__482: VCU118RocketSystem__GC0,
-case__710: RocketTile__GCB0,
-reg__229: VCU118RocketSystem__GC0,
-case__779: RocketTile__GCB0,
-case__362: DCache,
-case__1487: tracking_wrapper,
-logic__8258: APBGpsBlock__GCB0,
-logic__6773: VCU118RocketSystem__GC0,
-reg__365: RocketTile__GCB0,
-logic__4448: FPU__GB1,
-logic__6144: VCU118RocketSystem__GC0,
-DivSqrtRecFN_small: FPU__GB2,
-case__445: FPU__GB0,
-logic__6811: VCU118RocketSystem__GC0,
-reg__663: RocketTile__GCB0,
-reg__518: FPU__GB2,
-logic__792: VCU118RocketSystem__GC0,
-reg__1204: tracking_wrapper,
-reg__345: RocketTile__GCB0,
-logic__13: genesys2_rocket_top__GC0,
-logic__4921: RocketTile__GCB0,
-case__8: genesys2_rocket_top__GC0,
-case__646: RocketTile__GCB0,
-reg__166: VCU118RocketSystem__GC0,
-datapath__362: FPU__GB1,
-logic__896: VCU118RocketSystem__GC0,
-case__496: FPU__GB2,
-case__355: DCache,
-logic__2717: FPU__GB1,
-reg__1365: APBGpsBlock__GCB0,
-logic__3842: FPU__GB1,
-reg__996: VCU118RocketSystem__GC0,
-case__663: RocketTile__GCB0,
-logic__6514: VCU118RocketSystem__GC0,
-reg__630: RocketTile__GCB0,
-logic__4278: FPU__GB2,
-logic__3890: FPU__GB2, FPU__GB1,
-case__989: VCU118RocketSystem__GC0,
-logic__475: VCU118RocketSystem__GC0,
-logic__2811: FPU__GB1,
-logic__1506: RocketTile__GCB0,
-logic__429: VCU118RocketSystem__GC0,
-logic__9114: APBGpsBlock__GCB0,
-case__811: VCU118RocketSystem__GC0,
-case__294: RocketTile__GCB0,
-case__874: VCU118RocketSystem__GC0,
-logic__7744: APBGpsBlock__GCB1,
-logic__6175: VCU118RocketSystem__GC0,
-case__1174: APBGpsBlock__GCB1,
-logic__4295: FPU__GB2,
-logic__5508: RocketTile__GCB0,
-logic__5282: RocketTile__GCB0,
-case__1617: APBGpsBlock__GCB0,
-case__1426: tracking_wrapper,
-logic__3426: FPU__GB2,
-logic__2504: RocketTile__GCB0,
-reg__272: DCache,
-logic__6192: VCU118RocketSystem__GC0,
-logic__2415: RocketTile__GCB0,
-logic__2648: RocketTile__GCB0,
-reg__808: VCU118RocketSystem__GC0,
-case__37: VCU118RocketSystem__GC0,
-logic__4643: RocketTile__GCB0,
-logic__1807: DCache,
-logic__4554: RocketTile__GCB0,
-datapath__508: VCU118RocketSystem__GC0,
-logic__1057: VCU118RocketSystem__GC0,
-reg__415: FPU__GB1,
-case__1390: tracking_wrapper,
-logic__3398: FPU__GB2,
-datapath__129: VCU118RocketSystem__GC0,
-logic__3480: FPU__GB2,
-logic__2722: FPU__GB1,
-logic__3025: FPU__GB2, FPU__GB1,
-reg__767: RocketTile__GCB0,
-case__485: FPU__GB2,
-ifft_abs_sqr: APBGpsBlock__GCB1,
-reg__30: VCU118RocketSystem__GC0,
-logic__4017: FPU__GB1,
-logic__7202: VCU118RocketSystem__GC0,
-logic__6804: VCU118RocketSystem__GC0,
-logic__5985: RocketTile__GCB0,
-logic__2702: FPU__GB1,
-logic__2948: FPU__GB1,
-reg__697: RocketTile__GCB0,
-logic__1917: RocketTile__GCB0, DCache,
-logic__7526: VCU118RocketSystem__GC0,
-case__1313: APBGpsBlock__GCB1,
-logic__4924: RocketTile__GCB0,
-logic__4659: RocketTile__GCB0,
-case__667: RocketTile__GCB0,
-muxpart__69: FPU__GB0,
-DCacheDataArray: DCache,
-reg__676: RocketTile__GCB0,
-logic__8692: tracking_wrapper,
-logic__6767: VCU118RocketSystem__GC0,
-case__234: VCU118RocketSystem__GC0,
-logic__4029: FPU__GB2,
-case__187: VCU118RocketSystem__GC0,
-logic__2603: RocketTile__GCB0,
-logic__6505: VCU118RocketSystem__GC0,
-logic__4198: FPU__GB2,
-logic__4267: FPU__GB2,
-logic__515: VCU118RocketSystem__GC0,
-case__517: FPU__GB1,
-logic__5300: RocketTile__GCB0,
-case__313: DCache,
-case__705: RocketTile__GCB0,
-logic__1007: VCU118RocketSystem__GC0,
-logic__4657: RocketTile__GCB0,
-reg__93: VCU118RocketSystem__GC0,
-logic__6778: VCU118RocketSystem__GC0,
-logic__4819: RocketTile__GCB0,
-case__944: VCU118RocketSystem__GC0,
-logic__6137: VCU118RocketSystem__GC0,
-logic__5393: RocketTile__GCB0,
-logic__8431: tracking_wrapper,
-logic__491: VCU118RocketSystem__GC0,
-datapath__303: FPU__GB1,
-logic__9270: APBGpsBlock__GCB0,
-datapath__240: DCache,
-logic__1684: DCache,
-datapath__686: tracking_wrapper,
-logic__5656: RocketTile__GCB0,
-logic__2392: RocketTile__GCB0,
-logic__1719: DCache,
-logic__3818: FPU__GB1,
-logic__5717: RocketTile__GCB0,
-case__1169: APBGpsBlock__GCB1,
-logic__3879: FPU__GB1,
-logic__2457: RocketTile__GCB0,
-reg__939: VCU118RocketSystem__GC0,
-logic__131: VCU118RocketSystem__GC0,
-reg__565: FPU__GB1,
-logic__7672: VCU118RocketSystem__GC0,
-case__1687: TLToAPB,
-logic__4996: RocketTile__GCB0,
-logic__8660: tracking_wrapper,
-reg__239: DCache,
-reg__129: VCU118RocketSystem__GC0,
-logic__1532: DCache,
-logic__7219: VCU118RocketSystem__GC0,
-reg__418: FPU__GB1,
-reg__405: FPU__GB1,
-reg__732: RocketTile__GCB0,
-reg__1094: APBGpsBlock__GCB1,
-reg__495: FPU__GB1,
-logic__2205: DCache,
-logic__3723: FPU__GB1,
-logic__3028: FPU__GB2, FPU__GB1,
-reg__1263: tracking_wrapper,
-case__965: VCU118RocketSystem__GC0,
-case__264: VCU118RocketSystem__GC0,
-case__1310: APBGpsBlock__GCB1,
-case__771: RocketTile__GCB0,
-logic__3543: FPU__GB1,
-logic__1188: VCU118RocketSystem__GC0,
-case__375: RocketTile__GCB0,
-logic__6209: VCU118RocketSystem__GC0,
-logic__566: VCU118RocketSystem__GC0,
-case__1098: APBGpsBlock__GCB1,
-logic__400: VCU118RocketSystem__GC0,
-case__573: FPU__GB2,
-datapath__18: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2716: FPU__GB1,
-datapath__323: FPU__GB2,
-logic__484: VCU118RocketSystem__GC0,
-reg__956: VCU118RocketSystem__GC0,
-case__1392: tracking_wrapper,
-case__682: RocketTile__GCB0,
-logic__8501: tracking_wrapper,
-logic__2293: DCache,
-logic__6477: VCU118RocketSystem__GC0,
-logic__5354: RocketTile__GCB0,
-logic__7446: VCU118RocketSystem__GC0,
-reg__888: VCU118RocketSystem__GC0,
-case__1042: VCU118RocketSystem__GC0,
-counter__18: tracking_wrapper,
-case__1049: VCU118RocketSystem__GC0,
-logic__235: VCU118RocketSystem__GC0,
-logic__3932: FPU__GB2, FPU__GB1,
-logic__2649: RocketTile__GCB0,
-datapath__3: genesys2_rocket_top__GC0,
-reg__635: RocketTile__GCB0,
-logic__6686: VCU118RocketSystem__GC0,
-logic__6445: VCU118RocketSystem__GC0,
-logic__695: VCU118RocketSystem__GC0,
-reg__1413: APBGpsBlock__GCB0,
-case__156: VCU118RocketSystem__GC0,
-keep__42: genesys2_rocket_top__GC0,
-reg__873: VCU118RocketSystem__GC0,
-reg__1184: tracking_wrapper,
-logic__2875: FPU__GB1,
-logic__5317: RocketTile__GCB0,
-logic__6802: VCU118RocketSystem__GC0,
-case__92: VCU118RocketSystem__GC0,
-reg__340: RocketTile__GCB0,
-logic__3755: FPU__GB1,
-logic__3870: FPU__GB1,
-logic__2639: RocketTile__GCB0,
-case__1512: tracking_wrapper,
-logic__6179: VCU118RocketSystem__GC0,
-logic__2839: FPU__GB1,
-case__1489: tracking_wrapper,
-logic__6940: VCU118RocketSystem__GC0,
-reg__1429: APBGpsBlock__GCB0,
-reg__1273: tracking_wrapper,
-reg__667: RocketTile__GCB0,
-reg__682: RocketTile__GCB0,
-case__9: genesys2_rocket_top__GC0,
-logic__2200: DCache,
-datapath__348: FPU__GB1,
-rom__8: tracking_wrapper,
-muxpart__306: APBGpsBlock__GCB0,
-logic__3558: FPU__GB1,
-TLBuffer_a32d64s2k1z3u_1: TilePRCIDomain__GC0,
-logic__4116: FPU__GB2,
-logic__7138: VCU118RocketSystem__GC0,
-logic__6356: VCU118RocketSystem__GC0,
-logic__6245: VCU118RocketSystem__GC0,
-logic__359: VCU118RocketSystem__GC0,
-case__1469: tracking_wrapper,
-reg__1337: tracking_wrapper,
-logic__4311: FPU__GB1,
-reg__338: RocketTile__GCB0,
-logic__6731: VCU118RocketSystem__GC0,
-logic__1117: VCU118RocketSystem__GC0,
-case__371: DCache,
-logic__3878: FPU__GB1,
-logic__2465: RocketTile__GCB0,
-logic__8477: tracking_wrapper,
-logic__6762: VCU118RocketSystem__GC0,
-datapath__520: VCU118RocketSystem__GC0,
-logic__6576: VCU118RocketSystem__GC0,
-logic__2636: RocketTile__GCB0,
-reg__1030: APBGpsBlock__GCB1,
-logic__6788: VCU118RocketSystem__GC0,
-logic__9299: APBGpsBlock__GCB0,
-reg__735: RocketTile__GCB0,
-logic__5176: RocketTile__GCB0,
-logic__4707: RocketTile__GCB0,
-logic__2384: RocketTile__GCB0,
-logic__5431: RocketTile__GCB0,
-case__1603: APBGpsBlock__GCB0,
-logic__7718: APBGpsBlock__GCB1,
-logic__2815: FPU__GB1,
-reg__613: RocketTile__GCB0,
-reg__149: VCU118RocketSystem__GC0,
-logic__8266: APBGpsBlock__GCB0,
-logic__6042: RocketTile__GCB0,
-logic__2513: RocketTile__GCB0,
-logic__8588: tracking_wrapper,
-muxpart__33: FPU__GB0,
-case__777: RocketTile__GCB0,
-logic__1498: RocketTile__GCB0,
-logic__255: VCU118RocketSystem__GC0,
-datapath__220: VCU118RocketSystem__GC0,
-reg__835: VCU118RocketSystem__GC0,
-datapath__20: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__38: VCU118RocketSystem__GC0,
-logic__4112: FPU__GB2,
-logic__5063: RocketTile__GCB0,
-case__2: genesys2_rocket_top__GC0,
-reg__1363: APBGpsBlock__GCB0,
-TLDebugModule: VCU118RocketSystem__GC0,
-case__561: FPU__GB2,
-logic__105: VCU118RocketSystem__GC0,
-reg__1077: APBGpsBlock__GCB1,
-logic__7966: APBGpsBlock__GCB1,
-logic__6584: VCU118RocketSystem__GC0,
-reg__498: FPU__GB2,
-case__1383: tracking_wrapper,
-logic__6439: VCU118RocketSystem__GC0,
-case__1001: VCU118RocketSystem__GC0,
-logic__687: VCU118RocketSystem__GC0,
-logic__1844: RocketTile__GCB0, DCache,
-reg__810: VCU118RocketSystem__GC0,
-logic__8395: tracking_wrapper,
-case__1486: tracking_wrapper,
-case__850: VCU118RocketSystem__GC0,
-muxpart__29: FPU__GB0,
-cdc_fifo_gray_dst: tracking_wrapper,
-datapath__380: FPU__GB2,
-case__50: VCU118RocketSystem__GC0,
-reg__253: DCache,
-case__564: FPU__GB2,
-ram__1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__1010: VCU118RocketSystem__GC0,
-logic__7416: VCU118RocketSystem__GC0,
-logic__9330: APBGpsBlock__GCB0,
-logic__8774: tracking_wrapper,
-logic__2286: DCache,
-logic__6271: VCU118RocketSystem__GC0,
-logic__7904: APBGpsBlock__GCB1,
-datapath__370: FPU__GB2,
-logic__7583: VCU118RocketSystem__GC0,
-logic__135: VCU118RocketSystem__GC0,
-logic__4743: RocketTile__GCB0,
-reg__609: RocketTile__GCB0,
-logic__5492: RocketTile__GCB0,
-datapath__540: APBGpsBlock__GCB1,
-case__435: RocketTile__GCB0,
-case__628: RocketTile__GCB0,
-datapath__302: FPU__GB2, FPU__GB1,
-logic__1300: VCU118RocketSystem__GC0,
-logic__4847: RocketTile__GCB0,
-case__1295: APBGpsBlock__GCB1,
-datapath__678: tracking_wrapper,
-case__1299: APBGpsBlock__GCB1,
-addsub__1: tracking_wrapper,
-logic__2889: FPU__GB1,
-reg__598: RocketTile__GCB0,
-case__118: VCU118RocketSystem__GC0,
-reg__632: RocketTile__GCB0,
-reg__1317: tracking_wrapper,
-reg__914: VCU118RocketSystem__GC0,
-case__531: FPU__GB2, FPU__GB1,
-case__792: VCU118RocketSystem__GC0,
-datapath__27: VCU118RocketSystem__GC0,
-logic__2176: DCache,
-logic__1421: VCU118RocketSystem__GC0,
-reg__51: VCU118RocketSystem__GC0,
-logic__5655: RocketTile__GCB0,
-logic__2557: RocketTile__GCB0,
-reg__18: genesys2_rocket_top__GC0,
-logic__7807: APBGpsBlock__GCB1,
-reg__437: FPU__GB2,
-datapath__324: FPU__GB2,
-logic__6530: VCU118RocketSystem__GC0,
-logic__3797: FPU__GB1,
-case__288: VCU118RocketSystem__GC0,
-logic__8414: tracking_wrapper,
-logic__3295: FPU__GB2,
-case__995: VCU118RocketSystem__GC0,
-case__1690: TLToAPB,
-logic__4928: RocketTile__GCB0,
-case__1043: VCU118RocketSystem__GC0,
-logic__2359: RocketTile__GCB0,
-case__1173: APBGpsBlock__GCB1,
-case__38: VCU118RocketSystem__GC0,
-datapath__670: tracking_wrapper,
-case__76: VCU118RocketSystem__GC0,
-case__535: FPU__GB2, FPU__GB1,
-logic__138: VCU118RocketSystem__GC0,
-reg__1121: APBGpsBlock__GCB1,
-datapath__549: APBGpsBlock__GCB1,
-logic__2081: DCache,
-logic__1881: RocketTile__GCB0, DCache,
-logic__5330: RocketTile__GCB0,
-case__822: VCU118RocketSystem__GC0,
-TLBuffer_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__1962: DCache,
-case__547: FPU__GB2,
-logic__2916: FPU__GB1,
-case__1493: tracking_wrapper,
-reg__812: VCU118RocketSystem__GC0,
-logic__7816: APBGpsBlock__GCB1,
-case__527: FPU__GB2, FPU__GB1,
-case__188: VCU118RocketSystem__GC0,
-reg__1326: tracking_wrapper,
-logic__848: VCU118RocketSystem__GC0,
-logic__713: VCU118RocketSystem__GC0,
-reg__1345: APBGpsBlock__GCB0,
-reg__560: FPU__GB1,
-FPGASPIClockSinkDomain: VCU118RocketSystem__GC0,
-logic__1999: DCache,
-MulAddRecFNToRaw_postMul: FPU__GB1,
-reg__172: VCU118RocketSystem__GC0,
-case__684: RocketTile__GCB0,
-logic__6953: VCU118RocketSystem__GC0,
-counter__19: tracking_wrapper,
-logic__2469: RocketTile__GCB0,
-logic__2998: FPU__GB2, FPU__GB1,
-datapath__436: RocketTile__GCB0,
-logic__2551: RocketTile__GCB0,
-logic__4201: FPU__GB2,
-datapath__685: tracking_wrapper,
-case__399: RocketTile__GCB0,
-logic__6316: VCU118RocketSystem__GC0,
-logic__936: VCU118RocketSystem__GC0,
-logic__9346: TLToAPB,
-logic__8595: tracking_wrapper,
-case__683: RocketTile__GCB0,
-reg__231: RocketTile__GCB0,
-logic__4230: FPU__GB2,
-case__1360: tracking_wrapper,
-logic__8902: tracking_wrapper,
-logic__543: VCU118RocketSystem__GC0,
-reg__460: FPU__GB1,
-datapath__42: VCU118RocketSystem__GC0,
-case__648: RocketTile__GCB0,
-logic__236: VCU118RocketSystem__GC0,
-reg__1339: tracking_wrapper,
-reg__1173: tracking_wrapper,
-DivSqrtRecFN_small_1: FPU__GB2,
-case__566: FPU__GB2,
-logic__117: VCU118RocketSystem__GC0,
-reg__474: FPU__GB1,
-logic__8980: APBGpsBlock__GCB0,
-case__293: RocketTile__GCB0,
-datapath__156: VCU118RocketSystem__GC0,
-case__432: RocketTile__GCB0,
-reg__966: VCU118RocketSystem__GC0,
-logic__4785: RocketTile__GCB0,
-reg__824: VCU118RocketSystem__GC0,
-dsp48e1__35: tracking_wrapper,
-reg__1344: APBGpsBlock__GCB0,
-logic__7444: VCU118RocketSystem__GC0,
-case__888: VCU118RocketSystem__GC0,
-case__252: VCU118RocketSystem__GC0,
-logic__4748: RocketTile__GCB0,
-datapath__712: APBGpsBlock__GCB0,
-logic__251: VCU118RocketSystem__GC0,
-case__239: VCU118RocketSystem__GC0,
-logic__3787: FPU__GB1,
-reg__109: VCU118RocketSystem__GC0,
-logic__1459: RocketTile__GCB0,
-case__1428: tracking_wrapper,
-reg__237: DCache,
-logic__8409: tracking_wrapper,
-logic__8550: tracking_wrapper,
-case__1002: VCU118RocketSystem__GC0,
-logic__386: VCU118RocketSystem__GC0,
-logic__9117: APBGpsBlock__GCB0,
-datapath__387: FPU__GB1,
-logic__2432: RocketTile__GCB0,
-logic__6812: VCU118RocketSystem__GC0,
-case__1301: APBGpsBlock__GCB1,
-reg__1073: APBGpsBlock__GCB1,
-logic__4796: RocketTile__GCB0,
-logic__2128: DCache,
-logic__396: VCU118RocketSystem__GC0,
-case__492: FPU__GB2,
-reg__770: RocketTile__GCB0,
-reg__719: RocketTile__GCB0,
-logic__7702: VCU118RocketSystem__GC0,
-logic__6379: VCU118RocketSystem__GC0,
-reg__1191: tracking_wrapper,
-logic__5236: RocketTile__GCB0,
-logic__5206: RocketTile__GCB0,
-logic__6214: VCU118RocketSystem__GC0,
-logic__7709: APBGpsBlock__GCB1,
-logic__4334: FPU__GB1,
-logic__822: VCU118RocketSystem__GC0,
-case__115: VCU118RocketSystem__GC0,
-logic__8587: tracking_wrapper,
-reg__664: RocketTile__GCB0,
-logic__3852: FPU__GB1,
-datapath__710: APBGpsBlock__GCB0,
-case__106: VCU118RocketSystem__GC0,
-logic__8608: tracking_wrapper,
-logic__8310: tracking_wrapper,
-case__548: FPU__GB2,
-logic__5080: RocketTile__GCB0,
-logic__6524: VCU118RocketSystem__GC0,
-logic__4473: FPU__GB1,
-logic__9237: APBGpsBlock__GCB0,
-case__971: VCU118RocketSystem__GC0,
-case__1329: APBGpsBlock__GCB1,
-reg__154: VCU118RocketSystem__GC0,
-reg__275: DCache,
-reg__349: RocketTile__GCB0,
-logic__7569: VCU118RocketSystem__GC0,
-reg__333: RocketTile__GCB0,
-case__877: VCU118RocketSystem__GC0,
-datapath__536: APBGpsBlock__GCB1,
-reg__392: FPU__GB0,
-reg__961: VCU118RocketSystem__GC0,
-logic__4572: RocketTile__GCB0,
-DivSqrtRecFNToRaw_small: FPU__GB2,
-logic__4711: RocketTile__GCB0,
-logic__2724: FPU__GB1,
-case__1399: tracking_wrapper,
-logic__7264: VCU118RocketSystem__GC0,
-TLROM: VCU118RocketSystem__GC0,
-logic__7559: VCU118RocketSystem__GC0,
-logic__3520: FPU__GB2,
-logic__3776: FPU__GB1,
-logic__1158: VCU118RocketSystem__GC0,
-reg__1053: APBGpsBlock__GCB1,
-case__666: RocketTile__GCB0,
-reg__877: VCU118RocketSystem__GC0,
-datapath__89: VCU118RocketSystem__GC0,
-case__803: VCU118RocketSystem__GC0,
-reg__634: RocketTile__GCB0,
-logic__4650: RocketTile__GCB0,
-muxpart__21: FPU__GB0,
-reg__264: DCache,
-case__1342: tracking_wrapper,
-case__1287: APBGpsBlock__GCB1,
-logic__3311: FPU__GB2,
-reg__528: FPU__GB1,
-logic__6444: VCU118RocketSystem__GC0,
-logic__3451: FPU__GB2,
-reg__1215: tracking_wrapper,
-logic__3181: FPU__GB2,
-logic__4066: FPU__GB2,
-case__800: VCU118RocketSystem__GC0,
-case__232: VCU118RocketSystem__GC0,
-logic__959: VCU118RocketSystem__GC0,
-logic__6228: VCU118RocketSystem__GC0,
-logic__4695: RocketTile__GCB0,
-logic__5246: RocketTile__GCB0,
-muxpart__99: RocketTile__GCB0,
-logic__3969: FPU__GB2, FPU__GB1,
-case__534: FPU__GB2, FPU__GB1,
-logic__5978: RocketTile__GCB0,
-logic__4370: FPU__GB1,
-reg__1241: tracking_wrapper,
-case__317: DCache,
-logic__4803: RocketTile__GCB0,
-logic__4152: FPU__GB2,
-logic__7298: VCU118RocketSystem__GC0,
-case__545: FPU__GB2,
-logic__9298: APBGpsBlock__GCB0,
-datapath__490: VCU118RocketSystem__GC0,
-logic__5932: RocketTile__GCB0,
-reg__712: RocketTile__GCB0,
-logic__2953: FPU__GB1,
-reg__226: VCU118RocketSystem__GC0,
-logic__750: VCU118RocketSystem__GC0,
-case__100: VCU118RocketSystem__GC0,
-logic__1469: RocketTile__GCB0,
-logic__4498: FPU__GB1,
-logic__5220: RocketTile__GCB0,
-logic__1812: DCache,
-reg__1165: tracking_wrapper,
-case__229: VCU118RocketSystem__GC0,
-LF_carr: tracking_wrapper,
-logic__7579: VCU118RocketSystem__GC0,
-logic__352: VCU118RocketSystem__GC0,
-datapath__660: tracking_wrapper,
-logic__1392: VCU118RocketSystem__GC0,
-logic__6521: VCU118RocketSystem__GC0,
-datapath__61: VCU118RocketSystem__GC0,
-datapath__185: VCU118RocketSystem__GC0,
-datapath__41: VCU118RocketSystem__GC0,
-logic__7157: VCU118RocketSystem__GC0,
-logic__4860: RocketTile__GCB0,
-case__1445: tracking_wrapper,
-reg__232: RocketTile__GCB0,
-case__744: RocketTile__GCB0,
-logic__5219: RocketTile__GCB0,
-case__1410: tracking_wrapper,
-reg__558: FPU__GB1,
-logic__6813: VCU118RocketSystem__GC0,
-reg__34: VCU118RocketSystem__GC0,
-logic__140: VCU118RocketSystem__GC0,
-logic__5397: RocketTile__GCB0,
-datapath__307: FPU__GB2,
-reg__509: FPU__GB2,
-logic__847: VCU118RocketSystem__GC0,
-logic__649: VCU118RocketSystem__GC0,
-reg__771: RocketTile__GCB0,
-logic__230: VCU118RocketSystem__GC0,
-logic__3759: FPU__GB1,
-case__319: DCache,
-case__552: FPU__GB2,
-datapath__62: VCU118RocketSystem__GC0,
-rockettile_dcache_data_arrays_0_131072x64: DCache,
-logic__7130: VCU118RocketSystem__GC0,
-logic__118: VCU118RocketSystem__GC0,
-logic__5944: RocketTile__GCB0,
-logic__3542: FPU__GB1,
-case__1372: tracking_wrapper,
-reg__693: RocketTile__GCB0,
-logic__9163: APBGpsBlock__GCB0,
-logic__1899: RocketTile__GCB0, DCache,
-logic__785: VCU118RocketSystem__GC0,
-logic__834: VCU118RocketSystem__GC0,
-logic__282: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2486: RocketTile__GCB0,
-logic__3636: FPU__GB1,
-logic__8057: APBGpsBlock__GCB1,
-logic__4658: RocketTile__GCB0,
-logic__9351: TLToAPB,
-case__992: VCU118RocketSystem__GC0,
-logic__4082: FPU__GB2,
-logic__940: VCU118RocketSystem__GC0,
-logic__2416: RocketTile__GCB0,
-reg__709: RocketTile__GCB0,
-reg__71: VCU118RocketSystem__GC0,
-reg__836: VCU118RocketSystem__GC0, APBGpsBlock__GCB1, APBGpsBlock__GCB0,
-logic__8937: APBGpsBlock__GCB0,
-logic__1240: VCU118RocketSystem__GC0,
-logic__844: VCU118RocketSystem__GC0,
-Queue2_TLBundleD_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-TLXbar_dmixbar_i1_o2_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-reg__1213: tracking_wrapper,
-logic__3951: FPU__GB2, FPU__GB1,
-logic__3010: FPU__GB2, FPU__GB1,
-case__1417: tracking_wrapper,
-case__875: VCU118RocketSystem__GC0,
-logic__164: VCU118RocketSystem__GC0,
-logic__1038: VCU118RocketSystem__GC0,
-case__1338: APBGpsBlock__GCB0,
-reg__943: VCU118RocketSystem__GC0,
-logic__4882: RocketTile__GCB0,
-logic__5177: RocketTile__GCB0,
-reg__551: FPU__GB1,
-keep__28: APBGpsBlock__GCB0,
-logic__450: VCU118RocketSystem__GC0,
-logic__1539: DCache,
-reg__683: RocketTile__GCB0,
-logic__6458: VCU118RocketSystem__GC0,
-dsp48e1__46: tracking_wrapper,
-logic__6779: VCU118RocketSystem__GC0,
-datapath__603: APBGpsBlock__GCB1,
-logic__6710: VCU118RocketSystem__GC0,
-logic__1080: VCU118RocketSystem__GC0,
-muxpart__227: tracking_wrapper,
-logic__8502: tracking_wrapper,
-logic__5691: RocketTile__GCB0,
-logic__1268: VCU118RocketSystem__GC0,
-case__256: VCU118RocketSystem__GC0,
-logic__3300: FPU__GB2,
-reg__821: VCU118RocketSystem__GC0,
-logic__2860: FPU__GB1,
-logic__8719: tracking_wrapper,
-case__1639: APBGpsBlock__GCB0,
-logic__6435: VCU118RocketSystem__GC0,
-logic__5493: RocketTile__GCB0,
-logic__4696: RocketTile__GCB0,
-logic__6683: VCU118RocketSystem__GC0,
-logic__8693: tracking_wrapper,
-logic__4870: RocketTile__GCB0,
-reg__1240: tracking_wrapper,
-case__536: FPU__GB1,
-reg__665: RocketTile__GCB0,
-logic__3011: FPU__GB2, FPU__GB1,
-logic__3377: FPU__GB2,
-logic__4995: RocketTile__GCB0,
-logic__8659: tracking_wrapper,
-reg__458: FPU__GB1,
-logic__8083: APBGpsBlock__GCB1,
-logic__4061: FPU__GB2,
-muxpart__149: APBGpsBlock__GCB1,
-logic__7567: VCU118RocketSystem__GC0,
-logic__1259: VCU118RocketSystem__GC0,
-logic__1696: DCache,
-logic__4407: FPU__GB1,
-logic__1977: DCache,
-case__1439: tracking_wrapper,
-case__1433: tracking_wrapper,
-case__719: RocketTile__GCB0,
-logic__2273: DCache,
-case__5: genesys2_rocket_top__GC0,
-logic__4806: RocketTile__GCB0,
-logic__6130: VCU118RocketSystem__GC0,
-reg__220: VCU118RocketSystem__GC0,
-logic__2388: RocketTile__GCB0,
-reg__309: RocketTile__GCB0,
-logic__6846: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a12d64s2k1z3u: VCU118RocketSystem__GC0,
-reg__31: VCU118RocketSystem__GC0,
-logic__4802: RocketTile__GCB0,
-datapath__662: tracking_wrapper,
-reg__1455: TLToAPB,
-logic__4363: FPU__GB1,
-logic__2738: FPU__GB1,
-datapath__328: FPU__GB2,
-reg__1058: APBGpsBlock__GCB1,
-logic__3778: FPU__GB1,
-logic__259: VCU118RocketSystem__GC0,
-reg__395: FPU__GB0,
-logic__6774: VCU118RocketSystem__GC0,
-datapath__568: APBGpsBlock__GCB1,
-logic__2029: DCache,
-extram__4: APBGpsBlock__GCB1,
-logic__4813: RocketTile__GCB0,
-logic__1557: DCache,
-logic__9362: TLToAPB,
-logic__5250: RocketTile__GCB0,
-logic__782: VCU118RocketSystem__GC0,
-reg__1078: APBGpsBlock__GCB1,
-case__1511: tracking_wrapper,
-logic__4359: FPU__GB1,
-logic__2699: FPU__GB1,
-datapath__326: FPU__GB2,
-logic__6735: VCU118RocketSystem__GC0,
-logic__1098: VCU118RocketSystem__GC0,
-logic__3635: FPU__GB1,
-logic__7231: VCU118RocketSystem__GC0,
-logic__1174: VCU118RocketSystem__GC0,
-muxpart__28: FPU__GB0,
-LevelGateway: VCU118RocketSystem__GC0,
-case__213: VCU118RocketSystem__GC0,
-Arbiter4_DCacheDataReq: DCache,
-logic__7600: VCU118RocketSystem__GC0,
-logic__4783: RocketTile__GCB0,
-logic__7620: VCU118RocketSystem__GC0,
-datapath__596: APBGpsBlock__GCB1,
-reg__214: VCU118RocketSystem__GC0,
-logic__1528: DCache,
-logic__6991: VCU118RocketSystem__GC0,
-case__312: DCache,
-logic__3849: FPU__GB1,
-reg__72: VCU118RocketSystem__GC0,
-reg__1338: tracking_wrapper,
-reg__1300: tracking_wrapper,
-case__699: RocketTile__GCB0,
-logic__8746: tracking_wrapper,
-logic__2484: RocketTile__GCB0,
-ShiftQueue: RocketTile__GCB0,
-reg__246: DCache,
-reg__921: VCU118RocketSystem__GC0,
-datapath__11: VCU118RocketSystem__GC0,
-counter__27: APBGpsBlock__GCB0,
-logic__1981: DCache,
-case__471: FPU__GB2,
-logic__2059: DCache,
-reg__897: VCU118RocketSystem__GC0,
-case__1307: APBGpsBlock__GCB1,
-logic__7003: VCU118RocketSystem__GC0,
-logic__9137: APBGpsBlock__GCB0,
-reg__960: VCU118RocketSystem__GC0,
-datapath__450: RocketTile__GCB0,
-logic__2732: FPU__GB1,
-logic__5404: RocketTile__GCB0,
-case__391: RocketTile__GCB0,
-datapath__204: VCU118RocketSystem__GC0,
-logic__3853: FPU__GB1,
-logic__7419: VCU118RocketSystem__GC0,
-case__1389: tracking_wrapper,
-case__1541: APBGpsBlock__GCB0,
-logic__6335: VCU118RocketSystem__GC0,
-datapath__581: APBGpsBlock__GCB1,
-logic__978: VCU118RocketSystem__GC0,
-logic__8207: APBGpsBlock__GCB1,
-case__1239: APBGpsBlock__GCB1,
-logic__5526: RocketTile__GCB0,
-logic__2320: DCache,
-logic__6594: VCU118RocketSystem__GC0,
-logic__889: VCU118RocketSystem__GC0,
-case__973: VCU118RocketSystem__GC0,
-logic__7111: VCU118RocketSystem__GC0,
-case__1680: TLToAPB,
-reg__1188: tracking_wrapper,
-case__1448: tracking_wrapper,
-ICache: RocketTile__GCB0,
-logic__2647: RocketTile__GCB0,
-logic__8720: tracking_wrapper,
-logic__1343: VCU118RocketSystem__GC0,
-muxpart__85: FPU__GB0,
-logic__1540: DCache,
-case__658: RocketTile__GCB0,
-logic__6423: VCU118RocketSystem__GC0,
-reg__1139: tracking_wrapper,
-TLInterconnectCoupler_pbus_to_gps: VCU118RocketSystem__GC0,
-logic__1021: VCU118RocketSystem__GC0,
-logic__633: VCU118RocketSystem__GC0,
-logic__9291: APBGpsBlock__GCB0,
-logic__4389: FPU__GB2,
-logic__3366: FPU__GB2,
-Queue1_RegMapperInput_i9_m8: VCU118RocketSystem__GC0,
-logic__2711: FPU__GB1,
-logic__3665: FPU__GB1,
-logic__3793: FPU__GB1,
-datapath__573: APBGpsBlock__GCB1,
-logic__2310: DCache,
-case__642: RocketTile__GCB0,
-logic__887: VCU118RocketSystem__GC0,
-reg__1120: APBGpsBlock__GCB1,
-case__696: RocketTile__GCB0,
-reg__289: DCache,
-logic__6180: VCU118RocketSystem__GC0,
-case__73: VCU118RocketSystem__GC0,
-reg__15: genesys2_rocket_top__GC0,
-logic__7208: VCU118RocketSystem__GC0,
-logic__613: VCU118RocketSystem__GC0,
-logic__7572: VCU118RocketSystem__GC0,
-reg__982: VCU118RocketSystem__GC0,
-reg__113: VCU118RocketSystem__GC0,
-logic__8446: tracking_wrapper,
-datapath__231: VCU118RocketSystem__GC0,
-logic__2888: FPU__GB1,
-logic__8399: tracking_wrapper,
-logic__4058: FPU__GB2,
-logic__3796: FPU__GB1,
-logic__664: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-PMPChecker_s3: DCache,
-case__1197: APBGpsBlock__GCB1,
-logic__5341: RocketTile__GCB0,
-case__1464: tracking_wrapper,
-case__30: VCU118RocketSystem__GC0,
-logic__2919: FPU__GB1,
-logic__7568: VCU118RocketSystem__GC0,
-logic__6120: VCU118RocketSystem__GC0,
-logic__567: VCU118RocketSystem__GC0,
-reg__391: FPU__GB0,
-reg__1423: APBGpsBlock__GCB0,
-logic__1517: DCache,
-reg__1412: APBGpsBlock__GCB0,
-reg__55: VCU118RocketSystem__GC0,
-reg__1351: APBGpsBlock__GCB0,
-reg__248: DCache,
-reg__628: RocketTile__GCB0,
-logic__4127: FPU__GB2,
-logic__4292: FPU__GB2,
-logic__7271: VCU118RocketSystem__GC0,
-case__388: RocketTile__GCB0,
-logic__6732: VCU118RocketSystem__GC0,
-logic__6367: VCU118RocketSystem__GC0,
-logic__8054: APBGpsBlock__GCB1,
-datapath__381: FPU__GB2,
-datapath__138: VCU118RocketSystem__GC0,
-logic__6665: VCU118RocketSystem__GC0,
-logic__348: VCU118RocketSystem__GC0,
-logic__8802: tracking_wrapper,
-logic__7004: VCU118RocketSystem__GC0,
-logic__6658: VCU118RocketSystem__GC0,
-logic__3554: FPU__GB1,
-case__1289: APBGpsBlock__GCB1,
-datapath__693: APBGpsBlock__GCB0,
-datapath__137: VCU118RocketSystem__GC0,
-reg__469: FPU__GB1,
-IntXbar_i2_o1: VCU118RocketSystem__GC0,
-logic__8921: APBGpsBlock__GCB0,
-logic__4630: RocketTile__GCB0,
-logic__8251: APBGpsBlock__GCB1,
-logic__9386: genesys2_rocket_top__GC0,
-logic__6566: VCU118RocketSystem__GC0,
-counter__4: VCU118RocketSystem__GC0,
-logic__4852: RocketTile__GCB0,
-logic__2939: FPU__GB1,
-logic__1965: DCache,
-logic__6390: VCU118RocketSystem__GC0,
-case__818: VCU118RocketSystem__GC0,
-logic__5525: RocketTile__GCB0,
-plusarg_reader: RocketTile__GCB0,
-logic__6672: VCU118RocketSystem__GC0,
-case__1308: APBGpsBlock__GCB1,
-case__1291: APBGpsBlock__GCB1,
-logic__8398: tracking_wrapper,
-logic__8271: tracking_wrapper,
-reg__1355: APBGpsBlock__GCB0,
-logic__8914: APBGpsBlock__GCB0,
-datapath__191: VCU118RocketSystem__GC0,
-datapath__95: VCU118RocketSystem__GC0,
-case__1394: tracking_wrapper,
-case__1243: APBGpsBlock__GCB1,
-reg__1037: APBGpsBlock__GCB1,
-case__751: RocketTile__GCB0,
-reg__639: RocketTile__GCB0,
-reg__1031: APBGpsBlock__GCB1,
-logic__4412: FPU__GB1,
-reg__408: FPU__GB1,
-logic__1215: VCU118RocketSystem__GC0,
-logic__6226: VCU118RocketSystem__GC0,
-case__128: VCU118RocketSystem__GC0,
-reg__327: RocketTile__GCB0,
-reg__736: RocketTile__GCB0,
-logic__6816: VCU118RocketSystem__GC0,
-Repeater_TLBundleD_a32d64s1k1z4u: VCU118RocketSystem__GC0,
-case__328: DCache,
-datapath__96: VCU118RocketSystem__GC0,
-logic__6798: VCU118RocketSystem__GC0,
-reg__1195: tracking_wrapper,
-logic__8071: APBGpsBlock__GCB1,
-keep__32: APBGpsBlock__GCB0,
-logic__9347: TLToAPB,
-reg__506: FPU__GB2,
-logic__5913: RocketTile__GCB0,
-logic__4090: FPU__GB2,
-logic__1193: VCU118RocketSystem__GC0,
-datapath__365: FPU__GB2,
-datapath__99: VCU118RocketSystem__GC0,
-reg__1142: tracking_wrapper,
-reg__387: FPU__GB0,
-logic__9383: genesys2_rocket_top__GC0,
-logic__6976: VCU118RocketSystem__GC0,
-logic__6560: VCU118RocketSystem__GC0,
-datapath__443: RocketTile__GCB0,
-case__108: VCU118RocketSystem__GC0,
-logic__4149: FPU__GB2,
-datapath__692: APBGpsBlock__GCB0,
-datapath__378: FPU__GB2,
-datapath__421: RocketTile__GCB0,
-logic__8789: tracking_wrapper,
-case__685: RocketTile__GCB0,
-case__413: RocketTile__GCB0,
-case__1676: APBGpsBlock__GCB1,
-case__1017: VCU118RocketSystem__GC0,
-case__1032: VCU118RocketSystem__GC0,
-logic__264: VCU118RocketSystem__GC0,
-reg__1024: APBGpsBlock__GCB1,
-logic__1330: VCU118RocketSystem__GC0,
-logic__4997: RocketTile__GCB0,
-logic__4463: FPU__GB0,
-case__926: VCU118RocketSystem__GC0,
-logic__8418: tracking_wrapper,
-logic__2613: RocketTile__GCB0,
-case__259: VCU118RocketSystem__GC0,
-code_loop_discriminator: tracking_wrapper,
-logic__890: VCU118RocketSystem__GC0,
-reg__476: FPU__GB1,
-case__1225: APBGpsBlock__GCB1,
-logic__6061: RocketTile__GCB0,
-logic__8428: tracking_wrapper,
-logic__6463: VCU118RocketSystem__GC0,
-logic__7665: VCU118RocketSystem__GC0,
-logic__6736: VCU118RocketSystem__GC0,
-case__233: VCU118RocketSystem__GC0,
-case__208: VCU118RocketSystem__GC0,
-logic__2683: RocketTile__GCB0,
-dsp48e1__31: tracking_wrapper,
-logic__1346: VCU118RocketSystem__GC0,
-Queue2_TLBundleD_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-case__311: DCache,
-logic__6449: VCU118RocketSystem__GC0,
-case__1337: APBGpsBlock__GCB1,
-logic__7546: VCU118RocketSystem__GC0,
-logic__5417: RocketTile__GCB0,
-TLInterconnectCoupler_cbus_to_clint: VCU118RocketSystem__GC0,
-logic__6114: VCU118RocketSystem__GC0,
-reg__442: FPU__GB2,
-datapath__511: VCU118RocketSystem__GC0,
-case__396: RocketTile__GCB0,
-logic__3250: FPU__GB2,
-logic__6391: VCU118RocketSystem__GC0,
-logic__220: VCU118RocketSystem__GC0,
-logic__102: VCU118RocketSystem__GC0,
-logic__8280: tracking_wrapper,
-logic__9240: APBGpsBlock__GCB0,
-logic__5368: RocketTile__GCB0,
-reg__822: VCU118RocketSystem__GC0,
-datapath__690: tracking_wrapper,
-reg__1408: APBGpsBlock__GCB0,
-logic__2149: DCache,
-logic__6229: VCU118RocketSystem__GC0,
-datapath__101: VCU118RocketSystem__GC0,
-datapath__503: VCU118RocketSystem__GC0,
-datapath__199: VCU118RocketSystem__GC0,
-reg__714: RocketTile__GCB0,
-logic__5433: RocketTile__GCB0,
-reg__669: RocketTile__GCB0,
-RoundAnyRawFNToRecFN: FPU__GB2, FPU__GB1,
-logic__7399: VCU118RocketSystem__GC0,
-logic__401: VCU118RocketSystem__GC0,
-logic__1961: DCache,
-reg__1105: APBGpsBlock__GCB1,
-logic__1361: VCU118RocketSystem__GC0,
-reg__967: VCU118RocketSystem__GC0,
-case__1058: VCU118RocketSystem__GC0,
-datapath__43: VCU118RocketSystem__GC0,
-logic__2861: FPU__GB1,
-case__724: RocketTile__GCB0,
-case__245: VCU118RocketSystem__GC0,
-TLWidthWidget8: VCU118RocketSystem__GC0,
-logic__7100: VCU118RocketSystem__GC0,
-reg__384: FPU__GB0,
-reg__1247: tracking_wrapper,
-case__932: VCU118RocketSystem__GC0,
-logic__5451: RocketTile__GCB0,
-logic__8447: tracking_wrapper,
-case__834: VCU118RocketSystem__GC0,
-reg__1334: tracking_wrapper,
-logic__3718: FPU__GB1,
-case__168: VCU118RocketSystem__GC0,
-muxpart__208: tracking_wrapper,
-logic__7288: VCU118RocketSystem__GC0,
-muxpart__22: FPU__GB0,
-logic__1736: DCache,
-reg__998: VCU118RocketSystem__GC0,
-logic__7497: VCU118RocketSystem__GC0,
-reg__1290: tracking_wrapper,
-logic__941: VCU118RocketSystem__GC0,
-case__1545: APBGpsBlock__GCB0,
-reg__260: DCache,
-logic__2280: DCache,
-reg__1271: tracking_wrapper,
-reg__569: FPU__GB1,
-case__1133: APBGpsBlock__GCB1,
-logic__6666: VCU118RocketSystem__GC0,
-logic__9181: APBGpsBlock__GCB0,
-logic__1984: DCache,
-case__136: VCU118RocketSystem__GC0,
-logic__4160: FPU__GB2,
-logic__6786: VCU118RocketSystem__GC0,
-logic__6770: VCU118RocketSystem__GC0,
-datapath__452: RocketTile__GCB0,
-reg__1122: APBGpsBlock__GCB0,
-logic__4844: RocketTile__GCB0,
-logic__5366: RocketTile__GCB0,
-reg__703: RocketTile__GCB0,
-logic__6772: VCU118RocketSystem__GC0,
-logic__5972: RocketTile__GCB0,
-logic__6401: VCU118RocketSystem__GC0,
-logic__3783: FPU__GB1,
-datapath__645: tracking_wrapper,
-reg__249: DCache,
-case__1359: tracking_wrapper,
-logic__2514: RocketTile__GCB0,
-reg__1444: APBGpsBlock__GCB0,
-logic__681: VCU118RocketSystem__GC0,
-logic__3801: FPU__GB1,
-datapath__663: tracking_wrapper,
-logic__2309: DCache,
-logic__190: VCU118RocketSystem__GC0,
-datapath__298: FPU__GB2, FPU__GB1,
-case__204: VCU118RocketSystem__GC0,
-reg__710: RocketTile__GCB0,
-logic__8718: tracking_wrapper,
-reg__1069: APBGpsBlock__GCB1,
-logic__5555: RocketTile__GCB0,
-logic__6344: VCU118RocketSystem__GC0,
-logic__3567: FPU__GB1,
-datapath__704: APBGpsBlock__GCB0,
-TLAsyncCrossingSink_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-datapath__30: VCU118RocketSystem__GC0,
-case__429: RocketTile__GCB0,
-logic__3700: FPU__GB1,
-logic__6511: VCU118RocketSystem__GC0,
-keep__40: APBGpsBlock__GCB0,
-reg__494: FPU__GB1,
-logic__266: VCU118RocketSystem__GC0,
-logic__4301: FPU__GB1,
-logic__5096: RocketTile__GCB0,
-case__1106: APBGpsBlock__GCB1,
-logic__3792: FPU__GB1,
-logic__653: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6500: VCU118RocketSystem__GC0,
-reg__625: RocketTile__GCB0,
-logic__1764: DCache,
-reg__421: FPU__GB1,
-datapath__218: VCU118RocketSystem__GC0,
-case__231: VCU118RocketSystem__GC0,
-datapath__132: VCU118RocketSystem__GC0,
-case__34: VCU118RocketSystem__GC0,
-reg__1201: tracking_wrapper,
-logic__3541: FPU__GB1,
-datapath__420: RocketTile__GCB0,
-logic__6206: VCU118RocketSystem__GC0,
-TLBuffer_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__9377: TLToAPB,
-case__1172: APBGpsBlock__GCB1,
-extram__5: APBGpsBlock__GCB1,
-datapath__696: APBGpsBlock__GCB0,
-logic__3697: FPU__GB1,
-reg__91: VCU118RocketSystem__GC0,
-logic__2727: FPU__GB1,
-logic__6704: VCU118RocketSystem__GC0,
-muxpart__7: VCU118RocketSystem__GC0,
-logic__3758: FPU__GB1,
-logic__5471: RocketTile__GCB0,
-logic__4718: RocketTile__GCB0,
-logic__3952: FPU__GB2, FPU__GB1,
-logic__3575: FPU__GB1,
-logic__5171: RocketTile__GCB0,
-datapath__310: FPU__GB2,
-keep__41: genesys2_rocket_top__GC0,
-datapath__313: FPU__GB2,
-case__880: VCU118RocketSystem__GC0,
-logic__770: VCU118RocketSystem__GC0,
-logic__2407: RocketTile__GCB0,
-logic__702: VCU118RocketSystem__GC0,
-logic__3802: FPU__GB1,
-logic__7277: VCU118RocketSystem__GC0,
-logic__8419: tracking_wrapper,
-dsp48e1__26: APBGpsBlock__GCB1,
-TLWidthWidget8_1: VCU118RocketSystem__GC0, RocketTile__GCB0,
-case__1434: tracking_wrapper,
-case__1663: APBGpsBlock__GCB0,
-logic__4445: FPU__GB1,
-logic__8256: APBGpsBlock__GCB0,
-logic__6220: VCU118RocketSystem__GC0,
-reg__905: VCU118RocketSystem__GC0,
-datapath__702: APBGpsBlock__GCB0,
-logic__4961: RocketTile__GCB0,
-logic__3715: FPU__GB1,
-logic__4751: RocketTile__GCB0,
-logic__1551: DCache,
-logic__7578: VCU118RocketSystem__GC0,
-reg__1435: APBGpsBlock__GCB0,
-reg__1057: APBGpsBlock__GCB1,
-logic__2612: RocketTile__GCB0,
-reg__968: VCU118RocketSystem__GC0,
-logic__6339: VCU118RocketSystem__GC0,
-reg__764: RocketTile__GCB0,
-reg__432: FPU__GB1,
-logic__1035: VCU118RocketSystem__GC0,
-logic__439: VCU118RocketSystem__GC0,
-case__1143: APBGpsBlock__GCB1,
-datapath__640: tracking_wrapper,
-datapath__256: DCache,
-datapath__228: VCU118RocketSystem__GC0,
-datapath__397: RocketTile__GCB0,
-reg__1179: tracking_wrapper,
-case__506: FPU__GB1,
-reg: genesys2_rocket_top__GC0,
-datapath__141: VCU118RocketSystem__GC0,
-datapath__585: APBGpsBlock__GCB1,
-logic__1664: DCache,
-logic__3696: FPU__GB1,
-datapath__731: APBGpsBlock__GCB0,
-reg__530: FPU__GB1,
-reg__1106: APBGpsBlock__GCB1,
-case__774: RocketTile__GCB0,
-datapath__661: tracking_wrapper,
-logic__2882: FPU__GB1,
-logic__3779: FPU__GB1,
-logic__6164: VCU118RocketSystem__GC0,
-logic__4584: RocketTile__GCB0,
-logic__8408: tracking_wrapper,
-logic__6140: VCU118RocketSystem__GC0,
-mult_53_53_106: FPU__GB1,
-logic__7426: VCU118RocketSystem__GC0,
-case__397: RocketTile__GCB0,
-case__1102: APBGpsBlock__GCB1,
-case__80: VCU118RocketSystem__GC0,
-case__793: VCU118RocketSystem__GC0,
-reg__1084: APBGpsBlock__GCB1,
-datapath__311: FPU__GB2,
-logic__7564: VCU118RocketSystem__GC0,
-logic__8076: APBGpsBlock__GCB1,
-logic__1583: DCache,
-logic__1149: VCU118RocketSystem__GC0,
-logic__589: VCU118RocketSystem__GC0,
-logic__8051: APBGpsBlock__GCB1,
-reg__590: RocketTile__GCB0,
-logic__8803: tracking_wrapper,
-logic__2884: FPU__GB1,
-logic__5929: RocketTile__GCB0,
-reg__283: DCache,
-datapath__636: tracking_wrapper,
-logic__4449: FPU__GB1,
-logic__223: VCU118RocketSystem__GC0,
-logic__4495: FPU__GB1,
-case__652: RocketTile__GCB0,
-reg__131: VCU118RocketSystem__GC0,
-reg__65: VCU118RocketSystem__GC0,
-reg__674: RocketTile__GCB0,
-logic__4369: FPU__GB1,
-logic__8347: tracking_wrapper,
-logic__1569: DCache,
-logic__620: VCU118RocketSystem__GC0,
-logic__1605: DCache,
-logic__5896: RocketTile__GCB0,
-logic__233: VCU118RocketSystem__GC0,
-logic__700: VCU118RocketSystem__GC0,
-datapath__665: tracking_wrapper,
-logic__6678: VCU118RocketSystem__GC0,
-logic__353: VCU118RocketSystem__GC0,
-reg__215: VCU118RocketSystem__GC0,
-logic__1542: DCache,
-logic__6348: VCU118RocketSystem__GC0,
-logic__3957: FPU__GB2, FPU__GB1,
-reg__377: FPU__GB0,
-reg__611: RocketTile__GCB0,
-case__77: VCU118RocketSystem__GC0,
-logic__8896: tracking_wrapper,
-FPUFMAPipe_l4_f64: FPU__GB1,
-logic__6697: VCU118RocketSystem__GC0,
-case__730: RocketTile__GCB0,
-case__1671: APBGpsBlock__GCB0,
-TLInterconnectCoupler_cbus_to_debug: VCU118RocketSystem__GC0,
-muxpart__65: FPU__GB0,
-logic__3807: FPU__GB1,
-logic__6627: VCU118RocketSystem__GC0,
-logic__7117: VCU118RocketSystem__GC0,
-logic__6909: VCU118RocketSystem__GC0,
-reg__367: RocketTile__GCB0,
-reg__257: DCache,
-logic__3080: FPU__GB2,
-case__791: VCU118RocketSystem__GC0,
-case__704: RocketTile__GCB0,
-logic__728: VCU118RocketSystem__GC0,
-reg__431: FPU__GB1,
-reg__553: FPU__GB1,
-reg__1376: APBGpsBlock__GCB0,
-reg__666: RocketTile__GCB0,
-logic__2125: DCache,
-case__537: FPU__GB2,
-logic__3477: FPU__GB2,
-logic__7629: VCU118RocketSystem__GC0,
-logic__3417: FPU__GB2,
-logic__6694: VCU118RocketSystem__GC0,
-reg__753: RocketTile__GCB0,
-dsp48e1__45: tracking_wrapper,
-reg__891: VCU118RocketSystem__GC0,
-logic__4618: RocketTile__GCB0,
-case__589: FPU__GB1,
-dsp48e1__9: APBGpsBlock__GCB1,
-reg__1430: APBGpsBlock__GCB0,
-logic__8591: tracking_wrapper,
-reg__58: VCU118RocketSystem__GC0,
-reg__616: RocketTile__GCB0,
-datapath__638: tracking_wrapper,
-reg__1381: APBGpsBlock__GCB0,
-logic__919: VCU118RocketSystem__GC0,
-case__947: VCU118RocketSystem__GC0,
-logic__1187: VCU118RocketSystem__GC0,
-dsp48e1: FPU__GB1,
-datapath__304: FPU__GB2,
-reg__508: FPU__GB2,
-reg__828: VCU118RocketSystem__GC0,
-datapath__170: VCU118RocketSystem__GC0,
-logic__1833: DCache,
-case__215: VCU118RocketSystem__GC0,
-logic__2588: RocketTile__GCB0,
-muxpart__78: FPU__GB0,
-logic__6224: VCU118RocketSystem__GC0,
-case__934: VCU118RocketSystem__GC0,
-logic__8172: APBGpsBlock__GCB1,
-logic__2630: RocketTile__GCB0,
-datapath__104: VCU118RocketSystem__GC0,
-logic__6807: VCU118RocketSystem__GC0,
-logic__8316: tracking_wrapper,
-logic__512: VCU118RocketSystem__GC0,
-case__669: RocketTile__GCB0,
-Repeater_TLBundleA_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__849: VCU118RocketSystem__GC0,
-datapath__605: APBGpsBlock__GCB1,
-logic__3521: FPU__GB2,
-logic__6055: RocketTile__GCB0,
-logic__6689: VCU118RocketSystem__GC0,
-case__753: RocketTile__GCB0,
-datapath__172: VCU118RocketSystem__GC0,
-datapath__143: VCU118RocketSystem__GC0,
-logic__6764: VCU118RocketSystem__GC0,
-fft_radix_2__parameterized1: APBGpsBlock__GCB1,
-logic__2580: RocketTile__GCB0,
-case__1510: tracking_wrapper,
-logic__6215: VCU118RocketSystem__GC0,
-case__49: VCU118RocketSystem__GC0,
-case__1198: APBGpsBlock__GCB1,
-reg__743: RocketTile__GCB0,
-datapath__519: VCU118RocketSystem__GC0,
-logic__4501: FPU__GB1,
-logic__3004: FPU__GB2, FPU__GB1,
-logic__8760: tracking_wrapper,
-logic__6831: VCU118RocketSystem__GC0,
-case__645: RocketTile__GCB0,
-logic__4947: RocketTile__GCB0,
-logic__817: VCU118RocketSystem__GC0,
-reg__618: RocketTile__GCB0,
-reg__725: RocketTile__GCB0,
-logic__3408: FPU__GB2,
-reg__90: VCU118RocketSystem__GC0,
-reg__1257: tracking_wrapper,
-logic__3788: FPU__GB1,
-logic__8790: tracking_wrapper,
-case__10: genesys2_rocket_top__GC0,
-logic__6482: VCU118RocketSystem__GC0,
-logic__3211: FPU__GB2,
-datapath__459: RocketTile__GCB0,
-case__418: RocketTile__GCB0,
-reg__134: VCU118RocketSystem__GC0,
-AsyncQueueSource_TLBundleD_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-datapath__719: APBGpsBlock__GCB0,
-logic__809: VCU118RocketSystem__GC0,
-datapath__611: APBGpsBlock__GCB1,
-case__656: RocketTile__GCB0,
-logic__3944: FPU__GB2, FPU__GB1,
-reg__262: DCache,
-datapath__349: FPU__GB1,
-reg__510: FPU__GB2,
-case__968: VCU118RocketSystem__GC0,
-logic__2709: FPU__GB1,
-reg__839: VCU118RocketSystem__GC0,
-logic__6691: VCU118RocketSystem__GC0,
-logic__6606: VCU118RocketSystem__GC0,
-TLWidthWidget8_2: VCU118RocketSystem__GC0,
-logic__273: VCU118RocketSystem__GC0,
-datapath__590: APBGpsBlock__GCB1,
-logic__6965: VCU118RocketSystem__GC0,
-reg__1395: APBGpsBlock__GCB0,
-logic__754: VCU118RocketSystem__GC0,
-case__930: VCU118RocketSystem__GC0,
-reg__1235: tracking_wrapper,
-reg__695: RocketTile__GCB0,
-logic__9150: APBGpsBlock__GCB0,
-datapath__202: VCU118RocketSystem__GC0,
-reg__799: VCU118RocketSystem__GC0,
-logic__1051: VCU118RocketSystem__GC0,
-FrontBus: VCU118RocketSystem__GC0,
-TLXbar_cbus_out_i1_o7_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-case__967: VCU118RocketSystem__GC0,
-case__1673: APBGpsBlock__GCB1,
-reg__130: VCU118RocketSystem__GC0,
-datapath__563: APBGpsBlock__GCB1,
-logic__4271: FPU__GB2,
-reg__244: DCache,
-logic__971: VCU118RocketSystem__GC0,
-logic__2290: DCache,
-logic__1900: RocketTile__GCB0, DCache,
-case__1412: tracking_wrapper,
-logic__7401: VCU118RocketSystem__GC0,
-datapath__171: VCU118RocketSystem__GC0,
-muxpart__315: APBGpsBlock__GCB0,
-case__248: VCU118RocketSystem__GC0,
-reg__1119: APBGpsBlock__GCB1,
-logic__4186: FPU__GB2,
-reg__1145: tracking_wrapper,
-logic__65: genesys2_rocket_top__GC0,
-reg__817: VCU118RocketSystem__GC0,
-logic__4033: FPU__GB2,
-datapath__160: VCU118RocketSystem__GC0,
-logic__6883: VCU118RocketSystem__GC0,
-reg__1323: tracking_wrapper,
-datapath__689: tracking_wrapper,
-addsub__4: tracking_wrapper,
-reg__838: VCU118RocketSystem__GC0, APBGpsBlock__GCB1, APBGpsBlock__GCB0,
-logic__6293: VCU118RocketSystem__GC0,
-logic__668: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__225: VCU118RocketSystem__GC0,
-logic__6058: RocketTile__GCB0,
-keep__30: APBGpsBlock__GCB0,
-muxpart__56: FPU__GB0,
-logic__945: VCU118RocketSystem__GC0,
-logic__187: VCU118RocketSystem__GC0,
-reg__22: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__862: VCU118RocketSystem__GC0,
-reg__156: VCU118RocketSystem__GC0,
-logic__1: genesys2_rocket_top__GC0,
-case__1033: VCU118RocketSystem__GC0,
-case__27: VCU118RocketSystem__GC0,
-logic__6334: VCU118RocketSystem__GC0,
-case__1460: tracking_wrapper,
-datapath__502: VCU118RocketSystem__GC0,
-reg__1068: APBGpsBlock__GCB1,
-counter__37: APBGpsBlock__GCB0,
-logic__1896: RocketTile__GCB0, DCache,
-logic__4753: RocketTile__GCB0,
-reg__1353: APBGpsBlock__GCB0,
-reg__547: FPU__GB1,
-logic__8764: tracking_wrapper,
-case__1020: VCU118RocketSystem__GC0,
-logic__7571: VCU118RocketSystem__GC0,
-logic__5371: RocketTile__GCB0,
-logic__147: VCU118RocketSystem__GC0,
-case__225: VCU118RocketSystem__GC0,
-case__1100: APBGpsBlock__GCB1,
-logic__2692: RocketTile__GCB0,
-reg__1267: tracking_wrapper,
-logic__5207: RocketTile__GCB0,
-case__863: VCU118RocketSystem__GC0,
-reg__1307: tracking_wrapper,
-logic__211: VCU118RocketSystem__GC0,
-reg__352: RocketTile__GCB0,
-logic__4868: RocketTile__GCB0,
-logic__9129: APBGpsBlock__GCB0,
-logic__8604: tracking_wrapper,
-logic__1935: DCache,
-reg__188: VCU118RocketSystem__GC0,
-dsp48e1__42: tracking_wrapper,
-logic__1590: DCache,
-datapath__329: FPU__GB2,
-logic__8478: tracking_wrapper,
-case__579: FPU__GB1,
-logic__6283: VCU118RocketSystem__GC0,
-TLWidthWidget1: VCU118RocketSystem__GC0,
-logic__4279: FPU__GB2,
-case__1137: APBGpsBlock__GCB1,
-logic__6513: VCU118RocketSystem__GC0,
-case__36: VCU118RocketSystem__GC0,
-logic__5915: RocketTile__GCB0,
-logic__1963: DCache,
-case__759: RocketTile__GCB0,
-case__695: RocketTile__GCB0,
-logic__6561: VCU118RocketSystem__GC0,
-case__643: RocketTile__GCB0,
-logic__2584: RocketTile__GCB0,
-logic__4863: RocketTile__GCB0,
-logic__8357: tracking_wrapper,
-case__766: RocketTile__GCB0,
-TLXbar_fbus_i1_o1_a32d64s1k1z4u: VCU118RocketSystem__GC0,
-logic__751: VCU118RocketSystem__GC0,
-logic__830: VCU118RocketSystem__GC0,
-muxpart__114: VCU118RocketSystem__GC0,
-logic__3786: FPU__GB1,
-datapath__117: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4018: FPU__GB1,
-reg__446: FPU__GB2,
-logic__6081: RocketTile__GCB0,
-case__1364: tracking_wrapper,
-logic__4138: FPU__GB2,
-logic__6393: VCU118RocketSystem__GC0,
-case__305: RocketTile__GCB0,
-logic__2827: FPU__GB1,
-case__1007: VCU118RocketSystem__GC0,
-reg__406: FPU__GB1,
-case__1540: APBGpsBlock__GCB0,
-reg__276: DCache,
-muxpart__80: FPU__GB0,
-case__595: FPU__GB1,
-logic__3075: FPU__GB1,
-logic__4694: RocketTile__GCB0,
-logic__9208: APBGpsBlock__GCB0,
-datapath__253: DCache,
-logic__1522: DCache,
-logic__4755: RocketTile__GCB0,
-logic__18: genesys2_rocket_top__GC0,
-reg__204: VCU118RocketSystem__GC0,
-reg__42: VCU118RocketSystem__GC0,
-case__621: RocketTile__GCB0,
-logic__2731: FPU__GB1,
-reg__479: FPU__GB1,
-logic__2508: RocketTile__GCB0,
-reg__931: VCU118RocketSystem__GC0,
-logic__4227: FPU__GB2,
-logic__9303: APBGpsBlock__GCB0,
-datapath__492: VCU118RocketSystem__GC0,
-logic__1818: DCache,
-logic__300: VCU118RocketSystem__GC0,
-case__631: RocketTile__GCB0,
-logic__8627: tracking_wrapper,
-logic__6643: VCU118RocketSystem__GC0,
-addsub: APBGpsBlock__GCB1,
-FPUDecoder: FPU__GB1,
-logic__9116: APBGpsBlock__GCB0,
-counter__8: APBGpsBlock__GCB1,
-logic__4577: RocketTile__GCB0,
-logic__6893: VCU118RocketSystem__GC0,
-logic__6565: VCU118RocketSystem__GC0,
-logic__326: VCU118RocketSystem__GC0,
-case__1194: APBGpsBlock__GCB1,
-reg__447: FPU__GB2,
-case__715: RocketTile__GCB0,
-logic__9334: APBGpsBlock__GCB1,
-muxpart__305: APBGpsBlock__GCB0,
-logic__1595: DCache,
-logic__843: VCU118RocketSystem__GC0,
-datapath__697: APBGpsBlock__GCB0,
-logic__975: VCU118RocketSystem__GC0,
-logic__6616: VCU118RocketSystem__GC0,
-reg__1199: tracking_wrapper,
-dsp48e1__44: tracking_wrapper,
-reg__875: VCU118RocketSystem__GC0,
-logic__1983: DCache,
-logic__4862: RocketTile__GCB0,
-logic__1243: VCU118RocketSystem__GC0,
-datapath__238: RocketTile__GCB0,
-logic__3948: FPU__GB2, FPU__GB1,
-case__366: DCache,
-logic__5674: RocketTile__GCB0,
-logic__5044: RocketTile__GCB0,
-logic__527: VCU118RocketSystem__GC0,
-case__384: RocketTile__GCB0,
-logic__496: VCU118RocketSystem__GC0,
-case__263: VCU118RocketSystem__GC0,
-logic__2106: DCache,
-logic__4302: FPU__GB1,
-reg__857: VCU118RocketSystem__GC0,
-reg__640: RocketTile__GCB0,
-logic__1279: VCU118RocketSystem__GC0,
-logic__3774: FPU__GB1,
-logic__8307: tracking_wrapper,
-case__1057: VCU118RocketSystem__GC0,
-logic__1478: RocketTile__GCB0,
-case__339: DCache,
-reg__499: FPU__GB2,
-reg__992: VCU118RocketSystem__GC0,
-case__223: VCU118RocketSystem__GC0,
-case__131: VCU118RocketSystem__GC0,
-datapath__440: RocketTile__GCB0,
-logic__1998: DCache,
-case__1435: tracking_wrapper,
-case__1145: APBGpsBlock__GCB1,
-logic__2414: RocketTile__GCB0,
-logic__6595: VCU118RocketSystem__GC0,
-logic__313: VCU118RocketSystem__GC0,
-datapath__733: APBGpsBlock__GCB0,
-extladd: RocketTile__GCB0,
-reg__1294: tracking_wrapper,
-case__289: VCU118RocketSystem__GC0,
-case__659: RocketTile__GCB0,
-logic__332: VCU118RocketSystem__GC0,
-logic__3973: FPU__GB2, FPU__GB1,
-logic__5165: RocketTile__GCB0,
-FPU__GB2: FPU__GB2,
-case__1675: APBGpsBlock__GCB1,
-logic__8737: tracking_wrapper,
-logic__7889: APBGpsBlock__GCB1,
-PMPChecker_s2: RocketTile__GCB0,
-datapath__224: VCU118RocketSystem__GC0,
-dsp48e1__28: APBGpsBlock__GCB1,
-case__483: FPU__GB2,
-muxpart__68: FPU__GB0,
-reg__33: VCU118RocketSystem__GC0,
-logic__119: VCU118RocketSystem__GC0,
-logic__1982: DCache,
-case__308: RocketTile__GCB0,
-logic__7435: VCU118RocketSystem__GC0,
-logic__7684: VCU118RocketSystem__GC0,
-datapath__214: VCU118RocketSystem__GC0,
-logic__691: VCU118RocketSystem__GC0,
-datapath__613: APBGpsBlock__GCB1,
-logic__4812: RocketTile__GCB0,
-logic__9113: APBGpsBlock__GCB0,
-datapath__195: VCU118RocketSystem__GC0,
-logic__2625: RocketTile__GCB0,
-case__706: RocketTile__GCB0,
-logic__6815: VCU118RocketSystem__GC0,
-datapath__206: VCU118RocketSystem__GC0,
-case__1524: tracking_wrapper,
-logic__7027: VCU118RocketSystem__GC0,
-case__565: FPU__GB2,
-logic__5060: RocketTile__GCB0,
-logic__825: VCU118RocketSystem__GC0,
-logic__8736: tracking_wrapper,
-logic__8969: APBGpsBlock__GCB0,
-logic__3795: FPU__GB1,
-case__56: VCU118RocketSystem__GC0,
-logic__2062: DCache,
-logic__924: VCU118RocketSystem__GC0,
-reg__17: genesys2_rocket_top__GC0,
-reg__1197: tracking_wrapper,
-logic__6675: VCU118RocketSystem__GC0,
-reg__844: VCU118RocketSystem__GC0,
-logic__9175: APBGpsBlock__GCB0,
-case__1361: tracking_wrapper,
-reg__502: FPU__GB2,
-logic__9149: APBGpsBlock__GCB0,
-case__977: VCU118RocketSystem__GC0,
-case__644: RocketTile__GCB0,
-case__557: FPU__GB2,
-gray_to_binary: tracking_wrapper,
-NCO_carr: tracking_wrapper,
-datapath__372: FPU__GB2,
-case__1241: APBGpsBlock__GCB1,
-logic__2698: FPU__GB1,
-logic__5690: RocketTile__GCB0,
-datapath__629: tracking_wrapper,
-logic__1472: RocketTile__GCB0,
-case__1683: TLToAPB,
-case__550: FPU__GB2,
-logic__930: VCU118RocketSystem__GC0,
-logic__8304: tracking_wrapper,
-logic__4649: RocketTile__GCB0,
-logic__7246: VCU118RocketSystem__GC0,
-reg__312: RocketTile__GCB0,
-logic__4479: FPU__GB1,
-logic__5994: RocketTile__GCB0,
-pps_wrapper: APBGpsBlock__GCB0,
-logic__2404: RocketTile__GCB0,
-logic__7458: VCU118RocketSystem__GC0,
-case__1612: APBGpsBlock__GCB0,
-case__807: VCU118RocketSystem__GC0,
-mult_66_66_66: RocketTile__GCB0,
-reg__688: RocketTile__GCB0,
-logic__2445: RocketTile__GCB0,
-logic__3502: FPU__GB2,
-reg__1113: APBGpsBlock__GCB1,
-logic__3756: FPU__GB1,
-logic__1385: VCU118RocketSystem__GC0,
-datapath__9: VCU118RocketSystem__GC0,
-case__923: VCU118RocketSystem__GC0,
-reg__805: VCU118RocketSystem__GC0,
-reg__602: RocketTile__GCB0,
-TLDebugModuleOuter: VCU118RocketSystem__GC0,
-logic__6851: VCU118RocketSystem__GC0,
-TLXbar_cbus_in_i1_o1_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__1644: DCache,
-reg__671: RocketTile__GCB0,
-logic__5552: RocketTile__GCB0,
-reg__24: VCU118RocketSystem__GC0,
-logic__3499: FPU__GB2,
-logic__6376: VCU118RocketSystem__GC0,
-VCU118RocketSystem__GC0: VCU118RocketSystem__GC0,
-muxpart__58: FPU__GB0,
-reg__1259: tracking_wrapper,
-Arbiter8_DCacheMetadataReq: DCache,
-logic__1114: VCU118RocketSystem__GC0,
-TLBuffer_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-reg__122: VCU118RocketSystem__GC0,
-logic__206: VCU118RocketSystem__GC0,
-case__711: RocketTile__GCB0,
-logic__7072: VCU118RocketSystem__GC0,
-datapath__155: VCU118RocketSystem__GC0,
-logic__2190: DCache,
-reg__592: RocketTile__GCB0,
-ResetCatchAndSync_d3: APBGpsBlock__GCB1, APBGpsBlock__GCB0,
-logic__6632: VCU118RocketSystem__GC0,
-case__812: VCU118RocketSystem__GC0,
-reg__194: VCU118RocketSystem__GC0,
-logic__7404: VCU118RocketSystem__GC0,
-case__935: VCU118RocketSystem__GC0,
-datapath__586: APBGpsBlock__GCB1,
-datapath__634: tracking_wrapper,
-logic__9151: APBGpsBlock__GCB0,
-logic__6507: VCU118RocketSystem__GC0,
-datapath__207: VCU118RocketSystem__GC0,
-logic__6201: VCU118RocketSystem__GC0,
-reg__1375: APBGpsBlock__GCB0,
-reg__717: RocketTile__GCB0,
-reg__274: DCache,
-case__320: DCache,
-logic__6327: VCU118RocketSystem__GC0,
-case__196: VCU118RocketSystem__GC0,
-logic__965: VCU118RocketSystem__GC0,
-reg__1318: tracking_wrapper,
-logic__96: genesys2_rocket_top__GC0,
-logic__3660: FPU__GB1,
-logic__8351: tracking_wrapper,
-reg__826: VCU118RocketSystem__GC0,
-logic__8544: tracking_wrapper,
-case__186: VCU118RocketSystem__GC0,
-muxpart__49: FPU__GB0,
-keep__20: APBGpsBlock__GCB0,
-RecFNToRecFN: FPU__GB1,
-reg__403: FPU__GB1,
-logic__7624: VCU118RocketSystem__GC0,
-logic__970: VCU118RocketSystem__GC0,
-logic__2247: DCache,
-logic__4253: FPU__GB2,
-logic__8517: tracking_wrapper,
-divider_fsm: APBGpsBlock__GCB1,
-dsp48e1__41: tracking_wrapper,
-reg__855: VCU118RocketSystem__GC0,
-case__1624: APBGpsBlock__GCB0,
-datapath__161: VCU118RocketSystem__GC0,
-logic__3097: FPU__GB2,
-logic__1524: DCache,
-spill_register_flushable: tracking_wrapper,
-acq_corr: APBGpsBlock__GCB1,
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0: VCU118RocketSystem__GC0, APBGpsBlock__GCB1, APBGpsBlock__GCB0,
-case__1443: tracking_wrapper,
-logic__6333: VCU118RocketSystem__GC0,
-logic__891: VCU118RocketSystem__GC0,
-logic__2898: FPU__GB1,
-reg__1299: tracking_wrapper,
-muxpart__72: FPU__GB0,
-logic__8665: tracking_wrapper,
-datapath__522: VCU118RocketSystem__GC0,
-logic__2596: RocketTile__GCB0,
-case__662: RocketTile__GCB0,
-reg__815: VCU118RocketSystem__GC0,
-logic__2028: DCache,
-logic__1658: DCache,
-dual_port_bram: APBGpsBlock__GCB1,
-case__882: VCU118RocketSystem__GC0,
-reg__1437: APBGpsBlock__GCB0,
-case__832: VCU118RocketSystem__GC0,
-reg__294: RocketTile__GCB0,
-logic__3798: FPU__GB1,
-logic__4521: RocketTile__GCB0,
-acq_wrapper: APBGpsBlock__GCB1,
-reg__197: VCU118RocketSystem__GC0,
-case__90: VCU118RocketSystem__GC0,
-datapath__83: VCU118RocketSystem__GC0,
-case__1521: tracking_wrapper,
-case__230: VCU118RocketSystem__GC0,
-logic__689: VCU118RocketSystem__GC0,
-reg__1266: tracking_wrapper,
-case__416: RocketTile__GCB0,
-logic__1165: VCU118RocketSystem__GC0,
-logic__3212: FPU__GB2,
-logic__7163: VCU118RocketSystem__GC0,
-logic__4417: FPU__GB1,
-reg__546: FPU__GB1,
-reg__501: FPU__GB2,
-logic__2179: DCache,
-reg__606: RocketTile__GCB0,
-case__1183: APBGpsBlock__GCB1,
-case__948: VCU118RocketSystem__GC0,
-reg__614: RocketTile__GCB0,
-logic__2850: FPU__GB1,
-logic__1576: DCache,
-extram__8: APBGpsBlock__GCB1,
-logic__2995: FPU__GB2, FPU__GB1,
-datapath__680: tracking_wrapper,
-reg__1442: APBGpsBlock__GCB0,
-case__681: RocketTile__GCB0,
-logic__4257: FPU__GB2,
-case__997: VCU118RocketSystem__GC0,
-logic__6538: VCU118RocketSystem__GC0,
-logic__4738: RocketTile__GCB0,
-logic__6649: VCU118RocketSystem__GC0,
-datapath__213: VCU118RocketSystem__GC0,
-TLAtomicAutomata_cbus: VCU118RocketSystem__GC0,
-datapath__601: APBGpsBlock__GCB1,
-case__1094: APBGpsBlock__GCB1,
-reg__490: FPU__GB1,
-case__946: VCU118RocketSystem__GC0,
-datapath__139: VCU118RocketSystem__GC0,
-logic__2277: DCache,
-reg__1150: tracking_wrapper,
-logic__4031: FPU__GB2,
-logic__1202: VCU118RocketSystem__GC0,
-logic__2027: DCache,
-regfile_32x65: FPU__GB0,
-reg__1070: APBGpsBlock__GCB1,
-logic__260: VCU118RocketSystem__GC0,
-logic__2816: FPU__GB1,
-logic__55: genesys2_rocket_top__GC0,
-logic__4349: FPU__GB2,
-logic__1637: DCache,
-logic__1005: VCU118RocketSystem__GC0,
-datapath__167: VCU118RocketSystem__GC0,
-case__458: FPU__GB2, FPU__GB1,
-Queue2_TLBundleD_a29d64s2k1z3u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4784: RocketTile__GCB0,
-logic__7181: VCU118RocketSystem__GC0,
-logic__3101: FPU__GB2,
-reg__142: VCU118RocketSystem__GC0,
-logic__6508: VCU118RocketSystem__GC0,
-datapath__375: FPU__GB2,
-case__109: VCU118RocketSystem__GC0,
-logic__1979: DCache,
-logic__5203: RocketTile__GCB0,
-logic__1575: DCache,
-case__1415: tracking_wrapper,
-logic__1630: DCache,
-logic__7562: VCU118RocketSystem__GC0,
-logic__6462: VCU118RocketSystem__GC0,
-case__484: FPU__GB2,
-logic__51: genesys2_rocket_top__GC0,
-case__1367: tracking_wrapper,
-reg__1198: tracking_wrapper,
-logic__263: VCU118RocketSystem__GC0,
-logic__7213: VCU118RocketSystem__GC0,
-reg__1316: tracking_wrapper,
-reg__807: VCU118RocketSystem__GC0,
-case__452: FPU__GB1,
-dsp48e1__47: tracking_wrapper,
-reg__1221: tracking_wrapper,
-case__155: VCU118RocketSystem__GC0,
-logic__4875: RocketTile__GCB0,
-logic__177: VCU118RocketSystem__GC0,
-reg__1313: tracking_wrapper,
-logic__2408: RocketTile__GCB0,
-logic__2806: FPU__GB1,
-logic__7366: VCU118RocketSystem__GC0,
-case__1376: tracking_wrapper,
-datapath__407: RocketTile__GCB0,
-logic__6522: VCU118RocketSystem__GC0,
-logic__4139: FPU__GB2,
-logic__3643: FPU__GB1,
-logic__6385: VCU118RocketSystem__GC0,
-datapath__168: VCU118RocketSystem__GC0,
-logic__136: VCU118RocketSystem__GC0,
-logic__5229: RocketTile__GCB0,
-case__1622: APBGpsBlock__GCB0,
-reg__1125: APBGpsBlock__GCB0,
-logic__4950: RocketTile__GCB0,
-logic__8831: tracking_wrapper,
-logic__1371: VCU118RocketSystem__GC0,
-logic__6783: VCU118RocketSystem__GC0,
-case__178: VCU118RocketSystem__GC0,
-reg__765: RocketTile__GCB0,
-logic__1631: DCache,
-logic__3791: FPU__GB1,
-logic__3780: FPU__GB1,
-case__1191: APBGpsBlock__GCB1,
-logic__3644: FPU__GB1,
-datapath__499: VCU118RocketSystem__GC0,
-muxpart__12: DCache,
-datapath__694: APBGpsBlock__GCB0,
-logic__1016: VCU118RocketSystem__GC0,
-case__917: VCU118RocketSystem__GC0,
-logic__6610: VCU118RocketSystem__GC0,
-logic__4804: RocketTile__GCB0,
-datapath__338: FPU__GB1,
-datapath__339: FPU__GB1,
-logic__893: VCU118RocketSystem__GC0,
-logic__8956: APBGpsBlock__GCB0,
-logic__4752: RocketTile__GCB0,
-reg__906: VCU118RocketSystem__GC0,
-logic__2107: DCache,
-logic__1939: DCache,
-case__392: RocketTile__GCB0,
-logic__6264: VCU118RocketSystem__GC0,
-reg__766: RocketTile__GCB0,
-logic__1431: RocketTile__GCB0,
-logic__7511: VCU118RocketSystem__GC0,
-DMIToTL: VCU118RocketSystem__GC0,
-logic__8661: tracking_wrapper,
-case__407: RocketTile__GCB0,
-logic__2017: DCache,
-reg__320: RocketTile__GCB0,
-logic__4101: FPU__GB2,
-logic__5453: RocketTile__GCB0,
-logic__6506: VCU118RocketSystem__GC0,
-logic__5255: RocketTile__GCB0,
-logic__5168: RocketTile__GCB0,
-logic__4219: FPU__GB2,
-reg__747: RocketTile__GCB0,
-datapath__264: RocketTile__GCB0,
-logic__982: VCU118RocketSystem__GC0,
-reg__115: VCU118RocketSystem__GC0,
-dsp48e1__25: APBGpsBlock__GCB1,
-case__1668: APBGpsBlock__GCB0,
-case__1637: APBGpsBlock__GCB0,
-case__459: FPU__GB2, FPU__GB1,
-datapath__368: FPU__GB2,
-case__220: VCU118RocketSystem__GC0,
-logic__191: VCU118RocketSystem__GC0,
-logic__7180: VCU118RocketSystem__GC0,
-logic__6337: VCU118RocketSystem__GC0,
-case__1626: APBGpsBlock__GCB0,
-logic__4426: FPU__GB1,
-case__978: VCU118RocketSystem__GC0,
-reg__94: VCU118RocketSystem__GC0,
-logic__799: VCU118RocketSystem__GC0,
-logic__2370: RocketTile__GCB0,
-logic__1586: DCache,
-case__870: VCU118RocketSystem__GC0,
-logic__4268: FPU__GB2,
-logic__1153: VCU118RocketSystem__GC0,
-logic__964: VCU118RocketSystem__GC0,
-reg__591: RocketTile__GCB0,
-logic__351: VCU118RocketSystem__GC0,
-datapath__501: VCU118RocketSystem__GC0,
-datapath__671: tracking_wrapper,
-RoundAnyRawFNToRecFN_2: FPU__GB2,
-reg__463: FPU__GB1,
-logic__5210: RocketTile__GCB0,
-reg__20: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4583: RocketTile__GCB0,
-case__21: genesys2_rocket_top__GC0,
-case__873: VCU118RocketSystem__GC0,
-Rocket: RocketTile__GCB0,
-reg__866: VCU118RocketSystem__GC0,
-reg__79: VCU118RocketSystem__GC0,
-reg__306: RocketTile__GCB0,
-reg__208: VCU118RocketSystem__GC0,
-datapath__198: VCU118RocketSystem__GC0,
-counter__11: APBGpsBlock__GCB1,
-reg__1297: tracking_wrapper,
-datapath__217: VCU118RocketSystem__GC0,
-logic__3191: FPU__GB2,
-logic__393: VCU118RocketSystem__GC0,
-case__331: DCache,
-case__456: FPU__GB1,
-logic__8763: tracking_wrapper,
-logic__6254: VCU118RocketSystem__GC0,
-logic__688: VCU118RocketSystem__GC0,
-logic__5706: RocketTile__GCB0,
-case__99: VCU118RocketSystem__GC0,
-logic__6087: RocketTile__GCB0,
-logic__5342: RocketTile__GCB0,
-logic__6440: VCU118RocketSystem__GC0,
-logic__8723: tracking_wrapper,
-logic__6690: VCU118RocketSystem__GC0,
-case__1542: APBGpsBlock__GCB0,
-case__1230: APBGpsBlock__GCB1,
-logic__8262: APBGpsBlock__GCB0,
-datapath__393: RocketTile__GCB0,
-case__123: VCU118RocketSystem__GC0,
-logic__5409: RocketTile__GCB0,
-case__826: VCU118RocketSystem__GC0,
-datapath__205: VCU118RocketSystem__GC0,
-case__797: VCU118RocketSystem__GC0,
-logic__6795: VCU118RocketSystem__GC0,
-logic__3431: FPU__GB2,
-logic__6006: RocketTile__GCB0,
-logic__8062: APBGpsBlock__GCB1,
-reg__937: VCU118RocketSystem__GC0,
-AsyncQueueSink_TLBundleA_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-reg__1302: tracking_wrapper,
-DivSqrtRecFNToRaw_small_1: FPU__GB2,
-logic__4580: RocketTile__GCB0,
-logic__4491: FPU__GB1,
-datapath__22: VCU118RocketSystem__GC0,
-case__354: DCache,
-logic__389: VCU118RocketSystem__GC0,
-reg__1043: APBGpsBlock__GCB1,
-case__984: VCU118RocketSystem__GC0,
-case__78: VCU118RocketSystem__GC0,
-datapath__416: RocketTile__GCB0,
-case__318: DCache,
-logic__7612: VCU118RocketSystem__GC0,
-logic__1978: DCache,
-logic__7614: VCU118RocketSystem__GC0,
-logic__1004: VCU118RocketSystem__GC0,
-logic__8322: tracking_wrapper,
-logic__8702: tracking_wrapper,
-logic__7496: VCU118RocketSystem__GC0,
-reg__96: VCU118RocketSystem__GC0,
-case__915: VCU118RocketSystem__GC0,
-logic__7105: VCU118RocketSystem__GC0,
-reg__227: VCU118RocketSystem__GC0,
-datapath__507: VCU118RocketSystem__GC0,
-datapath__192: VCU118RocketSystem__GC0,
-logic__4378: FPU__GB1,
-logic__6138: VCU118RocketSystem__GC0,
-case__171: VCU118RocketSystem__GC0,
-datapath__609: APBGpsBlock__GCB1,
-logic__5000: RocketTile__GCB0,
-case__844: VCU118RocketSystem__GC0,
-logic__3183: FPU__GB2,
-logic__6970: VCU118RocketSystem__GC0,
-case__983: VCU118RocketSystem__GC0,
-logic__8301: tracking_wrapper,
-logic__3157: FPU__GB2,
-datapath__489: VCU118RocketSystem__GC0,
-logic__3074: FPU__GB1,
-reg__397: FPU__GB0,
-logic__2356: RocketTile__GCB0,
-case__453: FPU__GB1,
-muxpart__24: FPU__GB0,
-case__323: DCache,
-datapath__267: RocketTile__GCB0,
-logic__6558: VCU118RocketSystem__GC0,
-logic__1541: DCache,
-logic__4166: FPU__GB2,
-logic__4333: FPU__GB1,
-case__378: RocketTile__GCB0,
-logic__6049: RocketTile__GCB0,
-reg__818: VCU118RocketSystem__GC0,
-muxpart__224: tracking_wrapper,
-reg__63: VCU118RocketSystem__GC0,
-logic__3775: FPU__GB1,
-case__588: FPU__GB1,
-logic__7724: APBGpsBlock__GCB1,
-logic__2412: RocketTile__GCB0,
-case__364: DCache,
-reg__878: VCU118RocketSystem__GC0,
-case__192: VCU118RocketSystem__GC0,
-case__62: VCU118RocketSystem__GC0,
-logic__5225: RocketTile__GCB0,
-logic__3963: FPU__GB2, FPU__GB1,
-IntSyncAsyncCrossingSink_n1x1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__957: VCU118RocketSystem__GC0,
-logic__8148: APBGpsBlock__GCB1,
-logic__5990: RocketTile__GCB0,
-muxpart__225: tracking_wrapper,
-logic__7016: VCU118RocketSystem__GC0,
-logic__5331: RocketTile__GCB0,
-case__1672: APBGpsBlock__GCB0,
-datapath__371: FPU__GB2,
-logic__7400: VCU118RocketSystem__GC0,
-logic__8951: APBGpsBlock__GCB0,
-logic__6241: VCU118RocketSystem__GC0,
-logic__1415: VCU118RocketSystem__GC0,
-logic__1465: RocketTile__GCB0,
-logic__446: VCU118RocketSystem__GC0,
-logic__8721: tracking_wrapper,
-reg__555: FPU__GB1,
-logic__327: VCU118RocketSystem__GC0,
-case__707: RocketTile__GCB0,
-logic__6034: RocketTile__GCB0,
-case__478: FPU__GB2,
-logic__1002: VCU118RocketSystem__GC0,
-logic__4256: FPU__GB2,
-logic__1205: VCU118RocketSystem__GC0,
-case__999: VCU118RocketSystem__GC0,
-logic__5904: RocketTile__GCB0,
-logic__8750: tracking_wrapper,
-logic__6679: VCU118RocketSystem__GC0,
-reg__1369: APBGpsBlock__GCB0,
-datapath__366: FPU__GB2,
-datapath__606: APBGpsBlock__GCB1,
-logic__2321: DCache,
-logic__4419: FPU__GB1,
-case__507: FPU__GB1,
-logic__7808: APBGpsBlock__GCB1,
-logic__7060: VCU118RocketSystem__GC0,
-INToRecFN_1: FPU__GB2,
-reg__620: RocketTile__GCB0,
-reg__101: VCU118RocketSystem__GC0,
-datapath__495: VCU118RocketSystem__GC0,
-reg__577: FPU__GB1,
-muxpart__81: FPU__GB0,
-reg__861: VCU118RocketSystem__GC0,
-datapath__357: FPU__GB2, FPU__GB1,
-reg__608: RocketTile__GCB0,
-muxpart__30: FPU__GB0,
-logic__6580: VCU118RocketSystem__GC0,
-logic__6532: VCU118RocketSystem__GC0,
-logic__6343: VCU118RocketSystem__GC0,
-case__634: RocketTile__GCB0,
-case__324: DCache,
-logic__7150: VCU118RocketSystem__GC0,
-cordic_angle_lut__parameterized0: tracking_wrapper,
-logic__8975: APBGpsBlock__GCB0,
-logic__6030: RocketTile__GCB0,
-muxpart__319: APBGpsBlock__GCB0,
-logic__4287: FPU__GB2,
-logic__6060: RocketTile__GCB0,
-rockettile_icache_data_arrays_512x32: RocketTile__GCB0,
-logic__2650: RocketTile__GCB0,
-reg__456: FPU__GB1,
-reg__1141: tracking_wrapper,
-logic__7334: VCU118RocketSystem__GC0,
-reg__67: VCU118RocketSystem__GC0,
-logic__5040: RocketTile__GCB0,
-logic__6635: VCU118RocketSystem__GC0,
-logic__1414: VCU118RocketSystem__GC0,
-case__1148: APBGpsBlock__GCB1,
-case__296: RocketTile__GCB0,
-logic__6261: VCU118RocketSystem__GC0,
-reg__1220: tracking_wrapper,
-logic__6915: VCU118RocketSystem__GC0,
-muxpart__314: APBGpsBlock__GCB0,
-reg__668: RocketTile__GCB0,
-logic__3854: FPU__GB1,
-case__1515: tracking_wrapper,
-logic__4159: FPU__GB2,
-logic__5240: RocketTile__GCB0,
-logic__5301: RocketTile__GCB0,
-case__329: DCache,
-FixedClockBroadcast_1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6250: VCU118RocketSystem__GC0,
-case__1129: APBGpsBlock__GCB1,
-case__982: VCU118RocketSystem__GC0,
-logic__7291: VCU118RocketSystem__GC0,
-logic__6464: VCU118RocketSystem__GC0,
-reg__427: FPU__GB1,
-logic__5899: RocketTile__GCB0,
-case__849: VCU118RocketSystem__GC0,
-case__424: RocketTile__GCB0,
-logic__611: VCU118RocketSystem__GC0,
-logic__8457: tracking_wrapper,
-logic__7896: APBGpsBlock__GCB1,
-case__12: genesys2_rocket_top__GC0,
-logic__4953: RocketTile__GCB0,
-reg__880: VCU118RocketSystem__GC0,
-logic__4778: RocketTile__GCB0,
-logic__9329: APBGpsBlock__GCB1,
-case__495: FPU__GB2,
-logic__6046: RocketTile__GCB0,
-reg__471: FPU__GB1,
-logic__3800: FPU__GB1,
-case__276: VCU118RocketSystem__GC0,
-reg__1278: tracking_wrapper,
-reg__1226: tracking_wrapper,
-reg__21: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2011: DCache,
-datapath__394: RocketTile__GCB0,
-reg__1066: APBGpsBlock__GCB1,
-case__356: DCache,
-reg__159: VCU118RocketSystem__GC0,
-case__785: RocketTile__GCB0,
-reg__708: RocketTile__GCB0,
-logic__8540: tracking_wrapper,
-logic__6207: VCU118RocketSystem__GC0,
-reg__443: FPU__GB2,
-logic__8761: tracking_wrapper,
-logic__2695: FPU__GB1,
-logic__2956: FPU__GB1,
-case__990: VCU118RocketSystem__GC0,
-datapath__543: APBGpsBlock__GCB1,
-case__961: VCU118RocketSystem__GC0,
-datapath__107: VCU118RocketSystem__GC0,
-case__1614: APBGpsBlock__GCB0,
-case__641: RocketTile__GCB0,
-logic__9107: APBGpsBlock__GCB0,
-logic__3578: FPU__GB1,
-logic__1025: VCU118RocketSystem__GC0,
-logic__379: VCU118RocketSystem__GC0,
-case__83: VCU118RocketSystem__GC0,
-reg__135: VCU118RocketSystem__GC0,
-case__1379: tracking_wrapper,
-logic__8899: tracking_wrapper,
-reg__313: RocketTile__GCB0,
-logic__1100: VCU118RocketSystem__GC0,
-bootromClockSinkDomain: VCU118RocketSystem__GC0,
-case__966: VCU118RocketSystem__GC0,
-reg__1384: APBGpsBlock__GCB0,
-reg__1292: tracking_wrapper,
-logic__942: VCU118RocketSystem__GC0,
-dsp48e1__39: tracking_wrapper,
-logic__8848: tracking_wrapper,
-case__633: RocketTile__GCB0,
-reg__1251: tracking_wrapper,
-NonSyncResetSynchronizerPrimitiveShiftReg_d3: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__9199: APBGpsBlock__GCB0,
-case__103: VCU118RocketSystem__GC0,
-case__1339: tracking_wrapper,
-datapath__438: RocketTile__GCB0,
-case__551: FPU__GB2,
-logic__5285: RocketTile__GCB0,
-logic__8584: tracking_wrapper,
-logic__4277: FPU__GB2,
-datapath__513: VCU118RocketSystem__GC0,
-logic__7283: VCU118RocketSystem__GC0,
-case__913: VCU118RocketSystem__GC0,
-logic__1175: VCU118RocketSystem__GC0,
-logic__988: VCU118RocketSystem__GC0,
-logic__4434: FPU__GB1,
-logic__1470: RocketTile__GCB0,
-case__654: RocketTile__GCB0,
-datapath__173: VCU118RocketSystem__GC0,
-case__240: VCU118RocketSystem__GC0,
-case__198: VCU118RocketSystem__GC0,
-logic__684: VCU118RocketSystem__GC0,
-reg__1116: APBGpsBlock__GCB1,
-logic__4736: RocketTile__GCB0,
-logic__5172: RocketTile__GCB0,
-reg__684: RocketTile__GCB0,
-reg__1004: APBGpsBlock__GCB1,
-muxpart__76: FPU__GB0,
-logic__6018: RocketTile__GCB0,
-logic__1163: VCU118RocketSystem__GC0,
-logic__3773: FPU__GB1,
-logic__7066: VCU118RocketSystem__GC0,
-logic__6699: VCU118RocketSystem__GC0,
-case__1330: APBGpsBlock__GCB1,
-keep__38: APBGpsBlock__GCB0,
-mult_33_65_98: APBGpsBlock__GCB0,
-reg__505: FPU__GB2,
-logic__1280: VCU118RocketSystem__GC0,
-logic__937: VCU118RocketSystem__GC0,
-logic__1860: RocketTile__GCB0, DCache,
-case__673: RocketTile__GCB0,
-muxpart__112: VCU118RocketSystem__GC0,
-logic__2440: RocketTile__GCB0,
-logic__6674: VCU118RocketSystem__GC0,
-datapath__653: tracking_wrapper,
-logic__4504: FPU__GB1,
-logic__3574: FPU__GB1,
-logic__5016: RocketTile__GCB0,
-logic__8819: tracking_wrapper,
-logic__1334: VCU118RocketSystem__GC0,
-logic__7145: VCU118RocketSystem__GC0,
-case__1175: APBGpsBlock__GCB1,
-logic__3469: FPU__GB2,
-logic__2433: RocketTile__GCB0,
-muxpart__84: FPU__GB0,
-MulAddRecFNPipe_l2_e11_s53: FPU__GB1,
-case__1219: APBGpsBlock__GCB1,
-logic__3429: FPU__GB2,
-cordic_atan_basic: tracking_wrapper,
-logic__2883: FPU__GB1,
-logic__2156: DCache,
-logic__8791: tracking_wrapper,
-reg__801: VCU118RocketSystem__GC0,
-logic__6509: VCU118RocketSystem__GC0,
-case__127: VCU118RocketSystem__GC0,
-datapath__188: VCU118RocketSystem__GC0,
-reg__1234: tracking_wrapper,
-rom__2: APBGpsBlock__GCB1,
-case__883: VCU118RocketSystem__GC0,
-case__1670: APBGpsBlock__GCB0,
-logic__3699: FPU__GB1,
-binary_to_gray: tracking_wrapper,
-logic__6039: RocketTile__GCB0,
-logic__2696: FPU__GB1,
-logic__4525: RocketTile__GCB0,
-reg__243: DCache,
-logic__5700: RocketTile__GCB0,
-case__668: RocketTile__GCB0,
-logic__5357: RocketTile__GCB0,
-reg__167: VCU118RocketSystem__GC0,
-logic__2890: FPU__GB1,
-dsp48e1__8: APBGpsBlock__GCB1,
-reg__402: FPU__GB1,
-reg__636: RocketTile__GCB0,
-logic__143: VCU118RocketSystem__GC0,
-logic__4025: FPU__GB2,
-muxpart__50: FPU__GB0,
-reg__554: FPU__GB1,
-logic__1319: VCU118RocketSystem__GC0,
-datapath__374: FPU__GB2,
-case__1331: APBGpsBlock__GCB1,
-reg__1341: tracking_wrapper,
-logic__2490: RocketTile__GCB0,
-case__866: VCU118RocketSystem__GC0,
-logic__6420: VCU118RocketSystem__GC0,
-dsp48e1__17: APBGpsBlock__GCB1,
-reg__285: DCache,
-case__47: VCU118RocketSystem__GC0,
-datapath__456: RocketTile__GCB0,
-reg__106: VCU118RocketSystem__GC0,
-datapath__607: APBGpsBlock__GCB1,
-reg__334: RocketTile__GCB0,
-case__271: VCU118RocketSystem__GC0,
-logic__4107: FPU__GB2,
-logic__8345: tracking_wrapper,
-logic__9294: APBGpsBlock__GCB0,
-logic__763: VCU118RocketSystem__GC0,
-dsp48e1__23: APBGpsBlock__GCB1,
-case__95: VCU118RocketSystem__GC0,
-reg__1178: tracking_wrapper,
-logic__1622: DCache,
-logic__3472: FPU__GB2,
-logic__960: VCU118RocketSystem__GC0,
-logic__3772: FPU__GB1,
-datapath__60: VCU118RocketSystem__GC0,
-logic__5964: RocketTile__GCB0,
-dsp48e1__40: tracking_wrapper,
-logic__4147: FPU__GB2,
-reg__1149: tracking_wrapper,
-logic__466: VCU118RocketSystem__GC0,
-MulDiv: RocketTile__GCB0,
-datapath__19: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__354: VCU118RocketSystem__GC0,
-logic__8745: tracking_wrapper,
-logic__4381: FPU__GB1,
-logic__3728: FPU__GB1,
-logic__6794: VCU118RocketSystem__GC0,
-logic__487: VCU118RocketSystem__GC0,
-reg__1156: tracking_wrapper,
-logic__670: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__151: VCU118RocketSystem__GC0,
-logic__7753: APBGpsBlock__GCB1,
-logic__436: VCU118RocketSystem__GC0,
-logic__6190: VCU118RocketSystem__GC0,
-logic__1189: VCU118RocketSystem__GC0,
-case__1110: APBGpsBlock__GCB1,
-logic__5204: RocketTile__GCB0,
-logic__8411: tracking_wrapper,
-case__924: VCU118RocketSystem__GC0,
-reg__1151: tracking_wrapper,
-logic__7603: VCU118RocketSystem__GC0,
-counter__31: APBGpsBlock__GCB0,
-logic__6696: VCU118RocketSystem__GC0,
-reg__1005: APBGpsBlock__GCB1,
-case__134: VCU118RocketSystem__GC0,
-reg__1433: APBGpsBlock__GCB0,
-logic__2544: RocketTile__GCB0,
-logic__3441: FPU__GB2,
-logic__3799: FPU__GB1,
-logic__8773: tracking_wrapper,
-dsp48e1__1: FPU__GB1,
-logic__7799: APBGpsBlock__GCB1,
-logic__8473: tracking_wrapper,
-logic__4732: RocketTile__GCB0,
-reg__1109: APBGpsBlock__GCB1,
-logic__8664: tracking_wrapper,
-logic__3859: FPU__GB1,
-reg__492: FPU__GB1,
-reg__254: DCache,
-case__638: RocketTile__GCB0,
-logic__1679: DCache,
-logic__6242: VCU118RocketSystem__GC0,
-logic__9184: APBGpsBlock__GCB0,
-reg__733: RocketTile__GCB0,
-logic__465: VCU118RocketSystem__GC0,
-logic__4719: RocketTile__GCB0,
-butterfly__parameterized1: APBGpsBlock__GCB1,
-logic__5988: RocketTile__GCB0,
-case__107: VCU118RocketSystem__GC0,
-logic__3283: FPU__GB2,
-logic__2382: RocketTile__GCB0,
-case__242: VCU118RocketSystem__GC0,
-counter__13: APBGpsBlock__GCB1,
-logic__6607: VCU118RocketSystem__GC0,
-datapath__226: VCU118RocketSystem__GC0,
-reg__1028: APBGpsBlock__GCB1,
-logic__6225: VCU118RocketSystem__GC0,
-reg__1054: APBGpsBlock__GCB1,
-logic__8439: tracking_wrapper,
-logic__6817: VCU118RocketSystem__GC0,
-logic__6582: VCU118RocketSystem__GC0,
-case__265: VCU118RocketSystem__GC0,
-datapath__102: VCU118RocketSystem__GC0,
-logic__296: VCU118RocketSystem__GC0,
-reg__314: RocketTile__GCB0,
-logic__7425: VCU118RocketSystem__GC0,
-reg__932: VCU118RocketSystem__GC0,
-reg__722: RocketTile__GCB0,
-logic__9335: APBGpsBlock__GCB1,
-logic__8694: tracking_wrapper,
-case__752: RocketTile__GCB0,
-reg__426: FPU__GB1,
-datapath: genesys2_rocket_top__GC0,
-case__70: VCU118RocketSystem__GC0,
-case__528: FPU__GB2, FPU__GB1,
-case__632: RocketTile__GCB0,
-case__1650: APBGpsBlock__GCB0,
-case__786: RocketTile__GCB0,
-reg__659: RocketTile__GCB0,
-keep__33: APBGpsBlock__GCB0,
-datapath__444: RocketTile__GCB0,
-logic__7585: VCU118RocketSystem__GC0,
-logic__330: VCU118RocketSystem__GC0,
-case__558: FPU__GB2,
-case__428: RocketTile__GCB0,
-case__838: VCU118RocketSystem__GC0,
-reg__152: VCU118RocketSystem__GC0,
-case__1275: APBGpsBlock__GCB1,
-logic__4452: FPU__GB1,
-logic__6624: VCU118RocketSystem__GC0,
-case__25: VCU118RocketSystem__GC0,
-datapath__537: APBGpsBlock__GCB1,
-logic__4377: FPU__GB1,
-logic__1839: DCache,
-logic__6810: VCU118RocketSystem__GC0,
-logic__1314: VCU118RocketSystem__GC0,
-logic__796: VCU118RocketSystem__GC0,
-logic__5554: RocketTile__GCB0,
-MulAddRecFNToRaw_preMul: FPU__GB1,
-reg__1265: tracking_wrapper,
-case__1407: tracking_wrapper,
-case__969: VCU118RocketSystem__GC0,
-logic__6421: VCU118RocketSystem__GC0,
-logic__2098: DCache,
-reg__19: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__1046: VCU118RocketSystem__GC0,
-case__1475: tracking_wrapper,
-reg__366: RocketTile__GCB0,
-datapath__351: FPU__GB1,
-logic__6623: VCU118RocketSystem__GC0,
-reg__234: RocketTile__GCB0,
-logic__7196: VCU118RocketSystem__GC0,
-reg__1325: tracking_wrapper,
-datapath__648: tracking_wrapper,
-logic__4376: FPU__GB1,
-logic__7717: APBGpsBlock__GCB1,
-reg__572: FPU__GB1,
-logic__9165: APBGpsBlock__GCB0,
-reg__619: RocketTile__GCB0,
-datapath__261: DCache,
-case__1520: tracking_wrapper,
-logic__8328: tracking_wrapper,
-case__281: VCU118RocketSystem__GC0,
-datapath__127: VCU118RocketSystem__GC0,
-logic__7112: VCU118RocketSystem__GC0,
-datapath__158: VCU118RocketSystem__GC0,
-logic__6185: VCU118RocketSystem__GC0,
-logic__7214: VCU118RocketSystem__GC0,
-logic__966: VCU118RocketSystem__GC0,
-case__1634: APBGpsBlock__GCB0,
-reg__1155: tracking_wrapper,
-logic__8295: tracking_wrapper,
-logic__9302: APBGpsBlock__GCB0,
-case__374: RocketTile__GCB0,
-logic__5450: RocketTile__GCB0,
-case__769: RocketTile__GCB0,
-case__102: VCU118RocketSystem__GC0,
-reg__301: RocketTile__GCB0,
-logic__4395: FPU__GB1,
-logic__74: genesys2_rocket_top__GC0,
-TLInterconnectCoupler_fbus_from_debug_sb: VCU118RocketSystem__GC0,
-case__1536: APBGpsBlock__GCB0,
-logic__3668: FPU__GB1,
-reg__481: FPU__GB1,
-logic__6255: VCU118RocketSystem__GC0,
-logic__1106: VCU118RocketSystem__GC0,
-logic__2509: RocketTile__GCB0,
-reg__1308: tracking_wrapper,
-logic__4284: FPU__GB2,
-datapath__236: VCU118RocketSystem__GC0,
-logic__5464: RocketTile__GCB0,
-datapath__90: VCU118RocketSystem__GC0,
-datapath__547: APBGpsBlock__GCB1,
-logic__4737: RocketTile__GCB0,
-logic__1142: VCU118RocketSystem__GC0,
-reg__1262: tracking_wrapper,
-case__1201: APBGpsBlock__GCB1,
-dsp48e1__3: APBGpsBlock__GCB1,
-muxpart__317: APBGpsBlock__GCB0,
-logic__3197: FPU__GB2,
-reg__898: VCU118RocketSystem__GC0,
-case__637: RocketTile__GCB0,
-logic__5226: RocketTile__GCB0,
-case__574: FPU__GB1,
-case__433: RocketTile__GCB0,
-logic__5981: RocketTile__GCB0,
-logic__6935: VCU118RocketSystem__GC0,
-dsp48e1__33: tracking_wrapper,
-counter__3: DCache,
-case__82: VCU118RocketSystem__GC0,
-muxpart__82: FPU__GB0,
-logic__1921: DCache,
-reg__1374: APBGpsBlock__GCB0,
-extram: DCache,
-logic__6777: VCU118RocketSystem__GC0,
-logic__287: VCU118RocketSystem__GC0,
-reg__1436: APBGpsBlock__GCB0,
-datapath__112: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__879: VCU118RocketSystem__GC0,
-reg__1322: tracking_wrapper,
-logic__5370: RocketTile__GCB0,
-logic__2363: RocketTile__GCB0,
-case__1688: TLToAPB,
-logic__3627: FPU__GB1,
-reg__755: RocketTile__GCB0,
-logic__6640: VCU118RocketSystem__GC0,
-reg__788: VCU118RocketSystem__GC0,
-logic__3886: FPU__GB1,
-DivSqrtRawFN_small_1: FPU__GB2,
-logic__2676: RocketTile__GCB0,
-logic__5079: RocketTile__GCB0,
-reg__27: VCU118RocketSystem__GC0,
-logic__7654: VCU118RocketSystem__GC0,
-logic__1239: VCU118RocketSystem__GC0,
-reg__1332: tracking_wrapper,
-logic__4360: FPU__GB1,
-logic__6155: VCU118RocketSystem__GC0,
-logic__455: VCU118RocketSystem__GC0,
-logic__2900: FPU__GB1,
-logic__2108: DCache,
-muxpart: genesys2_rocket_top__GC0,
-spill_register: tracking_wrapper,
-logic__4113: FPU__GB2,
-logic__6745: VCU118RocketSystem__GC0,
-case__808: VCU118RocketSystem__GC0,
-case__153: VCU118RocketSystem__GC0,
-dsp48e1__36: tracking_wrapper,
-logic__5512: RocketTile__GCB0,
-logic__4402: FPU__GB1,
-reg__1454: TLToAPB,
-case__1288: APBGpsBlock__GCB1,
-logic__8549: tracking_wrapper,
-case__594: FPU__GB1,
-datapath__518: VCU118RocketSystem__GC0,
-logic__6094: RocketTile__GCB0,
-logic__9385: genesys2_rocket_top__GC0,
-reg__928: VCU118RocketSystem__GC0,
-case__625: RocketTile__GCB0,
-datapath__582: APBGpsBlock__GCB1,
-reg__776: RocketTile__GCB0,
-case__582: FPU__GB1,
-case__1615: APBGpsBlock__GCB0,
-muxpart__41: FPU__GB0,
-TLError: VCU118RocketSystem__GC0,
-reg__902: VCU118RocketSystem__GC0,
-logic__4663: RocketTile__GCB0,
-logic__4455: FPU__GB1,
-case__286: VCU118RocketSystem__GC0,
-reg__1131: APBGpsBlock__GCB0,
-case__647: RocketTile__GCB0,
-logic__5997: RocketTile__GCB0,
-logic__7378: VCU118RocketSystem__GC0,
-case__1388: tracking_wrapper,
-logic__6568: VCU118RocketSystem__GC0,
-reg__1275: tracking_wrapper,
-logic__612: VCU118RocketSystem__GC0,
-logic__3016: FPU__GB2, FPU__GB1,
-reg__317: RocketTile__GCB0,
-logic__3249: FPU__GB2,
-logic__5369: RocketTile__GCB0,
-datapath__322: FPU__GB2,
-logic__2364: RocketTile__GCB0,
-logic__879: VCU118RocketSystem__GC0,
-reg__84: VCU118RocketSystem__GC0,
-datapath__82: VCU118RocketSystem__GC0,
-keep__14: APBGpsBlock__GCB0,
-case__1283: APBGpsBlock__GCB1,
-datapath__587: APBGpsBlock__GCB1,
-logic__2594: RocketTile__GCB0,
-datapath__531: APBGpsBlock__GCB1,
-reg__583: RocketTile__GCB0,
-datapath__676: tracking_wrapper,
-datapath__44: VCU118RocketSystem__GC0,
-logic__4723: RocketTile__GCB0,
-case__605: FPU__GB0,
-case__726: RocketTile__GCB0,
-reg__802: VCU118RocketSystem__GC0,
-logic__3846: FPU__GB1,
-logic__2198: DCache,
-logic__9204: APBGpsBlock__GCB0,
-muxpart__110: RocketTile__GCB0,
-FPU__GB1: FPU__GB1,
-case__1095: APBGpsBlock__GCB1,
-logic__1437: RocketTile__GCB0,
-reg__627: RocketTile__GCB0,
-logic__3648: FPU__GB1,
-logic__1473: RocketTile__GCB0,
-reg__175: VCU118RocketSystem__GC0,
-datapath__423: RocketTile__GCB0,
-logic__256: VCU118RocketSystem__GC0,
-logic__2152: DCache,
-reg__155: VCU118RocketSystem__GC0,
-counter__1: VCU118RocketSystem__GC0,
-case__412: RocketTile__GCB0,
-logic__8705: tracking_wrapper,
-logic__2914: FPU__GB1,
-muxpart__19: FPU__GB0,
-reg__292: RocketTile__GCB0,
-logic__511: VCU118RocketSystem__GC0,
-reg__1154: tracking_wrapper,
-logic__3468: FPU__GB2,
-logic__291: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_sbus_from_bus_named_fbus: VCU118RocketSystem__GC0,
-case__1336: APBGpsBlock__GCB1,
-reg__531: FPU__GB1,
-logic__7354: VCU118RocketSystem__GC0,
-logic__4914: RocketTile__GCB0,
-datapath__223: VCU118RocketSystem__GC0,
-reg__1108: APBGpsBlock__GCB1,
-logic__6510: VCU118RocketSystem__GC0,
-case__241: VCU118RocketSystem__GC0,
-case__1478: tracking_wrapper,
-case__237: VCU118RocketSystem__GC0,
-logic__178: VCU118RocketSystem__GC0,
-logic__1156: VCU118RocketSystem__GC0,
-logic__3130: FPU__GB2,
-case__1466: tracking_wrapper,
-datapath__461: RocketTile__GCB0,
-reg__604: RocketTile__GCB0,
-logic__9389: genesys2_rocket_top__GC0,
-logic__6208: VCU118RocketSystem__GC0,
-dsp48e1__21: APBGpsBlock__GCB1,
-logic__8930: APBGpsBlock__GCB0,
-IntToFP: FPU__GB2,
-reg__472: FPU__GB1,
-logic__6429: VCU118RocketSystem__GC0,
-logic__3794: FPU__GB1,
-case__1279: APBGpsBlock__GCB1,
-case__893: VCU118RocketSystem__GC0,
-case__167: VCU118RocketSystem__GC0,
-datapath__72: VCU118RocketSystem__GC0,
-logic__7479: VCU118RocketSystem__GC0,
-logic__943: VCU118RocketSystem__GC0,
-case__69: VCU118RocketSystem__GC0,
-logic__4999: RocketTile__GCB0,
-case__505: FPU__GB1,
-logic__7988: APBGpsBlock__GCB1,
-datapath__594: APBGpsBlock__GCB1,
-reg__748: RocketTile__GCB0,
-logic__7049: VCU118RocketSystem__GC0,
-logic__1932: DCache,
-case__15: genesys2_rocket_top__GC0,
-logic__6147: VCU118RocketSystem__GC0,
-logic__897: VCU118RocketSystem__GC0,
-lock_detector: tracking_wrapper,
-case__760: RocketTile__GCB0,
-logic__6177: VCU118RocketSystem__GC0,
-reg__1342: APBGpsBlock__GCB0,
-logic__7459: VCU118RocketSystem__GC0,
-AMOALU: DCache,
-reg__1210: tracking_wrapper,
-reg__236: DCache,
-logic__208: VCU118RocketSystem__GC0,
-keep__18: APBGpsBlock__GCB0,
-logic__1895: RocketTile__GCB0, DCache,
-logic__3848: FPU__GB1,
-logic__5657: RocketTile__GCB0,
-logic__563: VCU118RocketSystem__GC0,
-counter__24: tracking_wrapper,
-logic__6799: VCU118RocketSystem__GC0,
-cordic_atan_one_stage__parameterized0: tracking_wrapper,
-logic__8340: tracking_wrapper,
-FixedClockBroadcast_3: VCU118RocketSystem__GC0,
-logic__2497: RocketTile__GCB0,
-logic__6971: VCU118RocketSystem__GC0,
-datapath__379: FPU__GB2,
-dsp48e1__24: APBGpsBlock__GCB1,
-case__1070: APBGpsBlock__GCB1,
-logic__1931: DCache,
-logic__3768: FPU__GB1,
-logic__880: VCU118RocketSystem__GC0,
-logic__435: VCU118RocketSystem__GC0,
-addsub__6: tracking_wrapper,
-datapath__164: VCU118RocketSystem__GC0,
-case__1140: APBGpsBlock__GCB1,
-reg__178: VCU118RocketSystem__GC0,
-logic__4444: FPU__GB1,
-logic__6615: VCU118RocketSystem__GC0,
-reg__371: FPU__GB0,
-datapath__194: VCU118RocketSystem__GC0,
-case__1131: APBGpsBlock__GCB1,
-logic__9141: APBGpsBlock__GCB0,
-case__687: RocketTile__GCB0,
-reg__734: RocketTile__GCB0,
-logic__4706: RocketTile__GCB0,
-logic__325: VCU118RocketSystem__GC0,
-logic__816: VCU118RocketSystem__GC0,
-logic__2907: FPU__GB1,
-reg__331: RocketTile__GCB0,
-logic__8336: tracking_wrapper,
-logic__5892: RocketTile__GCB0,
-logic__217: VCU118RocketSystem__GC0,
-logic__2140: DCache,
-datapath__134: VCU118RocketSystem__GC0,
-case__60: VCU118RocketSystem__GC0,
-case__1039: VCU118RocketSystem__GC0,
-logic__21: genesys2_rocket_top__GC0,
-case__712: RocketTile__GCB0,
-reg__865: VCU118RocketSystem__GC0,
-logic__9190: APBGpsBlock__GCB0,
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/e/elab.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/e/elab.rtd
deleted file mode 100644
index d9be555..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/e/elab.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1220760385.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1220760385.rtd
deleted file mode 100644
index fb0e6bd..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index 46cffc6..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1294509424.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1294509424.rtd
deleted file mode 100644
index 5dcf470..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index 3a8e996..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/136113302.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/136113302.rtd
deleted file mode 100644
index 76041f1..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd
deleted file mode 100644
index 744d552..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1672436263.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1672436263.rtd
deleted file mode 100644
index 089268e..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index f46a8bb..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2610937407.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2610937407.rtd
deleted file mode 100644
index 010c7c1..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index 8a56c00..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2737226844.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2737226844.rtd
deleted file mode 100644
index 04b4d75..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index b2cb04c..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2962621930.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2962621930.rtd
deleted file mode 100644
index 52d4f9e..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index ad3f0db..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2996647647.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2996647647.rtd
deleted file mode 100644
index c4822a4..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2996647647.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2996647647.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2996647647.rtd.straps.rtd
deleted file mode 100644
index 7b70544..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2996647647.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2996647647.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2996647647.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2996647647.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2996647647.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/2996647647.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3315205705.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3315205705.rtd
deleted file mode 100644
index cd16072..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3315205705.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3315205705.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3315205705.rtd.straps.rtd
deleted file mode 100644
index 6a28836..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3315205705.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3315205705.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3315205705.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3315205705.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3315205705.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3315205705.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3482045580.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3482045580.rtd
deleted file mode 100644
index abb87d8..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index e69e2d5..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3990655999.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3990655999.rtd
deleted file mode 100644
index 416c97e..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3990655999.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd
deleted file mode 100644
index 21eb65d..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/976197094.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/976197094.rtd
deleted file mode 100644
index adfb6dd..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd
deleted file mode 100644
index 355b4f9..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/global_name.straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/global_name.straps.rtd
deleted file mode 100644
index 6eb5290..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/instToEncGenName.map b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/instToEncGenName.map
deleted file mode 100644
index 2cd4d4d..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/g/instToEncGenName.map
+++ /dev/null
@@ -1,20 +0,0 @@
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GCB1:3315205705
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GCB0:2996647647
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/genesys2_rocket_top__GC0:3990655999
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/genomeDependencyGraph.out b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/genomeDependencyGraph.out
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/genomes.map b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/genomes.map
deleted file mode 100644
index b6ec85d..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/genomes.map
+++ /dev/null
@@ -1,12 +0,0 @@
-FPU__GB0 82AC8E00
-FPU__GB1 85310880
-FPU__GB2 83F79C80
-RocketTile__GCB0 58CD6940
-DCache 58C70140
-TilePRCIDomain__GC0 58B23700
-tracking_wrapper 58C35EE0
-APBGpsBlock__GCB0 86F57440
-APBGpsBlock__GCB1 85272BE0
-TLToAPB 97F14C40
-VCU118RocketSystem__GC0 581830E0
-genesys2_rocket_top__GC0 5720EAA0
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/genomes.txt b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/genomes.txt
deleted file mode 100644
index 37eb853..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/genomes.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-FPU__GB0
-FPU__GB1
-FPU__GB2
-RocketTile__GCB0
-DCache
-TilePRCIDomain__GC0
-tracking_wrapper
-APBGpsBlock__GCB0
-APBGpsBlock__GCB1
-TLToAPB
-VCU118RocketSystem__GC0
-genesys2_rocket_top__GC0
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/parentModToGenomes.map b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/parentModToGenomes.map
deleted file mode 100644
index b445d07..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/parentModToGenomes.map
+++ /dev/null
@@ -1,8 +0,0 @@
-genesys2_rocket_top: TilePRCIDomain__GC0, VCU118RocketSystem__GC0, APBGpsBlock__GCB0, APBGpsBlock__GCB1, TLToAPB, genesys2_rocket_top__GC0, DCache, RocketTile__GCB0, FPU__GB0, FPU__GB2, FPU__GB1, tracking_wrapper,
-VCU118RocketSystem: TilePRCIDomain__GC0, VCU118RocketSystem__GC0, APBGpsBlock__GCB0, APBGpsBlock__GCB1, TLToAPB, DCache, RocketTile__GCB0, FPU__GB0, FPU__GB2, FPU__GB1, tracking_wrapper,
-FPGAGPSClockSinkDomain: TLToAPB, APBGpsBlock__GCB1, APBGpsBlock__GCB0, tracking_wrapper,
-APBGpsBlock: APBGpsBlock__GCB1, APBGpsBlock__GCB0, tracking_wrapper,
-TilePRCIDomain: TilePRCIDomain__GC0, RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-HierarchicalElementResetDomain: RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-RocketTile: RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-FPU: FPU__GB2, FPU__GB1, FPU__GB0,
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/synthNameToElabName.map b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/synthNameToElabName.map
deleted file mode 100644
index 5c90635..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/synthNameToElabName.map
+++ /dev/null
@@ -1,9276 +0,0 @@
-logic__4194: logic__4194
-logic__1893: logic__1893
-reg__1559: reg__837
-case__94: case__94
-logic__289: logic__289
-logic__2492: logic__2492
-case__1134: case__1134
-logic__5519: logic__5519
-logic__793: logic__793
-case__482: case__482
-reg__1136: reg__1136
-logic__4428: logic__4428
-RoundAnyRawFNToRecFN_3: RoundAnyRawFNToRecFN_3
-logic__9632: logic__1560
-logic__948: logic__948
-case__1543: case__1543
-reg__651: reg__651
-datapath__655: datapath__655
-logic__9738: logic__6152
-logic__7861: logic__7861
-reg__1170: reg__1170
-logic__6824: logic__6824
-case__1728: case__1424
-logic__7186: logic__7186
-logic__6791: logic__6791
-logic__7270: logic__7270
-reg__439: reg__439
-logic__5028: logic__5028
-case__1358: case__1358
-case__219: case__219
-logic__6473: logic__6473
-logic__1263: logic__1263
-reg__462: reg__462
-logic__5359: logic__5359
-reg__1194: reg__1194
-reg__1243: reg__1243
-case__1366: case__1366
-ram__2: ram__2
-datapath__358: datapath__358
-reg__378: reg__378
-case__206: case__206
-logic__8793: logic__8793
-reg__1557: reg__836
-reg__903: reg__903
-case__824: case__824
-case__454: case__454
-dual_port_bram__parameterized0: dual_port_bram__parameterized0
-logic__4615: logic__4615
-reg__731: reg__731
-logic__6946: logic__6946
-case__1195: case__1195
-logic__8082: logic__8082
-muxpart__228: muxpart__228
-case__479: case__479
-logic__6483: logic__6483
-logic__6025: logic__6025
-CLINT: CLINT
-case__488: case__488
-logic__5360: logic__5360
-logic__9693: logic__8276
-logic__2439: logic__2439
-logic__8434: logic__8434
-reg__83: reg__83
-reg__789: reg__789
-datapath__760: datapath__240
-datapath__286: datapath__286
-reg__896: reg__896
-logic__6952: logic__6952
-reg__803: reg__803
-logic__3532: logic__3532
-datapath__265: datapath__265
-logic__9578: logic__1696
-logic__6818: logic__6818
-logic__6567: logic__6567
-reg__206: reg__206
-reg__622: reg__622
-datapath__446: datapath__446
-case__170: case__170
-case__161: case__161
-logic__3495: logic__3495
-AsyncQueueSource_DebugInternalBundle: AsyncQueueSource_DebugInternalBundle
-reg__883: reg__883
-logic__1178: logic__1178
-datapath__595: datapath__595
-reg__1244: reg__1244
-datapath__84: datapath__84
-reg__49: reg__49
-comp_mult: comp_mult
-logic__9300: logic__9300
-logic__6512: logic__6512
-datapath__121: datapath__121
-datapath__551: datapath__551
-reg__419: reg__419
-logic__9588: logic__1662
-logic__8283: logic__8283
-datapath__399: datapath__399
-logic__6386: logic__6386
-case__611: case__611
-logic__3584: logic__3584
-muxpart__10: muxpart__10
-reg__863: reg__863
-logic__3945: logic__3945
-reg__556: reg__556
-logic__2155: logic__2155
-case__980: case__980
-reg__573: reg__573
-logic__9430: logic__3963
-logic__508: logic__508
-logic__124: logic__124
-logic__2567: logic__2567
-logic__2123: logic__2123
-muxpart__96: muxpart__96
-logic__4362: logic__4362
-datapath__280: datapath__280
-logic__3445: logic__3445
-logic__7998: logic__7998
-logic__4274: logic__4274
-reg__1592: reg__837
-logic__9172: logic__9172
-muxpart__301: muxpart__301
-logic__6472: logic__6472
-logic__7967: logic__7967
-logic__4850: logic__4850
-logic__3934: logic__3934
-logic__9681: logic__8273
-logic__1186: logic__1186
-case__781: case__781
-reg__1663: reg__38
-logic__4731: logic__4731
-case__1278: case__1278
-logic__8717: logic__8717
-case__920: case__920
-datapath__744: datapath__298
-logic__3457: logic__3457
-reg__1219: reg__1219
-logic__4534: logic__4534
-reg__157: reg__157
-case__1067: case__1067
-reg__834: reg__834
-case__1386: case__1386
-reg__284: reg__284
-signinv: signinv
-logic__3235: logic__3235
-case__806: case__806
-logic__9649: logic__1525
-reg__900: reg__900
-reg__870: reg__870
-logic__4168: logic__4168
-case__1660: case__1660
-case__841: case__841
-logic__1791: logic__1791
-logic__4427: logic__4427
-datapath__193: datapath__193
-TLInterconnectCoupler_pbus_to_fpga_uart: TLInterconnectCoupler_pbus_to_fpga_uart
-case__1052: case__1052
-logic__5048: logic__5048
-reg__557: reg__557
-logic__3351: logic__3351
-logic__3804: logic__3804
-logic__6020: logic__6020
-reg__881: reg__881
-logic__5324: logic__5324
-datapath__247: datapath__247
-case__363: case__363
-logic__1875: logic__1875
-datapath__677: datapath__677
-reg__80: reg__80
-logic__9686: logic__8272
-logic__4699: logic__4699
-datapath__454: datapath__454
-logic__6572: logic__6572
-case__825: case__825
-reg__99: reg__99
-ram__7: ram__7
-case__162: case__162
-logic__9155: logic__9155
-datapath__747: datapath__359
-logic__240: logic__240
-reg__513: reg__513
-logic__5542: logic__5542
-logic__2121: logic__2121
-case__1018: case__1018
-logic__6251: logic__6251
-logic__1649: logic__1649
-reg__617: reg__617
-logic__9344: logic__9344
-TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u: TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u
-muxpart__73: muxpart__73
-muxpart__26: muxpart__26
-case__905: case__905
-reg__809: reg__809
-case__855: case__855
-logic__4770: logic__4770
-logic__9609: logic__1613
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__35: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__4361: logic__4361
-TLFragmenter_CLINT: TLFragmenter_CLINT
-reg__322: reg__322
-logic__1076: logic__1076
-logic__516: logic__516
-logic__5654: logic__5654
-logic__4397: logic__4397
-logic__6468: logic__6468
-logic__5361: logic__5361
-logic__7073: logic__7073
-logic__918: logic__918
-logic__6539: logic__6539
-case__1730: case__1422
-reg__989: reg__989
-keep__25: keep__25
-logic__4639: logic__4639
-reg__544: reg__544
-datapath__718: datapath__718
-logic__7891: logic__7891
-case__385: case__385
-case__1179: case__1179
-AsyncValidSync__10: AsyncValidSync
-logic__4790: logic__4790
-counter__16: counter__16
-datapath__441: datapath__441
-datapath__698: datapath__698
-logic__3805: logic__3805
-reg__1359: reg__1359
-reg__1450: reg__1450
-reg__751: reg__751
-case__1305: case__1305
-logic__4069: logic__4069
-logic__2084: logic__2084
-datapath__210: datapath__210
-logic__8654: logic__8654
-logic__8850: logic__8850
-reg__354: reg__354
-logic__8786: logic__8786
-reg__588: reg__588
-case__765: case__765
-logic__4682: logic__4682
-logic__2371: logic__2371
-double_ff_syn__5: double_ff_syn
-case__1677: case__1677
-logic__2854: logic__2854
-datapath__616: datapath__616
-case__843: case__843
-case__446: case__446
-cdc_fifo_gray_src: cdc_fifo_gray_src
-logic__8538: logic__8538
-logic__3172: logic__3172
-logic__3935: logic__3935
-TLBuffer_a32d64s1k1z4u_1: TLBuffer_a32d64s1k1z4u_1
-logic__9630: logic__1568
-logic__935: logic__935
-case__46: case__46
-logic__3899: logic__3899
-reg__658: reg__658
-reg__1583: reg__837
-case__876: case__876
-reg__1397: reg__1397
-datapath__389: datapath__389
-logic__6941: logic__6941
-logic__6591: logic__6591
-logic__9675: logic__8476
-case__953: case__953
-case__19: case__19
-reg__44: reg__44
-reg__1451: reg__1451
-reg__1441: reg__1441
-logic__6252: logic__6252
-reg__247: reg__247
-datapath__542: datapath__542
-logic__6090: logic__6090
-logic__4156: logic__4156
-logic__9636: logic__1554
-logic__6418: logic__6418
-logic__1172: logic__1172
-logic__6622: logic__6622
-reg__831: reg__831
-muxpart__111: muxpart__111
-reg__356: reg__356
-logic__1619: logic__1619
-logic__7607: logic__7607
-reg__389: reg__389
-TLFpgaUART: TLFpgaUART
-datapath__123: datapath__123
-reg__1023: reg__1023
-RoundRawFNToRecFN_1__1: RoundRawFNToRecFN_1
-logic__9400: logic__3015
-logic__9338: logic__9338
-logic__9616: logic__1596
-logic__6026: logic__6026
-logic__304: logic__304
-case__138: case__138
-reg__1192: reg__1192
-reg__413: reg__413
-logic__4396: logic__4396
-datapath__363: datapath__363
-logic__9783: logic__498
-case__351: case__351
-reg__1029: reg__1029
-dsp48e1__2: dsp48e1__2
-logic__6162: logic__6162
-case__1167: case__1167
-logic__3840: logic__3840
-logic__4745: logic__4745
-case__346: case__346
-logic__2518: logic__2518
-reg__1227: reg__1227
-logic__9170: logic__9170
-case__691: case__691
-logic__3095: logic__3095
-logic__7315: logic__7315
-logic__7106: logic__7106
-case__1142: case__1142
-reg__364: reg__364
-case__629: case__629
-logic__2814: logic__2814
-datapath__300: datapath__300
-case__1277: case__1277
-logic__9736: logic__6152
-logic__762: logic__762
-logic__5483: logic__5483
-datapath__31: datapath__31
-reg__786: reg__786
-logic__5430: logic__5430
-logic__9574: logic__1704
-logic__6833: logic__6833
-logic__456: logic__456
-logic__6313: logic__6313
-logic__8734: logic__8734
-logic__1113: logic__1113
-datapath__23: datapath__23
-datapath__382: datapath__382
-logic__3762: logic__3762
-case__1300: case__1300
-logic__8806: logic__8806
-logic__4126: logic__4126
-logic__8406: logic__8406
-reg__1620: reg__836
-logic__7655: logic__7655
-logic__6625: logic__6625
-datapath__780: datapath__648
-logic__2961: logic__2961
-reg__182: reg__182
-logic__6093: logic__6093
-logic__5452: logic__5452
-logic__5419: logic__5419
-reg__605: reg__605
-muxpart__48: muxpart__48
-logic__1386: logic__1386
-logic__4757: logic__4757
-reg__1352: reg__1352
-muxpart__313: muxpart__313
-reg__746: reg__746
-logic__8959: logic__8959
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__6: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__4888: logic__4888
-reg__718: reg__718
-logic__6611: logic__6611
-reg__1422: reg__1422
-logic__8392: logic__8392
-datapath__786: datapath__522
-datapath__292: datapath__292
-logic__2862: logic__2862
-logic__3214: logic__3214
-case__1406: case__1406
-logic__6347: logic__6347
-logic__4418: logic__4418
-case__713: case__713
-logic__9187: logic__9187
-reg__1239: reg__1239
-reg__677: reg__677
-logic__2993: logic__2993
-logic__4040: logic__4040
-logic__6785: logic__6785
-logic__9618: logic__1594
-logic__4288: logic__4288
-logic__7310: logic__7310
-logic__2063: logic__2063
-logic__85: logic__85
-logic__2026: logic__2026
-case__1727: case__310
-logic__3930: logic__3930
-logic__2322: logic__2322
-logic__9657: logic__282
-case__226: case__226
-logic__755: logic__755
-logic__1824: logic__1824
-logic__9577: logic__1699
-case__1703: case__533
-logic__9703: logic__7691
-logic__7037: logic__7037
-logic__3113: logic__3113
-case__521: case__521
-logic__344: logic__344
-logic__9656: logic__283
-logic__2122: logic__2122
-logic__5283: logic__5283
-logic__4303: logic__4303
-reg__520: reg__520
-logic__1219: logic__1219
-logic__3767: logic__3767
-logic__4771: logic__4771
-reg__5: reg__5
-TLWidthWidget8_3: TLWidthWidget8_3
-reg__1130: reg__1130
-logic__2655: logic__2655
-logic__2881: logic__2881
-datapath__620: datapath__620
-case__369: case__369
-logic__4631: logic__4631
-logic__6600: logic__6600
-reg__1356: reg__1356
-logic__7339: logic__7339
-logic__632: logic__632
-logic__717: logic__717
-reg__804: reg__804
-logic__9286: logic__9286
-logic__9679: logic__8466
-case__949: case__949
-case__279: case__279
-logic__3712: logic__3712
-reg__1340: reg__1340
-reg__741: reg__741
-case__1311: case__1311
-muxpart__312: muxpart__312
-logic__9192: logic__9192
-logic__947: logic__947
-reg__95: reg__95
-case__41: case__41
-datapath__727: datapath__727
-reg__1466: reg__37
-logic__6754: logic__6754
-datapath__458: datapath__458
-muxpart__8: muxpart__8
-logic__265: logic__265
-logic__2599: logic__2599
-logic__4864: logic__4864
-logic__7590: logic__7590
-datapath__100: datapath__100
-datapath__131: datapath__131
-logic__3354: logic__3354
-case__1014: case__1014
-datapath__524: datapath__524
-TLAtomicAutomata_pbus: TLAtomicAutomata_pbus
-extram__7: extram__7
-case__587: case__587
-logic__8403: logic__8403
-genesys2_rocket_top__GC0: genesys2_rocket_top__GC0
-case__829: case__829
-keep__73: keep
-case__297: case__297
-case__1653: case__1653
-logic__8547: logic__8547
-reg__1200: reg__1200
-reg__656: reg__656
-case__13: case__13
-logic__9784: logic__497
-case__508: case__508
-logic__4447: logic__4447
-logic__9415: logic__2991
-reg__468: reg__468
-reg__545: reg__545
-reg__341: reg__341
-case__1409: case__1409
-case__962: case__962
-logic__8211: logic__8211
-datapath__621: datapath__621
-logic__5363: logic__5363
-reg__1006: reg__1006
-datapath__656: datapath__656
-logic__9110: logic__9110
-logic__4446: logic__4446
-case__783: case__783
-logic__6141: logic__6141
-datapath__184: datapath__184
-reg__488: reg__488
-logic__2144: logic__2144
-logic__3271: logic__3271
-logic__9416: logic__2990
-case__1525: case__1525
-case__1621: case__1621
-datapath__433: datapath__433
-logic__9421: logic__2970
-logic__9154: logic__9154
-logic__5095: logic__5095
-case__867: case__867
-logic__6023: logic__6023
-logic__1287: logic__1287
-logic__8404: logic__8404
-logic__5362: logic__5362
-LevelGateway__6: LevelGateway
-case__1452: case__1452
-logic__6769: logic__6769
-case__270: case__270
-logic__6280: logic__6280
-LevelGateway__9: LevelGateway
-logic__460: logic__460
-logic__6617: logic__6617
-logic__8548: logic__8548
-case__1387: case__1387
-logic__9580: logic__1684
-reg__1610: reg__837
-case__125: case__125
-case__84: case__84
-logic__2502: logic__2502
-logic__7741: logic__7741
-datapath__422: datapath__422
-logic__6057: logic__6057
-datapath__344: datapath__344
-logic__9750: logic__518
-datapath__75: datapath__75
-datapath__651: datapath__651
-datapath__627: datapath__627
-case__960: case__960
-logic__3884: logic__3884
-reg__1009: reg__1009
-logic__6217: logic__6217
-reg__394: reg__394
-reg__983: reg__983
-logic__7563: logic__7563
-logic__4111: logic__4111
-reg__388: reg__388
-Queue2_TLBundleA_a32d64s1k1z4u: Queue2_TLBundleA_a32d64s1k1z4u
-logic__5298: logic__5298
-logic__3233: logic__3233
-ClockCrossingReg_w55: ClockCrossingReg_w55
-reg__1647: reg__67
-datapath__13: datapath__13
-datapath__541: datapath__541
-logic__885: logic__885
-case__1223: case__1223
-dsp48e1__15: dsp48e1__15
-datapath__729: datapath__729
-case__337: case__337
-logic__3937: logic__3937
-reg__1624: reg__838
-reg__1082: reg__1082
-reg__1319: reg__1319
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__19: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__7589: logic__7589
-case__1006: case__1006
-logic__9785: logic__496
-logic__9464: logic__1900
-logic__5036: logic__5036
-datapath__255: datapath__255
-logic__7156: logic__7156
-case__1177: case__1177
-logic__4167: logic__4167
-datapath__476: datapath__476
-SynchronizerShiftReg_w1_d3: SynchronizerShiftReg_w1_d3
-dsp48e1__30: dsp48e1__30
-case__494: case__494
-logic__9591: logic__1657
-reg__343: reg__343
-logic__6541: logic__6541
-logic__654: logic__654
-reg__1111: reg__1111
-datapath__643: datapath__643
-AsyncResetRegVec_w1_i0__3: AsyncResetRegVec_w1_i0
-logic__3032: logic__3032
-logic__6763: logic__6763
-case__1326: case__1326
-logic__9429: logic__3966
-reg__655: reg__655
-reg__1628: reg__784
-logic__144: logic__144
-logic__8252: logic__8252
-logic__7189: logic__7189
-logic__9147: logic__9147
-datapath__598: datapath__598
-logic__7415: logic__7415
-case__137: case__137
-datapath__308: datapath__308
-logic__9555: logic__1771
-muxpart__232: muxpart__232
-logic__9458: logic__3890
-logic__2694: logic__2694
-logic__6488: logic__6488
-logic__6248: logic__6248
-logic__1657: logic__1657
-reg__1453: reg__1453
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__10: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__9239: logic__9239
-logic__886: logic__886
-reg__1495: reg__1001
-case__910: case__910
-logic__1034: logic__1034
-reg__1366: reg__1366
-addsub__7: addsub__6
-datapath__367: datapath__367
-logic__2054: logic__2054
-reg__417: reg__417
-logic__6958: logic__6958
-reg__423: reg__423
-counter: counter
-logic__6205: logic__6205
-logic__7821: logic__7821
-datapath__237: datapath__237
-case__635: case__635
-logic__6926: logic__6926
-logic__9452: logic__3911
-case__357: case__357
-reg__250: reg__250
-logic__3386: logic__3386
-logic__9447: logic__3933
-case__1714: case__323
-case__1708: case__527
-logic__2726: logic__2726
-logic__6819: logic__6819
-reg__845: reg__845
-acq_ca_gen: acq_ca_gen
-logic__3770: logic__3770
-logic__8801: logic__8801
-reg__1007: reg__1007
-case__58: case__58
-reg__358: reg__358
-logic__2885: logic__2885
-case__1424: case__1424
-case__601: case__601
-reg__1358: reg__1358
-case__758: case__758
-logic__2640: logic__2640
-reg__785: reg__785
-FixedClockBroadcast_5: FixedClockBroadcast_5
-reg__1228: reg__1228
-logic__2133: logic__2133
-case__919: case__919
-reg__562: reg__562
-case__789: case__789
-logic__8360: logic__8360
-logic__7265: logic__7265
-logic__6537: logic__6537
-case__988: case__988
-logic__7580: logic__7580
-reg__1645: reg__69
-case__210: case__210
-datapath__136: datapath__136
-logic__4911: logic__4911
-counter__5: counter__5
-double_ff_syn__parameterized1: double_ff_syn__parameterized1
-logic__4579: logic__4579
-muxpart__20: muxpart__20
-logic__5415: logic__5415
-logic__4867: logic__4867
-logic__706: logic__706
-logic__384: logic__384
-logic__4865: logic__4865
-reg__60: reg__60
-case__586: case__586
-logic__2562: logic__2562
-case__135: case__135
-logic__7303: logic__7303
-case__847: case__847
-datapath__647: datapath__647
-reg__1081: reg__1081
-logic__7292: logic__7292
-reg__884: reg__884
-logic__9645: logic__1535
-reg__300: reg__300
-TilePRCIDomain__GC0: TilePRCIDomain__GC0
-logic__5969: logic__5969
-logic__6638: logic__6638
-logic__6188: logic__6188
-logic__675: logic__675
-case__143: case__143
-IntSyncSyncCrossingSink_n1x1: IntSyncSyncCrossingSink_n1x1
-logic__355: logic__355
-logic__2137: logic__2137
-logic__6219: logic__6219
-reg__1505: reg__837
-logic__3137: logic__3137
-logic__4968: logic__4968
-logic__367: logic__367
-logic__2351: logic__2351
-logic__2737: logic__2737
-logic__4195: logic__4195
-logic__1626: logic__1626
-logic__3777: logic__3777
-reg__962: reg__962
-logic__6647: logic__6647
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__30: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__5970: logic__5970
-reg__241: reg__241
-logic__3939: logic__3939
-case__979: case__979
-logic__8484: logic__8484
-case__23: case__23
-logic__9198: logic__9198
-logic__4869: logic__4869
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__1: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__743: case__743
-logic__7252: logic__7252
-logic__6803: logic__6803
-logic__696: logic__696
-logic__5307: logic__5307
-logic__9405: logic__3004
-logic__4300: logic__4300
-case__780: case__780
-logic__1419: logic__1419
-reg__1279: reg__1279
-case__1237: case__1237
-muxpart__60: muxpart__60
-reg__1211: reg__1211
-logic__6659: logic__6659
-logic__244: logic__244
-logic__2538: logic__2538
-reg__57: reg__57
-logic__103: logic__103
-logic__9146: logic__9146
-logic__2739: logic__2739
-logic__7421: logic__7421
-logic__8820: logic__8820
-reg__1291: reg__1291
-reg__757: reg__757
-case__675: case__675
-logic__4027: logic__4027
-logic__1169: logic__1169
-reg__270: reg__270
-ram__4: ram__4
-dsp48e1__19: dsp48e1__19
-muxpart__74: muxpart__74
-logic__5352: logic__5352
-logic__8804: logic__8804
-reg__1378: reg__1378
-Repeater_TLBundleA_a29d64s2k1z3u__1: Repeater_TLBundleA_a29d64s2k1z3u
-TLWidthWidget8_4: TLWidthWidget8_4
-logic__6964: logic__6964
-case__906: case__906
-datapath__91: datapath__91
-logic__4431: logic__4431
-logic__4894: logic__4894
-logic__7860: logic__7860
-logic__2845: logic__2845
-reg__594: reg__594
-case__1285: case__1285
-case__1740: case__1412
-logic__9559: logic__1759
-reg__144: reg__144
-logic__8979: logic__8979
-logic__8466: logic__8466
-case__620: case__620
-logic__3430: logic__3430
-logic__3822: logic__3822
-reg__200: reg__200
-reg__1086: reg__1086
-logic__8068: logic__8068
-logic__5522: logic__5522
-RVCExpander: RVCExpander
-muxpart__229: muxpart__229
-case__737: case__737
-reg__504: reg__504
-logic__7813: logic__7813
-datapath__425: datapath__425
-reg__1182: reg__1182
-logic__8367: logic__8367
-case__602: case__602
-logic__472: logic__472
-logic__8709: logic__8709
-datapath__150: datapath__150
-datapath__251: datapath__251
-reg__700: reg__700
-logic__4019: logic__4019
-datapath__619: datapath__619
-reg__1047: reg__1047
-reg__1368: reg__1368
-logic__6052: logic__6052
-logic__6838: logic__6838
-reg__171: reg__171
-reg__1483: reg__1144
-reg__202: reg__202
-logic__8405: logic__8405
-reg__925: reg__925
-logic__9341: logic__9341
-reg__1626: reg__836
-case__141: case__141
-case__255: case__255
-keep__1: keep__1
-logic__6392: logic__6392
-case__191: case__191
-logic__4106: logic__4106
-reg__864: reg__864
-reg__1478: reg__1253
-logic__1377: logic__1377
-case__562: case__562
-case__139: case__139
-counter__14: counter__14
-logic__5673: logic__5673
-case__1654: case__1654
-logic__3769: logic__3769
-reg__1330: reg__1330
-case__1178: case__1178
-reg__1223: reg__1223
-datapath__369: datapath__369
-logic__917: logic__917
-reg__1578: reg__836
-logic__7135: logic__7135
-case__864: case__864
-logic__7992: logic__7992
-datapath__533: datapath__533
-counter__17: counter__17
-datapath__588: datapath__588
-logic__9584: logic__1676
-datapath__24: datapath__24
-case__981: case__981
-logic__1275: logic__1275
-logic__5230: logic__5230
-logic__397: logic__397
-logic__9153: logic__9153
-logic__6032: logic__6032
-logic__5502: logic__5502
-logic__6059: logic__6059
-TLFragmenter_FPGAUART: TLFragmenter_FPGAUART
-logic__2852: logic__2852
-logic__2374: logic__2374
-logic__9765: logic__487
-case__29: case__29
-case__298: case__298
-logic__6747: logic__6747
-logic__9726: logic__6152
-reg__783: reg__783
-muxpart__5: muxpart__5
-counter__29: counter__29
-logic__1462: logic__1462
-reg__601: reg__601
-datapath__799: datapath__95
-datapath__447: datapath__447
-logic__375: logic__375
-logic__4180: logic__4180
-case__929: case__929
-datapath__633: datapath__633
-logic__904: logic__904
-case__404: case__404
-logic__6695: logic__6695
-logic__2503: logic__2503
-reg__523: reg__523
-logic__6469: logic__6469
-logic__8421: logic__8421
-logic__3332: logic__3332
-datapath__529: datapath__529
-case__1757: case__112
-datapath__514: datapath__514
-logic__477: logic__477
-datapath__239: datapath__239
-FPToInt: FPToInt
-logic__7253: logic__7253
-case__814: case__814
-case__1107: case__1107
-case__1064: case__1064
-case__714: case__714
-logic__9529: logic__1848
-case__119: case__119
-logic__5413: logic__5413
-reg__1236: reg__1236
-logic__31: logic__31
-logic__7175: logic__7175
-case__1722: case__315
-logic__9221: logic__9221
-datapath__305: datapath__305
-keep__74: keep__1
-logic__5351: logic__5351
-logic__7439: logic__7439
-logic__6361: logic__6361
-DTLB: DTLB
-case__837: case__837
-reg__797: reg__797
-logic__234: logic__234
-reg__1527: reg__992
-logic__9710: logic__7672
-logic__3089: logic__3089
-case__933: case__933
-logic__9537: logic__1830
-logic__5989: logic__5989
-logic__3938: logic__3938
-reg__657: reg__657
-logic__7601: logic__7601
-logic__7384: logic__7384
-reg__1161: reg__1161
-datapath__721: datapath__721
-logic__9186: logic__9186
-logic__3362: logic__3362
-case__493: case__493
-case__88: case__88
-reg__886: reg__886
-reg__401: reg__401
-logic__956: logic__956
-logic__2999: logic__2999
-logic__4185: logic__4185
-logic__6639: logic__6639
-logic__5071: logic__5071
-reg__1238: reg__1238
-datapath__739: datapath__739
-reg__853: reg__853
-case__1749: case__1053
-logic__7048: logic__7048
-logic__610: logic__610
-ram__11: ram__2
-case__394: case__394
-logic__8891: logic__8891
-logic__9361: logic__9361
-muxpart__167: muxpart__167
-logic__9768: logic__477
-logic__3771: logic__3771
-case__522: case__522
-datapath__49: datapath__49
-reg__382: reg__382
-reg__1522: reg__997
-case__650: case__650
-datapath__189: datapath__189
-logic__7901: logic__7901
-case__441: case__441
-acq_nco_carr: acq_nco_carr
-logic__8892: logic__8892
-logic__2554: logic__2554
-reg__440: reg__440
-logic__6244: logic__6244
-reg__1019: reg__1019
-logic__9293: logic__9293
-logic__4761: logic__4761
-reg__137: reg__137
-logic__7385: logic__7385
-logic__5903: logic__5903
-logic__7669: logic__7669
-logic__9332: logic__9332
-FPToFP: FPToFP
-logic__6703: logic__6703
-logic__4880: logic__4880
-logic__3021: logic__3021
-logic__9486: logic__1847
-case__1054: case__1054
-reg__98: reg__98
-PlusArgTimeout: PlusArgTimeout
-reg__500: reg__500
-logic__9511: logic__1895
-case__1362: case__1362
-reg__127: reg__127
-logic__5447: logic__5447
-logic__5412: logic__5412
-reg__86: reg__86
-logic__317: logic__317
-logic__5545: logic__5545
-reg__981: reg__981
-logic__4222: logic__4222
-logic__1352: logic__1352
-logic__9775: logic__518
-logic__9480: logic__1863
-logic__3760: logic__3760
-case__373: case__373
-logic__1088: logic__1088
-pps_core: pps_core
-case__295: case__295
-keep__16: keep__16
-logic__1784: logic__1784
-logic__6822: logic__6822
-logic__703: logic__703
-logic__1771: logic__1771
-logic__4306: logic__4306
-logic__8152: logic__8152
-counter__10: counter__10
-reg__315: reg__315
-keep__26: keep__26
-logic__5353: logic__5353
-logic__6389: logic__6389
-case__1164: case__1164
-logic__2323: logic__2323
-logic__4635: logic__4635
-reg__1018: reg__1018
-logic__5658: logic__5658
-muxpart__9: muxpart__9
-logic__6852: logic__6852
-logic__6820: logic__6820
-muxpart__55: muxpart__55
-reg__637: reg__637
-logic__2595: logic__2595
-logic__862: logic__862
-dual_port_ram: dual_port_ram
-logic__3594: logic__3594
-logic__2109: logic__2109
-datapath__272: datapath__272
-reg__436: reg__436
-logic__1648: logic__1648
-logic__574: logic__574
-datapath__796: datapath__98
-case__606: case__606
-logic__6062: logic__6062
-reg__216: reg__216
-logic__2808: logic__2808
-logic__7078: logic__7078
-reg__1303: reg__1303
-logic__1109: logic__1109
-reg__1040: reg__1040
-logic__9477: logic__1872
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__2: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__1421: case__1421
-case__610: case__610
-datapath__190: datapath__190
-reg__1591: reg__838
-logic__4941: logic__4941
-case__604: case__604
-logic__9419: logic__2977
-logic__2894: logic__2894
-reg__532: reg__532
-logic__6825: logic__6825
-logic__9613: logic__1605
-logic__7955: logic__7955
-keep__29: keep__29
-datapath__652: datapath__652
-logic__9207: logic__9207
-logic__3243: logic__3243
-datapath__505: datapath__505
-case__1719: case__318
-logic__2289: logic__2289
-logic__6619: logic__6619
-reg__564: reg__564
-logic__7373: logic__7373
-logic__6109: logic__6109
-logic__4347: logic__4347
-case__1697: case__460
-case__514: case__514
-logic__4532: logic__4532
-datapath__578: datapath__578
-logic__4887: logic__4887
-logic__6056: logic__6056
-keep__27: keep__27
-datapath__413: datapath__413
-case__1011: case__1011
-reg__999: reg__999
-logic__9471: logic__1891
-logic__2809: logic__2809
-logic__3571: logic__3571
-case__1005: case__1005
-reg__82: reg__82
-logic__3014: logic__3014
-logic__1535: logic__1535
-logic__9218: logic__9218
-logic__4308: logic__4308
-logic__6845: logic__6845
-logic__2099: logic__2099
-case__321: case__321
-logic__9205: logic__9205
-logic__7431: logic__7431
-logic__9467: logic__1895
-datapath__402: datapath__402
-muxpart__206: muxpart__206
-reg__1554: reg__836
-logic__7201: logic__7201
-datapath__641: datapath__641
-case__379: case__379
-logic__5061: logic__5061
-logic__707: logic__707
-reg__593: reg__593
-datapath__432: datapath__432
-case__419: case__419
-logic__5723: logic__5723
-reg__730: reg__730
-logic__9547: logic__1799
-logic__8630: logic__8630
-logic__8732: logic__8732
-datapath__612: datapath__612
-logic__4226: logic__4226
-logic__6374: logic__6374
-reg__1159: reg__1159
-logic__4076: logic__4076
-logic__4543: logic__4543
-logic__2168: logic__2168
-logic__1162: logic__1162
-datapath__806: datapath__15
-reg__1143: reg__1143
-logic__2608: logic__2608
-logic__6634: logic__6634
-LevelGateway__5: LevelGateway
-logic__4990: logic__4990
-logic__2964: logic__2964
-logic__8194: logic__8194
-logic__2880: logic__2880
-reg__1399: reg__1399
-case__489: case__489
-reg__1459: reg__1459
-logic__6707: logic__6707
-logic__6267: logic__6267
-logic__5694: logic__5694
-ram_2x124: ram_2x124
-logic__3766: logic__3766
-case__775: case__775
-datapath__67: datapath__67
-logic__9684: logic__8270
-reg__1055: reg__1055
-RoundAnyRawFNToRecFN_4: RoundAnyRawFNToRecFN_4
-AsyncValidSync__16: AsyncValidSync
-logic__4623: logic__4623
-case__117: case__117
-trck_top: trck_top
-reg__1575: reg__836
-logic__4353: logic__4353
-reg__737: reg__737
-reg__1301: reg__1301
-muxpart__15: muxpart__15
-logic__7712: logic__7712
-reg__1650: reg__64
-datapath__575: datapath__575
-logic__1430: logic__1430
-logic__4789: logic__4789
-logic__767: logic__767
-case__1126: case__1126
-datapath__73: datapath__73
-logic__7321: logic__7321
-logic__5237: logic__5237
-logic__3336: logic__3336
-logic__6618: logic__6618
-ram__15: ram
-logic__2160: logic__2160
-logic__4289: logic__4289
-ram_2x77__2: ram_2x77
-logic__7788: logic__7788
-muxpart__64: muxpart__64
-logic__3535: logic__3535
-reg__396: reg__396
-datapath__47: datapath__47
-logic__9139: logic__9139
-reg__899: reg__899
-case__71: case__71
-case__603: case__603
-logic__6158: logic__6158
-logic__9109: logic__9109
-logic__7169: logic__7169
-logic__2936: logic__2936
-muxpart__108: muxpart__108
-case__1709: case__526
-double_ff_syn: double_ff_syn
-logic__4551: logic__4551
-logic__8762: logic__8762
-case__1015: case__1015
-logic__6319: logic__6319
-logic__5358: logic__5358
-case__1425: case__1425
-case__1105: case__1105
-logic__2943: logic__2943
-reg__841: reg__841
-datapath__7: datapath__7
-datapath__337: datapath__337
-case__1483: case__1483
-logic__262: logic__262
-logic__14: logic__14
-logic__3118: logic__3118
-logic__5539: logic__5539
-reg__1582: reg__838
-datapath__720: datapath__720
-logic__9290: logic__9290
-case__278: case__278
-datapath__700: datapath__700
-logic__3765: logic__3765
-case__607: case__607
-logic__4134: logic__4134
-case__1227: case__1227
-logic__3055: logic__3055
-reg__398: reg__398
-logic__9622: logic__1586
-logic__7637: logic__7637
-logic__949: logic__949
-reg__893: reg__893
-logic__602: logic__602
-case__31: case__31
-logic__6705: logic__6705
-logic__6336: logic__6336
-case__1099: case__1099
-logic__258: logic__258
-logic__5420: logic__5420
-logic__4866: logic__4866
-case__1611: case__1611
-logic__9398: logic__3021
-reg__798: reg__798
-case__140: case__140
-logic__9399: logic__3016
-reg__1283: reg__1283
-logic__6741: logic__6741
-reg__1662: reg__63
-logic__3803: logic__3803
-logic__6457: logic__6457
-case__280: case__280
-logic__90: logic__90
-case__1759: case__110
-datapath__8: datapath__8
-case__1416: case__1416
-datapath__426: datapath__426
-logic__7406: logic__7406
-reg__933: reg__933
-logic__9724: logic__6152
-logic__6651: logic__6651
-muxpart__308: muxpart__308
-logic__2970: logic__2970
-logic__9445: logic__3935
-reg__988: reg__988
-ram__5: ram__5
-logic__4684: logic__4684
-logic__9424: logic__3993
-reg__213: reg__213
-reg__1091: reg__1091
-sync: sync
-logic__2859: logic__2859
-reg__534: reg__534
-logic__3673: logic__3673
-logic__3091: logic__3091
-FPUFMAPipe_l3_f32: FPUFMAPipe_l3_f32
-case__1228: case__1228
-case__1226: case__1226
-logic__4836: logic__4836
-logic__9760: logic__496
-logic__9731: logic__6147
-logic__9489: logic__1842
-reg__1386: reg__1386
-logic__8278: logic__8278
-reg__372: reg__372
-logic__1463: logic__1463
-logic__4420: logic__4420
-logic__9434: logic__3955
-logic__2681: logic__2681
-logic__6854: logic__6854
-logic__6840: logic__6840
-reg__1613: reg__837
-reg__1127: reg__1127
-datapath__473: datapath__473
-reg__920: reg__920
-logic__9354: logic__9354
-datapath__97: datapath__97
-dsp48e1__12: dsp48e1__12
-logic__109: logic__109
-logic__2395: logic__2395
-logic__9500: logic__1927
-logic__3388: logic__3388
-case__481: case__481
-logic__3088: logic__3088
-reg__1056: reg__1056
-logic__4528: logic__4528
-logic__6033: logic__6033
-logic__3209: logic__3209
-logic__6113: logic__6113
-reg__66: reg__66
-logic__4660: logic__4660
-RocketTile__GCB0: RocketTile__GCB0
-logic__6654: logic__6654
-counter__30: counter__30
-datapath__740: datapath__302
-logic__8332: logic__8332
-logic__7022: logic__7022
-logic__1286: logic__1286
-muxpart__193: muxpart__193
-reg__1314: reg__1314
-logic__9176: logic__9176
-logic__3747: logic__3747
-logic__2718: logic__2718
-logic__6044: logic__6044
-logic__6977: logic__6977
-reg__522: reg__522
-case__567: case__567
-logic__8777: logic__8777
-logic__2391: logic__2391
-case__303: case__303
-TLDebugModuleInner: TLDebugModuleInner
-logic__8943: logic__8943
-ram__9: ram__1
-logic__3176: logic__3176
-case__1423: case__1423
-logic__2461: logic__2461
-logic__9144: logic__9144
-logic__2213: logic__2213
-reg__1404: reg__1404
-logic__6821: logic__6821
-case__731: case__731
-logic__9767: logic__483
-reg__1484: reg__1144
-reg__559: reg__559
-logic__3385: logic__3385
-logic__3729: logic__3729
-logic__2887: logic__2887
-case__1777: case__103
-logic__7021: logic__7021
-datapath__108: datapath__108
-logic__5325: logic__5325
-datapath__408: datapath__408
-logic__4760: logic__4760
-logic__1722: logic__1722
-logic__3695: logic__3695
-reg__973: reg__973
-keep__13: keep__13
-logic__5280: logic__5280
-logic__3418: logic__3418
-reg__1621: reg__838
-twiddle_ram: twiddle_ram
-logic__4912: logic__4912
-case__1610: case__1610
-logic__548: logic__548
-reg__1487: reg__1144
-logic__4573: logic__4573
-datapath__288: datapath__288
-case__854: case__854
-logic__4727: logic__4727
-reg__36: reg__36
-case__1601: case__1601
-case__1050: case__1050
-logic__1295: logic__1295
-logic__2863: logic__2863
-logic__6789: logic__6789
-logic__9390: logic__3055
-datapath__448: datapath__448
-logic__5281: logic__5281
-reg__519: reg__519
-logic__3764: logic__3764
-logic__2977: logic__2977
-logic__1699: logic__1699
-logic__3868: logic__3868
-logic__9367: logic__9367
-keep__19: keep__19
-reg__993: reg__993
-case__523: case__523
-datapath__212: datapath__212
-logic__8191: logic__8191
-logic__8849: logic__8849
-case__45: case__45
-reg__1563: reg__836
-logic__2217: logic__2217
-case__676: case__676
-reg__699: reg__699
-logic__8050: logic__8050
-logic__4788: logic__4788
-datapath__232: datapath__232
-logic__8915: logic__8915
-logic__4586: logic__4586
-logic__9543: logic__1812
-logic__2855: logic__2855
-logic__2723: logic__2723
-reg__850: reg__850
-reg__1463: reg__20
-reg__223: reg__223
-logic__4764: logic__4764
-reg__412: reg__412
-ram_2x78: ram_2x78
-datapath__55: datapath__55
-muxpart__216: muxpart__216
-logic__9288: logic__9288
-reg__1548: reg__836
-reg__1526: reg__993
-case__1028: case__1028
-datapath__187: datapath__187
-case__190: case__190
-case__762: case__762
-datapath__262: datapath__262
-datapath__666: datapath__666
-logic__5439: logic__5439
-reg__1616: reg__837
-logic__7259: logic__7259
-logic__3460: logic__3460
-logic__1782: logic__1782
-case__179: case__179
-logic__254: logic__254
-logic__905: logic__905
-logic__7969: logic__7969
-case__553: case__553
-logic__6063: logic__6063
-reg__271: reg__271
-datapath__287: datapath__287
-case__1233: case__1233
-reg__1383: reg__1383
-reg__846: reg__846
-case__1066: case__1066
-logic__8776: logic__8776
-TLBuffer_a32d64s1k1z4u__1: TLBuffer_a32d64s1k1z4u
-logic__9690: logic__8272
-reg__1546: reg__838
-ram__13: ram__1
-datapath__746: datapath__360
-case__1430: case__1430
-logic__1190: logic__1190
-keep__71: keep
-logic__6814: logic__6814
-datapath__430: datapath__430
-datapath__716: datapath__716
-logic__3387: logic__3387
-logic__3492: logic__3492
-reg__1157: reg__1157
-logic__4976: logic__4976
-case__1679: case__1679
-logic__2730: logic__2730
-logic__7653: logic__7653
-logic__6828: logic__6828
-logic__6411: logic__6411
-reg__1230: reg__1230
-logic__3782: logic__3782
-Queue1_RegMapperInput_i9_m8__1: Queue1_RegMapperInput_i9_m8
-reg__1112: reg__1112
-logic__4765: logic__4765
-logic__4485: logic__4485
-TLFragmenter_FPGAGPS: TLFragmenter_FPGAGPS
-logic__7956: logic__7956
-reg__1632: reg__784
-logic__4117: logic__4117
-logic__4522: logic__4522
-logic__1192: logic__1192
-reg__184: reg__184
-reg__568: reg__568
-logic__4171: logic__4171
-logic__7636: logic__7636
-reg__1405: reg__1405
-reg__691: reg__691
-case__559: case__559
-counter__33: counter__33
-logic__1538: logic__1538
-datapath__52: datapath__52
-reg__1203: reg__1203
-case__1232: case__1232
-logic__3563: logic__3563
-logic__9450: logic__3930
-logic__9493: logic__1944
-case__154: case__154
-case__75: case__75
-logic__5894: logic__5894
-reg__1217: reg__1217
-logic__1012: logic__1012
-sync__5: sync
-logic__1234: logic__1234
-case__32: case__32
-logic__4079: logic__4079
-logic__3641: logic__3641
-logic__7225: logic__7225
-case__469: case__469
-logic__4913: logic__4913
-logic__476: logic__476
-logic__6583: logic__6583
-datapath__76: datapath__76
-datapath__535: datapath__535
-case__653: case__653
-logic__9268: logic__9268
-logic__5434: logic__5434
-logic__9384: logic__9384
-muxpart__18: muxpart__18
-datapath__325: datapath__325
-logic__4034: logic__4034
-case__770: case__770
-reg__514: reg__514
-case__430: case__430
-logic__7432: logic__7432
-muxpart__94: muxpart__94
-logic__2346: logic__2346
-case__287: case__287
-datapath__530: datapath__530
-logic__4137: logic__4137
-case__757: case__757
-logic__3414: logic__3414
-case__214: case__214
-logic__9658: logic__281
-reg__1321: reg__1321
-case__1623: case__1623
-muxpart__53: muxpart__53
-TLFpgaSPI__1: TLFpgaSPI
-datapath__147: datapath__147
-datapath__215: datapath__215
-logic__104: logic__104
-reg__1174: reg__1174
-datapath__203: datapath__203
-datapath__708: datapath__708
-case__172: case__172
-logic__6249: logic__6249
-TLInterconnectCoupler_sbus_from_rockettile: TLInterconnectCoupler_sbus_from_rockettile
-case__1200: case__1200
-muxpart__226: muxpart__226
-logic__7036: logic__7036
-case__794: case__794
-logic__4486: logic__4486
-case__1678: case__1678
-reg__889: reg__889
-IntSyncCrossingSource_n1x1_Registered: IntSyncCrossingSource_n1x1_Registered
-reg__958: reg__958
-reg__1434: reg__1434
-datapath__496: datapath__496
-case__211: case__211
-logic__2136: logic__2136
-datapath__600: datapath__600
-muxpart__39: muxpart__39
-counter__21: counter__21
-logic__8706: logic__8706
-reg__1396: reg__1396
-logic__2976: logic__2976
-logic__1525: logic__1525
-case__1691: case__1691
-reg__218: reg__218
-datapath__25: datapath__25
-logic__6159: logic__6159
-logic__8972: logic__8972
-case__1763: case__106
-logic__3462: logic__3462
-logic__1376: logic__1376
-reg__1036: reg__1036
-reg__1569: reg__836
-logic__9466: logic__1896
-reg__1409: reg__1409
-reg__374: reg__374
-logic__2654: logic__2654
-datapath__364: datapath__364
-logic__3187: logic__3187
-case__285: case__285
-logic__9737: logic__6147
-datapath__546: datapath__546
-case__376: case__376
-logic__7009: logic__7009
-reg__950: reg__950
-logic__301: logic__301
-reg__1520: reg__974
-case__857: case__857
-reg__1646: reg__68
-logic__4793: logic__4793
-logic__7554: logic__7554
-reg__1041: reg__1041
-logic__3940: logic__3940
-logic__8272: logic__8272
-case__518: case__518
-logic__9360: logic__9360
-logic__4342: logic__4342
-reg__1426: reg__1426
-logic__3678: logic__3678
-reg__1175: reg__1175
-logic__1629: logic__1629
-case__885: case__885
-reg__879: reg__879
-logic__3761: logic__3761
-logic__1743: logic__1743
-logic__8313: logic__8313
-logic__7675: logic__7675
-logic__6520: logic__6520
-reg__813: reg__813
-logic__663: logic__663
-datapath__285: datapath__285
-datapath__296: datapath__296
-logic__3656: logic__3656
-IntSyncCrossingSource_n1x1__3: IntSyncCrossingSource_n1x1
-datapath__126: datapath__126
-datapath__80: datapath__80
-case__434: case__434
-logic__1191: logic__1191
-logic__7948: logic__7948
-datapath__732: datapath__732
-reg__570: reg__570
-logic__2563: logic__2563
-SystemBus: SystemBus
-case__577: case__577
-reg__1038: reg__1038
-nav_solve_timer: nav_solve_timer
-logic__6982: logic__6982
-reg__1449: reg__1449
-logic__1296: logic__1296
-case__1069: case__1069
-logic__2614: logic__2614
-logic__8858: logic__8858
-logic__6479: logic__6479
-case__570: case__570
-logic__974: logic__974
-logic__3754: logic__3754
-reg__1472: reg__117
-LevelGateway__8: LevelGateway
-addsub__5: addsub__5
-case__746: case__746
-logic__5056: logic__5056
-logic__1508: logic__1508
-datapath__714: datapath__714
-logic__7584: logic__7584
-datapath__468: datapath__468
-logic__337: logic__337
-logic__9558: logic__1762
-case__890: case__890
-reg__882: reg__882
-logic__492: logic__492
-logic__4236: logic__4236
-logic__5518: logic__5518
-logic__1231: logic__1231
-reg__511: reg__511
-case__301: case__301
-logic__9353: logic__9353
-reg__1260: reg__1260
-reg__121: reg__121
-case__1547: case__1547
-datapath__77: datapath__77
-case__1031: case__1031
-reg__1414: reg__1414
-reg__360: reg__360
-case__764: case__764
-logic__2241: logic__2241
-reg__1556: reg__837
-reg__1612: reg__838
-logic__5402: logic__5402
-case__1539: case__1539
-logic__4348: logic__4348
-logic__3473: logic__3473
-logic__9102: logic__9102
-logic__5891: logic__5891
-keep__62: keep__7
-CLINTClockSinkDomain: CLINTClockSinkDomain
-case__1280: case__1280
-datapath__564: datapath__564
-reg__644: reg__644
-logic__5350: logic__5350
-case__199: case__199
-case__209: case__209
-logic__1878: logic__1878
-case__1045: case__1045
-logic__1157: logic__1157
-reg__1206: reg__1206
-case__649: case__649
-datapath__148: datapath__148
-reg__670: reg__670
-logic__9182: logic__9182
-logic__5675: logic__5675
-keep__61: keep__8
-datapath__110: datapath__110
-logic__4972: logic__4972
-case__657: case__657
-logic__4476: logic__4476
-datapath__383: datapath__383
-logic__779: logic__779
-logic__9692: logic__8270
-reg__1452: reg__1452
-datapath__703: datapath__703
-logic__6318: logic__6318
-logic__2682: logic__2682
-reg__652: reg__652
-logic__8084: logic__8084
-logic__4925: logic__4925
-logic__2296: logic__2296
-reg__945: reg__945
-logic__916: logic__916
-logic__7144: logic__7144
-logic__383: logic__383
-logic__5224: logic__5224
-logic__7241: logic__7241
-logic__2193: logic__2193
-IntSyncCrossingSource_n1x1__2: IntSyncCrossingSource_n1x1
-ClockGroupAggregator_pbus: ClockGroupAggregator_pbus
-logic__5890: logic__5890
-reg__1085: reg__1085
-case__262: case__262
-datapath__527: datapath__527
-reg__1446: reg__1446
-logic__2023: logic__2023
-reg__205: reg__205
-logic__1159: logic__1159
-case__142: case__142
-case__974: case__974
-datapath__151: datapath__151
-case__121: case__121
-logic__9164: logic__9164
-reg__1095: reg__1095
-logic__557: logic__557
-logic__9169: logic__9169
-reg__323: reg__323
-logic__1927: logic__1927
-logic__6504: logic__6504
-logic__5893: logic__5893
-reg__946: reg__946
-reg__885: reg__885
-logic__1067: logic__1067
-muxpart__88: muxpart__88
-logic__345: logic__345
-reg__1168: reg__1168
-logic__3698: logic__3698
-datapath__58: datapath__58
-logic__137: logic__137
-logic__5293: logic__5293
-datapath__301: datapath__301
-datapath__669: datapath__669
-logic__1209: logic__1209
-case__159: case__159
-logic__9648: logic__1528
-reg__151: reg__151
-datapath__521: datapath__521
-logic__4905: logic__4905
-reg__1542: reg__836
-logic__3138: logic__3138
-logic__7220: logic__7220
-reg__574: reg__574
-logic__7480: logic__7480
-case__1026: case__1026
-case__498: case__498
-logic__5305: logic__5305
-reg__1550: reg__837
-logic__2713: logic__2713
-datapath__332: datapath__332
-datapath__258: datapath__258
-logic__3134: logic__3134
-muxpart__109: muxpart__109
-logic__7708: logic__7708
-case__761: case__761
-logic__4014: logic__4014
-case__405: case__405
-reg__304: reg__304
-AsyncQueueSource_TLBundleA_a9d32s1k1z2u: AsyncQueueSource_TLBundleA_a9d32s1k1z2u
-keep__36: keep__36
-case__1492: case__1492
-logic__2568: logic__2568
-datapath__14: datapath__14
-logic__6776: logic__6776
-reg__390: reg__390
-logic__7736: logic__7736
-logic__3763: logic__3763
-logic__4837: logic__4837
-logic__6702: logic__6702
-case__831: case__831
-reg__1090: reg__1090
-reg__1373: reg__1373
-logic__954: logic__954
-logic__4170: logic__4170
-case__784: case__784
-case__1345: case__1345
-logic__9462: logic__1909
-muxpart__104: muxpart__104
-logic__8708: logic__8708
-logic__1066: logic__1066
-logic__1336: logic__1336
-logic__6017: logic__6017
-logic__3808: logic__3808
-case__1391: case__1391
-case__1556: case__1556
-reg__926: reg__926
-logic__6035: logic__6035
-logic__6184: logic__6184
-case__600: case__600
-logic__2333: logic__2333
-reg__970: reg__970
-logic__9460: logic__1916
-datapath__246: datapath__246
-reg__1008: reg__1008
-case__590: case__590
-case__1396: case__1396
-case__386: case__386
-logic__1357: logic__1357
-datapath__208: datapath__208
-reg__1411: reg__1411
-logic__8075: logic__8075
-logic__7936: logic__7936
-reg__904: reg__904
-logic__9446: logic__3934
-logic__9795: logic__475
-logic__9404: logic__3007
-datapath__664: datapath__664
-logic__5065: logic__5065
-logic__4382: logic__4382
-reg__507: reg__507
-logic__9492: logic__1945
-case__1631: case__1631
-logic__9712: logic__7670
-logic__6761: logic__6761
-case__1165: case__1165
-reg__1272: reg__1272
-Repeater_TLBundleA_a17d64s2k1z3u: Repeater_TLBundleA_a17d64s2k1z3u
-logic__1756: logic__1756
-double_ff_syn__parameterized0: double_ff_syn__parameterized0
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__15: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__8286: logic__8286
-case__674: case__674
-case__1707: case__528
-reg__621: reg__621
-reg__563: reg__563
-case__173: case__173
-logic__8603: logic__8603
-muxpart__16: muxpart__16
-case__722: case__722
-reg__959: reg__959
-muxpart__91: muxpart__91
-logic__9624: logic__1578
-logic__592: logic__592
-logic__8778: logic__8778
-reg__1196: reg__1196
-logic__9506: logic__1909
-logic__8166: logic__8166
-reg__1289: reg__1289
-case__1022: case__1022
-reg__1372: reg__1372
-case__367: case__367
-logic__6069: logic__6069
-TLXbar_sbus_i2_o1_a32d64s2k1z4u: TLXbar_sbus_i2_o1_a32d64s2k1z4u
-logic__281: logic__281
-logic__4508: logic__4508
-logic__2046: logic__2046
-case__1745: case__1058
-logic__7872: logic__7872
-addsub__3: addsub__3
-logic__5438: logic__5438
-reg__1537: reg__838
-case__133: case__133
-muxpart__300: muxpart__300
-case__735: case__735
-reg__1209: reg__1209
-MulAddRecFNToRaw_preMul_1: MulAddRecFNToRaw_preMul_1
-logic__3167: logic__3167
-reg__1588: reg__838
-reg__1133: reg__1133
-logic__644: logic__644
-logic__6320: logic__6320
-logic__9277: logic__9277
-reg__941: reg__941
-case__243: case__243
-reg__890: reg__890
-datapath__485: datapath__485
-logic__4907: logic__4907
-logic__8818: logic__8818
-logic__532: logic__532
-case__415: case__415
-datapath__319: datapath__319
-logic__4763: logic__4763
-logic__8276: logic__8276
-logic__8759: logic__8759
-keep__60: keep__6
-datapath__116: datapath__116
-muxpart__223: muxpart__223
-logic__1370: logic__1370
-ram_2x120: ram_2x120
-logic__3461: logic__3461
-logic__5336: logic__5336
-logic__2856: logic__2856
-logic__5289: logic__5289
-reg__160: reg__160
-logic__8532: logic__8532
-case__1038: case__1038
-reg__491: reg__491
-reg__1187: reg__1187
-case__1343: case__1343
-reg__1635: reg__784
-logic__2383: logic__2383
-muxpart__115: muxpart__115
-logic__1030: logic__1030
-logic__2343: logic__2343
-case__702: case__702
-logic__498: logic__498
-logic__9554: logic__1776
-reg__539: reg__539
-logic__9718: logic__7587
-reg__952: reg__952
-logic__6830: logic__6830
-extrom__4: extrom__1
-muxpart__103: muxpart__103
-case__898: case__898
-TLDebugModuleOuterAsync: TLDebugModuleOuterAsync
-reg__1497: reg__999
-logic__8176: logic__8176
-logic__7687: logic__7687
-logic__6760: logic__6760
-logic__6322: logic__6322
-case__332: case__332
-logic__8837: logic__8837
-logic__7576: logic__7576
-datapath__779: datapath__649
-logic__2680: logic__2680
-reg__1619: reg__837
-reg__425: reg__425
-case__892: case__892
-case__258: case__258
-case__1314: case__1314
-logic__4744: logic__4744
-logic__7561: logic__7561
-datapath__711: datapath__711
-logic__3933: logic__3933
-logic__3725: logic__3725
-logic__2531: logic__2531
-logic__7438: logic__7438
-logic__9393: logic__3032
-logic__3806: logic__3806
-logic__1003: logic__1003
-ram_2x123: ram_2x123
-logic__8151: logic__8151
-logic__5326: logic__5326
-reg__953: reg__953
-logic__8354: logic__8354
-logic__8731: logic__8731
-logic__8443: logic__8443
-reg__1536: reg__836
-cordic_angle_lut: cordic_angle_lut
-reg__256: reg__256
-logic__6836: logic__6836
-logic__288: logic__288
-logic__1305: logic__1305
-logic__1857: logic__1857
-logic__3628: logic__3628
-logic__7190: logic__7190
-logic__6796: logic__6796
-datapath__263: datapath__263
-logic__3357: logic__3357
-logic__9295: logic__9295
-logic__7691: logic__7691
-logic__1290: logic__1290
-reg__1035: reg__1035
-reg__296: reg__296
-logic__5337: logic__5337
-datapath__70: datapath__70
-logic__7276: logic__7276
-logic__6328: logic__6328
-logic__4988: logic__4988
-datapath__330: datapath__330
-case__333: case__333
-case__1059: case__1059
-reg__1132: reg__1132
-case__475: case__475
-datapath__493: datapath__493
-logic__1815: logic__1815
-reg__1310: reg__1310
-logic__1568: logic__1568
-logic__4787: logic__4787
-dsp48e1__34: dsp48e1__34
-reg__1562: reg__837
-logic__9696: logic__9290
-case__1665: case__1665
-logic__5086: logic__5086
-logic__660: logic__660
-TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u: TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u
-logic__646: logic__646
-case__1527: case__1527
-reg__399: reg__399
-datapath__81: datapath__81
-logic__9365: logic__9365
-case__40: case__40
-logic__5205: logic__5205
-datapath__135: datapath__135
-datapath__177: datapath__177
-datapath__142: datapath__142
-logic__8279: logic__8279
-reg__359: reg__359
-reg__1046: reg__1046
-BreakpointUnit: BreakpointUnit
-case__1395: case__1395
-case__1196: case__1196
-case__132: case__132
-case__1034: case__1034
-case__1182: case__1182
-logic__1802: logic__1802
-logic__9422: logic__2967
-case__497: case__497
-logic__9333: logic__9333
-logic__6253: logic__6253
-reg__1479: reg__1252
-case__1706: case__529
-logic__7055: logic__7055
-reg__720: reg__720
-logic__5355: logic__5355
-datapath__320: datapath__320
-case__91: case__91
-case__1413: case__1413
-mult_46_15_61__3: mult_46_15_61
-logic__6534: logic__6534
-logic__7663: logic__7663
-reg__1401: reg__1401
-logic__3136: logic__3136
-case__26: case__26
-logic__9691: logic__8271
-case__821: case__821
-case__503: case__503
-datapath__149: datapath__149
-logic__2223: logic__2223
-logic__1350: logic__1350
-case__257: case__257
-datapath__728: datapath__728
-logic__6849: logic__6849
-case__1490: case__1490
-case__480: case__480
-case__1450: case__1450
-reg__1189: reg__1189
-datapath__128: datapath__128
-reg__543: reg__543
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__5: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6310: logic__6310
-logic__1632: logic__1632
-logic__9108: logic__9108
-logic__9265: logic__9265
-logic__6680: logic__6680
-reg__1261: reg__1261
-logic__4120: logic__4120
-logic__6531: logic__6531
-logic__277: logic__277
-reg__242: reg__242
-reg__1665: reg__36
-logic__8204: logic__8204
-logic__9496: logic__1935
-case__1363: case__1363
-datapath__269: datapath__269
-logic__7418: logic__7418
-datapath__798: datapath__96
-case__651: case__651
-logic__9188: logic__9188
-logic__9589: logic__1661
-logic__6559: logic__6559
-logic__718: logic__718
-logic__1572: logic__1572
-logic__331: logic__331
-reg__319: reg__319
-case__1473: case__1473
-case__330: case__330
-logic__6047: logic__6047
-logic__5323: logic__5323
-logic__1230: logic__1230
-reg__1385: reg__1385
-case__195: case__195
-case__728: case__728
-logic__6757: logic__6757
-logic__7361: logic__7361
-ram_2x123__1: ram_2x123
-logic__6614: logic__6614
-logic__1464: logic__1464
-datapath__165: datapath__165
-CSRFile: CSRFile
-reg__1393: reg__1393
-reg__422: reg__422
-logic__1554: logic__1554
-reg__1284: reg__1284
-case__509: case__509
-logic__6782: logic__6782
-case__491: case__491
-logic__2944: logic__2944
-case__723: case__723
-logic__669: logic__669
-SynchronizerShiftReg_w1_d3__1: SynchronizerShiftReg_w1_d3
-logic__7454: logic__7454
-PLICFanIn: PLICFanIn
-reg__842: reg__842
-case__1689: case__1689
-case__203: case__203
-reg__1625: reg__837
-reg__1010: reg__1010
-logic__3036: logic__3036
-datapath__557: datapath__557
-logic__6428: logic__6428
-datapath__85: datapath__85
-logic__202: logic__202
-logic__4900: logic__4900
-datapath__146: datapath__146
-datapath__626: datapath__626
-datapath__517: datapath__517
-case__1144: case__1144
-case__227: case__227
-counter__35: counter__35
-reg__445: reg__445
-reg__23: reg__23
-logic__4022: logic__4022
-logic__1641: logic__1641
-logic__6152: logic__6152
-extram__9: extram__2
-logic__4533: logic__4533
-logic__6402: logic__6402
-muxpart__51: muxpart__51
-logic__3205: logic__3205
-datapath__309: datapath__309
-reg__75: reg__75
-datapath__556: datapath__556
-reg__910: reg__910
-reg__1507: reg__838
-case__597: case__597
-logic__2129: logic__2129
-IBuf: IBuf
-datapath__260: datapath__260
-datapath__449: datapath__449
-logic__5306: logic__5306
-logic__3561: logic__3561
-logic__833: logic__833
-case__395: case__395
-logic__8600: logic__8600
-reg__525: reg__525
-logic__2095: logic__2095
-logic__3708: logic__3708
-muxpart__117: muxpart__117
-logic__6289: logic__6289
-logic__517: logic__517
-logic__7615: logic__7615
-datapath__509: datapath__509
-logic__614: logic__614
-datapath__6: datapath__6
-case__1096: case__1096
-logic__3487: logic__3487
-divider__parameterized0: divider__parameterized0
-logic__168: logic__168
-logic__4956: logic__4956
-reg__1096: reg__1096
-reg__974: reg__974
-logic__546: logic__546
-logic__3588: logic__3588
-logic__9106: logic__9106
-logic__5887: logic__5887
-case__402: case__402
-reg__124: reg__124
-reg__228: reg__228
-case__194: case__194
-RoundRawFNToRecFN: RoundRawFNToRecFN
-logic__6478: logic__6478
-case__268: case__268
-reg__1491: reg__1144
-logic__642: logic__642
-logic__4128: logic__4128
-logic__3860: logic__3860
-datapath__211: datapath__211
-reg__643: reg__643
-logic__9735: logic__6147
-dsp48e1__29: dsp48e1__29
-logic__9781: logic__508
-counter__38: counter__38
-logic__312: logic__312
-case__1422: case__1422
-logic__7973: logic__7973
-keep__4: keep__4
-reg__1097: reg__1097
-reg__538: reg__538
-reg__1124: reg__1124
-keep__56: keep__7
-reg__123: reg__123
-datapath__331: datapath__331
-reg__1377: reg__1377
-case__1420: case__1420
-logic__2339: logic__2339
-case__16: case__16
-case__182: case__182
-case__916: case__916
-datapath__736: datapath__736
-cordic_atan_basic__parameterized0: cordic_atan_basic__parameterized0
-case__1056: case__1056
-logic__624: logic__624
-logic__9567: logic__1731
-case__1357: case__1357
-logic__9397: logic__3022
-datapath__439: datapath__439
-logic__9115: logic__9115
-logic__483: logic__483
-keep__17: keep__17
-datapath__691: datapath__691
-datapath__750: datapath__250
-logic__8805: logic__8805
-datapath__705: datapath__705
-case__1630: case__1630
-case__1530: case__1530
-reg__286: reg__286
-reg__820: reg__820
-logic__9709: logic__7675
-reg__909: reg__909
-reg__1001: reg__1001
-reg__1000: reg__1000
-datapath__345: datapath__345
-reg__326: reg__326
-logic__6383: logic__6383
-datapath__79: datapath__79
-reg__347: reg__347
-sync__4: sync
-reg__361: reg__361
-reg__690: reg__690
-logic__1565: logic__1565
-reg__1207: reg__1207
-logic__8410: logic__8410
-reg__1350: reg__1350
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__13: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__952: case__952
-datapath__342: datapath__342
-case__1528: case__1528
-logic__6797: logic__6797
-mult_32_27_59: mult_32_27_59
-logic__4320: logic__4320
-datapath__497: datapath__497
-reg__784: reg__784
-logic__7413: logic__7413
-reg__136: reg__136
-case__1368: case__1368
-logic__6753: logic__6753
-logic__9252: logic__9252
-dsp48e1__13: dsp48e1__13
-datapath__637: datapath__637
-case__1071: case__1071
-muxpart__59: muxpart__59
-logic__9512: logic__1894
-datapath__715: datapath__715
-logic__7309: logic__7309
-logic__5999: logic__5999
-logic__9451: logic__3924
-logic__3052: logic__3052
-case__928: case__928
-case__788: case__788
-logic__3814: logic__3814
-case__1723: case__314
-case__986: case__986
-RoundRawFNToRecFN__1: RoundRawFNToRecFN
-ram_2x115: ram_2x115
-reg__1002: reg__1002
-TLInterconnectCoupler_cbus_to_bus_named_pbus: TLInterconnectCoupler_cbus_to_bus_named_pbus
-logic__9096: logic__9096
-case__912: case__912
-acq_top: acq_top
-logic__2873: logic__2873
-reg__1171: reg__1171
-case__1044: case__1044
-logic__9442: logic__3938
-datapath__475: datapath__475
-case__1090: case__1090
-reg__133: reg__133
-reg__1216: reg__1216
-logic__3924: logic__3924
-logic__9561: logic__1751
-muxpart__106: muxpart__106
-case__1235: case__1235
-reg__435: reg__435
-logic__5406: logic__5406
-case__865: case__865
-logic__9614: logic__1604
-datapath__470: datapath__470
-case__426: case__426
-logic__1711: logic__1711
-case__360: case__360
-muxpart__63: muxpart__63
-logic__9167: logic__9167
-logic__5315: logic__5315
-reg__348: reg__348
-RoundAnyRawFNToRecFN_1: RoundAnyRawFNToRecFN_1
-case__1242: case__1242
-logic__6412: logic__6412
-reg__1538: reg__837
-datapath__163: datapath__163
-case__63: case__63
-reg__26: reg__26
-logic__8911: logic__8911
-datapath__654: datapath__654
-tracking_wrapper: tracking_wrapper
-dual_port_bram__parameterized1: dual_port_bram__parameterized1
-logic__7892: logic__7892
-logic__8981: logic__8981
-logic__7297: logic__7297
-case__584: case__584
-reg__102: reg__102
-logic__2110: logic__2110
-logic__3871: logic__3871
-logic__4165: logic__4165
-reg__1361: reg__1361
-reg__1496: reg__1000
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__21: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__1110: logic__1110
-case__177: case__177
-case__1130: case__1130
-datapath__639: datapath__639
-logic__5718: logic__5718
-logic__1244: logic__1244
-reg__450: reg__450
-datapath__390: datapath__390
-logic__7490: logic__7490
-logic__5467: logic__5467
-logic__6585: logic__6585
-datapath__318: datapath__318
-logic__2823: logic__2823
-case__886: case__886
-logic__601: logic__601
-logic__553: logic__553
-reg__376: reg__376
-logic__9670: logic__653
-logic__1401: logic__1401
-logic__5072: logic__5072
-logic__5322: logic__5322
-logic__6453: logic__6453
-reg__951: reg__951
-reg__373: reg__373
-case__184: case__184
-logic__5137: logic__5137
-double_ff_syn__4: double_ff_syn
-datapath__271: datapath__271
-reg__1169: reg__1169
-case__24: case__24
-logic__2218: logic__2218
-logic__7333: logic__7333
-reg__1079: reg__1079
-case__950: case__950
-logic__9148: logic__9148
-reg__745: reg__745
-logic__6499: logic__6499
-reg__849: reg__849
-case__1053: case__1053
-counter__34: counter__34
-reg__268: reg__268
-case__1684: case__1684
-datapath__795: datapath__95
-case__200: case__200
-case__546: case__546
-logic__983: logic__983
-logic__7757: logic__7757
-datapath__532: datapath__532
-logic__9171: logic__9171
-logic__66: logic__66
-reg__854: reg__854
-logic__290: logic__290
-logic__5003: logic__5003
-case__856: case__856
-dsp48e1__37: dsp48e1__37
-case__782: case__782
-reg__1617: reg__836
-case__1765: case__104
-extrom: extrom
-Arbiter2_Valid_PTWReq: Arbiter2_Valid_PTWReq
-reg__1597: reg__838
-logic__552: logic__552
-case__411: case__411
-logic__3596: logic__3596
-logic__6108: logic__6108
-logic__2436: logic__2436
-logic__5294: logic__5294
-logic__4322: logic__4322
-logic__1611: logic__1611
-reg__303: reg__303
-reg__975: reg__975
-logic__7054: logic__7054
-case__732: case__732
-OptimizationBarrier_TLBEntryData__2: OptimizationBarrier_TLBEntryData
-logic__7721: logic__7721
-extladd__1: extladd__1
-reg__1349: reg__1349
-case__246: case__246
-case__544: case__544
-logic__3883: logic__3883
-reg__869: reg__869
-datapath__243: datapath__243
-datapath__268: datapath__268
-reg__930: reg__930
-logic__1349: logic__1349
-bram: bram
-mult_64_48_112__1: mult_64_48_112
-extrom__5: extrom
-reg__1392: reg__1392
-logic__5837: logic__5837
-logic__9699: logic__7585
-case__519: case__519
-datapath__610: datapath__610
-case__68: case__68
-reg__370: reg__370
-AsyncResetSynchronizerShiftReg_w1_d3_i0: AsyncResetSynchronizerShiftReg_w1_d3_i0
-muxpart__303: muxpart__303
-logic__4786: logic__4786
-logic__2252: logic__2252
-logic__4247: logic__4247
-AsyncQueueSink_DebugInternalBundle: AsyncQueueSink_DebugInternalBundle
-logic__9373: logic__9373
-counter__23: counter__23
-logic__6755: logic__6755
-reg__174: reg__174
-logic__7873: logic__7873
-logic__2673: logic__2673
-reg__1011: reg__1011
-case__1461: case__1461
-logic__9659: logic__277
-logic__2283: logic__2283
-logic__9296: logic__9296
-datapath__401: datapath__401
-logic__9159: logic__9159
-logic__5661: logic__5661
-case__763: case__763
-logic__9688: logic__8270
-datapath__252: datapath__252
-muxpart__233: muxpart__233
-logic__9701: logic__7708
-logic__5265: logic__5265
-logic__3465: logic__3465
-logic__539: logic__539
-logic__3591: logic__3591
-logic__2196: logic__2196
-logic__1945: logic__1945
-reg__146: reg__146
-logic__3515: logic__3515
-case__466: case__466
-reg__342: reg__342
-logic__9231: logic__9231
-reg__1651: reg__63
-case__377: case__377
-reg__251: reg__251
-muxpart__70: muxpart__70
-Arbiter3_LLWB: Arbiter3_LLWB
-logic__1102: logic__1102
-counter__7: counter__7
-logic__8787: logic__8787
-logic__6542: logic__6542
-case__693: case__693
-logic__4507: logic__4507
-logic__9195: logic__9195
-logic__5956: logic__5956
-logic__2049: logic__2049
-reg__987: reg__987
-reg__796: reg__796
-case__149: case__149
-reg__88: reg__88
-logic__3746: logic__3746
-case__1128: case__1128
-reg__1486: reg__1144
-case__809: case__809
-reg__173: reg__173
-logic__3790: logic__3790
-logic__1405: logic__1405
-logic__8422: logic__8422
-logic__7424: logic__7424
-logic__338: logic__338
-logic__9549: logic__1791
-logic__3719: logic__3719
-logic__5314: logic__5314
-logic__272: logic__272
-logic__9396: logic__3025
-logic__9739: logic__6147
-Queue2_TLBundleA_a32d64s2k1z4u: Queue2_TLBundleA_a32d64s2k1z4u
-logic__2222: logic__2222
-bit_gen: bit_gen
-case__442: case__442
-logic__5553: logic__5553
-logic__4817: logic__4817
-logic__7743: logic__7743
-RoundAnyRawFNToRecFN__1: RoundAnyRawFNToRecFN
-logic__9412: logic__2994
-reg__1403: reg__1403
-logic__3163: logic__3163
-logic__5083: logic__5083
-case__1312: case__1312
-logic__5089: logic__5089
-logic__884: logic__884
-logic__7123: logic__7123
-logic__6326: logic__6326
-logic__7993: logic__7993
-logic__8851: logic__8851
-case__473: case__473
-case__909: case__909
-keep__75: keep
-case__112: case__112
-reg__293: reg__293
-logic__9380: logic__9380
-reg__929: reg__929
-logic__6842: logic__6842
-logic__6400: logic__6400
-datapath__431: datapath__431
-reg__672: reg__672
-logic__1928: logic__1928
-logic__892: logic__892
-logic__1578: logic__1578
-logic__3031: logic__3031
-keep__54: keep__6
-logic__6835: logic__6835
-datapath__506: datapath__506
-logic__4131: logic__4131
-reg__189: reg__189
-case__1220: case__1220
-case__1544: case__1544
-case__939: case__939
-case__1306: case__1306
-logic__3007: logic__3007
-logic__6633: logic__6633
-case__1332: case__1332
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__14: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6194: logic__6194
-reg__126: reg__126
-case__455: case__455
-case__1437: case__1437
-case__624: case__624
-reg__158: reg__158
-logic__1702: logic__1702
-logic__1759: logic__1759
-logic__9753: logic__515
-keep__15: keep__15
-reg__424: reg__424
-case__1013: case__1013
-logic__8162: logic__8162
-logic__4062: logic__4062
-logic__7830: logic__7830
-logic__6117: logic__6117
-logic__8169: logic__8169
-reg__1445: reg__1445
-case__1726: case__311
-case__1369: case__1369
-case__1694: case__464
-logic__2805: logic__2805
-logic__1294: logic__1294
-logic__5551: logic__5551
-logic__8273: logic__8273
-logic__3724: logic__3724
-case__1632: case__1632
-logic__2733: logic__2733
-logic__3381: logic__3381
-logic__2105: logic__2105
-datapath__591: datapath__591
-case__734: case__734
-case__1494: case__1494
-Repeater_TLBundleA_a32d64s2k1z3u: Repeater_TLBundleA_a32d64s2k1z3u
-reg__1103: reg__1103
-reg__1418: reg__1418
-reg__990: reg__990
-case__1023: case__1023
-reg__832: reg__832
-logic__4055: logic__4055
-logic__8440: logic__8440
-case__525: case__525
-reg__1462: reg__21
-reg__698: reg__698
-reg__811: reg__811
-logic__1683: logic__1683
-case__660: case__660
-case__105: case__105
-reg__542: reg__542
-logic__2728: logic__2728
-keep__53: keep__7
-datapath__483: datapath__483
-logic__5070: logic__5070
-logic__2836: logic__2836
-case__830: case__830
-case__54: case__54
-logic__2001: logic__2001
-extram__1: extram__1
-logic__1103: logic__1103
-reg__148: reg__148
-reg__119: reg__119
-reg__1146: reg__1146
-reg__777: reg__777
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__8: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__8689: logic__8689
-logic__5421: logic__5421
-logic__9395: logic__3028
-logic__4557: logic__4557
-datapath__250: datapath__250
-case__1229: case__1229
-logic__6850: logic__6850
-logic__2989: logic__2989
-datapath__51: datapath__51
-logic__2305: logic__2305
-logic__3277: logic__3277
-reg__1089: reg__1089
-logic__6740: logic__6740
-logic__3402: logic__3402
-reg__954: reg__954
-logic__6574: logic__6574
-logic__4054: logic__4054
-logic__8528: logic__8528
-reg__654: reg__654
-logic__6998: logic__6998
-case__820: case__820
-logic__1779: logic__1779
-logic__9517: logic__1884
-logic__1520: logic__1520
-logic__6098: logic__6098
-datapath__642: datapath__642
-case__918: case__918
-logic__1311: logic__1311
-ClockGroup: ClockGroup
-logic__2192: logic__2192
-datapath__706: datapath__706
-logic__1587: logic__1587
-datapath__745: datapath__361
-logic__9770: logic__475
-logic__2903: logic__2903
-logic__4774: logic__4774
-reg__1208: reg__1208
-logic__3874: logic__3874
-muxpart__320: muxpart__11
-logic__1477: logic__1477
-logic__6749: logic__6749
-case__1418: case__1418
-logic__6601: logic__6601
-reg__1394: reg__1394
-ITLB: ITLB
-datapath__59: datapath__59
-case__688: case__688
-logic__9525: logic__1860
-reg__8: reg__8
-AsyncValidSync__21: AsyncValidSync
-logic__5437: logic__5437
-logic__7715: logic__7715
-datapath__550: datapath__550
-logic__2409: logic__2409
-AsyncResetRegVec_w1_i0__2: AsyncResetRegVec_w1_i0
-reg__503: reg__503
-case__768: case__768
-datapath__679: datapath__679
-logic__674: logic__674
-datapath__622: datapath__622
-reg__196: reg__196
-case__350: case__350
-logic__6771: logic__6771
-logic__1096: logic__1096
-reg__1071: reg__1071
-logic__7740: logic__7740
-reg__1402: reg__1402
-logic__9702: logic__7702
-TLFpgaSPI: TLFpgaSPI
-logic__2009: logic__2009
-logic__6097: logic__6097
-logic__5416: logic__5416
-logic__257: logic__257
-logic__7436: logic__7436
-case__1065: case__1065
-case__1605: case__1605
-logic__9453: logic__3902
-logic__9556: logic__1764
-logic__9136: logic__9136
-cos2x: cos2x
-logic__6827: logic__6827
-logic__8220: logic__8220
-reg__444: reg__444
-logic__6484: logic__6484
-case__1667: case__1667
-muxpart__34: muxpart__34
-case__145: case__145
-logic__8198: logic__8198
-cordic_atan_one_stage__parameterized0__1: cordic_atan_one_stage__parameterized0
-logic__9719: logic__7586
-ram__10: ram__1
-reg__825: reg__825
-reg__362: reg__362
-case__1429: case__1429
-accum_dump: accum_dump
-case__387: case__387
-case__846: case__846
-logic__704: logic__704
-case__1646: case__1646
-case__795: case__795
-case__1282: case__1282
-logic__146: logic__146
-logic__9595: logic__1647
-logic__5334: logic__5334
-logic__6751: logic__6751
-logic__3232: logic__3232
-logic__6631: logic__6631
-muxpart__298: muxpart__298
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__10: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__735: datapath__735
-logic__7316: logic__7316
-case__940: case__940
-logic__7714: logic__7714
-AsyncResetSynchronizerShiftReg_w1_d3_i0__11: AsyncResetSynchronizerShiftReg_w1_d3_i0
-case__1696: case__461
-logic__3730: logic__3730
-logic__2231: logic__2231
-case__520: case__520
-reg__116: reg__116
-case__85: case__85
-logic__1179: logic__1179
-logic__201: logic__201
-reg__56: reg__56
-logic__673: logic__673
-case__1086: case__1086
-reg__217: reg__217
-reg__1320: reg__1320
-logic__2051: logic__2051
-datapath__758: datapath__242
-case__467: case__467
-logic__1168: logic__1168
-logic__9531: logic__1844
-logic__6051: logic__6051
-logic__5407: logic__5407
-logic__9794: logic__476
-logic__7033: logic__7033
-case__110: case__110
-logic__2115: logic__2115
-datapath__282: datapath__282
-case__622: case__622
-logic__9236: logic__9236
-case__860: case__860
-logic__8623: logic__8623
-reg__978: reg__978
-logic__2853: logic__2853
-reg__449: reg__449
-logic__4514: logic__4514
-datapath__157: datapath__157
-datapath__36: datapath__36
-logic__9193: logic__9193
-datapath__398: datapath__398
-logic__6195: logic__6195
-case__249: case__249
-logic__626: logic__626
-case__680: case__680
-case__14: case__14
-reg__1360: reg__1360
-logic__8344: logic__8344
-case__796: case__796
-case__1488: case__1488
-logic__9118: logic__9118
-datapath__341: datapath__341
-reg__70: reg__70
-logic__2729: logic__2729
-case__618: case__618
-logic__6826: logic__6826
-reg__769: reg__769
-logic__1006: logic__1006
-logic__595: logic__595
-datapath__615: datapath__615
-logic__789: logic__789
-reg__1348: reg__1348
-reg__772: reg__772
-reg__860: reg__860
-reg__198: reg__198
-logic__9440: logic__3940
-logic__7232: logic__7232
-case__692: case__692
-case__1470: case__1470
-logic__6200: logic__6200
-logic__721: logic__721
-logic__205: logic__205
-logic__3153: logic__3153
-logic__52: logic__52
-logic__1916: logic__1916
-logic__6112: logic__6112
-muxpart__299: muxpart__299
-reg__410: reg__410
-logic__9394: logic__3031
-datapath__583: datapath__583
-logic__9406: logic__3003
-muxpart__1: muxpart__1
-TLBusBypass: TLBusBypass
-reg__1092: reg__1092
-case__742: case__742
-logic__7417: logic__7417
-reg__1448: reg__1448
-reg__1080: reg__1080
-logic__17: logic__17
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__20: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__150: reg__150
-muxpart__40: muxpart__40
-case__359: case__359
-case__1534: case__1534
-logic__9790: logic__487
-logic__7379: logic__7379
-muxpart__31: muxpart__31
-reg__1371: reg__1371
-logic__5422: logic__5422
-logic__8853: logic__8853
-logic__3977: logic__3977
-logic__4096: logic__4096
-logic__319: logic__319
-reg__527: reg__527
-datapath__471: datapath__471
-reg__1653: reg__72
-logic__4886: logic__4886
-reg__252: reg__252
-logic__9515: logic__1891
-datapath__347: datapath__347
-ram_2x77: ram_2x77
-logic__250: logic__250
-case__1294: case__1294
-logic__5312: logic__5312
-logic__7588: logic__7588
-ClockCrossingReg_w15: ClockCrossingReg_w15
-reg__48: reg__48
-logic__4922: logic__4922
-case__1037: case__1037
-logic__1502: logic__1502
-reg__868: reg__868
-case__221: case__221
-reg__407: reg__407
-logic__8358: logic__8358
-logic__6103: logic__6103
-reg__1102: reg__1102
-case__619: case__619
-logic__6043: logic__6043
-reg__310: reg__310
-logic__7412: logic__7412
-reg__1245: reg__1245
-reg__47: reg__47
-reg__1382: reg__1382
-logic__3239: logic__3239
-logic__6494: logic__6494
-rocket_bscan_dmi_tunnel: rocket_bscan_dmi_tunnel
-case__414: case__414
-logic__1830: logic__1830
-datapath__234: datapath__234
-datapath__437: datapath__437
-case__1393: case__1393
-logic__5405: logic__5405
-logic__320: logic__320
-reg__724: reg__724
-reg__1144: reg__1144
-reg__550: reg__550
-reg__1654: reg__71
-logic__7632: logic__7632
-case__216: case__216
-reg__1416: reg__1416
-logic__8289: logic__8289
-logic__2651: logic__2651
-logic__6126: logic__6126
-logic__950: logic__950
-logic__8788: logic__8788
-logic__4587: logic__4587
-logic__1017: logic__1017
-datapath__589: datapath__589
-reg__1288: reg__1288
-datapath__635: datapath__635
-muxpart__102: muxpart__102
-reg__1458: reg__1458
-logic__7643: logic__7643
-logic__6212: logic__6212
-logic__2896: logic__2896
-datapath__539: datapath__539
-logic__9112: logic__9112
-logic__4035: logic__4035
-logic__3726: logic__3726
-reg__1477: reg__1254
-logic__8749: logic__8749
-reg__1044: reg__1044
-logic__6011: logic__6011
-reg__1574: reg__837
-logic__2667: logic__2667
-datapath__717: datapath__717
-logic__4935: logic__4935
-logic__5394: logic__5394
-reg__837: reg__837
-case__504: case__504
-datapath__34: datapath__34
-datapath__667: datapath__667
-logic__1523: logic__1523
-logic__6589: logic__6589
-reg__219: reg__219
-logic__2381: logic__2381
-logic__829: logic__829
-reg__1425: reg__1425
-logic__5078: logic__5078
-case__677: case__677
-logic__4293: logic__4293
-logic__7690: logic__7690
-logic__1278: logic__1278
-case__1674: case__1674
-case__665: case__665
-logic__6698: logic__6698
-logic__1486: logic__1486
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__24: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__2955: logic__2955
-reg__1596: reg__836
-case__1747: case__1056
-case__1149: case__1149
-logic__1445: logic__1445
-case__1774: case__106
-logic__3530: logic__3530
-reg__1519: reg__975
-logic__2677: logic__2677
-reg__1605: reg__836
-reg__62: reg__62
-logic__4181: logic__4181
-logic__2581: logic__2581
-logic__1045: logic__1045
-logic__5396: logic__5396
-reg__963: reg__963
-logic__7240: logic__7240
-case__1378: case__1378
-Queue1_TLBundleD_a29d32s7k1z2u: Queue1_TLBundleD_a29d32s7k1z2u
-logic__2734: logic__2734
-logic__5223: logic__5223
-case__380: case__380
-logic__9798: logic__282
-logic__5509: logic__5509
-logic__4231: logic__4231
-logic__9545: logic__1803
-reg__1115: reg__1115
-logic__5062: logic__5062
-datapath__553: datapath__553
-AsyncResetRegVec_w1_i0: AsyncResetRegVec_w1_i0
-reg__1074: reg__1074
-datapath__761: datapath__21
-logic__3087: logic__3087
-logic__6663: logic__6663
-logic__2994: logic__2994
-logic__4441: logic__4441
-case__352: case__352
-reg__1190: reg__1190
-datapath__724: datapath__724
-reg__1237: reg__1237
-keep__5: keep__5
-reg__1547: reg__837
-case__852: case__852
-datapath__276: datapath__276
-logic__6492: logic__6492
-logic__8402: logic__8402
-logic__5004: logic__5004
-logic__6765: logic__6765
-logic__3893: logic__3893
-case__1724: case__313
-reg__210: reg__210
-datapath__544: datapath__544
-logic__9665: logic__663
-counter__32: counter__32
-logic__4624: logic__4624
-logic__7151: logic__7151
-logic__9378: logic__9378
-logic__5073: logic__5073
-datapath__469: datapath__469
-reg__414: reg__414
-case__421: case__421
-logic__1851: logic__1851
-logic__6216: logic__6216
-logic__2195: logic__2195
-logic__3735: logic__3735
-logic__1612: logic__1612
-case__580: case__580
-case__956: case__956
-case__1176: case__1176
-case__840: case__840
-logic__7968: logic__7968
-case__1516: case__1516
-logic__9542: logic__1815
-logic__8747: logic__8747
-logic__6493: logic__6493
-datapath__494: datapath__494
-logic__2266: logic__2266
-AsyncValidSync__18: AsyncValidSync
-case__694: case__694
-logic__407: logic__407
-keep__64: keep__8
-reg__1475: reg__1256
-reg__1256: reg__1256
-datapath__334: datapath__334
-case__623: case__623
-logic__6038: logic__6038
-case__382: case__382
-reg__816: reg__816
-case__1465: case__1465
-case__1016: case__1016
-case__985: case__985
-logic__5510: logic__5510
-logic__1447: logic__1447
-logic__3291: logic__3291
-AsyncResetSynchronizerShiftReg_w1_d3_i0__12: AsyncResetSynchronizerShiftReg_w1_d3_i0
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__7: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__152: logic__152
-logic__9125: logic__9125
-logic__4923: logic__4923
-logic__95: logic__95
-reg__685: reg__685
-logic__6371: logic__6371
-logic__445: logic__445
-logic__7409: logic__7409
-datapath__154: datapath__154
-reg__642: reg__642
-logic__1061: logic__1061
-logic__7477: logic__7477
-reg__97: reg__97
-muxpart__191: muxpart__191
-TLFIFOFixer_2: TLFIFOFixer_2
-reg__638: reg__638
-case__250: case__250
-reg__168: reg__168
-datapath__577: datapath__577
-logic__4979: logic__4979
-logic__7573: logic__7573
-case__911: case__911
-reg__852: reg__852
-logic__7881: logic__7881
-logic__9178: logic__9178
-logic__9509: logic__1899
-reg__416: reg__416
-logic__8703: logic__8703
-logic__5914: logic__5914
-logic__8535: logic__8535
-case__802: case__802
-logic__1329: logic__1329
-logic__526: logic__526
-case__954: case__954
-logic__6843: logic__6843
-logic__6222: logic__6222
-logic__2877: logic__2877
-logic__8488: logic__8488
-reg__143: reg__143
-reg__128: reg__128
-reg__477: reg__477
-case__1402: case__1402
-case__427: case__427
-logic__5082: logic__5082
-reg__7: reg__7
-logic__9602: logic__1630
-logic__5328: logic__5328
-reg__1229: reg__1229
-logic__4164: logic__4164
-logic__252: logic__252
-logic__1596: logic__1596
-dsp48e1__32: dsp48e1__32
-case__1656: case__1656
-reg__1460: reg__22
-reg__281: reg__281
-logic__3182: logic__3182
-logic__7087: logic__7087
-case__1097: case__1097
-case__406: case__406
-Queue2_TLBundleA_a32d64s2k1z3u: Queue2_TLBundleA_a32d64s2k1z3u
-logic__4904: logic__4904
-case__224: case__224
-case__1681: case__1681
-reg__1406: reg__1406
-case__1286: case__1286
-muxpart__318: muxpart__318
-reg__595: reg__595
-case__1741: case__1411
-IntSyncSyncCrossingSink_n1x2: IntSyncSyncCrossingSink_n1x2
-logic__859: logic__859
-datapath__466: datapath__466
-case__1633: case__1633
-logic__3156: logic__3156
-case__316: case__316
-logic__5532: logic__5532
-reg__269: reg__269
-case__425: case__425
-datapath__737: datapath__737
-reg__1354: reg__1354
-cacode_gen_trck: cacode_gen_trck
-case__201: case__201
-logic__4531: logic__4531
-logic__6031: logic__6031
-case__987: case__987
-logic__8002: logic__8002
-logic__2876: logic__2876
-reg__29: reg__29
-case__1482: case__1482
-datapath__477: datapath__477
-logic__9587: logic__1663
-case__921: case__921
-reg__225: reg__225
-case__1537: case__1537
-logic__5175: logic__5175
-logic__2232: logic__2232
-logic__4327: logic__4327
-logic__5886: logic__5886
-logic__6489: logic__6489
-logic__1264: logic__1264
-counter__6: counter__6
-logic__1029: logic__1029
-logic__9376: logic__9376
-reg__1088: reg__1088
-logic__2933: logic__2933
-FPGAUARTClockSinkDomain: FPGAUARTClockSinkDomain
-datapath__35: datapath__35
-CompareRecFN: CompareRecFN
-logic__462: logic__462
-logic__7463: logic__7463
-reg__199: reg__199
-logic__4600: logic__4600
-TLXbar_pbus_out_i1_o4_a29d64s2k1z3u: TLXbar_pbus_out_i1_o4_a29d64s2k1z3u
-logic__6024: logic__6024
-reg__381: reg__381
-logic__1418: logic__1418
-case__79: case__79
-reg__894: reg__894
-reg__484: reg__484
-case__729: case__729
-case__697: case__697
-logic__7829: logic__7829
-gray_to_binary__2: gray_to_binary
-IntXbar_i3_o1: IntXbar_i3_o1
-reg__107: reg__107
-keep__31: keep__31
-logic__6107: logic__6107
-ram_2x78__1: ram_2x78
-reg__1390: reg__1390
-signinv__1: signinv__1
-reg__876: reg__876
-logic__1843: logic__1843
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__7: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__443: case__443
-logic__6834: logic__6834
-logic__194: logic__194
-datapath__614: datapath__614
-logic__4805: logic__4805
-logic__8163: logic__8163
-case__1649: case__1649
-logic__8335: logic__8335
-logic__1604: logic__1604
-case__1315: case__1315
-reg__1027: reg__1027
-logic__8748: logic__8748
-logic__1640: logic__1640
-logic__2249: logic__2249
-logic__4978: logic__4978
-datapath__241: datapath__241
-reg__1205: reg__1205
-logic__9603: logic__1629
-case__1629: case__1629
-AsyncValidSync__12: AsyncValidSync
-logic__3359: logic__3359
-reg__795: reg__795
-logic__8944: logic__8944
-reg__913: reg__913
-case__941: case__941
-case__776: case__776
-logic__8407: logic__8407
-reg__599: reg__599
-logic__6317: logic__6317
-datapath__69: datapath__69
-datapath__33: datapath__33
-logic__6930: logic__6930
-case__851: case__851
-reg__791: reg__791
-logic__1331: logic__1331
-reg__1298: reg__1298
-logic__8830: logic__8830
-logic__5390: logic__5390
-case__1613: case__1613
-reg__1163: reg__1163
-logic__4895: logic__4895
-logic__826: logic__826
-logic__2700: logic__2700
-logic__9716: logic__7663
-keep__48: keep__6
-logic__4246: logic__4246
-logic__5327: logic__5327
-logic__4162: logic__4162
-reg__1391: reg__1391
-reg__482: reg__482
-logic__3135: logic__3135
-logic__9503: logic__1917
-logic__6650: logic__6650
-datapath__487: datapath__487
-logic__888: logic__888
-logic__1033: logic__1033
-logic__6191: logic__6191
-logic__1238: logic__1238
-datapath__140: datapath__140
-case__440: case__440
-logic__5432: logic__5432
-reg__1607: reg__837
-case__955: case__955
-reg__533: reg__533
-logic__3084: logic__3084
-logic__321: logic__321
-logic__1420: logic__1420
-case__1309: case__1309
-datapath__593: datapath__593
-logic__8634: logic__8634
-case__908: case__908
-logic__4929: logic__4929
-case__772: case__772
-logic__2804: logic__2804
-reg__1012: reg__1012
-logic__6656: logic__6656
-reg__1420: reg__1420
-counter__20: counter__20
-logic__9654: logic__1520
-logic__2895: logic__2895
-logic__2867: logic__2867
-AsyncQueueSink_TLBundleD_a9d32s1k1z2u: AsyncQueueSink_TLBundleD_a9d32s1k1z2u
-logic__8341: logic__8341
-logic__2886: logic__2886
-logic__9598: logic__1640
-datapath__451: datapath__451
-reg__1327: reg__1327
-logic__5017: logic__5017
-logic__6823: logic__6823
-case__560: case__560
-reg__680: reg__680
-logic__69: logic__69
-logic__9502: logic__1921
-logic__4851: logic__4851
-logic__2194: logic__2194
-reg__161: reg__161
-case__197: case__197
-reg__580: reg__580
-reg__1565: reg__837
-logic__6012: logic__6012
-datapath__284: datapath__284
-logic__6129: logic__6129
-TLBuffer_a32d64s2k1z3u: TLBuffer_a32d64s2k1z3u
-logic__3175: logic__3175
-datapath__554: datapath__554
-reg__908: reg__908
-case__1138: case__1138
-keep__35: keep__35
-reg__2: reg__2
-case__922: case__922
-logic__4807: logic__4807
-logic__547: logic__547
-logic__5295: logic__5295
-logic__6947: logic__6947
-reg__480: reg__480
-reg__118: reg__118
-logic__3727: logic__3727
-logic__430: logic__430
-TLAsyncCrossingSource_a9d32s1k1z2u: TLAsyncCrossingSource_a9d32s1k1z2u
-reg__911: reg__911
-case__260: case__260
-logic__6070: logic__6070
-case__755: case__755
-logic__2473: logic__2473
-reg__1176: reg__1176
-datapath__28: datapath__28
-logic__2069: logic__2069
-logic__6193: logic__6193
-logic__6832: logic__6832
-logic__6227: logic__6227
-double_ff_syn__1: double_ff_syn
-case__750: case__750
-reg__1048: reg__1048
-logic__9122: logic__9122
-logic__3595: logic__3595
-case__349: case__349
-logic__7500: logic__7500
-TLInterconnectCoupler_cbus_to_plic: TLInterconnectCoupler_cbus_to_plic
-reg__1428: reg__1428
-logic__2480: logic__2480
-logic__2701: logic__2701
-case__1021: case__1021
-logic__6829: logic__6829
-logic__1274: logic__1274
-logic__9161: logic__9161
-logic__4773: logic__4773
-logic__3694: logic__3694
-logic__2910: logic__2910
-reg__1270: reg__1270
-case__1382: case__1382
-datapath__682: datapath__682
-datapath__270: datapath__270
-case__513: case__513
-reg__997: reg__997
-logic__5938: logic__5938
-datapath__46: datapath__46
-logic__2072: logic__2072
-logic__6886: logic__6886
-logic__3270: logic__3270
-reg__1447: reg__1447
-reg__497: reg__497
-reg__540: reg__540
-TLBuffer_a29d64s2k1z3u__1: TLBuffer_a29d64s2k1z3u
-logic__6015: logic__6015
-datapath__415: datapath__415
-logic__7884: logic__7884
-reg__859: reg__859
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__3: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-Queue2_TLBundleA_a29d64s2k1z3u: Queue2_TLBundleA_a29d64s2k1z3u
-logic__1262: logic__1262
-logic__9792: logic__483
-logic__9757: logic__502
-reg__1370: reg__1370
-case__1041: case__1041
-reg__316: reg__316
-reg__140: reg__140
-case__627: case__627
-logic__7174: logic__7174
-reg__4: reg__4
-reg__46: reg__46
-AsyncResetSynchronizerShiftReg_w1_d3_i0__2: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__8652: logic__8652
-logic__2736: logic__2736
-case__810: case__810
-logic__6021: logic__6021
-case__1474: case__1474
-logic__8149: logic__8149
-reg__1158: reg__1158
-datapath__617: datapath__617
-case__749: case__749
-logic__9725: logic__6147
-logic__3757: logic__3757
-case__33: case__33
-case__801: case__801
-logic__9585: logic__1671
-reg__428: reg__428
-logic__5731: logic__5731
-case__4: case__4
-logic__4321: logic__4321
-logic__9379: logic__9379
-logic__7606: logic__7606
-logic__6290: logic__6290
-reg__742: reg__742
-reg__1025: reg__1025
-reg__1440: reg__1440
-case__6: case__6
-reg__139: reg__139
-logic__2932: logic__2932
-logic__3901: logic__3901
-reg__1469: reg__120
-case__1380: case__1380
-reg__645: reg__645
-Queue2_TLBundleA_a14d64s2k1z4u: Queue2_TLBundleA_a14d64s2k1z4u
-datapath__500: datapath__500
-datapath__457: datapath__457
-case__283: case__283
-logic__9103: logic__9103
-butterfly__parameterized0: butterfly__parameterized0
-reg__201: reg__201
-case__345: case__345
-logic__5665: logic__5665
-logic__5457: logic__5457
-logic__1391: logic__1391
-datapath__445: datapath__445
-logic__9652: logic__1522
-case__447: case__447
-reg__464: reg__464
-logic__2663: logic__2663
-ClockCrossingReg_w43: ClockCrossingReg_w43
-reg__1016: reg__1016
-logic__7447: logic__7447
-logic__6748: logic__6748
-case__163: case__163
-datapath__66: datapath__66
-logic__528: logic__528
-counter__39: counter__39
-case__348: case__348
-logic__1848: logic__1848
-logic__4299: logic__4299
-logic__4206: logic__4206
-logic__9285: logic__9285
-logic__2691: logic__2691
-reg__922: reg__922
-logic__1434: logic__1434
-case__1298: case__1298
-case__165: case__165
-logic__6756: logic__6756
-datapath__115: datapath__115
-DCache: DCache
-case__736: case__736
-reg__774: reg__774
-muxpart__14: muxpart__14
-logic__6384: logic__6384
-case__689: case__689
-reg__255: reg__255
-datapath__254: datapath__254
-logic__4827: logic__4827
-reg__1140: reg__1140
-logic__598: logic__598
-logic__2124: logic__2124
-logic__3731: logic__3731
-case__1180: case__1180
-logic__5533: logic__5533
-case__581: case__581
-logic__9610: logic__1612
-logic__4161: logic__4161
-datapath__455: datapath__455
-reg__792: reg__792
-Queue1_RegMapperInput_i23_m8: Queue1_RegMapperInput_i23_m8
-datapath__741: datapath__301
-case__858: case__858
-logic__1148: logic__1148
-case__1068: case__1068
-reg__1467: reg__36
-case__901: case__901
-logic__7642: logic__7642
-case__996: case__996
-datapath__486: datapath__486
-datapath__462: datapath__462
-logic__2212: logic__2212
-reg__288: reg__288
-case__451: case__451
-TLDebugModuleInnerAsync: TLDebugModuleInnerAsync
-reg__165: reg__165
-rom__7: rom__7
-reg__85: reg__85
-logic__1890: logic__1890
-logic__8832: logic__8832
-reg__675: reg__675
-logic__9158: logic__9158
-reg__529: reg__529
-logic__2478: logic__2478
-logic__3677: logic__3677
-case__1770: case__110
-case__1170: case__1170
-datapath__118: datapath__118
-logic__9619: logic__1593
-case__1370: case__1370
-datapath__86: datapath__86
-TLInterconnectCoupler_sbus_to_bus_named_cbus: TLInterconnectCoupler_sbus_to_bus_named_cbus
-keep__10: keep__10
-case__334: case__334
-logic__8653: logic__8653
-logic__1143: logic__1143
-rom__6: rom__6
-logic__1208: logic__1208
-dsp48e1__10: dsp48e1__10
-case__461: case__461
-logic__7650: logic__7650
-reg__212: reg__212
-logic__4148: logic__4148
-logic__408: logic__408
-logic__2419: logic__2419
-logic__4471: logic__4471
-logic__9523: logic__1866
-logic__4245: logic__4245
-logic__2835: logic__2835
-logic__2004: logic__2004
-logic__6758: logic__6758
-logic__7729: logic__7729
-case__1746: case__1057
-reg__1576: reg__838
-logic__650: logic__650
-reg__332: reg__332
-logic__4614: logic__4614
-logic__8704: logic__8704
-reg__610: reg__610
-LevelGateway__4: LevelGateway
-logic__2214: logic__2214
-logic__8936: logic__8936
-reg__696: reg__696
-MulAddRecFNPipe_l2_e8_s24: MulAddRecFNPipe_l2_e8_s24
-case__274: case__274
-logic__4175: logic__4175
-logic__5550: logic__5550
-logic__9174: logic__9174
-case__790: case__790
-TLXbar_pbus_in_i1_o1_a29d64s2k1z3u: TLXbar_pbus_in_i1_o1_a29d64s2k1z3u
-logic__8596: logic__8596
-logic__9177: logic__9177
-sync__3: sync
-logic__7437: logic__7437
-case__42: case__42
-datapath__109: datapath__109
-datapath__133: datapath__133
-reg__1202: reg__1202
-reg__1421: reg__1421
-logic__8908: logic__8908
-Queue2_TLBundleD_a32d64s2k1z4u__1: Queue2_TLBundleD_a32d64s2k1z4u
-case__1775: case__105
-case__1027: case__1027
-reg__1415: reg__1415
-logic__4876: logic__4876
-reg__512: reg__512
-reg__800: reg__800
-case__1025: case__1025
-sync__1: sync
-logic__9410: logic__2996
-logic__8758: logic__8758
-reg__1312: reg__1312
-logic__2693: logic__2693
-reg__451: reg__451
-logic__7360: logic__7360
-logic__261: logic__261
-logic__3872: logic__3872
-logic__3709: logic__3709
-reg__1644: reg__70
-case__48: case__48
-logic__2992: logic__2992
-logic__9179: logic__9179
-datapath__294: datapath__294
-case__409: case__409
-case__897: case__897
-reg__278: reg__278
-reg__587: reg__587
-logic__6924: logic__6924
-logic__627: logic__627
-reg__25: reg__25
-case__344: case__344
-logic__9456: logic__3899
-datapath__770: datapath__112
-logic__3514: logic__3514
-logic__1614: logic__1614
-logic__2545: logic__2545
-datapath__376: datapath__376
-logic__2250: logic__2250
-logic__7800: logic__7800
-logic__3079: logic__3079
-case__261: case__261
-logic__690: logic__690
-datapath__807: datapath__14
-logic__9510: logic__1896
-logic__9678: logic__8469
-counter__9: counter__9
-case__1608: case__1608
-case__592: case__592
-logic__8298: logic__8298
-logic__5998: logic__5998
-logic__9339: logic__9339
-case__1548: case__1548
-logic__6554: logic__6554
-logic__9448: logic__3932
-reg__393: reg__393
-logic__3734: logic__3734
-logic__5876: logic__5876
-logic__7258: logic__7258
-datapath__474: datapath__474
-logic__2253: logic__2253
-reg__10: reg__10
-IntSyncCrossingSource_n1x2: IntSyncCrossingSource_n1x2
-datapath__56: datapath__56
-reg__1631: reg__784
-muxpart__307: muxpart__307
-keep__58: keep__8
-logic__6547: logic__6547
-case__938: case__938
-logic__3129: logic__3129
-case__1658: case__1658
-case__1761: case__108
-logic__4908: logic__4908
-datapath__162: datapath__162
-logic__5484: logic__5484
-reg__487: reg__487
-case__1333: case__1333
-logic__5418: logic__5418
-reg__827: reg__827
-case__887: case__887
-datapath__472: datapath__472
-logic__599: logic__599
-reg__814: reg__814
-case__543: case__543
-logic__6454: logic__6454
-datapath__64: datapath__64
-case__1552: case__1552
-datapath__166: datapath__166
-keep__39: keep__39
-logic__1258: logic__1258
-logic__2148: logic__2148
-reg__649: reg__649
-logic__5429: logic__5429
-case__678: case__678
-reg__1287: reg__1287
-logic__9425: logic__3977
-datapath__316: datapath__316
-reg__806: reg__806
-reg__141: reg__141
-logic__1531: logic__1531
-logic__4482: logic__4482
-muxpart__13: muxpart__13
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__29: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__515: case__515
-reg__763: reg__763
-logic__322: logic__322
-logic__7414: logic__7414
-logic__1222: logic__1222
-logic__5321: logic__5321
-TLInterconnectCoupler_pbus_to_fpga_uart__1: TLInterconnectCoupler_pbus_to_fpga_uart
-logic__6706: logic__6706
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__1365: case__1365
-reg__457: reg__457
-case__1753: case__1049
-reg__760: reg__760
-muxpart__321: muxpart__10
-logic__7343: logic__7343
-datapath__403: datapath__403
-reg__1398: reg__1398
-datapath__400: datapath__400
-logic__6793: logic__6793
-reg__762: reg__762
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__8: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__8005: logic__8005
-logic__6037: logic__6037
-logic__6847: logic__6847
-logic__7042: logic__7042
-datapath__98: datapath__98
-case__44: case__44
-case__1514: case__1514
-case__549: case__549
-datapath__802: datapath__19
-logic__7713: logic__7713
-case__636: case__636
-logic__5919: logic__5919
-case__593: case__593
-reg__579: reg__579
-muxpart__27: muxpart__27
-logic__1210: logic__1210
-logic__1065: logic__1065
-logic__9579: logic__1691
-logic__2931: logic__2931
-logic__605: logic__605
-case__310: case__310
-logic__697: logic__697
-reg__739: reg__739
-logic__9534: logic__1839
-reg__73: reg__73
-logic__5454: logic__5454
-keep__66: keep__6
-Queue2_TLBundleA_a32d64s1k1z4u__1: Queue2_TLBundleA_a32d64s1k1z4u
-logic__5993: logic__5993
-case__1669: case__1669
-logic__9605: logic__1623
-logic__6452: logic__6452
-logic__9301: logic__9301
-logic__9273: logic__9273
-AsyncValidSync__2: AsyncValidSync
-logic__2899: logic__2899
-case__1519: case__1519
-case__322: case__322
-logic__5923: logic__5923
-logic__7322: logic__7322
-logic__1032: logic__1032
-logic__9340: logic__9340
-logic__1265: logic__1265
-logic__631: logic__631
-logic__2579: logic__2579
-logic__5388: logic__5388
-logic__1367: logic__1367
-datapath__290: datapath__290
-logic__1399: logic__1399
-logic__9769: logic__476
-logic__3090: logic__3090
-case__273: case__273
-logic__3294: logic__3294
-reg__1252: reg__1252
-logic__1092: logic__1092
-reg__1061: reg__1061
-logic__7207: logic__7207
-reg__181: reg__181
-ClockGroup__3: ClockGroup
-logic__1763: logic__1763
-case__767: case__767
-reg__187: reg__187
-datapath__209: datapath__209
-case__679: case__679
-logic__6223: logic__6223
-datapath__227: datapath__227
-PTW: PTW
-logic__4028: logic__4028
-reg__979: reg__979
-logic__894: logic__894
-muxpart__83: muxpart__83
-reg__459: reg__459
-case__869: case__869
-TLBuffer_a32d64s2k1z4u_1: TLBuffer_a32d64s2k1z4u_1
-logic__9417: logic__2989
-logic__493: logic__493
-reg__1649: reg__65
-logic__5318: logic__5318
-logic__9355: logic__9355
-case__1284: case__1284
-rom__1: rom__1
-logic__5333: logic__5333
-datapath__57: datapath__57
-reg__1162: reg__1162
-reg__848: reg__848
-case__1559: case__1559
-reg__470: reg__470
-case__7: case__7
-case__1127: case__1127
-logic__440: logic__440
-logic__4899: logic__4899
-reg__279: reg__279
-case__1538: case__1538
-datapath__434: datapath__434
-case__464: case__464
-logic__808: logic__808
-logic__749: logic__749
-logic__123: logic__123
-reg__1003: reg__1003
-logic__2935: logic__2935
-reg__686: reg__686
-reg__496: reg__496
-logic__8153: logic__8153
-logic__1739: logic__1739
-cdc_fifo_gray: cdc_fifo_gray
-datapath__125: datapath__125
-case__59: case__59
-reg__942: reg__942
-case__1557: case__1557
-keep__65: keep__7
-logic__6132: logic__6132
-muxpart__35: muxpart__35
-case__613: case__613
-datapath__460: datapath__460
-case__1485: case__1485
-reg__1135: reg__1135
-logic__1214: logic__1214
-logic__1196: logic__1196
-reg__368: reg__368
-logic__182: logic__182
-reg__1357: reg__1357
-logic__38: logic__38
-logic__813: logic__813
-logic__3733: logic__3733
-reg__147: reg__147
-logic__271: logic__271
-logic__6016: logic__6016
-logic__309: logic__309
-logic__3274: logic__3274
-reg__949: reg__949
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__23: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-rom__4: rom__4
-logic__3887: logic__3887
-reg__1627: reg__22
-logic__130: logic__130
-logic__7935: logic__7935
-datapath__145: datapath__145
-datapath__392: datapath__392
-logic__6197: logic__6197
-datapath__219: datapath__219
-datapath__283: datapath__283
-logic__8909: logic__8909
-datapath__538: datapath__538
-logic__9183: logic__9183
-case__1625: case__1625
-case__343: case__343
-case__533: case__533
-logic__3681: logic__3681
-logic__2: logic__2
-reg__994: reg__994
-logic__9343: logic__9343
-logic__1724: logic__1724
-case__1685: case__1685
-logic__9698: logic__7586
-logic__6311: logic__6311
-logic__3902: logic__3902
-logic__2441: logic__2441
-logic__4439: logic__4439
-muxpart__4: muxpart__4
-muxpart__3: muxpart__3
-logic__4874: logic__4874
-datapath__766: datapath__116
-logic__1776: logic__1776
-logic__6410: logic__6410
-logic__1662: logic__1662
-logic__4980: logic__4980
-case__1000: case__1000
-logic__8541: logic__8541
-logic__6527: logic__6527
-logic__1691: logic__1691
-logic__9495: logic__1936
-case__907: case__907
-logic__253: logic__253
-logic__4683: logic__4683
-counter__22: counter__22
-logic__3559: logic__3559
-case__972: case__972
-counter__2: counter__2
-logic__9156: logic__9156
-logic__2230: logic__2230
-case__739: case__739
-reg__1601: reg__837
-logic__3266: logic__3266
-TLFragmenter_bootrom: TLFragmenter_bootrom
-reg__916: reg__916
-case__748: case__748
-logic__1593: logic__1593
-reg__1407: reg__1407
-logic__5403: logic__5403
-reg__1164: reg__1164
-case__1135: case__1135
-case__1004: case__1004
-logic__9597: logic__1641
-logic__5332: logic__5332
-muxpart__66: muxpart__66
-logic__5941: logic__5941
-datapath__650: datapath__650
-logic__7422: logic__7422
-reg__1543: reg__838
-case__836: case__836
-logic__6312: logic__6312
-datapath__775: datapath__653
-logic__2087: logic__2087
-case__717: case__717
-logic__4646: logic__4646
-datapath__484: datapath__484
-datapath__792: datapath__98
-reg__186: reg__186
-case__664: case__664
-case__1447: case__1447
-AsyncValidSync__3: AsyncValidSync
-logic__710: logic__710
-logic__186: logic__186
-reg__438: reg__438
-logic__7237: logic__7237
-AsyncResetRegVec_w2_i0: AsyncResetRegVec_w2_i0
-datapath__17: datapath__17
-logic__2204: logic__2204
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__6: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__1993: logic__1993
-case__66: case__66
-logic__134: logic__134
-case__1231: case__1231
-case__571: case__571
-TLError_1: TLError_1
-case__266: case__266
-logic__1097: logic__1097
-logic__5713: logic__5713
-muxpart__38: muxpart__38
-reg__1636: reg__784
-logic__1400: logic__1400
-logic__2954: logic__2954
-logic__7405: logic__7405
-logic__8691: logic__8691
-keep__55: keep__8
-reg__110: reg__110
-logic__5489: logic__5489
-logic__6211: logic__6211
-ClockSinkDomain: ClockSinkDomain
-case__1546: case__1546
-datapath__723: datapath__723
-logic__4032: logic__4032
-case__403: case__403
-case__472: case__472
-logic__2485: logic__2485
-case__1400: case__1400
-logic__2712: logic__2712
-reg__1660: reg__65
-datapath__221: datapath__221
-logic__8081: logic__8081
-reg__752: reg__752
-logic__7671: logic__7671
-logic__4438: logic__4438
-muxpart__44: muxpart__44
-datapath__186: datapath__186
-logic__2050: logic__2050
-logic__4613: logic__4613
-reg__379: reg__379
-logic__8775: logic__8775
-logic__4566: logic__4566
-reg__1568: reg__837
-case__244: case__244
-keep__11: keep__11
-datapath__709: datapath__709
-case__185: case__185
-reg__203: reg__203
-logic__4854: logic__4854
-fft_radix_2: fft_radix_2
-case__417: case__417
-case__307: case__307
-reg__947: reg__947
-reg__1331: reg__1331
-logic__2934: logic__2934
-reg__295: reg__295
-case__17: case__17
-logic__7118: logic__7118
-logic__2043: logic__2043
-reg__1255: reg__1255
-case__1628: case__1628
-logic__9552: logic__1782
-case: case
-case__81: case__81
-reg__1269: reg__1269
-case__490: case__490
-logic__6766: logic__6766
-logic__7880: logic__7880
-case__43: case__43
-logic__7427: logic__7427
-logic__9642: logic__1540
-logic__8949: logic__8949
-reg__1465: reg__38
-logic__3260: logic__3260
-logic__2846: logic__2846
-reg__1129: reg__1129
-logic__3972: logic__3972
-logic__9551: logic__1783
-logic__2233: logic__2233
-logic__6306: logic__6306
-case__1776: case__104
-logic__452: logic__452
-logic__4202: logic__4202
-case__1648: case__1648
-logic__5310: logic__5310
-logic__1594: logic__1594
-reg__923: reg__923
-case__67: case__67
-reg__971: reg__971
-logic__1164: logic__1164
-logic__239: logic__239
-case__1103: case__1103
-logic__6431: logic__6431
-datapath__391: datapath__391
-logic__3078: logic__3078
-case__1048: case__1048
-logic__207: logic__207
-logic__5460: logic__5460
-logic__8847: logic__8847
-logic__461: logic__461
-case__951: case__951
-logic__856: logic__856
-logic__9123: logic__9123
-reg__1551: reg__836
-reg__64: reg__64
-reg__111: reg__111
-datapath__646: datapath__646
-logic__6986: logic__6986
-reg__452: reg__452
-logic__1661: logic__1661
-case__889: case__889
-logic__1894: logic__1894
-logic__6459: logic__6459
-logic__267: logic__267
-case__1509: case__1509
-case__1638: case__1638
-reg__1222: reg__1222
-logic__4983: logic__4983
-logic__6124: logic__6124
-logic__2276: logic__2276
-logic__8359: logic__8359
-datapath__169: datapath__169
-logic__1799: logic__1799
-addsub__2: addsub__2
-logic__2169: logic__2169
-logic__7139: logic__7139
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__15: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__6174: logic__6174
-logic__390: logic__390
-reg__1464: reg__19
-logic__9677: logic__8472
-logic__1926: logic__1926
-reset_synch: reset_synch
-logic__9532: logic__1843
-logic__2851: logic__2851
-logic__8626: logic__8626
-reg__934: reg__934
-reg__355: reg__355
-logic__882: logic__882
-logic__8072: logic__8072
-muxpart__87: muxpart__87
-logic__6041: logic__6041
-case__1477: case__1477
-logic__6314: logic__6314
-reg__1063: reg__1063
-logic__3855: logic__3855
-muxpart__192: muxpart__192
-keep__77: keep
-reg__16: reg__16
-reg__705: reg__705
-logic__6368: logic__6368
-reg__1439: reg__1439
-case__1484: case__1484
-logic__9470: logic__1892
-logic__9660: logic__276
-logic__3022: logic__3022
-muxpart__105: muxpart__105
-reg__729: reg__729
-logic__2411: logic__2411
-reg__1347: reg__1347
-reg__701: reg__701
-logic__6746: logic__6746
-logic__6019: logic__6019
-case__53: case__53
-logic__9124: logic__9124
-logic__4754: logic__4754
-logic__5504: logic__5504
-reg__515: reg__515
-logic__1909: logic__1909
-case__39: case__39
-logic__6415: logic__6415
-logic__6199: logic__6199
-logic__1072: logic__1072
-muxpart__36: muxpart__36
-logic__6648: logic__6648
-ram_2x77__3: ram_2x77
-reg__704: reg__704
-logic__1762: logic__1762
-logic__9758: logic__498
-case__1555: case__1555
-logic__5926: logic__5926
-datapath__668: datapath__668
-logic__5081: logic__5081
-logic__8854: logic__8854
-reg__782: reg__782
-case__61: case__61
-logic__4097: logic__4097
-case__157: case__157
-datapath__273: datapath__273
-logic__2735: logic__2735
-logic__6540: logic__6540
-logic__6022: logic__6022
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__9: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__306: logic__306
-logic__771: logic__771
-IntSyncCrossingSource_n1x1: IntSyncCrossingSource_n1x1
-logic__6036: logic__6036
-datapath__410: datapath__410
-muxpart__79: muxpart__79
-reg__467: reg__467
-logic__6366: logic__6366
-reg__787: reg__787
-case__144: case__144
-datapath__599: datapath__599
-reg__1277: reg__1277
-reg__1282: reg__1282
-reg__977: reg__977
-logic__6257: logic__6257
-logic__9640: logic__1542
-logic__2810: logic__2810
-logic__7662: logic__7662
-logic__9138: logic__9138
-case__423: case__423
-case__398: case__398
-muxpart__230: muxpart__230
-logic__2906: logic__2906
-logic__2197: logic__2197
-logic__5123: logic__5123
-logic__5881: logic__5881
-logic__2826: logic__2826
-logic__6233: logic__6233
-logic__2449: logic__2449
-reg__790: reg__790
-reg__120: reg__120
-case__1438: case__1438
-logic__8197: logic__8197
-logic__1424: logic__1424
-TLFragmenter_1: TLFragmenter_1
-logic__9682: logic__8272
-logic__6608: logic__6608
-logic__4529: logic__4529
-logic__1490: logic__1490
-case__335: case__335
-logic__4670: logic__4670
-logic__5235: logic__5235
-logic__47: logic__47
-case__1166: case__1166
-logic__9527: logic__1854
-muxpart__89: muxpart__89
-reg__350: reg__350
-logic__4260: logic__4260
-logic__242: logic__242
-MulAddRecFNToRaw_postMul_1: MulAddRecFNToRaw_postMul_1
-logic__7410: logic__7410
-muxpart__207: muxpart__207
-logic__8635: logic__8635
-datapath__21: datapath__21
-logic__9668: logic__658
-case__1431: case__1431
-logic__1731: logic__1731
-logic__9196: logic__9196
-logic__8533: logic__8533
-logic__6167: logic__6167
-reg__1015: reg__1015
-reg__624: reg__624
-logic__2659: logic__2659
-logic__9563: logic__1743
-logic__6801: logic__6801
-reg__549: reg__549
-reg__1573: reg__838
-datapath__528: datapath__528
-TLBusBypassBar: TLBusBypassBar
-logic__9522: logic__1869
-reg__678: reg__678
-logic__7560: logic__7560
-logic__7061: logic__7061
-reg__1177: reg__1177
-muxpart__25: muxpart__25
-case__438: case__438
-datapath__111: datapath__111
-reg__1304: reg__1304
-logic__1355: logic__1355
-reg__541: reg__541
-logic__7168: logic__7168
-case__126: case__126
-logic__895: logic__895
-logic__9140: logic__9140
-reg__856: reg__856
-datapath__592: datapath__592
-case__1374: case__1374
-case__1238: case__1238
-logic__5288: logic__5288
-datapath__306: datapath__306
-case__372: case__372
-case__1619: case__1619
-logic__4045: logic__4045
-case__914: case__914
-datapath__74: datapath__74
-reg__409: reg__409
-reg__1630: reg__784
-sample_counter: sample_counter
-PLICClockSinkDomain: PLICClockSinkDomain
-logic__9569: logic__1723
-case__22: case__22
-datapath__762: datapath__20
-logic__3265: logic__3265
-reg__324: reg__324
-logic__5885: logic__5885
-case__1468: case__1468
-logic__724: logic__724
-logic__6127: logic__6127
-datapath__580: datapath__580
-logic__5535: logic__5535
-logic__4144: logic__4144
-logic__8078: logic__8078
-reg__455: reg__455
-case__1732: case__1420
-datapath__768: datapath__114
-datapath__559: datapath__559
-logic__5372: logic__5372
-logic__4595: logic__4595
-logic__8814: logic__8814
-case__848: case__848
-logic__6183: logic__6183
-logic__9664: logic__664
-reg__1315: reg__1315
-logic__3850: logic__3850
-logic__6128: logic__6128
-case__393: case__393
-case__741: case__741
-logic__6985: logic__6985
-logic__4199: logic__4199
-logic__9435: logic__3952
-reg__170: reg__170
-reg__1093: reg__1093
-logic__5277: logic__5277
-logic__6029: logic__6029
-logic__6430: logic__6430
-logic__929: logic__929
-case__410: case__410
-case__754: case__754
-logic__8476: logic__8476
-logic__4741: logic__4741
-logic__6925: logic__6925
-reg__915: reg__915
-logic__3956: logic__3956
-logic__4599: logic__4599
-case__1532: case__1532
-case__572: case__572
-case__269: case__269
-logic__9130: logic__9130
-keep__34: keep__34
-case__315: case__315
-logic__9766: logic__484
-logic__5084: logic__5084
-reg__626: reg__626
-logic__3867: logic__3867
-logic__3505: logic__3505
-datapath__631: datapath__631
-logic__6670: logic__6670
-case__181: case__181
-datapath__120: datapath__120
-reg__1147: reg__1147
-case__787: case__787
-case__1442: case__1442
-logic__7084: logic__7084
-logic__6641: logic__6641
-reg__43: reg__43
-logic__2360: logic__2360
-keep__6: keep__6
-case__1744: case__1408
-case__365: case__365
-logic__7888: logic__7888
-logic__3931: logic__3931
-reg__177: reg__177
-logic__1577: logic__1577
-logic__7411: logic__7411
-logic__8940: logic__8940
-datapath__124: datapath__124
-reg__1488: reg__1144
-cordic_atan_one_stage: cordic_atan_one_stage
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__17: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__891: case__891
-reg__14: reg__14
-reg__980: reg__980
-logic__9297: logic__9297
-logic__9473: logic__1884
-logic__6681: logic__6681
-logic__686: logic__686
-reg__1062: reg__1062
-datapath__281: datapath__281
-datapath__763: datapath__19
-logic__2624: logic__2624
-datapath__350: datapath__350
-case__640: case__640
-logic__6997: logic__6997
-logic__5955: logic__5955
-logic__7664: logic__7664
-logic__533: logic__533
-logic__5458: logic__5458
-logic__6898: logic__6898
-case__347: case__347
-logic__9673: logic__8478
-logic__9289: logic__9289
-logic__1842: logic__1842
-case__563: case__563
-logic__7587: logic__7587
-logic__4232: logic__4232
-datapath__249: datapath__249
-reg__1642: reg__72
-logic__5284: logic__5284
-logic__9469: logic__1893
-logic__9717: logic__7662
-datapath__569: datapath__569
-ClockGroup__1: ClockGroup
-logic__6671: logic__6671
-logic__6125: logic__6125
-logic__7787: logic__7787
-reg__646: reg__646
-case__449: case__449
-datapath__674: datapath__674
-logic__2167: logic__2167
-logic__1335: logic__1335
-muxpart__309: muxpart__309
-reg__957: reg__957
-logic__9443: logic__3937
-logic__6780: logic__6780
-ResetCatchAndSync_d3__1: ResetCatchAndSync_d3
-logic__9152: logic__9152
-reg__483: reg__483
-RecFNToIN_1: RecFNToIN_1
-reg__100: reg__100
-case__487: case__487
-logic__5910: logic__5910
-logic__3358: logic__3358
-case__1471: case__1471
-case__686: case__686
-datapath__417: datapath__417
-datapath__565: datapath__565
-logic__8427: logic__8427
-logic__6305: logic__6305
-logic__5428: logic__5428
-logic__2990: logic__2990
-logic__22: logic__22
-reg__901: reg__901
-logic__725: logic__725
-logic__6784: logic__6784
-case__401: case__401
-logic__3682: logic__3682
-case__1462: case__1462
-datapath__738: datapath__738
-logic__4758: logic__4758
-logic__7226: logic__7226
-logic__2842: logic__2842
-case__1620: case__1620
-logic__3642: logic__3642
-datapath__764: datapath__18
-logic__2248: logic__2248
-case__254: case__254
-datapath__65: datapath__65
-FPU__GB0: FPU__GB0
-case__251: case__251
-case__942: case__942
-logic__6176: logic__6176
-logic__6202: logic__6202
-logic__4906: logic__4906
-logic__7613: logic__7613
-muxpart__52: muxpart__52
-case__444: case__444
-logic__9411: logic__2995
-logic__9494: logic__1939
-reg__1059: reg__1059
-logic__2094: logic__2094
-case__539: case__539
-logic__9804: logic__271
-datapath__570: datapath__570
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__3: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__5344: logic__5344
-logic__6446: logic__6446
-datapath__152: datapath__152
-logic__371: logic__371
-logic__1273: logic__1273
-logic__5728: logic__5728
-reg__1560: reg__836
-logic__1380: logic__1380
-reg__582: reg__582
-case__609: case__609
-logic__914: logic__914
-reg__132: reg__132
-muxpart__23: muxpart__23
-datapath__106: datapath__106
-case__1560: case__1560
-sample_align: sample_align
-logic__4364: logic__4364
-datapath__197: datapath__197
-extrom__1: extrom__1
-logic__9426: logic__3973
-case__733: case__733
-logic__8319: logic__8319
-keep__59: keep__7
-logic__6189: logic__6189
-case__1202: case__1202
-case__1551: case__1551
-logic__4932: logic__4932
-reg__465: reg__465
-logic__3638: logic__3638
-logic__8292: logic__8292
-logic__4223: logic__4223
-datapath__555: datapath__555
-case__1373: case__1373
-logic__8391: logic__8391
-logic__4585: logic__4585
-logic__1827: logic__1827
-case__526: case__526
-reg__912: reg__912
-logic__2962: logic__2962
-divider: divider
-case__576: case__576
-reg__353: reg__353
-datapath__279: datapath__279
-case__578: case__578
-logic__7716: logic__7716
-logic__9773: logic__526
-reg__561: reg__561
-logic__276: logic__276
-case__468: case__468
-logic__7991: logic__7991
-case__1109: case__1109
-case__1440: case__1440
-logic__8420: logic__8420
-logic__4581: logic__4581
-logic__518: logic__518
-case__57: case__57
-case__556: case__556
-logic__7748: logic__7748
-reg__778: reg__778
-case__175: case__175
-reg__1087: reg__1087
-logic__5514: logic__5514
-reg__1276: reg__1276
-reg__183: reg__183
-reg__77: reg__77
-logic__5343: logic__5343
-reg__330: reg__330
-case__1371: case__1371
-logic__241: logic__241
-case__1554: case__1554
-logic__3562: logic__3562
-logic__9197: logic__9197
-reg__267: reg__267
-reg__261: reg__261
-logic__1512: logic__1512
-logic__4675: logic__4675
-logic__2991: logic__2991
-logic__9444: logic__3936
-reg__1285: reg__1285
-case__150: case__150
-logic__7478: logic__7478
-case__1276: case__1276
-logic__5536: logic__5536
-logic__4251: logic__4251
-case__166: case__166
-logic__8903: logic__8903
-logic__5338: logic__5338
-case__302: case__302
-logic__3180: logic__3180
-logic__2260: logic__2260
-reg__1521: reg__998
-datapath__159: datapath__159
-datapath__673: datapath__673
-logic__2240: logic__2240
-logic__2010: logic__2010
-logic__3256: logic__3256
-reg__597: reg__597
-logic__1039: logic__1039
-logic__5954: logic__5954
-logic__3851: logic__3851
-logic__1216: logic__1216
-logic__9560: logic__1756
-logic__8931: logic__8931
-case__575: case__575
-TLFIFOFixer_1: TLFIFOFixer_1
-logic__2498: logic__2498
-logic__6837: logic__6837
-reg__32: reg__32
-datapath__321: datapath__321
-logic__2118: logic__2118
-reg__1456: reg__1456
-logic__3327: logic__3327
-reg__793: reg__793
-logic__2090: logic__2090
-reg__576: reg__576
-logic__6599: logic__6599
-case__1093: case__1093
-logic__4598: logic__4598
-logic__6342: logic__6342
-logic__9729: logic__6147
-logic__8150: logic__8150
-case__325: case__325
-case__756: case__756
-reg__969: reg__969
-case__1491: case__1491
-logic__1224: logic__1224
-logic__9706: logic__7684
-case__390: case__390
-logic__628: logic__628
-logic__6844: logic__6844
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__11: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__817: case__817
-logic__3741: logic__3741
-case__894: case__894
-logic__5313: logic__5313
-reg__1060: reg__1060
-case__845: case__845
-logic__6292: logic__6292
-logic__4960: logic__4960
-case__1517: case__1517
-logic__4046: logic__4046
-logic__6068: logic__6068
-case__253: case__253
-case__512: case__512
-logic__7670: logic__7670
-case__277: case__277
-logic__9568: logic__1724
-logic__4172: logic__4172
-case__902: case__902
-logic__5727: logic__5727
-reg__948: reg__948
-logic__4893: logic__4893
-reg__280: reg__280
-logic__2417: logic__2417
-reg__38: reg__38
-reg__1655: reg__70
-case__1171: case__1171
-counter__36: counter__36
-logic__9669: logic__654
-logic__4252: logic__4252
-reg__631: reg__631
-case__1224: case__1224
-logic__8607: logic__8607
-reg__475: reg__475
-logic__7586: logic__7586
-logic__9723: logic__6147
-case__358: case__358
-logic__7905: logic__7905
-reg__1017: reg__1017
-logic__7725: logic__7725
-logic__6000: logic__6000
-case__1222: case__1222
-datapath__435: datapath__435
-datapath__315: datapath__315
-reg__673: reg__673
-logic__6662: logic__6662
-reg__1343: reg__1343
-logic__5494: logic__5494
-case__709: case__709
-logic__6848: logic__6848
-logic__195: logic__195
-reg__493: reg__493
-logic__341: logic__341
-reg__273: reg__273
-logic__5316: logic__5316
-logic__9292: logic__9292
-case__1019: case__1019
-logic__3880: logic__3880
-logic__9653: logic__1521
-TLFragmenter_FPGAUART__1: TLFragmenter_FPGAUART
-logic__8217: logic__8217
-datapath__576: datapath__576
-logic__3869: logic__3869
-logic__1751: logic__1751
-reg__1586: reg__837
-logic__3531: logic__3531
-logic__9194: logic__9194
-logic__865: logic__865
-logic__9478: logic__1869
-logic__9337: logic__9337
-datapath__414: datapath__414
-logic__8450: logic__8450
-logic__2706: logic__2706
-Repeater_TLBundleA_a28d64s2k1z3u: Repeater_TLBundleA_a28d64s2k1z3u
-logic__8346: logic__8346
-logic__5511: logic__5511
-reg__1329: reg__1329
-logic__2437: logic__2437
-reg__89: reg__89
-case__304: case__304
-datapath__699: datapath__699
-case__1558: case__1558
-reg__991: reg__991
-logic__991: logic__991
-datapath__395: datapath__395
-datapath__63: datapath__63
-logic__6575: logic__6575
-case__1618: case__1618
-datapath__623: datapath__623
-logic__6682: logic__6682
-logic__4030: logic__4030
-logic__3483: logic__3483
-reg__59: reg__59
-case__470: case__470
-case__1778: case__102
-datapath__453: datapath__453
-case__773: case__773
-logic__82: logic__82
-logic__1452: logic__1452
-logic__8067: logic__8067
-case__18: case__18
-datapath__412: datapath__412
-logic__4555: logic__4555
-reg__125: reg__125
-logic__6630: logic__6630
-reg__858: reg__858
-ClockGroupAggregator_sbus: ClockGroupAggregator_sbus
-reg__179: reg__179
-logic__232: logic__232
-case__28: case__28
-logic__540: logic__540
-reg__291: reg__291
-logic__9475: logic__1878
-datapath__359: datapath__359
-logic__9143: logic__9143
-logic__4092: logic__4092
-PMAChecker__2: PMAChecker
-ram__3: ram__3
-reg__1101: reg__1101
-muxpart__61: muxpart__61
-case__389: case__389
-logic__5884: logic__5884
-logic__176: logic__176
-logic__502: logic__502
-reg__28: reg__28
-reg__723: reg__723
-case__585: case__585
-muxpart__86: muxpart__86
-rf_31x64: rf_31x64
-reg__535: reg__535
-logic__1601: logic__1601
-case__959: case__959
-logic__3234: logic__3234
-logic__6642: logic__6642
-logic__4742: logic__4742
-datapath__175: datapath__175
-reg__581: reg__581
-logic__2040: logic__2040
-case__116: case__116
-case__439: case__439
-logic__1671: logic__1671
-logic__7970: logic__7970
-case__1616: case__1616
-case__690: case__690
-logic__9356: logic__9356
-reg__344: reg__344
-reg__918: reg__918
-logic__5513: logic__5513
-reg__578: reg__578
-reg__1167: reg__1167
-logic__1299: logic__1299
-logic__583: logic__583
-datapath__94: datapath__94
-logic__1744: logic__1744
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__27: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__531: logic__531
-logic__2161: logic__2161
-reg__1603: reg__838
-logic__1043: logic__1043
-logic__5389: logic__5389
-case__1029: case__1029
-logic__9468: logic__1894
-case__1698: case__459
-logic__4086: logic__4086
-logic__853: logic__853
-case__1303: case__1303
-reg__1480: reg__1251
-logic__7529: logic__7529
-logic__3824: logic__3824
-reg__169: reg__169
-reg__11: reg__11
-logic__5335: logic__5335
-logic__3732: logic__3732
-logic__4155: logic__4155
-logic__6315: logic__6315
-logic__6131: logic__6131
-dsp48e1__38: dsp48e1__38
-logic__8577: logic__8577
-logic__1451: logic__1451
-case__1008: case__1008
-logic__8178: logic__8178
-logic__459: logic__459
-datapath__314: datapath__314
-logic__3845: logic__3845
-logic__6414: logic__6414
-logic__8955: logic__8955
-logic__3966: logic__3966
-logic__1351: logic__1351
-reg__92: reg__92
-datapath__5: datapath__5
-case__884: case__884
-RecFNToIN: RecFNToIN
-logic__8088: logic__8088
-logic__6027: logic__6027
-logic__3629: logic__3629
-reg__298: reg__298
-datapath__78: datapath__78
-logic__9539: logic__1824
-logic__7602: logic__7602
-logic__71: logic__71
-logic__6388: logic__6388
-logic__2897: logic__2897
-logic__79: logic__79
-logic__9553: logic__1779
-case__400: case__400
-logic__7328: logic__7328
-logic__172: logic__172
-logic__3823: logic__3823
-logic__7625: logic__7625
-logic__7349: logic__7349
-logic__1068: logic__1068
-reg__615: reg__615
-logic__5534: logic__5534
-datapath__418: datapath__418
-case__554: case__554
-PMPChecker_s3__1: PMPChecker_s3
-logic__9761: logic__493
-logic__5007: logic__5007
-logic__6186: logic__6186
-reg__517: reg__517
-reg__383: reg__383
-reg__935: reg__935
-case__51: case__51
-logic__2963: logic__2963
-case__460: case__460
-logic__2057: logic__2057
-logic__1026: logic__1026
-DTLB__1: DTLB
-reg__567: reg__567
-reg__1552: reg__838
-logic__3213: logic__3213
-logic__868: logic__868
-datapath__562: datapath__562
-reg__1137: reg__1137
-logic__5463: logic__5463
-logic__3557: logic__3557
-logic__3612: logic__3612
-logic__1663: logic__1663
-logic__4756: logic__4756
-logic__4310: logic__4310
-logic__8203: logic__8203
-logic__8976: logic__8976
-logic__2066: logic__2066
-case__148: case__148
-PeripheryBus_cbus: PeripheryBus_cbus
-reg__329: reg__329
-APBGpsBlock__GCB0: APBGpsBlock__GCB0
-logic__5052: logic__5052
-reg__411: reg__411
-logic__3096: logic__3096
-reg__207: reg__207
-case__169: case__169
-reg__76: reg__76
-reg__715: reg__715
-logic__3637: logic__3637
-logic__3815: logic__3815
-reg__1295: reg__1295
-logic__8592: logic__8592
-logic__7355: logic__7355
-logic__1387: logic__1387
-case__193: case__193
-case__1092: case__1092
-logic__8512: logic__8512
-reg__1268: reg__1268
-reg__653: reg__653
-case__217: case__217
-case__878: case__878
-logic__6688: logic__6688
-ram_2x10: ram_2x10
-logic__4513: logic__4513
-case__993: case__993
-muxpart__47: muxpart__47
-logic__8817: logic__8817
-logic__9544: logic__1807
-logic__6918: logic__6918
-logic__4826: logic__4826
-reg__369: reg__369
-reg__1474: reg__1257
-FixedClockBroadcast_1__1: FixedClockBroadcast_1
-logic__3847: logic__3847
-case__1609: case__1609
-datapath__776: datapath__652
-datapath__771: datapath__111
-AsyncValidSync__7: AsyncValidSync
-logic__625: logic__625
-logic__2708: logic__2708
-case__1024: case__1024
-logic__6407: logic__6407
-keep: keep
-logic__571: logic__571
-logic__883: logic__883
-reg__1643: reg__71
-logic__1980: logic__1980
-logic__5287: logic__5287
-logic__6750: logic__6750
-cordic_atan_basic__parameterized0__1: cordic_atan_basic__parameterized0
-reg__1258: reg__1258
-logic__685: logic__685
-logic__9612: logic__1608
-OptimizationBarrier_TLBEntryData__1: OptimizationBarrier_TLBEntryData
-logic__1398: logic__1398
-reg__103: reg__103
-reg__1076: reg__1076
-logic__9514: logic__1892
-logic__9745: logic__960
-case__1088: case__1088
-muxpart__304: muxpart__304
-datapath__479: datapath__479
-case__1091: case__1091
-logic__9661: logic__670
-datapath__759: datapath__241
-logic__70: logic__70
-reg__1183: reg__1183
-logic__4582: logic__4582
-logic__4328: logic__4328
-logic__3508: logic__3508
-logic__363: logic__363
-reg__1364: reg__1364
-reg__321: reg__321
-case__805: case__805
-logic__5716: logic__5716
-logic__580: logic__580
-datapath__572: datapath__572
-logic__8970: logic__8970
-case__1480: case__1480
-logic__6291: logic__6291
-logic__148: logic__148
-datapath__428: datapath__428
-ram: ram
-logic__6646: logic__6646
-reg__1549: reg__838
-reg__1362: reg__1362
-logic__5937: logic__5937
-reg__895: reg__895
-reg__112: reg__112
-reg__258: reg__258
-logic__2132: logic__2132
-muxpart__231: muxpart__231
-case__1104: case__1104
-dsp48e1__22: dsp48e1__22
-logic__6787: logic__6787
-case__868: case__868
-case__1661: case__1661
-datapath__229: datapath__229
-logic__4855: logic__4855
-logic__2120: logic__2120
-reg__400: reg__400
-logic__5909: logic__5909
-logic__938: logic__938
-logic__659: logic__659
-logic__2080: logic__2080
-logic__987: logic__987
-reg__1666: reg__35
-reg__1110: reg__1110
-logic__9180: logic__9180
-sync__7: sync
-datapath__681: datapath__681
-case__370: case__370
-reg__1585: reg__838
-logic__4530: logic__4530
-logic__4998: logic__4998
-case__338: case__338
-keep__2: keep__2
-case__96: case__96
-logic__8539: logic__8539
-logic__2938: logic__2938
-reg__728: reg__728
-reg__944: reg__944
-case__1: case__1
-logic__4237: logic__4237
-reg__780: reg__780
-logic__1324: logic__1324
-logic__9754: logic__512
-logic__1099: logic__1099
-logic__3863: logic__3863
-muxpart__45: muxpart__45
-case__903: case__903
-logic__6268: logic__6268
-reg__964: reg__964
-logic__5461: logic__5461
-reg__302: reg__302
-logic__6588: logic__6588
-logic__600: logic__600
-logic__2602: logic__2602
-muxpart__77: muxpart__77
-case__725: case__725
-case__1405: case__1405
-datapath__618: datapath__618
-logic__3680: logic__3680
-logic__4672: logic__4672
-reg__1296: reg__1296
-logic: logic
-logic__8388: logic__8388
-reg__749: reg__749
-logic__4309: logic__4309
-logic__4546: logic__4546
-logic__6187: logic__6187
-butterfly: butterfly
-reg__1638: reg__156
-reg__612: reg__612
-reg__1293: reg__1293
-AsyncValidSync__23: AsyncValidSync
-logic__5410: logic__5410
-reg__1567: reg__838
-logic__7093: logic__7093
-SBToTL: SBToTL
-logic__4632: logic__4632
-logic__4889: logic__4889
-logic__8816: logic__8816
-datapath__783: datapath__515
-logic__2347: logic__2347
-logic__1255: logic__1255
-case__745: case__745
-logic__3363: logic__3363
-reg__461: reg__461
-logic__1716: logic__1716
-reg__1531: reg__838
-logic__5064: logic__5064
-datapath__222: datapath__222
-case__1035: case__1035
-case__1682: case__1682
-reg__6: reg__6
-logic__2191: logic__2191
-logic__6136: logic__6136
-logic__4634: logic__4634
-logic__9536: logic__1833
-reg__1457: reg__1457
-logic__6809: logic__6809
-datapath__352: datapath__352
-case__52: case__52
-reg__1324: reg__1324
-case__1602: case__1602
-logic__3743: logic__3743
-logic__1913: logic__1913
-logic__8472: logic__8472
-logic__4315: logic__4315
-logic__645: logic__645
-rom__3: rom__3
-reg__584: reg__584
-reg__299: reg__299
-datapath__317: datapath__317
-datapath__790: datapath__137
-case__639: case__639
-logic__1783: logic__1783
-dsp48e1__7: dsp48e1__7
-logic__4091: logic__4091
-reg__867: reg__867
-datapath__26: datapath__26
-datapath__523: datapath__523
-logic__5356: logic__5356
-datapath__752: datapath__248
-reg__1232: reg__1232
-logic__7304: logic__7304
-logic__3422: logic__3422
-case__1666: case__1666
-logic__8339: logic__8339
-logic__78: logic__78
-keep__9: keep__9
-reg__35: reg__35
-reg__927: reg__927
-datapath__153: datapath__153
-logic__4087: logic__4087
-logic__5963: logic__5963
-logic__9639: logic__1547
-datapath__730: datapath__730
-logic__9501: logic__1926
-logic__3264: logic__3264
-logic__6210: logic__6210
-logic__6123: logic__6123
-datapath__748: datapath__358
-logic__4329: logic__4329
-datapath__105: datapath__105
-reg__1417: reg__1417
-logic__5455: logic__5455
-acq_peak_srch: acq_peak_srch
-reg__681: reg__681
-logic__8061: logic__8061
-logic__1944: logic__1944
-logic__2119: logic__2119
-dsp48e1__5: dsp48e1__5
-dsp48e1__4: dsp48e1__4
-datapath__293: datapath__293
-AsyncValidSync__17: AsyncValidSync
-logic__1494: logic__1494
-reg__290: reg__290
-logic__3858: logic__3858
-case__457: case__457
-case__596: case__596
-logic__7195: logic__7195
-logic__694: logic__694
-datapath__216: datapath__216
-reg__339: reg__339
-logic__2566: logic__2566
-keep__12: keep__12
-logic__3736: logic__3736
-AsyncValidSync__13: AsyncValidSync
-logic__3936: logic__3936
-logic__6427: logic__6427
-logic__939: logic__939
-case__964: case__964
-logic__6396: logic__6396
-muxpart__310: muxpart__310
-logic__7372: logic__7372
-logic__1821: logic__1821
-logic__8722: logic__8722
-datapath__624: datapath__624
-case__292: case__292
-logic__2952: logic__2952
-datapath__340: datapath__340
-case__176: case__176
-logic__2479: logic__2479
-logic__5459: logic__5459
-datapath__675: datapath__675
-logic__2199: logic__2199
-case__524: case__524
-case__963: case__963
-logic__4915: logic__4915
-logic__3877: logic__3877
-case__1344: case__1344
-DivSqrtRawFN_small: DivSqrtRawFN_small
-case__842: case__842
-Repeater_TLBundleA_a29d64s2k1z3u_3: Repeater_TLBundleA_a29d64s2k1z3u_3
-logic__9799: logic__281
-logic__3259: logic__3259
-logic__4608: logic__4608
-reg__1172: reg__1172
-reg__1594: reg__838
-case__1607: case__1607
-logic__9157: logic__9157
-logic__2704: logic__2704
-logic__4671: logic__4671
-case__130: case__130
-Queue1_TLBundleA_a29d32s7k1z2u: Queue1_TLBundleA_a29d32s7k1z2u
-case__465: case__465
-reg__679: reg__679
-case__1636: case__1636
-reg__1566: reg__836
-logic__4411: logic__4411
-case__436: case__436
-muxpart__32: muxpart__32
-reg__164: reg__164
-case__35: case__35
-datapath__353: datapath__353
-case__247: case__247
-AsyncResetSynchronizerShiftReg_w1_d3_i0__1: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__8765: logic__8765
-logic__2267: logic__2267
-datapath__289: datapath__289
-rom__5: rom__5
-reg__647: reg__647
-logic__9786: logic__493
-datapath__29: datapath__29
-datapath__757: datapath__243
-logic__387: logic__387
-logic__1050: logic__1050
-case__164: case__164
-logic__451: logic__451
-logic__2996: logic__2996
-case__1036: case__1036
-logic__8815: logic__8815
-logic__4542: logic__4542
-logic__7348: logic__7348
-reg__375: reg__375
-logic__5308: logic__5308
-reg__924: reg__924
-case__1141: case__1141
-reg__1123: reg__1123
-NonSyncResetSynchronizerPrimitiveShiftReg_d3__1: NonSyncResetSynchronizerPrimitiveShiftReg_d3
-dsp48e1__6: dsp48e1__6
-logic__1836: logic__1836
-logic__6101: logic__6101
-logic__705: logic__705
-reg__727: reg__727
-datapath__695: datapath__695
-counter__12: counter__12
-ram_2x77__1: ram_2x77
-logic__3133: logic__3133
-logic__3509: logic__3509
-logic__6409: logic__6409
-logic__3781: logic__3781
-logic__8733: logic__8733
-case__1051: case__1051
-reg__209: reg__209
-logic__748: logic__748
-reg__263: reg__263
-logic__3876: logic__3876
-logic__6321: logic__6321
-datapath__230: datapath__230
-logic__7124: logic__7124
-muxpart__75: muxpart__75
-reg__756: reg__756
-case__591: case__591
-mult_30_25_55: mult_30_25_55
-logic__2429: logic__2429
-reg__607: reg__607
-case__904: case__904
-logic__6422: logic__6422
-logic__4927: logic__4927
-datapath__630: datapath__630
-sync__9: sync
-reg__692: reg__692
-logic__2705: logic__2705
-reg__744: reg__744
-case__1713: case__324
-AsyncResetSynchronizerShiftReg_w1_d3_i0__9: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__9615: logic__1601
-reg__1535: reg__837
-logic__9801: logic__276
-case__1627: case__1627
-case__612: case__612
-logic__5933: logic__5933
-reg__936: reg__936
-logic__2058: logic__2058
-logic__9740: logic__6152
-datapath__467: datapath__467
-case__936: case__936
-logic__4317: logic__4317
-case__853: case__853
-logic__5879: logic__5879
-case__1771: case__109
-case__1766: case__103
-extram__6: extram__6
-datapath__384: datapath__384
-reg__13: reg__13
-logic__7067: logic__7067
-logic__8506: logic__8506
-IntSyncAsyncCrossingSink_n1x1__1: IntSyncAsyncCrossingSink_n1x1
-datapath__765: datapath__117
-ram_2x99: ram_2x99
-signinv__2: signinv__2
-logic__5085: logic__5085
-reg__380: reg__380
-reg__180: reg__180
-case__1087: case__1087
-logic__6099: logic__6099
-logic__5487: logic__5487
-logic__7162: logic__7162
-logic__3263: logic__3263
-logic__3073: logic__3073
-reg__754: reg__754
-logic__4926: logic__4926
-reg__536: reg__536
-reg__1532: reg__837
-case__64: case__64
-datapath__657: datapath__657
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__11: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__1571: reg__837
-logic__9763: logic__491
-reg__1493: reg__1000
-logic__5462: logic__5462
-logic__6213: logic__6213
-datapath__687: datapath__687
-logic__9173: logic__9173
-reg__1138: reg__1138
-logic__6931: logic__6931
-reg__940: reg__940
-case__1221: case__1221
-logic__5505: logic__5505
-datapath__50: datapath__50
-case__93: case__93
-case__816: case__816
-logic__984: logic__984
-logic__9803: logic__272
-logic__2270: logic__2270
-reg__9: reg__9
-case__1411: case__1411
-logic__1471: logic__1471
-logic__8707: logic__8707
-logic__411: logic__411
-datapath__295: datapath__295
-logic__7570: logic__7570
-logic__2410: logic__2410
-logic__4930: logic__4930
-case__598: case__598
-logic__3838: logic__3838
-reg__3: reg__3
-datapath__277: datapath__277
-reg__351: reg__351
-datapath__373: datapath__373
-logic__3613: logic__3613
-logic__759: logic__759
-logic__3739: logic__3739
-reg__847: reg__847
-logic__9623: logic__1583
-logic__7129: logic__7129
-logic__2334: logic__2334
-logic__2616: logic__2616
-Queue2_TLBundleD_a29d64s2k1z3u__1: Queue2_TLBundleD_a29d64s2k1z3u
-case__462: case__462
-reg__287: reg__287
-case__1147: case__1147
-case__1711: case__326
-reg__1166: reg__1166
-logic__8257: logic__8257
-reg__689: reg__689
-case__1750: case__1052
-datapath__504: datapath__504
-case__1606: case__1606
-datapath__248: datapath__248
-reg__357: reg__357
-case__1398: case__1398
-reg__761: reg__761
-case__1062: case__1062
-logic__786: logic__786
-datapath__245: datapath__245
-case__895: case__895
-logic__9160: logic__9160
-INToRecFN: INToRecFN
-reg__919: reg__919
-logic__1237: logic__1237
-logic__643: logic__643
-datapath__803: datapath__18
-APBGpsBlock__GCB1: APBGpsBlock__GCB1
-logic__9526: logic__1857
-logic__9744: logic__964
-reg__833: reg__833
-case__300: case__300
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__4: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__1481: case__1481
-reg__1499: reg__1000
-logic__2141: logic__2141
-logic__318: logic__318
-logic__467: logic__467
-muxpart__42: muxpart__42
-logic__3585: logic__3585
-datapath__361: datapath__361
-logic__404: logic__404
-datapath__684: datapath__684
-logic__820: logic__820
-reg__995: reg__995
-case__1441: case__1441
-reg__12: reg__12
-case__86: case__86
-logic__6800: logic__6800
-case__89: case__89
-reg__404: reg__404
-logic__6573: logic__6573
-logic__3789: logic__3789
-reg__871: reg__871
-reg__114: reg__114
-logic__9166: logic__9166
-logic__101: logic__101
-logic__6296: logic__6296
-logic__3298: logic__3298
-case__823: case__823
-case__614: case__614
-logic__2978: logic__2978
-logic__3560: logic__3560
-case__11: case__11
-logic__7423: logic__7423
-logic__8173: logic__8173
-logic__9797: logic__283
-logic__9663: logic__668
-logic__2496: logic__2496
-logic__8451: logic__8451
-logic__6808: logic__6808
-logic__6562: logic__6562
-mult_46_15_61: mult_46_15_61
-logic__881: logic__881
-logic__3310: logic__3310
-logic__6781: logic__6781
-case__815: case__815
-reg__1126: reg__1126
-logic__8348: logic__8348
-logic__9651: logic__1523
-datapath__804: datapath__17
-reg__641: reg__641
-logic__9666: logic__660
-reg__773: reg__773
-logic__7817: logic__7817
-logic__8534: logic__8534
-logic__9627: logic__1575
-logic__6387: logic__6387
-case__205: case__205
-reg__1180: reg__1180
-case__267: case__267
-reg__162: reg__162
-case__529: case__529
-muxpart__143: muxpart__143
-logic__9667: logic__659
-logic__3164: logic__3164
-logic__6805: logic__6805
-logic__5666: logic__5666
-reg__1225: reg__1225
-reg__81: reg__81
-datapath__343: datapath__343
-reg__230: reg__230
-reg__1026: reg__1026
-logic__9548: logic__1796
-logic__9402: logic__3011
-reg__1250: reg__1250
-case__1427: case__1427
-logic__2000: logic__2000
-logic__3326: logic__3326
-logic__7577: logic__7577
-logic__969: logic__969
-logic__2997: logic__2997
-case__828: case__828
-afe_top: afe_top
-logic__443: logic__443
-reg__707: reg__707
-datapath__93: datapath__93
-reg__1039: reg__1039
-datapath__429: datapath__429
-reg__485: reg__485
-reg__41: reg__41
-logic__243: logic__243
-logic__3740: logic__3740
-logic__3993: logic__3993
-case__74: case__74
-case__1449: case__1449
-reg__648: reg__648
-logic__4083: logic__4083
-logic__6609: logic__6609
-case__813: case__813
-logic__3811: logic__3811
-reg__1400: reg__1400
-logic__9145: logic__9145
-datapath__174: datapath__174
-bram__parameterized0: bram__parameterized0
-logic__9189: logic__9189
-logic__4588: logic__4588
-logic__5971: logic__5971
-logic__9572: logic__1716
-reg__307: reg__307
-logic__4708: logic__4708
-case__716: case__716
-dsp48e1__11: dsp48e1__11
-case__1377: case__1377
-logic__3579: logic__3579
-datapath__333: datapath__333
-muxpart__67: muxpart__67
-reg__660: reg__660
-logic__5274: logic__5274
-reg__629: reg__629
-case__896: case__896
-logic__8180: logic__8180
-reg__537: reg__537
-case__626: case__626
-datapath__355: datapath__355
-mult_64_48_112: mult_64_48_112
-reg__195: reg__195
-case__1136: case__1136
-counter__28: counter__28
-counter__25: counter__25
-case__1549: case__1549
-logic__1301: logic__1301
-case__599: case__599
-logic__7626: logic__7626
-logic__6673: logic__6673
-logic__6102: logic__6102
-logic__2438: logic__2438
-logic__4550: logic__4550
-reg__907: reg__907
-reg__266: reg__266
-logic__2635: logic__2635
-logic__9200: logic__9200
-logic__4013: logic__4013
-case__1061: case__1061
-ram__8: ram__8
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__4: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__9755: logic__511
-logic__9162: logic__9162
-logic__7495: logic__7495
-logic__6028: logic__6028
-logic__2104: logic__2104
-logic__1884: logic__1884
-logic__6067: logic__6067
-reg__308: reg__308
-AsyncResetRegVec_w1_i0__1: AsyncResetRegVec_w1_i0
-datapath__545: datapath__545
-case__1526: case__1526
-logic__7595: logic__7595
-reg__1045: reg__1045
-case__859: case__859
-fft_radix_2__parameterized0: fft_radix_2__parameterized0
-logic__8658: logic__8658
-logic__449: logic__449
-logic__3206: logic__3206
-case__1535: case__1535
-muxpart__107: muxpart__107
-case__1734: case__1418
-logic__5456: logic__5456
-logic__2714: logic__2714
-logic__6593: logic__6593
-logic__316: logic__316
-reg__1052: reg__1052
-logic__3843: logic__3843
-case__1768: case__112
-PMAChecker: PMAChecker
-AsyncValidSync__19: AsyncValidSync
-logic__3305: logic__3305
-logic__8792: logic__8792
-logic__5286: logic__5286
-logic__9672: logic__8484
-PeripheryBus_pbus: PeripheryBus_pbus
-case__1479: case__1479
-logic__7420: logic__7420
-logic__6739: logic__6739
-logic__3885: logic__3885
-logic__7367: logic__7367
-logic__9742: logic__966
-logic__1704: logic__1704
-datapath__71: datapath__71
-logic__9366: logic__9366
-reg__1104: reg__1104
-logic__7676: logic__7676
-logic__7661: logic__7661
-logic__2821: logic__2821
-logic__2400: logic__2400
-logic__2604: logic__2604
-logic__385: logic__385
-logic__5503: logic__5503
-logic__9594: logic__1648
-logic__1429: logic__1429
-logic__9787: logic__492
-logic__9485: logic__1848
-logic__9720: logic__7585
-logic__6916: logic__6916
-logic__521: logic__521
-datapath__785: datapath__523
-logic__5662: logic__5662
-reg__1553: reg__837
-logic__821: logic__821
-logic__9191: logic__9191
-reg__117: reg__117
-logic__4401: logic__4401
-logic__3419: logic__3419
-reg__955: reg__955
-logic__6590: logic__6590
-reg__1067: reg__1067
-logic__7733: logic__7733
-keep__24: keep__24
-case__65: case__65
-logic__5339: logic__5339
-case__871: case__871
-logic__127: logic__127
-case__238: case__238
-logic__623: logic__623
-case__20: case__20
-reg__586: reg__586
-datapath__396: datapath__396
-datapath__404: datapath__404
-datapath__722: datapath__722
-logic__9671: logic__8488
-reg__1599: reg__836
-case__342: case__342
-logic__6048: logic__6048
-logic__6598: logic__6598
-logic__2254: logic__2254
-reg__721: reg__721
-logic__2311: logic__2311
-datapath__560: datapath__560
-logic__4838: logic__4838
-reg__938: reg__938
-logic__9756: logic__508
-case__1754: case__1048
-muxpart__43: muxpart__43
-logic__7342: logic__7342
-keep__22: keep__22
-logic__4023: logic__4023
-case__1436: case__1436
-logic__9142: logic__9142
-logic__2930: logic__2930
-logic__4338: logic__4338
-logic__9528: logic__1851
-case__158: case__158
-case__1304: case__1304
-datapath__266: datapath__266
-datapath__346: datapath__346
-logic__2710: logic__2710
-case__101: case__101
-counter__26: counter__26
-logic__9778: logic__515
-Queue1_TLBundleA_a14d64s2k1z4u: Queue1_TLBundleA_a14d64s2k1z4u
-logic__3742: logic__3742
-logic__5292: logic__5292
-case__617: case__617
-logic__1320: logic__1320
-logic__9805: logic__267
-case__1381: case__1381
-logic__4839: logic__4839
-reg__185: reg__185
-logic__8948: logic__8948
-logic__3267: logic__3267
-logic__6133: logic__6133
-logic__9746: logic__959
-logic__5247: logic__5247
-logic__4212: logic__4212
-datapath__201: datapath__201
-logic__160: logic__160
-reg__521: reg__521
-case__881: case__881
-logic__1054: logic__1054
-logic__1676: logic__1676
-logic__6792: logic__6792
-case__500: case__500
-logic__4316: logic__4316
-logic__2697: logic__2697
-logic__6304: logic__6304
-case__542: case__542
-logic__2327: logic__2327
-reg__829: reg__829
-reg__1249: reg__1249
-logic__4072: logic__4072
-reg__454: reg__454
-logic__4720: logic__4720
-reg__108: reg__108
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__20: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__476: case__476
-logic__5395: logic__5395
-datapath__742: datapath__300
-logic__4633: logic__4633
-case__804: case__804
-reg__1309: reg__1309
-reg__193: reg__193
-case__1764: case__105
-case__708: case__708
-logic__1124: logic__1124
-logic__1863: logic__1863
-logic__3015: logic__3015
-Repeater_TLBundleA_a26d64s2k1z3u: Repeater_TLBundleA_a26d64s2k1z3u
-logic__979: logic__979
-logic__9741: logic__6147
-datapath__92: datapath__92
-logic__7010: logic__7010
-logic__6198: logic__6198
-reg__363: reg__363
-logic__4861: logic__4861
-datapath__525: datapath__525
-reg__385: reg__385
-case__1467: case__1467
-datapath__48: datapath__48
-case__314: case__314
-case__747: case__747
-reg__265: reg__265
-logic__4383: logic__4383
-reg__138: reg__138
-TLFIFOFixer: TLFIFOFixer
-logic__8066: logic__8066
-datapath__235: datapath__235
-logic__8060: logic__8060
-logic__7079: logic__7079
-logic__2967: logic__2967
-logic__2945: logic__2945
-case__272: case__272
-logic__1854: logic__1854
-case__540: case__540
-logic__1892: logic__1892
-case__1756: case__1046
-case__120: case__120
-logic__4375: logic__4375
-datapath__196: datapath__196
-logic__714: logic__714
-reg__662: reg__662
-logic__5075: logic__5075
-logic__9352: logic__9352
-datapath__597: datapath__597
-logic__5309: logic__5309
-reg__823: reg__823
-reg__52: reg__52
-case__616: case__616
-logic__1869: logic__1869
-logic__8437: logic__8437
-logic__1433: logic__1433
-case__778: case__778
-logic__1411: logic__1411
-extram__3: extram__3
-case__486: case__486
-logic__6992: logic__6992
-case__299: case__299
-reg__566: reg__566
-case__1012: case__1012
-datapath__181: datapath__181
-case__448: case__448
-logic__4619: logic__4619
-reg__706: reg__706
-logic__4931: logic__4931
-logic__139: logic__139
-reg__687: reg__687
-logic__1796: logic__1796
-case__114: case__114
-reg__40: reg__40
-datapath__1: datapath__1
-reg__972: reg__972
-logic__9596: logic__1644
-logic__3873: logic__3873
-datapath__683: datapath__683
-logic__6040: logic__6040
-logic__3229: logic__3229
-logic__1120: logic__1120
-case__183: case__183
-reg__524: reg__524
-logic__4879: logic__4879
-logic__586: logic__586
-Repeater_TLBundleA_a29d32s2k1z3u: Repeater_TLBundleA_a29d32s2k1z3u
-datapath__625: datapath__625
-datapath__772: datapath__110
-muxpart__92: muxpart__92
-logic__7594: logic__7594
-case__1125: case__1125
-logic__6545: logic__6545
-case__1101: case__1101
-reg__1500: reg__999
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__21: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-datapath__180: datapath__180
-reg__433: reg__433
-reg__1602: reg__836
-logic__6139: logic__6139
-case__1341: case__1341
-logic__64: logic__64
-case__122: case__122
-logic__1613: logic__1613
-logic__4341: logic__4341
-logic__3683: logic__3683
-reg__552: reg__552
-logic__2720: logic__2720
-case__976: case__976
-logic__3841: logic__3841
-reg__224: reg__224
-keep__50: keep__7
-logic__5067: logic__5067
-datapath__335: datapath__335
-logic__5320: logic__5320
-reg__1564: reg__838
-reg__1072: reg__1072
-logic__5529: logic__5529
-datapath__244: datapath__244
-reg__1540: reg__838
-logic__9488: logic__1843
-NCO_code: NCO_code
-case__630: case__630
-logic__1031: logic__1031
-case__1384: case__1384
-logic__9583: logic__1679
-logic__6569: logic__6569
-logic__747: logic__747
-logic__5549: logic__5549
-reg__335: reg__335
-logic__6927: logic__6927
-logic__9530: logic__1847
-logic__1847: logic__1847
-logic__1654: logic__1654
-case__129: case__129
-logic__871: logic__871
-reg__1160: reg__1160
-logic__6050: logic__6050
-logic__5712: logic__5712
-datapath__781: datapath__647
-case__1513: case__1513
-reg__516: reg__516
-logic__5517: logic__5517
-reg__1280: reg__1280
-datapath__88: datapath__88
-logic__2960: logic__2960
-logic__2641: logic__2641
-logic__8469: logic__8469
-reg__238: reg__238
-logic__238: logic__238
-case__1550: case__1550
-reg__61: reg__61
-case__672: case__672
-muxpart__17: muxpart__17
-datapath__788: datapath__139
-logic__5401: logic__5401
-logic__3474: logic__3474
-reg__738: reg__738
-case__1686: case__1686
-reg__1224: reg__1224
-logic__3198: logic__3198
-logic__142: logic__142
-datapath__10: datapath__10
-logic__7959: logic__7959
-logic__9316: logic__9316
-logic__2201: logic__2201
-datapath__336: datapath__336
-logic__1964: logic__1964
-logic__6759: logic__6759
-logic__1121: logic__1121
-datapath__424: datapath__424
-reg__1148: reg__1148
-logic__6080: logic__6080
-keep__37: keep__37
-reg__54: reg__54
-case__1328: case__1328
-datapath__478: datapath__478
-case__383: case__383
-reg__711: reg__711
-reg__1153: reg__1153
-reg__726: reg__726
-TLToAPB: TLToAPB
-logic__3996: logic__3996
-logic__4024: logic__4024
-logic__4356: logic__4356
-reg__1498: reg__1001
-reg__758: reg__758
-logic__1356: logic__1356
-ClockGroupAggregator_cbus: ClockGroupAggregator_cbus
-datapath__274: datapath__274
-keep__67: keep__8
-logic__3325: logic__3325
-reg__1218: reg__1218
-reg__1083: reg__1083
-reg__1181: reg__1181
-logic__6667: logic__6667
-logic__5962: logic__5962
-logic__8529: logic__8529
-datapath__442: datapath__442
-keep__3: keep__3
-logic__7247: logic__7247
-logic__915: logic__915
-logic__3679: logic__3679
-rom: rom
-logic__490: logic__490
-logic__9774: logic__521
-reg__1512: reg__999
-logic__2957: logic__2957
-logic__4977: logic__4977
-logic__8325: logic__8325
-logic__944: logic__944
-logic__4241: logic__4241
-logic__9788: logic__491
-datapath__734: datapath__734
-logic__3568: logic__3568
-datapath__144: datapath__144
-reg__1128: reg__1128
-logic__4938: logic__4938
-logic__1547: logic__1547
-reg__336: reg__336
-reg__984: reg__984
-dsp48e1__27: dsp48e1__27
-case__738: case__738
-logic__8465: logic__8465
-reg__429: reg__429
-logic__6839: logic__6839
-case__1234: case__1234
-case__655: case__655
-case__1356: case__1356
-AsyncResetSynchronizerShiftReg_w1_d3_i0__5: AsyncResetSynchronizerShiftReg_w1_d3_i0
-case__1419: case__1419
-logic__9721: logic__7584
-reg__1561: reg__838
-case__160: case__160
-logic__5215: logic__5215
-muxpart__62: muxpart__62
-logic__9625: logic__1577
-datapath__558: datapath__558
-reg__1410: reg__1410
-reg__1502: reg__1000
-logic__6357: logic__6357
-logic__5880: logic__5880
-case__608: case__608
-case__721: case__721
-reg__1311: reg__1311
-reg__917: reg__917
-PMAChecker__1: PMAChecker
-keep__52: keep__8
-Queue2_TLBundleD_a32d8s1k1z4u: Queue2_TLBundleD_a32d8s1k1z4u
-datapath__805: datapath__16
-logic__9499: logic__1928
-logic__9474: logic__1881
-logic__3309: logic__3309
-logic__5367: logic__5367
-logic__6258: logic__6258
-logic__1482: logic__1482
-datapath__37: datapath__37
-logic__7681: logic__7681
-logic__8950: logic__8950
-logic__2426: logic__2426
-logic__2686: logic__2686
-keep__76: keep__1
-reg__571: reg__571
-logic__4636: logic__4636
-case__189: case__189
-case__353: case__353
-reg__74: reg__74
-logic__2719: logic__2719
-extram__2: extram__2
-logic__9521: logic__1872
-case__326: case__326
-ram__6: ram__6
-case__945: case__945
-case__207: case__207
-datapath__119: datapath__119
-logic__1432: logic__1432
-logic__6467: logic__6467
-case__87: case__87
-reg__87: reg__87
-logic__2940: logic__2940
-logic__5920: logic__5920
-case__1742: case__1410
-logic__6196: logic__6196
-logic__1020: logic__1020
-case__212: case__212
-reg__453: reg__453
-reg__37: reg__37
-logic__4169: logic__4169
-logic__6218: logic__6218
-case__833: case__833
-logic__1249: logic__1249
-case__1192: case__1192
-logic__9465: logic__1899
-logic__5266: logic__5266
-logic__2397: logic__2397
-logic__9557: logic__1763
-reg__1152: reg__1152
-rockettile_icache_tag_array_0_64x21: rockettile_icache_tag_array_0_64x21
-case__1414: case__1414
-case__98: case__98
-case__1346: case__1346
-sync__8: sync
-reg__277: reg__277
-AsyncResetSynchronizerShiftReg_w1_d3_i0__6: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__1245: logic__1245
-logic__5364: logic__5364
-case__872: case__872
-case__615: case__615
-LevelGateway__7: LevelGateway
-reg__176: reg__176
-case__340: case__340
-case__799: case__799
-case__740: case__740
-case__97: case__97
-case__1476: case__1476
-logic__1040: logic__1040
-logic__3839: logic__3839
-reg__486: reg__486
-ClockGroupAggregator_aggregator: ClockGroupAggregator_aggregator
-logic__4105: logic__4105
-logic__6934: logic__6934
-logic__634: logic__634
-datapath__584: datapath__584
-logic__2725: logic__2725
-reg__661: reg__661
-logic__9463: logic__1901
-logic__9601: logic__1631
-reg__1346: reg__1346
-logic__6790: logic__6790
-case__1760: case__109
-reg__1253: reg__1253
-datapath__114: datapath__114
-muxpart__71: muxpart__71
-logic__8492: logic__8492
-reg__222: reg__222
-reg__840: reg__840
-case__827: case__827
-reg__39: reg__39
-HellaCacheArbiter: HellaCacheArbiter
-reg__1214: reg__1214
-case__1408: case__1408
-case__700: case__700
-logic__3911: logic__3911
-logic__4856: logic__4856
-logic__3555: logic__3555
-reg__346: reg__346
-reg__1246: reg__1246
-case__1334: case__1334
-logic__4041: logic__4041
-case__275: case__275
-logic__9454: logic__3901
-case__228: case__228
-datapath__242: datapath__242
-logic__1936: logic__1936
-datapath__632: datapath__632
-case__900: case__900
-datapath__278: datapath__278
-datapath__658: datapath__658
-case__1199: case__1199
-case__569: case__569
-logic__3785: logic__3785
-reg__1432: reg__1432
-logic__6603: logic__6603
-logic__1742: logic__1742
-case__1340: case__1340
-case__1404: case__1404
-datapath__183: datapath__183
-reg__1595: reg__837
-case__1717: case__320
-logic__1507: logic__1507
-logic__9481: logic__1860
-datapath__782: datapath__646
-logic__1891: logic__1891
-logic__6664: logic__6664
-reg__548: reg__548
-case__499: case__499
-logic__9418: logic__2978
-logic__4625: logic__4625
-reg__78: reg__78
-logic__3684: logic__3684
-logic__6533: logic__6533
-dsp48e1__18: dsp48e1__18
-keep__7: keep__7
-reg__1443: reg__1443
-logic__8270: logic__8270
-logic__8433: logic__8433
-logic__6752: logic__6752
-TLFragmenter_Debug: TLFragmenter_Debug
-logic__4963: logic__4963
-logic__2825: logic__2825
-logic__106: logic__106
-logic__2617: logic__2617
-datapath__464: datapath__464
-logic__4440: logic__4440
-datapath__182: datapath__182
-logic__955: logic__955
-logic__639: logic__639
-AsyncValidSync__11: AsyncValidSync
-reg__53: reg__53
-reg__1049: reg__1049
-logic__8461: logic__8461
-AsyncValidSync: AsyncValidSync
-case__1529: case__1529
-logic__9336: logic__9336
-logic__1623: logic__1623
-counter__15: counter__15
-reg__1233: reg__1233
-case__899: case__899
-ClockGroupAggregator_pbus__1: ClockGroupAggregator_pbus
-logic__7947: logic__7947
-case__1531: case__1531
-logic__3425: logic__3425
-RocketALU: RocketALU
-logic__9372: logic__9372
-logic__6474: logic__6474
-logic__568: logic__568
-datapath__526: datapath__526
-logic__9476: logic__1875
-logic__1550: logic__1550
-reg__1501: reg__1001
-case__284: case__284
-logic__8255: logic__8255
-case__720: case__720
-datapath__701: datapath__701
-reg__386: reg__386
-logic__3962: logic__3962
-case__174: case__174
-case__368: case__368
-Frontend: Frontend
-datapath__743: datapath__299
-logic__2721: logic__2721
-reg__420: reg__420
-case__568: case__568
-logic__5074: logic__5074
-reg__1075: reg__1075
-reg__297: reg__297
-logic__5304: logic__5304
-reg__68: reg__68
-logic__7756: logic__7756
-reg__965: reg__965
-logic__6523: logic__6523
-logic__237: logic__237
-logic__2901: logic__2901
-logic__5092: logic__5092
-logic__5032: logic__5032
-case__361: case__361
-logic__9680: logic__8465
-logic__8361: logic__8361
-reg__311: reg__311
-logic__2707: logic__2707
-keep__70: keep__1
-datapath__419: datapath__419
-logic__7327: logic__7327
-logic__9408: logic__2998
-case__583: case__583
-reg__1042: reg__1042
-case__1533: case__1533
-RoundRawFNToRecFN_1: RoundRawFNToRecFN_1
-logic__8329: logic__8329
-case__180: case__180
-datapath__659: datapath__659
-logic__1152: logic__1152
-logic__8188: logic__8188
-logic__4840: logic__4840
-case__1281: case__1281
-case__306: case__306
-logic__1022: logic__1022
-case__147: case__147
-reg__1387: reg__1387
-case__291: case__291
-datapath__579: datapath__579
-datapath__465: datapath__465
-logic__4307: logic__4307
-case__798: case__798
-logic__305: logic__305
-case__670: case__670
-logic__3350: logic__3350
-logic__6503: logic__6503
-logic__6419: logic__6419
-datapath__481: datapath__481
-datapath__602: datapath__602
-muxpart__95: muxpart__95
-datapath__751: datapath__249
-reg__887: reg__887
-logic__3556: logic__3556
-datapath__409: datapath__409
-datapath__480: datapath__480
-reg__191: reg__191
-logic__9655: logic__1517
-reg__872: reg__872
-logic__3173: logic__3173
-logic__3844: logic__3844
-logic__6687: logic__6687
-case__1375: case__1375
-logic__3955: logic__3955
-case__1030: case__1030
-logic__9407: logic__2999
-logic__4638: logic__4638
-datapath__749: datapath__357
-datapath__2: datapath__2
-reg__1034: reg__1034
-logic__7462: logic__7462
-logic__8087: logic__8087
-AsyncValidSync__5: AsyncValidSync
-logic__283: logic__283
-logic__8966: logic__8966
-datapath__275: datapath__275
-reg__1490: reg__1144
-logic__8438: logic__8438
-case__698: case__698
-logic__701: logic__701
-reg__1020: reg__1020
-reg__448: reg__448
-muxpart__37: muxpart__37
-logic__3900: logic__3900
-reg__575: reg__575
-reg__892: reg__892
-reg__600: reg__600
-logic__5365: logic__5365
-logic__1446: logic__1446
-reg__1438: reg__1438
-case__1451: case__1451
-muxpart__57: muxpart__57
-TLPLIC: TLPLIC
-reg__1264: reg__1264
-logic__2014: logic__2014
-case__1739: case__1413
-logic__7088: logic__7088
-logic__6142: logic__6142
-reg__819: reg__819
-logic__6178: logic__6178
-case__1132: case__1132
-logic__9255: logic__9255
-logic__1101: logic__1101
-case__1139: case__1139
-logic__9331: logic__9331
-datapath__571: datapath__571
-case__839: case__839
-case__1773: case__107
-ScratchpadSlavePort: ScratchpadSlavePort
-logic__8735: logic__8735
-reg__259: reg__259
-logic__4059: logic__4059
-reg__1286: reg__1286
-case__727: case__727
-logic__1458: logic__1458
-datapath__130: datapath__130
-reg__702: reg__702
-logic__3687: logic__3687
-reg__596: reg__596
-logic__497: logic__497
-logic__1682: logic__1682
-case__1240: case__1240
-logic__9600: logic__1632
-case__1518: case__1518
-logic__4294: logic__4294
-logic__5830: logic__5830
-logic__6602: logic__6602
-logic__6413: logic__6413
-logic__6546: logic__6546
-logic__6286: logic__6286
-datapath__53: datapath__53
-case__975: case__975
-LevelGateway__2: LevelGateway
-logic__1866: logic__1866
-logic__9571: logic__1719
-logic__8012: logic__8012
-logic__6276: logic__6276
-logic__6143: logic__6143
-logic__3174: logic__3174
-case__104: case__104
-keep__8: keep__8
-reg__163: reg__163
-reg__1431: reg__1431
-logic__8415: logic__8415
-trck_cntrl: trck_cntrl
-muxpart__2: muxpart__2
-logic__6045: logic__6045
-logic__1173: logic__1173
-case__1193: case__1193
-dsp48e1__43: dsp48e1__43
-reg__1637: reg__784
-reg__623: reg__623
-datapath__87: datapath__87
-reg__1328: reg__1328
-logic__9634: logic__1558
-extrom__2: extrom__1
-reg__305: reg__305
-case__541: case__541
-datapath__257: datapath__257
-logic__1315: logic__1315
-logic__7814: logic__7814
-keep__23: keep__23
-reg__233: reg__233
-logic__9185: logic__9185
-logic__7555: logic__7555
-case__937: case__937
-case__1600: case__1600
-reg__318: reg__318
-logic__6892: logic__6892
-logic__444: logic__444
-logic__3688: logic__3688
-reg__1248: reg__1248
-logic__7028: logic__7028
-logic__3190: logic__3190
-case__450: case__450
-logic__4153: logic__4153
-case__1712: case__325
-AsyncValidSync__6: AsyncValidSync
-logic__3240: logic__3240
-datapath__327: datapath__327
-case__55: case__55
-reg__1516: reg__838
-logic__4687: logic__4687
-case__72: case__72
-datapath__179: datapath__179
-logic__8690: logic__8690
-case__235: case__235
-logic__4462: logic__4462
-reg__985: reg__985
-datapath__103: datapath__103
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__34: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__431: case__431
-case__1397: case__1397
-logic__1058: logic__1058
-logic__2396: logic__2396
-logic__9234: logic__9234
-logic__8364: logic__8364
-reg__768: reg__768
-reg__245: reg__245
-muxpart__311: muxpart__311
-IntSyncCrossingSource_n1x1__1: IntSyncCrossingSource_n1x1
-case__994: case__994
-datapath__299: datapath__299
-TLInterconnectCoupler_cbus_to_rockettile: TLInterconnectCoupler_cbus_to_rockettile
-case__236: case__236
-logic__2893: logic__2893
-case__420: case__420
-logic__5231: logic__5231
-logic__6917: logic__6917
-logic__3689: logic__3689
-reg__1494: reg__999
-logic__6564: logic__6564
-logic__3158: logic__3158
-logic__6487: logic__6487
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__36: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__1703: logic__1703
-logic__3290: logic__3290
-mult_46_15_61__2: mult_46_15_61
-logic__8971: logic__8971
-logic__8662: logic__8662
-logic__6256: logic__6256
-logic__5705: logic__5705
-logic__4472: logic__4472
-logic__6075: logic__6075
-logic__6626: logic__6626
-case__1009: case__1009
-datapath__68: datapath__68
-logic__4740: logic__4740
-logic__2902: logic__2902
-keep__69: keep__6
-logic__2915: logic__2915
-case__336: case__336
-logic__2020: logic__2020
-reg__603: reg__603
-logic__4556: logic__4556
-logic__1374: logic__1374
-logic__6841: logic__6841
-logic__9772: logic__527
-logic__2251: logic__2251
-reg__478: reg__478
-reg__862: reg__862
-datapath__512: datapath__512
-case__152: case__152
-logic__3286: logic__3286
-reg__1539: reg__836
-logic__5916: logic__5916
-datapath__40: datapath__40
-logic__9342: logic__9342
-reg__650: reg__650
-logic__5722: logic__5722
-datapath__725: datapath__725
-logic__4216: logic__4216
-logic__4962: logic__4962
-reg__1424: reg__1424
-reg__526: reg__526
-case__218: case__218
-logic__6426: logic__6426
-logic__1223: logic__1223
-logic__9694: logic__9290
-datapath__4: datapath__4
-datapath__510: datapath__510
-reg__1193: reg__1193
-reg__337: reg__337
-logic__7015: logic__7015
-datapath__548: datapath__548
-case__925: case__925
-logic__7826: logic__7826
-datapath__39: datapath__39
-case__309: case__309
-reg__192: reg__192
-logic__577: logic__577
-reg__781: reg__781
-reg__145: reg__145
-datapath__713: datapath__713
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__32: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__977: logic__977
-datapath__16: datapath__16
-reg__1114: reg__1114
-datapath__534: datapath__534
-case__819: case__819
-case__282: case__282
-logic__3875: logic__3875
-logic__5340: logic__5340
-logic__6657: logic__6657
-logic__1466: logic__1466
-datapath__297: datapath__297
-datapath__463: datapath__463
-logic__4425: logic__4425
-logic__4458: logic__4458
-logic__8852: logic__8852
-datapath__516: datapath__516
-logic__1044: logic__1044
-logic__850: logic__850
-logic__5411: logic__5411
-reg__976: reg__976
-TLInterconnectCoupler_cbus_to_bootrom: TLInterconnectCoupler_cbus_to_bootrom
-logic__4266: logic__4266
-logic__6163: logic__6163
-logic__4772: logic__4772
-reg__1419: reg__1419
-logic__1318: logic__1318
-logic__5479: logic__5479
-case__1640: case__1640
-logic__1474: logic__1474
-logic__8554: logic__8554
-logic__8503: logic__8503
-logic__9647: logic__1531
-logic__2157: logic__2157
-logic__388: logic__388
-reg__1367: reg__1367
-TLBuffer_a32d64s1k1z4u: TLBuffer_a32d64s1k1z4u
-logic__4026: logic__4026
-logic__3496: logic__3496
-reg__740: reg__740
-datapath__491: datapath__491
-logic__4944: logic__4944
-reg__1274: reg__1274
-reg__1254: reg__1254
-logic__9401: logic__3014
-reg__843: reg__843
-logic__7471: logic__7471
-logic__7282: logic__7282
-logic__9806: logic__266
-case__1659: case__1659
-datapath__45: datapath__45
-logic__6234: logic__6234
-case__437: case__437
-reg__633: reg__633
-logic__9714: logic__7665
-logic__4818: logic__4818
-datapath__427: datapath__427
-logic__5400: logic__5400
-logic__2474: logic__2474
-case__124: case__124
-logic__7501: logic__7501
-logic__9573: logic__1711
-logic__2420: logic__2420
-reg__694: reg__694
-case__1748: case__1054
-logic__141: logic__141
-logic__5066: logic__5066
-logic__9607: logic__1619
-reg__775: reg__775
-logic__3248: logic__3248
-logic__2491: logic__2491
-keep__68: keep__7
-datapath__604: datapath__604
-case__501: case__501
-logic__2824: logic__2824
-reg__105: reg__105
-case__1089: case__1089
-logic__9504: logic__1916
-logic__4637: logic__4637
-logic__7099: logic__7099
-reg__328: reg__328
-datapath__498: datapath__498
-datapath__176: datapath__176
-reg__282: reg__282
-case__701: case__701
-logic__6577: logic__6577
-logic__2937: logic__2937
-logic__8932: logic__8932
-reg__45: reg__45
-logic__5408: logic__5408
-logic__4296: logic__4296
-reg__1107: reg__1107
-datapath__291: datapath__291
-logic__6408: logic__6408
-logic__5162: logic__5162
-logic__3753: logic__3753
-logic__4578: logic__4578
-datapath__644: datapath__644
-case__511: case__511
-datapath__54: datapath__54
-logic__946: logic__946
-case__477: case__477
-datapath__356: datapath__356
-logic__6100: logic__6100
-reg__235: reg__235
-case__1168: case__1168
-logic__2423: logic__2423
-case__502: case__502
-case__1385: case__1385
-logic__1723: logic__1723
-logic__9168: logic__9168
-reg__473: reg__473
-case__1523: case__1523
-reg__1489: reg__1144
-logic__658: logic__658
-case__146: case__146
-reg__1281: reg__1281
-logic__6581: logic__6581
-reg__50: reg__50
-reg__759: reg__759
-case__1725: case__312
-reg__1: reg__1
-logic__1558: logic__1558
-logic__6338: logic__6338
-logic__5975: logic__5975
-reg__713: reg__713
-case__661: case__661
-logic__8432: logic__8432
-datapath__515: datapath__515
-case__1297: case__1297
-dsp48e1__20: dsp48e1__20
-logic__4154: logic__4154
-LF_code: LF_code
-logic__9662: logic__669
-logic__8631: logic__8631
-logic__6544: logic__6544
-logic__3784: logic__3784
-datapath__233: datapath__233
-reg__221: reg__221
-datapath__574: datapath__574
-logic__2874: logic__2874
-case__474: case__474
-datapath__32: datapath__32
-case__111: case__111
-dsp48e1__16: dsp48e1__16
-logic__9586: logic__1664
-datapath__354: datapath__354
-logic__9782: logic__502
-muxpart__93: muxpart__93
-logic__4209: logic__4209
-logic__2413: logic__2413
-logic__1521: logic__1521
-logic__2342: logic__2342
-reg__874: reg__874
-reg__1427: reg__1427
-datapath__566: datapath__566
-reg__716: reg__716
-logic__2378: logic__2378
-logic__6806: logic__6806
-OptimizationBarrier_TLBEntryData: OptimizationBarrier_TLBEntryData
-logic__6375: logic__6375
-logic__8495: logic__8495
-reg__750: reg__750
-keep__63: keep__6
-ErrorDeviceWrapper: ErrorDeviceWrapper
-logic__231: logic__231
-logic__2257: logic__2257
-Queue2_TLBundleA_a29d64s2k1z3u__1: Queue2_TLBundleA_a29d64s2k1z3u
-logic__5475: logic__5475
-Queue2_TLBundleD_a29d64s2k1z3u__2: Queue2_TLBundleD_a29d64s2k1z3u
-logic__7989: logic__7989
-reg__240: reg__240
-logic__6543: logic__6543
-reg__794: reg__794
-case__113: case__113
-signinv__3: signinv__1
-reg__1640: reg__154
-reg__1134: reg__1134
-case__530: case__530
-logic__4350: logic__4350
-ram__12: ram__4
-logic__6563: logic__6563
-datapath__200: datapath__200
-logic__3827: logic__3827
-logic__2891: logic__2891
-logic__9599: logic__1637
-logic__6775: logic__6775
-reg__466: reg__466
-case__341: case__341
-logic__7885: logic__7885
-Queue2_TLBundleD_a32d64s1k1z4u__1: Queue2_TLBundleD_a32d64s1k1z4u
-case__3: case__3
-case__1302: case__1302
-case__1047: case__1047
-datapath__707: datapath__707
-logic__8663: logic__8663
-datapath__122: datapath__122
-datapath__259: datapath__259
-logic__2866: logic__2866
-logic__4820: logic__4820
-reg__434: reg__434
-datapath__567: datapath__567
-case__927: case__927
-datapath__726: datapath__726
-logic__4494: logic__4494
-case__1700: case__457
-logic__8821: logic__8821
-datapath__649: datapath__649
-case__1401: case__1401
-case__516: case__516
-reg__1333: reg__1333
-datapath__385: datapath__385
-logic__1390: logic__1390
-logic__4759: logic__4759
-logic__1321: logic__1321
-logic__7445: logic__7445
-logic__156: logic__156
-reg__430: reg__430
-case__861: case__861
-datapath__113: datapath__113
-logic__9516: logic__1890
-logic__2807: logic__2807
-case__991: case__991
-logic__3159: logic__3159
-logic__1064: logic__1064
-logic__5488: logic__5488
-extladd__2: extladd__2
-logic__1872: logic__1872
-keep__21: keep__21
-logic__1559: logic__1559
-case__1651: case__1651
-reg__585: reg__585
-logic__5311: logic__5311
-logic__6432: logic__6432
-reg__1100: reg__1100
-reg__441: reg__441
-logic__6243: logic__6243
-logic__9345: logic__9345
-logic__8580: logic__8580
-logic__2075: logic__2075
-logic__9674: logic__8477
-AsyncResetSynchronizerShiftReg_w1_d3_i0__7: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__9097: logic__9097
-datapath__628: datapath__628
-reg__830: reg__830
-logic__5936: logic__5936
-reg__1572: reg__836
-mult_46_15_61__1: mult_46_15_61
-logic__6768: logic__6768
-logic__1180: logic__1180
-case__943: case__943
-logic__1342: logic__1342
-datapath__608: datapath__608
-logic__3210: logic__3210
-logic__2316: logic__2316
-logic__8829: logic__8829
-datapath__15: datapath__15
-datapath__388: datapath__388
-logic__2703: logic__2703
-logic__1375: logic__1375
-logic__1647: logic__1647
-logic__775: logic__775
-case__327: case__327
-logic__2715: logic__2715
-case__422: case__422
-logic__1084: logic__1084
-logic__8599: logic__8599
-logic__6959: logic__6959
-reg__589: reg__589
-logic__5329: logic__5329
-logic__1455: logic__1455
-case__1003: case__1003
-case__222: case__222
-case__1146: case__1146
-logic__2662: logic__2662
-datapath__12: datapath__12
-reg__211: reg__211
-logic__1803: logic__1803
-reg__69: reg__69
-muxpart__90: muxpart__90
-logic__3003: logic__3003
-logic__9697: logic__7587
-muxpart__46: muxpart__46
-logic__7043: logic__7043
-logic__1293: logic__1293
-logic__812: logic__812
-case__1181: case__1181
-reg__325: reg__325
-logic__901: logic__901
-datapath__377: datapath__377
-case__970: case__970
-case__958: case__958
-case__1432: case__1432
-logic__778: logic__778
-logic__145: logic__145
-datapath__561: datapath__561
-datapath__552: datapath__552
-reg__1231: reg__1231
-logic__3632: logic__3632
-reg__104: reg__104
-logic__214: logic__214
-muxpart__54: muxpart__54
-logic__6655: logic__6655
-TLFragmenter_PLIC: TLFragmenter_PLIC
-logic__9498: logic__1931
-datapath__178: datapath__178
-datapath__672: datapath__672
-logic__72: logic__72
-reg__190: reg__190
-logic__4642: logic__4642
-logic__6221: logic__6221
-logic__2822: logic__2822
-reg__489: reg__489
-muxpart__6: muxpart__6
-logic__4762: logic__4762
-logic__2418: logic__2418
-logic__4853: logic__4853
-case__1715: case__322
-logic__3299: logic__3299
-case__1635: case__1635
-reg__1212: reg__1212
-logic__5319: logic__5319
-logic__1608: logic__1608
-reg__851: reg__851
-logic__976: logic__976
-case__835: case__835
-case__1403: case__1403
-case__290: case__290
-reg__1641: reg__73
-logic__2892: logic__2892
-logic__1185: logic__1185
-logic__4825: logic__4825
-logic__8277: logic__8277
-case__408: case__408
-case__931: case__931
-datapath__360: datapath__360
-datapath__405: datapath__405
-muxpart__11: muxpart__11
-case__381: case__381
-datapath__488: datapath__488
-reg__779: reg__779
-dsp48e1__14: dsp48e1__14
-case__1108: case__1108
-logic__1901: logic__1901
-logic__2615: logic__2615
-logic__2263: logic__2263
-logic__7094: logic__7094
-logic__6592: logic__6592
-logic__2453: logic__2453
-case__1604: case__1604
-case__1553: case__1553
-reg__153: reg__153
-logic__286: logic__286
-logic__6853: logic__6853
-logic__9722: logic__6152
-datapath__688: datapath__688
-logic__1560: logic__1560
-reg__1242: reg__1242
-logic__5414: logic__5414
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__17: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-keep__51: keep__6
-logic__4163: logic__4163
-datapath__312: datapath__312
-reg__986: reg__986
-logic__3486: logic__3486
-logic__5299: logic__5299
-case__202: case__202
-logic__6498: logic__6498
-datapath__482: datapath__482
-case__710: case__710
-reg__229: reg__229
-reg__1668: reg__33
-case__779: case__779
-case__362: case__362
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__18: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__1487: case__1487
-logic__8258: logic__8258
-logic__6773: logic__6773
-reg__365: reg__365
-rockettile_icache_data_arrays_512x32__1: rockettile_icache_data_arrays_512x32
-logic__4448: logic__4448
-logic__6144: logic__6144
-DivSqrtRecFN_small: DivSqrtRecFN_small
-case__445: case__445
-logic__6811: logic__6811
-reg__663: reg__663
-reg__518: reg__518
-logic__792: logic__792
-logic__9593: logic__1649
-reg__1204: reg__1204
-reg__345: reg__345
-logic__13: logic__13
-logic__9620: logic__1590
-logic__4921: logic__4921
-case__8: case__8
-case__646: case__646
-reg__166: reg__166
-datapath__362: datapath__362
-logic__896: logic__896
-case__496: case__496
-case__355: case__355
-logic__2717: logic__2717
-reg__1365: reg__1365
-logic__9437: logic__3948
-logic__3842: logic__3842
-reg__996: reg__996
-case__1767: case__102
-case__663: case__663
-logic__6514: logic__6514
-reg__630: reg__630
-logic__4278: logic__4278
-logic__3890: logic__3890
-case__989: case__989
-logic__475: logic__475
-logic__2811: logic__2811
-logic__1506: logic__1506
-logic__429: logic__429
-logic__9114: logic__9114
-logic__9715: logic__7664
-case__811: case__811
-reg__1639: reg__155
-case__294: case__294
-case__874: case__874
-logic__7744: logic__7744
-logic__6175: logic__6175
-case__1174: case__1174
-logic__4295: logic__4295
-logic__5508: logic__5508
-keep__46: keep__8
-case__1617: case__1617
-logic__5282: logic__5282
-case__1426: case__1426
-logic__3426: logic__3426
-logic__2504: logic__2504
-reg__272: reg__272
-logic__6192: logic__6192
-logic__2415: logic__2415
-logic__2648: logic__2648
-reg__808: reg__808
-case__37: case__37
-logic__4643: logic__4643
-logic__1807: logic__1807
-logic__4554: logic__4554
-datapath__508: datapath__508
-logic__1057: logic__1057
-reg__415: reg__415
-case__1390: case__1390
-logic__3398: logic__3398
-counter__40: counter__22
-datapath__129: datapath__129
-logic__3480: logic__3480
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__2: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__2722: logic__2722
-reg__1470: reg__119
-logic__3025: logic__3025
-reg__767: reg__767
-case__485: case__485
-ifft_abs_sqr: ifft_abs_sqr
-reg__1577: reg__837
-reg__30: reg__30
-logic__4017: logic__4017
-logic__7202: logic__7202
-logic__6804: logic__6804
-logic__5985: logic__5985
-logic__2702: logic__2702
-logic__2948: logic__2948
-reg__697: reg__697
-logic__1917: logic__1917
-logic__7526: logic__7526
-case__1313: case__1313
-logic__4924: logic__4924
-logic__4659: logic__4659
-case__667: case__667
-muxpart__69: muxpart__69
-DCacheDataArray: DCacheDataArray
-reg__676: reg__676
-logic__8692: logic__8692
-reg__1558: reg__838
-logic__6767: logic__6767
-case__234: case__234
-logic__4029: logic__4029
-case__187: case__187
-case__1692: case__466
-logic__2603: logic__2603
-logic__6505: logic__6505
-logic__4198: logic__4198
-logic__4267: logic__4267
-logic__515: logic__515
-logic__9777: logic__516
-case__517: case__517
-logic__5300: logic__5300
-case__313: case__313
-case__705: case__705
-logic__1007: logic__1007
-logic__4657: logic__4657
-reg__93: reg__93
-logic__9779: logic__512
-logic__6778: logic__6778
-logic__4819: logic__4819
-case__944: case__944
-logic__6137: logic__6137
-logic__5393: logic__5393
-logic__8431: logic__8431
-logic__491: logic__491
-datapath__303: datapath__303
-logic__9270: logic__9270
-datapath__240: datapath__240
-logic__1684: logic__1684
-datapath__686: datapath__686
-logic__5656: logic__5656
-logic__2392: logic__2392
-logic__1719: logic__1719
-logic__3818: logic__3818
-logic__5717: logic__5717
-case__1169: case__1169
-logic__3879: logic__3879
-logic__2457: logic__2457
-reg__939: reg__939
-logic__131: logic__131
-reg__565: reg__565
-logic__7672: logic__7672
-case__1687: case__1687
-logic__4996: logic__4996
-logic__8660: logic__8660
-reg__239: reg__239
-reg__129: reg__129
-logic__1532: logic__1532
-logic__7219: logic__7219
-reg__418: reg__418
-reg__405: reg__405
-reg__732: reg__732
-reg__1524: reg__995
-reg__1094: reg__1094
-reg__495: reg__495
-logic__2205: logic__2205
-logic__3723: logic__3723
-logic__3028: logic__3028
-logic__9628: logic__1572
-reg__1263: reg__1263
-case__965: case__965
-case__264: case__264
-case__1310: case__1310
-case__771: case__771
-logic__3543: logic__3543
-logic__1188: logic__1188
-case__375: case__375
-logic__6209: logic__6209
-logic__566: logic__566
-case__1098: case__1098
-datapath__18: datapath__18
-logic__400: logic__400
-case__573: case__573
-logic__2716: logic__2716
-case__1752: case__1050
-datapath__323: datapath__323
-logic__484: logic__484
-reg__956: reg__956
-case__1392: case__1392
-case__682: case__682
-logic__8501: logic__8501
-logic__2293: logic__2293
-logic__6477: logic__6477
-logic__5354: logic__5354
-logic__7446: logic__7446
-reg__888: reg__888
-case__1042: case__1042
-logic__9637: logic__1551
-counter__18: counter__18
-case__1049: case__1049
-logic__235: logic__235
-logic__3932: logic__3932
-logic__2649: logic__2649
-datapath__3: datapath__3
-reg__635: reg__635
-logic__6686: logic__6686
-logic__6445: logic__6445
-logic__695: logic__695
-reg__1413: reg__1413
-case__156: case__156
-keep__42: keep__42
-reg__873: reg__873
-logic__9776: logic__517
-reg__1184: reg__1184
-logic__2875: logic__2875
-logic__5317: logic__5317
-keep__45: keep__6
-logic__6802: logic__6802
-case__92: case__92
-reg__340: reg__340
-logic__3755: logic__3755
-logic__3870: logic__3870
-logic__2639: logic__2639
-case__1512: case__1512
-logic__9646: logic__1532
-logic__6179: logic__6179
-logic__2839: logic__2839
-case__1489: case__1489
-reg__1481: reg__1250
-logic__6940: logic__6940
-reg__1429: reg__1429
-reg__1273: reg__1273
-reg__667: reg__667
-reg__682: reg__682
-case__9: case__9
-logic__2200: logic__2200
-datapath__348: datapath__348
-datapath__774: datapath__654
-logic__9700: logic__7584
-muxpart__306: muxpart__306
-rom__8: rom__8
-logic__3558: logic__3558
-TLBuffer_a32d64s2k1z3u_1: TLBuffer_a32d64s2k1z3u_1
-logic__4116: logic__4116
-logic__7138: logic__7138
-logic__6356: logic__6356
-logic__6245: logic__6245
-logic__9541: logic__1818
-logic__359: logic__359
-datapath__755: datapath__245
-case__1469: case__1469
-reg__1337: reg__1337
-logic__4311: logic__4311
-reg__338: reg__338
-logic__6731: logic__6731
-logic__1117: logic__1117
-case__371: case__371
-logic__3878: logic__3878
-logic__2465: logic__2465
-logic__8477: logic__8477
-logic__6762: logic__6762
-datapath__520: datapath__520
-logic__6576: logic__6576
-logic__2636: logic__2636
-reg__1030: reg__1030
-logic__6788: logic__6788
-logic__9299: logic__9299
-datapath__778: datapath__650
-reg__735: reg__735
-logic__5176: logic__5176
-logic__4707: logic__4707
-logic__2384: logic__2384
-logic__5431: logic__5431
-logic__7718: logic__7718
-case__1603: case__1603
-logic__2815: logic__2815
-reg__613: reg__613
-reg__149: reg__149
-logic__8266: logic__8266
-cordic_angle_lut__parameterized0__1: cordic_angle_lut__parameterized0
-logic__6042: logic__6042
-logic__2513: logic__2513
-logic__8588: logic__8588
-muxpart__33: muxpart__33
-case__777: case__777
-logic__1498: logic__1498
-logic__255: logic__255
-datapath__220: datapath__220
-reg__835: reg__835
-logic__9743: logic__965
-datapath__20: datapath__20
-datapath__38: datapath__38
-logic__4112: logic__4112
-logic__5063: logic__5063
-case__2: case__2
-reg__1363: reg__1363
-TLDebugModule: TLDebugModule
-case__561: case__561
-logic__105: logic__105
-reg__1077: reg__1077
-logic__7966: logic__7966
-logic__6584: logic__6584
-reg__498: reg__498
-case__1383: case__1383
-logic__6439: logic__6439
-case__1001: case__1001
-logic__687: logic__687
-logic__1844: logic__1844
-reg__810: reg__810
-logic__8395: logic__8395
-case__1486: case__1486
-case__850: case__850
-muxpart__29: muxpart__29
-cdc_fifo_gray_dst: cdc_fifo_gray_dst
-datapath__380: datapath__380
-AsyncValidSync__1: AsyncValidSync
-case__50: case__50
-reg__253: reg__253
-ram__1: ram__1
-case__564: case__564
-case__1010: case__1010
-logic__7416: logic__7416
-logic__9330: logic__9330
-logic__8774: logic__8774
-logic__2286: logic__2286
-logic__6271: logic__6271
-logic__7904: logic__7904
-datapath__370: datapath__370
-logic__7583: logic__7583
-logic__135: logic__135
-logic__4743: logic__4743
-LevelGateway__3: LevelGateway
-reg__609: reg__609
-logic__5492: logic__5492
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__18: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-datapath__801: datapath__20
-datapath__540: datapath__540
-case__435: case__435
-case__628: case__628
-datapath__302: datapath__302
-logic__1300: logic__1300
-logic__4847: logic__4847
-TLWidthWidget8_1__1: TLWidthWidget8_1
-case__1295: case__1295
-datapath__678: datapath__678
-case__1299: case__1299
-addsub__1: addsub__1
-logic__2889: logic__2889
-reg__598: reg__598
-logic__9759: logic__497
-case__118: case__118
-reg__632: reg__632
-reg__1317: reg__1317
-reg__914: reg__914
-AsyncResetSynchronizerShiftReg_w1_d3_i0__10: AsyncResetSynchronizerShiftReg_w1_d3_i0
-case__531: case__531
-case__792: case__792
-datapath__27: datapath__27
-logic__2176: logic__2176
-logic__9704: logic__7690
-logic__1421: logic__1421
-reg__51: reg__51
-logic__5655: logic__5655
-logic__2557: logic__2557
-reg__18: reg__18
-logic__7807: logic__7807
-reg__437: reg__437
-datapath__324: datapath__324
-logic__6530: logic__6530
-logic__3797: logic__3797
-case__288: case__288
-logic__8414: logic__8414
-logic__3295: logic__3295
-case__995: case__995
-case__1690: case__1690
-logic__4928: logic__4928
-case__1043: case__1043
-logic__2359: logic__2359
-case__1173: case__1173
-case__38: case__38
-datapath__670: datapath__670
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__19: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__76: case__76
-case__535: case__535
-datapath__767: datapath__115
-logic__138: logic__138
-reg__1121: reg__1121
-datapath__549: datapath__549
-logic__2081: logic__2081
-logic__1881: logic__1881
-logic__5330: logic__5330
-case__822: case__822
-TLBuffer_a14d64s2k1z4u: TLBuffer_a14d64s2k1z4u
-logic__1962: logic__1962
-case__547: case__547
-logic__2916: logic__2916
-case__1493: case__1493
-reg__812: reg__812
-logic__7816: logic__7816
-case__527: case__527
-case__188: case__188
-reg__1326: reg__1326
-logic__848: logic__848
-logic__713: logic__713
-reg__1345: reg__1345
-reg__560: reg__560
-FPGASPIClockSinkDomain: FPGASPIClockSinkDomain
-logic__1999: logic__1999
-MulAddRecFNToRaw_postMul: MulAddRecFNToRaw_postMul
-reg__172: reg__172
-case__684: case__684
-logic__6953: logic__6953
-counter__19: counter__19
-logic__2469: logic__2469
-logic__2998: logic__2998
-datapath__436: datapath__436
-logic__2551: logic__2551
-logic__4201: logic__4201
-datapath__685: datapath__685
-case__399: case__399
-logic__6316: logic__6316
-logic__936: logic__936
-logic__9346: logic__9346
-logic__8595: logic__8595
-case__683: case__683
-reg__231: reg__231
-logic__4230: logic__4230
-case__1758: case__111
-case__1360: case__1360
-logic__8902: logic__8902
-logic__543: logic__543
-reg__460: reg__460
-datapath__42: datapath__42
-case__648: case__648
-logic__236: logic__236
-reg__1339: reg__1339
-reg__1173: reg__1173
-case__1721: case__316
-DivSqrtRecFN_small_1: DivSqrtRecFN_small_1
-case__566: case__566
-logic__117: logic__117
-logic__8980: logic__8980
-reg__474: reg__474
-case__293: case__293
-datapath__156: datapath__156
-case__432: case__432
-reg__966: reg__966
-logic__4785: logic__4785
-reg__824: reg__824
-dsp48e1__35: dsp48e1__35
-reg__1344: reg__1344
-logic__7444: logic__7444
-case__888: case__888
-case__252: case__252
-logic__4748: logic__4748
-logic__9546: logic__1802
-reg__1461: reg__22
-datapath__712: datapath__712
-logic__251: logic__251
-logic__9713: logic__7669
-case__239: case__239
-logic__3787: logic__3787
-LevelGateway__1: LevelGateway
-reg__109: reg__109
-logic__1459: logic__1459
-case__1428: case__1428
-reg__237: reg__237
-logic__8409: logic__8409
-logic__8550: logic__8550
-case__1002: case__1002
-logic__9727: logic__6147
-logic__386: logic__386
-logic__9117: logic__9117
-datapath__387: datapath__387
-logic__2432: logic__2432
-logic__6812: logic__6812
-case__1301: case__1301
-reg__1073: reg__1073
-logic__4796: logic__4796
-reg__1503: reg__999
-logic__2128: logic__2128
-logic__396: logic__396
-case__492: case__492
-reg__770: reg__770
-reg__719: reg__719
-logic__7702: logic__7702
-logic__6379: logic__6379
-reg__1191: reg__1191
-logic__5236: logic__5236
-logic__5206: logic__5206
-logic__6214: logic__6214
-datapath__791: datapath__136
-logic__7709: logic__7709
-logic__4334: logic__4334
-logic__822: logic__822
-case__115: case__115
-logic__8587: logic__8587
-reg__664: reg__664
-logic__3852: logic__3852
-datapath__710: datapath__710
-case__106: case__106
-logic__8608: logic__8608
-logic__8310: logic__8310
-case__548: case__548
-logic__5080: logic__5080
-logic__6524: logic__6524
-sync__6: sync
-logic__4473: logic__4473
-logic__9237: logic__9237
-case__971: case__971
-case__1329: case__1329
-reg__154: reg__154
-reg__275: reg__275
-reg__349: reg__349
-logic__7569: logic__7569
-reg__333: reg__333
-case__877: case__877
-datapath__536: datapath__536
-reg__392: reg__392
-reg__961: reg__961
-logic__4572: logic__4572
-DivSqrtRecFNToRaw_small: DivSqrtRecFNToRaw_small
-logic__4711: logic__4711
-logic__2724: logic__2724
-case__1399: case__1399
-logic__7264: logic__7264
-TLROM: TLROM
-datapath__769: datapath__113
-logic__7559: logic__7559
-logic__3520: logic__3520
-logic__3776: logic__3776
-logic__1158: logic__1158
-reg__1053: reg__1053
-case__666: case__666
-reg__877: reg__877
-datapath__89: datapath__89
-case__803: case__803
-reg__1468: reg__121
-reg__634: reg__634
-logic__4650: logic__4650
-muxpart__21: muxpart__21
-reg__264: reg__264
-logic__9414: logic__2992
-logic__9441: logic__3939
-case__1342: case__1342
-case__1287: case__1287
-logic__3311: logic__3311
-reg__528: reg__528
-logic__6444: logic__6444
-logic__3451: logic__3451
-reg__1215: reg__1215
-case__1751: case__1051
-logic__9687: logic__8271
-logic__3181: logic__3181
-logic__4066: logic__4066
-case__800: case__800
-case__232: case__232
-logic__959: logic__959
-logic__6228: logic__6228
-logic__4695: logic__4695
-logic__5246: logic__5246
-muxpart__99: muxpart__99
-logic__3969: logic__3969
-case__534: case__534
-logic__5978: logic__5978
-logic__4370: logic__4370
-reg__1241: reg__1241
-case__317: case__317
-logic__4803: logic__4803
-logic__4152: logic__4152
-case__1704: case__531
-logic__7298: logic__7298
-case__545: case__545
-logic__9298: logic__9298
-datapath__490: datapath__490
-datapath__793: datapath__97
-logic__5932: logic__5932
-reg__1506: reg__836
-logic__9566: logic__1736
-reg__712: reg__712
-logic__2953: logic__2953
-reg__226: reg__226
-logic__750: logic__750
-case__100: case__100
-logic__1469: logic__1469
-logic__4498: logic__4498
-logic__5220: logic__5220
-logic__1812: logic__1812
-reg__1165: reg__1165
-case__229: case__229
-reg__1485: reg__1144
-LF_carr: LF_carr
-logic__7579: logic__7579
-logic__352: logic__352
-datapath__660: datapath__660
-logic__1392: logic__1392
-logic__6521: logic__6521
-datapath__61: datapath__61
-reg__1492: reg__1001
-datapath__185: datapath__185
-datapath__41: datapath__41
-logic__7157: logic__7157
-logic__9747: logic__527
-ram_2x77__4: ram_2x77
-logic__4860: logic__4860
-case__1445: case__1445
-reg__232: reg__232
-case__744: case__744
-logic__5219: logic__5219
-case__1410: case__1410
-reg__558: reg__558
-logic__6813: logic__6813
-reg__34: reg__34
-logic__140: logic__140
-logic__5397: logic__5397
-datapath__307: datapath__307
-reg__509: reg__509
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__25: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__847: logic__847
-logic__649: logic__649
-reg__771: reg__771
-logic__230: logic__230
-logic__3759: logic__3759
-logic__9683: logic__8271
-case__319: case__319
-case__552: case__552
-datapath__62: datapath__62
-rockettile_dcache_data_arrays_0_131072x64: rockettile_dcache_data_arrays_0_131072x64
-logic__7130: logic__7130
-logic__118: logic__118
-logic__5944: logic__5944
-logic__3542: logic__3542
-case__1738: case__1414
-addsub__9: addsub__4
-case__1372: case__1372
-reg__693: reg__693
-logic__9163: logic__9163
-logic__1899: logic__1899
-logic__785: logic__785
-logic__9391: logic__3052
-logic__834: logic__834
-logic__282: logic__282
-logic__2486: logic__2486
-logic__3636: logic__3636
-logic__8057: logic__8057
-logic__4658: logic__4658
-logic__9351: logic__9351
-case__992: case__992
-logic__4082: logic__4082
-logic__940: logic__940
-logic__2416: logic__2416
-reg__709: reg__709
-reg__71: reg__71
-reg__836: reg__836
-logic__8937: logic__8937
-logic__1240: logic__1240
-logic__844: logic__844
-Queue2_TLBundleD_a32d64s1k1z4u: Queue2_TLBundleD_a32d64s1k1z4u
-TLXbar_dmixbar_i1_o2_a9d32s1k1z2u: TLXbar_dmixbar_i1_o2_a9d32s1k1z2u
-reg__1213: reg__1213
-logic__3951: logic__3951
-logic__3010: logic__3010
-case__1417: case__1417
-case__875: case__875
-logic__164: logic__164
-logic__1038: logic__1038
-case__1338: case__1338
-reg__943: reg__943
-logic__4882: logic__4882
-logic__5177: logic__5177
-keep__28: keep__28
-reg__551: reg__551
-logic__450: logic__450
-logic__1539: logic__1539
-reg__683: reg__683
-logic__6458: logic__6458
-dsp48e1__46: dsp48e1__46
-logic__6779: logic__6779
-datapath__603: datapath__603
-logic__6710: logic__6710
-logic__1080: logic__1080
-muxpart__227: muxpart__227
-logic__8502: logic__8502
-logic__5691: logic__5691
-logic__1268: logic__1268
-keep__44: keep__7
-case__256: case__256
-logic__3300: logic__3300
-reg__821: reg__821
-case__1639: case__1639
-logic__2860: logic__2860
-logic__8719: logic__8719
-logic__6435: logic__6435
-logic__5493: logic__5493
-logic__4696: logic__4696
-logic__6683: logic__6683
-logic__9791: logic__484
-logic__8693: logic__8693
-twiddle_ram__1: twiddle_ram
-logic__4870: logic__4870
-reg__1240: reg__1240
-case__536: case__536
-reg__665: reg__665
-logic__3011: logic__3011
-reg__1471: reg__118
-logic__3377: logic__3377
-logic__9427: logic__3972
-logic__4995: logic__4995
-logic__8659: logic__8659
-reg__458: reg__458
-logic__8083: logic__8083
-logic__4061: logic__4061
-muxpart__149: muxpart__149
-logic__7567: logic__7567
-logic__1259: logic__1259
-logic__1696: logic__1696
-logic__9752: logic__516
-logic__4407: logic__4407
-logic__1977: logic__1977
-case__1439: case__1439
-case__1433: case__1433
-case__719: case__719
-logic__2273: logic__2273
-case__5: case__5
-datapath__789: datapath__138
-logic__4806: logic__4806
-reg__1570: reg__838
-logic__6130: logic__6130
-reg__220: reg__220
-logic__2388: logic__2388
-reg__309: reg__309
-logic__6846: logic__6846
-Repeater_TLBundleA_a12d64s2k1z3u: Repeater_TLBundleA_a12d64s2k1z3u
-reg__31: reg__31
-logic__4802: logic__4802
-datapath__662: datapath__662
-reg__1455: reg__1455
-logic__4363: logic__4363
-logic__2738: logic__2738
-datapath__328: datapath__328
-reg__1058: reg__1058
-logic__3778: logic__3778
-logic__259: logic__259
-reg__395: reg__395
-binary_to_gray__1: binary_to_gray
-logic__9629: logic__1569
-logic__6774: logic__6774
-datapath__568: datapath__568
-extram__4: extram__4
-logic__2029: logic__2029
-logic__4813: logic__4813
-logic__9708: logic__7676
-logic__1557: logic__1557
-logic__9362: logic__9362
-logic__5250: logic__5250
-reg__1590: reg__836
-logic__782: logic__782
-reg__1078: reg__1078
-reg__1508: reg__837
-case__1511: case__1511
-logic__4359: logic__4359
-logic__2699: logic__2699
-datapath__326: datapath__326
-logic__6735: logic__6735
-logic__1098: logic__1098
-logic__3635: logic__3635
-logic__9621: logic__1587
-logic__7231: logic__7231
-logic__1174: logic__1174
-logic__9730: logic__6152
-muxpart__28: muxpart__28
-LevelGateway: LevelGateway
-case__213: case__213
-Arbiter4_DCacheDataReq: Arbiter4_DCacheDataReq
-logic__9507: logic__1901
-logic__7600: logic__7600
-logic__4783: logic__4783
-logic__7620: logic__7620
-datapath__596: datapath__596
-reg__214: reg__214
-logic__1528: logic__1528
-logic__6991: logic__6991
-case__312: case__312
-logic__3849: logic__3849
-logic__9392: logic__3036
-reg__72: reg__72
-reg__1338: reg__1338
-reg__1300: reg__1300
-case__699: case__699
-logic__8746: logic__8746
-logic__2484: logic__2484
-ShiftQueue: ShiftQueue
-reg__246: reg__246
-reg__921: reg__921
-datapath__11: datapath__11
-counter__27: counter__27
-logic__1981: logic__1981
-case__471: case__471
-logic__2059: logic__2059
-reg__897: reg__897
-logic__9802: logic__273
-case__1307: case__1307
-logic__7003: logic__7003
-logic__9137: logic__9137
-reg__960: reg__960
-datapath__450: datapath__450
-logic__2732: logic__2732
-logic__5404: logic__5404
-case__391: case__391
-datapath__204: datapath__204
-logic__3853: logic__3853
-keep__47: keep__7
-logic__7419: logic__7419
-case__1541: case__1541
-case__1389: case__1389
-logic__6335: logic__6335
-datapath__581: datapath__581
-logic__978: logic__978
-logic__8207: logic__8207
-case__1239: case__1239
-logic__5526: logic__5526
-logic__2320: logic__2320
-logic__9518: logic__1881
-logic__6594: logic__6594
-logic__889: logic__889
-datapath__794: datapath__96
-case__973: case__973
-logic__7111: logic__7111
-case__1680: case__1680
-reg__1188: reg__1188
-case__1448: case__1448
-logic__9705: logic__7687
-ICache: ICache
-logic__2647: logic__2647
-logic__8720: logic__8720
-logic__1343: logic__1343
-muxpart__85: muxpart__85
-logic__1540: logic__1540
-case__658: case__658
-logic__6423: logic__6423
-reg__1139: reg__1139
-TLInterconnectCoupler_pbus_to_gps: TLInterconnectCoupler_pbus_to_gps
-logic__1021: logic__1021
-logic__633: logic__633
-logic__9291: logic__9291
-keep__49: keep__8
-logic__4389: logic__4389
-logic__3366: logic__3366
-Queue1_RegMapperInput_i9_m8: Queue1_RegMapperInput_i9_m8
-logic__2711: logic__2711
-logic__3665: logic__3665
-logic__3793: logic__3793
-datapath__573: datapath__573
-logic__2310: logic__2310
-case__642: case__642
-logic__887: logic__887
-reg__1120: reg__1120
-case__696: case__696
-reg__289: reg__289
-logic__6180: logic__6180
-case__73: case__73
-reg__15: reg__15
-logic__7208: logic__7208
-logic__613: logic__613
-logic__7572: logic__7572
-reg__982: reg__982
-reg__113: reg__113
-logic__8446: logic__8446
-reg__1661: reg__64
-datapath__231: datapath__231
-logic__2888: logic__2888
-logic__8399: logic__8399
-logic__664: logic__664
-logic__4058: logic__4058
-logic__3796: logic__3796
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__5: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-PMPChecker_s3: PMPChecker_s3
-case__1197: case__1197
-logic__5341: logic__5341
-case__1464: case__1464
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__9: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__30: case__30
-logic__2919: logic__2919
-logic__7568: logic__7568
-logic__6120: logic__6120
-logic__567: logic__567
-reg__391: reg__391
-reg__1423: reg__1423
-logic__1517: logic__1517
-reg__1412: reg__1412
-reg__55: reg__55
-reg__1351: reg__1351
-reg__248: reg__248
-reg__628: reg__628
-logic__4127: logic__4127
-logic__4292: logic__4292
-logic__7271: logic__7271
-case__388: case__388
-logic__6732: logic__6732
-logic__6367: logic__6367
-logic__8054: logic__8054
-datapath__381: datapath__381
-datapath__138: datapath__138
-logic__6665: logic__6665
-logic__348: logic__348
-logic__8802: logic__8802
-logic__7004: logic__7004
-logic__6658: logic__6658
-logic__3554: logic__3554
-case__1289: case__1289
-datapath__693: datapath__693
-reg__1618: reg__838
-datapath__137: datapath__137
-case__1736: case__1416
-reg__469: reg__469
-IntXbar_i2_o1: IntXbar_i2_o1
-logic__8921: logic__8921
-logic__4630: logic__4630
-logic__8251: logic__8251
-logic__9386: logic__9386
-logic__6566: logic__6566
-counter__4: counter__4
-logic__4852: logic__4852
-case__1737: case__1415
-logic__2939: logic__2939
-logic__1965: logic__1965
-logic__6390: logic__6390
-case__818: case__818
-logic__5525: logic__5525
-plusarg_reader: plusarg_reader
-logic__6672: logic__6672
-case__1308: case__1308
-case__1291: case__1291
-logic__8398: logic__8398
-reg__1658: reg__67
-logic__8271: logic__8271
-reg__1355: reg__1355
-logic__8914: logic__8914
-datapath__191: datapath__191
-datapath__95: datapath__95
-case__1394: case__1394
-case__1243: case__1243
-reg__1037: reg__1037
-case__751: case__751
-reg__639: reg__639
-reg__1031: reg__1031
-logic__4412: logic__4412
-reg__408: reg__408
-logic__1215: logic__1215
-logic__6226: logic__6226
-case__128: case__128
-reg__327: reg__327
-logic__9676: logic__8473
-reg__736: reg__736
-logic__6816: logic__6816
-Repeater_TLBundleD_a32d64s1k1z4u: Repeater_TLBundleD_a32d64s1k1z4u
-case__328: case__328
-datapath__96: datapath__96
-logic__6798: logic__6798
-reg__1195: reg__1195
-logic__8071: logic__8071
-keep__32: keep__32
-logic__9347: logic__9347
-reg__506: reg__506
-logic__5913: logic__5913
-logic__4090: logic__4090
-logic__1193: logic__1193
-datapath__365: datapath__365
-datapath__99: datapath__99
-reg__1142: reg__1142
-reg__387: reg__387
-logic__9383: logic__9383
-logic__6976: logic__6976
-logic__6560: logic__6560
-datapath__443: datapath__443
-case__108: case__108
-logic__4149: logic__4149
-datapath__692: datapath__692
-datapath__378: datapath__378
-datapath__421: datapath__421
-logic__8789: logic__8789
-case__685: case__685
-case__1676: case__1676
-case__413: case__413
-case__1017: case__1017
-case__1032: case__1032
-logic__264: logic__264
-reg__1024: reg__1024
-logic__1330: logic__1330
-logic__4997: logic__4997
-logic__4463: logic__4463
-case__926: case__926
-case__1695: case__462
-logic__8418: logic__8418
-logic__9565: logic__1739
-reg__1608: reg__836
-logic__9432: logic__3957
-logic__2613: logic__2613
-logic__9711: logic__7671
-case__259: case__259
-code_loop_discriminator: code_loop_discriminator
-logic__890: logic__890
-reg__476: reg__476
-case__1225: case__1225
-logic__6061: logic__6061
-logic__9520: logic__1875
-logic__8428: logic__8428
-logic__6463: logic__6463
-double_ff_syn__3: double_ff_syn
-logic__7665: logic__7665
-logic__6736: logic__6736
-case__233: case__233
-case__208: case__208
-logic__2683: logic__2683
-dsp48e1__31: dsp48e1__31
-logic__1346: logic__1346
-Queue2_TLBundleD_a32d64s2k1z4u: Queue2_TLBundleD_a32d64s2k1z4u
-case__311: case__311
-logic__6449: logic__6449
-case__1337: case__1337
-logic__7546: logic__7546
-logic__5417: logic__5417
-TLInterconnectCoupler_cbus_to_clint: TLInterconnectCoupler_cbus_to_clint
-logic__6114: logic__6114
-reg__442: reg__442
-datapath__511: datapath__511
-case__1729: case__1423
-case__1699: case__458
-case__396: case__396
-logic__3250: logic__3250
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__1: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__6391: logic__6391
-logic__220: logic__220
-datapath__787: datapath__515
-logic__102: logic__102
-logic__8280: logic__8280
-logic__9519: logic__1878
-logic__9240: logic__9240
-logic__5368: logic__5368
-reg__822: reg__822
-reg__1408: reg__1408
-datapath__690: datapath__690
-logic__2149: logic__2149
-logic__6229: logic__6229
-datapath__101: datapath__101
-datapath__503: datapath__503
-datapath__199: datapath__199
-AsyncValidSync__22: AsyncValidSync
-reg__714: reg__714
-logic__5433: logic__5433
-reg__669: reg__669
-logic__9762: logic__492
-RoundAnyRawFNToRecFN: RoundAnyRawFNToRecFN
-logic__7399: logic__7399
-logic__401: logic__401
-logic__1961: logic__1961
-reg__1105: reg__1105
-logic__1361: logic__1361
-reg__967: reg__967
-case__1058: case__1058
-datapath__43: datapath__43
-logic__9695: logic__9290
-logic__2861: logic__2861
-case__724: case__724
-case__245: case__245
-TLWidthWidget8: TLWidthWidget8
-logic__7100: logic__7100
-reg__384: reg__384
-reg__1247: reg__1247
-case__932: case__932
-logic__5451: logic__5451
-logic__8447: logic__8447
-case__834: case__834
-reg__1334: reg__1334
-datapath__797: datapath__97
-logic__3718: logic__3718
-case__168: case__168
-logic__9457: logic__3893
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__23: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-muxpart__208: muxpart__208
-logic__7288: logic__7288
-muxpart__22: muxpart__22
-logic__1736: logic__1736
-reg__998: reg__998
-logic__7497: logic__7497
-logic__9764: logic__490
-reg__1290: reg__1290
-logic__941: logic__941
-case__1545: case__1545
-reg__260: reg__260
-logic__2280: logic__2280
-reg__1271: reg__1271
-reg__569: reg__569
-case__1133: case__1133
-logic__6666: logic__6666
-logic__9181: logic__9181
-TLFragmenter_FPGAUART__2: TLFragmenter_FPGAUART
-logic__1984: logic__1984
-case__136: case__136
-logic__4160: logic__4160
-logic__6786: logic__6786
-reg__1518: reg__836
-logic__6770: logic__6770
-datapath__452: datapath__452
-reg__1122: reg__1122
-logic__4844: logic__4844
-logic__5366: logic__5366
-reg__703: reg__703
-logic__6772: logic__6772
-logic__5972: logic__5972
-logic__6401: logic__6401
-logic__3783: logic__3783
-datapath__645: datapath__645
-reg__249: reg__249
-case__1359: case__1359
-AsyncValidSync__14: AsyncValidSync
-reg__1444: reg__1444
-logic__2514: logic__2514
-logic__681: logic__681
-logic__3801: logic__3801
-datapath__663: datapath__663
-logic__2309: logic__2309
-logic__9751: logic__517
-logic__190: logic__190
-datapath__298: datapath__298
-case__204: case__204
-reg__710: reg__710
-logic__8718: logic__8718
-reg__1069: reg__1069
-logic__5555: logic__5555
-logic__6344: logic__6344
-logic__3567: logic__3567
-reg__1473: reg__116
-datapath__704: datapath__704
-TLAsyncCrossingSink_a9d32s1k1z2u: TLAsyncCrossingSink_a9d32s1k1z2u
-datapath__30: datapath__30
-case__429: case__429
-logic__3700: logic__3700
-logic__6511: logic__6511
-logic__9433: logic__3956
-keep__40: keep__40
-reg__494: reg__494
-logic__266: logic__266
-logic__4301: logic__4301
-logic__5096: logic__5096
-logic__653: logic__653
-case__1106: case__1106
-logic__3792: logic__3792
-logic__6500: logic__6500
-reg__625: reg__625
-logic__1764: logic__1764
-reg__421: reg__421
-datapath__218: datapath__218
-case__231: case__231
-datapath__132: datapath__132
-case__34: case__34
-reg__1201: reg__1201
-logic__3541: logic__3541
-datapath__420: datapath__420
-logic__6206: logic__6206
-TLBuffer_a29d64s2k1z3u: TLBuffer_a29d64s2k1z3u
-logic__9377: logic__9377
-case__1172: case__1172
-extram__5: extram__5
-datapath__696: datapath__696
-logic__9611: logic__1611
-logic__3697: logic__3697
-logic__9423: logic__3996
-reg__91: reg__91
-logic__2727: logic__2727
-logic__6704: logic__6704
-logic__9439: logic__3944
-muxpart__7: muxpart__7
-logic__3758: logic__3758
-logic__5471: logic__5471
-logic__4718: logic__4718
-logic__9564: logic__1742
-reg__1606: reg__838
-reg__1529: reg__975
-logic__3952: logic__3952
-logic__3575: logic__3575
-logic__5171: logic__5171
-datapath__310: datapath__310
-keep__41: keep__41
-datapath__313: datapath__313
-case__880: case__880
-logic__770: logic__770
-logic__2407: logic__2407
-logic__702: logic__702
-logic__3802: logic__3802
-logic__7277: logic__7277
-logic__8419: logic__8419
-AsyncResetSynchronizerShiftReg_w1_d3_i0__3: AsyncResetSynchronizerShiftReg_w1_d3_i0
-dsp48e1__26: dsp48e1__26
-TLWidthWidget8_1: TLWidthWidget8_1
-case__1434: case__1434
-case__1663: case__1663
-logic__9490: logic__1962
-logic__4445: logic__4445
-logic__8256: logic__8256
-logic__6220: logic__6220
-reg__905: reg__905
-datapath__702: datapath__702
-logic__4961: logic__4961
-logic__3715: logic__3715
-reg__1509: reg__836
-logic__4751: logic__4751
-logic__1551: logic__1551
-logic__7578: logic__7578
-reg__1435: reg__1435
-reg__1057: reg__1057
-logic__2612: logic__2612
-reg__968: reg__968
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__31: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__9689: logic__8273
-logic__6339: logic__6339
-reg__764: reg__764
-reg__432: reg__432
-logic__1035: logic__1035
-logic__439: logic__439
-case__1143: case__1143
-datapath__640: datapath__640
-datapath__256: datapath__256
-datapath__228: datapath__228
-datapath__397: datapath__397
-reg__1179: reg__1179
-case__506: case__506
-reg: reg
-datapath__141: datapath__141
-datapath__585: datapath__585
-logic__1664: logic__1664
-datapath__731: datapath__731
-logic__3696: logic__3696
-reg__530: reg__530
-reg__1106: reg__1106
-case__774: case__774
-datapath__661: datapath__661
-logic__2882: logic__2882
-reg__1533: reg__836
-logic__3779: logic__3779
-keep__72: keep__1
-reg__1541: reg__837
-logic__6164: logic__6164
-logic__4584: logic__4584
-logic__8408: logic__8408
-logic__6140: logic__6140
-mult_53_53_106: mult_53_53_106
-reg__1545: reg__836
-logic__7426: logic__7426
-case__397: case__397
-case__1102: case__1102
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__22: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__80: case__80
-case__793: case__793
-reg__1084: reg__1084
-datapath__311: datapath__311
-logic__7564: logic__7564
-logic__8076: logic__8076
-logic__1583: logic__1583
-reg__1580: reg__837
-logic__1149: logic__1149
-logic__589: logic__589
-logic__8051: logic__8051
-reg__590: reg__590
-logic__8803: logic__8803
-logic__2884: logic__2884
-logic__5929: logic__5929
-reg__283: reg__283
-datapath__636: datapath__636
-logic__4449: logic__4449
-logic__223: logic__223
-logic__4495: logic__4495
-case__652: case__652
-reg__131: reg__131
-reg__65: reg__65
-reg__674: reg__674
-logic__4369: logic__4369
-logic__8347: logic__8347
-logic__1569: logic__1569
-logic__620: logic__620
-logic__1605: logic__1605
-logic__5896: logic__5896
-logic__233: logic__233
-logic__700: logic__700
-datapath__665: datapath__665
-logic__6678: logic__6678
-logic__353: logic__353
-reg__215: reg__215
-logic__1542: logic__1542
-logic__6348: logic__6348
-logic__3957: logic__3957
-reg__377: reg__377
-reg__611: reg__611
-case__77: case__77
-logic__8896: logic__8896
-FPUFMAPipe_l4_f64: FPUFMAPipe_l4_f64
-logic__6697: logic__6697
-case__730: case__730
-case__1671: case__1671
-logic__9606: logic__1622
-TLInterconnectCoupler_cbus_to_debug: TLInterconnectCoupler_cbus_to_debug
-case__1701: case__535
-muxpart__65: muxpart__65
-logic__3807: logic__3807
-logic__6627: logic__6627
-logic__7117: logic__7117
-logic__6909: logic__6909
-reg__367: reg__367
-reg__257: reg__257
-datapath__773: datapath__655
-logic__3080: logic__3080
-case__791: case__791
-case__704: case__704
-logic__728: logic__728
-reg__431: reg__431
-reg__553: reg__553
-reg__1376: reg__1376
-reg__666: reg__666
-logic__2125: logic__2125
-case__537: case__537
-logic__3477: logic__3477
-logic__7629: logic__7629
-logic__3417: logic__3417
-logic__6694: logic__6694
-reg__753: reg__753
-dsp48e1__45: dsp48e1__45
-reg__891: reg__891
-logic__4618: logic__4618
-case__589: case__589
-dsp48e1__9: dsp48e1__9
-reg__1430: reg__1430
-logic__8591: logic__8591
-logic__9771: logic__472
-reg__58: reg__58
-reg__616: reg__616
-reg__1381: reg__1381
-logic__9455: logic__3900
-datapath__638: datapath__638
-logic__919: logic__919
-case__947: case__947
-logic__1187: logic__1187
-dsp48e1: dsp48e1
-datapath__304: datapath__304
-reg__508: reg__508
-reg__828: reg__828
-datapath__170: datapath__170
-logic__1833: logic__1833
-case__215: case__215
-logic__2588: logic__2588
-muxpart__78: muxpart__78
-logic__6224: logic__6224
-case__1705: case__530
-case__934: case__934
-logic__8172: logic__8172
-logic__2630: logic__2630
-datapath__104: datapath__104
-logic__6807: logic__6807
-logic__8316: logic__8316
-FPGASPIClockSinkDomain__1: FPGASPIClockSinkDomain
-logic__512: logic__512
-case__669: case__669
-Repeater_TLBundleA_a29d64s2k1z3u: Repeater_TLBundleA_a29d64s2k1z3u
-logic__849: logic__849
-datapath__605: datapath__605
-logic__3521: logic__3521
-logic__6055: logic__6055
-logic__6689: logic__6689
-case__753: case__753
-datapath__172: datapath__172
-datapath__143: datapath__143
-logic__6764: logic__6764
-reg__1528: reg__991
-reg__1581: reg__836
-fft_radix_2__parameterized1: fft_radix_2__parameterized1
-logic__2580: logic__2580
-case__1510: case__1510
-logic__6215: logic__6215
-case__49: case__49
-case__1198: case__1198
-reg__743: reg__743
-datapath__519: datapath__519
-logic__4501: logic__4501
-logic__3004: logic__3004
-logic__8760: logic__8760
-logic__6831: logic__6831
-case__645: case__645
-logic__4947: logic__4947
-logic__817: logic__817
-reg__618: reg__618
-reg__725: reg__725
-logic__3408: logic__3408
-reg__90: reg__90
-reg__1257: reg__1257
-logic__3788: logic__3788
-logic__8790: logic__8790
-case__10: case__10
-logic__6482: logic__6482
-logic__3211: logic__3211
-datapath__459: datapath__459
-case__418: case__418
-reg__134: reg__134
-AsyncQueueSource_TLBundleD_a9d32s1k1z2u: AsyncQueueSource_TLBundleD_a9d32s1k1z2u
-datapath__719: datapath__719
-logic__809: logic__809
-datapath__611: datapath__611
-case__656: case__656
-logic__9491: logic__1961
-logic__3944: logic__3944
-reg__262: reg__262
-datapath__349: datapath__349
-reg__510: reg__510
-case__968: case__968
-logic__2709: logic__2709
-reg__839: reg__839
-logic__6691: logic__6691
-logic__6606: logic__6606
-TLWidthWidget8_2: TLWidthWidget8_2
-logic__273: logic__273
-datapath__590: datapath__590
-logic__6965: logic__6965
-reg__1395: reg__1395
-logic__754: logic__754
-case__930: case__930
-reg__1515: reg__836
-logic__9150: logic__9150
-reg__1235: reg__1235
-reg__695: reg__695
-datapath__202: datapath__202
-reg__799: reg__799
-logic__1051: logic__1051
-FrontBus: FrontBus
-TLXbar_cbus_out_i1_o7_a32d64s2k1z4u: TLXbar_cbus_out_i1_o7_a32d64s2k1z4u
-case__967: case__967
-case__1673: case__1673
-reg__130: reg__130
-datapath__563: datapath__563
-logic__4271: logic__4271
-reg__244: reg__244
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__22: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__971: logic__971
-logic__2290: logic__2290
-logic__1900: logic__1900
-case__1412: case__1412
-logic__7401: logic__7401
-datapath__171: datapath__171
-muxpart__315: muxpart__315
-case__248: case__248
-logic__9590: logic__1658
-logic__9562: logic__1744
-reg__1119: reg__1119
-logic__4186: logic__4186
-reg__1145: reg__1145
-logic__65: logic__65
-reg__817: reg__817
-logic__4033: logic__4033
-datapath__160: datapath__160
-logic__6883: logic__6883
-reg__1323: reg__1323
-datapath__689: datapath__689
-reg__838: reg__838
-addsub__4: addsub__4
-logic__6293: logic__6293
-logic__668: logic__668
-datapath__225: datapath__225
-keep__30: keep__30
-logic__6058: logic__6058
-logic__9728: logic__6152
-muxpart__56: muxpart__56
-logic__945: logic__945
-logic__187: logic__187
-reg__22: reg__22
-case__862: case__862
-reg__156: reg__156
-logic__1: logic__1
-case__1033: case__1033
-reg__1555: reg__838
-AsyncValidSync__8: AsyncValidSync
-case__27: case__27
-logic__6334: logic__6334
-case__1460: case__1460
-datapath__502: datapath__502
-reg__1068: reg__1068
-counter__37: counter__37
-logic__1896: logic__1896
-logic__4753: logic__4753
-logic__9484: logic__1851
-reg__1353: reg__1353
-reg__547: reg__547
-logic__8764: logic__8764
-case__1020: case__1020
-logic__7571: logic__7571
-logic__5371: logic__5371
-logic__147: logic__147
-case__225: case__225
-case__1100: case__1100
-logic__2692: logic__2692
-reg__1267: reg__1267
-logic__5207: logic__5207
-case__863: case__863
-reg__1307: reg__1307
-logic__211: logic__211
-logic__9524: logic__1863
-reg__352: reg__352
-logic__4868: logic__4868
-logic__9129: logic__9129
-logic__8604: logic__8604
-logic__1935: logic__1935
-reg__188: reg__188
-dsp48e1__42: dsp48e1__42
-logic__1590: logic__1590
-datapath__329: datapath__329
-logic__8478: logic__8478
-case__579: case__579
-logic__6283: logic__6283
-TLWidthWidget1: TLWidthWidget1
-case__1731: case__1421
-logic__4279: logic__4279
-logic__9420: logic__2976
-case__1137: case__1137
-RoundAnyRawFNToRecFN_4__1: RoundAnyRawFNToRecFN_4
-logic__6513: logic__6513
-case__36: case__36
-logic__5915: logic__5915
-logic__1963: logic__1963
-logic__9732: logic__6152
-case__759: case__759
-case__695: case__695
-logic__6561: logic__6561
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__14: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__643: case__643
-logic__2584: logic__2584
-logic__4863: logic__4863
-logic__8357: logic__8357
-case__766: case__766
-keep__78: keep__1
-TLXbar_fbus_i1_o1_a32d64s1k1z4u: TLXbar_fbus_i1_o1_a32d64s1k1z4u
-datapath__777: datapath__651
-logic__751: logic__751
-logic__830: logic__830
-muxpart__114: muxpart__114
-datapath__117: datapath__117
-logic__3786: logic__3786
-logic__4018: logic__4018
-reg__446: reg__446
-logic__6081: logic__6081
-case__1364: case__1364
-logic__4138: logic__4138
-logic__6393: logic__6393
-case__305: case__305
-logic__2827: logic__2827
-case__1007: case__1007
-case__1540: case__1540
-reg__406: reg__406
-reg__276: reg__276
-muxpart__80: muxpart__80
-case__595: case__595
-logic__3075: logic__3075
-logic__4694: logic__4694
-reg__1525: reg__994
-logic__9644: logic__1538
-logic__9208: logic__9208
-datapath__253: datapath__253
-logic__1522: logic__1522
-logic__4755: logic__4755
-logic__18: logic__18
-reg__204: reg__204
-reg__42: reg__42
-case__621: case__621
-logic__2731: logic__2731
-reg__479: reg__479
-logic__2508: logic__2508
-reg__931: reg__931
-logic__4227: logic__4227
-logic__9303: logic__9303
-datapath__492: datapath__492
-logic__1818: logic__1818
-logic__300: logic__300
-case__631: case__631
-logic__8627: logic__8627
-logic__6643: logic__6643
-addsub: addsub
-FPUDecoder: FPUDecoder
-counter__8: counter__8
-logic__9116: logic__9116
-logic__4577: logic__4577
-logic__6893: logic__6893
-logic__6565: logic__6565
-logic__326: logic__326
-case__1194: case__1194
-reg__447: reg__447
-case__715: case__715
-logic__9334: logic__9334
-datapath__753: datapath__247
-muxpart__305: muxpart__305
-logic__1595: logic__1595
-logic__843: logic__843
-datapath__697: datapath__697
-logic__975: logic__975
-reg__1513: reg__838
-logic__6616: logic__6616
-reg__1199: reg__1199
-dsp48e1__44: dsp48e1__44
-reg__875: reg__875
-logic__1983: logic__1983
-logic__4862: logic__4862
-logic__1243: logic__1243
-datapath__238: datapath__238
-logic__3948: logic__3948
-case__366: case__366
-logic__5674: logic__5674
-logic__5044: logic__5044
-logic__527: logic__527
-case__384: case__384
-Queue1_RegMapperInput_i9_m8__2: Queue1_RegMapperInput_i9_m8
-logic__496: logic__496
-case__263: case__263
-logic__2106: logic__2106
-logic__4302: logic__4302
-reg__857: reg__857
-reg__640: reg__640
-logic__1279: logic__1279
-logic__3774: logic__3774
-logic__8307: logic__8307
-case__1057: case__1057
-logic__1478: logic__1478
-case__339: case__339
-reg__499: reg__499
-reg__992: reg__992
-case__223: case__223
-case__131: case__131
-datapath__440: datapath__440
-logic__1998: logic__1998
-case__1435: case__1435
-case__1145: case__1145
-logic__2414: logic__2414
-logic__6595: logic__6595
-AsyncResetSynchronizerShiftReg_w1_d3_i0__8: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__313: logic__313
-datapath__733: datapath__733
-extladd: extladd
-reg__1294: reg__1294
-case__289: case__289
-case__659: case__659
-logic__332: logic__332
-logic__3973: logic__3973
-logic__5165: logic__5165
-FPU__GB2: FPU__GB2
-case__1675: case__1675
-logic__8737: logic__8737
-logic__7889: logic__7889
-PMPChecker_s2: PMPChecker_s2
-datapath__224: datapath__224
-dsp48e1__28: dsp48e1__28
-case__483: case__483
-muxpart__68: muxpart__68
-reg__33: reg__33
-logic__119: logic__119
-logic__1982: logic__1982
-case__308: case__308
-logic__7435: logic__7435
-logic__7684: logic__7684
-datapath__214: datapath__214
-logic__691: logic__691
-datapath__613: datapath__613
-logic__4812: logic__4812
-logic__9113: logic__9113
-datapath__195: datapath__195
-logic__2625: logic__2625
-case__706: case__706
-logic__6815: logic__6815
-datapath__206: datapath__206
-case__1524: case__1524
-logic__7027: logic__7027
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__12: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__565: case__565
-logic__5060: logic__5060
-logic__825: logic__825
-logic__8969: logic__8969
-logic__8736: logic__8736
-logic__3795: logic__3795
-case__56: case__56
-logic__2062: logic__2062
-logic__924: logic__924
-reg__17: reg__17
-reg__1534: reg__838
-reg__1197: reg__1197
-logic__6675: logic__6675
-reg__844: reg__844
-logic__9175: logic__9175
-case__1361: case__1361
-reg__502: reg__502
-logic__9149: logic__9149
-case__977: case__977
-case__644: case__644
-case__557: case__557
-gray_to_binary: gray_to_binary
-case__1743: case__1409
-NCO_carr: NCO_carr
-datapath__372: datapath__372
-case__1241: case__1241
-logic__2698: logic__2698
-logic__5690: logic__5690
-datapath__629: datapath__629
-logic__1472: logic__1472
-case__1683: case__1683
-reg__1504: reg__838
-case__550: case__550
-logic__930: logic__930
-logic__8304: logic__8304
-logic__4649: logic__4649
-logic__7246: logic__7246
-reg__312: reg__312
-logic__4479: logic__4479
-logic__5994: logic__5994
-pps_wrapper: pps_wrapper
-logic__2404: logic__2404
-logic__7458: logic__7458
-case__1612: case__1612
-case__807: case__807
-mult_66_66_66: mult_66_66_66
-reg__688: reg__688
-logic__2445: logic__2445
-logic__3502: logic__3502
-reg__1113: reg__1113
-logic__3756: logic__3756
-logic__1385: logic__1385
-datapath__9: datapath__9
-case__923: case__923
-reg__805: reg__805
-reg__602: reg__602
-TLDebugModuleOuter: TLDebugModuleOuter
-logic__9533: logic__1842
-logic__6851: logic__6851
-TLXbar_cbus_in_i1_o1_a32d64s2k1z4u: TLXbar_cbus_in_i1_o1_a32d64s2k1z4u
-logic__1644: logic__1644
-reg__671: reg__671
-logic__5552: logic__5552
-reg__24: reg__24
-ResetCatchAndSync_d3__3: ResetCatchAndSync_d3
-logic__3499: logic__3499
-logic__6376: logic__6376
-VCU118RocketSystem__GC0: VCU118RocketSystem__GC0
-muxpart__58: muxpart__58
-reg__1259: reg__1259
-Arbiter8_DCacheMetadataReq: Arbiter8_DCacheMetadataReq
-logic__1114: logic__1114
-TLBuffer_a32d64s2k1z4u: TLBuffer_a32d64s2k1z4u
-reg__122: reg__122
-logic__206: logic__206
-case__711: case__711
-logic__7072: logic__7072
-datapath__155: datapath__155
-logic__2190: logic__2190
-ResetCatchAndSync_d3: ResetCatchAndSync_d3
-reg__592: reg__592
-logic__6632: logic__6632
-case__812: case__812
-reg__194: reg__194
-logic__7404: logic__7404
-case__935: case__935
-logic__9641: logic__1541
-case__1755: case__1047
-datapath__586: datapath__586
-logic__9151: logic__9151
-datapath__634: datapath__634
-logic__6507: logic__6507
-datapath__207: datapath__207
-logic__6201: logic__6201
-reg__1375: reg__1375
-logic__9793: logic__477
-reg__717: reg__717
-reg__274: reg__274
-case__320: case__320
-logic__6327: logic__6327
-case__196: case__196
-logic__965: logic__965
-ram__14: ram__1
-reg__1318: reg__1318
-logic__96: logic__96
-logic__3660: logic__3660
-logic__8351: logic__8351
-reg__826: reg__826
-logic__8544: logic__8544
-reg__1530: reg__974
-case__186: case__186
-muxpart__49: muxpart__49
-logic__9575: logic__1703
-keep__20: keep__20
-RecFNToRecFN: RecFNToRecFN
-reg__403: reg__403
-logic__7624: logic__7624
-logic__970: logic__970
-keep__79: keep
-logic__2247: logic__2247
-logic__4253: logic__4253
-logic__8517: logic__8517
-case__1762: case__107
-divider_fsm: divider_fsm
-dsp48e1__41: dsp48e1__41
-logic__9748: logic__526
-reg__855: reg__855
-case__1624: case__1624
-datapath__161: datapath__161
-logic__3097: logic__3097
-logic__1524: logic__1524
-spill_register_flushable: spill_register_flushable
-acq_corr: acq_corr
-gray_to_binary__1: gray_to_binary
-reg__1476: reg__1255
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__1443: case__1443
-logic__6333: logic__6333
-logic__891: logic__891
-logic__2898: logic__2898
-reg__1299: reg__1299
-muxpart__72: muxpart__72
-logic__8665: logic__8665
-datapath__522: datapath__522
-logic__2596: logic__2596
-case__662: case__662
-reg__815: reg__815
-logic__2028: logic__2028
-dual_port_bram: dual_port_bram
-AsyncResetSynchronizerShiftReg_w1_d3_i0__4: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__1658: logic__1658
-case__882: case__882
-reg__1437: reg__1437
-case__832: case__832
-reg__294: reg__294
-logic__3798: logic__3798
-logic__4521: logic__4521
-acq_wrapper: acq_wrapper
-reg__197: reg__197
-case__90: case__90
-datapath__83: datapath__83
-case__1521: case__1521
-case__230: case__230
-logic__689: logic__689
-reg__1266: reg__1266
-case__416: case__416
-logic__1165: logic__1165
-logic__3212: logic__3212
-logic__7163: logic__7163
-gray_to_binary__3: gray_to_binary
-logic__4417: logic__4417
-reg__546: reg__546
-reg__501: reg__501
-logic__2179: logic__2179
-reg__606: reg__606
-case__1183: case__1183
-case__948: case__948
-reg__614: reg__614
-logic__2850: logic__2850
-logic__1576: logic__1576
-ResetCatchAndSync_d3__2: ResetCatchAndSync_d3
-extram__8: extram__8
-reg__1442: reg__1442
-logic__2995: logic__2995
-datapath__680: datapath__680
-case__681: case__681
-AsyncValidSync__20: AsyncValidSync
-logic__4257: logic__4257
-case__997: case__997
-logic__6538: logic__6538
-AsyncValidSync__15: AsyncValidSync
-logic__4738: logic__4738
-reg__1634: reg__784
-logic__6649: logic__6649
-datapath__213: datapath__213
-TLAtomicAutomata_cbus: TLAtomicAutomata_cbus
-datapath__601: datapath__601
-case__1094: case__1094
-reg__490: reg__490
-case__946: case__946
-datapath__139: datapath__139
-logic__2277: logic__2277
-reg__1150: reg__1150
-logic__4031: logic__4031
-logic__1202: logic__1202
-logic__2027: logic__2027
-regfile_32x65: regfile_32x65
-reg__1598: reg__837
-reg__1070: reg__1070
-logic__260: logic__260
-logic__2816: logic__2816
-logic__55: logic__55
-logic__4349: logic__4349
-logic__1637: logic__1637
-logic__1005: logic__1005
-sync__2: sync
-datapath__167: datapath__167
-LevelGateway__10: LevelGateway
-case__458: case__458
-reg__1600: reg__838
-Queue2_TLBundleD_a29d64s2k1z3u: Queue2_TLBundleD_a29d64s2k1z3u
-logic__9685: logic__8273
-logic__4784: logic__4784
-logic__7181: logic__7181
-logic__3101: logic__3101
-reg__142: reg__142
-reg__1609: reg__838
-logic__6508: logic__6508
-datapath__375: datapath__375
-case__109: case__109
-reg__1648: reg__66
-logic__1979: logic__1979
-logic__5203: logic__5203
-logic__1575: logic__1575
-logic__9550: logic__1784
-case__1415: case__1415
-logic__1630: logic__1630
-logic__7562: logic__7562
-logic__6462: logic__6462
-case__484: case__484
-logic__51: logic__51
-case__1367: case__1367
-reg__1198: reg__1198
-logic__263: logic__263
-logic__7213: logic__7213
-reg__1316: reg__1316
-reg__807: reg__807
-extrom__3: extrom
-logic__9789: logic__490
-case__452: case__452
-dsp48e1__47: dsp48e1__47
-reg__1221: reg__1221
-case__155: case__155
-logic__4875: logic__4875
-logic__177: logic__177
-reg__1313: reg__1313
-logic__2408: logic__2408
-logic__2806: logic__2806
-logic__7366: logic__7366
-case__1376: case__1376
-datapath__407: datapath__407
-logic__6522: logic__6522
-reg__1584: reg__836
-logic__4139: logic__4139
-logic__3643: logic__3643
-logic__6385: logic__6385
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__12: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-datapath__168: datapath__168
-logic__136: logic__136
-logic__5229: logic__5229
-case__1622: case__1622
-reg__1125: reg__1125
-logic__4950: logic__4950
-logic__8831: logic__8831
-logic__1371: logic__1371
-logic__6783: logic__6783
-case__178: case__178
-reg__765: reg__765
-logic__1631: logic__1631
-logic__3791: logic__3791
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__16: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__3780: logic__3780
-case__1191: case__1191
-logic__3644: logic__3644
-datapath__499: datapath__499
-muxpart__12: muxpart__12
-datapath__694: datapath__694
-logic__1016: logic__1016
-logic__9570: logic__1722
-case__917: case__917
-logic__6610: logic__6610
-logic__4804: logic__4804
-logic__9780: logic__511
-datapath__338: datapath__338
-datapath__339: datapath__339
-logic__893: logic__893
-logic__8956: logic__8956
-logic__4752: logic__4752
-reg__906: reg__906
-logic__2107: logic__2107
-logic__1939: logic__1939
-case__392: case__392
-logic__6264: logic__6264
-reg__766: reg__766
-logic__1431: logic__1431
-logic__7511: logic__7511
-DMIToTL: DMIToTL
-logic__8661: logic__8661
-FixedClockBroadcast_5__1: FixedClockBroadcast_5
-case__407: case__407
-logic__2017: logic__2017
-reg__320: reg__320
-logic__4101: logic__4101
-logic__5453: logic__5453
-logic__6506: logic__6506
-logic__5255: logic__5255
-TLWidthWidget8_1__2: TLWidthWidget8_1
-logic__5168: logic__5168
-logic__4219: logic__4219
-reg__747: reg__747
-datapath__264: datapath__264
-logic__982: logic__982
-reg__115: reg__115
-dsp48e1__25: dsp48e1__25
-case__1668: case__1668
-case__1637: case__1637
-case__459: case__459
-datapath__368: datapath__368
-case__220: case__220
-logic__191: logic__191
-ram_2x120__1: ram_2x120
-logic__7180: logic__7180
-logic__6337: logic__6337
-case__1626: case__1626
-logic__4426: logic__4426
-twiddle_ram__2: twiddle_ram
-case__978: case__978
-reg__94: reg__94
-logic__799: logic__799
-logic__9608: logic__1614
-logic__2370: logic__2370
-logic__1586: logic__1586
-case__870: case__870
-logic__4268: logic__4268
-logic__1153: logic__1153
-logic__964: logic__964
-reg__591: reg__591
-logic__351: logic__351
-datapath__501: datapath__501
-datapath__671: datapath__671
-RoundAnyRawFNToRecFN_2: RoundAnyRawFNToRecFN_2
-reg__20: reg__20
-reg__463: reg__463
-logic__5210: logic__5210
-logic__4583: logic__4583
-case__21: case__21
-case__873: case__873
-Rocket: Rocket
-logic__9535: logic__1836
-reg__866: reg__866
-reg__79: reg__79
-reg__306: reg__306
-reg__208: reg__208
-datapath__198: datapath__198
-counter__11: counter__11
-reg__1297: reg__1297
-datapath__217: datapath__217
-logic__3191: logic__3191
-logic__393: logic__393
-case__331: case__331
-case__456: case__456
-logic__8763: logic__8763
-logic__6254: logic__6254
-logic__688: logic__688
-logic__5706: logic__5706
-case__99: case__99
-logic__6087: logic__6087
-logic__5342: logic__5342
-logic__6440: logic__6440
-logic__8723: logic__8723
-logic__6690: logic__6690
-reg__1589: reg__837
-case__1542: case__1542
-case__1230: case__1230
-logic__8262: logic__8262
-datapath__393: datapath__393
-case__123: case__123
-case__1693: case__465
-logic__5409: logic__5409
-case__826: case__826
-datapath__205: datapath__205
-case__797: case__797
-logic__6795: logic__6795
-logic__3431: logic__3431
-logic__6006: logic__6006
-logic__8062: logic__8062
-reg__937: reg__937
-AsyncQueueSink_TLBundleA_a9d32s1k1z2u: AsyncQueueSink_TLBundleA_a9d32s1k1z2u
-reg__1302: reg__1302
-DivSqrtRecFNToRaw_small_1: DivSqrtRecFNToRaw_small_1
-logic__4580: logic__4580
-logic__4491: logic__4491
-datapath__22: datapath__22
-case__354: case__354
-logic__389: logic__389
-reg__1043: reg__1043
-case__984: case__984
-case__78: case__78
-datapath__416: datapath__416
-case__318: case__318
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__13: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__7612: logic__7612
-logic__1978: logic__1978
-logic__7614: logic__7614
-logic__1004: logic__1004
-logic__8322: logic__8322
-logic__8702: logic__8702
-logic__7496: logic__7496
-reg__1633: reg__784
-reg__96: reg__96
-case__1716: case__321
-logic__9582: logic__1682
-case__915: case__915
-logic__7105: logic__7105
-reg__227: reg__227
-datapath__507: datapath__507
-datapath__192: datapath__192
-logic__4378: logic__4378
-reg__1614: reg__836
-logic__6138: logic__6138
-case__171: case__171
-datapath__609: datapath__609
-logic__5000: logic__5000
-logic__9428: logic__3969
-case__844: case__844
-logic__3183: logic__3183
-logic__6970: logic__6970
-reg__1593: reg__836
-case__983: case__983
-logic__8301: logic__8301
-logic__3157: logic__3157
-datapath__489: datapath__489
-logic__3074: logic__3074
-reg__397: reg__397
-datapath__754: datapath__246
-logic__2356: logic__2356
-case__453: case__453
-muxpart__24: muxpart__24
-case__323: case__323
-datapath__267: datapath__267
-logic__6558: logic__6558
-logic__1541: logic__1541
-logic__4166: logic__4166
-logic__4333: logic__4333
-logic__9487: logic__1844
-case__378: case__378
-logic__6049: logic__6049
-reg__818: reg__818
-muxpart__224: muxpart__224
-reg__63: reg__63
-logic__3775: logic__3775
-logic__7724: logic__7724
-case__588: case__588
-logic__2412: logic__2412
-reg__1667: reg__34
-case__364: case__364
-reg__878: reg__878
-case__192: case__192
-logic__9631: logic__1565
-logic__9592: logic__1654
-case__62: case__62
-logic__5225: logic__5225
-logic__3963: logic__3963
-IntSyncAsyncCrossingSink_n1x1: IntSyncAsyncCrossingSink_n1x1
-case__957: case__957
-logic__8148: logic__8148
-logic__9483: logic__1854
-logic__5990: logic__5990
-muxpart__225: muxpart__225
-logic__7016: logic__7016
-logic__9505: logic__1913
-case__1672: case__1672
-logic__5331: logic__5331
-datapath__371: datapath__371
-logic__7400: logic__7400
-logic__8951: logic__8951
-logic__6241: logic__6241
-logic__1415: logic__1415
-logic__1465: logic__1465
-logic__446: logic__446
-logic__8721: logic__8721
-reg__555: reg__555
-logic__327: logic__327
-case__707: case__707
-logic__9479: logic__1866
-logic__6034: logic__6034
-case__478: case__478
-logic__1002: logic__1002
-logic__4256: logic__4256
-logic__1205: logic__1205
-case__999: case__999
-logic__5904: logic__5904
-logic__8750: logic__8750
-logic__6679: logic__6679
-reg__1369: reg__1369
-datapath__366: datapath__366
-datapath__606: datapath__606
-logic__2321: logic__2321
-logic__4419: logic__4419
-case__507: case__507
-logic__7808: logic__7808
-logic__7060: logic__7060
-INToRecFN_1: INToRecFN_1
-reg__620: reg__620
-reg__101: reg__101
-datapath__495: datapath__495
-reg__577: reg__577
-muxpart__81: muxpart__81
-reg__861: reg__861
-datapath__357: datapath__357
-reg__608: reg__608
-muxpart__30: muxpart__30
-logic__6580: logic__6580
-logic__6532: logic__6532
-logic__6343: logic__6343
-case__634: case__634
-case__324: case__324
-case__1720: case__317
-logic__7150: logic__7150
-logic__9604: logic__1626
-cordic_angle_lut__parameterized0: cordic_angle_lut__parameterized0
-muxpart__319: muxpart__319
-logic__8975: logic__8975
-logic__6030: logic__6030
-logic__4287: logic__4287
-logic__6060: logic__6060
-rockettile_icache_data_arrays_512x32: rockettile_icache_data_arrays_512x32
-reg__1579: reg__838
-logic__2650: logic__2650
-reg__456: reg__456
-reg__1141: reg__1141
-logic__7334: logic__7334
-reg__67: reg__67
-logic__5040: logic__5040
-logic__6635: logic__6635
-logic__1414: logic__1414
-case__1148: case__1148
-case__296: case__296
-logic__6261: logic__6261
-reg__1657: reg__68
-reg__1220: reg__1220
-logic__6915: logic__6915
-muxpart__314: muxpart__314
-datapath__800: datapath__21
-reg__668: reg__668
-logic__9409: logic__2997
-logic__3854: logic__3854
-case__1515: case__1515
-logic__4159: logic__4159
-logic__5240: logic__5240
-logic__5301: logic__5301
-case__329: case__329
-FixedClockBroadcast_1: FixedClockBroadcast_1
-logic__9472: logic__1890
-logic__6250: logic__6250
-case__1129: case__1129
-case__982: case__982
-logic__7291: logic__7291
-logic__6464: logic__6464
-reg__427: reg__427
-logic__5899: logic__5899
-case__849: case__849
-case__424: case__424
-logic__611: logic__611
-logic__8457: logic__8457
-logic__7896: logic__7896
-reg__1510: reg__1001
-case__12: case__12
-logic__4953: logic__4953
-logic__9438: logic__3945
-reg__880: reg__880
-logic__4778: logic__4778
-logic__9329: logic__9329
-case__495: case__495
-logic__6046: logic__6046
-reg__471: reg__471
-logic__3800: logic__3800
-reg__1629: reg__784
-case__276: case__276
-reg__1278: reg__1278
-reg__21: reg__21
-reg__1226: reg__1226
-logic__9733: logic__6147
-logic__2011: logic__2011
-datapath__394: datapath__394
-reg__1066: reg__1066
-case__356: case__356
-reg__159: reg__159
-case__785: case__785
-reg__708: reg__708
-logic__8540: logic__8540
-logic__6207: logic__6207
-reg__443: reg__443
-logic__8761: logic__8761
-logic__2695: logic__2695
-logic__2956: logic__2956
-case__990: case__990
-datapath__543: datapath__543
-case__961: case__961
-datapath__107: datapath__107
-logic__9633: logic__1559
-case__1614: case__1614
-case__641: case__641
-logic__9107: logic__9107
-logic__3578: logic__3578
-logic__9540: logic__1821
-logic__1025: logic__1025
-logic__379: logic__379
-case__83: case__83
-reg__135: reg__135
-case__1379: case__1379
-logic__8899: logic__8899
-reg__313: reg__313
-logic__1100: logic__1100
-logic__9403: logic__3010
-bootromClockSinkDomain: bootromClockSinkDomain
-case__966: case__966
-reg__1384: reg__1384
-reg__1292: reg__1292
-logic__942: logic__942
-dsp48e1__39: dsp48e1__39
-logic__8848: logic__8848
-case__633: case__633
-reg__1251: reg__1251
-NonSyncResetSynchronizerPrimitiveShiftReg_d3: NonSyncResetSynchronizerPrimitiveShiftReg_d3
-logic__9538: logic__1827
-logic__9199: logic__9199
-case__103: case__103
-case__1339: case__1339
-datapath__438: datapath__438
-case__551: case__551
-logic__5285: logic__5285
-logic__9459: logic__1917
-logic__9617: logic__1595
-logic__8584: logic__8584
-logic__4277: logic__4277
-datapath__513: datapath__513
-logic__7283: logic__7283
-case__913: case__913
-logic__1175: logic__1175
-logic__988: logic__988
-logic__9508: logic__1900
-logic__4434: logic__4434
-logic__1470: logic__1470
-case__654: case__654
-logic__9734: logic__6152
-datapath__173: datapath__173
-case__240: case__240
-case__198: case__198
-logic__684: logic__684
-logic__9749: logic__521
-reg__1116: reg__1116
-logic__4736: logic__4736
-logic__5172: logic__5172
-logic__9431: logic__3962
-reg__684: reg__684
-reg__1004: reg__1004
-muxpart__76: muxpart__76
-logic__6018: logic__6018
-logic__1163: logic__1163
-logic__3773: logic__3773
-logic__7066: logic__7066
-logic__6699: logic__6699
-case__1330: case__1330
-keep__38: keep__38
-mult_33_65_98: mult_33_65_98
-reg__505: reg__505
-logic__1280: logic__1280
-logic__937: logic__937
-logic__1860: logic__1860
-case__673: case__673
-muxpart__112: muxpart__112
-logic__2440: logic__2440
-logic__6674: logic__6674
-datapath__653: datapath__653
-logic__4504: logic__4504
-logic__3574: logic__3574
-logic__9643: logic__1539
-logic__5016: logic__5016
-logic__8819: logic__8819
-logic__1334: logic__1334
-logic__7145: logic__7145
-case__1175: case__1175
-logic__9449: logic__3931
-logic__3469: logic__3469
-logic__2433: logic__2433
-muxpart__84: muxpart__84
-MulAddRecFNPipe_l2_e11_s53: MulAddRecFNPipe_l2_e11_s53
-case__1219: case__1219
-logic__3429: logic__3429
-cordic_atan_basic: cordic_atan_basic
-logic__2883: logic__2883
-logic__9650: logic__1524
-logic__2156: logic__2156
-logic__8791: logic__8791
-reg__801: reg__801
-logic__6509: logic__6509
-case__127: case__127
-datapath__188: datapath__188
-reg__1234: reg__1234
-rom__2: rom__2
-case__883: case__883
-case__1670: case__1670
-logic__3699: logic__3699
-binary_to_gray: binary_to_gray
-logic__6039: logic__6039
-logic__2696: logic__2696
-logic__4525: logic__4525
-reg__243: reg__243
-logic__5700: logic__5700
-case__668: case__668
-logic__5357: logic__5357
-reg__167: reg__167
-logic__2890: logic__2890
-dsp48e1__8: dsp48e1__8
-reg__402: reg__402
-reg__636: reg__636
-logic__143: logic__143
-logic__4025: logic__4025
-muxpart__50: muxpart__50
-reg__554: reg__554
-logic__1319: logic__1319
-datapath__374: datapath__374
-case__1331: case__1331
-reg__1341: reg__1341
-logic__2490: logic__2490
-case__866: case__866
-logic__6420: logic__6420
-dsp48e1__17: dsp48e1__17
-reg__285: reg__285
-case__47: case__47
-datapath__456: datapath__456
-reg__1587: reg__836
-reg__106: reg__106
-datapath__607: datapath__607
-logic__9497: logic__1932
-reg__334: reg__334
-case__271: case__271
-logic__4107: logic__4107
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__28: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__1659: reg__66
-logic__8345: logic__8345
-logic__9294: logic__9294
-logic__763: logic__763
-Repeater_TLBundleA_a29d64s2k1z3u__2: Repeater_TLBundleA_a29d64s2k1z3u
-dsp48e1__23: dsp48e1__23
-case__95: case__95
-reg__1178: reg__1178
-logic__1622: logic__1622
-logic__3472: logic__3472
-logic__960: logic__960
-logic__3772: logic__3772
-datapath__60: datapath__60
-logic__5964: logic__5964
-dsp48e1__40: dsp48e1__40
-logic__4147: logic__4147
-reg__1149: reg__1149
-logic__466: logic__466
-MulDiv: MulDiv
-datapath__19: datapath__19
-logic__354: logic__354
-logic__8745: logic__8745
-logic__9576: logic__1702
-logic__4381: logic__4381
-logic__3728: logic__3728
-logic__6794: logic__6794
-logic__487: logic__487
-reg__1156: reg__1156
-logic__670: logic__670
-case__151: case__151
-logic__7753: logic__7753
-logic__436: logic__436
-logic__9707: logic__7681
-logic__6190: logic__6190
-logic__1189: logic__1189
-case__1110: case__1110
-reg__1511: reg__1000
-logic__5204: logic__5204
-logic__8411: logic__8411
-case__924: case__924
-logic__9513: logic__1893
-reg__1151: reg__1151
-logic__7603: logic__7603
-counter__31: counter__31
-logic__6696: logic__6696
-reg__1005: reg__1005
-case__134: case__134
-reg__1433: reg__1433
-logic__2544: logic__2544
-logic__3441: logic__3441
-logic__3799: logic__3799
-logic__8773: logic__8773
-dsp48e1__1: dsp48e1__1
-logic__7799: logic__7799
-logic__8473: logic__8473
-logic__4732: logic__4732
-reg__1109: reg__1109
-logic__8664: logic__8664
-logic__3859: logic__3859
-reg__492: reg__492
-reg__254: reg__254
-case__638: case__638
-logic__1679: logic__1679
-logic__6242: logic__6242
-logic__9184: logic__9184
-reg__733: reg__733
-logic__465: logic__465
-case__1718: case__319
-logic__4719: logic__4719
-reg__1611: reg__836
-butterfly__parameterized1: butterfly__parameterized1
-logic__5988: logic__5988
-case__107: case__107
-logic__3283: logic__3283
-logic__2382: logic__2382
-case__242: case__242
-counter__13: counter__13
-logic__6607: logic__6607
-datapath__226: datapath__226
-reg__1028: reg__1028
-logic__6225: logic__6225
-reg__1054: reg__1054
-logic__9626: logic__1576
-reg__1514: reg__837
-logic__8439: logic__8439
-logic__6817: logic__6817
-logic__6582: logic__6582
-case__265: case__265
-datapath__102: datapath__102
-logic__296: logic__296
-reg__314: reg__314
-logic__7425: logic__7425
-reg__932: reg__932
-case__1772: case__108
-reg__722: reg__722
-logic__9335: logic__9335
-logic__8694: logic__8694
-case__752: case__752
-reg__426: reg__426
-datapath: datapath
-case__70: case__70
-case__528: case__528
-case__632: case__632
-reg__1656: reg__69
-case__1650: case__1650
-case__786: case__786
-keep__33: keep__33
-reg__659: reg__659
-datapath__444: datapath__444
-logic__7585: logic__7585
-logic__330: logic__330
-logic__9796: logic__472
-case__558: case__558
-case__428: case__428
-case__838: case__838
-reg__152: reg__152
-case__1733: case__1419
-case__1275: case__1275
-logic__4452: logic__4452
-logic__6624: logic__6624
-case__25: case__25
-datapath__537: datapath__537
-double_ff_syn__2: double_ff_syn
-logic__4377: logic__4377
-logic__1839: logic__1839
-datapath__756: datapath__244
-logic__6810: logic__6810
-logic__1314: logic__1314
-logic__796: logic__796
-logic__5554: logic__5554
-MulAddRecFNToRaw_preMul: MulAddRecFNToRaw_preMul
-reg__1265: reg__1265
-case__1407: case__1407
-case__969: case__969
-logic__6421: logic__6421
-logic__2098: logic__2098
-reg__19: reg__19
-case__1046: case__1046
-case__1475: case__1475
-reg__366: reg__366
-datapath__351: datapath__351
-logic__6623: logic__6623
-reg__234: reg__234
-logic__7196: logic__7196
-reg__1325: reg__1325
-datapath__648: datapath__648
-logic__4376: logic__4376
-logic__7717: logic__7717
-reg__572: reg__572
-logic__9165: logic__9165
-reg__619: reg__619
-datapath__261: datapath__261
-case__1520: case__1520
-logic__8328: logic__8328
-keep__57: keep__6
-reg__1523: reg__996
-case__281: case__281
-datapath__127: datapath__127
-logic__7112: logic__7112
-datapath__158: datapath__158
-logic__6185: logic__6185
-reg__1604: reg__837
-logic__7214: logic__7214
-logic__966: logic__966
-case__1634: case__1634
-reg__1155: reg__1155
-logic__8295: logic__8295
-logic__9302: logic__9302
-case__374: case__374
-logic__5450: logic__5450
-case__769: case__769
-case__102: case__102
-reg__301: reg__301
-logic__4395: logic__4395
-logic__74: logic__74
-reg__1544: reg__837
-TLInterconnectCoupler_fbus_from_debug_sb: TLInterconnectCoupler_fbus_from_debug_sb
-case__1536: case__1536
-logic__3668: logic__3668
-reg__481: reg__481
-logic__6255: logic__6255
-logic__1106: logic__1106
-logic__2509: logic__2509
-reg__1308: reg__1308
-logic__4284: logic__4284
-datapath__236: datapath__236
-logic__5464: logic__5464
-datapath__90: datapath__90
-datapath__547: datapath__547
-logic__4737: logic__4737
-logic__1142: logic__1142
-reg__1262: reg__1262
-case__1201: case__1201
-dsp48e1__3: dsp48e1__3
-muxpart__317: muxpart__317
-logic__3197: logic__3197
-reg__898: reg__898
-ClockGroup__2: ClockGroup
-case__637: case__637
-logic__5226: logic__5226
-case__574: case__574
-case__433: case__433
-logic__5981: logic__5981
-logic__6935: logic__6935
-dsp48e1__33: dsp48e1__33
-counter__3: counter__3
-datapath__784: datapath__524
-case__82: case__82
-muxpart__82: muxpart__82
-reg__1374: reg__1374
-logic__1921: logic__1921
-extram: extram
-logic__6777: logic__6777
-logic__287: logic__287
-reg__1436: reg__1436
-datapath__112: datapath__112
-case__879: case__879
-reg__1322: reg__1322
-logic__5370: logic__5370
-logic__2363: logic__2363
-case__1688: case__1688
-logic__3627: logic__3627
-reg__755: reg__755
-logic__6640: logic__6640
-reg__788: reg__788
-logic__3886: logic__3886
-DivSqrtRawFN_small_1: DivSqrtRawFN_small_1
-logic__2676: logic__2676
-logic__5079: logic__5079
-reg__27: reg__27
-logic__7654: logic__7654
-logic__1239: logic__1239
-logic__9461: logic__1913
-reg__1332: reg__1332
-logic__4360: logic__4360
-logic__9638: logic__1550
-logic__6155: logic__6155
-logic__455: logic__455
-logic__2900: logic__2900
-logic__9482: logic__1857
-logic__2108: logic__2108
-muxpart: muxpart
-case__1702: case__534
-spill_register: spill_register
-logic__4113: logic__4113
-logic__6745: logic__6745
-case__808: case__808
-case__153: case__153
-dsp48e1__36: dsp48e1__36
-logic__5512: logic__5512
-logic__4402: logic__4402
-reg__1454: reg__1454
-case__1288: case__1288
-logic__8549: logic__8549
-case__594: case__594
-datapath__518: datapath__518
-logic__6094: logic__6094
-logic__9385: logic__9385
-reg__928: reg__928
-case__625: case__625
-reg__1482: reg__1249
-AsyncValidSync__4: AsyncValidSync
-datapath__582: datapath__582
-reg__776: reg__776
-case__582: case__582
-case__1615: case__1615
-muxpart__41: muxpart__41
-TLError: TLError
-reg__902: reg__902
-reg__1622: reg__837
-logic__4663: logic__4663
-logic__4455: logic__4455
-case__286: case__286
-reg__1131: reg__1131
-case__647: case__647
-logic__5997: logic__5997
-logic__7378: logic__7378
-case__1388: case__1388
-logic__9581: logic__1683
-logic__6568: logic__6568
-reg__1275: reg__1275
-logic__612: logic__612
-reg__1652: reg__73
-logic__3016: logic__3016
-reg__317: reg__317
-logic__3249: logic__3249
-logic__5369: logic__5369
-datapath__322: datapath__322
-logic__2364: logic__2364
-logic__879: logic__879
-reg__84: reg__84
-datapath__82: datapath__82
-keep__14: keep__14
-case__1283: case__1283
-datapath__587: datapath__587
-logic__2594: logic__2594
-datapath__531: datapath__531
-logic__9800: logic__277
-reg__583: reg__583
-datapath__676: datapath__676
-datapath__44: datapath__44
-logic__4723: logic__4723
-case__605: case__605
-case__726: case__726
-reg__802: reg__802
-logic__3846: logic__3846
-logic__2198: logic__2198
-logic__9204: logic__9204
-muxpart__110: muxpart__110
-FPU__GB1: FPU__GB1
-case__1095: case__1095
-logic__1437: logic__1437
-reg__627: reg__627
-logic__3648: logic__3648
-logic__1473: logic__1473
-reg__175: reg__175
-datapath__423: datapath__423
-logic__256: logic__256
-keep__43: keep__8
-case__1735: case__1417
-logic__2152: logic__2152
-reg__155: reg__155
-counter__1: counter__1
-case__412: case__412
-logic__8705: logic__8705
-logic__2914: logic__2914
-logic__9635: logic__1557
-muxpart__19: muxpart__19
-reg__292: reg__292
-reg__1615: reg__838
-case__1710: case__525
-logic__511: logic__511
-case__1769: case__111
-reg__1154: reg__1154
-logic__3468: logic__3468
-logic__291: logic__291
-TLInterconnectCoupler_sbus_from_bus_named_fbus: TLInterconnectCoupler_sbus_from_bus_named_fbus
-case__1336: case__1336
-reg__531: reg__531
-logic__7354: logic__7354
-logic__4914: logic__4914
-datapath__223: datapath__223
-reg__1108: reg__1108
-logic__6510: logic__6510
-case__241: case__241
-case__1478: case__1478
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__33: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__237: case__237
-logic__178: logic__178
-logic__1156: logic__1156
-logic__3130: logic__3130
-case__1466: case__1466
-AsyncValidSync__9: AsyncValidSync
-datapath__461: datapath__461
-reg__604: reg__604
-logic__9389: logic__9389
-logic__6208: logic__6208
-TLInterconnectCoupler_pbus_to_fpga_uart__2: TLInterconnectCoupler_pbus_to_fpga_uart
-dsp48e1__21: dsp48e1__21
-logic__8930: logic__8930
-IntToFP: IntToFP
-reg__472: reg__472
-logic__6429: logic__6429
-logic__3794: logic__3794
-case__1279: case__1279
-case__893: case__893
-case__167: case__167
-datapath__72: datapath__72
-logic__7479: logic__7479
-logic__943: logic__943
-case__69: case__69
-reg__1623: reg__836
-reg__1664: reg__37
-logic__4999: logic__4999
-case__505: case__505
-logic__7988: logic__7988
-datapath__594: datapath__594
-reg__748: reg__748
-logic__7049: logic__7049
-logic__1932: logic__1932
-case__15: case__15
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__26: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6147: logic__6147
-logic__897: logic__897
-logic__9436: logic__3951
-addsub__8: addsub__5
-lock_detector: lock_detector
-case__760: case__760
-logic__6177: logic__6177
-reg__1342: reg__1342
-logic__7459: logic__7459
-AMOALU: AMOALU
-reg__1210: reg__1210
-reg__236: reg__236
-logic__208: logic__208
-keep__18: keep__18
-logic__1895: logic__1895
-logic__3848: logic__3848
-logic__5657: logic__5657
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__16: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__563: logic__563
-counter__24: counter__24
-logic__6799: logic__6799
-cordic_atan_one_stage__parameterized0: cordic_atan_one_stage__parameterized0
-logic__8340: logic__8340
-FixedClockBroadcast_3: FixedClockBroadcast_3
-logic__2497: logic__2497
-logic__6971: logic__6971
-datapath__379: datapath__379
-dsp48e1__24: dsp48e1__24
-case__1070: case__1070
-logic__1931: logic__1931
-logic__3768: logic__3768
-logic__880: logic__880
-logic__435: logic__435
-addsub__6: addsub__6
-datapath__164: datapath__164
-case__1140: case__1140
-reg__178: reg__178
-logic__4444: logic__4444
-logic__6615: logic__6615
-reg__371: reg__371
-datapath__194: datapath__194
-case__1131: case__1131
-logic__9141: logic__9141
-case__687: case__687
-reg__734: reg__734
-logic__4706: logic__4706
-logic__325: logic__325
-reg__1517: reg__837
-logic__816: logic__816
-logic__2907: logic__2907
-reg__331: reg__331
-logic__8336: logic__8336
-logic__5892: logic__5892
-logic__9413: logic__2993
-logic__217: logic__217
-logic__2140: logic__2140
-datapath__134: datapath__134
-case__60: case__60
-case__1039: case__1039
-logic__21: logic__21
-case__712: case__712
-reg__865: reg__865
-logic__9190: logic__9190
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/53F669E0.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/53F669E0.rtd
deleted file mode 100644
index 45364f8..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/53F669E0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/57A39820.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/57A39820.rtd
deleted file mode 100644
index 98c532a..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/57A39820.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/58AE7C20.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/58AE7C20.rtd
deleted file mode 100644
index 87937d1..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/58AE7C20.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/5988A760.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/5988A760.rtd
deleted file mode 100644
index d51a2e8..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/5988A760.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/5AE1E420.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/5AE1E420.rtd
deleted file mode 100644
index d7471b6..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/5AE1E420.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/5B8FEC00.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/5B8FEC00.rtd
deleted file mode 100644
index eab637f..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/5B8FEC00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7A5CCD00.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7A5CCD00.rtd
deleted file mode 100644
index 3cb7244..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7A5CCD00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7C364560.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7C364560.rtd
deleted file mode 100644
index f8f9f45..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7C364560.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7F2F87A0.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7F2F87A0.rtd
deleted file mode 100644
index 16f75af..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7F2F87A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7F2F9A00.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7F2F9A00.rtd
deleted file mode 100644
index 40e27c4..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/7F2F9A00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/8B672100.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/8B672100.rtd
deleted file mode 100644
index 224e803..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/8B672100.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/9710DC80.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/9710DC80.rtd
deleted file mode 100644
index cd2c588..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/9710DC80.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/design.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/design.rtd
deleted file mode 100644
index 0fe55de..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/files.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/files.rtd
deleted file mode 100644
index 20fb801..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/files.rtd
+++ /dev/null
@@ -1,14 +0,0 @@
-design.rtd
-straps.rtd
-5AE1E420.rtd
-57A39820.rtd
-5988A760.rtd
-8B672100.rtd
-7A5CCD00.rtd
-7F2F87A0.rtd
-53F669E0.rtd
-7F2F9A00.rtd
-5B8FEC00.rtd
-58AE7C20.rtd
-7C364560.rtd
-9710DC80.rtd
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/straps.rtd b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/straps.rtd
deleted file mode 100644
index 5261858..0000000
Binary files a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/topModuleToGenome.map b/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/topModuleToGenome.map
deleted file mode 100644
index 5e4c704..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/1309558296/u/topModuleToGenome.map
+++ /dev/null
@@ -1,10 +0,0 @@
-TilePRCIDomain: TilePRCIDomain__GC0, HierarchicalElementResetDomain,
-APBGpsBlock: APBGpsBlock__GCB1, APBGpsBlock__GCB0, tracking_wrapper,
-TLToAPB: TLToAPB,
-DCache: DCache,
-FPGAGPSClockSinkDomain: TLToAPB, APBGpsBlock,
-RocketTile: RocketTile__GCB0, FPU, DCache,
-VCU118RocketSystem: VCU118RocketSystem__GC0, FPGAGPSClockSinkDomain, TilePRCIDomain,
-HierarchicalElementResetDomain: RocketTile,
-FPU: FPU__GB2, FPU__GB1, FPU__GB0,
-tracking_wrapper: tracking_wrapper,
diff --git a/.Xil/Vivado-303406-onur/incrSyn/soln.nlo b/.Xil/Vivado-303406-onur/incrSyn/soln.nlo
deleted file mode 100644
index 13af484..0000000
--- a/.Xil/Vivado-303406-onur/incrSyn/soln.nlo
+++ /dev/null
@@ -1 +0,0 @@
-1 -2
diff --git a/.Xil/Vivado-303406-onur/wt/synthesis.wdf b/.Xil/Vivado-303406-onur/wt/synthesis.wdf
deleted file mode 100644
index 706c337..0000000
--- a/.Xil/Vivado-303406-onur/wt/synthesis.wdf
+++ /dev/null
@@ -1,52 +0,0 @@
-version:1
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b333235746666673930302d32:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:67656e65737973325f726f636b65745f746f70:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d53594e544845534953:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7668646c5f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66696c65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f77:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f775f73657474696e6773:64656661756c743a3a6e6f6e65:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c75745f63617363616465:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d676c6f62616c5f726574696d696e67:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30343a313973:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:333339392e3436314d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313734332e3237374d42:00:00
-eof:1147723455
diff --git a/.Xil/Vivado-303406-onur/wt/synthesis_details.wdf b/.Xil/Vivado-303406-onur/wt/synthesis_details.wdf
deleted file mode 100644
index 78f8d66..0000000
--- a/.Xil/Vivado-303406-onur/wt/synthesis_details.wdf
+++ /dev/null
@@ -1,3 +0,0 @@
-version:1
-73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
-eof:2511430288
diff --git a/.Xil/Vivado-60579-onur/.lpr b/.Xil/Vivado-60579-onur/.lpr
deleted file mode 100644
index 4922431..0000000
--- a/.Xil/Vivado-60579-onur/.lpr
+++ /dev/null
@@ -1,9 +0,0 @@
-
-
-
-
-
-
-
-
-
diff --git a/.Xil/Vivado-7908-onur/.lpr b/.Xil/Vivado-7908-onur/.lpr
deleted file mode 100644
index 04ef66e..0000000
--- a/.Xil/Vivado-7908-onur/.lpr
+++ /dev/null
@@ -1,7 +0,0 @@
-
-
-
-
-
-
-
diff --git a/.Xil/Vivado-7908-onur/elab.rtd b/.Xil/Vivado-7908-onur/elab.rtd
deleted file mode 100644
index 3ea400e..0000000
Binary files a/.Xil/Vivado-7908-onur/elab.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/equivDumpFile.info b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/equivDumpFile.info
deleted file mode 100644
index 5f2df82..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/equivDumpFile.info
+++ /dev/null
@@ -1,5 +0,0 @@
-/u_rocket/VCU118RocketSystem__GC0#79:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#0
-/u_rocket/VCU118RocketSystem__GC0#80:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#1
-/u_rocket/VCU118RocketSystem__GC0#293:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#405
-/u_rocket/VCU118RocketSystem__GC0#291:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#403
-/u_rocket/VCU118RocketSystem__GC0#292:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#404
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1220760385.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1220760385.rtd
deleted file mode 100644
index c9b4991..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index 4aeff56..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1294509424.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1294509424.rtd
deleted file mode 100644
index abc9b89..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index b530a7d..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/136113302.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/136113302.rtd
deleted file mode 100644
index 3231c5f..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd
deleted file mode 100644
index 6f03b5e..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1672436263.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1672436263.rtd
deleted file mode 100644
index 80e6ced..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index dbae173..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2438764479.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2438764479.rtd
deleted file mode 100644
index 7c398bc..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2438764479.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd
deleted file mode 100644
index 3338c4f..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2438764479.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2610937407.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2610937407.rtd
deleted file mode 100644
index 5406c87..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index c055017..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2737226844.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2737226844.rtd
deleted file mode 100644
index 456e797..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index 049ddf7..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2962621930.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2962621930.rtd
deleted file mode 100644
index f3a1bf2..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index e5c5377..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3482045580.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3482045580.rtd
deleted file mode 100644
index 51bb5b5..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index f5b1e77..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3990655999.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3990655999.rtd
deleted file mode 100644
index f0bd047..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3990655999.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd
deleted file mode 100644
index 2200c03..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/3990655999.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/976197094.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/976197094.rtd
deleted file mode 100644
index 5b6b566..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd
deleted file mode 100644
index 7a9896f..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/global_name.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/global_name.straps.rtd
deleted file mode 100644
index 8aeb0c8..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/instToEncGenName.map b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/instToEncGenName.map
deleted file mode 100644
index 610ac59..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/g/instToEncGenName.map
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/genesys2_rocket_top__GC0:3990655999
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0:2438764479
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/genomeDependencyGraph.out b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/genomeDependencyGraph.out
deleted file mode 100644
index 7534bff..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/genomeDependencyGraph.out
+++ /dev/null
@@ -1,53 +0,0 @@
-GENOME NON_GENOME PIN 406: GENOME NON_GENOME PIN 0
-GENOME NON_GENOME PIN 0: GENOME NON_GENOME PIN 406
-GENOME NON_GENOME PIN 407: GENOME NON_GENOME PIN 1
-GENOME NON_GENOME PIN 1: GENOME NON_GENOME PIN 407
-GENOME NON_GENOME PIN 805: GENOME NON_GENOME PIN 403
-GENOME NON_GENOME PIN 403: GENOME NON_GENOME PIN 805
-GENOME NON_GENOME PIN 806: GENOME NON_GENOME PIN 404
-GENOME NON_GENOME PIN 404: GENOME NON_GENOME PIN 806
-GENOME NON_GENOME PIN 807: GENOME NON_GENOME PIN 405
-GENOME NON_GENOME PIN 405: GENOME NON_GENOME PIN 807
-GENOME NON_GENOME PIN 98: GENOME NON_GENOME PIN 47
-GENOME NON_GENOME PIN 47: GENOME NON_GENOME PIN 98
-INST genesys2_rocket_top__GC0 PIN 44: INST NON_GENOME PIN 102 TYPE 1 GENOME genesys2_rocket_top__GC0 PIN 44
-INST TLToAPB PIN 119: INST VCU118RocketSystem__GC0 PIN 83 TYPE 5
-INST TLToAPB PIN 120: INST VCU118RocketSystem__GC0 PIN 84 TYPE 5
-INST TLToAPB PIN 121: INST VCU118RocketSystem__GC0 PIN 85 TYPE 5
-INST TLToAPB PIN 122: INST VCU118RocketSystem__GC0 PIN 86 TYPE 5
-INST TLToAPB PIN 123: INST VCU118RocketSystem__GC0 PIN 87 TYPE 5
-INST TLToAPB PIN 162: INST VCU118RocketSystem__GC0 PIN 126 TYPE 5
-INST TLToAPB PIN 163: INST VCU118RocketSystem__GC0 PIN 127 TYPE 5
-INST TLToAPB PIN 164: INST VCU118RocketSystem__GC0 PIN 128 TYPE 5
-INST TLToAPB PIN 165: INST VCU118RocketSystem__GC0 PIN 129 TYPE 5
-INST TLToAPB PIN 166: INST VCU118RocketSystem__GC0 PIN 130 TYPE 5
-INST TLToAPB PIN 167: INST VCU118RocketSystem__GC0 PIN 131 TYPE 5
-INST TLToAPB PIN 168: INST VCU118RocketSystem__GC0 PIN 132 TYPE 5
-INST TLToAPB PIN 169: INST VCU118RocketSystem__GC0 PIN 133 TYPE 5
-INST TLToAPB PIN 170: INST VCU118RocketSystem__GC0 PIN 134 TYPE 5
-INST TLToAPB PIN 171: INST VCU118RocketSystem__GC0 PIN 135 TYPE 5
-INST TLToAPB PIN 172: INST VCU118RocketSystem__GC0 PIN 136 TYPE 5
-INST TLToAPB PIN 205: INST VCU118RocketSystem__GC0 PIN 169 TYPE 5
-INST TilePRCIDomain__GC0 PIN 728: INST VCU118RocketSystem__GC0 PIN 289 TYPE 5
-INST TilePRCIDomain__GC0 PIN 808: INST RocketTile__GCB0 PIN 74 TYPE 5
-INST VCU118RocketSystem__GC0 PIN 79: INST TilePRCIDomain__GC0 PIN 0 TYPE 3 INST FPU__GB0 PIN 301 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST DCache PIN 338 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 80: INST TilePRCIDomain__GC0 PIN 1 TYPE 3 INST FPU__GB1 PIN 323 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST DCache PIN 339 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 293: INST TilePRCIDomain__GC0 PIN 405 TYPE 3 INST RocketTile__GCB0 PIN 1114 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 291: INST TilePRCIDomain__GC0 PIN 403 TYPE 3 INST RocketTile__GCB0 PIN 1115 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 292: INST TilePRCIDomain__GC0 PIN 404 TYPE 3 INST RocketTile__GCB0 PIN 1116 TYPE 4
-INST TLToAPB PIN 2: INST VCU118RocketSystem__GC0 PIN 489 TYPE 0 GENOME TLToAPB PIN 2
-INST TLToAPB PIN 3: INST VCU118RocketSystem__GC0 PIN 490 TYPE 0 GENOME TLToAPB PIN 3
-INST TLToAPB PIN 5: INST VCU118RocketSystem__GC0 PIN 492 TYPE 0 GENOME TLToAPB PIN 5
-INST TLToAPB PIN 6: INST VCU118RocketSystem__GC0 PIN 493 TYPE 0 GENOME TLToAPB PIN 6
-INST TLToAPB PIN 16: INST VCU118RocketSystem__GC0 PIN 503 TYPE 0 GENOME TLToAPB PIN 16
-INST TilePRCIDomain__GC0 PIN 218: INST VCU118RocketSystem__GC0 PIN 550 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 218
-INST TilePRCIDomain__GC0 PIN 219: INST VCU118RocketSystem__GC0 PIN 551 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 219
-INST TilePRCIDomain__GC0 PIN 284: INST VCU118RocketSystem__GC0 PIN 616 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 284
-INST TilePRCIDomain__GC0 PIN 0: GENOME TilePRCIDomain__GC0 PIN 0
-INST TilePRCIDomain__GC0 PIN 1: GENOME TilePRCIDomain__GC0 PIN 1
-INST TilePRCIDomain__GC0 PIN 403: GENOME TilePRCIDomain__GC0 PIN 403
-INST TilePRCIDomain__GC0 PIN 404: GENOME TilePRCIDomain__GC0 PIN 404
-INST TilePRCIDomain__GC0 PIN 405: GENOME TilePRCIDomain__GC0 PIN 405
-INST TilePRCIDomain__GC0 PIN 805: INST VCU118RocketSystem__GC0 PIN 291 TYPE 5
-INST TilePRCIDomain__GC0 PIN 806: INST VCU118RocketSystem__GC0 PIN 292 TYPE 5
-INST TilePRCIDomain__GC0 PIN 807: INST VCU118RocketSystem__GC0 PIN 293 TYPE 5
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/genomes.map b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/genomes.map
deleted file mode 100644
index 61341d1..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/genomes.map
+++ /dev/null
@@ -1,11 +0,0 @@
-FPU__GB0 88C687C0
-FPU__GB1 55CCF5C0
-FPU__GB2 82A8DC80
-RocketTile__GCB0 59376600
-DCache 55D97040
-TilePRCIDomain__GC0 6BE153A0
-tracking_wrapper 79F91720
-APBGpsBlock__GC0 5655A480
-TLToAPB 6D2DBAE0
-VCU118RocketSystem__GC0 5278D140
-genesys2_rocket_top__GC0 7BDD0DC0
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/54573100.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/54573100.rtd
deleted file mode 100644
index 48be5c4..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/54573100.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55C42420.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55C42420.rtd
deleted file mode 100644
index ef8657b..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55C42420.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55C67420.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55C67420.rtd
deleted file mode 100644
index 94f504f..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55C67420.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55DF1B00.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55DF1B00.rtd
deleted file mode 100644
index fe733c3..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55DF1B00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55E32220.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55E32220.rtd
deleted file mode 100644
index 5622845..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/55E32220.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/562790E0.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/562790E0.rtd
deleted file mode 100644
index 3812670..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/562790E0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/56DC6640.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/56DC6640.rtd
deleted file mode 100644
index b01c93d..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/56DC6640.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/59BB7D60.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/59BB7D60.rtd
deleted file mode 100644
index e6d401a..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/59BB7D60.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/820E5E00.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/820E5E00.rtd
deleted file mode 100644
index 708e894..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/820E5E00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/9289B660.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/9289B660.rtd
deleted file mode 100644
index 3b0573b..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/9289B660.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/93836360.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/93836360.rtd
deleted file mode 100644
index 745ea84..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/93836360.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/design.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/design.rtd
deleted file mode 100644
index 9de2c69..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/files.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/files.rtd
deleted file mode 100644
index 48b9873..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/files.rtd
+++ /dev/null
@@ -1,13 +0,0 @@
-design.rtd
-straps.rtd
-54573100.rtd
-56DC6640.rtd
-93836360.rtd
-55C67420.rtd
-562790E0.rtd
-59BB7D60.rtd
-55DF1B00.rtd
-55C42420.rtd
-9289B660.rtd
-820E5E00.rtd
-55E32220.rtd
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/straps.rtd
deleted file mode 100644
index 8fc11e5..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/uniqInferGenToOrigInferGen.map b/.Xil/Vivado-7908-onur/incrSyn/1309558296/a/uniqInferGenToOrigInferGen.map
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/genomeDependencyGraph.out b/.Xil/Vivado-7908-onur/incrSyn/1309558296/genomeDependencyGraph.out
deleted file mode 100644
index 8197aa3..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/genomeDependencyGraph.out
+++ /dev/null
@@ -1,900 +0,0 @@
-GENOME NON_GENOME PIN 406: GENOME NON_GENOME PIN 0
-GENOME NON_GENOME PIN 0: GENOME NON_GENOME PIN 406
-GENOME NON_GENOME PIN 407: GENOME NON_GENOME PIN 1
-GENOME NON_GENOME PIN 1: GENOME NON_GENOME PIN 407
-GENOME NON_GENOME PIN 805: GENOME NON_GENOME PIN 403 GENOME NON_GENOME PIN 867
-GENOME NON_GENOME PIN 403: GENOME NON_GENOME PIN 805 GENOME NON_GENOME PIN 465
-GENOME NON_GENOME PIN 806: GENOME NON_GENOME PIN 404 GENOME NON_GENOME PIN 744
-GENOME NON_GENOME PIN 404: GENOME NON_GENOME PIN 806
-GENOME NON_GENOME PIN 807: GENOME NON_GENOME PIN 405
-GENOME NON_GENOME PIN 405: GENOME NON_GENOME PIN 807
-GENOME NON_GENOME PIN 98: GENOME NON_GENOME PIN 47
-GENOME NON_GENOME PIN 47: GENOME NON_GENOME PIN 98 GENOME NON_GENOME PIN 1290
-INST genesys2_rocket_top__GC0 PIN 44: INST NON_GENOME PIN 102 TYPE 1 GENOME genesys2_rocket_top__GC0 PIN 44
-INST TLToAPB PIN 119: INST VCU118RocketSystem__GC0 PIN 83 TYPE 5
-INST TLToAPB PIN 120: INST VCU118RocketSystem__GC0 PIN 84 TYPE 5
-INST TLToAPB PIN 121: INST VCU118RocketSystem__GC0 PIN 85 TYPE 5
-INST TLToAPB PIN 122: INST VCU118RocketSystem__GC0 PIN 86 TYPE 5
-INST TLToAPB PIN 123: INST VCU118RocketSystem__GC0 PIN 87 TYPE 5
-INST TLToAPB PIN 162: INST VCU118RocketSystem__GC0 PIN 126 TYPE 5
-INST TLToAPB PIN 163: INST VCU118RocketSystem__GC0 PIN 127 TYPE 5
-INST TLToAPB PIN 164: INST VCU118RocketSystem__GC0 PIN 128 TYPE 5
-INST TLToAPB PIN 165: INST VCU118RocketSystem__GC0 PIN 129 TYPE 5
-INST TLToAPB PIN 166: INST VCU118RocketSystem__GC0 PIN 130 TYPE 5
-INST TLToAPB PIN 167: INST VCU118RocketSystem__GC0 PIN 131 TYPE 5
-INST TLToAPB PIN 168: INST VCU118RocketSystem__GC0 PIN 132 TYPE 5
-INST TLToAPB PIN 169: INST VCU118RocketSystem__GC0 PIN 133 TYPE 5
-INST TLToAPB PIN 170: INST VCU118RocketSystem__GC0 PIN 134 TYPE 5
-INST TLToAPB PIN 171: INST VCU118RocketSystem__GC0 PIN 135 TYPE 5
-INST TLToAPB PIN 172: INST VCU118RocketSystem__GC0 PIN 136 TYPE 5
-INST TLToAPB PIN 205: INST VCU118RocketSystem__GC0 PIN 169 TYPE 5
-INST TilePRCIDomain__GC0 PIN 728: INST VCU118RocketSystem__GC0 PIN 289 TYPE 5
-INST TilePRCIDomain__GC0 PIN 808: INST RocketTile__GCB0 PIN 74 TYPE 5
-INST VCU118RocketSystem__GC0 PIN 79: INST TilePRCIDomain__GC0 PIN 0 TYPE 3 INST FPU__GB0 PIN 301 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST DCache PIN 338 TYPE 4 GENOME VCU118RocketSystem__GC0 PIN 79
-INST VCU118RocketSystem__GC0 PIN 80: INST TilePRCIDomain__GC0 PIN 1 TYPE 3 INST FPU__GB1 PIN 323 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST DCache PIN 339 TYPE 4 GENOME VCU118RocketSystem__GC0 PIN 80
-INST VCU118RocketSystem__GC0 PIN 293: INST TilePRCIDomain__GC0 PIN 405 TYPE 3 INST RocketTile__GCB0 PIN 1114 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 291: INST TilePRCIDomain__GC0 PIN 403 TYPE 3 INST RocketTile__GCB0 PIN 1115 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 292: INST TilePRCIDomain__GC0 PIN 404 TYPE 3 INST RocketTile__GCB0 PIN 1116 TYPE 4
-INST TLToAPB PIN 2: INST VCU118RocketSystem__GC0 PIN 489 TYPE 0 GENOME TLToAPB PIN 2
-INST TLToAPB PIN 3: INST VCU118RocketSystem__GC0 PIN 490 TYPE 0 GENOME TLToAPB PIN 3
-INST TLToAPB PIN 5: INST VCU118RocketSystem__GC0 PIN 492 TYPE 0 GENOME TLToAPB PIN 5
-INST TLToAPB PIN 6: INST VCU118RocketSystem__GC0 PIN 493 TYPE 0 GENOME TLToAPB PIN 6
-INST TLToAPB PIN 16: INST VCU118RocketSystem__GC0 PIN 503 TYPE 0 GENOME TLToAPB PIN 16
-INST TilePRCIDomain__GC0 PIN 218: INST VCU118RocketSystem__GC0 PIN 550 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 218
-INST TilePRCIDomain__GC0 PIN 219: INST VCU118RocketSystem__GC0 PIN 551 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 219
-INST TilePRCIDomain__GC0 PIN 284: INST VCU118RocketSystem__GC0 PIN 616 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 284
-INST TilePRCIDomain__GC0 PIN 0: GENOME TilePRCIDomain__GC0 PIN 0
-INST TilePRCIDomain__GC0 PIN 1: GENOME TilePRCIDomain__GC0 PIN 1
-INST TilePRCIDomain__GC0 PIN 403: GENOME TilePRCIDomain__GC0 PIN 403
-INST TilePRCIDomain__GC0 PIN 404: GENOME TilePRCIDomain__GC0 PIN 404
-INST TilePRCIDomain__GC0 PIN 405: GENOME TilePRCIDomain__GC0 PIN 405
-INST TilePRCIDomain__GC0 PIN 805: INST VCU118RocketSystem__GC0 PIN 291 TYPE 5
-INST TilePRCIDomain__GC0 PIN 806: INST VCU118RocketSystem__GC0 PIN 292 TYPE 5
-INST TilePRCIDomain__GC0 PIN 807: INST VCU118RocketSystem__GC0 PIN 293 TYPE 5
-INST APBGpsBlock__GC0 PIN 110: INST TLToAPB PIN 52 TYPE 5
-INST APBGpsBlock__GC0 PIN 112: INST TLToAPB PIN 83 TYPE 5
-INST APBGpsBlock__GC0 PIN 113: INST TLToAPB PIN 84 TYPE 5
-INST APBGpsBlock__GC0 PIN 114: INST TLToAPB PIN 85 TYPE 5
-INST APBGpsBlock__GC0 PIN 115: INST TLToAPB PIN 86 TYPE 5
-INST APBGpsBlock__GC0 PIN 116: INST TLToAPB PIN 87 TYPE 5
-INST APBGpsBlock__GC0 PIN 117: INST TLToAPB PIN 88 TYPE 5
-INST APBGpsBlock__GC0 PIN 118: INST TLToAPB PIN 89 TYPE 5
-INST APBGpsBlock__GC0 PIN 119: INST TLToAPB PIN 90 TYPE 5
-INST APBGpsBlock__GC0 PIN 120: INST TLToAPB PIN 91 TYPE 5
-INST APBGpsBlock__GC0 PIN 121: INST TLToAPB PIN 92 TYPE 5
-INST APBGpsBlock__GC0 PIN 122: INST TLToAPB PIN 93 TYPE 5
-INST APBGpsBlock__GC0 PIN 123: INST TLToAPB PIN 94 TYPE 5
-INST APBGpsBlock__GC0 PIN 124: INST TLToAPB PIN 95 TYPE 5
-INST APBGpsBlock__GC0 PIN 125: INST TLToAPB PIN 96 TYPE 5
-INST APBGpsBlock__GC0 PIN 126: INST TLToAPB PIN 97 TYPE 5
-INST APBGpsBlock__GC0 PIN 127: INST TLToAPB PIN 98 TYPE 5
-INST APBGpsBlock__GC0 PIN 128: INST TLToAPB PIN 99 TYPE 5
-INST APBGpsBlock__GC0 PIN 129: INST TLToAPB PIN 100 TYPE 5
-INST APBGpsBlock__GC0 PIN 130: INST TLToAPB PIN 101 TYPE 5
-INST APBGpsBlock__GC0 PIN 131: INST TLToAPB PIN 102 TYPE 5
-INST APBGpsBlock__GC0 PIN 132: INST TLToAPB PIN 103 TYPE 5
-INST APBGpsBlock__GC0 PIN 133: INST TLToAPB PIN 104 TYPE 5
-INST APBGpsBlock__GC0 PIN 134: INST TLToAPB PIN 105 TYPE 5
-INST APBGpsBlock__GC0 PIN 135: INST TLToAPB PIN 106 TYPE 5
-INST APBGpsBlock__GC0 PIN 136: INST TLToAPB PIN 107 TYPE 5
-INST APBGpsBlock__GC0 PIN 137: INST TLToAPB PIN 108 TYPE 5
-INST APBGpsBlock__GC0 PIN 138: INST TLToAPB PIN 109 TYPE 5
-INST NON_GENOME PIN 51: INST VCU118RocketSystem__GC0 PIN 171 TYPE 3 INST tracking_wrapper PIN 35 TYPE 4 INST APBGpsBlock__GC0 PIN 80 TYPE 4 INST TLToAPB PIN 115 TYPE 4
-INST NON_GENOME PIN 52: INST VCU118RocketSystem__GC0 PIN 172 TYPE 3 INST APBGpsBlock__GC0 PIN 151 TYPE 4 INST TLToAPB PIN 116 TYPE 4
-INST tracking_wrapper PIN 50: INST TLToAPB PIN 52 TYPE 5
-INST tracking_wrapper PIN 84: INST APBGpsBlock__GC0 PIN 36 TYPE 5
-INST tracking_wrapper PIN 85: INST APBGpsBlock__GC0 PIN 2 TYPE 5
-INST NON_GENOME PIN 55: INST VCU118RocketSystem__GC0 PIN 79 TYPE 3 INST DCache PIN 338 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB0 PIN 301 TYPE 4 INST TilePRCIDomain__GC0 PIN 406 TYPE 4
-INST NON_GENOME PIN 56: INST VCU118RocketSystem__GC0 PIN 80 TYPE 3 INST DCache PIN 339 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST FPU__GB1 PIN 323 TYPE 4 INST TilePRCIDomain__GC0 PIN 407 TYPE 4
-INST RocketTile__GCB0 PIN 1244: INST TilePRCIDomain__GC0 PIN 7 TYPE 5
-INST RocketTile__GCB0 PIN 1245: INST TilePRCIDomain__GC0 PIN 8 TYPE 5
-INST RocketTile__GCB0 PIN 1251: INST TilePRCIDomain__GC0 PIN 14 TYPE 5
-INST RocketTile__GCB0 PIN 1650: INST DCache PIN 336 TYPE 5
-INST RocketTile__GCB0 PIN 1651: INST DCache PIN 337 TYPE 5
-INST DCache PIN 342: INST RocketTile__GCB0 PIN 2 TYPE 5
-INST DCache PIN 349: INST RocketTile__GCB0 PIN 9 TYPE 5
-INST TilePRCIDomain__GC0 PIN 5: INST RocketTile__GCB0 PIN 3 TYPE 3 INST DCache PIN 343 TYPE 4
-INST TilePRCIDomain__GC0 PIN 6: INST RocketTile__GCB0 PIN 4 TYPE 3 INST DCache PIN 344 TYPE 4
-INST TilePRCIDomain__GC0 PIN 9: INST RocketTile__GCB0 PIN 5 TYPE 3 INST DCache PIN 345 TYPE 4
-INST TilePRCIDomain__GC0 PIN 10: INST RocketTile__GCB0 PIN 6 TYPE 3 INST DCache PIN 346 TYPE 4
-INST TilePRCIDomain__GC0 PIN 11: INST RocketTile__GCB0 PIN 7 TYPE 3 INST DCache PIN 347 TYPE 4
-INST TilePRCIDomain__GC0 PIN 12: INST RocketTile__GCB0 PIN 8 TYPE 3 INST DCache PIN 348 TYPE 4
-INST TilePRCIDomain__GC0 PIN 16: INST RocketTile__GCB0 PIN 10 TYPE 3 INST DCache PIN 350 TYPE 4
-INST TilePRCIDomain__GC0 PIN 17: INST RocketTile__GCB0 PIN 11 TYPE 3 INST DCache PIN 351 TYPE 4
-INST TilePRCIDomain__GC0 PIN 18: INST RocketTile__GCB0 PIN 12 TYPE 3 INST DCache PIN 352 TYPE 4
-INST TilePRCIDomain__GC0 PIN 19: INST RocketTile__GCB0 PIN 13 TYPE 3 INST DCache PIN 353 TYPE 4
-INST TilePRCIDomain__GC0 PIN 20: INST RocketTile__GCB0 PIN 14 TYPE 3 INST DCache PIN 354 TYPE 4
-INST TilePRCIDomain__GC0 PIN 21: INST RocketTile__GCB0 PIN 15 TYPE 3 INST DCache PIN 355 TYPE 4
-INST TilePRCIDomain__GC0 PIN 22: INST RocketTile__GCB0 PIN 16 TYPE 3 INST DCache PIN 356 TYPE 4
-INST TilePRCIDomain__GC0 PIN 23: INST RocketTile__GCB0 PIN 17 TYPE 3 INST DCache PIN 357 TYPE 4
-INST TilePRCIDomain__GC0 PIN 24: INST RocketTile__GCB0 PIN 18 TYPE 3 INST DCache PIN 358 TYPE 4
-INST TilePRCIDomain__GC0 PIN 25: INST RocketTile__GCB0 PIN 19 TYPE 3 INST DCache PIN 359 TYPE 4
-INST TilePRCIDomain__GC0 PIN 26: INST RocketTile__GCB0 PIN 20 TYPE 3 INST DCache PIN 360 TYPE 4
-INST TilePRCIDomain__GC0 PIN 27: INST RocketTile__GCB0 PIN 21 TYPE 3 INST DCache PIN 361 TYPE 4
-INST TilePRCIDomain__GC0 PIN 28: INST RocketTile__GCB0 PIN 22 TYPE 3 INST DCache PIN 362 TYPE 4
-INST TilePRCIDomain__GC0 PIN 29: INST RocketTile__GCB0 PIN 23 TYPE 3 INST DCache PIN 363 TYPE 4
-INST TilePRCIDomain__GC0 PIN 30: INST RocketTile__GCB0 PIN 24 TYPE 3 INST DCache PIN 364 TYPE 4
-INST TilePRCIDomain__GC0 PIN 31: INST RocketTile__GCB0 PIN 25 TYPE 3 INST DCache PIN 365 TYPE 4
-INST TilePRCIDomain__GC0 PIN 32: INST RocketTile__GCB0 PIN 26 TYPE 3 INST DCache PIN 366 TYPE 4
-INST TilePRCIDomain__GC0 PIN 33: INST RocketTile__GCB0 PIN 27 TYPE 3 INST DCache PIN 367 TYPE 4
-INST TilePRCIDomain__GC0 PIN 34: INST RocketTile__GCB0 PIN 28 TYPE 3 INST DCache PIN 368 TYPE 4
-INST TilePRCIDomain__GC0 PIN 35: INST RocketTile__GCB0 PIN 29 TYPE 3 INST DCache PIN 369 TYPE 4
-INST TilePRCIDomain__GC0 PIN 36: INST RocketTile__GCB0 PIN 30 TYPE 3 INST DCache PIN 370 TYPE 4
-INST TilePRCIDomain__GC0 PIN 37: INST RocketTile__GCB0 PIN 31 TYPE 3 INST DCache PIN 371 TYPE 4
-INST TilePRCIDomain__GC0 PIN 38: INST RocketTile__GCB0 PIN 32 TYPE 3 INST DCache PIN 372 TYPE 4
-INST TilePRCIDomain__GC0 PIN 39: INST RocketTile__GCB0 PIN 33 TYPE 3 INST DCache PIN 373 TYPE 4
-INST TilePRCIDomain__GC0 PIN 40: INST RocketTile__GCB0 PIN 34 TYPE 3 INST DCache PIN 374 TYPE 4
-INST TilePRCIDomain__GC0 PIN 41: INST RocketTile__GCB0 PIN 35 TYPE 3 INST DCache PIN 375 TYPE 4
-INST TilePRCIDomain__GC0 PIN 42: INST RocketTile__GCB0 PIN 36 TYPE 3 INST DCache PIN 376 TYPE 4
-INST TilePRCIDomain__GC0 PIN 43: INST RocketTile__GCB0 PIN 37 TYPE 3 INST DCache PIN 377 TYPE 4
-INST TilePRCIDomain__GC0 PIN 44: INST RocketTile__GCB0 PIN 38 TYPE 3 INST DCache PIN 378 TYPE 4
-INST TilePRCIDomain__GC0 PIN 45: INST RocketTile__GCB0 PIN 39 TYPE 3 INST DCache PIN 379 TYPE 4
-INST TilePRCIDomain__GC0 PIN 46: INST RocketTile__GCB0 PIN 40 TYPE 3 INST DCache PIN 380 TYPE 4
-INST TilePRCIDomain__GC0 PIN 47: INST RocketTile__GCB0 PIN 41 TYPE 3 INST DCache PIN 381 TYPE 4
-INST TilePRCIDomain__GC0 PIN 48: INST RocketTile__GCB0 PIN 42 TYPE 3 INST DCache PIN 382 TYPE 4
-INST TilePRCIDomain__GC0 PIN 49: INST RocketTile__GCB0 PIN 43 TYPE 3 INST DCache PIN 383 TYPE 4
-INST TilePRCIDomain__GC0 PIN 50: INST RocketTile__GCB0 PIN 44 TYPE 3 INST DCache PIN 384 TYPE 4
-INST TilePRCIDomain__GC0 PIN 51: INST RocketTile__GCB0 PIN 45 TYPE 3 INST DCache PIN 385 TYPE 4
-INST TilePRCIDomain__GC0 PIN 52: INST RocketTile__GCB0 PIN 46 TYPE 3 INST DCache PIN 386 TYPE 4
-INST TilePRCIDomain__GC0 PIN 53: INST RocketTile__GCB0 PIN 47 TYPE 3 INST DCache PIN 387 TYPE 4
-INST TilePRCIDomain__GC0 PIN 54: INST RocketTile__GCB0 PIN 48 TYPE 3 INST DCache PIN 388 TYPE 4
-INST TilePRCIDomain__GC0 PIN 55: INST RocketTile__GCB0 PIN 49 TYPE 3 INST DCache PIN 389 TYPE 4
-INST TilePRCIDomain__GC0 PIN 56: INST RocketTile__GCB0 PIN 50 TYPE 3 INST DCache PIN 390 TYPE 4
-INST TilePRCIDomain__GC0 PIN 57: INST RocketTile__GCB0 PIN 51 TYPE 3 INST DCache PIN 391 TYPE 4
-INST TilePRCIDomain__GC0 PIN 58: INST RocketTile__GCB0 PIN 52 TYPE 3 INST DCache PIN 392 TYPE 4
-INST TilePRCIDomain__GC0 PIN 59: INST RocketTile__GCB0 PIN 53 TYPE 3 INST DCache PIN 393 TYPE 4
-INST TilePRCIDomain__GC0 PIN 60: INST RocketTile__GCB0 PIN 54 TYPE 3 INST DCache PIN 394 TYPE 4
-INST TilePRCIDomain__GC0 PIN 61: INST RocketTile__GCB0 PIN 55 TYPE 3 INST DCache PIN 395 TYPE 4
-INST TilePRCIDomain__GC0 PIN 62: INST RocketTile__GCB0 PIN 56 TYPE 3 INST DCache PIN 396 TYPE 4
-INST TilePRCIDomain__GC0 PIN 63: INST RocketTile__GCB0 PIN 57 TYPE 3 INST DCache PIN 397 TYPE 4
-INST TilePRCIDomain__GC0 PIN 64: INST RocketTile__GCB0 PIN 58 TYPE 3 INST DCache PIN 398 TYPE 4
-INST TilePRCIDomain__GC0 PIN 65: INST RocketTile__GCB0 PIN 59 TYPE 3 INST DCache PIN 399 TYPE 4
-INST TilePRCIDomain__GC0 PIN 66: INST RocketTile__GCB0 PIN 60 TYPE 3 INST DCache PIN 400 TYPE 4
-INST TilePRCIDomain__GC0 PIN 67: INST RocketTile__GCB0 PIN 61 TYPE 3 INST DCache PIN 401 TYPE 4
-INST TilePRCIDomain__GC0 PIN 68: INST RocketTile__GCB0 PIN 62 TYPE 3 INST DCache PIN 402 TYPE 4
-INST TilePRCIDomain__GC0 PIN 69: INST RocketTile__GCB0 PIN 63 TYPE 3 INST DCache PIN 403 TYPE 4
-INST TilePRCIDomain__GC0 PIN 70: INST RocketTile__GCB0 PIN 64 TYPE 3 INST DCache PIN 404 TYPE 4
-INST TilePRCIDomain__GC0 PIN 71: INST RocketTile__GCB0 PIN 65 TYPE 3 INST DCache PIN 405 TYPE 4
-INST TilePRCIDomain__GC0 PIN 72: INST RocketTile__GCB0 PIN 66 TYPE 3 INST DCache PIN 406 TYPE 4
-INST TilePRCIDomain__GC0 PIN 73: INST RocketTile__GCB0 PIN 67 TYPE 3 INST DCache PIN 407 TYPE 4
-INST TilePRCIDomain__GC0 PIN 74: INST RocketTile__GCB0 PIN 68 TYPE 3 INST DCache PIN 408 TYPE 4
-INST TilePRCIDomain__GC0 PIN 75: INST RocketTile__GCB0 PIN 69 TYPE 3 INST DCache PIN 409 TYPE 4
-INST TilePRCIDomain__GC0 PIN 76: INST RocketTile__GCB0 PIN 70 TYPE 3 INST DCache PIN 410 TYPE 4
-INST TilePRCIDomain__GC0 PIN 77: INST RocketTile__GCB0 PIN 71 TYPE 3 INST DCache PIN 411 TYPE 4
-INST TilePRCIDomain__GC0 PIN 78: INST RocketTile__GCB0 PIN 72 TYPE 3 INST DCache PIN 412 TYPE 4
-INST TilePRCIDomain__GC0 PIN 79: INST RocketTile__GCB0 PIN 73 TYPE 3 INST DCache PIN 413 TYPE 4
-INST RocketTile__GCB0 PIN 324: INST RocketTile__GCB0 PIN 325 TYPE 2 INST DCache PIN 465 TYPE 4
-INST RocketTile__GCB0 PIN 315: INST RocketTile__GCB0 PIN 326 TYPE 2 INST DCache PIN 466 TYPE 4
-INST RocketTile__GCB0 PIN 403: INST RocketTile__GCB0 PIN 465 TYPE 2 INST DCache PIN 605 TYPE 4
-INST RocketTile__GCB0 PIN 466: INST DCache PIN 606 TYPE 1 GENOME RocketTile__GCB0 PIN 466
-INST RocketTile__GCB0 PIN 467: INST DCache PIN 607 TYPE 1 GENOME RocketTile__GCB0 PIN 467
-INST RocketTile__GCB0 PIN 470: INST RocketTile__GCB0 PIN 532 TYPE 2 INST DCache PIN 672 TYPE 4
-INST RocketTile__GCB0 PIN 533: INST DCache PIN 673 TYPE 1 GENOME RocketTile__GCB0 PIN 533
-INST RocketTile__GCB0 PIN 534: INST DCache PIN 674 TYPE 1 GENOME RocketTile__GCB0 PIN 534
-INST RocketTile__GCB0 PIN 537: INST RocketTile__GCB0 PIN 599 TYPE 2 INST DCache PIN 739 TYPE 4
-INST RocketTile__GCB0 PIN 600: INST DCache PIN 740 TYPE 1 GENOME RocketTile__GCB0 PIN 600
-INST RocketTile__GCB0 PIN 601: INST DCache PIN 741 TYPE 1 GENOME RocketTile__GCB0 PIN 601
-INST RocketTile__GCB0 PIN 604: INST RocketTile__GCB0 PIN 666 TYPE 2 INST DCache PIN 806 TYPE 4
-INST RocketTile__GCB0 PIN 667: INST DCache PIN 807 TYPE 1 GENOME RocketTile__GCB0 PIN 667
-INST RocketTile__GCB0 PIN 668: INST DCache PIN 808 TYPE 1 GENOME RocketTile__GCB0 PIN 668
-INST RocketTile__GCB0 PIN 671: INST RocketTile__GCB0 PIN 733 TYPE 2 INST DCache PIN 873 TYPE 4
-INST RocketTile__GCB0 PIN 734: INST DCache PIN 874 TYPE 1 GENOME RocketTile__GCB0 PIN 734
-INST RocketTile__GCB0 PIN 735: INST DCache PIN 875 TYPE 1 GENOME RocketTile__GCB0 PIN 735
-INST RocketTile__GCB0 PIN 738: INST RocketTile__GCB0 PIN 800 TYPE 2 INST DCache PIN 940 TYPE 4
-INST RocketTile__GCB0 PIN 801: INST DCache PIN 941 TYPE 1 GENOME RocketTile__GCB0 PIN 801
-INST RocketTile__GCB0 PIN 802: INST DCache PIN 942 TYPE 1 GENOME RocketTile__GCB0 PIN 802
-INST RocketTile__GCB0 PIN 805: INST RocketTile__GCB0 PIN 867 TYPE 2 INST DCache PIN 1007 TYPE 4
-INST RocketTile__GCB0 PIN 868: INST DCache PIN 1008 TYPE 1 GENOME RocketTile__GCB0 PIN 868
-INST RocketTile__GCB0 PIN 869: INST DCache PIN 1009 TYPE 1 GENOME RocketTile__GCB0 PIN 869
-INST RocketTile__GCB0 PIN 872: INST RocketTile__GCB0 PIN 934 TYPE 2 INST DCache PIN 1074 TYPE 4
-INST RocketTile__GCB0 PIN 935: INST DCache PIN 1075 TYPE 1 GENOME RocketTile__GCB0 PIN 935
-INST RocketTile__GCB0 PIN 936: INST DCache PIN 1076 TYPE 1 GENOME RocketTile__GCB0 PIN 936
-INST DCache PIN 7: INST RocketTile__GCB0 PIN 1125 TYPE 0 GENOME DCache PIN 7
-INST DCache PIN 8: INST RocketTile__GCB0 PIN 1126 TYPE 0 GENOME DCache PIN 8
-INST DCache PIN 43: INST RocketTile__GCB0 PIN 1161 TYPE 0 GENOME DCache PIN 43
-INST DCache PIN 44: INST RocketTile__GCB0 PIN 1162 TYPE 0 GENOME DCache PIN 44
-INST DCache PIN 45: INST RocketTile__GCB0 PIN 1163 TYPE 0 GENOME DCache PIN 45
-INST DCache PIN 46: INST RocketTile__GCB0 PIN 1164 TYPE 0 GENOME DCache PIN 46
-INST DCache PIN 330: INST RocketTile__GCB0 PIN 1644 TYPE 0 GENOME DCache PIN 330
-INST DCache PIN 331: INST RocketTile__GCB0 PIN 1645 TYPE 0 GENOME DCache PIN 331
-INST FPU__GB2 PIN 317: INST FPU__GB1 PIN 162 TYPE 5
-INST FPU__GB2 PIN 323: INST FPU__GB1 PIN 137 TYPE 5
-INST FPU__GB2 PIN 393: INST FPU__GB1 PIN 1 TYPE 5
-INST FPU__GB2 PIN 171: INST FPU__GB1 PIN 525 TYPE 0 GENOME FPU__GB2 PIN 171
-INST FPU__GB2 PIN 172: INST FPU__GB1 PIN 526 TYPE 0 GENOME FPU__GB2 PIN 172
-INST FPU__GB2 PIN 173: INST FPU__GB1 PIN 527 TYPE 0 GENOME FPU__GB2 PIN 173
-INST FPU__GB2 PIN 174: INST FPU__GB1 PIN 528 TYPE 0 GENOME FPU__GB2 PIN 174
-INST FPU__GB2 PIN 306: INST FPU__GB1 PIN 531 TYPE 0 GENOME FPU__GB2 PIN 306
-INST FPU__GB2 PIN 307: INST FPU__GB1 PIN 532 TYPE 0 GENOME FPU__GB2 PIN 307
-INST FPU__GB2 PIN 308: INST FPU__GB1 PIN 533 TYPE 0 GENOME FPU__GB2 PIN 308
-INST DCache PIN 124: INST RocketTile__GCB0 PIN 1040 TYPE 3 INST FPU__GB1 PIN 641 TYPE 4
-INST DCache PIN 125: INST RocketTile__GCB0 PIN 1041 TYPE 3 INST FPU__GB1 PIN 642 TYPE 4
-INST DCache PIN 126: INST RocketTile__GCB0 PIN 1042 TYPE 3 INST FPU__GB1 PIN 643 TYPE 4
-INST DCache PIN 127: INST RocketTile__GCB0 PIN 1043 TYPE 3 INST FPU__GB1 PIN 644 TYPE 4
-INST DCache PIN 128: INST RocketTile__GCB0 PIN 1044 TYPE 3 INST FPU__GB1 PIN 645 TYPE 4
-INST DCache PIN 199: INST RocketTile__GCB0 PIN 1045 TYPE 3 INST FPU__GB1 PIN 646 TYPE 4
-INST DCache PIN 200: INST RocketTile__GCB0 PIN 1046 TYPE 3 INST FPU__GB1 PIN 647 TYPE 4
-INST DCache PIN 201: INST RocketTile__GCB0 PIN 1047 TYPE 3 INST FPU__GB1 PIN 648 TYPE 4
-INST DCache PIN 202: INST RocketTile__GCB0 PIN 1048 TYPE 3 INST FPU__GB1 PIN 649 TYPE 4
-INST DCache PIN 203: INST RocketTile__GCB0 PIN 1049 TYPE 3 INST FPU__GB1 PIN 650 TYPE 4
-INST DCache PIN 204: INST RocketTile__GCB0 PIN 1050 TYPE 3 INST FPU__GB1 PIN 651 TYPE 4
-INST DCache PIN 205: INST RocketTile__GCB0 PIN 1051 TYPE 3 INST FPU__GB1 PIN 652 TYPE 4
-INST DCache PIN 206: INST RocketTile__GCB0 PIN 1052 TYPE 3 INST FPU__GB1 PIN 653 TYPE 4
-INST DCache PIN 207: INST RocketTile__GCB0 PIN 1053 TYPE 3 INST FPU__GB1 PIN 654 TYPE 4
-INST DCache PIN 208: INST RocketTile__GCB0 PIN 1054 TYPE 3 INST FPU__GB1 PIN 655 TYPE 4
-INST DCache PIN 209: INST RocketTile__GCB0 PIN 1055 TYPE 3 INST FPU__GB1 PIN 656 TYPE 4
-INST DCache PIN 210: INST RocketTile__GCB0 PIN 1056 TYPE 3 INST FPU__GB1 PIN 657 TYPE 4
-INST DCache PIN 211: INST RocketTile__GCB0 PIN 1057 TYPE 3 INST FPU__GB1 PIN 658 TYPE 4
-INST DCache PIN 212: INST RocketTile__GCB0 PIN 1058 TYPE 3 INST FPU__GB1 PIN 659 TYPE 4
-INST DCache PIN 213: INST RocketTile__GCB0 PIN 1059 TYPE 3 INST FPU__GB1 PIN 660 TYPE 4
-INST DCache PIN 214: INST RocketTile__GCB0 PIN 1060 TYPE 3 INST FPU__GB1 PIN 661 TYPE 4
-INST DCache PIN 215: INST RocketTile__GCB0 PIN 1061 TYPE 3 INST FPU__GB1 PIN 662 TYPE 4
-INST DCache PIN 216: INST RocketTile__GCB0 PIN 1062 TYPE 3 INST FPU__GB1 PIN 663 TYPE 4
-INST DCache PIN 217: INST RocketTile__GCB0 PIN 1063 TYPE 3 INST FPU__GB1 PIN 664 TYPE 4
-INST DCache PIN 218: INST RocketTile__GCB0 PIN 1064 TYPE 3 INST FPU__GB1 PIN 665 TYPE 4
-INST DCache PIN 219: INST RocketTile__GCB0 PIN 1065 TYPE 3 INST FPU__GB1 PIN 666 TYPE 4
-INST DCache PIN 220: INST RocketTile__GCB0 PIN 1066 TYPE 3 INST FPU__GB1 PIN 667 TYPE 4
-INST DCache PIN 221: INST RocketTile__GCB0 PIN 1067 TYPE 3 INST FPU__GB1 PIN 668 TYPE 4
-INST DCache PIN 222: INST RocketTile__GCB0 PIN 1068 TYPE 3 INST FPU__GB1 PIN 669 TYPE 4
-INST DCache PIN 223: INST RocketTile__GCB0 PIN 1069 TYPE 3 INST FPU__GB1 PIN 670 TYPE 4
-INST DCache PIN 224: INST RocketTile__GCB0 PIN 1070 TYPE 3 INST FPU__GB1 PIN 671 TYPE 4
-INST DCache PIN 225: INST RocketTile__GCB0 PIN 1071 TYPE 3 INST FPU__GB1 PIN 672 TYPE 4
-INST DCache PIN 226: INST RocketTile__GCB0 PIN 1072 TYPE 3 INST FPU__GB1 PIN 673 TYPE 4
-INST DCache PIN 227: INST RocketTile__GCB0 PIN 1073 TYPE 3 INST FPU__GB1 PIN 674 TYPE 4
-INST DCache PIN 228: INST RocketTile__GCB0 PIN 1074 TYPE 3 INST FPU__GB1 PIN 675 TYPE 4
-INST DCache PIN 229: INST RocketTile__GCB0 PIN 1075 TYPE 3 INST FPU__GB1 PIN 676 TYPE 4
-INST DCache PIN 230: INST RocketTile__GCB0 PIN 1076 TYPE 3 INST FPU__GB1 PIN 677 TYPE 4
-INST DCache PIN 231: INST RocketTile__GCB0 PIN 1077 TYPE 3 INST FPU__GB1 PIN 678 TYPE 4
-INST DCache PIN 232: INST RocketTile__GCB0 PIN 1078 TYPE 3 INST FPU__GB1 PIN 679 TYPE 4
-INST DCache PIN 233: INST RocketTile__GCB0 PIN 1079 TYPE 3 INST FPU__GB1 PIN 680 TYPE 4
-INST DCache PIN 234: INST RocketTile__GCB0 PIN 1080 TYPE 3 INST FPU__GB1 PIN 681 TYPE 4
-INST DCache PIN 235: INST RocketTile__GCB0 PIN 1081 TYPE 3 INST FPU__GB1 PIN 682 TYPE 4
-INST DCache PIN 236: INST RocketTile__GCB0 PIN 1082 TYPE 3 INST FPU__GB1 PIN 683 TYPE 4
-INST DCache PIN 237: INST RocketTile__GCB0 PIN 1083 TYPE 3 INST FPU__GB1 PIN 684 TYPE 4
-INST DCache PIN 238: INST RocketTile__GCB0 PIN 1084 TYPE 3 INST FPU__GB1 PIN 685 TYPE 4
-INST DCache PIN 239: INST RocketTile__GCB0 PIN 1085 TYPE 3 INST FPU__GB1 PIN 686 TYPE 4
-INST DCache PIN 240: INST RocketTile__GCB0 PIN 1086 TYPE 3 INST FPU__GB1 PIN 687 TYPE 4
-INST DCache PIN 241: INST RocketTile__GCB0 PIN 1087 TYPE 3 INST FPU__GB1 PIN 688 TYPE 4
-INST DCache PIN 242: INST RocketTile__GCB0 PIN 1088 TYPE 3 INST FPU__GB1 PIN 689 TYPE 4
-INST DCache PIN 243: INST RocketTile__GCB0 PIN 1089 TYPE 3 INST FPU__GB1 PIN 690 TYPE 4
-INST DCache PIN 244: INST RocketTile__GCB0 PIN 1090 TYPE 3 INST FPU__GB1 PIN 691 TYPE 4
-INST DCache PIN 245: INST RocketTile__GCB0 PIN 1091 TYPE 3 INST FPU__GB1 PIN 692 TYPE 4
-INST DCache PIN 246: INST RocketTile__GCB0 PIN 1092 TYPE 3 INST FPU__GB1 PIN 693 TYPE 4
-INST DCache PIN 247: INST RocketTile__GCB0 PIN 1093 TYPE 3 INST FPU__GB1 PIN 694 TYPE 4
-INST DCache PIN 248: INST RocketTile__GCB0 PIN 1094 TYPE 3 INST FPU__GB1 PIN 695 TYPE 4
-INST DCache PIN 249: INST RocketTile__GCB0 PIN 1095 TYPE 3 INST FPU__GB1 PIN 696 TYPE 4
-INST DCache PIN 250: INST RocketTile__GCB0 PIN 1096 TYPE 3 INST FPU__GB1 PIN 697 TYPE 4
-INST DCache PIN 251: INST RocketTile__GCB0 PIN 1097 TYPE 3 INST FPU__GB1 PIN 698 TYPE 4
-INST DCache PIN 252: INST RocketTile__GCB0 PIN 1098 TYPE 3 INST FPU__GB1 PIN 699 TYPE 4
-INST DCache PIN 253: INST RocketTile__GCB0 PIN 1099 TYPE 3 INST FPU__GB1 PIN 700 TYPE 4
-INST DCache PIN 254: INST RocketTile__GCB0 PIN 1100 TYPE 3 INST FPU__GB1 PIN 701 TYPE 4
-INST DCache PIN 255: INST RocketTile__GCB0 PIN 1101 TYPE 3 INST FPU__GB1 PIN 702 TYPE 4
-INST DCache PIN 256: INST RocketTile__GCB0 PIN 1102 TYPE 3 INST FPU__GB1 PIN 703 TYPE 4
-INST DCache PIN 257: INST RocketTile__GCB0 PIN 1103 TYPE 3 INST FPU__GB1 PIN 704 TYPE 4
-INST DCache PIN 258: INST RocketTile__GCB0 PIN 1104 TYPE 3 INST FPU__GB1 PIN 705 TYPE 4
-INST DCache PIN 259: INST RocketTile__GCB0 PIN 1105 TYPE 3 INST FPU__GB1 PIN 706 TYPE 4
-INST DCache PIN 260: INST RocketTile__GCB0 PIN 1106 TYPE 3 INST FPU__GB1 PIN 707 TYPE 4
-INST DCache PIN 261: INST RocketTile__GCB0 PIN 1107 TYPE 3 INST FPU__GB1 PIN 708 TYPE 4
-INST DCache PIN 262: INST RocketTile__GCB0 PIN 1108 TYPE 3 INST FPU__GB1 PIN 709 TYPE 4
-INST DCache PIN 132: INST RocketTile__GCB0 PIN 1039 TYPE 3 INST FPU__GB1 PIN 710 TYPE 4
-INST RocketTile__GCB0 PIN 198: INST TilePRCIDomain__GC0 PIN 531 TYPE 0 GENOME RocketTile__GCB0 PIN 198
-INST RocketTile__GCB0 PIN 202: INST TilePRCIDomain__GC0 PIN 732 TYPE 0 GENOME RocketTile__GCB0 PIN 202
-INST RocketTile__GCB0 PIN 203: INST TilePRCIDomain__GC0 PIN 733 TYPE 0 GENOME RocketTile__GCB0 PIN 203
-INST VCU118RocketSystem__GC0 PIN 331: INST NON_GENOME PIN 34 TYPE 0 GENOME VCU118RocketSystem__GC0 PIN 331
-INST VCU118RocketSystem__GC0 PIN 334: INST VCU118RocketSystem__GC0 PIN 335 TYPE 2 INST NON_GENOME PIN 46 TYPE 4 INST VCU118RocketSystem__GC0 PIN 336 TYPE 2 INST NON_GENOME PIN 47 TYPE 4
-INST RocketTile__GCB0 PIN 2: GENOME RocketTile__GCB0 PIN 2
-INST RocketTile__GCB0 PIN 3: GENOME RocketTile__GCB0 PIN 3
-INST RocketTile__GCB0 PIN 4: GENOME RocketTile__GCB0 PIN 4
-INST RocketTile__GCB0 PIN 5: GENOME RocketTile__GCB0 PIN 5
-INST RocketTile__GCB0 PIN 6: GENOME RocketTile__GCB0 PIN 6
-INST RocketTile__GCB0 PIN 7: GENOME RocketTile__GCB0 PIN 7
-INST RocketTile__GCB0 PIN 8: GENOME RocketTile__GCB0 PIN 8
-INST RocketTile__GCB0 PIN 9: GENOME RocketTile__GCB0 PIN 9
-INST RocketTile__GCB0 PIN 10: GENOME RocketTile__GCB0 PIN 10
-INST RocketTile__GCB0 PIN 11: GENOME RocketTile__GCB0 PIN 11
-INST RocketTile__GCB0 PIN 12: GENOME RocketTile__GCB0 PIN 12
-INST RocketTile__GCB0 PIN 13: GENOME RocketTile__GCB0 PIN 13
-INST RocketTile__GCB0 PIN 14: GENOME RocketTile__GCB0 PIN 14
-INST RocketTile__GCB0 PIN 15: GENOME RocketTile__GCB0 PIN 15
-INST RocketTile__GCB0 PIN 16: GENOME RocketTile__GCB0 PIN 16
-INST RocketTile__GCB0 PIN 17: GENOME RocketTile__GCB0 PIN 17
-INST RocketTile__GCB0 PIN 18: GENOME RocketTile__GCB0 PIN 18
-INST RocketTile__GCB0 PIN 19: GENOME RocketTile__GCB0 PIN 19
-INST RocketTile__GCB0 PIN 20: GENOME RocketTile__GCB0 PIN 20
-INST RocketTile__GCB0 PIN 21: GENOME RocketTile__GCB0 PIN 21
-INST RocketTile__GCB0 PIN 22: GENOME RocketTile__GCB0 PIN 22
-INST RocketTile__GCB0 PIN 23: GENOME RocketTile__GCB0 PIN 23
-INST RocketTile__GCB0 PIN 24: GENOME RocketTile__GCB0 PIN 24
-INST RocketTile__GCB0 PIN 25: GENOME RocketTile__GCB0 PIN 25
-INST RocketTile__GCB0 PIN 26: GENOME RocketTile__GCB0 PIN 26
-INST RocketTile__GCB0 PIN 27: GENOME RocketTile__GCB0 PIN 27
-INST RocketTile__GCB0 PIN 28: GENOME RocketTile__GCB0 PIN 28
-INST RocketTile__GCB0 PIN 29: GENOME RocketTile__GCB0 PIN 29
-INST RocketTile__GCB0 PIN 30: GENOME RocketTile__GCB0 PIN 30
-INST RocketTile__GCB0 PIN 31: GENOME RocketTile__GCB0 PIN 31
-INST RocketTile__GCB0 PIN 32: GENOME RocketTile__GCB0 PIN 32
-INST RocketTile__GCB0 PIN 33: GENOME RocketTile__GCB0 PIN 33
-INST RocketTile__GCB0 PIN 34: GENOME RocketTile__GCB0 PIN 34
-INST RocketTile__GCB0 PIN 35: GENOME RocketTile__GCB0 PIN 35
-INST RocketTile__GCB0 PIN 36: GENOME RocketTile__GCB0 PIN 36
-INST RocketTile__GCB0 PIN 37: GENOME RocketTile__GCB0 PIN 37
-INST RocketTile__GCB0 PIN 38: GENOME RocketTile__GCB0 PIN 38
-INST RocketTile__GCB0 PIN 39: GENOME RocketTile__GCB0 PIN 39
-INST RocketTile__GCB0 PIN 40: GENOME RocketTile__GCB0 PIN 40
-INST RocketTile__GCB0 PIN 41: GENOME RocketTile__GCB0 PIN 41
-INST RocketTile__GCB0 PIN 42: GENOME RocketTile__GCB0 PIN 42
-INST RocketTile__GCB0 PIN 43: GENOME RocketTile__GCB0 PIN 43
-INST RocketTile__GCB0 PIN 44: GENOME RocketTile__GCB0 PIN 44
-INST RocketTile__GCB0 PIN 45: GENOME RocketTile__GCB0 PIN 45
-INST RocketTile__GCB0 PIN 46: GENOME RocketTile__GCB0 PIN 46
-INST RocketTile__GCB0 PIN 47: GENOME RocketTile__GCB0 PIN 47
-INST RocketTile__GCB0 PIN 48: GENOME RocketTile__GCB0 PIN 48
-INST RocketTile__GCB0 PIN 49: GENOME RocketTile__GCB0 PIN 49
-INST RocketTile__GCB0 PIN 50: GENOME RocketTile__GCB0 PIN 50
-INST RocketTile__GCB0 PIN 51: GENOME RocketTile__GCB0 PIN 51
-INST RocketTile__GCB0 PIN 52: GENOME RocketTile__GCB0 PIN 52
-INST RocketTile__GCB0 PIN 53: GENOME RocketTile__GCB0 PIN 53
-INST RocketTile__GCB0 PIN 54: GENOME RocketTile__GCB0 PIN 54
-INST RocketTile__GCB0 PIN 55: GENOME RocketTile__GCB0 PIN 55
-INST RocketTile__GCB0 PIN 56: GENOME RocketTile__GCB0 PIN 56
-INST RocketTile__GCB0 PIN 57: GENOME RocketTile__GCB0 PIN 57
-INST RocketTile__GCB0 PIN 58: GENOME RocketTile__GCB0 PIN 58
-INST RocketTile__GCB0 PIN 59: GENOME RocketTile__GCB0 PIN 59
-INST RocketTile__GCB0 PIN 60: GENOME RocketTile__GCB0 PIN 60
-INST RocketTile__GCB0 PIN 61: GENOME RocketTile__GCB0 PIN 61
-INST RocketTile__GCB0 PIN 62: GENOME RocketTile__GCB0 PIN 62
-INST RocketTile__GCB0 PIN 63: GENOME RocketTile__GCB0 PIN 63
-INST RocketTile__GCB0 PIN 64: GENOME RocketTile__GCB0 PIN 64
-INST RocketTile__GCB0 PIN 65: GENOME RocketTile__GCB0 PIN 65
-INST RocketTile__GCB0 PIN 66: GENOME RocketTile__GCB0 PIN 66
-INST RocketTile__GCB0 PIN 67: GENOME RocketTile__GCB0 PIN 67
-INST RocketTile__GCB0 PIN 68: GENOME RocketTile__GCB0 PIN 68
-INST RocketTile__GCB0 PIN 69: GENOME RocketTile__GCB0 PIN 69
-INST RocketTile__GCB0 PIN 70: GENOME RocketTile__GCB0 PIN 70
-INST RocketTile__GCB0 PIN 71: GENOME RocketTile__GCB0 PIN 71
-INST RocketTile__GCB0 PIN 72: GENOME RocketTile__GCB0 PIN 72
-INST RocketTile__GCB0 PIN 73: GENOME RocketTile__GCB0 PIN 73
-INST RocketTile__GCB0 PIN 74: GENOME RocketTile__GCB0 PIN 74
-INST RocketTile__GCB0 PIN 325: GENOME RocketTile__GCB0 PIN 325
-INST RocketTile__GCB0 PIN 326: GENOME RocketTile__GCB0 PIN 326
-INST RocketTile__GCB0 PIN 465: GENOME RocketTile__GCB0 PIN 465
-INST RocketTile__GCB0 PIN 532: GENOME RocketTile__GCB0 PIN 532
-INST RocketTile__GCB0 PIN 599: GENOME RocketTile__GCB0 PIN 599
-INST RocketTile__GCB0 PIN 666: GENOME RocketTile__GCB0 PIN 666
-INST RocketTile__GCB0 PIN 733: GENOME RocketTile__GCB0 PIN 733
-INST RocketTile__GCB0 PIN 800: GENOME RocketTile__GCB0 PIN 800
-INST RocketTile__GCB0 PIN 867: GENOME RocketTile__GCB0 PIN 867
-INST RocketTile__GCB0 PIN 934: GENOME RocketTile__GCB0 PIN 934
-INST RocketTile__GCB0 PIN 1037: GENOME RocketTile__GCB0 PIN 1037
-INST RocketTile__GCB0 PIN 1038: GENOME RocketTile__GCB0 PIN 1038
-INST RocketTile__GCB0 PIN 1039: GENOME RocketTile__GCB0 PIN 1039
-INST RocketTile__GCB0 PIN 1040: GENOME RocketTile__GCB0 PIN 1040
-INST RocketTile__GCB0 PIN 1041: GENOME RocketTile__GCB0 PIN 1041
-INST RocketTile__GCB0 PIN 1042: GENOME RocketTile__GCB0 PIN 1042
-INST RocketTile__GCB0 PIN 1043: GENOME RocketTile__GCB0 PIN 1043
-INST RocketTile__GCB0 PIN 1044: GENOME RocketTile__GCB0 PIN 1044
-INST RocketTile__GCB0 PIN 1045: GENOME RocketTile__GCB0 PIN 1045
-INST RocketTile__GCB0 PIN 1046: GENOME RocketTile__GCB0 PIN 1046
-INST RocketTile__GCB0 PIN 1047: GENOME RocketTile__GCB0 PIN 1047
-INST RocketTile__GCB0 PIN 1048: GENOME RocketTile__GCB0 PIN 1048
-INST RocketTile__GCB0 PIN 1049: GENOME RocketTile__GCB0 PIN 1049
-INST RocketTile__GCB0 PIN 1050: GENOME RocketTile__GCB0 PIN 1050
-INST RocketTile__GCB0 PIN 1051: GENOME RocketTile__GCB0 PIN 1051
-INST RocketTile__GCB0 PIN 1052: GENOME RocketTile__GCB0 PIN 1052
-INST RocketTile__GCB0 PIN 1053: GENOME RocketTile__GCB0 PIN 1053
-INST RocketTile__GCB0 PIN 1054: GENOME RocketTile__GCB0 PIN 1054
-INST RocketTile__GCB0 PIN 1055: GENOME RocketTile__GCB0 PIN 1055
-INST RocketTile__GCB0 PIN 1056: GENOME RocketTile__GCB0 PIN 1056
-INST RocketTile__GCB0 PIN 1057: GENOME RocketTile__GCB0 PIN 1057
-INST RocketTile__GCB0 PIN 1058: GENOME RocketTile__GCB0 PIN 1058
-INST RocketTile__GCB0 PIN 1059: GENOME RocketTile__GCB0 PIN 1059
-INST RocketTile__GCB0 PIN 1060: GENOME RocketTile__GCB0 PIN 1060
-INST RocketTile__GCB0 PIN 1061: GENOME RocketTile__GCB0 PIN 1061
-INST RocketTile__GCB0 PIN 1062: GENOME RocketTile__GCB0 PIN 1062
-INST RocketTile__GCB0 PIN 1063: GENOME RocketTile__GCB0 PIN 1063
-INST RocketTile__GCB0 PIN 1064: GENOME RocketTile__GCB0 PIN 1064
-INST RocketTile__GCB0 PIN 1065: GENOME RocketTile__GCB0 PIN 1065
-INST RocketTile__GCB0 PIN 1066: GENOME RocketTile__GCB0 PIN 1066
-INST RocketTile__GCB0 PIN 1067: GENOME RocketTile__GCB0 PIN 1067
-INST RocketTile__GCB0 PIN 1068: GENOME RocketTile__GCB0 PIN 1068
-INST RocketTile__GCB0 PIN 1069: GENOME RocketTile__GCB0 PIN 1069
-INST RocketTile__GCB0 PIN 1070: GENOME RocketTile__GCB0 PIN 1070
-INST RocketTile__GCB0 PIN 1071: GENOME RocketTile__GCB0 PIN 1071
-INST RocketTile__GCB0 PIN 1072: GENOME RocketTile__GCB0 PIN 1072
-INST RocketTile__GCB0 PIN 1073: GENOME RocketTile__GCB0 PIN 1073
-INST RocketTile__GCB0 PIN 1074: GENOME RocketTile__GCB0 PIN 1074
-INST RocketTile__GCB0 PIN 1075: GENOME RocketTile__GCB0 PIN 1075
-INST RocketTile__GCB0 PIN 1076: GENOME RocketTile__GCB0 PIN 1076
-INST RocketTile__GCB0 PIN 1077: GENOME RocketTile__GCB0 PIN 1077
-INST RocketTile__GCB0 PIN 1078: GENOME RocketTile__GCB0 PIN 1078
-INST RocketTile__GCB0 PIN 1079: GENOME RocketTile__GCB0 PIN 1079
-INST RocketTile__GCB0 PIN 1080: GENOME RocketTile__GCB0 PIN 1080
-INST RocketTile__GCB0 PIN 1081: GENOME RocketTile__GCB0 PIN 1081
-INST RocketTile__GCB0 PIN 1082: GENOME RocketTile__GCB0 PIN 1082
-INST RocketTile__GCB0 PIN 1083: GENOME RocketTile__GCB0 PIN 1083
-INST RocketTile__GCB0 PIN 1084: GENOME RocketTile__GCB0 PIN 1084
-INST RocketTile__GCB0 PIN 1085: GENOME RocketTile__GCB0 PIN 1085
-INST RocketTile__GCB0 PIN 1086: GENOME RocketTile__GCB0 PIN 1086
-INST RocketTile__GCB0 PIN 1087: GENOME RocketTile__GCB0 PIN 1087
-INST RocketTile__GCB0 PIN 1088: GENOME RocketTile__GCB0 PIN 1088
-INST RocketTile__GCB0 PIN 1089: GENOME RocketTile__GCB0 PIN 1089
-INST RocketTile__GCB0 PIN 1090: GENOME RocketTile__GCB0 PIN 1090
-INST RocketTile__GCB0 PIN 1091: GENOME RocketTile__GCB0 PIN 1091
-INST RocketTile__GCB0 PIN 1092: GENOME RocketTile__GCB0 PIN 1092
-INST RocketTile__GCB0 PIN 1093: GENOME RocketTile__GCB0 PIN 1093
-INST RocketTile__GCB0 PIN 1094: GENOME RocketTile__GCB0 PIN 1094
-INST RocketTile__GCB0 PIN 1095: GENOME RocketTile__GCB0 PIN 1095
-INST RocketTile__GCB0 PIN 1096: GENOME RocketTile__GCB0 PIN 1096
-INST RocketTile__GCB0 PIN 1097: GENOME RocketTile__GCB0 PIN 1097
-INST RocketTile__GCB0 PIN 1098: GENOME RocketTile__GCB0 PIN 1098
-INST RocketTile__GCB0 PIN 1099: GENOME RocketTile__GCB0 PIN 1099
-INST RocketTile__GCB0 PIN 1100: GENOME RocketTile__GCB0 PIN 1100
-INST RocketTile__GCB0 PIN 1101: GENOME RocketTile__GCB0 PIN 1101
-INST RocketTile__GCB0 PIN 1102: GENOME RocketTile__GCB0 PIN 1102
-INST RocketTile__GCB0 PIN 1103: GENOME RocketTile__GCB0 PIN 1103
-INST RocketTile__GCB0 PIN 1104: GENOME RocketTile__GCB0 PIN 1104
-INST RocketTile__GCB0 PIN 1105: GENOME RocketTile__GCB0 PIN 1105
-INST RocketTile__GCB0 PIN 1106: GENOME RocketTile__GCB0 PIN 1106
-INST RocketTile__GCB0 PIN 1107: GENOME RocketTile__GCB0 PIN 1107
-INST RocketTile__GCB0 PIN 1108: GENOME RocketTile__GCB0 PIN 1108
-INST RocketTile__GCB0 PIN 1125: GENOME RocketTile__GCB0 PIN 1125
-INST RocketTile__GCB0 PIN 1126: GENOME RocketTile__GCB0 PIN 1126
-INST RocketTile__GCB0 PIN 1161: GENOME RocketTile__GCB0 PIN 1161
-INST RocketTile__GCB0 PIN 1162: GENOME RocketTile__GCB0 PIN 1162
-INST RocketTile__GCB0 PIN 1163: GENOME RocketTile__GCB0 PIN 1163
-INST RocketTile__GCB0 PIN 1164: GENOME RocketTile__GCB0 PIN 1164
-INST RocketTile__GCB0 PIN 1644: GENOME RocketTile__GCB0 PIN 1644
-INST RocketTile__GCB0 PIN 1645: GENOME RocketTile__GCB0 PIN 1645
-GENOME NON_GENOME PIN 1241: GENOME NON_GENOME PIN 2
-GENOME NON_GENOME PIN 2: GENOME NON_GENOME PIN 1241
-GENOME NON_GENOME PIN 1242: GENOME NON_GENOME PIN 3
-GENOME NON_GENOME PIN 3: GENOME NON_GENOME PIN 1242
-GENOME NON_GENOME PIN 1243: GENOME NON_GENOME PIN 4
-GENOME NON_GENOME PIN 4: GENOME NON_GENOME PIN 1243
-GENOME NON_GENOME PIN 1246: GENOME NON_GENOME PIN 5
-GENOME NON_GENOME PIN 5: GENOME NON_GENOME PIN 1246
-GENOME NON_GENOME PIN 1247: GENOME NON_GENOME PIN 6
-GENOME NON_GENOME PIN 6: GENOME NON_GENOME PIN 1247
-GENOME NON_GENOME PIN 1248: GENOME NON_GENOME PIN 7
-GENOME NON_GENOME PIN 7: GENOME NON_GENOME PIN 1248
-GENOME NON_GENOME PIN 1249: GENOME NON_GENOME PIN 8
-GENOME NON_GENOME PIN 8: GENOME NON_GENOME PIN 1249
-GENOME NON_GENOME PIN 1252: GENOME NON_GENOME PIN 9
-GENOME NON_GENOME PIN 9: GENOME NON_GENOME PIN 1252
-GENOME NON_GENOME PIN 1253: GENOME NON_GENOME PIN 10
-GENOME NON_GENOME PIN 10: GENOME NON_GENOME PIN 1253
-GENOME NON_GENOME PIN 1254: GENOME NON_GENOME PIN 11
-GENOME NON_GENOME PIN 11: GENOME NON_GENOME PIN 1254
-GENOME NON_GENOME PIN 1255: GENOME NON_GENOME PIN 12
-GENOME NON_GENOME PIN 12: GENOME NON_GENOME PIN 1255
-GENOME NON_GENOME PIN 1256: GENOME NON_GENOME PIN 13
-GENOME NON_GENOME PIN 13: GENOME NON_GENOME PIN 1256
-GENOME NON_GENOME PIN 1257: GENOME NON_GENOME PIN 14
-GENOME NON_GENOME PIN 14: GENOME NON_GENOME PIN 1257
-GENOME NON_GENOME PIN 1258: GENOME NON_GENOME PIN 15
-GENOME NON_GENOME PIN 15: GENOME NON_GENOME PIN 1258
-GENOME NON_GENOME PIN 1259: GENOME NON_GENOME PIN 16
-GENOME NON_GENOME PIN 16: GENOME NON_GENOME PIN 1259
-GENOME NON_GENOME PIN 1260: GENOME NON_GENOME PIN 17
-GENOME NON_GENOME PIN 17: GENOME NON_GENOME PIN 1260
-GENOME NON_GENOME PIN 1261: GENOME NON_GENOME PIN 18
-GENOME NON_GENOME PIN 18: GENOME NON_GENOME PIN 1261
-GENOME NON_GENOME PIN 1262: GENOME NON_GENOME PIN 19
-GENOME NON_GENOME PIN 19: GENOME NON_GENOME PIN 1262
-GENOME NON_GENOME PIN 1263: GENOME NON_GENOME PIN 20
-GENOME NON_GENOME PIN 20: GENOME NON_GENOME PIN 1263
-GENOME NON_GENOME PIN 1264: GENOME NON_GENOME PIN 21
-GENOME NON_GENOME PIN 21: GENOME NON_GENOME PIN 1264
-GENOME NON_GENOME PIN 1265: GENOME NON_GENOME PIN 22
-GENOME NON_GENOME PIN 22: GENOME NON_GENOME PIN 1265
-GENOME NON_GENOME PIN 1266: GENOME NON_GENOME PIN 23
-GENOME NON_GENOME PIN 23: GENOME NON_GENOME PIN 1266
-GENOME NON_GENOME PIN 1267: GENOME NON_GENOME PIN 24
-GENOME NON_GENOME PIN 24: GENOME NON_GENOME PIN 1267
-GENOME NON_GENOME PIN 1268: GENOME NON_GENOME PIN 25
-GENOME NON_GENOME PIN 25: GENOME NON_GENOME PIN 1268
-GENOME NON_GENOME PIN 1269: GENOME NON_GENOME PIN 26
-GENOME NON_GENOME PIN 26: GENOME NON_GENOME PIN 1269
-GENOME NON_GENOME PIN 1270: GENOME NON_GENOME PIN 27
-GENOME NON_GENOME PIN 27: GENOME NON_GENOME PIN 1270
-GENOME NON_GENOME PIN 1271: GENOME NON_GENOME PIN 28
-GENOME NON_GENOME PIN 28: GENOME NON_GENOME PIN 1271
-GENOME NON_GENOME PIN 1272: GENOME NON_GENOME PIN 29
-GENOME NON_GENOME PIN 29: GENOME NON_GENOME PIN 1272
-GENOME NON_GENOME PIN 1273: GENOME NON_GENOME PIN 30
-GENOME NON_GENOME PIN 30: GENOME NON_GENOME PIN 1273
-GENOME NON_GENOME PIN 1274: GENOME NON_GENOME PIN 31
-GENOME NON_GENOME PIN 31: GENOME NON_GENOME PIN 1274
-GENOME NON_GENOME PIN 1275: GENOME NON_GENOME PIN 32
-GENOME NON_GENOME PIN 32: GENOME NON_GENOME PIN 1275
-GENOME NON_GENOME PIN 1276: GENOME NON_GENOME PIN 33
-GENOME NON_GENOME PIN 33: GENOME NON_GENOME PIN 1276
-GENOME NON_GENOME PIN 1277: GENOME NON_GENOME PIN 34
-GENOME NON_GENOME PIN 34: GENOME NON_GENOME PIN 1277
-GENOME NON_GENOME PIN 1278: GENOME NON_GENOME PIN 35
-GENOME NON_GENOME PIN 35: GENOME NON_GENOME PIN 1278
-GENOME NON_GENOME PIN 1279: GENOME NON_GENOME PIN 36
-GENOME NON_GENOME PIN 36: GENOME NON_GENOME PIN 1279
-GENOME NON_GENOME PIN 1280: GENOME NON_GENOME PIN 37
-GENOME NON_GENOME PIN 37: GENOME NON_GENOME PIN 1280
-GENOME NON_GENOME PIN 1281: GENOME NON_GENOME PIN 38
-GENOME NON_GENOME PIN 38: GENOME NON_GENOME PIN 1281
-GENOME NON_GENOME PIN 1282: GENOME NON_GENOME PIN 39
-GENOME NON_GENOME PIN 39: GENOME NON_GENOME PIN 1282
-GENOME NON_GENOME PIN 1283: GENOME NON_GENOME PIN 40
-GENOME NON_GENOME PIN 40: GENOME NON_GENOME PIN 1283
-GENOME NON_GENOME PIN 1284: GENOME NON_GENOME PIN 41
-GENOME NON_GENOME PIN 41: GENOME NON_GENOME PIN 1284
-GENOME NON_GENOME PIN 1285: GENOME NON_GENOME PIN 42
-GENOME NON_GENOME PIN 42: GENOME NON_GENOME PIN 1285
-GENOME NON_GENOME PIN 1286: GENOME NON_GENOME PIN 43
-GENOME NON_GENOME PIN 43: GENOME NON_GENOME PIN 1286
-GENOME NON_GENOME PIN 1287: GENOME NON_GENOME PIN 44
-GENOME NON_GENOME PIN 44: GENOME NON_GENOME PIN 1287
-GENOME NON_GENOME PIN 1288: GENOME NON_GENOME PIN 45
-GENOME NON_GENOME PIN 45: GENOME NON_GENOME PIN 1288
-GENOME NON_GENOME PIN 1289: GENOME NON_GENOME PIN 46
-GENOME NON_GENOME PIN 46: GENOME NON_GENOME PIN 1289
-GENOME NON_GENOME PIN 1290: GENOME NON_GENOME PIN 47
-GENOME NON_GENOME PIN 1291: GENOME NON_GENOME PIN 48
-GENOME NON_GENOME PIN 48: GENOME NON_GENOME PIN 1291
-GENOME NON_GENOME PIN 1292: GENOME NON_GENOME PIN 49
-GENOME NON_GENOME PIN 49: GENOME NON_GENOME PIN 1292
-GENOME NON_GENOME PIN 1293: GENOME NON_GENOME PIN 50
-GENOME NON_GENOME PIN 50: GENOME NON_GENOME PIN 1293
-GENOME NON_GENOME PIN 1294: GENOME NON_GENOME PIN 51
-GENOME NON_GENOME PIN 51: GENOME NON_GENOME PIN 1294
-GENOME NON_GENOME PIN 1295: GENOME NON_GENOME PIN 52
-GENOME NON_GENOME PIN 52: GENOME NON_GENOME PIN 1295
-GENOME NON_GENOME PIN 1296: GENOME NON_GENOME PIN 53
-GENOME NON_GENOME PIN 53: GENOME NON_GENOME PIN 1296
-GENOME NON_GENOME PIN 1297: GENOME NON_GENOME PIN 54
-GENOME NON_GENOME PIN 54: GENOME NON_GENOME PIN 1297
-GENOME NON_GENOME PIN 1298: GENOME NON_GENOME PIN 55
-GENOME NON_GENOME PIN 55: GENOME NON_GENOME PIN 1298
-GENOME NON_GENOME PIN 1299: GENOME NON_GENOME PIN 56
-GENOME NON_GENOME PIN 56: GENOME NON_GENOME PIN 1299
-GENOME NON_GENOME PIN 1300: GENOME NON_GENOME PIN 57
-GENOME NON_GENOME PIN 57: GENOME NON_GENOME PIN 1300
-GENOME NON_GENOME PIN 1301: GENOME NON_GENOME PIN 58
-GENOME NON_GENOME PIN 58: GENOME NON_GENOME PIN 1301
-GENOME NON_GENOME PIN 1302: GENOME NON_GENOME PIN 59
-GENOME NON_GENOME PIN 59: GENOME NON_GENOME PIN 1302
-GENOME NON_GENOME PIN 1303: GENOME NON_GENOME PIN 60
-GENOME NON_GENOME PIN 60: GENOME NON_GENOME PIN 1303
-GENOME NON_GENOME PIN 1304: GENOME NON_GENOME PIN 61
-GENOME NON_GENOME PIN 61: GENOME NON_GENOME PIN 1304
-GENOME NON_GENOME PIN 1305: GENOME NON_GENOME PIN 62
-GENOME NON_GENOME PIN 62: GENOME NON_GENOME PIN 1305
-GENOME NON_GENOME PIN 1306: GENOME NON_GENOME PIN 63
-GENOME NON_GENOME PIN 63: GENOME NON_GENOME PIN 1306
-GENOME NON_GENOME PIN 1307: GENOME NON_GENOME PIN 64
-GENOME NON_GENOME PIN 64: GENOME NON_GENOME PIN 1307
-GENOME NON_GENOME PIN 1308: GENOME NON_GENOME PIN 65
-GENOME NON_GENOME PIN 65: GENOME NON_GENOME PIN 1308
-GENOME NON_GENOME PIN 1309: GENOME NON_GENOME PIN 66
-GENOME NON_GENOME PIN 66: GENOME NON_GENOME PIN 1309
-GENOME NON_GENOME PIN 1310: GENOME NON_GENOME PIN 67
-GENOME NON_GENOME PIN 67: GENOME NON_GENOME PIN 1310
-GENOME NON_GENOME PIN 1311: GENOME NON_GENOME PIN 68
-GENOME NON_GENOME PIN 68: GENOME NON_GENOME PIN 1311
-GENOME NON_GENOME PIN 1312: GENOME NON_GENOME PIN 69
-GENOME NON_GENOME PIN 69: GENOME NON_GENOME PIN 1312
-GENOME NON_GENOME PIN 1313: GENOME NON_GENOME PIN 70
-GENOME NON_GENOME PIN 70: GENOME NON_GENOME PIN 1313
-GENOME NON_GENOME PIN 1314: GENOME NON_GENOME PIN 71
-GENOME NON_GENOME PIN 71: GENOME NON_GENOME PIN 1314
-GENOME NON_GENOME PIN 1315: GENOME NON_GENOME PIN 72
-GENOME NON_GENOME PIN 72: GENOME NON_GENOME PIN 1315
-GENOME NON_GENOME PIN 1316: GENOME NON_GENOME PIN 73
-GENOME NON_GENOME PIN 73: GENOME NON_GENOME PIN 1316
-GENOME NON_GENOME PIN 83: GENOME NON_GENOME PIN 119 GENOME NON_GENOME PIN 120
-GENOME NON_GENOME PIN 119: GENOME NON_GENOME PIN 83
-GENOME NON_GENOME PIN 120: GENOME NON_GENOME PIN 83
-GENOME NON_GENOME PIN 324: GENOME NON_GENOME PIN 315 GENOME NON_GENOME PIN 325
-GENOME NON_GENOME PIN 315: GENOME NON_GENOME PIN 324 GENOME NON_GENOME PIN 326
-GENOME NON_GENOME PIN 325: GENOME NON_GENOME PIN 324
-GENOME NON_GENOME PIN 326: GENOME NON_GENOME PIN 315
-GENOME NON_GENOME PIN 465: GENOME NON_GENOME PIN 403 GENOME NON_GENOME PIN 464
-GENOME NON_GENOME PIN 470: GENOME NON_GENOME PIN 532
-GENOME NON_GENOME PIN 532: GENOME NON_GENOME PIN 470
-GENOME NON_GENOME PIN 537: GENOME NON_GENOME PIN 599
-GENOME NON_GENOME PIN 599: GENOME NON_GENOME PIN 537
-GENOME NON_GENOME PIN 604: GENOME NON_GENOME PIN 666
-GENOME NON_GENOME PIN 666: GENOME NON_GENOME PIN 604
-GENOME NON_GENOME PIN 671: GENOME NON_GENOME PIN 733
-GENOME NON_GENOME PIN 733: GENOME NON_GENOME PIN 671
-GENOME NON_GENOME PIN 738: GENOME NON_GENOME PIN 800
-GENOME NON_GENOME PIN 800: GENOME NON_GENOME PIN 738
-GENOME NON_GENOME PIN 867: GENOME NON_GENOME PIN 805
-GENOME NON_GENOME PIN 872: GENOME NON_GENOME PIN 934
-GENOME NON_GENOME PIN 934: GENOME NON_GENOME PIN 872
-GENOME NON_GENOME PIN 1445: GENOME NON_GENOME PIN 1038
-GENOME NON_GENOME PIN 1038: GENOME NON_GENOME PIN 1445
-GENOME NON_GENOME PIN 1446: GENOME NON_GENOME PIN 1039
-GENOME NON_GENOME PIN 1039: GENOME NON_GENOME PIN 1446
-GENOME NON_GENOME PIN 1438: GENOME NON_GENOME PIN 1040
-GENOME NON_GENOME PIN 1040: GENOME NON_GENOME PIN 1438
-GENOME NON_GENOME PIN 1439: GENOME NON_GENOME PIN 1041
-GENOME NON_GENOME PIN 1041: GENOME NON_GENOME PIN 1439
-GENOME NON_GENOME PIN 1440: GENOME NON_GENOME PIN 1042
-GENOME NON_GENOME PIN 1042: GENOME NON_GENOME PIN 1440
-GENOME NON_GENOME PIN 1441: GENOME NON_GENOME PIN 1043
-GENOME NON_GENOME PIN 1043: GENOME NON_GENOME PIN 1441
-GENOME NON_GENOME PIN 1442: GENOME NON_GENOME PIN 1044
-GENOME NON_GENOME PIN 1044: GENOME NON_GENOME PIN 1442
-GENOME NON_GENOME PIN 1513: GENOME NON_GENOME PIN 1045
-GENOME NON_GENOME PIN 1045: GENOME NON_GENOME PIN 1513
-GENOME NON_GENOME PIN 1514: GENOME NON_GENOME PIN 1046
-GENOME NON_GENOME PIN 1046: GENOME NON_GENOME PIN 1514
-GENOME NON_GENOME PIN 1515: GENOME NON_GENOME PIN 1047
-GENOME NON_GENOME PIN 1047: GENOME NON_GENOME PIN 1515
-GENOME NON_GENOME PIN 1516: GENOME NON_GENOME PIN 1048
-GENOME NON_GENOME PIN 1048: GENOME NON_GENOME PIN 1516
-GENOME NON_GENOME PIN 1517: GENOME NON_GENOME PIN 1049
-GENOME NON_GENOME PIN 1049: GENOME NON_GENOME PIN 1517
-GENOME NON_GENOME PIN 1518: GENOME NON_GENOME PIN 1050
-GENOME NON_GENOME PIN 1050: GENOME NON_GENOME PIN 1518
-GENOME NON_GENOME PIN 1519: GENOME NON_GENOME PIN 1051
-GENOME NON_GENOME PIN 1051: GENOME NON_GENOME PIN 1519
-GENOME NON_GENOME PIN 1520: GENOME NON_GENOME PIN 1052
-GENOME NON_GENOME PIN 1052: GENOME NON_GENOME PIN 1520
-GENOME NON_GENOME PIN 1521: GENOME NON_GENOME PIN 1053
-GENOME NON_GENOME PIN 1053: GENOME NON_GENOME PIN 1521
-GENOME NON_GENOME PIN 1522: GENOME NON_GENOME PIN 1054
-GENOME NON_GENOME PIN 1054: GENOME NON_GENOME PIN 1522
-GENOME NON_GENOME PIN 1523: GENOME NON_GENOME PIN 1055
-GENOME NON_GENOME PIN 1055: GENOME NON_GENOME PIN 1523
-GENOME NON_GENOME PIN 1524: GENOME NON_GENOME PIN 1056
-GENOME NON_GENOME PIN 1056: GENOME NON_GENOME PIN 1524
-GENOME NON_GENOME PIN 1525: GENOME NON_GENOME PIN 1057
-GENOME NON_GENOME PIN 1057: GENOME NON_GENOME PIN 1525
-GENOME NON_GENOME PIN 1526: GENOME NON_GENOME PIN 1058
-GENOME NON_GENOME PIN 1058: GENOME NON_GENOME PIN 1526
-GENOME NON_GENOME PIN 1527: GENOME NON_GENOME PIN 1059
-GENOME NON_GENOME PIN 1059: GENOME NON_GENOME PIN 1527
-GENOME NON_GENOME PIN 1528: GENOME NON_GENOME PIN 1060
-GENOME NON_GENOME PIN 1060: GENOME NON_GENOME PIN 1528
-GENOME NON_GENOME PIN 1529: GENOME NON_GENOME PIN 1061
-GENOME NON_GENOME PIN 1061: GENOME NON_GENOME PIN 1529
-GENOME NON_GENOME PIN 1530: GENOME NON_GENOME PIN 1062
-GENOME NON_GENOME PIN 1062: GENOME NON_GENOME PIN 1530
-GENOME NON_GENOME PIN 1531: GENOME NON_GENOME PIN 1063
-GENOME NON_GENOME PIN 1063: GENOME NON_GENOME PIN 1531
-GENOME NON_GENOME PIN 1532: GENOME NON_GENOME PIN 1064
-GENOME NON_GENOME PIN 1064: GENOME NON_GENOME PIN 1532
-GENOME NON_GENOME PIN 1533: GENOME NON_GENOME PIN 1065
-GENOME NON_GENOME PIN 1065: GENOME NON_GENOME PIN 1533
-GENOME NON_GENOME PIN 1534: GENOME NON_GENOME PIN 1066
-GENOME NON_GENOME PIN 1066: GENOME NON_GENOME PIN 1534
-GENOME NON_GENOME PIN 1535: GENOME NON_GENOME PIN 1067
-GENOME NON_GENOME PIN 1067: GENOME NON_GENOME PIN 1535
-GENOME NON_GENOME PIN 1536: GENOME NON_GENOME PIN 1068
-GENOME NON_GENOME PIN 1068: GENOME NON_GENOME PIN 1536
-GENOME NON_GENOME PIN 1537: GENOME NON_GENOME PIN 1069
-GENOME NON_GENOME PIN 1069: GENOME NON_GENOME PIN 1537
-GENOME NON_GENOME PIN 1538: GENOME NON_GENOME PIN 1070
-GENOME NON_GENOME PIN 1070: GENOME NON_GENOME PIN 1538
-GENOME NON_GENOME PIN 1539: GENOME NON_GENOME PIN 1071
-GENOME NON_GENOME PIN 1071: GENOME NON_GENOME PIN 1539
-GENOME NON_GENOME PIN 1540: GENOME NON_GENOME PIN 1072
-GENOME NON_GENOME PIN 1072: GENOME NON_GENOME PIN 1540
-GENOME NON_GENOME PIN 1541: GENOME NON_GENOME PIN 1073
-GENOME NON_GENOME PIN 1073: GENOME NON_GENOME PIN 1541
-GENOME NON_GENOME PIN 1542: GENOME NON_GENOME PIN 1074
-GENOME NON_GENOME PIN 1074: GENOME NON_GENOME PIN 1542 GENOME NON_GENOME PIN 1012
-GENOME NON_GENOME PIN 1543: GENOME NON_GENOME PIN 1075
-GENOME NON_GENOME PIN 1075: GENOME NON_GENOME PIN 1543
-GENOME NON_GENOME PIN 1544: GENOME NON_GENOME PIN 1076
-GENOME NON_GENOME PIN 1076: GENOME NON_GENOME PIN 1544
-GENOME NON_GENOME PIN 1545: GENOME NON_GENOME PIN 1077
-GENOME NON_GENOME PIN 1077: GENOME NON_GENOME PIN 1545
-GENOME NON_GENOME PIN 1546: GENOME NON_GENOME PIN 1078
-GENOME NON_GENOME PIN 1078: GENOME NON_GENOME PIN 1546
-GENOME NON_GENOME PIN 1547: GENOME NON_GENOME PIN 1079
-GENOME NON_GENOME PIN 1079: GENOME NON_GENOME PIN 1547
-GENOME NON_GENOME PIN 1548: GENOME NON_GENOME PIN 1080
-GENOME NON_GENOME PIN 1080: GENOME NON_GENOME PIN 1548
-GENOME NON_GENOME PIN 1549: GENOME NON_GENOME PIN 1081
-GENOME NON_GENOME PIN 1081: GENOME NON_GENOME PIN 1549
-GENOME NON_GENOME PIN 1550: GENOME NON_GENOME PIN 1082
-GENOME NON_GENOME PIN 1082: GENOME NON_GENOME PIN 1550
-GENOME NON_GENOME PIN 1551: GENOME NON_GENOME PIN 1083
-GENOME NON_GENOME PIN 1083: GENOME NON_GENOME PIN 1551
-GENOME NON_GENOME PIN 1552: GENOME NON_GENOME PIN 1084
-GENOME NON_GENOME PIN 1084: GENOME NON_GENOME PIN 1552
-GENOME NON_GENOME PIN 1553: GENOME NON_GENOME PIN 1085
-GENOME NON_GENOME PIN 1085: GENOME NON_GENOME PIN 1553
-GENOME NON_GENOME PIN 1554: GENOME NON_GENOME PIN 1086
-GENOME NON_GENOME PIN 1086: GENOME NON_GENOME PIN 1554
-GENOME NON_GENOME PIN 1555: GENOME NON_GENOME PIN 1087
-GENOME NON_GENOME PIN 1087: GENOME NON_GENOME PIN 1555
-GENOME NON_GENOME PIN 1556: GENOME NON_GENOME PIN 1088
-GENOME NON_GENOME PIN 1088: GENOME NON_GENOME PIN 1556
-GENOME NON_GENOME PIN 1557: GENOME NON_GENOME PIN 1089
-GENOME NON_GENOME PIN 1089: GENOME NON_GENOME PIN 1557
-GENOME NON_GENOME PIN 1558: GENOME NON_GENOME PIN 1090
-GENOME NON_GENOME PIN 1090: GENOME NON_GENOME PIN 1558
-GENOME NON_GENOME PIN 1559: GENOME NON_GENOME PIN 1091
-GENOME NON_GENOME PIN 1091: GENOME NON_GENOME PIN 1559
-GENOME NON_GENOME PIN 1560: GENOME NON_GENOME PIN 1092
-GENOME NON_GENOME PIN 1092: GENOME NON_GENOME PIN 1560
-GENOME NON_GENOME PIN 1561: GENOME NON_GENOME PIN 1093
-GENOME NON_GENOME PIN 1093: GENOME NON_GENOME PIN 1561
-GENOME NON_GENOME PIN 1562: GENOME NON_GENOME PIN 1094
-GENOME NON_GENOME PIN 1094: GENOME NON_GENOME PIN 1562
-GENOME NON_GENOME PIN 1563: GENOME NON_GENOME PIN 1095
-GENOME NON_GENOME PIN 1095: GENOME NON_GENOME PIN 1563
-GENOME NON_GENOME PIN 1564: GENOME NON_GENOME PIN 1096
-GENOME NON_GENOME PIN 1096: GENOME NON_GENOME PIN 1564
-GENOME NON_GENOME PIN 1565: GENOME NON_GENOME PIN 1097
-GENOME NON_GENOME PIN 1097: GENOME NON_GENOME PIN 1565
-GENOME NON_GENOME PIN 1566: GENOME NON_GENOME PIN 1098
-GENOME NON_GENOME PIN 1098: GENOME NON_GENOME PIN 1566
-GENOME NON_GENOME PIN 1567: GENOME NON_GENOME PIN 1099
-GENOME NON_GENOME PIN 1099: GENOME NON_GENOME PIN 1567
-GENOME NON_GENOME PIN 1568: GENOME NON_GENOME PIN 1100
-GENOME NON_GENOME PIN 1100: GENOME NON_GENOME PIN 1568
-GENOME NON_GENOME PIN 1569: GENOME NON_GENOME PIN 1101
-GENOME NON_GENOME PIN 1101: GENOME NON_GENOME PIN 1569
-GENOME NON_GENOME PIN 1570: GENOME NON_GENOME PIN 1102
-GENOME NON_GENOME PIN 1102: GENOME NON_GENOME PIN 1570
-GENOME NON_GENOME PIN 1571: GENOME NON_GENOME PIN 1103
-GENOME NON_GENOME PIN 1103: GENOME NON_GENOME PIN 1571
-GENOME NON_GENOME PIN 1572: GENOME NON_GENOME PIN 1104
-GENOME NON_GENOME PIN 1104: GENOME NON_GENOME PIN 1572
-GENOME NON_GENOME PIN 1573: GENOME NON_GENOME PIN 1105
-GENOME NON_GENOME PIN 1105: GENOME NON_GENOME PIN 1573
-GENOME NON_GENOME PIN 1574: GENOME NON_GENOME PIN 1106
-GENOME NON_GENOME PIN 1106: GENOME NON_GENOME PIN 1574
-GENOME NON_GENOME PIN 1575: GENOME NON_GENOME PIN 1107
-GENOME NON_GENOME PIN 1107: GENOME NON_GENOME PIN 1575
-GENOME NON_GENOME PIN 1576: GENOME NON_GENOME PIN 1108
-GENOME NON_GENOME PIN 1108: GENOME NON_GENOME PIN 1576
-INST RocketTile__GCB0 PIN 1241: INST TilePRCIDomain__GC0 PIN 4 TYPE 5
-INST RocketTile__GCB0 PIN 1242: INST TilePRCIDomain__GC0 PIN 5 TYPE 5
-INST RocketTile__GCB0 PIN 1252: INST TilePRCIDomain__GC0 PIN 15 TYPE 5
-INST RocketTile__GCB0 PIN 1445: INST DCache PIN 131 TYPE 5
-INST RocketTile__GCB0 PIN 1446: INST DCache PIN 132 TYPE 5
-INST RocketTile__GCB0 PIN 82: INST TilePRCIDomain__GC0 PIN 415 TYPE 0 GENOME RocketTile__GCB0 PIN 82
-INST RocketTile__GCB0 PIN 121: INST TilePRCIDomain__GC0 PIN 454 TYPE 0 GENOME RocketTile__GCB0 PIN 121
-INST RocketTile__GCB0 PIN 122: INST TilePRCIDomain__GC0 PIN 455 TYPE 0 GENOME RocketTile__GCB0 PIN 122
-INST DCache PIN 131: GENOME DCache PIN 131
-INST DCache PIN 336: GENOME DCache PIN 336
-INST DCache PIN 337: GENOME DCache PIN 337
-INST DCache PIN 465: GENOME DCache PIN 465 INST RocketTile__GCB0 PIN 324 TYPE 5
-INST DCache PIN 464: GENOME DCache PIN 464
-INST DCache PIN 466: GENOME DCache PIN 466 INST RocketTile__GCB0 PIN 315 TYPE 5
-INST DCache PIN 455: GENOME DCache PIN 455
-INST DCache PIN 605: GENOME DCache PIN 605 INST RocketTile__GCB0 PIN 403 TYPE 5
-INST DCache PIN 543: GENOME DCache PIN 543
-INST DCache PIN 606: GENOME DCache PIN 606
-INST DCache PIN 607: GENOME DCache PIN 607
-INST DCache PIN 672: GENOME DCache PIN 672 INST RocketTile__GCB0 PIN 470 TYPE 5
-INST DCache PIN 610: GENOME DCache PIN 610
-INST DCache PIN 673: GENOME DCache PIN 673
-INST DCache PIN 674: GENOME DCache PIN 674
-INST DCache PIN 739: GENOME DCache PIN 739 INST RocketTile__GCB0 PIN 537 TYPE 5
-INST DCache PIN 677: GENOME DCache PIN 677
-INST DCache PIN 740: GENOME DCache PIN 740
-INST DCache PIN 741: GENOME DCache PIN 741
-INST DCache PIN 806: GENOME DCache PIN 806 INST RocketTile__GCB0 PIN 604 TYPE 5
-INST DCache PIN 744: GENOME DCache PIN 744
-INST DCache PIN 807: GENOME DCache PIN 807
-INST DCache PIN 808: GENOME DCache PIN 808
-INST DCache PIN 873: GENOME DCache PIN 873 INST RocketTile__GCB0 PIN 671 TYPE 5
-INST DCache PIN 811: GENOME DCache PIN 811
-INST DCache PIN 874: GENOME DCache PIN 874
-INST DCache PIN 875: GENOME DCache PIN 875
-INST DCache PIN 940: GENOME DCache PIN 940 INST RocketTile__GCB0 PIN 738 TYPE 5
-INST DCache PIN 878: GENOME DCache PIN 878
-INST DCache PIN 941: GENOME DCache PIN 941
-INST DCache PIN 942: GENOME DCache PIN 942
-INST DCache PIN 1007: GENOME DCache PIN 1007 INST RocketTile__GCB0 PIN 805 TYPE 5
-INST DCache PIN 945: GENOME DCache PIN 945
-INST DCache PIN 1008: GENOME DCache PIN 1008
-INST DCache PIN 1009: GENOME DCache PIN 1009
-INST DCache PIN 1074: GENOME DCache PIN 1074 INST RocketTile__GCB0 PIN 872 TYPE 5
-INST DCache PIN 1012: GENOME DCache PIN 1012
-INST DCache PIN 1075: GENOME DCache PIN 1075
-INST DCache PIN 1076: GENOME DCache PIN 1076
-GENOME NON_GENOME PIN 464: GENOME NON_GENOME PIN 465
-GENOME NON_GENOME PIN 455: GENOME NON_GENOME PIN 466
-GENOME NON_GENOME PIN 466: GENOME NON_GENOME PIN 455
-GENOME NON_GENOME PIN 543: GENOME NON_GENOME PIN 605
-GENOME NON_GENOME PIN 605: GENOME NON_GENOME PIN 543
-GENOME NON_GENOME PIN 610: GENOME NON_GENOME PIN 672
-GENOME NON_GENOME PIN 672: GENOME NON_GENOME PIN 610
-GENOME NON_GENOME PIN 677: GENOME NON_GENOME PIN 739
-GENOME NON_GENOME PIN 739: GENOME NON_GENOME PIN 677
-GENOME NON_GENOME PIN 744: GENOME NON_GENOME PIN 806
-GENOME NON_GENOME PIN 811: GENOME NON_GENOME PIN 873
-GENOME NON_GENOME PIN 873: GENOME NON_GENOME PIN 811
-GENOME NON_GENOME PIN 878: GENOME NON_GENOME PIN 940
-GENOME NON_GENOME PIN 940: GENOME NON_GENOME PIN 878
-GENOME NON_GENOME PIN 945: GENOME NON_GENOME PIN 1007
-GENOME NON_GENOME PIN 1007: GENOME NON_GENOME PIN 945
-GENOME NON_GENOME PIN 1012: GENOME NON_GENOME PIN 1074
-INST VCU118RocketSystem__GC0 PIN 83: GENOME VCU118RocketSystem__GC0 PIN 83
-INST VCU118RocketSystem__GC0 PIN 84: GENOME VCU118RocketSystem__GC0 PIN 84
-INST VCU118RocketSystem__GC0 PIN 85: GENOME VCU118RocketSystem__GC0 PIN 85
-INST VCU118RocketSystem__GC0 PIN 86: GENOME VCU118RocketSystem__GC0 PIN 86
-INST VCU118RocketSystem__GC0 PIN 87: GENOME VCU118RocketSystem__GC0 PIN 87
-INST VCU118RocketSystem__GC0 PIN 126: GENOME VCU118RocketSystem__GC0 PIN 126
-INST VCU118RocketSystem__GC0 PIN 127: GENOME VCU118RocketSystem__GC0 PIN 127
-INST VCU118RocketSystem__GC0 PIN 128: GENOME VCU118RocketSystem__GC0 PIN 128
-INST VCU118RocketSystem__GC0 PIN 129: GENOME VCU118RocketSystem__GC0 PIN 129
-INST VCU118RocketSystem__GC0 PIN 130: GENOME VCU118RocketSystem__GC0 PIN 130
-INST VCU118RocketSystem__GC0 PIN 131: GENOME VCU118RocketSystem__GC0 PIN 131
-INST VCU118RocketSystem__GC0 PIN 132: GENOME VCU118RocketSystem__GC0 PIN 132
-INST VCU118RocketSystem__GC0 PIN 133: GENOME VCU118RocketSystem__GC0 PIN 133
-INST VCU118RocketSystem__GC0 PIN 134: GENOME VCU118RocketSystem__GC0 PIN 134
-INST VCU118RocketSystem__GC0 PIN 135: GENOME VCU118RocketSystem__GC0 PIN 135
-INST VCU118RocketSystem__GC0 PIN 136: GENOME VCU118RocketSystem__GC0 PIN 136
-INST VCU118RocketSystem__GC0 PIN 169: GENOME VCU118RocketSystem__GC0 PIN 169
-INST VCU118RocketSystem__GC0 PIN 171: GENOME VCU118RocketSystem__GC0 PIN 171
-INST VCU118RocketSystem__GC0 PIN 172: GENOME VCU118RocketSystem__GC0 PIN 172
-INST VCU118RocketSystem__GC0 PIN 289: GENOME VCU118RocketSystem__GC0 PIN 289
-INST VCU118RocketSystem__GC0 PIN 335: GENOME VCU118RocketSystem__GC0 PIN 335
-INST VCU118RocketSystem__GC0 PIN 336: GENOME VCU118RocketSystem__GC0 PIN 336
-INST VCU118RocketSystem__GC0 PIN 489: GENOME VCU118RocketSystem__GC0 PIN 489
-INST VCU118RocketSystem__GC0 PIN 490: GENOME VCU118RocketSystem__GC0 PIN 490
-INST VCU118RocketSystem__GC0 PIN 492: GENOME VCU118RocketSystem__GC0 PIN 492
-INST VCU118RocketSystem__GC0 PIN 493: GENOME VCU118RocketSystem__GC0 PIN 493
-INST VCU118RocketSystem__GC0 PIN 503: GENOME VCU118RocketSystem__GC0 PIN 503
-INST VCU118RocketSystem__GC0 PIN 550: GENOME VCU118RocketSystem__GC0 PIN 550
-INST VCU118RocketSystem__GC0 PIN 551: GENOME VCU118RocketSystem__GC0 PIN 551
-INST VCU118RocketSystem__GC0 PIN 616: GENOME VCU118RocketSystem__GC0 PIN 616
-GENOME NON_GENOME PIN 360: GENOME NON_GENOME PIN 79
-GENOME NON_GENOME PIN 79: GENOME NON_GENOME PIN 360
-GENOME NON_GENOME PIN 361: GENOME NON_GENOME PIN 80
-GENOME NON_GENOME PIN 80: GENOME NON_GENOME PIN 361
-GENOME NON_GENOME PIN 356: GENOME NON_GENOME PIN 171
-GENOME NON_GENOME PIN 171: GENOME NON_GENOME PIN 356
-GENOME NON_GENOME PIN 357: GENOME NON_GENOME PIN 172
-GENOME NON_GENOME PIN 172: GENOME NON_GENOME PIN 357
-GENOME NON_GENOME PIN 334: GENOME NON_GENOME PIN 335 GENOME NON_GENOME PIN 336
-GENOME NON_GENOME PIN 335: GENOME NON_GENOME PIN 334
-GENOME NON_GENOME PIN 336: GENOME NON_GENOME PIN 334
-INST FPU__GB1 PIN 1: GENOME FPU__GB1 PIN 1
-INST FPU__GB1 PIN 137: GENOME FPU__GB1 PIN 137
-INST FPU__GB1 PIN 162: GENOME FPU__GB1 PIN 162
-INST FPU__GB1 PIN 525: GENOME FPU__GB1 PIN 525
-INST FPU__GB1 PIN 526: GENOME FPU__GB1 PIN 526
-INST FPU__GB1 PIN 527: GENOME FPU__GB1 PIN 527
-INST FPU__GB1 PIN 528: GENOME FPU__GB1 PIN 528
-INST FPU__GB1 PIN 531: GENOME FPU__GB1 PIN 531
-INST FPU__GB1 PIN 532: GENOME FPU__GB1 PIN 532
-INST FPU__GB1 PIN 533: GENOME FPU__GB1 PIN 533
-GENOME NON_GENOME PIN 536: GENOME NON_GENOME PIN 146
-GENOME NON_GENOME PIN 146: GENOME NON_GENOME PIN 536
-INST TilePRCIDomain__GC0 PIN 4: GENOME TilePRCIDomain__GC0 PIN 4
-INST TilePRCIDomain__GC0 PIN 7: GENOME TilePRCIDomain__GC0 PIN 7
-INST TilePRCIDomain__GC0 PIN 8: GENOME TilePRCIDomain__GC0 PIN 8
-INST TilePRCIDomain__GC0 PIN 14: GENOME TilePRCIDomain__GC0 PIN 14
-INST TilePRCIDomain__GC0 PIN 15: GENOME TilePRCIDomain__GC0 PIN 15
-INST TilePRCIDomain__GC0 PIN 415: GENOME TilePRCIDomain__GC0 PIN 415
-INST TilePRCIDomain__GC0 PIN 454: GENOME TilePRCIDomain__GC0 PIN 454
-INST TilePRCIDomain__GC0 PIN 455: GENOME TilePRCIDomain__GC0 PIN 455
-INST TilePRCIDomain__GC0 PIN 531: GENOME TilePRCIDomain__GC0 PIN 531
-INST TilePRCIDomain__GC0 PIN 732: GENOME TilePRCIDomain__GC0 PIN 732
-INST TilePRCIDomain__GC0 PIN 733: GENOME TilePRCIDomain__GC0 PIN 733
-INST APBGpsBlock__GC0 PIN 2: GENOME APBGpsBlock__GC0 PIN 2
-INST APBGpsBlock__GC0 PIN 36: GENOME APBGpsBlock__GC0 PIN 36
-INST TLToAPB PIN 52: GENOME TLToAPB PIN 52
-INST FPU__GB2 PIN 1: INST FPU__GB1 PIN 146 TYPE 3 INST RocketTile__GCB0 PIN 1654 TYPE 4
-INST RocketTile__GCB0 PIN 83: INST RocketTile__GCB0 PIN 119 TYPE 2 INST TilePRCIDomain__GC0 PIN 452 TYPE 4 INST RocketTile__GCB0 PIN 120 TYPE 2 INST TilePRCIDomain__GC0 PIN 453 TYPE 4
-INST RocketTile__GCB0 PIN 119: GENOME RocketTile__GCB0 PIN 119
-INST RocketTile__GCB0 PIN 120: GENOME RocketTile__GCB0 PIN 120
-INST TilePRCIDomain__GC0 PIN 452: GENOME TilePRCIDomain__GC0 PIN 452 INST RocketTile__GCB0 PIN 83 TYPE 5
-INST TilePRCIDomain__GC0 PIN 416: GENOME TilePRCIDomain__GC0 PIN 416
-INST TilePRCIDomain__GC0 PIN 453: GENOME TilePRCIDomain__GC0 PIN 453 INST RocketTile__GCB0 PIN 83 TYPE 5
-GENOME NON_GENOME PIN 416: GENOME NON_GENOME PIN 452 GENOME NON_GENOME PIN 453
-GENOME NON_GENOME PIN 452: GENOME NON_GENOME PIN 416
-GENOME NON_GENOME PIN 453: GENOME NON_GENOME PIN 416
-INST FPU__GB1 PIN 146: GENOME FPU__GB1 PIN 146
-INST FPU__GB1 PIN 536: INST FPU__GB2 PIN 1 TYPE 5
-DISSOLVE_GENOME: GENOME tracking_wrapper
-INST TilePRCIDomain__GC0 PIN 204: INST VCU118RocketSystem__GC0 PIN 485 TYPE 0
-INST TilePRCIDomain__GC0 PIN 208: INST VCU118RocketSystem__GC0 PIN 540 TYPE 0
-INST TilePRCIDomain__GC0 PIN 212: INST VCU118RocketSystem__GC0 PIN 544 TYPE 0
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/equivDumpFile.info b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/equivDumpFile.info
deleted file mode 100644
index 54d9817..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/equivDumpFile.info
+++ /dev/null
@@ -1,155 +0,0 @@
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#5:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#3
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#6:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#4
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#9:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#5
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#10:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#6
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#11:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#7
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#12:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#8
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#16:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#10
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#17:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#11
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#18:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#12
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#19:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#13
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#20:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#14
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#21:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#15
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#22:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#16
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#23:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#17
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#24:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#18
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#25:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#19
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#26:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#20
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#27:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#21
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#28:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#22
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#29:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#23
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#30:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#24
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#31:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#25
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#32:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#26
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#33:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#27
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#34:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#28
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#35:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#29
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#36:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#30
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#37:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#31
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#38:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#32
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#39:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#33
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#40:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#34
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#41:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#35
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#42:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#36
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#43:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#37
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#44:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#38
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#45:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#39
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#46:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#40
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#47:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#41
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#48:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#42
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#49:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#43
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#50:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#44
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#51:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#45
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#52:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#46
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#53:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#47
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#54:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#48
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#55:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#49
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#56:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#50
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#57:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#51
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#58:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#52
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#59:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#53
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#60:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#54
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#61:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#55
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#62:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#56
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#63:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#57
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#64:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#58
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#65:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#59
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#66:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#60
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#67:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#61
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#68:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#62
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#69:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#63
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#70:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#64
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#71:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#65
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#72:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#66
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#73:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#67
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#74:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#68
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#75:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#69
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#76:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#70
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#77:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#71
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#78:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#72
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#79:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#73
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#324:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#325
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#315:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#326
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#403:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#465
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#470:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#532
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#537:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#599
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#604:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#666
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#671:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#733
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#738:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#800
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#805:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#867
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#872:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#934
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#124:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1040
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#125:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1041
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#126:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1042
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#127:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1043
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#128:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1044
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#199:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1045
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#200:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1046
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#201:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1047
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#202:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1048
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#203:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1049
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#204:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1050
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#205:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1051
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#206:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1052
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#207:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1053
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#208:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1054
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#209:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1055
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#210:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1056
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#211:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1057
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#212:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1058
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#213:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1059
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#214:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1060
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#215:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1061
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#216:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1062
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#217:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1063
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#218:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1064
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#219:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1065
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#220:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1066
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#221:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1067
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#222:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1068
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#223:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1069
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#224:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1070
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#225:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1071
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#226:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1072
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#227:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1073
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#228:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1074
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#229:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1075
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#230:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1076
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#231:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1077
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#232:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1078
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#233:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1079
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#234:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1080
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#235:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1081
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#236:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1082
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#237:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1083
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#238:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1084
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#239:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1085
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#240:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1086
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#241:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1087
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#242:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1088
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#243:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1089
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#244:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1090
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#245:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1091
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#246:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1092
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#247:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1093
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#248:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1094
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#249:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1095
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#250:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1096
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#251:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1097
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#252:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1098
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#253:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1099
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#254:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1100
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#255:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1101
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#256:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1102
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#257:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1103
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#258:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1104
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#259:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1105
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#260:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1106
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#261:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1107
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#262:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1108
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#132:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1039
-/u_rocket/VCU118RocketSystem__GC0#334:/u_rocket/VCU118RocketSystem__GC0#335
-/u_rocket/VCU118RocketSystem__GC0#334:/u_rocket/VCU118RocketSystem__GC0#336
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2#1:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1#146
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#83:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#119
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#83:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#120
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1220760385.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1220760385.rtd
deleted file mode 100644
index 4393756..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index 606564e..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1294509424.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1294509424.rtd
deleted file mode 100644
index 01f4f1e..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index 374a1dc..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/136113302.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/136113302.rtd
deleted file mode 100644
index c6baf36..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd
deleted file mode 100644
index b0ef7ad..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1672436263.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1672436263.rtd
deleted file mode 100644
index 7aeaacb..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index 4aa321f..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2438764479.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2438764479.rtd
deleted file mode 100644
index 8a05387..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2438764479.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd
deleted file mode 100644
index 2afe268..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2438764479.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2610937407.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2610937407.rtd
deleted file mode 100644
index 3d481f6..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index 3675360..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2737226844.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2737226844.rtd
deleted file mode 100644
index 083ac6d..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index 0b2727c..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2962621930.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2962621930.rtd
deleted file mode 100644
index 9cd8212..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index 2f00453..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3482045580.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3482045580.rtd
deleted file mode 100644
index 52c4a9c..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index 06bb3b3..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3990655999.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3990655999.rtd
deleted file mode 100644
index ef3c036..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3990655999.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd
deleted file mode 100644
index 7132df0..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/3990655999.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/976197094.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/976197094.rtd
deleted file mode 100644
index d37ff13..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd
deleted file mode 100644
index ffee345..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/global_name.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/global_name.straps.rtd
deleted file mode 100644
index b09af20..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/instToEncGenName.map b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/instToEncGenName.map
deleted file mode 100644
index 8025b8a..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/g/instToEncGenName.map
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
-/genesys2_rocket_top__GC0:3990655999
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0:2438764479
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/stitchPoint.lst b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/stitchPoint.lst
deleted file mode 100644
index 7e81f87..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/stitchPoint.lst
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2
-/u_rocket/fpga_gps_domain/dev/tracking_8
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache
-/u_rocket/fpga_gps_domain/dev/tracking_7
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0
-/genesys2_rocket_top__GC0
-/u_rocket/VCU118RocketSystem__GC0
-/u_rocket/fpga_gps_domain/dev/tracking_6
-/u_rocket/fpga_gps_domain/dev/tracking_5
-/u_rocket/fpga_gps_domain/dev/tracking_4
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0
-/u_rocket/fpga_gps_domain/tl2apb
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0
-/u_rocket/fpga_gps_domain/dev/tracking_3
-/u_rocket/fpga_gps_domain/dev/tracking_2
-/u_rocket/fpga_gps_domain/dev/tracking_1
-/u_rocket/fpga_gps_domain/dev/tracking_0
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/54573100.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/54573100.rtd
deleted file mode 100644
index efabb90..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/54573100.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55C42420.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55C42420.rtd
deleted file mode 100644
index e55e4e1..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55C42420.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55C67420.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55C67420.rtd
deleted file mode 100644
index 56aa6d9..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55C67420.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55DF1B00.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55DF1B00.rtd
deleted file mode 100644
index c614bc7..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55DF1B00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55E32220.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55E32220.rtd
deleted file mode 100644
index 5622845..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/55E32220.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/562790E0.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/562790E0.rtd
deleted file mode 100644
index 23b884c..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/562790E0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/56DC6640.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/56DC6640.rtd
deleted file mode 100644
index 4c2b3b7..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/56DC6640.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/59BB7D60.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/59BB7D60.rtd
deleted file mode 100644
index c6d0eb3..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/59BB7D60.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/820E5E00.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/820E5E00.rtd
deleted file mode 100644
index 0a3e5a5..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/820E5E00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/9289B660.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/9289B660.rtd
deleted file mode 100644
index 17826bf..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/9289B660.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/93836360.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/93836360.rtd
deleted file mode 100644
index f6b78c1..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/93836360.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/design.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/design.rtd
deleted file mode 100644
index e9afe7f..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/files.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/files.rtd
deleted file mode 100644
index 48b9873..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/files.rtd
+++ /dev/null
@@ -1,13 +0,0 @@
-design.rtd
-straps.rtd
-54573100.rtd
-56DC6640.rtd
-93836360.rtd
-55C67420.rtd
-562790E0.rtd
-59BB7D60.rtd
-55DF1B00.rtd
-55C42420.rtd
-9289B660.rtd
-820E5E00.rtd
-55E32220.rtd
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/straps.rtd
deleted file mode 100644
index 15975f4..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/uniqInferGenToOrigInferGen.map b/.Xil/Vivado-7908-onur/incrSyn/1309558296/o/uniqInferGenToOrigInferGen.map
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/childModToGenomes.map b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/childModToGenomes.map
deleted file mode 100644
index cf7fff3..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/childModToGenomes.map
+++ /dev/null
@@ -1,7760 +0,0 @@
-reg__151: VCU118RocketSystem__GC0,
-case__1295: APBGpsBlock__GC0,
-reg__418: FPU__GB1,
-logic__989: VCU118RocketSystem__GC0,
-logic__3298: FPU__GB2,
-logic__2683: FPU__GB1,
-reg__1055: APBGpsBlock__GC0,
-logic__6386: VCU118RocketSystem__GC0,
-logic__6278: VCU118RocketSystem__GC0,
-case__624: RocketTile__GCB0,
-case__28: VCU118RocketSystem__GC0,
-logic__833: VCU118RocketSystem__GC0,
-logic__563: VCU118RocketSystem__GC0,
-logic__8669: tracking_wrapper,
-logic__1163: VCU118RocketSystem__GC0,
-datapath__218: VCU118RocketSystem__GC0,
-logic__6449: VCU118RocketSystem__GC0,
-logic__1819: DCache,
-dsp48e1__15: APBGpsBlock__GC0,
-logic__503: VCU118RocketSystem__GC0,
-logic__4503: RocketTile__GCB0,
-case__168: VCU118RocketSystem__GC0,
-case__354: DCache,
-case__1399: tracking_wrapper,
-reg__1139: tracking_wrapper,
-logic__2627: RocketTile__GCB0,
-logic__6890: VCU118RocketSystem__GC0,
-logic__5387: RocketTile__GCB0,
-logic__6739: VCU118RocketSystem__GC0,
-keep__4: tracking_wrapper,
-reg__250: DCache,
-datapath__547: APBGpsBlock__GC0,
-case__263: VCU118RocketSystem__GC0,
-logic__438: VCU118RocketSystem__GC0,
-datapath__570: APBGpsBlock__GC0,
-logic__4226: FPU__GB2,
-logic__4079: FPU__GB2,
-logic__3849: FPU__GB1,
-logic__7386: VCU118RocketSystem__GC0,
-case__224: VCU118RocketSystem__GC0,
-reg__274: DCache,
-muxpart__228: tracking_wrapper,
-datapath__586: APBGpsBlock__GC0,
-case__589: FPU__GB1,
-reg__168: VCU118RocketSystem__GC0,
-logic__764: VCU118RocketSystem__GC0,
-logic__4356: FPU__GB2,
-logic__3516: FPU__GB1,
-logic__3568: FPU__GB1,
-counter__25: tracking_wrapper,
-case__647: RocketTile__GCB0,
-logic__7349: VCU118RocketSystem__GC0,
-case__1063: APBGpsBlock__GC0,
-datapath__142: VCU118RocketSystem__GC0,
-cordic_atan_one_stage: tracking_wrapper,
-case__386: RocketTile__GCB0,
-reg__489: FPU__GB1,
-reg__425: FPU__GB1,
-case__591: FPU__GB1,
-datapath__194: VCU118RocketSystem__GC0,
-logic__3654: FPU__GB1,
-logic__6394: VCU118RocketSystem__GC0,
-logic__2019: DCache,
-case__519: FPU__GB2, FPU__GB1,
-logic__7210: VCU118RocketSystem__GC0,
-reg__1241: tracking_wrapper,
-logic__5300: RocketTile__GCB0,
-logic__3815: FPU__GB1,
-reg__544: FPU__GB1,
-reg__1220: tracking_wrapper,
-logic__6753: VCU118RocketSystem__GC0,
-logic__2165: DCache,
-logic__3745: FPU__GB1,
-datapath__215: VCU118RocketSystem__GC0,
-case__69: VCU118RocketSystem__GC0,
-logic__2704: FPU__GB1,
-case__685: RocketTile__GCB0,
-logic__5317: RocketTile__GCB0,
-reg__1327: tracking_wrapper,
-logic__765: VCU118RocketSystem__GC0,
-case__718: RocketTile__GCB0,
-logic__2413: RocketTile__GCB0,
-case__1011: VCU118RocketSystem__GC0,
-datapath__537: APBGpsBlock__GC0,
-case__1045: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_pbus_to_gps: VCU118RocketSystem__GC0,
-logic__8448: tracking_wrapper,
-logic__7542: VCU118RocketSystem__GC0,
-logic__298: VCU118RocketSystem__GC0,
-logic__5051: RocketTile__GCB0,
-logic__6751: VCU118RocketSystem__GC0,
-logic__6814: VCU118RocketSystem__GC0,
-reg__1036: APBGpsBlock__GC0,
-datapath__187: VCU118RocketSystem__GC0,
-logic__5257: RocketTile__GCB0,
-case__424: RocketTile__GCB0,
-case__562: FPU__GB2,
-logic__3600: FPU__GB1,
-logic__2191: DCache,
-case__828: VCU118RocketSystem__GC0,
-logic__1142: VCU118RocketSystem__GC0,
-logic__525: VCU118RocketSystem__GC0,
-case__878: VCU118RocketSystem__GC0,
-logic__4060: FPU__GB2,
-case__478: FPU__GB2,
-logic__5299: RocketTile__GCB0,
-logic__6071: RocketTile__GCB0,
-logic__6610: VCU118RocketSystem__GC0,
-logic__6806: VCU118RocketSystem__GC0,
-logic__7363: VCU118RocketSystem__GC0,
-logic__4368: FPU__GB1,
-logic__5971: RocketTile__GCB0,
-logic__7777: APBGpsBlock__GC0,
-case__1331: tracking_wrapper,
-case__1540: VCU118RocketSystem__GC0,
-logic__7920: APBGpsBlock__GC0,
-reg__429: FPU__GB1,
-logic__6162: VCU118RocketSystem__GC0,
-logic__8783: tracking_wrapper,
-case__848: VCU118RocketSystem__GC0,
-reg__912: VCU118RocketSystem__GC0,
-logic__1453: RocketTile__GCB0,
-logic__673: VCU118RocketSystem__GC0,
-logic__4419: FPU__GB1,
-reg__1268: tracking_wrapper,
-case__156: VCU118RocketSystem__GC0,
-reg__646: RocketTile__GCB0,
-case__1226: APBGpsBlock__GC0,
-reg__960: VCU118RocketSystem__GC0,
-logic__228: VCU118RocketSystem__GC0,
-dsp48e1__9: APBGpsBlock__GC0,
-logic__5917: RocketTile__GCB0,
-logic__4645: RocketTile__GCB0,
-reg__1079: APBGpsBlock__GC0,
-logic__3456: FPU__GB2,
-logic__8656: tracking_wrapper,
-logic__6611: VCU118RocketSystem__GC0,
-logic__3404: FPU__GB2,
-muxpart__42: FPU__GB0,
-logic__7383: VCU118RocketSystem__GC0,
-counter__4: VCU118RocketSystem__GC0,
-datapath__152: VCU118RocketSystem__GC0,
-logic__3720: FPU__GB1,
-muxpart__54: FPU__GB0,
-logic__2666: FPU__GB1,
-logic__5301: RocketTile__GCB0,
-logic__6036: RocketTile__GCB0,
-logic__6309: VCU118RocketSystem__GC0,
-logic__971: VCU118RocketSystem__GC0,
-case__1478: tracking_wrapper,
-logic__4976: RocketTile__GCB0,
-logic__4591: RocketTile__GCB0,
-reg__641: RocketTile__GCB0,
-reg__941: VCU118RocketSystem__GC0,
-datapath__374: FPU__GB2,
-logic__8052: APBGpsBlock__GC0,
-case__1439: tracking_wrapper,
-reg__806: VCU118RocketSystem__GC0,
-logic__6612: VCU118RocketSystem__GC0,
-logic__915: VCU118RocketSystem__GC0,
-logic__842: VCU118RocketSystem__GC0,
-reg__454: FPU__GB1,
-reg__1161: tracking_wrapper,
-case__1427: tracking_wrapper,
-datapath__231: VCU118RocketSystem__GC0,
-logic__5293: RocketTile__GCB0,
-logic__1645: DCache,
-reg__1078: APBGpsBlock__GC0,
-reg__1064: APBGpsBlock__GC0,
-reg__334: RocketTile__GCB0,
-case__1422: tracking_wrapper,
-logic__3178: FPU__GB2,
-logic__1974: DCache,
-AsyncQueueSource_TLBundleA_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__4529: RocketTile__GCB0,
-logic__5412: RocketTile__GCB0,
-logic__8618: tracking_wrapper,
-logic__900: VCU118RocketSystem__GC0,
-reg__44: VCU118RocketSystem__GC0,
-datapath__188: VCU118RocketSystem__GC0,
-reg__522: FPU__GB1,
-logic__4747: RocketTile__GCB0,
-reg__764: RocketTile__GCB0,
-logic__1870: RocketTile__GCB0, DCache,
-case__1138: APBGpsBlock__GC0,
-logic__7399: VCU118RocketSystem__GC0,
-logic__5315: RocketTile__GCB0,
-datapath__497: VCU118RocketSystem__GC0,
-muxpart__25: FPU__GB0,
-datapath__195: VCU118RocketSystem__GC0,
-case__311: DCache,
-case__152: VCU118RocketSystem__GC0,
-keep__6: tracking_wrapper,
-logic__7566: VCU118RocketSystem__GC0,
-logic__6098: VCU118RocketSystem__GC0,
-case__155: VCU118RocketSystem__GC0,
-reg__40: VCU118RocketSystem__GC0,
-case__1477: tracking_wrapper,
-logic__6602: VCU118RocketSystem__GC0,
-logic__2653: RocketTile__GCB0,
-reg__525: FPU__GB1,
-datapath__17: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__3527: FPU__GB1,
-logic__6812: VCU118RocketSystem__GC0,
-datapath__35: VCU118RocketSystem__GC0,
-logic__1983: DCache,
-logic__3586: FPU__GB1,
-logic__8368: tracking_wrapper,
-logic__4704: RocketTile__GCB0,
-datapath__150: VCU118RocketSystem__GC0,
-logic__803: VCU118RocketSystem__GC0,
-logic__6313: VCU118RocketSystem__GC0,
-logic__1297: VCU118RocketSystem__GC0,
-logic__1909: DCache,
-case__879: VCU118RocketSystem__GC0,
-reg__1245: tracking_wrapper,
-logic__3267: FPU__GB2,
-logic__1782: DCache,
-case__1467: tracking_wrapper,
-logic__4195: FPU__GB2,
-datapath__550: APBGpsBlock__GC0,
-logic__2476: RocketTile__GCB0,
-logic__8116: APBGpsBlock__GC0,
-logic__5294: RocketTile__GCB0,
-reg__162: VCU118RocketSystem__GC0,
-logic__152: VCU118RocketSystem__GC0,
-logic__8452: tracking_wrapper,
-reg__685: RocketTile__GCB0,
-datapath__575: APBGpsBlock__GC0,
-reg__32: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__766: RocketTile__GCB0,
-datapath__120: VCU118RocketSystem__GC0,
-logic__3237: FPU__GB2,
-case__1292: APBGpsBlock__GC0,
-logic__4516: RocketTile__GCB0,
-reg__1025: APBGpsBlock__GC0,
-logic__299: VCU118RocketSystem__GC0,
-reg__451: FPU__GB1,
-logic__4809: RocketTile__GCB0,
-logic__4527: RocketTile__GCB0,
-logic__2356: RocketTile__GCB0,
-logic__8497: tracking_wrapper,
-case__671: RocketTile__GCB0,
-reg__1233: tracking_wrapper,
-case__727: RocketTile__GCB0,
-reg__831: VCU118RocketSystem__GC0,
-logic__8429: tracking_wrapper,
-datapath__515: VCU118RocketSystem__GC0,
-logic__630: VCU118RocketSystem__GC0,
-logic__5465: RocketTile__GCB0,
-case__891: VCU118RocketSystem__GC0,
-muxpart__15: RocketTile__GCB0,
-logic__3212: FPU__GB2,
-reg__963: VCU118RocketSystem__GC0,
-logic__8670: tracking_wrapper,
-datapath__143: VCU118RocketSystem__GC0,
-muxpart__92: FPU__GB1,
-reg__375: FPU__GB0,
-logic__6029: RocketTile__GCB0,
-logic__2628: RocketTile__GCB0,
-logic__6496: VCU118RocketSystem__GC0,
-case__639: RocketTile__GCB0,
-datapath__441: RocketTile__GCB0,
-reg__1053: APBGpsBlock__GC0,
-logic__5857: RocketTile__GCB0,
-logic__5999: RocketTile__GCB0,
-logic__69: genesys2_rocket_top__GC0,
-reg__367: FPU__GB0,
-reg__810: VCU118RocketSystem__GC0,
-case__261: VCU118RocketSystem__GC0,
-reg__929: VCU118RocketSystem__GC0,
-case__991: VCU118RocketSystem__GC0,
-logic__8917: APBGpsBlock__GC0,
-case__217: VCU118RocketSystem__GC0,
-double_ff_syn: APBGpsBlock__GC0, tracking_wrapper,
-logic__1694: DCache,
-logic__3987: FPU__GB1,
-logic__339: VCU118RocketSystem__GC0,
-reg__309: RocketTile__GCB0,
-logic__8496: tracking_wrapper,
-logic__8262: tracking_wrapper,
-reg__612: RocketTile__GCB0,
-reg__4: genesys2_rocket_top__GC0,
-logic__6414: VCU118RocketSystem__GC0,
-reg__983: VCU118RocketSystem__GC0,
-datapath__495: VCU118RocketSystem__GC0,
-datapath__114: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7234: VCU118RocketSystem__GC0,
-reg__181: VCU118RocketSystem__GC0,
-logic__7166: VCU118RocketSystem__GC0,
-reg__205: VCU118RocketSystem__GC0,
-datapath__165: VCU118RocketSystem__GC0,
-logic__5314: RocketTile__GCB0,
-logic__1157: VCU118RocketSystem__GC0,
-muxpart__115: VCU118RocketSystem__GC0,
-reg__340: RocketTile__GCB0,
-logic__3859: FPU__GB1,
-logic__8396: tracking_wrapper,
-case__687: RocketTile__GCB0,
-logic__6614: VCU118RocketSystem__GC0,
-logic__1627: DCache,
-reg__586: RocketTile__GCB0,
-reg__814: VCU118RocketSystem__GC0,
-logic__8404: tracking_wrapper,
-logic__5290: RocketTile__GCB0,
-logic__231: VCU118RocketSystem__GC0,
-logic__3813: FPU__GB1,
-logic__2418: RocketTile__GCB0,
-case__861: VCU118RocketSystem__GC0,
-case__1486: tracking_wrapper,
-logic__3739: FPU__GB1,
-logic__7051: VCU118RocketSystem__GC0,
-logic__3844: FPU__GB1,
-case__520: FPU__GB2, FPU__GB1,
-logic__8541: tracking_wrapper,
-logic__8115: APBGpsBlock__GC0,
-datapath__189: VCU118RocketSystem__GC0,
-datapath__592: APBGpsBlock__GC0,
-case__446: FPU__GB1,
-dsp48e1__3: APBGpsBlock__GC0,
-logic__164: VCU118RocketSystem__GC0,
-reg__547: FPU__GB1,
-logic__7385: VCU118RocketSystem__GC0,
-logic__4275: FPU__GB1,
-logic__8914: APBGpsBlock__GC0,
-datapath__24: VCU118RocketSystem__GC0,
-extram__7: APBGpsBlock__GC0,
-case__910: VCU118RocketSystem__GC0,
-logic__4337: FPU__GB1,
-logic__52: genesys2_rocket_top__GC0,
-logic__3465: FPU__GB2,
-logic__6557: VCU118RocketSystem__GC0,
-logic__295: VCU118RocketSystem__GC0,
-logic__3163: FPU__GB2,
-logic__5435: RocketTile__GCB0,
-logic__8513: tracking_wrapper,
-logic__2569: RocketTile__GCB0,
-case__597: FPU__GB1,
-logic__8711: tracking_wrapper,
-datapath__511: VCU118RocketSystem__GC0,
-case__471: FPU__GB2,
-reg__1097: APBGpsBlock__GC0,
-logic__4335: FPU__GB1,
-logic__3185: FPU__GB2,
-logic__4209: FPU__GB2,
-logic__6752: VCU118RocketSystem__GC0,
-logic__1507: DCache,
-logic__3146: FPU__GB2,
-logic__7957: APBGpsBlock__GC0,
-reg__75: VCU118RocketSystem__GC0,
-logic__5369: RocketTile__GCB0,
-TLFragmenter_FPGAUART: VCU118RocketSystem__GC0,
-logic__8698: tracking_wrapper,
-logic__5039: RocketTile__GCB0,
-logic__5991: RocketTile__GCB0,
-logic__871: VCU118RocketSystem__GC0,
-case__1363: tracking_wrapper,
-logic__8817: tracking_wrapper,
-case__391: RocketTile__GCB0,
-logic__8126: APBGpsBlock__GC0,
-AsyncResetSynchronizerShiftReg_w1_d3_i0: VCU118RocketSystem__GC0, APBGpsBlock__GC0,
-datapath__683: tracking_wrapper,
-reg__114: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4428: FPU__GB1,
-logic__4279: FPU__GB1,
-logic__1785: DCache,
-logic__3756: FPU__GB1,
-datapath__73: VCU118RocketSystem__GC0,
-logic__4336: FPU__GB1,
-reg__882: VCU118RocketSystem__GC0,
-datapath__240: DCache,
-logic__7628: VCU118RocketSystem__GC0,
-logic__3186: FPU__GB2,
-logic__250: VCU118RocketSystem__GC0,
-logic__4174: FPU__GB2,
-case__23: VCU118RocketSystem__GC0,
-case__610: RocketTile__GCB0,
-case__704: RocketTile__GCB0,
-reg__962: VCU118RocketSystem__GC0,
-logic__7617: VCU118RocketSystem__GC0,
-logic__7558: VCU118RocketSystem__GC0,
-logic__3361: FPU__GB2,
-logic__3569: FPU__GB1,
-logic__7751: APBGpsBlock__GC0,
-logic__2971: FPU__GB2, FPU__GB1,
-logic__6491: VCU118RocketSystem__GC0,
-logic__4524: RocketTile__GCB0,
-reg__366: FPU__GB0,
-logic__2632: RocketTile__GCB0,
-datapath__119: VCU118RocketSystem__GC0,
-logic__8310: tracking_wrapper,
-case__192: VCU118RocketSystem__GC0,
-logic__7764: APBGpsBlock__GC0,
-logic__2910: FPU__GB1,
-logic__5936: RocketTile__GCB0,
-logic__3757: FPU__GB1,
-reg__1046: APBGpsBlock__GC0,
-dsp48e1__30: tracking_wrapper,
-muxpart__32: FPU__GB0,
-datapath__56: VCU118RocketSystem__GC0,
-logic__3846: FPU__GB1,
-logic__3282: FPU__GB2,
-datapath__593: APBGpsBlock__GC0,
-logic__2659: RocketTile__GCB0,
-logic__5279: RocketTile__GCB0,
-logic__6613: VCU118RocketSystem__GC0,
-datapath__30: VCU118RocketSystem__GC0,
-logic__3438: FPU__GB2,
-logic__4158: FPU__GB2,
-logic__4539: RocketTile__GCB0,
-logic__2577: RocketTile__GCB0,
-case__17: genesys2_rocket_top__GC0,
-case__941: VCU118RocketSystem__GC0,
-logic__8127: APBGpsBlock__GC0,
-reg__881: VCU118RocketSystem__GC0,
-logic__8467: tracking_wrapper,
-case__1335: tracking_wrapper,
-reg__667: RocketTile__GCB0,
-reg__420: FPU__GB1,
-logic__2929: FPU__GB1,
-reg__171: VCU118RocketSystem__GC0,
-logic__462: VCU118RocketSystem__GC0,
-reg__1175: tracking_wrapper,
-logic__4603: RocketTile__GCB0,
-reg__1273: tracking_wrapper,
-logic__5407: RocketTile__GCB0,
-logic__3848: FPU__GB1,
-reg__1126: APBGpsBlock__GC0,
-logic__6591: VCU118RocketSystem__GC0,
-logic__2694: FPU__GB1,
-logic__6967: VCU118RocketSystem__GC0,
-logic__6850: VCU118RocketSystem__GC0,
-muxpart__108: RocketTile__GCB0,
-reg__972: VCU118RocketSystem__GC0,
-logic__2122: DCache,
-reg__383: FPU__GB0,
-logic__8230: APBGpsBlock__GC0,
-logic__137: VCU118RocketSystem__GC0,
-logic__654: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__132: VCU118RocketSystem__GC0,
-case__1481: tracking_wrapper,
-datapath__507: VCU118RocketSystem__GC0,
-logic__8018: APBGpsBlock__GC0,
-logic__225: VCU118RocketSystem__GC0,
-reg__1035: APBGpsBlock__GC0,
-logic__7564: VCU118RocketSystem__GC0,
-logic__3450: FPU__GB2,
-datapath__519: VCU118RocketSystem__GC0,
-logic__103: VCU118RocketSystem__GC0,
-logic__1148: VCU118RocketSystem__GC0,
-logic__872: VCU118RocketSystem__GC0,
-IntSyncSyncCrossingSink_n1x2: TilePRCIDomain__GC0,
-logic__7042: VCU118RocketSystem__GC0,
-logic__6578: VCU118RocketSystem__GC0,
-logic__3028: FPU__GB2, FPU__GB1,
-reg__1015: APBGpsBlock__GC0,
-case__460: FPU__GB1,
-case__922: VCU118RocketSystem__GC0,
-logic__1096: VCU118RocketSystem__GC0,
-logic__106: VCU118RocketSystem__GC0,
-reg__336: RocketTile__GCB0,
-logic__2909: FPU__GB1,
-logic__3732: FPU__GB1,
-logic__200: VCU118RocketSystem__GC0,
-logic__3847: FPU__GB1,
-datapath__196: VCU118RocketSystem__GC0,
-logic__7422: VCU118RocketSystem__GC0,
-datapath__669: tracking_wrapper,
-logic__711: VCU118RocketSystem__GC0,
-logic__5430: RocketTile__GCB0,
-logic__2487: RocketTile__GCB0,
-case__882: VCU118RocketSystem__GC0,
-datapath__191: VCU118RocketSystem__GC0,
-datapath__379: FPU__GB2,
-logic__6740: VCU118RocketSystem__GC0,
-logic__677: VCU118RocketSystem__GC0,
-logic__239: VCU118RocketSystem__GC0,
-datapath__530: APBGpsBlock__GC0,
-TLAtomicAutomata_cbus: VCU118RocketSystem__GC0,
-case__472: FPU__GB2,
-case__781: VCU118RocketSystem__GC0,
-reg__554: FPU__GB1,
-case__82: VCU118RocketSystem__GC0,
-TLBuffer_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__2656: RocketTile__GCB0,
-logic__6023: RocketTile__GCB0,
-logic__1449: RocketTile__GCB0,
-case__1353: tracking_wrapper,
-logic__866: VCU118RocketSystem__GC0,
-reg__1312: tracking_wrapper,
-reg__362: RocketTile__GCB0,
-logic__504: VCU118RocketSystem__GC0,
-reg__1135: tracking_wrapper,
-case__655: RocketTile__GCB0,
-logic__7700: APBGpsBlock__GC0,
-logic__7183: VCU118RocketSystem__GC0,
-reg__203: VCU118RocketSystem__GC0,
-logic__1996: DCache,
-reg__1052: APBGpsBlock__GC0,
-case__445: FPU__GB1,
-logic__8503: tracking_wrapper,
-counter__2: VCU118RocketSystem__GC0,
-case__1302: APBGpsBlock__GC0,
-logic__7285: VCU118RocketSystem__GC0,
-case__249: VCU118RocketSystem__GC0,
-datapath__635: tracking_wrapper,
-reg__107: VCU118RocketSystem__GC0,
-logic__7013: VCU118RocketSystem__GC0,
-logic__3004: FPU__GB2, FPU__GB1,
-datapath__403: RocketTile__GCB0,
-datapath__324: FPU__GB2,
-logic__2854: FPU__GB1,
-logic__753: VCU118RocketSystem__GC0,
-logic__2389: RocketTile__GCB0,
-muxpart__17: RocketTile__GCB0,
-case__31: VCU118RocketSystem__GC0,
-dsp48e1__26: APBGpsBlock__GC0,
-logic__8915: APBGpsBlock__GC0,
-logic__3136: FPU__GB2,
-reg__183: VCU118RocketSystem__GC0,
-TLDebugModuleOuter: VCU118RocketSystem__GC0,
-logic__1050: VCU118RocketSystem__GC0,
-case__449: FPU__GB1,
-logic__8728: tracking_wrapper,
-logic__972: VCU118RocketSystem__GC0,
-case__706: RocketTile__GCB0,
-logic__6326: VCU118RocketSystem__GC0,
-case__807: VCU118RocketSystem__GC0,
-case__1394: tracking_wrapper,
-reg__673: RocketTile__GCB0,
-logic__8940: TLToAPB,
-case__427: RocketTile__GCB0,
-IntSyncCrossingSource_n1x1_Registered: VCU118RocketSystem__GC0,
-datapath__670: tracking_wrapper,
-logic__8512: tracking_wrapper,
-case__11: genesys2_rocket_top__GC0,
-reg__910: VCU118RocketSystem__GC0,
-case__834: VCU118RocketSystem__GC0,
-logic__4769: RocketTile__GCB0,
-case__752: RocketTile__GCB0,
-logic__2819: FPU__GB1,
-logic__302: VCU118RocketSystem__GC0,
-logic__2905: FPU__GB1,
-logic__1312: VCU118RocketSystem__GC0,
-reg__495: FPU__GB2,
-case__357: DCache,
-logic__1412: VCU118RocketSystem__GC0,
-logic__241: VCU118RocketSystem__GC0,
-logic__5323: RocketTile__GCB0,
-logic__4241: FPU__GB2,
-logic__7593: VCU118RocketSystem__GC0,
-case__713: RocketTile__GCB0,
-logic__2307: DCache,
-reg__345: RocketTile__GCB0,
-logic__8511: tracking_wrapper,
-logic__3515: FPU__GB1,
-datapath__249: DCache,
-datapath__314: FPU__GB2,
-Rocket: RocketTile__GCB0,
-datapath__166: VCU118RocketSystem__GC0,
-logic__8951: TLToAPB,
-case__440: FPU__GB1,
-TLWidthWidget8: VCU118RocketSystem__GC0,
-reg__448: FPU__GB1,
-DivSqrtRecFNToRaw_small: FPU__GB2,
-case__462: FPU__GB2,
-logic__8456: tracking_wrapper,
-logic__4792: RocketTile__GCB0,
-logic__4257: FPU__GB2,
-logic__4200: FPU__GB2,
-logic__6280: VCU118RocketSystem__GC0,
-case__1403: tracking_wrapper,
-case__1509: tracking_wrapper,
-reg__354: RocketTile__GCB0,
-logic__3918: FPU__GB2, FPU__GB1,
-logic__7400: VCU118RocketSystem__GC0,
-reg__167: VCU118RocketSystem__GC0,
-case__1433: tracking_wrapper,
-logic__4728: RocketTile__GCB0,
-case__709: RocketTile__GCB0,
-case__954: VCU118RocketSystem__GC0,
-logic__4914: RocketTile__GCB0,
-datapath__528: APBGpsBlock__GC0,
-case__99: VCU118RocketSystem__GC0,
-ICache: RocketTile__GCB0,
-reg__24: VCU118RocketSystem__GC0,
-logic__4705: RocketTile__GCB0,
-logic__1759: DCache,
-reg__551: FPU__GB1,
-case__1193: APBGpsBlock__GC0,
-logic__4709: RocketTile__GCB0,
-case__854: VCU118RocketSystem__GC0,
-logic__2861: FPU__GB1,
-datapath__40: VCU118RocketSystem__GC0,
-logic__7589: VCU118RocketSystem__GC0,
-logic__6634: VCU118RocketSystem__GC0,
-logic__3529: FPU__GB1,
-datapath__588: APBGpsBlock__GC0,
-datapath__382: FPU__GB2,
-datapath__627: tracking_wrapper,
-datapath__613: APBGpsBlock__GC0,
-logic__4431: FPU__GB1,
-datapath__618: APBGpsBlock__GC0,
-reg__1125: APBGpsBlock__GC0,
-logic__6928: VCU118RocketSystem__GC0,
-logic__3731: FPU__GB1,
-datapath__2: genesys2_rocket_top__GC0,
-datapath__241: DCache,
-case__454: FPU__GB2, FPU__GB1,
-case__768: RocketTile__GCB0,
-logic__8328: tracking_wrapper,
-logic__6301: VCU118RocketSystem__GC0,
-Queue2_TLBundleA_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__326: RocketTile__GCB0,
-logic__3433: FPU__GB2,
-logic__4175: FPU__GB2,
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1: VCU118RocketSystem__GC0,
-logic__5183: RocketTile__GCB0,
-keep__5: tracking_wrapper,
-TLDebugModuleInner: VCU118RocketSystem__GC0,
-reg__204: VCU118RocketSystem__GC0,
-case__259: VCU118RocketSystem__GC0,
-logic__3223: FPU__GB2,
-TLWidthWidget1: VCU118RocketSystem__GC0,
-keep__10: genesys2_rocket_top__GC0,
-logic__598: VCU118RocketSystem__GC0,
-logic__3741: FPU__GB1,
-case__246: VCU118RocketSystem__GC0,
-logic__1856: RocketTile__GCB0, DCache,
-reg__1120: APBGpsBlock__GC0,
-reg__307: RocketTile__GCB0,
-logic__7139: VCU118RocketSystem__GC0,
-logic__2406: RocketTile__GCB0,
-case__880: VCU118RocketSystem__GC0,
-reg__1198: tracking_wrapper,
-reg__437: FPU__GB2,
-datapath__199: VCU118RocketSystem__GC0,
-logic__7953: APBGpsBlock__GC0,
-logic__741: VCU118RocketSystem__GC0,
-logic__2980: FPU__GB2, FPU__GB1,
-reg__792: VCU118RocketSystem__GC0,
-case__96: VCU118RocketSystem__GC0,
-logic__3601: FPU__GB1,
-logic__429: VCU118RocketSystem__GC0,
-logic__2828: FPU__GB1,
-logic__436: VCU118RocketSystem__GC0,
-datapath__254: DCache,
-datapath__211: VCU118RocketSystem__GC0,
-logic__8222: APBGpsBlock__GC0,
-case__729: RocketTile__GCB0,
-muxpart__111: RocketTile__GCB0,
-reg__233: DCache,
-datapath__181: VCU118RocketSystem__GC0,
-logic__2071: DCache,
-logic__3256: FPU__GB2,
-case__1463: tracking_wrapper,
-logic__6457: VCU118RocketSystem__GC0,
-logic__5962: RocketTile__GCB0,
-logic__5036: RocketTile__GCB0,
-logic__64: genesys2_rocket_top__GC0,
-case__122: VCU118RocketSystem__GC0,
-logic__1495: RocketTile__GCB0,
-logic__1722: DCache,
-reg__578: RocketTile__GCB0,
-reg__552: FPU__GB1,
-reg__18: genesys2_rocket_top__GC0,
-case__893: VCU118RocketSystem__GC0,
-reg__197: VCU118RocketSystem__GC0,
-datapath__222: VCU118RocketSystem__GC0,
-logic__1016: VCU118RocketSystem__GC0,
-case__646: RocketTile__GCB0,
-logic__5370: RocketTile__GCB0,
-case__1348: tracking_wrapper,
-logic__6034: RocketTile__GCB0,
-FPU__GB0: FPU__GB0,
-rom: VCU118RocketSystem__GC0,
-logic__7138: VCU118RocketSystem__GC0,
-reg__129: VCU118RocketSystem__GC0,
-logic__6102: VCU118RocketSystem__GC0,
-reg__956: VCU118RocketSystem__GC0,
-reg__198: VCU118RocketSystem__GC0,
-logic__5869: RocketTile__GCB0,
-logic__2105: DCache,
-logic__7868: APBGpsBlock__GC0,
-logic__78: genesys2_rocket_top__GC0,
-datapath__541: APBGpsBlock__GC0,
-logic__8627: tracking_wrapper,
-logic__5512: RocketTile__GCB0,
-logic__7543: VCU118RocketSystem__GC0,
-LevelGateway: VCU118RocketSystem__GC0,
-logic__6070: RocketTile__GCB0,
-logic__4556: RocketTile__GCB0,
-extram__8: APBGpsBlock__GC0,
-logic__736: VCU118RocketSystem__GC0,
-case__430: RocketTile__GCB0,
-muxpart__35: FPU__GB0,
-logic__4669: RocketTile__GCB0,
-logic__2539: RocketTile__GCB0,
-logic__5431: RocketTile__GCB0,
-logic__2344: RocketTile__GCB0,
-logic__8655: tracking_wrapper,
-datapath__38: VCU118RocketSystem__GC0,
-SystemBus: VCU118RocketSystem__GC0,
-logic__1298: VCU118RocketSystem__GC0,
-case__435: RocketTile__GCB0,
-logic__3780: FPU__GB1,
-logic__4306: FPU__GB1,
-reg__195: VCU118RocketSystem__GC0,
-logic__6847: VCU118RocketSystem__GC0,
-logic__635: VCU118RocketSystem__GC0,
-logic__3331: FPU__GB2,
-case__550: FPU__GB2,
-reg__738: RocketTile__GCB0,
-reg__364: RocketTile__GCB0,
-logic__3651: FPU__GB1,
-TLWidthWidget8_2: VCU118RocketSystem__GC0,
-datapath__99: VCU118RocketSystem__GC0,
-logic__4969: RocketTile__GCB0,
-muxpart__4: genesys2_rocket_top__GC0,
-logic__6456: VCU118RocketSystem__GC0,
-logic__1786: DCache,
-reg__91: VCU118RocketSystem__GC0,
-reg__1341: TLToAPB,
-logic__7720: APBGpsBlock__GC0,
-datapath__62: VCU118RocketSystem__GC0,
-Arbiter4_DCacheDataReq: DCache,
-logic__2972: FPU__GB2, FPU__GB1,
-case__1393: tracking_wrapper,
-datapath__440: RocketTile__GCB0,
-case__1268: APBGpsBlock__GC0,
-logic__5970: RocketTile__GCB0,
-reg__773: TilePRCIDomain__GC0,
-logic__8363: tracking_wrapper,
-logic__3240: FPU__GB2,
-reg__566: FPU__GB1,
-logic__312: VCU118RocketSystem__GC0,
-reg__513: FPU__GB2,
-logic__3950: FPU__GB2, FPU__GB1,
-logic__941: VCU118RocketSystem__GC0,
-logic__7678: APBGpsBlock__GC0,
-logic__22: genesys2_rocket_top__GC0,
-logic__986: VCU118RocketSystem__GC0,
-case__742: RocketTile__GCB0,
-logic__2695: FPU__GB1,
-case__681: RocketTile__GCB0,
-logic__3468: FPU__GB2,
-logic__1966: DCache,
-logic__6375: VCU118RocketSystem__GC0,
-logic__670: VCU118RocketSystem__GC0,
-logic__6899: VCU118RocketSystem__GC0,
-logic__7533: VCU118RocketSystem__GC0,
-case__946: VCU118RocketSystem__GC0,
-logic__851: VCU118RocketSystem__GC0,
-datapath__3: genesys2_rocket_top__GC0,
-logic__6097: VCU118RocketSystem__GC0,
-logic__233: VCU118RocketSystem__GC0,
-logic__656: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__876: VCU118RocketSystem__GC0,
-logic__7267: VCU118RocketSystem__GC0,
-datapath__93: VCU118RocketSystem__GC0,
-case__743: RocketTile__GCB0,
-muxpart__107: RocketTile__GCB0,
-logic__1766: DCache,
-case__931: VCU118RocketSystem__GC0,
-case__1192: APBGpsBlock__GC0,
-logic__382: VCU118RocketSystem__GC0,
-datapath__489: VCU118RocketSystem__GC0,
-reg__311: RocketTile__GCB0,
-case__466: FPU__GB2,
-logic__5228: RocketTile__GCB0,
-logic__6478: VCU118RocketSystem__GC0,
-reg__1307: tracking_wrapper,
-logic__5394: RocketTile__GCB0,
-reg__619: RocketTile__GCB0,
-logic__3904: FPU__GB2, FPU__GB1,
-case__1079: APBGpsBlock__GC0,
-logic__691: VCU118RocketSystem__GC0,
-muxpart__207: APBGpsBlock__GC0,
-case__927: VCU118RocketSystem__GC0,
-datapath__161: VCU118RocketSystem__GC0,
-logic__3398: FPU__GB2,
-logic__5961: RocketTile__GCB0,
-case__1283: APBGpsBlock__GC0,
-logic__4307: FPU__GB1,
-logic__2871: FPU__GB1,
-case__847: VCU118RocketSystem__GC0,
-datapath__58: VCU118RocketSystem__GC0,
-reg__1074: APBGpsBlock__GC0,
-case__352: DCache,
-logic__8751: tracking_wrapper,
-reg__739: RocketTile__GCB0,
-case__312: DCache,
-reg__403: FPU__GB1,
-case__387: RocketTile__GCB0,
-case__1360: tracking_wrapper,
-logic__8559: tracking_wrapper,
-reg__565: FPU__GB1,
-reg__27: VCU118RocketSystem__GC0,
-datapath__373: FPU__GB2,
-case__1124: APBGpsBlock__GC0,
-logic__7955: APBGpsBlock__GC0,
-reg__774: TilePRCIDomain__GC0,
-logic__6484: VCU118RocketSystem__GC0,
-reg__775: TilePRCIDomain__GC0,
-case__735: RocketTile__GCB0,
-logic__3399: FPU__GB2,
-case__1085: APBGpsBlock__GC0,
-datapath__288: FPU__GB1,
-reg__921: VCU118RocketSystem__GC0,
-datapath__102: VCU118RocketSystem__GC0,
-reg__63: VCU118RocketSystem__GC0,
-reg__572: FPU__GB1,
-logic__1754: DCache,
-datapath__399: RocketTile__GCB0,
-logic__1222: VCU118RocketSystem__GC0,
-logic__6563: VCU118RocketSystem__GC0,
-case__557: FPU__GB2,
-reg__473: FPU__GB1,
-reg__271: DCache,
-case__332: DCache,
-logic__597: VCU118RocketSystem__GC0,
-reg__145: VCU118RocketSystem__GC0,
-logic__7057: VCU118RocketSystem__GC0,
-acq_peak_srch: APBGpsBlock__GC0,
-logic__2388: RocketTile__GCB0,
-case__723: RocketTile__GCB0,
-reg__1329: tracking_wrapper,
-logic__7537: VCU118RocketSystem__GC0,
-logic__6667: VCU118RocketSystem__GC0,
-case__302: RocketTile__GCB0,
-logic__7444: VCU118RocketSystem__GC0,
-dsp48e1__24: APBGpsBlock__GC0,
-reg__895: VCU118RocketSystem__GC0,
-case__479: FPU__GB2,
-muxpart__106: RocketTile__GCB0,
-logic__6582: VCU118RocketSystem__GC0,
-logic__3874: FPU__GB2, FPU__GB1,
-case__924: VCU118RocketSystem__GC0,
-dsp48e1__41: tracking_wrapper,
-case__181: VCU118RocketSystem__GC0,
-logic__7524: VCU118RocketSystem__GC0,
-logic__7165: VCU118RocketSystem__GC0,
-datapath__597: APBGpsBlock__GC0,
-reg__1082: APBGpsBlock__GC0,
-logic__2177: DCache,
-logic__1256: VCU118RocketSystem__GC0,
-case__416: RocketTile__GCB0,
-muxpart__233: tracking_wrapper,
-logic__1508: DCache,
-logic__4013: FPU__GB2,
-reg__1033: APBGpsBlock__GC0,
-logic__7286: VCU118RocketSystem__GC0,
-mult_53_53_106: FPU__GB1,
-reg__510: FPU__GB2,
-reg__822: VCU118RocketSystem__GC0,
-keep__1: APBGpsBlock__GC0, tracking_wrapper,
-case__1466: tracking_wrapper,
-logic__6529: VCU118RocketSystem__GC0,
-tracking_wrapper: tracking_wrapper,
-logic__6769: VCU118RocketSystem__GC0,
-logic__6114: VCU118RocketSystem__GC0,
-reg__1225: tracking_wrapper,
-logic__4848: RocketTile__GCB0,
-case__995: VCU118RocketSystem__GC0,
-datapath__287: FPU__GB1,
-datapath__503: VCU118RocketSystem__GC0,
-logic__2823: FPU__GB1,
-reg__808: VCU118RocketSystem__GC0,
-logic__2222: DCache,
-rom__1: APBGpsBlock__GC0,
-reg__557: FPU__GB1,
-case__811: VCU118RocketSystem__GC0,
-reg__353: RocketTile__GCB0,
-logic__1765: DCache,
-case__517: FPU__GB1,
-logic__6453: VCU118RocketSystem__GC0,
-logic__6000: RocketTile__GCB0,
-logic__3777: FPU__GB1,
-reg__178: VCU118RocketSystem__GC0,
-logic__316: VCU118RocketSystem__GC0,
-logic__4354: FPU__GB1,
-logic__881: VCU118RocketSystem__GC0,
-logic__4793: RocketTile__GCB0,
-case__443: FPU__GB1,
-logic__5432: RocketTile__GCB0,
-logic__3906: FPU__GB2, FPU__GB1,
-datapath__642: tracking_wrapper,
-reg__879: VCU118RocketSystem__GC0,
-logic__8742: tracking_wrapper,
-logic__6372: VCU118RocketSystem__GC0,
-muxpart__112: VCU118RocketSystem__GC0,
-logic__477: VCU118RocketSystem__GC0,
-logic__2230: DCache,
-logic__690: VCU118RocketSystem__GC0,
-reg__652: RocketTile__GCB0,
-logic__1630: DCache,
-logic__7423: VCU118RocketSystem__GC0,
-logic__7153: VCU118RocketSystem__GC0,
-case__855: VCU118RocketSystem__GC0,
-reg__258: DCache,
-logic__3300: FPU__GB2,
-logic__1674: DCache,
-logic__957: VCU118RocketSystem__GC0,
-logic__2263: DCache,
-logic__877: VCU118RocketSystem__GC0,
-reg__112: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__751: RocketTile__GCB0,
-muxpart__99: RocketTile__GCB0,
-case__695: RocketTile__GCB0,
-case__58: VCU118RocketSystem__GC0,
-reg__1020: APBGpsBlock__GC0,
-datapath__686: tracking_wrapper,
-reg__332: RocketTile__GCB0,
-case__7: genesys2_rocket_top__GC0,
-logic__2517: RocketTile__GCB0,
-logic__6571: VCU118RocketSystem__GC0,
-logic__5306: RocketTile__GCB0,
-reg__967: VCU118RocketSystem__GC0,
-case__1381: tracking_wrapper,
-case__488: FPU__GB2,
-reg__901: VCU118RocketSystem__GC0,
-logic__6356: VCU118RocketSystem__GC0,
-case__408: RocketTile__GCB0,
-logic__136: VCU118RocketSystem__GC0,
-reg__1107: APBGpsBlock__GC0,
-logic__6485: VCU118RocketSystem__GC0,
-logic__4343: FPU__GB1,
-datapath__322: FPU__GB2,
-case__138: VCU118RocketSystem__GC0,
-muxpart__46: FPU__GB0,
-logic__4203: FPU__GB2,
-logic__6788: VCU118RocketSystem__GC0,
-case__989: VCU118RocketSystem__GC0,
-logic__3726: FPU__GB1,
-case__1058: APBGpsBlock__GC0,
-case__1003: VCU118RocketSystem__GC0,
-logic__4872: RocketTile__GCB0,
-logic__5149: RocketTile__GCB0,
-reg__982: VCU118RocketSystem__GC0,
-reg__384: FPU__GB0,
-case__1191: APBGpsBlock__GC0,
-TLInterconnectCoupler_cbus_to_bus_named_pbus: VCU118RocketSystem__GC0,
-case__825: VCU118RocketSystem__GC0,
-datapath__257: DCache,
-datapath__428: RocketTile__GCB0,
-logic__7190: VCU118RocketSystem__GC0,
-reg__765: RocketTile__GCB0,
-case__570: FPU__GB1,
-reg__753: RocketTile__GCB0,
-logic__1374: VCU118RocketSystem__GC0,
-reg__60: VCU118RocketSystem__GC0,
-logic__6974: VCU118RocketSystem__GC0,
-case__279: VCU118RocketSystem__GC0,
-logic__3103: FPU__GB2,
-logic__6332: VCU118RocketSystem__GC0,
-case__303: DCache,
-case__806: VCU118RocketSystem__GC0,
-logic__4034: FPU__GB2,
-case__100: VCU118RocketSystem__GC0,
-case__1535: TLToAPB,
-datapath__684: tracking_wrapper,
-dsp48e1__45: tracking_wrapper,
-logic__3670: FPU__GB1,
-logic__5951: RocketTile__GCB0,
-logic__4956: RocketTile__GCB0,
-logic__960: VCU118RocketSystem__GC0,
-reg__493: FPU__GB2,
-reg__516: FPU__GB2,
-reg__1058: APBGpsBlock__GC0,
-case__1050: VCU118RocketSystem__GC0,
-case__450: FPU__GB2, FPU__GB1,
-logic__2381: RocketTile__GCB0,
-case__1174: APBGpsBlock__GC0,
-case__875: VCU118RocketSystem__GC0,
-logic__560: VCU118RocketSystem__GC0,
-logic__4239: FPU__GB2,
-reg__245: DCache,
-case__938: VCU118RocketSystem__GC0,
-datapath__295: FPU__GB1,
-logic__1605: DCache,
-logic__7577: VCU118RocketSystem__GC0,
-logic__3392: FPU__GB2,
-logic__1397: VCU118RocketSystem__GC0,
-logic__1844: RocketTile__GCB0, DCache,
-case__1009: VCU118RocketSystem__GC0,
-logic__3086: FPU__GB2,
-reg__1038: APBGpsBlock__GC0,
-CSRFile: RocketTile__GCB0,
-logic__8697: tracking_wrapper,
-logic__6525: VCU118RocketSystem__GC0,
-reg__843: VCU118RocketSystem__GC0,
-reg__1089: APBGpsBlock__GC0,
-reg__795: VCU118RocketSystem__GC0,
-logic__2172: DCache,
-datapath__568: APBGpsBlock__GC0,
-datapath__650: tracking_wrapper,
-reg__902: VCU118RocketSystem__GC0,
-logic__3841: FPU__GB1,
-case__26: VCU118RocketSystem__GC0,
-logic__4838: RocketTile__GCB0,
-datapath__250: DCache,
-case__1419: tracking_wrapper,
-logic__689: VCU118RocketSystem__GC0,
-counter__3: DCache,
-reg__472: FPU__GB1,
-case__378: RocketTile__GCB0,
-logic__2024: DCache,
-case__951: VCU118RocketSystem__GC0,
-logic__7676: APBGpsBlock__GC0,
-case__598: FPU__GB0,
-logic__4929: RocketTile__GCB0,
-logic__6117: VCU118RocketSystem__GC0,
-logic__924: VCU118RocketSystem__GC0,
-datapath__78: VCU118RocketSystem__GC0,
-case__1183: APBGpsBlock__GC0,
-reg__1123: APBGpsBlock__GC0,
-logic__3682: FPU__GB1,
-logic__8671: tracking_wrapper,
-logic__3727: FPU__GB1,
-reg__616: RocketTile__GCB0,
-logic__879: VCU118RocketSystem__GC0,
-logic__4800: RocketTile__GCB0,
-datapath__178: VCU118RocketSystem__GC0,
-logic__6024: RocketTile__GCB0,
-logic__735: VCU118RocketSystem__GC0,
-logic__6103: VCU118RocketSystem__GC0,
-datapath__275: RocketTile__GCB0,
-datapath__673: tracking_wrapper,
-logic__6002: RocketTile__GCB0,
-reg__981: VCU118RocketSystem__GC0,
-logic__2936: FPU__GB1,
-logic__8860: tracking_wrapper,
-case__1435: tracking_wrapper,
-case__722: RocketTile__GCB0,
-reg__1187: tracking_wrapper,
-reg__310: RocketTile__GCB0,
-logic__8815: tracking_wrapper,
-logic__5522: RocketTile__GCB0,
-datapath__675: tracking_wrapper,
-case__1517: tracking_wrapper,
-reg__1330: tracking_wrapper,
-case__975: VCU118RocketSystem__GC0,
-cordic_angle_lut__parameterized0: tracking_wrapper,
-logic__6080: TilePRCIDomain__GC0,
-logic__1303: VCU118RocketSystem__GC0,
-case__630: RocketTile__GCB0,
-logic__7682: APBGpsBlock__GC0,
-case__219: VCU118RocketSystem__GC0,
-datapath__60: VCU118RocketSystem__GC0,
-logic__2691: FPU__GB1,
-logic__2380: RocketTile__GCB0,
-logic__733: VCU118RocketSystem__GC0,
-case__511: FPU__GB1,
-case__1118: APBGpsBlock__GC0,
-datapath__49: VCU118RocketSystem__GC0,
-logic__2259: DCache,
-datapath__577: APBGpsBlock__GC0,
-reg__1108: APBGpsBlock__GC0,
-reg__230: DCache,
-logic__1340: VCU118RocketSystem__GC0,
-case__1275: APBGpsBlock__GC0,
-case__1159: APBGpsBlock__GC0,
-logic__2976: FPU__GB2, FPU__GB1,
-reg__49: VCU118RocketSystem__GC0,
-reg__108: VCU118RocketSystem__GC0,
-datapath__13: VCU118RocketSystem__GC0,
-case__1227: APBGpsBlock__GC0,
-dsp48e1__7: APBGpsBlock__GC0,
-logic__2927: FPU__GB1,
-reg__636: RocketTile__GCB0,
-reg__1244: tracking_wrapper,
-logic__7279: VCU118RocketSystem__GC0,
-reg__1130: tracking_wrapper,
-reg__131: VCU118RocketSystem__GC0,
-logic__3609: FPU__GB1,
-case__283: RocketTile__GCB0,
-datapath__193: VCU118RocketSystem__GC0,
-logic__6216: VCU118RocketSystem__GC0,
-logic__1302: VCU118RocketSystem__GC0,
-logic__1141: VCU118RocketSystem__GC0,
-reg__377: FPU__GB0,
-logic__7252: VCU118RocketSystem__GC0,
-case__925: VCU118RocketSystem__GC0,
-datapath__600: APBGpsBlock__GC0,
-logic__3259: FPU__GB2,
-logic__6743: VCU118RocketSystem__GC0,
-logic__6004: RocketTile__GCB0,
-logic__6293: VCU118RocketSystem__GC0,
-logic__6116: VCU118RocketSystem__GC0,
-logic__4251: FPU__GB2,
-logic__4220: FPU__GB2,
-reg__1206: tracking_wrapper,
-logic__3447: FPU__GB2,
-datapath__12: VCU118RocketSystem__GC0,
-reg__1103: APBGpsBlock__GC0,
-logic__2083: DCache,
-reg__828: VCU118RocketSystem__GC0,
-logic__8930: TLToAPB,
-case__1160: APBGpsBlock__GC0,
-logic__1905: DCache,
-datapath__110: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__1594: DCache,
-case__982: VCU118RocketSystem__GC0,
-logic__1168: VCU118RocketSystem__GC0,
-logic__6749: VCU118RocketSystem__GC0,
-datapath__463: TilePRCIDomain__GC0,
-logic__2870: FPU__GB1,
-reg__33: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__306: DCache,
-reg__319: RocketTile__GCB0,
-TLXbar_sbus_i2_o1_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__3773: FPU__GB1,
-logic__4474: FPU__GB1,
-reg__515: FPU__GB2,
-logic__7976: APBGpsBlock__GC0,
-datapath__501: VCU118RocketSystem__GC0,
-logic__5528: RocketTile__GCB0,
-reg__314: RocketTile__GCB0,
-logic__2185: DCache,
-datapath__42: VCU118RocketSystem__GC0,
-datapath__434: RocketTile__GCB0,
-case__800: VCU118RocketSystem__GC0,
-logic__2965: FPU__GB2, FPU__GB1,
-logic__6086: VCU118RocketSystem__GC0,
-reg__381: FPU__GB0,
-logic__4779: RocketTile__GCB0,
-logic__1344: VCU118RocketSystem__GC0,
-logic__734: VCU118RocketSystem__GC0,
-logic__3787: FPU__GB1,
-reg__483: FPU__GB1,
-datapath__308: FPU__GB2,
-logic__1176: VCU118RocketSystem__GC0,
-datapath__567: APBGpsBlock__GC0,
-reg__1308: tracking_wrapper,
-case__317: DCache,
-logic__2169: DCache,
-logic__4648: RocketTile__GCB0,
-PlusArgTimeout: RocketTile__GCB0,
-case__1027: VCU118RocketSystem__GC0,
-logic__387: VCU118RocketSystem__GC0,
-logic__3446: FPU__GB2,
-case__37: VCU118RocketSystem__GC0,
-case__182: VCU118RocketSystem__GC0,
-datapath__44: VCU118RocketSystem__GC0,
-logic__8386: tracking_wrapper,
-datapath__202: VCU118RocketSystem__GC0,
-logic__6623: VCU118RocketSystem__GC0,
-logic__2129: DCache,
-datapath__426: RocketTile__GCB0,
-logic__6392: VCU118RocketSystem__GC0,
-logic__82: genesys2_rocket_top__GC0,
-logic__6157: VCU118RocketSystem__GC0,
-reg__575: RocketTile__GCB0,
-reg__238: DCache,
-logic__2384: RocketTile__GCB0,
-datapath__79: VCU118RocketSystem__GC0,
-logic__3671: FPU__GB1,
-case__1039: VCU118RocketSystem__GC0,
-muxpart__229: tracking_wrapper,
-TLDebugModuleOuterAsync: VCU118RocketSystem__GC0,
-logic__6419: VCU118RocketSystem__GC0,
-datapath__146: VCU118RocketSystem__GC0,
-reg__818: VCU118RocketSystem__GC0,
-logic__6085: VCU118RocketSystem__GC0,
-reg__1345: TLToAPB,
-datapath__177: VCU118RocketSystem__GC0,
-logic__4284: FPU__GB1,
-logic__7464: VCU118RocketSystem__GC0,
-logic__2386: RocketTile__GCB0,
-logic__2883: FPU__GB1,
-logic__2221: DCache,
-logic__7342: VCU118RocketSystem__GC0,
-case__863: VCU118RocketSystem__GC0,
-logic__502: VCU118RocketSystem__GC0,
-reg__1250: tracking_wrapper,
-reg__951: VCU118RocketSystem__GC0,
-logic__3481: FPU__GB2,
-logic__5375: RocketTile__GCB0,
-case__3: genesys2_rocket_top__GC0,
-logic__7144: VCU118RocketSystem__GC0,
-datapath__502: VCU118RocketSystem__GC0,
-logic__415: VCU118RocketSystem__GC0,
-AsyncValidSync: VCU118RocketSystem__GC0,
-case__461: FPU__GB2,
-logic__4269: FPU__GB2,
-datapath__443: RocketTile__GCB0,
-logic__7373: VCU118RocketSystem__GC0,
-logic__3775: FPU__GB1,
-datapath__297: FPU__GB2, FPU__GB1,
-logic__6755: VCU118RocketSystem__GC0,
-reg__754: RocketTile__GCB0,
-logic__6156: VCU118RocketSystem__GC0,
-logic__1745: DCache,
-logic__1588: DCache,
-case__1230: APBGpsBlock__GC0,
-logic__5267: RocketTile__GCB0,
-reg__124: VCU118RocketSystem__GC0,
-logic__6798: VCU118RocketSystem__GC0,
-logic__2256: DCache,
-datapath__294: FPU__GB1,
-case__290: RocketTile__GCB0,
-logic__6714: VCU118RocketSystem__GC0,
-reg__820: VCU118RocketSystem__GC0,
-logic__104: VCU118RocketSystem__GC0,
-logic__6255: VCU118RocketSystem__GC0,
-case__507: FPU__GB1,
-reg__587: RocketTile__GCB0,
-reg__57: VCU118RocketSystem__GC0,
-datapath__59: VCU118RocketSystem__GC0,
-reg__293: RocketTile__GCB0,
-logic__4902: RocketTile__GCB0,
-logic__2396: RocketTile__GCB0,
-LF_carr: tracking_wrapper,
-case__35: VCU118RocketSystem__GC0,
-logic__3615: FPU__GB1,
-case__40: VCU118RocketSystem__GC0,
-datapath__7: VCU118RocketSystem__GC0,
-case__1456: tracking_wrapper,
-logic__4598: RocketTile__GCB0,
-logic__806: VCU118RocketSystem__GC0,
-logic__6365: VCU118RocketSystem__GC0,
-logic__5985: RocketTile__GCB0,
-logic__4375: FPU__GB1,
-reg__1124: APBGpsBlock__GC0,
-reg__917: VCU118RocketSystem__GC0,
-logic__2858: FPU__GB1,
-logic__4777: RocketTile__GCB0,
-datapath__442: RocketTile__GCB0,
-logic__3884: FPU__GB2, FPU__GB1,
-case__299: RocketTile__GCB0,
-logic__1339: VCU118RocketSystem__GC0,
-logic__4760: RocketTile__GCB0,
-reg__459: FPU__GB1,
-logic__5663: RocketTile__GCB0,
-logic__190: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__5382: RocketTile__GCB0,
-logic__5860: RocketTile__GCB0,
-reg__410: FPU__GB1,
-MulAddRecFNToRaw_postMul_1: FPU__GB1,
-logic__1037: VCU118RocketSystem__GC0,
-logic__7541: VCU118RocketSystem__GC0,
-reg__825: VCU118RocketSystem__GC0,
-reg__846: VCU118RocketSystem__GC0,
-datapath__464: TilePRCIDomain__GC0,
-reg__880: VCU118RocketSystem__GC0,
-logic__6165: VCU118RocketSystem__GC0,
-reg__1227: tracking_wrapper,
-logic__6010: RocketTile__GCB0,
-logic__1169: VCU118RocketSystem__GC0,
-logic__588: VCU118RocketSystem__GC0,
-logic__3284: FPU__GB2,
-logic__4101: FPU__GB2,
-logic__4247: FPU__GB2,
-muxpart__28: FPU__GB0,
-case__394: RocketTile__GCB0,
-reg__779: VCU118RocketSystem__GC0,
-case__585: FPU__GB1,
-case__1398: tracking_wrapper,
-logic__498: VCU118RocketSystem__GC0,
-datapath__420: RocketTile__GCB0,
-datapath__109: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__932: VCU118RocketSystem__GC0,
-datapath__321: FPU__GB2,
-logic__3541: FPU__GB1,
-logic__3755: FPU__GB1,
-logic__6540: VCU118RocketSystem__GC0,
-case__782: VCU118RocketSystem__GC0,
-lock_detector: tracking_wrapper,
-case__577: FPU__GB2,
-logic__2166: DCache,
-logic__3749: FPU__GB1,
-case__353: DCache,
-reg__252: DCache,
-logic__3070: FPU__GB2,
-logic__4002: FPU__GB2,
-case__178: VCU118RocketSystem__GC0,
-logic__3441: FPU__GB2,
-case__1088: APBGpsBlock__GC0,
-logic__1465: RocketTile__GCB0,
-logic__2093: DCache,
-logic__6361: VCU118RocketSystem__GC0,
-case__890: VCU118RocketSystem__GC0,
-logic__6101: VCU118RocketSystem__GC0,
-logic__901: VCU118RocketSystem__GC0,
-logic__4435: FPU__GB0,
-logic__7204: VCU118RocketSystem__GC0,
-logic__6530: VCU118RocketSystem__GC0,
-dsp48e1__13: APBGpsBlock__GC0,
-logic__7115: VCU118RocketSystem__GC0,
-case__535: FPU__GB2,
-logic__890: VCU118RocketSystem__GC0,
-logic__3850: FPU__GB1,
-reg__329: RocketTile__GCB0,
-logic__4219: FPU__GB2,
-logic__5145: RocketTile__GCB0,
-sample_counter: APBGpsBlock__GC0,
-reg__847: VCU118RocketSystem__GC0,
-datapath__98: VCU118RocketSystem__GC0,
-logic__3752: FPU__GB1,
-logic__4205: FPU__GB2,
-reg__1027: APBGpsBlock__GC0,
-reg__788: VCU118RocketSystem__GC0,
-logic__1217: VCU118RocketSystem__GC0,
-case__95: VCU118RocketSystem__GC0,
-logic__4631: RocketTile__GCB0,
-case__1235: APBGpsBlock__GC0,
-DivSqrtRawFN_small_1: FPU__GB2,
-logic__7952: APBGpsBlock__GC0,
-case__1273: APBGpsBlock__GC0,
-reg__48: VCU118RocketSystem__GC0,
-reg__539: FPU__GB1,
-case__493: FPU__GB2,
-logic__6220: VCU118RocketSystem__GC0,
-logic__8885: APBGpsBlock__GC0,
-logic__2977: FPU__GB2, FPU__GB1,
-reg__327: RocketTile__GCB0,
-logic__902: VCU118RocketSystem__GC0,
-logic__6732: VCU118RocketSystem__GC0,
-logic__6174: VCU118RocketSystem__GC0,
-case__337: DCache,
-case__434: RocketTile__GCB0,
-logic__1904: DCache,
-datapath__173: VCU118RocketSystem__GC0,
-reg__665: RocketTile__GCB0,
-logic__6718: VCU118RocketSystem__GC0,
-reg__623: RocketTile__GCB0,
-case__300: RocketTile__GCB0,
-case__657: RocketTile__GCB0,
-logic__2243: DCache,
-case__1382: tracking_wrapper,
-logic__8158: APBGpsBlock__GC0,
-reg__769: RocketTile__GCB0,
-case__1336: tracking_wrapper,
-reg__333: RocketTile__GCB0,
-reg__87: VCU118RocketSystem__GC0,
-logic__6719: VCU118RocketSystem__GC0,
-logic__1908: DCache,
-logic__1080: VCU118RocketSystem__GC0,
-logic__2840: FPU__GB1,
-logic__3872: FPU__GB2, FPU__GB1,
-case__330: DCache,
-logic__3763: FPU__GB1,
-case__796: VCU118RocketSystem__GC0,
-case__1412: tracking_wrapper,
-logic__4963: RocketTile__GCB0,
-logic__6660: VCU118RocketSystem__GC0,
-logic__463: VCU118RocketSystem__GC0,
-case__1528: TLToAPB,
-logic__2125: DCache,
-reg__1032: APBGpsBlock__GC0,
-logic__7427: VCU118RocketSystem__GC0,
-logic__5486: RocketTile__GCB0,
-reg__482: FPU__GB1,
-Queue2_TLBundleA_a32d64s2k1z3u: TilePRCIDomain__GC0,
-reg__1128: APBGpsBlock__GC0,
-reg__1188: tracking_wrapper,
-logic__6508: VCU118RocketSystem__GC0,
-logic__680: VCU118RocketSystem__GC0,
-datapath__36: VCU118RocketSystem__GC0,
-cordic_angle_lut: tracking_wrapper,
-logic__2357: RocketTile__GCB0,
-logic__8411: tracking_wrapper,
-logic__1092: VCU118RocketSystem__GC0,
-reg__891: VCU118RocketSystem__GC0,
-logic__7531: VCU118RocketSystem__GC0,
-CLINT: VCU118RocketSystem__GC0,
-case__1084: APBGpsBlock__GC0,
-case__1130: APBGpsBlock__GC0,
-reg__817: VCU118RocketSystem__GC0,
-datapath__614: APBGpsBlock__GC0,
-TLInterconnectCoupler_sbus_to_bus_named_cbus: VCU118RocketSystem__GC0,
-FixedClockBroadcast_3: VCU118RocketSystem__GC0,
-logic__819: VCU118RocketSystem__GC0,
-logic__4333: FPU__GB1,
-logic__946: VCU118RocketSystem__GC0,
-reg__140: VCU118RocketSystem__GC0,
-reg__1098: APBGpsBlock__GC0,
-logic__8729: tracking_wrapper,
-logic__2888: FPU__GB1,
-logic__6470: VCU118RocketSystem__GC0,
-logic__3621: FPU__GB1,
-logic__1034: VCU118RocketSystem__GC0,
-logic__904: VCU118RocketSystem__GC0,
-case__529: FPU__GB1,
-logic__3905: FPU__GB2, FPU__GB1,
-case__4: genesys2_rocket_top__GC0,
-logic__7081: VCU118RocketSystem__GC0,
-case__1083: APBGpsBlock__GC0,
-FPU__GB2: FPU__GB2,
-logic__3263: FPU__GB2,
-logic__6765: VCU118RocketSystem__GC0,
-reg__256: DCache,
-datapath__323: FPU__GB2,
-muxpart__93: FPU__GB1,
-logic__1369: VCU118RocketSystem__GC0,
-logic__6104: VCU118RocketSystem__GC0,
-reg__597: RocketTile__GCB0,
-Queue2_TLBundleA_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__8226: APBGpsBlock__GC0,
-reg__761: RocketTile__GCB0,
-logic__8303: tracking_wrapper,
-logic__829: VCU118RocketSystem__GC0,
-reg__456: FPU__GB1,
-logic__4546: RocketTile__GCB0,
-logic__1172: VCU118RocketSystem__GC0,
-reg__1069: APBGpsBlock__GC0,
-reg__943: VCU118RocketSystem__GC0,
-logic__3816: FPU__GB1,
-logic__7324: VCU118RocketSystem__GC0,
-logic__373: VCU118RocketSystem__GC0,
-reg__1136: tracking_wrapper,
-reg__676: RocketTile__GCB0,
-case__987: VCU118RocketSystem__GC0,
-logic__206: VCU118RocketSystem__GC0,
-ClockCrossingReg_w43: VCU118RocketSystem__GC0,
-case__335: DCache,
-case__1141: APBGpsBlock__GC0,
-logic__7640: VCU118RocketSystem__GC0,
-logic__4300: FPU__GB1,
-logic__757: VCU118RocketSystem__GC0,
-muxpart__36: FPU__GB0,
-logic__1810: DCache,
-logic__7318: VCU118RocketSystem__GC0,
-logic__1084: VCU118RocketSystem__GC0,
-datapath__221: VCU118RocketSystem__GC0,
-logic__2282: DCache,
-logic__2693: FPU__GB1,
-reg__1167: tracking_wrapper,
-muxpart__86: FPU__GB1,
-case__90: VCU118RocketSystem__GC0,
-case__809: VCU118RocketSystem__GC0,
-reg__442: FPU__GB2,
-reg__89: VCU118RocketSystem__GC0,
-logic__6741: VCU118RocketSystem__GC0,
-logic__6003: RocketTile__GCB0,
-dsp48e1__18: APBGpsBlock__GC0,
-reg__874: VCU118RocketSystem__GC0,
-logic__127: VCU118RocketSystem__GC0,
-logic__4990: RocketTile__GCB0,
-logic__6775: VCU118RocketSystem__GC0,
-datapath__349: FPU__GB1,
-logic__4458: FPU__GB1,
-case__850: VCU118RocketSystem__GC0,
-datapath__302: FPU__GB1,
-logic__178: VCU118RocketSystem__GC0,
-reg__322: RocketTile__GCB0,
-reg__596: RocketTile__GCB0,
-logic__5393: RocketTile__GCB0,
-logic__286: VCU118RocketSystem__GC0,
-ClockGroupAggregator_pbus: VCU118RocketSystem__GC0,
-case__1437: tracking_wrapper,
-reg__1200: tracking_wrapper,
-datapath__355: FPU__GB1,
-logic__6725: VCU118RocketSystem__GC0,
-logic__3779: FPU__GB1,
-datapath__589: APBGpsBlock__GC0,
-logic__3488: FPU__GB2,
-datapath__90: VCU118RocketSystem__GC0,
-case__212: VCU118RocketSystem__GC0,
-logic__1136: VCU118RocketSystem__GC0,
-logic__5852: RocketTile__GCB0,
-logic__2797: FPU__GB1,
-logic__1505: DCache,
-reg__1306: tracking_wrapper,
-reg__1049: APBGpsBlock__GC0,
-logic__794: VCU118RocketSystem__GC0,
-logic__2109: DCache,
-logic__8144: APBGpsBlock__GC0,
-logic__1263: VCU118RocketSystem__GC0,
-logic__416: VCU118RocketSystem__GC0,
-logic__3641: FPU__GB1,
-case__1081: APBGpsBlock__GC0,
-logic__3533: FPU__GB1,
-datapath__75: VCU118RocketSystem__GC0,
-case__724: RocketTile__GCB0,
-case__88: VCU118RocketSystem__GC0,
-case__45: VCU118RocketSystem__GC0,
-logic__2589: RocketTile__GCB0,
-case__432: RocketTile__GCB0,
-reg__606: RocketTile__GCB0,
-case__114: VCU118RocketSystem__GC0,
-reg__408: FPU__GB1,
-logic__798: VCU118RocketSystem__GC0,
-logic__6722: VCU118RocketSystem__GC0,
-datapath__471: VCU118RocketSystem__GC0,
-logic__6217: VCU118RocketSystem__GC0,
-case__197: VCU118RocketSystem__GC0,
-logic__5928: RocketTile__GCB0,
-logic__7390: VCU118RocketSystem__GC0,
-logic__172: VCU118RocketSystem__GC0,
-reg__1028: APBGpsBlock__GC0,
-logic__1093: VCU118RocketSystem__GC0,
-logic__782: VCU118RocketSystem__GC0,
-butterfly__parameterized1: APBGpsBlock__GC0,
-reg__224: VCU118RocketSystem__GC0,
-logic__3860: FPU__GB1,
-logic__4855: RocketTile__GCB0,
-logic__7410: VCU118RocketSystem__GC0,
-logic__3814: FPU__GB1,
-logic__134: VCU118RocketSystem__GC0,
-case__1188: APBGpsBlock__GC0,
-datapath__198: VCU118RocketSystem__GC0,
-logic__1685: DCache,
-reg__845: VCU118RocketSystem__GC0,
-case__956: VCU118RocketSystem__GC0,
-logic__683: VCU118RocketSystem__GC0,
-logic__625: VCU118RocketSystem__GC0,
-datapath__612: APBGpsBlock__GC0,
-logic__6727: VCU118RocketSystem__GC0,
-logic__6005: RocketTile__GCB0,
-logic__1174: VCU118RocketSystem__GC0,
-logic__6766: VCU118RocketSystem__GC0,
-logic__518: VCU118RocketSystem__GC0,
-reg__19: VCU118RocketSystem__GC0,
-logic__8923: APBGpsBlock__GC0,
-logic__4636: RocketTile__GCB0,
-reg__156: VCU118RocketSystem__GC0,
-reg__736: RocketTile__GCB0,
-case__680: RocketTile__GCB0,
-logic__7627: VCU118RocketSystem__GC0,
-logic__7526: VCU118RocketSystem__GC0,
-case__772: RocketTile__GCB0,
-case__1357: tracking_wrapper,
-case__592: FPU__GB1,
-datapath__197: VCU118RocketSystem__GC0,
-RoundAnyRawFNToRecFN_2: FPU__GB2,
-logic__6506: VCU118RocketSystem__GC0,
-case__1532: TLToAPB,
-logic__1825: RocketTile__GCB0, DCache,
-case__1383: tracking_wrapper,
-case__513: FPU__GB1,
-reg__300: RocketTile__GCB0,
-muxpart__87: FPU__GB2,
-datapath__208: VCU118RocketSystem__GC0,
-logic__95: genesys2_rocket_top__GC0,
-datapath__680: tracking_wrapper,
-logic__4126: FPU__GB2,
-case__417: RocketTile__GCB0,
-case__136: VCU118RocketSystem__GC0,
-logic__4417: FPU__GB1,
-logic__8385: tracking_wrapper,
-case__1212: APBGpsBlock__GC0,
-case__728: RocketTile__GCB0,
-logic__4261: FPU__GB2,
-logic__6173: VCU118RocketSystem__GC0,
-logic__4905: RocketTile__GCB0,
-case__798: VCU118RocketSystem__GC0,
-logic__4495: RocketTile__GCB0,
-reg__397: FPU__GB1,
-case__515: FPU__GB1,
-AsyncQueueSink_DebugInternalBundle: VCU118RocketSystem__GC0,
-logic__7454: VCU118RocketSystem__GC0,
-logic__7532: VCU118RocketSystem__GC0,
-logic__1767: DCache,
-case__243: VCU118RocketSystem__GC0,
-case__1522: APBGpsBlock__GC0,
-datapath__350: FPU__GB1,
-reg__12: genesys2_rocket_top__GC0,
-reg__948: VCU118RocketSystem__GC0,
-logic__6583: VCU118RocketSystem__GC0,
-logic__2712: FPU__GB1,
-logic__1725: DCache,
-logic__148: VCU118RocketSystem__GC0,
-case__119: VCU118RocketSystem__GC0,
-logic__7793: APBGpsBlock__GC0,
-logic__6619: VCU118RocketSystem__GC0,
-counter__6: VCU118RocketSystem__GC0,
-reg__576: RocketTile__GCB0,
-logic__874: VCU118RocketSystem__GC0,
-logic__7228: VCU118RocketSystem__GC0,
-logic__1382: VCU118RocketSystem__GC0,
-datapath__452: RocketTile__GCB0,
-logic__2705: FPU__GB1,
-logic__3774: FPU__GB1,
-logic__5329: RocketTile__GCB0,
-reg__421: FPU__GB1,
-logic__1368: VCU118RocketSystem__GC0,
-logic__3327: FPU__GB2,
-logic__1682: DCache,
-logic__4721: RocketTile__GCB0,
-logic__4179: FPU__GB2,
-TLInterconnectCoupler_cbus_to_rockettile: VCU118RocketSystem__GC0,
-FixedClockBroadcast_5: VCU118RocketSystem__GC0,
-case__470: FPU__GB2,
-datapath__630: tracking_wrapper,
-logic__4302: FPU__GB1,
-logic__6013: RocketTile__GCB0,
-datapath__96: VCU118RocketSystem__GC0,
-logic__303: VCU118RocketSystem__GC0,
-logic__4117: FPU__GB2,
-logic__6562: VCU118RocketSystem__GC0,
-keep__2: tracking_wrapper,
-case__981: VCU118RocketSystem__GC0,
-fft_radix_2__parameterized0: APBGpsBlock__GC0,
-logic__7553: VCU118RocketSystem__GC0,
-reg__807: VCU118RocketSystem__GC0,
-reg__134: VCU118RocketSystem__GC0,
-logic__3052: FPU__GB2,
-case__1093: APBGpsBlock__GC0,
-muxpart__12: DCache,
-case__377: RocketTile__GCB0,
-muxpart__110: RocketTile__GCB0,
-datapath__561: APBGpsBlock__GC0,
-logic__6767: VCU118RocketSystem__GC0,
-logic__6565: VCU118RocketSystem__GC0,
-logic__252: VCU118RocketSystem__GC0,
-reg__1084: APBGpsBlock__GC0,
-logic__8415: tracking_wrapper,
-logic__7771: APBGpsBlock__GC0,
-logic__7336: VCU118RocketSystem__GC0,
-reg__1201: tracking_wrapper,
-logic__7852: APBGpsBlock__GC0,
-reg__1199: tracking_wrapper,
-logic__599: VCU118RocketSystem__GC0,
-reg__356: RocketTile__GCB0,
-reg__435: FPU__GB2,
-logic__1826: RocketTile__GCB0, DCache,
-muxpart__114: VCU118RocketSystem__GC0,
-case__345: DCache,
-reg__342: RocketTile__GCB0,
-dsp48e1__10: APBGpsBlock__GC0,
-logic__7177: VCU118RocketSystem__GC0,
-logic__6704: VCU118RocketSystem__GC0,
-datapath__23: VCU118RocketSystem__GC0,
-datapath__246: DCache,
-logic__7396: VCU118RocketSystem__GC0,
-reg__215: VCU118RocketSystem__GC0,
-logic__2391: RocketTile__GCB0,
-logic__3061: FPU__GB2,
-logic__6030: RocketTile__GCB0,
-logic__5193: RocketTile__GCB0,
-reg__959: VCU118RocketSystem__GC0,
-reg__811: VCU118RocketSystem__GC0,
-logic__7069: VCU118RocketSystem__GC0,
-reg__746: RocketTile__GCB0,
-case__787: VCU118RocketSystem__GC0,
-logic__1999: DCache,
-case__62: VCU118RocketSystem__GC0,
-logic__3909: FPU__GB2, FPU__GB1,
-case__612: RocketTile__GCB0,
-datapath__251: DCache,
-acq_nco_carr: APBGpsBlock__GC0,
-datapath__629: tracking_wrapper,
-reg__430: FPU__GB2,
-logic__1158: VCU118RocketSystem__GC0,
-logic__513: VCU118RocketSystem__GC0,
-reg__549: FPU__GB1,
-logic__2463: RocketTile__GCB0,
-extram__5: APBGpsBlock__GC0,
-logic__7899: APBGpsBlock__GC0,
-logic__8025: APBGpsBlock__GC0,
-case__154: VCU118RocketSystem__GC0,
-logic__247: VCU118RocketSystem__GC0,
-case__629: RocketTile__GCB0,
-case__877: VCU118RocketSystem__GC0,
-muxpart__11: DCache,
-logic__1333: VCU118RocketSystem__GC0,
-logic__1899: DCache,
-case__953: VCU118RocketSystem__GC0,
-reg__142: VCU118RocketSystem__GC0,
-case__756: RocketTile__GCB0,
-logic__1982: DCache,
-datapath__305: FPU__GB2,
-case__411: RocketTile__GCB0,
-logic__1179: VCU118RocketSystem__GC0,
-logic__6505: VCU118RocketSystem__GC0,
-case__830: VCU118RocketSystem__GC0,
-logic__8913: APBGpsBlock__GC0,
-CLINTClockSinkDomain: VCU118RocketSystem__GC0,
-case__79: VCU118RocketSystem__GC0,
-reg__268: DCache,
-Queue1_TLBundleA_a29d32s7k1z2u: TLToAPB,
-reg__642: RocketTile__GCB0,
-case__851: VCU118RocketSystem__GC0,
-logic__5192: RocketTile__GCB0,
-case__705: RocketTile__GCB0,
-reg__1106: APBGpsBlock__GC0,
-reg__372: FPU__GB0,
-reg__583: RocketTile__GCB0,
-logic__2576: RocketTile__GCB0,
-logic__6662: VCU118RocketSystem__GC0,
-reg__604: RocketTile__GCB0,
-logic__1490: RocketTile__GCB0,
-datapath__252: DCache,
-datapath__450: RocketTile__GCB0,
-logic__2711: FPU__GB1,
-logic__369: VCU118RocketSystem__GC0,
-case__1375: tracking_wrapper,
-datapath__574: APBGpsBlock__GC0,
-logic__6674: VCU118RocketSystem__GC0,
-logic__5383: RocketTile__GCB0,
-logic__7403: VCU118RocketSystem__GC0,
-reg__977: VCU118RocketSystem__GC0,
-logic__6251: VCU118RocketSystem__GC0,
-logic__5179: RocketTile__GCB0,
-logic__6385: VCU118RocketSystem__GC0,
-logic__3208: FPU__GB2,
-logic__4214: FPU__GB2,
-logic__6763: VCU118RocketSystem__GC0,
-case__1523: APBGpsBlock__GC0,
-logic__3536: FPU__GB1,
-logic__2246: DCache,
-reg__1110: APBGpsBlock__GC0,
-logic__1659: DCache,
-case__89: VCU118RocketSystem__GC0,
-logic__1473: RocketTile__GCB0,
-dsp48e1__28: APBGpsBlock__GC0,
-logic__6410: VCU118RocketSystem__GC0,
-case__158: VCU118RocketSystem__GC0,
-reg__461: FPU__GB1,
-case__1278: APBGpsBlock__GC0,
-reg__1285: tracking_wrapper,
-datapath__277: RocketTile__GCB0,
-logic__6764: VCU118RocketSystem__GC0,
-logic__501: VCU118RocketSystem__GC0,
-case__658: RocketTile__GCB0,
-logic__1247: VCU118RocketSystem__GC0,
-reg__684: RocketTile__GCB0,
-logic__6894: VCU118RocketSystem__GC0,
-logic__6430: VCU118RocketSystem__GC0,
-case__1524: APBGpsBlock__GC0,
-datapath__422: RocketTile__GCB0,
-datapath__378: FPU__GB2,
-logic__4730: RocketTile__GCB0,
-reg__1266: tracking_wrapper,
-case__323: DCache,
-logic__6495: VCU118RocketSystem__GC0,
-reg__221: VCU118RocketSystem__GC0,
-case__222: VCU118RocketSystem__GC0,
-case__865: VCU118RocketSystem__GC0,
-logic__2612: RocketTile__GCB0,
-datapath__681: tracking_wrapper,
-reg__947: VCU118RocketSystem__GC0,
-case__97: VCU118RocketSystem__GC0,
-logic__3493: FPU__GB2,
-logic__435: VCU118RocketSystem__GC0,
-logic__3784: FPU__GB1,
-logic__5282: RocketTile__GCB0,
-case__737: RocketTile__GCB0,
-logic__6793: VCU118RocketSystem__GC0,
-reg__697: RocketTile__GCB0,
-case__401: RocketTile__GCB0,
-case__1402: tracking_wrapper,
-case__1221: APBGpsBlock__GC0,
-logic__8701: tracking_wrapper,
-logic__4726: RocketTile__GCB0,
-RecFNToRecFN: FPU__GB1,
-logic__5998: RocketTile__GCB0,
-case__333: DCache,
-logic__7937: APBGpsBlock__GC0,
-logic__6556: VCU118RocketSystem__GC0,
-datapath__647: tracking_wrapper,
-logic__4530: RocketTile__GCB0,
-logic__3778: FPU__GB1,
-logic__1795: DCache,
-case__1140: APBGpsBlock__GC0,
-logic__3734: FPU__GB1,
-logic__5648: RocketTile__GCB0,
-logic__5303: RocketTile__GCB0,
-logic__2387: RocketTile__GCB0,
-reg__66: VCU118RocketSystem__GC0,
-case__32: VCU118RocketSystem__GC0,
-case__421: RocketTile__GCB0,
-logic__6053: RocketTile__GCB0,
-datapath__156: VCU118RocketSystem__GC0,
-logic__5444: RocketTile__GCB0,
-datapath__384: FPU__GB1,
-datapath__247: DCache,
-reg__46: VCU118RocketSystem__GC0,
-logic__3299: FPU__GB2,
-logic__1954: DCache,
-reg__347: RocketTile__GCB0,
-case__650: RocketTile__GCB0,
-datapath__466: TilePRCIDomain__GC0,
-case__457: FPU__GB2, FPU__GB1,
-datapath__262: RocketTile__GCB0,
-logic__1241: VCU118RocketSystem__GC0,
-case__779: RocketTile__GCB0,
-case__328: DCache,
-muxpart__167: APBGpsBlock__GC0,
-case__369: RocketTile__GCB0,
-logic__7211: VCU118RocketSystem__GC0,
-case__745: RocketTile__GCB0,
-logic__2621: RocketTile__GCB0,
-case__759: RocketTile__GCB0,
-logic__8366: tracking_wrapper,
-logic__8658: tracking_wrapper,
-logic__5401: RocketTile__GCB0,
-logic__815: VCU118RocketSystem__GC0,
-logic__4143: FPU__GB2,
-logic__5886: RocketTile__GCB0,
-logic__1873: RocketTile__GCB0, DCache,
-reg__885: VCU118RocketSystem__GC0,
-logic__6968: VCU118RocketSystem__GC0,
-reg__854: VCU118RocketSystem__GC0,
-datapath__103: VCU118RocketSystem__GC0,
-logic__2190: DCache,
-logic__5001: RocketTile__GCB0,
-case__871: VCU118RocketSystem__GC0,
-datapath__607: APBGpsBlock__GC0,
-case__663: RocketTile__GCB0,
-datapath__662: tracking_wrapper,
-ScratchpadSlavePort: RocketTile__GCB0,
-logic__452: VCU118RocketSystem__GC0,
-reg__491: FPU__GB2,
-logic__4323: FPU__GB2,
-case__504: FPU__GB1,
-reg__276: DCache,
-logic__6599: VCU118RocketSystem__GC0,
-case__305: DCache,
-logic__1871: RocketTile__GCB0, DCache,
-datapath__473: VCU118RocketSystem__GC0,
-logic__8946: TLToAPB,
-reg__1240: tracking_wrapper,
-logic__3796: FPU__GB1,
-case__1090: APBGpsBlock__GC0,
-reg__537: FPU__GB1,
-logic__2908: FPU__GB1,
-datapath__210: VCU118RocketSystem__GC0,
-case__19: genesys2_rocket_top__GC0,
-reg__1041: APBGpsBlock__GC0,
-logic__1503: DCache,
-logic__3928: FPU__GB2, FPU__GB1,
-logic__1388: VCU118RocketSystem__GC0,
-logic__3155: FPU__GB2,
-reg__797: VCU118RocketSystem__GC0,
-logic__5138: RocketTile__GCB0,
-reg__848: VCU118RocketSystem__GC0,
-case__820: VCU118RocketSystem__GC0,
-logic__3236: FPU__GB2,
-case__169: VCU118RocketSystem__GC0,
-reg__1350: genesys2_rocket_top__GC0,
-logic__5866: RocketTile__GCB0,
-case__376: RocketTile__GCB0,
-reg__264: DCache,
-logic__2950: FPU__GB2, FPU__GB1,
-logic__8932: TLToAPB,
-logic__6941: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a17d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__7348: VCU118RocketSystem__GC0,
-datapath__311: FPU__GB2,
-logic__5339: RocketTile__GCB0,
-case__604: FPU__GB1,
-logic__1667: DCache,
-case__967: VCU118RocketSystem__GC0,
-logic__929: VCU118RocketSystem__GC0,
-logic__2152: DCache,
-logic__6081: TilePRCIDomain__GC0,
-logic__7552: VCU118RocketSystem__GC0,
-reg__137: VCU118RocketSystem__GC0,
-case__1361: tracking_wrapper,
-logic__2128: DCache,
-datapath__122: VCU118RocketSystem__GC0,
-reg__316: RocketTile__GCB0,
-bit_gen: tracking_wrapper,
-logic__1953: DCache,
-reg__1160: tracking_wrapper,
-logic__3535: FPU__GB1,
-logic__4604: RocketTile__GCB0,
-extladd__1: tracking_wrapper,
-datapath__1: genesys2_rocket_top__GC0,
-case__944: VCU118RocketSystem__GC0,
-case__139: VCU118RocketSystem__GC0,
-case__600: FPU__GB1,
-logic__2874: FPU__GB1,
-logic__8367: tracking_wrapper,
-reg__1259: tracking_wrapper,
-logic__1447: RocketTile__GCB0,
-dsp48e1__6: APBGpsBlock__GC0,
-logic__6711: VCU118RocketSystem__GC0,
-logic__5810: RocketTile__GCB0,
-reg__648: RocketTile__GCB0,
-logic__3131: FPU__GB2,
-logic__7000: VCU118RocketSystem__GC0,
-logic__1384: VCU118RocketSystem__GC0,
-logic__2063: DCache,
-logic__6728: VCU118RocketSystem__GC0,
-logic__3791: FPU__GB1,
-logic__70: genesys2_rocket_top__GC0,
-datapath__477: VCU118RocketSystem__GC0,
-logic__2911: FPU__GB1,
-case__543: FPU__GB2,
-reg__1257: tracking_wrapper,
-logic__1417: RocketTile__GCB0,
-dsp48e1__1: FPU__GB1,
-logic__6351: VCU118RocketSystem__GC0,
-case__845: VCU118RocketSystem__GC0,
-logic__6285: VCU118RocketSystem__GC0,
-case__115: VCU118RocketSystem__GC0,
-logic__5385: RocketTile__GCB0,
-datapath__206: VCU118RocketSystem__GC0,
-logic__2826: FPU__GB1,
-logic__8699: tracking_wrapper,
-logic__6644: VCU118RocketSystem__GC0,
-logic__682: VCU118RocketSystem__GC0,
-datapath__281: RocketTile__GCB0,
-logic__8470: tracking_wrapper,
-logic__5110: RocketTile__GCB0,
-muxpart__74: FPU__GB0,
-reg__571: FPU__GB1,
-genesys2_rocket_top__GC0: genesys2_rocket_top__GC0,
-logic__7460: VCU118RocketSystem__GC0,
-logic__4322: FPU__GB2,
-reg__281: DCache,
-case__524: FPU__GB2, FPU__GB1,
-logic__8594: tracking_wrapper,
-logic__839: VCU118RocketSystem__GC0,
-case__902: VCU118RocketSystem__GC0,
-case__897: VCU118RocketSystem__GC0,
-logic__1868: RocketTile__GCB0, DCache,
-case__1373: tracking_wrapper,
-dsp48e1__39: tracking_wrapper,
-logic__6696: VCU118RocketSystem__GC0,
-logic__1041: VCU118RocketSystem__GC0,
-logic__749: VCU118RocketSystem__GC0,
-logic__2324: RocketTile__GCB0,
-case__1171: APBGpsBlock__GC0,
-logic__7778: APBGpsBlock__GC0,
-logic__1152: VCU118RocketSystem__GC0,
-case__1194: APBGpsBlock__GC0,
-logic__3832: FPU__GB1,
-logic__7150: VCU118RocketSystem__GC0,
-logic__672: VCU118RocketSystem__GC0,
-case__840: VCU118RocketSystem__GC0,
-logic__6532: VCU118RocketSystem__GC0,
-logic__6302: VCU118RocketSystem__GC0,
-logic__6199: VCU118RocketSystem__GC0,
-reg__16: genesys2_rocket_top__GC0,
-datapath__55: VCU118RocketSystem__GC0,
-reg__390: FPU__GB0,
-reg__634: RocketTile__GCB0,
-DMIToTL: VCU118RocketSystem__GC0,
-logic__6642: VCU118RocketSystem__GC0,
-logic__8133: APBGpsBlock__GC0,
-logic__4762: RocketTile__GCB0,
-reg__409: FPU__GB1,
-logic__1413: RocketTile__GCB0,
-logic__1161: VCU118RocketSystem__GC0,
-logic__445: VCU118RocketSystem__GC0,
-logic__8499: tracking_wrapper,
-logic__4004: FPU__GB2,
-logic__8015: APBGpsBlock__GC0,
-logic__4523: RocketTile__GCB0,
-logic__5673: RocketTile__GCB0,
-logic__2253: DCache,
-reg__1222: tracking_wrapper,
-reg__125: VCU118RocketSystem__GC0,
-logic__3991: FPU__GB1,
-datapath__513: VCU118RocketSystem__GC0,
-case__1157: APBGpsBlock__GC0,
-reg__1088: APBGpsBlock__GC0,
-case__1082: APBGpsBlock__GC0,
-datapath__364: FPU__GB2,
-logic__5997: RocketTile__GCB0,
-reg__821: VCU118RocketSystem__GC0,
-logic__8308: tracking_wrapper,
-datapath__628: tracking_wrapper,
-logic__4301: FPU__GB1,
-reg__1216: tracking_wrapper,
-logic__4014: FPU__GB2,
-datapath__571: APBGpsBlock__GC0,
-reg__350: RocketTile__GCB0,
-reg__934: VCU118RocketSystem__GC0,
-logic__5872: RocketTile__GCB0,
-logic__7571: VCU118RocketSystem__GC0,
-Queue1_TLBundleA_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-reg__133: VCU118RocketSystem__GC0,
-logic__7869: APBGpsBlock__GC0,
-logic__8274: tracking_wrapper,
-case__596: FPU__GB1,
-reg__102: VCU118RocketSystem__GC0,
-logic__3795: FPU__GB1,
-case__486: FPU__GB2,
-muxpart__7: VCU118RocketSystem__GC0,
-TLAtomicAutomata_pbus: VCU118RocketSystem__GC0,
-TLPLIC: VCU118RocketSystem__GC0,
-logic__4252: FPU__GB2,
-logic__6099: VCU118RocketSystem__GC0,
-logic__2481: RocketTile__GCB0,
-logic__3714: FPU__GB1,
-datapath__205: VCU118RocketSystem__GC0,
-case__232: VCU118RocketSystem__GC0,
-datapath__481: VCU118RocketSystem__GC0,
-logic__2646: RocketTile__GCB0,
-reg__111: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2998: FPU__GB2, FPU__GB1,
-case__397: RocketTile__GCB0,
-datapath__532: APBGpsBlock__GC0,
-logic__131: VCU118RocketSystem__GC0,
-reg__59: VCU118RocketSystem__GC0,
-logic__7201: VCU118RocketSystem__GC0,
-logic__6950: VCU118RocketSystem__GC0,
-logic__5059: RocketTile__GCB0,
-case__653: RocketTile__GCB0,
-FPToFP: FPU__GB1,
-logic__3766: FPU__GB1,
-logic__4471: FPU__GB1,
-logic__2586: RocketTile__GCB0,
-reg__313: RocketTile__GCB0,
-logic__2983: FPU__GB2, FPU__GB1,
-case__71: VCU118RocketSystem__GC0,
-logic__1679: DCache,
-signinv__2: APBGpsBlock__GC0,
-logic__6100: VCU118RocketSystem__GC0,
-reg__109: VCU118RocketSystem__GC0,
-reg__614: RocketTile__GCB0,
-logic__4233: FPU__GB2,
-logic__6778: VCU118RocketSystem__GC0,
-logic__2665: RocketTile__GCB0,
-reg__589: RocketTile__GCB0,
-logic__5344: RocketTile__GCB0,
-case__603: FPU__GB1,
-logic__6475: VCU118RocketSystem__GC0,
-logic__6423: VCU118RocketSystem__GC0,
-datapath__482: VCU118RocketSystem__GC0,
-reg__127: VCU118RocketSystem__GC0,
-logic__596: VCU118RocketSystem__GC0,
-logic__3716: FPU__GB1,
-muxpart__231: tracking_wrapper,
-logic__5250: RocketTile__GCB0,
-logic__484: VCU118RocketSystem__GC0,
-case__87: VCU118RocketSystem__GC0,
-logic__2098: DCache,
-logic__692: VCU118RocketSystem__GC0,
-case__316: DCache,
-plusarg_reader: RocketTile__GCB0,
-logic__6742: VCU118RocketSystem__GC0,
-case__75: VCU118RocketSystem__GC0,
-FPUFMAPipe_l4_f64: FPU__GB1,
-case__797: VCU118RocketSystem__GC0,
-logic__17: genesys2_rocket_top__GC0,
-logic__3283: FPU__GB2,
-logic__5336: RocketTile__GCB0,
-muxpart__149: APBGpsBlock__GC0,
-reg__512: FPU__GB2,
-reg__966: VCU118RocketSystem__GC0,
-logic__7369: VCU118RocketSystem__GC0,
-cos2x: tracking_wrapper,
-logic__7933: APBGpsBlock__GC0,
-reg__170: VCU118RocketSystem__GC0,
-logic__7018: VCU118RocketSystem__GC0,
-rf_31x64: RocketTile__GCB0,
-logic__4681: RocketTile__GCB0,
-datapath__398: RocketTile__GCB0,
-logic__2442: RocketTile__GCB0,
-logic__8710: tracking_wrapper,
-case__1213: APBGpsBlock__GC0,
-logic__6210: VCU118RocketSystem__GC0,
-case__679: RocketTile__GCB0,
-case__689: RocketTile__GCB0,
-reg__1178: tracking_wrapper,
-case__916: VCU118RocketSystem__GC0,
-logic__2149: DCache,
-logic__6799: VCU118RocketSystem__GC0,
-reg__490: FPU__GB1,
-case__552: FPU__GB2,
-logic__65: genesys2_rocket_top__GC0,
-case__901: VCU118RocketSystem__GC0,
-case__710: RocketTile__GCB0,
-logic__1319: VCU118RocketSystem__GC0,
-case__1135: APBGpsBlock__GC0,
-datapath__668: tracking_wrapper,
-reg__852: VCU118RocketSystem__GC0,
-case__266: VCU118RocketSystem__GC0,
-logic__2587: RocketTile__GCB0,
-reg__1169: tracking_wrapper,
-logic__7679: APBGpsBlock__GC0,
-logic__3278: FPU__GB2,
-case__1013: VCU118RocketSystem__GC0,
-case__291: RocketTile__GCB0,
-reg__431: FPU__GB2,
-case__1296: APBGpsBlock__GC0,
-case__127: VCU118RocketSystem__GC0,
-logic__2262: DCache,
-case__948: VCU118RocketSystem__GC0,
-reg__1102: APBGpsBlock__GC0,
-reg__631: RocketTile__GCB0,
-case__506: FPU__GB1,
-logic__3762: FPU__GB1,
-case__1231: APBGpsBlock__GC0,
-logic__8681: tracking_wrapper,
-logic__1640: DCache,
-reg__231: DCache,
-logic__5639: RocketTile__GCB0,
-logic__6581: VCU118RocketSystem__GC0,
-reg__163: VCU118RocketSystem__GC0,
-logic__3833: FPU__GB1,
-logic__6472: VCU118RocketSystem__GC0,
-logic__4711: RocketTile__GCB0,
-case__404: RocketTile__GCB0,
-logic__8563: tracking_wrapper,
-logic__2860: FPU__GB1,
-logic__1398: VCU118RocketSystem__GC0,
-case__1506: tracking_wrapper,
-datapath__544: APBGpsBlock__GC0,
-case__538: FPU__GB2,
-reg__766: RocketTile__GCB0,
-logic__628: VCU118RocketSystem__GC0,
-reg__645: RocketTile__GCB0,
-case__754: RocketTile__GCB0,
-logic__7384: VCU118RocketSystem__GC0,
-CompareRecFN: FPU__GB2,
-Arbiter8_DCacheMetadataReq: DCache,
-logic__8215: APBGpsBlock__GC0,
-logic__4218: FPU__GB2,
-reg__928: VCU118RocketSystem__GC0,
-logic__8957: TLToAPB,
-case__1520: APBGpsBlock__GC0,
-logic__3060: FPU__GB2,
-logic__3729: FPU__GB1,
-logic__3005: FPU__GB2, FPU__GB1,
-datapath__61: VCU118RocketSystem__GC0,
-reg__1253: tracking_wrapper,
-logic__3852: FPU__GB1,
-reg__1068: APBGpsBlock__GC0,
-case__381: RocketTile__GCB0,
-datapath__153: VCU118RocketSystem__GC0,
-logic__2410: RocketTile__GCB0,
-muxpart__14: DCache,
-logic__5402: RocketTile__GCB0,
-logic__1454: RocketTile__GCB0,
-Queue2_TLBundleD_a29d64s2k1z3u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6236: VCU118RocketSystem__GC0,
-datapath__105: VCU118RocketSystem__GC0,
-datapath__632: tracking_wrapper,
-reg__1093: APBGpsBlock__GC0,
-case__180: VCU118RocketSystem__GC0,
-logic__473: VCU118RocketSystem__GC0,
-logic__8433: tracking_wrapper,
-logic__5509: RocketTile__GCB0,
-case__575: FPU__GB1,
-reg__971: VCU118RocketSystem__GC0,
-logic__6149: VCU118RocketSystem__GC0,
-case__208: VCU118RocketSystem__GC0,
-logic__4348: FPU__GB1,
-datapath__563: APBGpsBlock__GC0,
-logic__6527: VCU118RocketSystem__GC0,
-reg__538: FPU__GB1,
-logic__3831: FPU__GB1,
-logic__6033: RocketTile__GCB0,
-reg__135: VCU118RocketSystem__GC0,
-logic__4710: RocketTile__GCB0,
-reg__255: DCache,
-reg__328: RocketTile__GCB0,
-case__523: FPU__GB2, FPU__GB1,
-logic__5876: RocketTile__GCB0,
-reg__1056: APBGpsBlock__GC0,
-case__162: VCU118RocketSystem__GC0,
-logic__768: VCU118RocketSystem__GC0,
-muxpart__95: RocketTile__GCB0,
-logic__5984: RocketTile__GCB0,
-logic__3788: FPU__GB1,
-logic__2225: DCache,
-datapath__329: FPU__GB2,
-logic__6770: VCU118RocketSystem__GC0,
-logic__4605: RocketTile__GCB0,
-dual_port_bram__parameterized0: APBGpsBlock__GC0,
-case__1022: VCU118RocketSystem__GC0,
-logic__240: VCU118RocketSystem__GC0,
-logic__5945: RocketTile__GCB0,
-logic__2486: RocketTile__GCB0,
-datapath__286: FPU__GB1,
-logic__2249: DCache,
-logic__1705: DCache,
-logic__4267: FPU__GB2,
-case__102: VCU118RocketSystem__GC0,
-logic__5996: RocketTile__GCB0,
-case__769: RocketTile__GCB0,
-logic__772: VCU118RocketSystem__GC0,
-reg__241: DCache,
-reg__331: RocketTile__GCB0,
-datapath__551: APBGpsBlock__GC0,
-case__331: DCache,
-logic__7229: VCU118RocketSystem__GC0,
-case__846: VCU118RocketSystem__GC0,
-ClockGroupAggregator_sbus: VCU118RocketSystem__GC0,
-logic__7331: VCU118RocketSystem__GC0,
-logic__1246: VCU118RocketSystem__GC0,
-logic__4791: RocketTile__GCB0,
-logic__2250: DCache,
-reg__438: FPU__GB2,
-case__740: RocketTile__GCB0,
-reg__96: VCU118RocketSystem__GC0,
-logic__4142: FPU__GB2,
-logic__1615: DCache,
-reg__786: VCU118RocketSystem__GC0,
-ram_2x123: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2383: RocketTile__GCB0,
-logic__3685: FPU__GB1,
-logic__7845: APBGpsBlock__GC0,
-case__775: RocketTile__GCB0,
-case__974: VCU118RocketSystem__GC0,
-logic__1511: DCache,
-logic__3614: FPU__GB1,
-datapath__134: VCU118RocketSystem__GC0,
-logic__1202: VCU118RocketSystem__GC0,
-logic__8933: TLToAPB,
-case__560: FPU__GB2,
-datapath__118: VCU118RocketSystem__GC0,
-logic__5526: RocketTile__GCB0,
-logic__5944: RocketTile__GCB0,
-logic__3617: FPU__GB1,
-logic__2872: FPU__GB1,
-logic__7578: VCU118RocketSystem__GC0,
-logic__6312: VCU118RocketSystem__GC0,
-logic__3712: FPU__GB1,
-FPGASPIClockSinkDomain: VCU118RocketSystem__GC0,
-counter__23: tracking_wrapper,
-logic__812: VCU118RocketSystem__GC0,
-case__994: VCU118RocketSystem__GC0,
-case__86: VCU118RocketSystem__GC0,
-rockettile_icache_data_arrays_512x32: RocketTile__GCB0,
-logic__5461: RocketTile__GCB0,
-logic__1523: DCache,
-logic__6997: VCU118RocketSystem__GC0,
-logic__6715: VCU118RocketSystem__GC0,
-reg__763: RocketTile__GCB0,
-logic__3395: FPU__GB2,
-datapath__219: VCU118RocketSystem__GC0,
-case__206: VCU118RocketSystem__GC0,
-datapath__687: tracking_wrapper,
-logic__5631: RocketTile__GCB0,
-logic__4110: FPU__GB2,
-reg__487: FPU__GB1,
-case__833: VCU118RocketSystem__GC0,
-logic__8137: APBGpsBlock__GC0,
-logic__4551: RocketTile__GCB0,
-logic__3945: FPU__GB2, FPU__GB1,
-logic__8259: tracking_wrapper,
-logic__4268: FPU__GB2,
-TLError: VCU118RocketSystem__GC0,
-logic__7790: APBGpsBlock__GC0,
-datapath__174: VCU118RocketSystem__GC0,
-logic__6695: VCU118RocketSystem__GC0,
-case__245: VCU118RocketSystem__GC0,
-logic__3540: FPU__GB1,
-reg__67: VCU118RocketSystem__GC0,
-case__569: FPU__GB1,
-muxpart__105: RocketTile__GCB0,
-logic__7303: VCU118RocketSystem__GC0,
-datapath__622: tracking_wrapper,
-logic__3730: FPU__GB1,
-PTW: RocketTile__GCB0,
-case__518: FPU__GB2, FPU__GB1,
-logic__4369: FPU__GB1,
-logic__1304: VCU118RocketSystem__GC0,
-logic__6322: VCU118RocketSystem__GC0,
-logic__8598: tracking_wrapper,
-logic__5378: RocketTile__GCB0,
-logic__1455: RocketTile__GCB0,
-reg__518: FPU__GB2,
-logic__5889: RocketTile__GCB0,
-logic__5135: RocketTile__GCB0,
-case__372: RocketTile__GCB0,
-muxpart__109: RocketTile__GCB0,
-reg__240: DCache,
-logic__6748: VCU118RocketSystem__GC0,
-datapath__472: VCU118RocketSystem__GC0,
-reg__1063: APBGpsBlock__GC0,
-reg__422: FPU__GB1,
-logic__5035: RocketTile__GCB0,
-logic__1595: DCache,
-rockettile_icache_tag_array_0_64x21: RocketTile__GCB0,
-reg__545: FPU__GB1,
-logic__4799: RocketTile__GCB0,
-case__859: VCU118RocketSystem__GC0,
-reg__605: RocketTile__GCB0,
-datapath__147: VCU118RocketSystem__GC0,
-logic__2422: RocketTile__GCB0,
-case__732: RocketTile__GCB0,
-case__1080: APBGpsBlock__GC0,
-reg__747: RocketTile__GCB0,
-logic__2689: FPU__GB1,
-case__1277: APBGpsBlock__GC0,
-reg__466: FPU__GB1,
-datapath__310: FPU__GB2,
-logic__232: VCU118RocketSystem__GC0,
-datapath__318: FPU__GB2,
-logic__1279: VCU118RocketSystem__GC0,
-case__803: VCU118RocketSystem__GC0,
-logic__870: VCU118RocketSystem__GC0,
-reg__223: VCU118RocketSystem__GC0,
-logic__447: VCU118RocketSystem__GC0,
-logic__4056: FPU__GB2,
-case__1386: tracking_wrapper,
-datapath__400: RocketTile__GCB0,
-case__860: VCU118RocketSystem__GC0,
-reg__159: VCU118RocketSystem__GC0,
-case__684: RocketTile__GCB0,
-case__741: RocketTile__GCB0,
-logic__1838: RocketTile__GCB0, DCache,
-AsyncQueueSink_TLBundleD_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-datapath__560: APBGpsBlock__GC0,
-logic__7540: VCU118RocketSystem__GC0,
-logic__7402: VCU118RocketSystem__GC0,
-logic__6533: VCU118RocketSystem__GC0,
-reg__126: VCU118RocketSystem__GC0,
-logic__1612: DCache,
-logic__8268: tracking_wrapper,
-case__1501: tracking_wrapper,
-reg__907: VCU118RocketSystem__GC0,
-logic__5859: RocketTile__GCB0,
-logic__6511: VCU118RocketSystem__GC0,
-reg__95: VCU118RocketSystem__GC0,
-logic__4961: RocketTile__GCB0,
-reg__1320: tracking_wrapper,
-logic__785: VCU118RocketSystem__GC0,
-logic__4001: FPU__GB2,
-logic__1026: VCU118RocketSystem__GC0,
-logic__3761: FPU__GB1,
-logic__7763: APBGpsBlock__GC0,
-datapath__456: RocketTile__GCB0,
-case__63: VCU118RocketSystem__GC0,
-logic__6043: RocketTile__GCB0,
-reg__927: VCU118RocketSystem__GC0,
-case__844: VCU118RocketSystem__GC0,
-muxpart__22: FPU__GB0,
-logic__1245: VCU118RocketSystem__GC0,
-logic__8587: tracking_wrapper,
-datapath__377: FPU__GB2,
-logic__4154: FPU__GB2,
-reg__1091: APBGpsBlock__GC0,
-logic__8544: tracking_wrapper,
-logic__8912: APBGpsBlock__GC0,
-logic__7374: VCU118RocketSystem__GC0,
-logic__6146: VCU118RocketSystem__GC0,
-double_ff_syn__parameterized1: tracking_wrapper,
-reg__378: FPU__GB0,
-logic__7235: VCU118RocketSystem__GC0,
-logic__2702: FPU__GB1,
-logic__3459: FPU__GB2,
-case__1185: APBGpsBlock__GC0,
-reg__1146: tracking_wrapper,
-logic__1558: DCache,
-case__296: RocketTile__GCB0,
-case__885: VCU118RocketSystem__GC0,
-logic__3339: FPU__GB2,
-reg__1294: tracking_wrapper,
-logic__2239: DCache,
-case__1190: APBGpsBlock__GC0,
-logic__2585: RocketTile__GCB0,
-logic__7523: VCU118RocketSystem__GC0,
-reg__657: RocketTile__GCB0,
-logic__945: VCU118RocketSystem__GC0,
-reg__1176: tracking_wrapper,
-logic__4074: FPU__GB2,
-logic__3107: FPU__GB2,
-logic__1226: VCU118RocketSystem__GC0,
-datapath__598: APBGpsBlock__GC0,
-keep__3: tracking_wrapper,
-reg__965: VCU118RocketSystem__GC0,
-mult_46_15_61: APBGpsBlock__GC0,
-datapath__439: RocketTile__GCB0,
-logic__2289: DCache,
-logic__3616: FPU__GB1,
-logic__2343: RocketTile__GCB0,
-logic__1555: DCache,
-logic__578: VCU118RocketSystem__GC0,
-case__298: RocketTile__GCB0,
-logic__4734: RocketTile__GCB0,
-logic__6186: VCU118RocketSystem__GC0,
-case__148: VCU118RocketSystem__GC0,
-case__587: FPU__GB1,
-logic__2552: RocketTile__GCB0,
-logic__8768: tracking_wrapper,
-reg__373: FPU__GB0,
-logic__3544: FPU__GB1,
-logic__6771: VCU118RocketSystem__GC0,
-logic__2917: FPU__GB1,
-datapath__390: RocketTile__GCB0,
-datapath__371: FPU__GB2,
-logic__2700: FPU__GB1,
-case__568: FPU__GB1,
-logic__6934: VCU118RocketSystem__GC0,
-logic__7052: VCU118RocketSystem__GC0,
-logic__177: VCU118RocketSystem__GC0,
-reg__303: RocketTile__GCB0,
-logic__6643: VCU118RocketSystem__GC0,
-case__41: VCU118RocketSystem__GC0,
-logic__6232: VCU118RocketSystem__GC0,
-reg__20: VCU118RocketSystem__GC0,
-case__765: RocketTile__GCB0,
-logic__6113: VCU118RocketSystem__GC0,
-logic__3646: FPU__GB1,
-logic__1504: DCache,
-reg__656: RocketTile__GCB0,
-reg__136: VCU118RocketSystem__GC0,
-reg__573: FPU__GB1,
-logic__8684: tracking_wrapper,
-logic__1404: VCU118RocketSystem__GC0,
-case__255: VCU118RocketSystem__GC0,
-reg__729: RocketTile__GCB0,
-reg__1252: tracking_wrapper,
-case__1304: APBGpsBlock__GC0,
-logic__5278: RocketTile__GCB0,
-logic__8241: tracking_wrapper,
-logic__4732: RocketTile__GCB0,
-case__505: FPU__GB1,
-logic__2667: FPU__GB1,
-logic__6699: VCU118RocketSystem__GC0,
-case__22: VCU118RocketSystem__GC0,
-logic__6020: RocketTile__GCB0,
-reg__1140: tracking_wrapper,
-logic__248: VCU118RocketSystem__GC0,
-case__1000: VCU118RocketSystem__GC0,
-muxpart__43: FPU__GB0,
-logic__8765: tracking_wrapper,
-logic__2240: DCache,
-logic__4989: RocketTile__GCB0,
-datapath__608: APBGpsBlock__GC0,
-logic__244: VCU118RocketSystem__GC0,
-addsub__1: tracking_wrapper,
-TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u: RocketTile__GCB0,
-datapath__569: APBGpsBlock__GC0,
-logic__6473: VCU118RocketSystem__GC0,
-case__521: FPU__GB2, FPU__GB1,
-datapath__67: VCU118RocketSystem__GC0,
-reg__732: RocketTile__GCB0,
-datapath__201: VCU118RocketSystem__GC0,
-logic__811: VCU118RocketSystem__GC0,
-datapath__95: VCU118RocketSystem__GC0,
-datapath__654: tracking_wrapper,
-logic__854: VCU118RocketSystem__GC0,
-logic__1874: RocketTile__GCB0, DCache,
-reg__1278: tracking_wrapper,
-logic__8625: tracking_wrapper,
-case__824: VCU118RocketSystem__GC0,
-datapath__76: VCU118RocketSystem__GC0,
-case__1062: APBGpsBlock__GC0,
-muxpart__39: FPU__GB0,
-logic__2320: RocketTile__GCB0,
-logic__6200: VCU118RocketSystem__GC0,
-logic__8175: APBGpsBlock__GC0,
-logic__3751: FPU__GB1,
-reg: genesys2_rocket_top__GC0,
-logic__7330: VCU118RocketSystem__GC0,
-logic__6488: VCU118RocketSystem__GC0,
-logic__3715: FPU__GB1,
-reg__227: RocketTile__GCB0,
-logic__273: VCU118RocketSystem__GC0,
-logic__5262: RocketTile__GCB0,
-reg__842: VCU118RocketSystem__GC0,
-logic__483: VCU118RocketSystem__GC0,
-reg__1315: tracking_wrapper,
-logic__1353: VCU118RocketSystem__GC0,
-ram_2x77: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__104: VCU118RocketSystem__GC0,
-logic__8024: APBGpsBlock__GC0,
-logic__8814: tracking_wrapper,
-reg__777: TilePRCIDomain__GC0,
-logic__2332: RocketTile__GCB0,
-reg__499: FPU__GB2,
-logic__2178: DCache,
-DTLB: DCache,
-datapath__633: tracking_wrapper,
-logic__2684: FPU__GB1,
-case__829: VCU118RocketSystem__GC0,
-datapath__599: APBGpsBlock__GC0,
-logic__5177: RocketTile__GCB0,
-sync: tracking_wrapper,
-case__235: VCU118RocketSystem__GC0,
-datapath__417: RocketTile__GCB0,
-logic__2315: RocketTile__GCB0,
-reg__452: FPU__GB1,
-case__545: FPU__GB2,
-case__823: VCU118RocketSystem__GC0,
-logic__6087: VCU118RocketSystem__GC0,
-logic__8873: APBGpsBlock__GC0,
-case__1036: VCU118RocketSystem__GC0,
-logic__5954: RocketTile__GCB0,
-datapath__517: VCU118RocketSystem__GC0,
-reg__161: VCU118RocketSystem__GC0,
-logic__4657: RocketTile__GCB0,
-logic__4798: RocketTile__GCB0,
-reg__608: RocketTile__GCB0,
-logic__8856: tracking_wrapper,
-logic__3605: FPU__GB1,
-logic__538: VCU118RocketSystem__GC0,
-logic__1540: DCache,
-logic__1614: DCache,
-reg__1224: tracking_wrapper,
-reg__1272: tracking_wrapper,
-BreakpointUnit: RocketTile__GCB0,
-logic__3633: FPU__GB1,
-logic__1089: VCU118RocketSystem__GC0,
-case__532: FPU__GB2,
-logic__1199: VCU118RocketSystem__GC0,
-datapath__444: RocketTile__GCB0,
-logic__2382: RocketTile__GCB0,
-datapath__576: APBGpsBlock__GC0,
-reg__899: VCU118RocketSystem__GC0,
-logic__6507: VCU118RocketSystem__GC0,
-datapath__33: VCU118RocketSystem__GC0,
-logic__5525: RocketTile__GCB0,
-TLXbar_cbus_in_i1_o1_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-case__1170: APBGpsBlock__GC0,
-reg__1100: APBGpsBlock__GC0,
-logic__1461: RocketTile__GCB0,
-DivSqrtRecFN_small_1: FPU__GB2,
-reg__827: VCU118RocketSystem__GC0,
-reg__210: VCU118RocketSystem__GC0,
-reg__45: VCU118RocketSystem__GC0,
-reg__243: DCache,
-logic__6747: VCU118RocketSystem__GC0,
-logic__482: VCU118RocketSystem__GC0,
-case__940: VCU118RocketSystem__GC0,
-datapath__617: APBGpsBlock__GC0,
-logic__7717: APBGpsBlock__GC0,
-case__512: FPU__GB1,
-logic__1283: VCU118RocketSystem__GC0,
-keep__9: genesys2_rocket_top__GC0,
-datapath__454: RocketTile__GCB0,
-reg__1301: tracking_wrapper,
-reg__92: VCU118RocketSystem__GC0,
-case__348: DCache,
-logic__4274: FPU__GB1,
-counter__26: tracking_wrapper,
-logic__361: VCU118RocketSystem__GC0,
-case__21: genesys2_rocket_top__GC0,
-reg__414: FPU__GB1,
-datapath__479: VCU118RocketSystem__GC0,
-case__161: VCU118RocketSystem__GC0,
-logic__6782: VCU118RocketSystem__GC0,
-logic__1481: RocketTile__GCB0,
-logic__1261: VCU118RocketSystem__GC0,
-logic__930: VCU118RocketSystem__GC0,
-logic__8910: APBGpsBlock__GC0,
-case__1060: APBGpsBlock__GC0,
-logic__2846: FPU__GB1,
-logic__2316: RocketTile__GCB0,
-reg__139: VCU118RocketSystem__GC0,
-logic__3335: FPU__GB2,
-reg__297: RocketTile__GCB0,
-reg__958: VCU118RocketSystem__GC0,
-muxpart__51: FPU__GB0,
-logic__6652: VCU118RocketSystem__GC0,
-dual_port_bram: APBGpsBlock__GC0,
-logic__1071: VCU118RocketSystem__GC0,
-reg__892: VCU118RocketSystem__GC0,
-logic__6713: VCU118RocketSystem__GC0,
-reg__782: VCU118RocketSystem__GC0,
-logic__693: VCU118RocketSystem__GC0,
-reg__84: VCU118RocketSystem__GC0,
-dsp48e1: FPU__GB1,
-logic__3629: FPU__GB1,
-logic__2213: DCache,
-logic__8911: APBGpsBlock__GC0,
-datapath__663: tracking_wrapper,
-case__739: RocketTile__GCB0,
-logic__6548: VCU118RocketSystem__GC0,
-logic__3445: FPU__GB2,
-logic__6105: VCU118RocketSystem__GC0,
-logic__3740: FPU__GB1,
-reg__259: DCache,
-binary_to_gray: tracking_wrapper,
-logic__6474: VCU118RocketSystem__GC0,
-logic__196: VCU118RocketSystem__GC0,
-logic__6553: VCU118RocketSystem__GC0,
-logic__8312: tracking_wrapper,
-logic__644: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__713: RocketTile__GCB0,
-reg__405: FPU__GB1,
-logic__5188: RocketTile__GCB0,
-rom__3: APBGpsBlock__GC0,
-case__572: FPU__GB1,
-datapath__217: VCU118RocketSystem__GC0,
-logic__8370: tracking_wrapper,
-logic__7087: VCU118RocketSystem__GC0,
-datapath__41: VCU118RocketSystem__GC0,
-case__1048: VCU118RocketSystem__GC0,
-reg__964: VCU118RocketSystem__GC0,
-datapath__572: APBGpsBlock__GC0,
-logic__4315: FPU__GB1,
-logic__5426: RocketTile__GCB0,
-logic__3064: FPU__GB2,
-datapath__226: VCU118RocketSystem__GC0,
-logic__18: genesys2_rocket_top__GC0,
-logic__7518: VCU118RocketSystem__GC0,
-logic__8738: tracking_wrapper,
-logic__1354: VCU118RocketSystem__GC0,
-logic__7247: VCU118RocketSystem__GC0,
-case__1187: APBGpsBlock__GC0,
-logic__130: VCU118RocketSystem__GC0,
-reg__1292: tracking_wrapper,
-logic__6133: VCU118RocketSystem__GC0,
-reg__1344: TLToAPB,
-datapath__423: RocketTile__GCB0,
-logic__2452: RocketTile__GCB0,
-datapath__381: FPU__GB2,
-case__1287: APBGpsBlock__GC0,
-logic__5052: RocketTile__GCB0,
-logic__950: VCU118RocketSystem__GC0,
-logic__8286: tracking_wrapper,
-case__247: VCU118RocketSystem__GC0,
-logic__1027: VCU118RocketSystem__GC0,
-dsp48e1__32: tracking_wrapper,
-logic__7596: VCU118RocketSystem__GC0,
-logic__7262: VCU118RocketSystem__GC0,
-reg__80: VCU118RocketSystem__GC0,
-case__773: RocketTile__GCB0,
-reg__337: RocketTile__GCB0,
-datapath__395: RocketTile__GCB0,
-reg__1122: APBGpsBlock__GC0,
-divider_fsm: APBGpsBlock__GC0,
-case__1299: APBGpsBlock__GC0,
-case__559: FPU__GB2,
-reg__447: FPU__GB1,
-logic__5223: RocketTile__GCB0,
-logic__611: VCU118RocketSystem__GC0,
-logic__8714: tracking_wrapper,
-logic__5502: RocketTile__GCB0,
-logic__8944: TLToAPB,
-case__862: VCU118RocketSystem__GC0,
-logic__8931: TLToAPB,
-datapath__542: APBGpsBlock__GC0,
-muxpart__216: tracking_wrapper,
-logic__2530: RocketTile__GCB0,
-reg__1258: tracking_wrapper,
-logic__1028: VCU118RocketSystem__GC0,
-logic__6547: VCU118RocketSystem__GC0,
-case__691: RocketTile__GCB0,
-reg__922: VCU118RocketSystem__GC0,
-case__465: FPU__GB2,
-muxpart__67: FPU__GB0,
-addsub__4: tracking_wrapper,
-reg__1042: APBGpsBlock__GC0,
-case__707: RocketTile__GCB0,
-reg__994: VCU118RocketSystem__GC0,
-case__473: FPU__GB2,
-reg__1087: APBGpsBlock__GC0,
-logic__3418: FPU__GB2,
-FPUFMAPipe_l3_f32: FPU__GB1,
-reg__1111: APBGpsBlock__GC0,
-logic__6783: VCU118RocketSystem__GC0,
-reg__148: VCU118RocketSystem__GC0,
-muxpart__62: FPU__GB0,
-case__1529: TLToAPB,
-logic__8767: tracking_wrapper,
-logic__3153: FPU__GB2,
-reg__317: RocketTile__GCB0,
-muxpart__55: FPU__GB0,
-logic__4314: FPU__GB1,
-logic__1375: VCU118RocketSystem__GC0,
-case__1078: APBGpsBlock__GC0,
-case__362: DCache,
-logic__3697: FPU__GB1,
-reg__637: RocketTile__GCB0,
-logic__7217: VCU118RocketSystem__GC0,
-reg__1295: tracking_wrapper,
-logic__6128: VCU118RocketSystem__GC0,
-logic__3514: FPU__GB1,
-logic__7007: VCU118RocketSystem__GC0,
-logic__891: VCU118RocketSystem__GC0,
-datapath__392: RocketTile__GCB0,
-logic__6147: VCU118RocketSystem__GC0,
-logic__7848: APBGpsBlock__GC0,
-case__666: RocketTile__GCB0,
-reg__14: genesys2_rocket_top__GC0,
-logic__7103: VCU118RocketSystem__GC0,
-reg__1194: tracking_wrapper,
-case__542: FPU__GB2,
-logic__7093: VCU118RocketSystem__GC0,
-logic__2204: DCache,
-logic__6544: VCU118RocketSystem__GC0,
-logic__5877: RocketTile__GCB0,
-logic__3765: FPU__GB1,
-signinv__1: VCU118RocketSystem__GC0,
-logic__3156: FPU__GB2,
-logic__2354: RocketTile__GCB0,
-logic__4596: RocketTile__GCB0,
-logic__2464: RocketTile__GCB0,
-logic__4643: RocketTile__GCB0,
-reg__39: VCU118RocketSystem__GC0,
-logic__5386: RocketTile__GCB0,
-logic__2561: RocketTile__GCB0,
-case__295: RocketTile__GCB0,
-case__819: VCU118RocketSystem__GC0,
-logic__3505: FPU__GB1,
-case__950: VCU118RocketSystem__GC0,
-reg__568: FPU__GB1,
-logic__2077: DCache,
-logic__7364: VCU118RocketSystem__GC0,
-logic__2223: DCache,
-logic__3548: FPU__GB1,
-case__1462: tracking_wrapper,
-logic__118: VCU118RocketSystem__GC0,
-reg__654: RocketTile__GCB0,
-logic__928: VCU118RocketSystem__GC0,
-logic__6468: VCU118RocketSystem__GC0,
-datapath__63: VCU118RocketSystem__GC0,
-logic__5803: RocketTile__GCB0,
-logic__795: VCU118RocketSystem__GC0,
-reg__745: RocketTile__GCB0,
-logic__6723: VCU118RocketSystem__GC0,
-case__1424: tracking_wrapper,
-logic__5209: RocketTile__GCB0,
-logic__612: VCU118RocketSystem__GC0,
-case__85: VCU118RocketSystem__GC0,
-logic__7551: VCU118RocketSystem__GC0,
-logic__5202: RocketTile__GCB0,
-logic__5495: RocketTile__GCB0,
-case__1165: APBGpsBlock__GC0,
-reg__98: VCU118RocketSystem__GC0,
-logic__2027: DCache,
-logic__1570: DCache,
-muxpart__13: DCache,
-logic__5331: RocketTile__GCB0,
-case__970: VCU118RocketSystem__GC0,
-case__228: VCU118RocketSystem__GC0,
-case__205: VCU118RocketSystem__GC0,
-logic__386: VCU118RocketSystem__GC0,
-logic__6021: RocketTile__GCB0,
-logic__6427: VCU118RocketSystem__GC0,
-logic__5423: RocketTile__GCB0,
-logic__8243: tracking_wrapper,
-reg__671: RocketTile__GCB0,
-case__866: VCU118RocketSystem__GC0,
-Queue2_TLBundleA_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__2224: DCache,
-datapath__267: RocketTile__GCB0,
-case__698: RocketTile__GCB0,
-dsp48e1__17: APBGpsBlock__GC0,
-case__571: FPU__GB1,
-logic__4610: RocketTile__GCB0,
-case__883: VCU118RocketSystem__GC0,
-datapath__64: VCU118RocketSystem__GC0,
-case__437: RocketTile__GCB0,
-datapath__351: FPU__GB1,
-logic__370: VCU118RocketSystem__GC0,
-logic__2879: FPU__GB1,
-logic__1332: VCU118RocketSystem__GC0,
-reg__160: VCU118RocketSystem__GC0,
-logic__7241: VCU118RocketSystem__GC0,
-logic__1548: DCache,
-logic__1609: DCache,
-datapath__157: VCU118RocketSystem__GC0,
-logic__8481: tracking_wrapper,
-case__836: VCU118RocketSystem__GC0,
-case__813: VCU118RocketSystem__GC0,
-case__1018: VCU118RocketSystem__GC0,
-logic__4619: RocketTile__GCB0,
-logic__8323: tracking_wrapper,
-addsub: APBGpsBlock__GC0,
-reg__154: VCU118RocketSystem__GC0,
-datapath__50: VCU118RocketSystem__GC0,
-muxpart__75: FPU__GB0,
-dsp48e1__31: tracking_wrapper,
-reg__308: RocketTile__GCB0,
-logic__7127: VCU118RocketSystem__GC0,
-logic__6873: VCU118RocketSystem__GC0,
-logic__2809: FPU__GB1,
-reg__355: RocketTile__GCB0,
-case__324: DCache,
-reg__1116: APBGpsBlock__GC0,
-logic__6233: VCU118RocketSystem__GC0,
-reg__919: VCU118RocketSystem__GC0,
-logic__2447: RocketTile__GCB0,
-logic__4833: RocketTile__GCB0,
-logic__883: VCU118RocketSystem__GC0,
-logic__8926: TLToAPB,
-case__1420: tracking_wrapper,
-datapath__578: APBGpsBlock__GC0,
-logic__4881: RocketTile__GCB0,
-datapath__237: RocketTile__GCB0,
-reg__266: DCache,
-datapath__469: VCU118RocketSystem__GC0,
-logic__478: VCU118RocketSystem__GC0,
-logic__962: VCU118RocketSystem__GC0,
-reg__468: FPU__GB1,
-case__195: VCU118RocketSystem__GC0,
-logic__8140: APBGpsBlock__GC0,
-case__395: RocketTile__GCB0,
-datapath__658: tracking_wrapper,
-logic__6703: VCU118RocketSystem__GC0,
-muxpart__104: RocketTile__GCB0,
-case__703: RocketTile__GCB0,
-reg__594: RocketTile__GCB0,
-logic__7368: VCU118RocketSystem__GC0,
-accum_dump: tracking_wrapper,
-logic__3820: FPU__GB1,
-extladd: RocketTile__GCB0,
-logic__1282: VCU118RocketSystem__GC0,
-logic__182: VCU118RocketSystem__GC0,
-logic__8685: tracking_wrapper,
-datapath__261: DCache,
-logic__7559: VCU118RocketSystem__GC0,
-logic__6905: VCU118RocketSystem__GC0,
-datapath__203: VCU118RocketSystem__GC0,
-datapath__387: FPU__GB1,
-case__1505: tracking_wrapper,
-case__771: RocketTile__GCB0,
-logic__1894: DCache,
-muxpart__23: FPU__GB0,
-case__194: VCU118RocketSystem__GC0,
-reg__1343: TLToAPB,
-reg__909: VCU118RocketSystem__GC0,
-logic__5523: RocketTile__GCB0,
-logic__7064: VCU118RocketSystem__GC0,
-logic__6378: VCU118RocketSystem__GC0,
-logic__2016: DCache,
-logic__1213: VCU118RocketSystem__GC0,
-case__215: VCU118RocketSystem__GC0,
-logic__3754: FPU__GB1,
-logic__5281: RocketTile__GCB0,
-logic__3126: FPU__GB2,
-datapath__290: FPU__GB1,
-logic__4467: FPU__GB1,
-logic__2696: FPU__GB1,
-logic__6645: VCU118RocketSystem__GC0,
-logic__2430: RocketTile__GCB0,
-logic__6110: VCU118RocketSystem__GC0,
-datapath__74: VCU118RocketSystem__GC0,
-reg__1155: tracking_wrapper,
-logic__4980: RocketTile__GCB0,
-logic__1632: DCache,
-Repeater_TLBundleA_a32d64s2k1z3u: RocketTile__GCB0,
-logic__8752: tracking_wrapper,
-logic__4294: FPU__GB2,
-case__25: VCU118RocketSystem__GC0,
-logic__4713: RocketTile__GCB0,
-logic__6431: VCU118RocketSystem__GC0,
-logic__4550: RocketTile__GCB0,
-muxpart__58: FPU__GB0,
-case__553: FPU__GB2,
-datapath__380: FPU__GB2,
-logic__8325: tracking_wrapper,
-logic__7693: APBGpsBlock__GC0,
-reg__502: FPU__GB2,
-logic__6358: VCU118RocketSystem__GC0,
-logic__5993: RocketTile__GCB0,
-logic__124: VCU118RocketSystem__GC0,
-logic__4826: RocketTile__GCB0,
-reg__653: RocketTile__GCB0,
-logic__933: VCU118RocketSystem__GC0,
-case__747: RocketTile__GCB0,
-logic__4554: RocketTile__GCB0,
-case__1338: tracking_wrapper,
-datapath__609: APBGpsBlock__GC0,
-logic__1847: RocketTile__GCB0, DCache,
-case__346: DCache,
-logic__6549: VCU118RocketSystem__GC0,
-logic__365: VCU118RocketSystem__GC0,
-logic__1938: DCache,
-logic__8277: tracking_wrapper,
-logic__3811: FPU__GB1,
-case__356: DCache,
-case__234: VCU118RocketSystem__GC0,
-logic__2511: RocketTile__GCB0,
-reg__225: VCU118RocketSystem__GC0,
-logic__4459: FPU__GB1,
-logic__8355: tracking_wrapper,
-datapath__491: VCU118RocketSystem__GC0,
-datapath__470: VCU118RocketSystem__GC0,
-logic__6603: VCU118RocketSystem__GC0,
-case__887: VCU118RocketSystem__GC0,
-reg__650: RocketTile__GCB0,
-case__500: FPU__GB1,
-butterfly: APBGpsBlock__GC0,
-logic__6956: VCU118RocketSystem__GC0,
-logic__6774: VCU118RocketSystem__GC0,
-case__265: VCU118RocketSystem__GC0,
-logic__2163: DCache,
-acq_top: APBGpsBlock__GC0,
-logic__1647: DCache,
-logic__2699: FPU__GB1,
-reg__1242: tracking_wrapper,
-logic__2937: FPU__GB1,
-case__1502: tracking_wrapper,
-logic__353: VCU118RocketSystem__GC0,
-logic__2032: DCache,
-logic__8884: APBGpsBlock__GC0,
-reg__591: RocketTile__GCB0,
-case__1423: tracking_wrapper,
-case__1019: VCU118RocketSystem__GC0,
-logic__394: VCU118RocketSystem__GC0,
-reg__734: RocketTile__GCB0,
-logic__8397: tracking_wrapper,
-reg__611: RocketTile__GCB0,
-logic__6215: VCU118RocketSystem__GC0,
-case__767: RocketTile__GCB0,
-logic__6016: RocketTile__GCB0,
-logic__748: VCU118RocketSystem__GC0,
-TLWidthWidget8_3: VCU118RocketSystem__GC0,
-reg__916: VCU118RocketSystem__GC0,
-logic__808: VCU118RocketSystem__GC0,
-datapath__666: tracking_wrapper,
-logic__1832: RocketTile__GCB0, DCache,
-ErrorDeviceWrapper: VCU118RocketSystem__GC0,
-case__1101: APBGpsBlock__GC0,
-logic__3611: FPU__GB1,
-datapath__363: FPU__GB2,
-logic__7636: VCU118RocketSystem__GC0,
-logic__8374: tracking_wrapper,
-logic__4477: FPU__GB1,
-logic__2672: FPU__GB1,
-muxpart__91: FPU__GB1,
-case__959: VCU118RocketSystem__GC0,
-logic__6336: VCU118RocketSystem__GC0,
-logic__2892: FPU__GB1,
-reg__688: RocketTile__GCB0,
-logic__282: VCU118RocketSystem__GC0,
-logic__5247: RocketTile__GCB0,
-case__292: RocketTile__GCB0,
-reg__5: genesys2_rocket_top__GC0,
-logic__338: VCU118RocketSystem__GC0,
-reg__11: genesys2_rocket_top__GC0,
-logic__6940: VCU118RocketSystem__GC0,
-datapath__396: RocketTile__GCB0,
-reg__588: RocketTile__GCB0,
-datapath__57: VCU118RocketSystem__GC0,
-case__1189: APBGpsBlock__GC0,
-logic__5310: RocketTile__GCB0,
-logic__925: VCU118RocketSystem__GC0,
-DCache: DCache,
-case__1097: APBGpsBlock__GC0,
-logic__7966: APBGpsBlock__GC0,
-logic__1445: RocketTile__GCB0,
-datapath__413: RocketTile__GCB0,
-logic__7527: VCU118RocketSystem__GC0,
-case__110: VCU118RocketSystem__GC0,
-case__423: RocketTile__GCB0,
-logic__2668: FPU__GB1,
-AsyncQueueSource_TLBundleD_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__6017: RocketTile__GCB0,
-reg__128: VCU118RocketSystem__GC0,
-logic__3992: FPU__GB1,
-logic__4786: RocketTile__GCB0,
-logic__8955: TLToAPB,
-case__51: VCU118RocketSystem__GC0,
-reg__1331: tracking_wrapper,
-reg__1112: APBGpsBlock__GC0,
-logic__1284: VCU118RocketSystem__GC0,
-case__908: VCU118RocketSystem__GC0,
-logic__5893: RocketTile__GCB0,
-case__849: VCU118RocketSystem__GC0,
-reg__1328: tracking_wrapper,
-logic__2164: DCache,
-logic__2518: RocketTile__GCB0,
-logic__5025: RocketTile__GCB0,
-logic__5436: RocketTile__GCB0,
-logic__1569: DCache,
-logic__5379: RocketTile__GCB0,
-ClockCrossingReg_w15: VCU118RocketSystem__GC0,
-reg__678: RocketTile__GCB0,
-logic__5888: RocketTile__GCB0,
-logic__4035: FPU__GB2,
-datapath__659: tracking_wrapper,
-case__1186: APBGpsBlock__GC0,
-reg__116: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2023: DCache,
-case__170: VCU118RocketSystem__GC0,
-logic__5629: RocketTile__GCB0,
-logic__2527: RocketTile__GCB0,
-case__264: VCU118RocketSystem__GC0,
-logic__6546: VCU118RocketSystem__GC0,
-case__678: RocketTile__GCB0,
-case__1334: tracking_wrapper,
-logic__269: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7426: VCU118RocketSystem__GC0,
-logic__3713: FPU__GB1,
-logic__7625: VCU118RocketSystem__GC0,
-logic__8184: APBGpsBlock__GC0,
-logic__6522: VCU118RocketSystem__GC0,
-case__694: RocketTile__GCB0,
-reg__88: VCU118RocketSystem__GC0,
-logic__6270: VCU118RocketSystem__GC0,
-logic__6768: VCU118RocketSystem__GC0,
-reg__996: APBGpsBlock__GC0, tracking_wrapper,
-case__906: VCU118RocketSystem__GC0,
-reg__370: FPU__GB0,
-dsp48e1__42: tracking_wrapper,
-cdc_fifo_gray_src: tracking_wrapper,
-case__976: VCU118RocketSystem__GC0,
-reg__26: VCU118RocketSystem__GC0,
-logic__4412: FPU__GB1,
-logic__1577: DCache,
-case__8: genesys2_rocket_top__GC0,
-datapath__285: RocketTile__GCB0,
-case__308: DCache,
-reg__1000: APBGpsBlock__GC0,
-datapath__525: APBGpsBlock__GC0,
-logic__6112: VCU118RocketSystem__GC0,
-reg__177: VCU118RocketSystem__GC0,
-logic__4834: RocketTile__GCB0,
-case__776: RocketTile__GCB0,
-case__407: RocketTile__GCB0,
-logic__6929: VCU118RocketSystem__GC0,
-logic__7378: VCU118RocketSystem__GC0,
-reg__505: FPU__GB2,
-case__1378: tracking_wrapper,
-logic__2706: FPU__GB1,
-reg__77: VCU118RocketSystem__GC0,
-reg__101: VCU118RocketSystem__GC0,
-logic__2293: DCache,
-case__815: VCU118RocketSystem__GC0,
-reg__593: RocketTile__GCB0,
-datapath__65: VCU118RocketSystem__GC0,
-reg__228: RocketTile__GCB0,
-case__900: VCU118RocketSystem__GC0,
-FixedClockBroadcast_1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__427: RocketTile__GCB0,
-logic__6604: VCU118RocketSystem__GC0,
-reg__672: RocketTile__GCB0,
-logic__532: VCU118RocketSystem__GC0,
-case__118: VCU118RocketSystem__GC0,
-case__856: VCU118RocketSystem__GC0,
-logic__4055: FPU__GB2,
-logic__4644: RocketTile__GCB0,
-logic__8666: tracking_wrapper,
-logic__6554: VCU118RocketSystem__GC0,
-logic__2701: FPU__GB1,
-logic__4229: FPU__GB2,
-logic__4311: FPU__GB1,
-reg__1205: tracking_wrapper,
-case__631: RocketTile__GCB0,
-reg__1190: tracking_wrapper,
-reg__731: RocketTile__GCB0,
-reg__517: FPU__GB2,
-case__1298: APBGpsBlock__GC0,
-datapath__258: DCache,
-logic__4421: FPU__GB1,
-logic__4139: FPU__GB2,
-logic__3402: FPU__GB2,
-logic__8876: APBGpsBlock__GC0,
-reg__449: FPU__GB1,
-logic__453: VCU118RocketSystem__GC0,
-case__638: RocketTile__GCB0,
-case__930: VCU118RocketSystem__GC0,
-logic__3853: FPU__GB1,
-TLBuffer_a32d64s1k1z4u_1: RocketTile__GCB0,
-case__1301: APBGpsBlock__GC0,
-logic__7268: VCU118RocketSystem__GC0,
-muxpart__89: FPU__GB2,
-logic__6813: VCU118RocketSystem__GC0,
-case__1452: tracking_wrapper,
-reg__358: RocketTile__GCB0,
-case__730: RocketTile__GCB0,
-logic__7934: APBGpsBlock__GC0,
-logic__2989: FPU__GB2, FPU__GB1,
-reg__741: RocketTile__GCB0,
-case__221: VCU118RocketSystem__GC0,
-logic__8952: TLToAPB,
-case__1530: TLToAPB,
-RocketTile__GCB0: RocketTile__GCB0,
-reg__216: VCU118RocketSystem__GC0,
-logic__7962: APBGpsBlock__GC0,
-logic__7418: VCU118RocketSystem__GC0,
-reg__1142: tracking_wrapper,
-logic__6670: VCU118RocketSystem__GC0,
-logic__1156: VCU118RocketSystem__GC0,
-case__876: VCU118RocketSystem__GC0,
-logic__4842: RocketTile__GCB0,
-logic__1827: RocketTile__GCB0, DCache,
-logic__6183: VCU118RocketSystem__GC0,
-logic__6032: RocketTile__GCB0,
-logic__710: VCU118RocketSystem__GC0,
-datapath__425: RocketTile__GCB0,
-reg__470: FPU__GB1,
-case__190: VCU118RocketSystem__GC0,
-logic__7160: VCU118RocketSystem__GC0,
-datapath__453: RocketTile__GCB0,
-TLInterconnectCoupler_cbus_to_debug: VCU118RocketSystem__GC0,
-logic__7196: VCU118RocketSystem__GC0,
-logic__448: VCU118RocketSystem__GC0,
-logic__7102: VCU118RocketSystem__GC0,
-logic__4107: FPU__GB2,
-logic__5527: RocketTile__GCB0,
-logic__1460: RocketTile__GCB0,
-case__1418: tracking_wrapper,
-reg__813: VCU118RocketSystem__GC0,
-logic__7195: VCU118RocketSystem__GC0,
-logic__584: VCU118RocketSystem__GC0,
-logic__934: VCU118RocketSystem__GC0,
-logic__8686: tracking_wrapper,
-case__574: FPU__GB1,
-logic__8753: tracking_wrapper,
-logic__4273: FPU__GB2,
-logic__3354: FPU__GB2,
-reg__931: VCU118RocketSystem__GC0,
-logic__1936: DCache,
-logic__606: VCU118RocketSystem__GC0,
-case__441: FPU__GB1,
-logic__1560: DCache,
-datapath__204: VCU118RocketSystem__GC0,
-logic__2703: FPU__GB1,
-reg__1131: tracking_wrapper,
-logic__5204: RocketTile__GCB0,
-logic__8265: tracking_wrapper,
-logic__8769: tracking_wrapper,
-reg__857: VCU118RocketSystem__GC0,
-bram__parameterized0: APBGpsBlock__GC0,
-butterfly__parameterized0: APBGpsBlock__GC0,
-case__615: RocketTile__GCB0,
-logic__4757: RocketTile__GCB0,
-logic__2697: FPU__GB1,
-logic__2818: FPU__GB1,
-logic__6476: VCU118RocketSystem__GC0,
-muxpart__68: FPU__GB0,
-logic__8672: tracking_wrapper,
-logic__7855: APBGpsBlock__GC0,
-reg__699: RocketTile__GCB0,
-extladd__2: tracking_wrapper,
-datapath__604: APBGpsBlock__GC0,
-logic__2677: FPU__GB1,
-case__1049: VCU118RocketSystem__GC0,
-case__785: VCU118RocketSystem__GC0,
-logic__966: VCU118RocketSystem__GC0,
-reg__324: RocketTile__GCB0,
-logic__2850: FPU__GB1,
-logic__4111: FPU__GB2,
-logic__6730: VCU118RocketSystem__GC0,
-datapath__549: APBGpsBlock__GC0,
-datapath__347: FPU__GB1,
-logic__2053: DCache,
-datapath__580: APBGpsBlock__GC0,
-case__341: DCache,
-datapath__53: VCU118RocketSystem__GC0,
-logic__2333: RocketTile__GCB0,
-reg__986: VCU118RocketSystem__GC0,
-reg__1270: tracking_wrapper,
-ClockCrossingReg_w55: VCU118RocketSystem__GC0,
-logic__4888: RocketTile__GCB0,
-logic__2101: DCache,
-reg__467: FPU__GB1,
-datapath__492: VCU118RocketSystem__GC0,
-logic__6355: VCU118RocketSystem__GC0,
-logic__7704: APBGpsBlock__GC0,
-case__998: VCU118RocketSystem__GC0,
-logic__5963: RocketTile__GCB0,
-logic__5994: RocketTile__GCB0,
-logic__6384: VCU118RocketSystem__GC0,
-case__201: VCU118RocketSystem__GC0,
-case__1441: tracking_wrapper,
-logic__6115: VCU118RocketSystem__GC0,
-logic__7923: APBGpsBlock__GC0,
-logic__2220: DCache,
-logic__5335: RocketTile__GCB0,
-case__980: VCU118RocketSystem__GC0,
-case__50: VCU118RocketSystem__GC0,
-datapath__358: FPU__GB2, FPU__GB1,
-logic__1434: RocketTile__GCB0,
-case__196: VCU118RocketSystem__GC0,
-reg__81: VCU118RocketSystem__GC0,
-logic__7401: VCU118RocketSystem__GC0,
-datapath__496: VCU118RocketSystem__GC0,
-case__202: VCU118RocketSystem__GC0,
-case__777: RocketTile__GCB0,
-logic__6160: VCU118RocketSystem__GC0,
-reg__1193: tracking_wrapper,
-logic__7409: VCU118RocketSystem__GC0,
-logic__1934: DCache,
-logic__2390: RocketTile__GCB0,
-logic__7319: VCU118RocketSystem__GC0,
-case__923: VCU118RocketSystem__GC0,
-FPGAUARTClockSinkDomain: VCU118RocketSystem__GC0,
-logic__259: VCU118RocketSystem__GC0,
-reg__1002: APBGpsBlock__GC0,
-datapath__648: tracking_wrapper,
-logic__3182: FPU__GB2,
-reg__192: VCU118RocketSystem__GC0,
-logic__6111: VCU118RocketSystem__GC0,
-reg__1059: APBGpsBlock__GC0,
-logic__1469: RocketTile__GCB0,
-reg__801: VCU118RocketSystem__GC0,
-reg__1173: tracking_wrapper,
-case__159: VCU118RocketSystem__GC0,
-logic__2214: DCache,
-logic__7844: APBGpsBlock__GC0,
-logic__6780: VCU118RocketSystem__GC0,
-case__700: RocketTile__GCB0,
-muxpart__102: RocketTile__GCB0,
-APBGpsBlock__GC0: APBGpsBlock__GC0,
-logic__995: VCU118RocketSystem__GC0,
-reg__1065: APBGpsBlock__GC0,
-logic__5883: RocketTile__GCB0,
-datapath__409: RocketTile__GCB0,
-case__229: VCU118RocketSystem__GC0,
-logic__6946: VCU118RocketSystem__GC0,
-case__39: VCU118RocketSystem__GC0,
-datapath__671: tracking_wrapper,
-logic__8590: tracking_wrapper,
-logic__1049: VCU118RocketSystem__GC0,
-logic__38: genesys2_rocket_top__GC0,
-logic__659: VCU118RocketSystem__GC0,
-acq_ca_gen: APBGpsBlock__GC0,
-ram__3: VCU118RocketSystem__GC0,
-logic__6241: VCU118RocketSystem__GC0,
-case__321: DCache,
-logic__3460: FPU__GB2,
-datapath__303: FPU__GB2,
-logic__7082: VCU118RocketSystem__GC0,
-logic__1448: RocketTile__GCB0,
-logic__2284: DCache,
-logic__834: VCU118RocketSystem__GC0,
-logic__8756: tracking_wrapper,
-logic__5258: RocketTile__GCB0,
-case__2: genesys2_rocket_top__GC0,
-case__319: DCache,
-case__171: VCU118RocketSystem__GC0,
-reg__601: RocketTile__GCB0,
-logic__4280: FPU__GB1,
-logic__507: VCU118RocketSystem__GC0,
-logic__6154: VCU118RocketSystem__GC0,
-logic__7639: VCU118RocketSystem__GC0,
-logic__1850: RocketTile__GCB0, DCache,
-RoundAnyRawFNToRecFN: FPU__GB2, FPU__GB1,
-logic__3842: FPU__GB1,
-logic__5325: RocketTile__GCB0,
-reg__301: RocketTile__GCB0,
-logic__6758: VCU118RocketSystem__GC0,
-logic__3702: FPU__GB1,
-reg__348: RocketTile__GCB0,
-case__1513: tracking_wrapper,
-muxpart__37: FPU__GB0,
-case__5: genesys2_rocket_top__GC0,
-logic__4623: RocketTile__GCB0,
-case__13: genesys2_rocket_top__GC0,
-logic__5865: RocketTile__GCB0,
-logic__4464: FPU__GB1,
-logic__4936: RocketTile__GCB0,
-case__494: FPU__GB2,
-logic__7312: VCU118RocketSystem__GC0,
-logic__6787: VCU118RocketSystem__GC0,
-logic__5055: RocketTile__GCB0,
-datapath__690: TLToAPB,
-logic__8595: tracking_wrapper,
-reg__457: FPU__GB1,
-case__734: RocketTile__GCB0,
-logic__1957: DCache,
-case__1371: tracking_wrapper,
-logic__3821: FPU__GB1,
-logic__5363: RocketTile__GCB0,
-reg__511: FPU__GB2,
-case__644: RocketTile__GCB0,
-datapath__145: VCU118RocketSystem__GC0,
-logic__5440: RocketTile__GCB0,
-reg__97: VCU118RocketSystem__GC0,
-logic__375: VCU118RocketSystem__GC0,
-Frontend: RocketTile__GCB0,
-logic__5141: RocketTile__GCB0,
-logic__1301: VCU118RocketSystem__GC0,
-logic__3547: FPU__GB1,
-logic__7382: VCU118RocketSystem__GC0,
-logic__2968: FPU__GB2, FPU__GB1,
-logic__3359: FPU__GB2,
-reg__995: VCU118RocketSystem__GC0,
-case__963: VCU118RocketSystem__GC0,
-reg__1157: tracking_wrapper,
-dsp48e1__12: APBGpsBlock__GC0,
-datapath__27: VCU118RocketSystem__GC0,
-case__1161: APBGpsBlock__GC0,
-datapath__45: VCU118RocketSystem__GC0,
-reg__382: FPU__GB0,
-logic__8383: tracking_wrapper,
-reg__526: FPU__GB1,
-logic__6589: VCU118RocketSystem__GC0,
-logic__5460: RocketTile__GCB0,
-reg__1148: tracking_wrapper,
-logic__4873: RocketTile__GCB0,
-logic__1205: VCU118RocketSystem__GC0,
-datapath__383: FPU__GB1,
-logic__4085: FPU__GB2,
-logic__8782: tracking_wrapper,
-double_ff_syn__parameterized0: tracking_wrapper,
-datapath__691: VCU118RocketSystem__GC0,
-datapath__480: VCU118RocketSystem__GC0,
-logic__6655: VCU118RocketSystem__GC0,
-ram__2: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__580: RocketTile__GCB0,
-logic__6106: VCU118RocketSystem__GC0,
-logic__6177: VCU118RocketSystem__GC0,
-reg__376: FPU__GB0,
-dsp48e1__47: tracking_wrapper,
-reg__120: VCU118RocketSystem__GC0,
-logic__3907: FPU__GB2, FPU__GB1,
-logic__6729: VCU118RocketSystem__GC0,
-addsub__3: tracking_wrapper,
-datapath__339: FPU__GB1,
-logic__585: VCU118RocketSystem__GC0,
-logic__8964: genesys2_rocket_top__GC0,
-reg__6: genesys2_rocket_top__GC0,
-case__1329: APBGpsBlock__GC0,
-logic__8391: tracking_wrapper,
-case__444: FPU__GB1,
-trck_top: tracking_wrapper,
-reg__1179: tracking_wrapper,
-case__1139: APBGpsBlock__GC0,
-case__262: VCU118RocketSystem__GC0,
-RVCExpander: RocketTile__GCB0,
-logic__5425: RocketTile__GCB0,
-logic__3719: FPU__GB1,
-muxpart__1: genesys2_rocket_top__GC0,
-case__683: RocketTile__GCB0,
-logic__4182: FPU__GB2,
-logic__357: VCU118RocketSystem__GC0,
-case__904: VCU118RocketSystem__GC0,
-logic__8945: TLToAPB,
-logic__5630: RocketTile__GCB0,
-logic__7001: VCU118RocketSystem__GC0,
-datapath__646: tracking_wrapper,
-reg__399: FPU__GB1,
-logic__8410: tracking_wrapper,
-case__1413: tracking_wrapper,
-logic__4660: RocketTile__GCB0,
-case__1002: VCU118RocketSystem__GC0,
-logic__3824: FPU__GB1,
-datapath__14: VCU118RocketSystem__GC0,
-reg__279: DCache,
-reg__579: RocketTile__GCB0,
-case__1349: tracking_wrapper,
-datapath__216: VCU118RocketSystem__GC0,
-case__554: FPU__GB2,
-logic__4894: RocketTile__GCB0,
-RoundAnyRawFNToRecFN_4: FPU__GB2, FPU__GB1,
-logic__655: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__672: RocketTile__GCB0,
-logic__1067: VCU118RocketSystem__GC0,
-logic__820: VCU118RocketSystem__GC0,
-reg__1050: APBGpsBlock__GC0,
-reg__630: RocketTile__GCB0,
-logic__6756: VCU118RocketSystem__GC0,
-logic__1727: DCache,
-case__6: genesys2_rocket_top__GC0,
-logic__4895: RocketTile__GCB0,
-logic__7376: VCU118RocketSystem__GC0,
-datapath__207: VCU118RocketSystem__GC0,
-logic__5858: RocketTile__GCB0,
-logic__4449: FPU__GB1,
-case__606: RocketTile__GCB0,
-logic__1912: DCache,
-case__27: VCU118RocketSystem__GC0,
-reg__781: VCU118RocketSystem__GC0,
-reg__122: VCU118RocketSystem__GC0,
-case__120: VCU118RocketSystem__GC0,
-logic__6155: VCU118RocketSystem__GC0,
-datapath__393: RocketTile__GCB0,
-case__533: FPU__GB2,
-case__621: RocketTile__GCB0,
-logic__5017: RocketTile__GCB0,
-logic__2622: RocketTile__GCB0,
-logic__4121: FPU__GB2,
-logic__4608: RocketTile__GCB0,
-logic__4171: FPU__GB2,
-logic__1185: VCU118RocketSystem__GC0,
-logic__5253: RocketTile__GCB0,
-logic__2106: DCache,
-case__1166: APBGpsBlock__GC0,
-logic__6651: VCU118RocketSystem__GC0,
-cacode_gen_trck: tracking_wrapper,
-logic__6700: VCU118RocketSystem__GC0,
-logic__6145: VCU118RocketSystem__GC0,
-reg__926: VCU118RocketSystem__GC0,
-case__1385: tracking_wrapper,
-case__1042: VCU118RocketSystem__GC0,
-case__1416: tracking_wrapper,
-logic__4616: RocketTile__GCB0,
-dsp48e1__5: APBGpsBlock__GC0,
-case__907: VCU118RocketSystem__GC0,
-datapath__447: RocketTile__GCB0,
-case__692: RocketTile__GCB0,
-logic__5307: RocketTile__GCB0,
-logic__1937: DCache,
-logic__3817: FPU__GB1,
-reg__29: VCU118RocketSystem__GC0,
-logic__6340: VCU118RocketSystem__GC0,
-reg__639: RocketTile__GCB0,
-logic__1576: DCache,
-datapath__5: genesys2_rocket_top__GC0,
-logic__4738: RocketTile__GCB0,
-datapath__299: FPU__GB2, FPU__GB1,
-case__147: VCU118RocketSystem__GC0,
-case__144: VCU118RocketSystem__GC0,
-dsp48e1__37: tracking_wrapper,
-reg__10: genesys2_rocket_top__GC0,
-addsub__5: tracking_wrapper,
-logic__3160: FPU__GB2,
-case__1442: tracking_wrapper,
-logic__8628: tracking_wrapper,
-reg__507: FPU__GB2,
-case__1004: VCU118RocketSystem__GC0,
-case__788: VCU118RocketSystem__GC0,
-datapath__645: tracking_wrapper,
-logic__8866: tracking_wrapper,
-reg__1275: tracking_wrapper,
-logic__4349: FPU__GB1,
-reg__86: VCU118RocketSystem__GC0,
-logic__5361: RocketTile__GCB0,
-reg__1127: APBGpsBlock__GC0,
-datapath__200: VCU118RocketSystem__GC0,
-mult_30_25_55: tracking_wrapper,
-reg__833: VCU118RocketSystem__GC0, APBGpsBlock__GC0,
-reg__980: VCU118RocketSystem__GC0,
-reg__992: VCU118RocketSystem__GC0,
-logic__614: VCU118RocketSystem__GC0,
-logic__4911: RocketTile__GCB0,
-logic__8795: tracking_wrapper,
-logic__4262: FPU__GB2,
-reg__954: VCU118RocketSystem__GC0,
-logic__4656: RocketTile__GCB0,
-logic__2862: FPU__GB1,
-logic__8040: APBGpsBlock__GC0,
-case__1414: tracking_wrapper,
-logic__8724: tracking_wrapper,
-reg__541: FPU__GB1,
-logic__4880: RocketTile__GCB0,
-logic__1126: VCU118RocketSystem__GC0,
-datapath__376: FPU__GB2,
-logic__4455: FPU__GB1,
-case__1031: VCU118RocketSystem__GC0,
-logic__5462: RocketTile__GCB0,
-case__699: RocketTile__GCB0,
-reg__974: VCU118RocketSystem__GC0,
-case__563: FPU__GB2,
-logic__4052: FPU__GB2,
-logic__6357: VCU118RocketSystem__GC0,
-muxpart__66: FPU__GB0,
-case__939: VCU118RocketSystem__GC0,
-logic__7313: VCU118RocketSystem__GC0,
-datapath__585: APBGpsBlock__GC0,
-case__241: VCU118RocketSystem__GC0,
-case__802: VCU118RocketSystem__GC0,
-reg__484: FPU__GB1,
-logic__5333: RocketTile__GCB0,
-logic__5062: RocketTile__GCB0,
-reg__900: VCU118RocketSystem__GC0,
-datapath__32: VCU118RocketSystem__GC0,
-case__546: FPU__GB2,
-logic__8740: tracking_wrapper,
-HellaCacheArbiter: RocketTile__GCB0,
-reg__1195: tracking_wrapper,
-reg__346: RocketTile__GCB0,
-reg__357: RocketTile__GCB0,
-logic__2674: FPU__GB1,
-logic__6308: VCU118RocketSystem__GC0,
-logic__1350: VCU118RocketSystem__GC0,
-logic__878: VCU118RocketSystem__GC0,
-reg__253: DCache,
-reg__312: RocketTile__GCB0,
-logic__613: VCU118RocketSystem__GC0,
-case__757: RocketTile__GCB0,
-logic__7240: VCU118RocketSystem__GC0,
-logic__2780: FPU__GB1,
-dsp48e1__23: APBGpsBlock__GC0,
-case__614: RocketTile__GCB0,
-case__320: DCache,
-case__274: VCU118RocketSystem__GC0,
-ram__1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__997: VCU118RocketSystem__GC0,
-logic__4852: RocketTile__GCB0,
-TLBuffer_a32d64s2k1z4u_1: VCU118RocketSystem__GC0,
-logic__4498: RocketTile__GCB0,
-reg__254: DCache,
-datapath__319: FPU__GB2,
-logic__7548: VCU118RocketSystem__GC0,
-reg__1342: TLToAPB,
-logic__6207: VCU118RocketSystem__GC0,
-case__1137: APBGpsBlock__GC0,
-case__1465: tracking_wrapper,
-logic__6564: VCU118RocketSystem__GC0,
-logic__2709: FPU__GB1,
-reg__47: VCU118RocketSystem__GC0,
-case__418: RocketTile__GCB0,
-case__360: DCache,
-case__287: RocketTile__GCB0,
-logic__5405: RocketTile__GCB0,
-logic__5268: RocketTile__GCB0,
-case__1352: tracking_wrapper,
-ClockGroupAggregator_cbus: VCU118RocketSystem__GC0,
-logic__2082: DCache,
-logic__740: VCU118RocketSystem__GC0,
-reg__1045: APBGpsBlock__GC0,
-reg__43: VCU118RocketSystem__GC0,
-reg__1261: tracking_wrapper,
-logic__1835: RocketTile__GCB0, DCache,
-reg__1004: APBGpsBlock__GC0,
-logic__2078: DCache,
-logic__3205: FPU__GB2,
-logic__2557: RocketTile__GCB0,
-logic__6779: VCU118RocketSystem__GC0,
-logic__4272: FPU__GB2,
-FPToInt: FPU__GB2,
-datapath__436: RocketTile__GCB0,
-logic__1051: VCU118RocketSystem__GC0,
-logic__2988: FPU__GB2, FPU__GB1,
-dsp48e1__2: APBGpsBlock__GC0,
-logic__8785: tracking_wrapper,
-logic__8571: tracking_wrapper,
-case__275: VCU118RocketSystem__GC0,
-case__429: RocketTile__GCB0,
-reg__166: VCU118RocketSystem__GC0,
-logic__5482: RocketTile__GCB0,
-logic__4148: FPU__GB2,
-logic__2681: FPU__GB1,
-datapath__565: APBGpsBlock__GC0,
-case__111: VCU118RocketSystem__GC0,
-logic__3184: FPU__GB2,
-reg__1166: tracking_wrapper,
-datapath__263: RocketTile__GCB0,
-logic__4260: FPU__GB2,
-logic__8916: APBGpsBlock__GC0,
-reg__556: FPU__GB1,
-logic__7865: APBGpsBlock__GC0,
-logic__5958: RocketTile__GCB0,
-logic__8152: APBGpsBlock__GC0,
-case__1333: tracking_wrapper,
-logic__7388: VCU118RocketSystem__GC0,
-datapath__446: RocketTile__GCB0,
-case__1415: tracking_wrapper,
-logic__6579: VCU118RocketSystem__GC0,
-reg__1274: tracking_wrapper,
-logic__5434: RocketTile__GCB0,
-logic__5905: RocketTile__GCB0,
-logic__6019: RocketTile__GCB0,
-reg__1147: tracking_wrapper,
-logic__345: VCU118RocketSystem__GC0,
-logic__4684: RocketTile__GCB0,
-logic__4192: FPU__GB2,
-counter__28: genesys2_rocket_top__GC0,
-logic__313: VCU118RocketSystem__GC0,
-logic__5690: RocketTile__GCB0,
-case__149: VCU118RocketSystem__GC0,
-case__73: VCU118RocketSystem__GC0,
-logic__4609: RocketTile__GCB0,
-reg__305: RocketTile__GCB0,
-dsp48e1__16: APBGpsBlock__GC0,
-logic__6785: VCU118RocketSystem__GC0,
-case__130: VCU118RocketSystem__GC0,
-reg__1066: APBGpsBlock__GC0,
-logic__8564: tracking_wrapper,
-reg__860: VCU118RocketSystem__GC0,
-reg__829: VCU118RocketSystem__GC0,
-reg__218: VCU118RocketSystem__GC0,
-logic__4655: RocketTile__GCB0,
-case__627: RocketTile__GCB0,
-logic__3924: FPU__GB2, FPU__GB1,
-logic__4879: RocketTile__GCB0,
-logic__4189: FPU__GB2,
-logic__2670: FPU__GB1,
-logic__4853: RocketTile__GCB0,
-logic__2829: FPU__GB1,
-case__191: VCU118RocketSystem__GC0,
-logic__8048: APBGpsBlock__GC0,
-reg__15: genesys2_rocket_top__GC0,
-case__961: VCU118RocketSystem__GC0,
-datapath__127: VCU118RocketSystem__GC0,
-logic__3487: FPU__GB2,
-case__244: VCU118RocketSystem__GC0,
-case__220: VCU118RocketSystem__GC0,
-datapath__140: VCU118RocketSystem__GC0,
-reg__643: RocketTile__GCB0,
-logic__6054: RocketTile__GCB0,
-case__558: FPU__GB2,
-case__270: VCU118RocketSystem__GC0,
-logic__2815: FPU__GB1,
-datapath__279: RocketTile__GCB0,
-datapath__69: VCU118RocketSystem__GC0,
-reg__1086: APBGpsBlock__GC0,
-case__121: VCU118RocketSystem__GC0,
-datapath__536: APBGpsBlock__GC0,
-logic__1048: VCU118RocketSystem__GC0,
-logic__3531: FPU__GB1,
-case__474: FPU__GB2,
-reg__567: FPU__GB1,
-logic__1273: VCU118RocketSystem__GC0,
-logic__1040: VCU118RocketSystem__GC0,
-logic__2933: FPU__GB1,
-datapath: genesys2_rocket_top__GC0,
-datapath__77: VCU118RocketSystem__GC0,
-case__576: FPU__GB1,
-case__1274: APBGpsBlock__GC0,
-logic__6153: VCU118RocketSystem__GC0,
-logic__458: VCU118RocketSystem__GC0,
-case__652: RocketTile__GCB0,
-reg__735: RocketTile__GCB0,
-datapath__369: FPU__GB2,
-reg__480: FPU__GB1,
-logic__2336: RocketTile__GCB0,
-logic__3358: FPU__GB2,
-datapath__352: FPU__GB1,
-reg__3: genesys2_rocket_top__GC0,
-ClockGroup: VCU118RocketSystem__GC0,
-logic__3696: FPU__GB1,
-datapath__616: APBGpsBlock__GC0,
-logic__5254: RocketTile__GCB0,
-logic__661: VCU118RocketSystem__GC0,
-logic__618: VCU118RocketSystem__GC0,
-case__1539: TLToAPB,
-datapath__328: FPU__GB2,
-logic__5689: RocketTile__GCB0,
-logic__6773: VCU118RocketSystem__GC0,
-datapath__416: RocketTile__GCB0,
-logic__8918: APBGpsBlock__GC0,
-reg__894: VCU118RocketSystem__GC0,
-logic__1003: VCU118RocketSystem__GC0,
-logic__5058: RocketTile__GCB0,
-reg__618: RocketTile__GCB0,
-dsp48e1__35: tracking_wrapper,
-logic__470: VCU118RocketSystem__GC0,
-case__396: RocketTile__GCB0,
-case__935: VCU118RocketSystem__GC0,
-logic__6376: VCU118RocketSystem__GC0,
-TLFragmenter_bootrom: VCU118RocketSystem__GC0,
-logic__7205: VCU118RocketSystem__GC0,
-logic__8882: APBGpsBlock__GC0,
-reg__553: FPU__GB1,
-logic__6539: VCU118RocketSystem__GC0,
-logic__2710: FPU__GB1,
-datapath__289: FPU__GB1,
-reg__488: FPU__GB1,
-logic__4716: RocketTile__GCB0,
-muxpart__96: RocketTile__GCB0,
-case__56: VCU118RocketSystem__GC0,
-reg__728: RocketTile__GCB0,
-reg__914: VCU118RocketSystem__GC0,
-logic__2110: DCache,
-reg__1226: tracking_wrapper,
-logic__4422: FPU__GB1,
-logic__1193: VCU118RocketSystem__GC0,
-logic__2072: DCache,
-logic__4276: FPU__GB1,
-logic__6373: VCU118RocketSystem__GC0,
-datapath__638: tracking_wrapper,
-afe_top: APBGpsBlock__GC0,
-reg__28: VCU118RocketSystem__GC0,
-case__1359: tracking_wrapper,
-datapath__455: RocketTile__GCB0,
-logic__2698: FPU__GB1,
-logic__1950: DCache,
-case__128: VCU118RocketSystem__GC0,
-reg__23: VCU118RocketSystem__GC0,
-case__1123: APBGpsBlock__GC0,
-logic__4737: RocketTile__GCB0,
-logic__5467: RocketTile__GCB0,
-logic__5854: RocketTile__GCB0,
-datapath__535: APBGpsBlock__GC0,
-logic__6187: VCU118RocketSystem__GC0,
-case__1365: tracking_wrapper,
-logic__2907: FPU__GB1,
-reg__273: DCache,
-logic__2875: FPU__GB1,
-case__176: VCU118RocketSystem__GC0,
-case__945: VCU118RocketSystem__GC0,
-reg__1325: tracking_wrapper,
-logic__331: VCU118RocketSystem__GC0,
-case__1099: APBGpsBlock__GC0,
-logic__2655: RocketTile__GCB0,
-extrom__1: APBGpsBlock__GC0,
-logic__3990: FPU__GB1,
-logic__6471: VCU118RocketSystem__GC0,
-logic__1746: DCache,
-logic__5424: RocketTile__GCB0,
-logic__2351: RocketTile__GCB0,
-case__12: genesys2_rocket_top__GC0,
-extram: DCache,
-logic__6891: VCU118RocketSystem__GC0,
-logic__4244: FPU__GB2,
-logic__6195: VCU118RocketSystem__GC0,
-logic__376: VCU118RocketSystem__GC0,
-logic__8476: tracking_wrapper,
-datapath__656: tracking_wrapper,
-logic__4504: RocketTile__GCB0,
-case__814: VCU118RocketSystem__GC0,
-datapath__112: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__1354: tracking_wrapper,
-reg__1031: APBGpsBlock__GC0,
-logic__4266: FPU__GB2,
-logic__2799: FPU__GB1,
-logic__5695: RocketTile__GCB0,
-reg__620: RocketTile__GCB0,
-logic__7651: VCU118RocketSystem__GC0,
-reg__794: VCU118RocketSystem__GC0,
-logic__1373: VCU118RocketSystem__GC0,
-logic__4007: FPU__GB2,
-logic__1227: VCU118RocketSystem__GC0,
-datapath__652: tracking_wrapper,
-case__979: VCU118RocketSystem__GC0,
-datapath__337: FPU__GB1,
-logic__1862: RocketTile__GCB0, DCache,
-muxpart: genesys2_rocket_top__GC0,
-logic__79: genesys2_rocket_top__GC0,
-logic__6636: VCU118RocketSystem__GC0,
-reg__202: VCU118RocketSystem__GC0,
-logic__2369: RocketTile__GCB0,
-case__1323: APBGpsBlock__GC0,
-reg__523: FPU__GB1,
-logic__927: VCU118RocketSystem__GC0,
-case__579: FPU__GB1,
-logic__8812: tracking_wrapper,
-logic__6772: VCU118RocketSystem__GC0,
-case__123: VCU118RocketSystem__GC0,
-datapath__667: tracking_wrapper,
-case__338: DCache,
-datapath__449: RocketTile__GCB0,
-case__481: FPU__GB2,
-logic__6303: VCU118RocketSystem__GC0,
-reg__726: RocketTile__GCB0,
-logic__6193: VCU118RocketSystem__GC0,
-datapath__10: VCU118RocketSystem__GC0,
-logic__650: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2196: DCache,
-case__351: DCache,
-case__1406: tracking_wrapper,
-logic__1620: DCache,
-logic__8673: tracking_wrapper,
-logic__3305: FPU__GB2,
-datapath__389: FPU__GB1,
-logic__3819: FPU__GB1,
-case__18: genesys2_rocket_top__GC0,
-case__355: DCache,
-logic__4404: FPU__GB1,
-reg__1234: tracking_wrapper,
-logic__8722: tracking_wrapper,
-logic__2: genesys2_rocket_top__GC0,
-logic__4849: RocketTile__GCB0,
-logic__4380: FPU__GB1,
-case__179: VCU118RocketSystem__GC0,
-logic__7184: VCU118RocketSystem__GC0,
-logic__8168: APBGpsBlock__GC0,
-logic__6464: VCU118RocketSystem__GC0,
-case__1408: tracking_wrapper,
-logic__8045: APBGpsBlock__GC0,
-reg__617: RocketTile__GCB0,
-reg__988: VCU118RocketSystem__GC0,
-case__1232: APBGpsBlock__GC0,
-datapath__545: APBGpsBlock__GC0,
-reg__1304: tracking_wrapper,
-case__1162: APBGpsBlock__GC0,
-case__584: FPU__GB1,
-logic__2409: RocketTile__GCB0,
-reg__581: RocketTile__GCB0,
-logic__4000: FPU__GB2,
-case__284: RocketTile__GCB0,
-Queue1_RegMapperInput_i9_m8: VCU118RocketSystem__GC0,
-logic__8321: tracking_wrapper,
-case__210: VCU118RocketSystem__GC0,
-logic__704: VCU118RocketSystem__GC0,
-case__586: FPU__GB1,
-muxpart__143: APBGpsBlock__GC0,
-reg__531: FPU__GB1,
-logic__6462: VCU118RocketSystem__GC0,
-reg__158: VCU118RocketSystem__GC0,
-logic__3661: FPU__GB1,
-logic__8181: APBGpsBlock__GC0,
-case__157: VCU118RocketSystem__GC0,
-logic__176: VCU118RocketSystem__GC0,
-reg__295: RocketTile__GCB0,
-logic__3371: FPU__GB2,
-case__1290: APBGpsBlock__GC0,
-logic__952: VCU118RocketSystem__GC0,
-logic__1407: VCU118RocketSystem__GC0,
-datapath__71: VCU118RocketSystem__GC0,
-ram_2x124: VCU118RocketSystem__GC0,
-logic__2669: FPU__GB1,
-case__837: VCU118RocketSystem__GC0,
-logic__6180: VCU118RocketSystem__GC0,
-datapath__253: DCache,
-reg__1279: tracking_wrapper,
-logic__2650: RocketTile__GCB0,
-reg__1105: APBGpsBlock__GC0,
-reg__401: FPU__GB1,
-logic__7900: APBGpsBlock__GC0,
-TLBusBypassBar: VCU118RocketSystem__GC0,
-case__1355: tracking_wrapper,
-logic__6555: VCU118RocketSystem__GC0,
-reg__759: RocketTile__GCB0,
-reg__898: VCU118RocketSystem__GC0,
-case__1511: tracking_wrapper,
-muxpart__77: FPU__GB0,
-reg__1305: tracking_wrapper,
-logic__451: VCU118RocketSystem__GC0,
-logic__3703: FPU__GB1,
-reg__536: FPU__GB1,
-reg__727: RocketTile__GCB0,
-logic__31: genesys2_rocket_top__GC0,
-logic__5484: RocketTile__GCB0,
-logic__7534: VCU118RocketSystem__GC0,
-datapath__516: VCU118RocketSystem__GC0,
-logic__967: VCU118RocketSystem__GC0,
-logic__6857: VCU118RocketSystem__GC0,
-case__189: VCU118RocketSystem__GC0,
-datapath__113: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__8117: APBGpsBlock__GC0,
-case__947: VCU118RocketSystem__GC0,
-logic__4926: RocketTile__GCB0,
-muxpart__20: FPU__GB0,
-case__141: VCU118RocketSystem__GC0,
-reg__31: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7261: VCU118RocketSystem__GC0,
-reg__1209: tracking_wrapper,
-logic__7633: VCU118RocketSystem__GC0,
-case__213: VCU118RocketSystem__GC0,
-logic__5287: RocketTile__GCB0,
-case__203: VCU118RocketSystem__GC0,
-logic__7370: VCU118RocketSystem__GC0,
-logic__8878: APBGpsBlock__GC0,
-logic__4724: RocketTile__GCB0,
-reg__804: VCU118RocketSystem__GC0,
-case__134: VCU118RocketSystem__GC0,
-logic__1918: DCache,
-reg__1162: tracking_wrapper,
-case__467: FPU__GB2,
-case__1220: APBGpsBlock__GC0,
-logic__4606: RocketTile__GCB0,
-logic__2970: FPU__GB2, FPU__GB1,
-case__309: DCache,
-logic__5053: RocketTile__GCB0,
-logic__8963: genesys2_rocket_top__GC0,
-logic__2173: DCache,
-reg__157: VCU118RocketSystem__GC0,
-case__1459: tracking_wrapper,
-logic__6388: VCU118RocketSystem__GC0,
-logic__5942: RocketTile__GCB0,
-case__125: VCU118RocketSystem__GC0,
-regfile_32x65: FPU__GB0,
-logic__2951: FPU__GB2, FPU__GB1,
-datapath__595: APBGpsBlock__GC0,
-logic__5381: RocketTile__GCB0,
-reg__172: VCU118RocketSystem__GC0,
-logic__4136: FPU__GB2,
-logic__55: genesys2_rocket_top__GC0,
-logic__1326: VCU118RocketSystem__GC0,
-reg__844: VCU118RocketSystem__GC0,
-reg__110: VCU118RocketSystem__GC0,
-reg__82: VCU118RocketSystem__GC0,
-case__98: VCU118RocketSystem__GC0,
-logic__4049: FPU__GB2,
-logic__6132: VCU118RocketSystem__GC0,
-case__137: VCU118RocketSystem__GC0,
-logic__8622: tracking_wrapper,
-logic__6011: RocketTile__GCB0,
-reg__286: RocketTile__GCB0,
-logic__6791: VCU118RocketSystem__GC0,
-case__1225: APBGpsBlock__GC0,
-datapath__255: DCache,
-case__227: VCU118RocketSystem__GC0,
-reg__1264: tracking_wrapper,
-logic__3324: FPU__GB2,
-logic__968: VCU118RocketSystem__GC0,
-muxpart__40: FPU__GB0,
-logic__2186: DCache,
-logic__5456: RocketTile__GCB0,
-case__874: VCU118RocketSystem__GC0,
-case__1434: tracking_wrapper,
-logic__6271: VCU118RocketSystem__GC0,
-logic__6353: VCU118RocketSystem__GC0,
-logic__940: VCU118RocketSystem__GC0,
-case__613: RocketTile__GCB0,
-reg__521: FPU__GB1,
-logic__2000: DCache,
-logic__2671: FPU__GB1,
-logic__6400: VCU118RocketSystem__GC0,
-reg__836: VCU118RocketSystem__GC0,
-logic__6486: VCU118RocketSystem__GC0,
-logic__6387: VCU118RocketSystem__GC0,
-logic__526: VCU118RocketSystem__GC0,
-datapath__672: tracking_wrapper,
-logic__4390: FPU__GB1,
-reg__706: RocketTile__GCB0,
-extram__2: RocketTile__GCB0,
-case__1184: APBGpsBlock__GC0,
-reg__71: VCU118RocketSystem__GC0,
-IntXbar_i3_o1: RocketTile__GCB0,
-logic__6524: VCU118RocketSystem__GC0,
-logic__4758: RocketTile__GCB0,
-case__167: VCU118RocketSystem__GC0,
-logic__6572: VCU118RocketSystem__GC0,
-datapath__429: RocketTile__GCB0,
-logic__4224: FPU__GB2,
-logic__6467: VCU118RocketSystem__GC0,
-case__645: RocketTile__GCB0,
-logic__4552: RocketTile__GCB0,
-logic__4581: RocketTile__GCB0,
-logic__5634: RocketTile__GCB0,
-logic__566: VCU118RocketSystem__GC0,
-logic__7576: VCU118RocketSystem__GC0,
-muxpart__82: FPU__GB0,
-logic__6629: VCU118RocketSystem__GC0,
-logic__2373: RocketTile__GCB0,
-reg__1191: tracking_wrapper,
-logic__1522: DCache,
-logic__4679: RocketTile__GCB0,
-logic__830: VCU118RocketSystem__GC0,
-reg__530: FPU__GB1,
-case__485: FPU__GB2,
-reg__762: RocketTile__GCB0,
-logic__1624: DCache,
-reg__789: VCU118RocketSystem__GC0,
-muxpart__41: FPU__GB0,
-logic__4766: RocketTile__GCB0,
-reg__989: VCU118RocketSystem__GC0,
-logic__5646: RocketTile__GCB0,
-case__482: FPU__GB2,
-case__943: VCU118RocketSystem__GC0,
-logic__2925: FPU__GB1,
-logic__7752: APBGpsBlock__GC0,
-logic__8030: APBGpsBlock__GC0,
-muxpart__27: FPU__GB0,
-reg__1021: APBGpsBlock__GC0,
-logic__6802: VCU118RocketSystem__GC0,
-logic__7697: APBGpsBlock__GC0,
-reg__1265: tracking_wrapper,
-logic__51: genesys2_rocket_top__GC0,
-rom__2: APBGpsBlock__GC0,
-case__649: RocketTile__GCB0,
-logic__8741: tracking_wrapper,
-logic__8352: tracking_wrapper,
-logic__7590: VCU118RocketSystem__GC0,
-case__784: VCU118RocketSystem__GC0,
-logic__1314: VCU118RocketSystem__GC0,
-reg__1347: TLToAPB,
-logic__3202: FPU__GB2,
-logic__1798: DCache,
-reg__629: RocketTile__GCB0,
-logic__6074: RocketTile__GCB0,
-logic__5068: RocketTile__GCB0,
-case__660: RocketTile__GCB0,
-logic__1984: DCache,
-logic__3106: FPU__GB2,
-logic__5286: RocketTile__GCB0,
-logic__2613: RocketTile__GCB0,
-reg__21: VCU118RocketSystem__GC0,
-case__1218: APBGpsBlock__GC0,
-reg__50: VCU118RocketSystem__GC0,
-logic__552: VCU118RocketSystem__GC0,
-reg__1313: tracking_wrapper,
-logic__8047: APBGpsBlock__GC0,
-reg__600: RocketTile__GCB0,
-reg__562: FPU__GB1,
-case__937: VCU118RocketSystem__GC0,
-logic__835: VCU118RocketSystem__GC0,
-logic__6784: VCU118RocketSystem__GC0,
-logic__8356: tracking_wrapper,
-reg__497: FPU__GB2,
-case__476: FPU__GB2,
-logic__3053: FPU__GB2,
-case__1453: tracking_wrapper,
-logic__963: VCU118RocketSystem__GC0,
-case__439: FPU__GB0,
-datapath__39: VCU118RocketSystem__GC0,
-reg__730: RocketTile__GCB0,
-case__428: RocketTile__GCB0,
-logic__102: VCU118RocketSystem__GC0,
-logic__2377: RocketTile__GCB0,
-case__146: VCU118RocketSystem__GC0,
-logic__8599: tracking_wrapper,
-case__581: FPU__GB1,
-reg__638: RocketTile__GCB0,
-muxpart__3: genesys2_rocket_top__GC0,
-logic__3551: FPU__GB1,
-logic__4945: RocketTile__GCB0,
-logic__6137: VCU118RocketSystem__GC0,
-reg__363: RocketTile__GCB0,
-datapath__291: FPU__GB1,
-case__1038: VCU118RocketSystem__GC0,
-datapath__175: VCU118RocketSystem__GC0,
-logic__5686: RocketTile__GCB0,
-reg__866: VCU118RocketSystem__GC0,
-logic__324: VCU118RocketSystem__GC0,
-datapath__283: RocketTile__GCB0,
-logic__3728: FPU__GB1,
-reg__330: RocketTile__GCB0,
-logic__8032: APBGpsBlock__GC0,
-logic__1559: DCache,
-datapath__636: tracking_wrapper,
-logic__6109: VCU118RocketSystem__GC0,
-logic__1686: DCache,
-logic__6042: RocketTile__GCB0,
-datapath__256: DCache,
-logic__5219: RocketTile__GCB0,
-signinv: RocketTile__GCB0,
-datapath__15: VCU118RocketSystem__GC0,
-reg__1013: APBGpsBlock__GC0,
-case__10: genesys2_rocket_top__GC0,
-logic__123: VCU118RocketSystem__GC0,
-datapath__685: tracking_wrapper,
-logic__446: VCU118RocketSystem__GC0,
-logic__8682: tracking_wrapper,
-case__340: DCache,
-datapath__419: RocketTile__GCB0,
-logic__3770: FPU__GB1,
-logic__8883: APBGpsBlock__GC0,
-logic__4329: FPU__GB1,
-logic__4714: RocketTile__GCB0,
-logic__6463: VCU118RocketSystem__GC0,
-reg__282: DCache,
-reg__570: FPU__GB1,
-logic__5420: RocketTile__GCB0,
-logic__3102: FPU__GB2,
-logic__4005: FPU__GB2,
-datapath__435: RocketTile__GCB0,
-datapath__643: tracking_wrapper,
-ram_2x99: VCU118RocketSystem__GC0,
-logic__2121: DCache,
-case__886: VCU118RocketSystem__GC0,
-case__903: VCU118RocketSystem__GC0,
-logic__340: VCU118RocketSystem__GC0,
-reg__997: APBGpsBlock__GC0, tracking_wrapper,
-case__1169: APBGpsBlock__GC0,
-reg__889: VCU118RocketSystem__GC0,
-case__659: RocketTile__GCB0,
-logic__8407: tracking_wrapper,
-case__952: VCU118RocketSystem__GC0,
-extram__1: RocketTile__GCB0,
-logic__2686: FPU__GB1,
-logic__5199: RocketTile__GCB0,
-datapath__624: tracking_wrapper,
-logic__8253: tracking_wrapper,
-datapath__606: APBGpsBlock__GC0,
-logic__4144: FPU__GB2,
-reg__1300: tracking_wrapper,
-logic__1597: DCache,
-datapath__676: tracking_wrapper,
-reg__1121: APBGpsBlock__GC0,
-reg__185: VCU118RocketSystem__GC0,
-logic__4555: RocketTile__GCB0,
-case__367: RocketTile__GCB0,
-case__166: VCU118RocketSystem__GC0,
-logic__2708: FPU__GB1,
-logic__4332: FPU__GB1,
-logic__3183: FPU__GB2,
-case__736: RocketTile__GCB0,
-logic__2482: RocketTile__GCB0,
-reg__1083: APBGpsBlock__GC0,
-reg__809: VCU118RocketSystem__GC0,
-case__1376: tracking_wrapper,
-case__223: VCU118RocketSystem__GC0,
-reg__862: VCU118RocketSystem__GC0,
-datapath__108: VCU118RocketSystem__GC0,
-logic__2921: FPU__GB1,
-logic__6257: VCU118RocketSystem__GC0,
-logic__4897: RocketTile__GCB0,
-reg__832: VCU118RocketSystem__GC0,
-reg__117: VCU118RocketSystem__GC0,
-logic__1383: VCU118RocketSystem__GC0,
-logic__371: VCU118RocketSystem__GC0,
-case__716: RocketTile__GCB0,
-logic__4199: FPU__GB2,
-acq_wrapper: APBGpsBlock__GC0,
-logic__2635: RocketTile__GCB0,
-logic__955: VCU118RocketSystem__GC0,
-logic__8567: tracking_wrapper,
-reg__400: FPU__GB1,
-logic__7172: VCU118RocketSystem__GC0,
-case__53: VCU118RocketSystem__GC0,
-case__193: VCU118RocketSystem__GC0,
-cdc_fifo_gray: tracking_wrapper,
-logic__2370: RocketTile__GCB0,
-logic__4843: RocketTile__GCB0,
-case__174: VCU118RocketSystem__GC0,
-reg__569: FPU__GB1,
-logic__8142: APBGpsBlock__GC0,
-logic__4971: RocketTile__GCB0,
-logic__2361: RocketTile__GCB0,
-logic__1882: RocketTile__GCB0, DCache,
-logic__6736: VCU118RocketSystem__GC0,
-reg__559: FPU__GB1,
-case__665: RocketTile__GCB0,
-logic__7912: APBGpsBlock__GC0,
-logic__7780: APBGpsBlock__GC0,
-logic__66: genesys2_rocket_top__GC0,
-reg__119: VCU118RocketSystem__GC0,
-case__242: VCU118RocketSystem__GC0,
-logic__5334: RocketTile__GCB0,
-case__1374: tracking_wrapper,
-datapath__144: VCU118RocketSystem__GC0,
-logic__4668: RocketTile__GCB0,
-TLFIFOFixer: VCU118RocketSystem__GC0,
-logic__1699: DCache,
-logic__4727: RocketTile__GCB0,
-datapath__590: APBGpsBlock__GC0,
-logic__6031: RocketTile__GCB0,
-logic__72: genesys2_rocket_top__GC0,
-logic__1325: VCU118RocketSystem__GC0,
-logic__6620: VCU118RocketSystem__GC0,
-case__117: VCU118RocketSystem__GC0,
-datapath__524: APBGpsBlock__GC0,
-logic__6445: VCU118RocketSystem__GC0,
-case__1519: APBGpsBlock__GC0,
-muxpart__10: DCache,
-logic__4828: RocketTile__GCB0,
-reg__235: DCache,
-reg__651: RocketTile__GCB0,
-case__661: RocketTile__GCB0,
-reg__787: VCU118RocketSystem__GC0,
-datapath__229: VCU118RocketSystem__GC0,
-datapath__562: APBGpsBlock__GC0,
-gray_to_binary: tracking_wrapper,
-logic__4401: FPU__GB1,
-logic__2491: RocketTile__GCB0,
-datapath__72: VCU118RocketSystem__GC0,
-logic__1441: RocketTile__GCB0,
-Queue2_TLBundleA_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__2687: FPU__GB1,
-logic__5271: RocketTile__GCB0,
-case__607: RocketTile__GCB0,
-logic__703: VCU118RocketSystem__GC0,
-datapath__619: tracking_wrapper,
-muxpart__227: tracking_wrapper,
-IntSyncCrossingSource_n1x2: VCU118RocketSystem__GC0,
-case__1426: tracking_wrapper,
-datapath__170: VCU118RocketSystem__GC0,
-reg__890: VCU118RocketSystem__GC0,
-case__786: VCU118RocketSystem__GC0,
-logic__7379: VCU118RocketSystem__GC0,
-logic__6448: VCU118RocketSystem__GC0,
-logic__2707: FPU__GB1,
-logic__4445: FPU__GB1,
-logic__2868: FPU__GB1,
-logic__8784: tracking_wrapper,
-case__622: RocketTile__GCB0,
-datapath__29: VCU118RocketSystem__GC0,
-logic__7043: VCU118RocketSystem__GC0,
-case__867: VCU118RocketSystem__GC0,
-reg__849: VCU118RocketSystem__GC0,
-case__402: RocketTile__GCB0,
-case__636: RocketTile__GCB0,
-case__1337: tracking_wrapper,
-logic__7465: VCU118RocketSystem__GC0,
-datapath__115: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-SBToTL: VCU118RocketSystem__GC0,
-logic__3250: FPU__GB2,
-datapath__225: VCU118RocketSystem__GC0,
-logic__5056: RocketTile__GCB0,
-logic__5373: RocketTile__GCB0,
-datapath__500: VCU118RocketSystem__GC0,
-case__15: genesys2_rocket_top__GC0,
-logic__437: VCU118RocketSystem__GC0,
-logic__7681: APBGpsBlock__GC0,
-datapath__404: RocketTile__GCB0,
-reg__212: VCU118RocketSystem__GC0,
-datapath__66: VCU118RocketSystem__GC0,
-logic__956: VCU118RocketSystem__GC0,
-reg__703: RocketTile__GCB0,
-reg__1260: tracking_wrapper,
-case__257: VCU118RocketSystem__GC0,
-reg__659: RocketTile__GCB0,
-reg__743: RocketTile__GCB0,
-reg__242: DCache,
-logic__2031: DCache,
-logic__6261: VCU118RocketSystem__GC0,
-logic__3812: FPU__GB1,
-case__973: VCU118RocketSystem__GC0,
-logic__6618: VCU118RocketSystem__GC0,
-case__359: DCache,
-case__448: FPU__GB1,
-reg__294: RocketTile__GCB0,
-logic__5966: RocketTile__GCB0,
-logic__554: VCU118RocketSystem__GC0,
-logic__1047: VCU118RocketSystem__GC0,
-case__1470: tracking_wrapper,
-logic__6354: VCU118RocketSystem__GC0,
-reg__784: VCU118RocketSystem__GC0,
-case__1119: APBGpsBlock__GC0,
-logic__2984: FPU__GB2, FPU__GB1,
-case__49: VCU118RocketSystem__GC0,
-logic__1867: RocketTile__GCB0, DCache,
-logic__1251: VCU118RocketSystem__GC0,
-datapath__167: VCU118RocketSystem__GC0,
-reg__103: VCU118RocketSystem__GC0,
-logic__7325: VCU118RocketSystem__GC0,
-logic__1935: DCache,
-logic__6754: VCU118RocketSystem__GC0,
-logic__6923: VCU118RocketSystem__GC0,
-muxpart__34: FPU__GB0,
-counter__15: APBGpsBlock__GC0,
-logic__8171: APBGpsBlock__GC0,
-logic__203: VCU118RocketSystem__GC0,
-cordic_atan_basic__parameterized0: tracking_wrapper,
-logic__3608: FPU__GB1,
-logic__7570: VCU118RocketSystem__GC0,
-case__113: VCU118RocketSystem__GC0,
-reg__1180: tracking_wrapper,
-reg__942: VCU118RocketSystem__GC0,
-logic__6716: VCU118RocketSystem__GC0,
-logic__6018: RocketTile__GCB0,
-case__260: VCU118RocketSystem__GC0,
-logic__441: VCU118RocketSystem__GC0,
-reg__888: VCU118RocketSystem__GC0,
-case__380: RocketTile__GCB0,
-LF_code: tracking_wrapper,
-logic__1238: VCU118RocketSystem__GC0,
-logic__3350: FPU__GB2,
-logic__3753: FPU__GB1,
-datapath__510: VCU118RocketSystem__GC0,
-case__388: RocketTile__GCB0,
-logic__6028: RocketTile__GCB0,
-case__971: VCU118RocketSystem__GC0,
-case__216: VCU118RocketSystem__GC0,
-logic__7932: APBGpsBlock__GC0,
-logic__3309: FPU__GB2,
-logic__8700: tracking_wrapper,
-logic__4731: RocketTile__GCB0,
-logic__96: genesys2_rocket_top__GC0,
-reg__232: DCache,
-logic__3062: FPU__GB2,
-ram_2x78: VCU118RocketSystem__GC0,
-logic__5491: RocketTile__GCB0,
-counter__27: VCU118RocketSystem__GC0,
-logic__461: VCU118RocketSystem__GC0,
-case__1387: tracking_wrapper,
-logic__3772: FPU__GB1,
-logic__5374: RocketTile__GCB0,
-reg__999: APBGpsBlock__GC0,
-reg__1203: tracking_wrapper,
-reg__824: VCU118RocketSystem__GC0,
-reg__193: VCU118RocketSystem__GC0,
-logic__258: VCU118RocketSystem__GC0,
-case__364: DCache,
-logic__3705: FPU__GB1,
-reg__318: RocketTile__GCB0,
-logic__3998: FPU__GB2,
-logic__3504: FPU__GB2,
-logic__2834: FPU__GB1,
-reg__1208: tracking_wrapper,
-logic__8362: tracking_wrapper,
-logic__6518: VCU118RocketSystem__GC0,
-logic__5065: RocketTile__GCB0,
-logic__1641: DCache,
-reg__757: RocketTile__GCB0,
-logic__7461: VCU118RocketSystem__GC0,
-case__160: VCU118RocketSystem__GC0,
-logic__3532: FPU__GB1,
-muxpart__206: APBGpsBlock__GC0,
-reg__9: genesys2_rocket_top__GC0,
-reg__622: RocketTile__GCB0,
-reg__496: FPU__GB2,
-reg__65: VCU118RocketSystem__GC0,
-datapath__493: VCU118RocketSystem__GC0,
-logic__6895: VCU118RocketSystem__GC0,
-logic__1734: DCache,
-reg__1150: tracking_wrapper,
-case__44: VCU118RocketSystem__GC0,
-reg__1207: tracking_wrapper,
-datapath__111: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6166: VCU118RocketSystem__GC0,
-datapath__137: VCU118RocketSystem__GC0,
-logic__6917: VCU118RocketSystem__GC0,
-reg__1137: tracking_wrapper,
-logic__2133: DCache,
-logic__6797: VCU118RocketSystem__GC0,
-reg__590: RocketTile__GCB0,
-logic__2876: FPU__GB1,
-rom__4: APBGpsBlock__GC0,
-logic__7076: VCU118RocketSystem__GC0,
-logic__5255: RocketTile__GCB0,
-case__1400: tracking_wrapper,
-reg__1202: tracking_wrapper,
-logic__6090: VCU118RocketSystem__GC0,
-AsyncResetRegVec_w2_i0: VCU118RocketSystem__GC0,
-datapath__212: VCU118RocketSystem__GC0,
-reg__555: FPU__GB1,
-TLBuffer_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__8687: tracking_wrapper,
-logic__3129: FPU__GB2,
-reg__503: FPU__GB2,
-logic__8617: tracking_wrapper,
-reg__680: RocketTile__GCB0,
-logic__4827: RocketTile__GCB0,
-logic__3691: FPU__GB1,
-logic__3602: FPU__GB1,
-logic__6281: VCU118RocketSystem__GC0,
-logic__951: VCU118RocketSystem__GC0,
-logic__7554: VCU118RocketSystem__GC0,
-logic__1561: DCache,
-case__1028: VCU118RocketSystem__GC0,
-case__1086: APBGpsBlock__GC0,
-reg__768: RocketTile__GCB0,
-reg__106: VCU118RocketSystem__GC0,
-logic__8863: tracking_wrapper,
-logic__8920: APBGpsBlock__GC0,
-logic__2863: FPU__GB1,
-logic__7550: VCU118RocketSystem__GC0,
-case__949: VCU118RocketSystem__GC0,
-logic__4342: FPU__GB1,
-case__1040: VCU118RocketSystem__GC0,
-logic__7025: VCU118RocketSystem__GC0,
-logic__6144: VCU118RocketSystem__GC0,
-datapath__234: VCU118RocketSystem__GC0,
-case__1158: APBGpsBlock__GC0,
-logic__7408: VCU118RocketSystem__GC0,
-logic__7849: APBGpsBlock__GC0,
-case__1021: VCU118RocketSystem__GC0,
-reg__1057: APBGpsBlock__GC0,
-datapath__148: VCU118RocketSystem__GC0,
-datapath__70: VCU118RocketSystem__GC0,
-case__68: VCU118RocketSystem__GC0,
-case__674: RocketTile__GCB0,
-logic__393: VCU118RocketSystem__GC0,
-logic__3508: FPU__GB1,
-RocketALU: RocketTile__GCB0,
-logic__3911: FPU__GB2, FPU__GB1,
-reg__840: VCU118RocketSystem__GC0,
-reg__783: VCU118RocketSystem__GC0,
-logic__488: VCU118RocketSystem__GC0,
-logic__4933: RocketTile__GCB0,
-logic__1317: VCU118RocketSystem__GC0,
-logic__2457: RocketTile__GCB0,
-logic__6776: VCU118RocketSystem__GC0,
-case__1054: APBGpsBlock__GC0,
-case__1392: tracking_wrapper,
-reg__906: VCU118RocketSystem__GC0,
-reg__1085: APBGpsBlock__GC0,
-logic__2597: RocketTile__GCB0,
-logic__3669: FPU__GB1,
-case__582: FPU__GB1,
-logic__135: VCU118RocketSystem__GC0,
-reg__1311: tracking_wrapper,
-case__588: FPU__GB1,
-case__1516: tracking_wrapper,
-case__103: VCU118RocketSystem__GC0,
-case__1508: tracking_wrapper,
-logic__8811: tracking_wrapper,
-logic__4607: RocketTile__GCB0,
-logic__6248: VCU118RocketSystem__GC0,
-logic__1055: VCU118RocketSystem__GC0,
-PMAChecker: RocketTile__GCB0, DCache,
-case__662: RocketTile__GCB0,
-case__778: RocketTile__GCB0,
-datapath__28: VCU118RocketSystem__GC0,
-logic__2636: RocketTile__GCB0,
-case__701: RocketTile__GCB0,
-case__599: FPU__GB1,
-logic__2295: DCache,
-case__1531: TLToAPB,
-logic__2283: DCache,
-logic__2866: FPU__GB1,
-case__188: VCU118RocketSystem__GC0,
-logic__5013: RocketTile__GCB0,
-logic__3239: FPU__GB2,
-logic__1534: DCache,
-DivSqrtRawFN_small: FPU__GB2,
-datapath__406: RocketTile__GCB0,
-logic__6777: VCU118RocketSystem__GC0,
-reg__647: RocketTile__GCB0,
-TLAsyncCrossingSource_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__6898: VCU118RocketSystem__GC0,
-logic__3699: FPU__GB1,
-logic__1008: VCU118RocketSystem__GC0,
-logic__8014: APBGpsBlock__GC0,
-logic__6307: VCU118RocketSystem__GC0,
-logic__4400: FPU__GB1,
-case__1480: tracking_wrapper,
-logic__1452: RocketTile__GCB0,
-datapath__344: FPU__GB1,
-reg__1319: tracking_wrapper,
-dsp48e1__29: tracking_wrapper,
-logic__935: VCU118RocketSystem__GC0,
-datapath__584: APBGpsBlock__GC0,
-case__1358: tracking_wrapper,
-datapath__431: RocketTile__GCB0,
-logic__4825: RocketTile__GCB0,
-reg__856: VCU118RocketSystem__GC0,
-logic__8779: tracking_wrapper,
-logic__8922: APBGpsBlock__GC0,
-case__770: RocketTile__GCB0,
-datapath__484: VCU118RocketSystem__GC0,
-logic__8292: tracking_wrapper,
-reg__165: VCU118RocketSystem__GC0,
-logic__2906: FPU__GB1,
-case__1215: APBGpsBlock__GC0,
-logic__1033: VCU118RocketSystem__GC0,
-INToRecFN_1: FPU__GB2,
-datapath__88: VCU118RocketSystem__GC0,
-logic__6060: RocketTile__GCB0,
-logic__517: VCU118RocketSystem__GC0,
-counter: genesys2_rocket_top__GC0,
-logic__1401: VCU118RocketSystem__GC0,
-reg__501: FPU__GB2,
-logic__8114: APBGpsBlock__GC0,
-logic__323: VCU118RocketSystem__GC0,
-datapath__558: APBGpsBlock__GC0,
-case__375: RocketTile__GCB0,
-logic__6762: VCU118RocketSystem__GC0,
-logic__6671: VCU118RocketSystem__GC0,
-logic__6409: VCU118RocketSystem__GC0,
-logic__1506: DCache,
-reg__180: VCU118RocketSystem__GC0,
-datapath__640: tracking_wrapper,
-logic__2682: FPU__GB1,
-logic__2781: FPU__GB1,
-datapath__125: VCU118RocketSystem__GC0,
-datapath__104: VCU118RocketSystem__GC0,
-case__641: RocketTile__GCB0,
-datapath__375: FPU__GB2,
-logic__1: genesys2_rocket_top__GC0,
-case__165: VCU118RocketSystem__GC0,
-logic__4282: FPU__GB1,
-divider: tracking_wrapper,
-logic__2623: RocketTile__GCB0,
-logic__8560: tracking_wrapper,
-case__1417: tracking_wrapper,
-reg__1152: tracking_wrapper,
-logic__660: VCU118RocketSystem__GC0,
-case__177: VCU118RocketSystem__GC0,
-datapath__274: RocketTile__GCB0,
-muxpart__47: FPU__GB0,
-logic__3866: FPU__GB2, FPU__GB1,
-mult_66_66_66: RocketTile__GCB0,
-reg__1118: APBGpsBlock__GC0,
-logic__6792: VCU118RocketSystem__GC0,
-logic__6653: VCU118RocketSystem__GC0,
-logic__6580: VCU118RocketSystem__GC0,
-logic__2796: FPU__GB1,
-muxpart__2: genesys2_rocket_top__GC0,
-reg__864: VCU118RocketSystem__GC0,
-logic__8371: tracking_wrapper,
-logic__1446: RocketTile__GCB0,
-logic__8754: tracking_wrapper,
-logic__688: VCU118RocketSystem__GC0,
-logic__7565: VCU118RocketSystem__GC0,
-case__150: VCU118RocketSystem__GC0,
-logic__341: VCU118RocketSystem__GC0,
-logic__7688: APBGpsBlock__GC0,
-logic__756: VCU118RocketSystem__GC0,
-logic__5691: RocketTile__GCB0,
-logic__8816: tracking_wrapper,
-logic__7109: VCU118RocketSystem__GC0,
-logic__4903: RocketTile__GCB0,
-reg__191: VCU118RocketSystem__GC0,
-muxpart__94: RocketTile__GCB0,
-reg__208: VCU118RocketSystem__GC0,
-logic__3843: FPU__GB1,
-reg__527: FPU__GB1,
-logic__5685: RocketTile__GCB0,
-logic__1993: DCache,
-logic__7280: VCU118RocketSystem__GC0,
-datapath__335: FPU__GB2,
-reg__770: RocketTile__GCB0,
-case__1276: APBGpsBlock__GC0,
-logic__4444: FPU__GB1,
-logic__6188: VCU118RocketSystem__GC0,
-logic__771: VCU118RocketSystem__GC0,
-logic__6125: VCU118RocketSystem__GC0,
-logic__3424: FPU__GB2,
-reg__1129: tracking_wrapper,
-logic__7121: VCU118RocketSystem__GC0,
-logic__6150: VCU118RocketSystem__GC0,
-reg__1212: tracking_wrapper,
-case__218: VCU118RocketSystem__GC0,
-logic__5518: RocketTile__GCB0,
-logic__3771: FPU__GB1,
-logic__5313: RocketTile__GCB0,
-logic__3995: FPU__GB2,
-logic__7626: VCU118RocketSystem__GC0,
-reg__389: FPU__GB0,
-logic__8421: tracking_wrapper,
-logic__1977: DCache,
-logic__1917: DCache,
-case__583: FPU__GB1,
-reg__704: RocketTile__GCB0,
-reg__877: VCU118RocketSystem__GC0,
-logic__1262: VCU118RocketSystem__GC0,
-reg__52: VCU118RocketSystem__GC0,
-case__1407: tracking_wrapper,
-logic__3273: FPU__GB2,
-case__326: DCache,
-logic__6922: VCU118RocketSystem__GC0,
-logic__1831: RocketTile__GCB0, DCache,
-reg__755: RocketTile__GCB0,
-reg__607: RocketTile__GCB0,
-logic__6503: VCU118RocketSystem__GC0,
-datapath__91: VCU118RocketSystem__GC0,
-logic__2865: FPU__GB1,
-muxpart__232: tracking_wrapper,
-case__539: FPU__GB2,
-sample_align: APBGpsBlock__GC0,
-logic__4505: RocketTile__GCB0,
-logic__2130: DCache,
-logic__2405: RocketTile__GCB0,
-muxpart__192: APBGpsBlock__GC0,
-counter__7: APBGpsBlock__GC0,
-logic__1841: RocketTile__GCB0, DCache,
-logic__5337: RocketTile__GCB0,
-case__965: VCU118RocketSystem__GC0,
-ClockSinkDomain: VCU118RocketSystem__GC0,
-logic__4320: FPU__GB1,
-case__841: VCU118RocketSystem__GC0,
-logic__5524: RocketTile__GCB0,
-logic__7528: VCU118RocketSystem__GC0,
-datapath__228: VCU118RocketSystem__GC0,
-case__361: DCache,
-case__414: RocketTile__GCB0,
-case__84: VCU118RocketSystem__GC0,
-logic__191: VCU118RocketSystem__GC0,
-logic__5238: RocketTile__GCB0,
-TLError_1: VCU118RocketSystem__GC0,
-reg__1254: tracking_wrapper,
-case__912: VCU118RocketSystem__GC0,
-case__1051: APBGpsBlock__GC0,
-logic__2168: DCache,
-datapath__401: RocketTile__GCB0,
-logic__4018: FPU__GB2,
-logic__7645: VCU118RocketSystem__GC0,
-logic__1021: VCU118RocketSystem__GC0,
-logic__6573: VCU118RocketSystem__GC0,
-reg__932: VCU118RocketSystem__GC0,
-case__1017: VCU118RocketSystem__GC0,
-logic__8551: tracking_wrapper,
-case__1267: APBGpsBlock__GC0,
-case__390: RocketTile__GCB0,
-logic__8572: tracking_wrapper,
-logic__4896: RocketTile__GCB0,
-case__1293: APBGpsBlock__GC0,
-datapath__688: tracking_wrapper,
-logic__6014: RocketTile__GCB0,
-case__1035: VCU118RocketSystem__GC0,
-logic__512: VCU118RocketSystem__GC0,
-reg__621: RocketTile__GCB0,
-reg__599: RocketTile__GCB0,
-reg__1138: tracking_wrapper,
-case__934: VCU118RocketSystem__GC0,
-logic__1107: VCU118RocketSystem__GC0,
-reg__1168: tracking_wrapper,
-reg__396: FPU__GB0,
-logic__2392: RocketTile__GCB0,
-logic__6935: VCU118RocketSystem__GC0,
-logic__6786: VCU118RocketSystem__GC0,
-logic__1151: VCU118RocketSystem__GC0,
-case__988: VCU118RocketSystem__GC0,
-logic__1370: VCU118RocketSystem__GC0,
-logic__3700: FPU__GB1,
-logic__291: VCU118RocketSystem__GC0,
-logic__1170: VCU118RocketSystem__GC0,
-case__200: VCU118RocketSystem__GC0,
-reg__1104: APBGpsBlock__GC0,
-logic__8378: tracking_wrapper,
-logic__8441: tracking_wrapper,
-counter__9: APBGpsBlock__GC0,
-logic__4817: RocketTile__GCB0,
-reg__460: FPU__GB1,
-logic__5679: RocketTile__GCB0,
-logic__5283: RocketTile__GCB0,
-TLDebugModule: VCU118RocketSystem__GC0,
-logic__6426: VCU118RocketSystem__GC0,
-logic__2524: RocketTile__GCB0,
-case__468: FPU__GB2,
-case__433: RocketTile__GCB0,
-case__410: RocketTile__GCB0,
-logic__8130: APBGpsBlock__GC0,
-logic__5487: RocketTile__GCB0,
-case__942: VCU118RocketSystem__GC0,
-reg__1338: tracking_wrapper,
-logic__8695: tracking_wrapper,
-logic__4778: RocketTile__GCB0,
-logic__5476: RocketTile__GCB0,
-logic__2347: RocketTile__GCB0,
-logic__8909: APBGpsBlock__GC0,
-reg__961: VCU118RocketSystem__GC0,
-logic__3472: FPU__GB2,
-logic__7298: VCU118RocketSystem__GC0,
-logic__8934: TLToAPB,
-case__349: DCache,
-counter__13: APBGpsBlock__GC0,
-logic__4414: FPU__GB1,
-logic__7223: VCU118RocketSystem__GC0,
-reg__532: FPU__GB1,
-logic__2904: FPU__GB1,
-logic__6818: VCU118RocketSystem__GC0,
-case__77: VCU118RocketSystem__GC0,
-case__1485: tracking_wrapper,
-reg__115: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__1402: VCU118RocketSystem__GC0,
-logic__3822: FPU__GB1,
-logic__4210: FPU__GB2,
-case__527: FPU__GB2, FPU__GB1,
-logic__7133: VCU118RocketSystem__GC0,
-reg__865: VCU118RocketSystem__GC0,
-reg__1287: tracking_wrapper,
-logic__6299: VCU118RocketSystem__GC0,
-logic__5437: RocketTile__GCB0,
-Arbiter3_LLWB: RocketTile__GCB0,
-reg__1239: tracking_wrapper,
-logic__4468: FPU__GB1,
-logic__2081: DCache,
-logic__6223: VCU118RocketSystem__GC0,
-case__183: VCU118RocketSystem__GC0,
-logic__3897: FPU__GB2, FPU__GB1,
-logic__4172: FPU__GB2,
-reg__851: VCU118RocketSystem__GC0,
-case__1507: tracking_wrapper,
-reg__121: VCU118RocketSystem__GC0,
-logic__6986: VCU118RocketSystem__GC0,
-logic__942: VCU118RocketSystem__GC0,
-case__1483: tracking_wrapper,
-logic__7389: VCU118RocketSystem__GC0,
-logic__5490: RocketTile__GCB0,
-case__419: RocketTile__GCB0,
-logic__6654: VCU118RocketSystem__GC0,
-reg__723: RocketTile__GCB0,
-case__469: FPU__GB2,
-logic__6800: VCU118RocketSystem__GC0,
-muxpart__73: FPU__GB0,
-counter__18: tracking_wrapper,
-logic__3997: FPU__GB2,
-logic__887: VCU118RocketSystem__GC0,
-logic__7443: VCU118RocketSystem__GC0,
-muxpart__85: FPU__GB0,
-logic__5274: RocketTile__GCB0,
-logic__7291: VCU118RocketSystem__GC0,
-reg__823: VCU118RocketSystem__GC0,
-reg__863: VCU118RocketSystem__GC0,
-reg__1232: tracking_wrapper,
-case__289: RocketTile__GCB0,
-logic__7222: VCU118RocketSystem__GC0,
-logic__4145: FPU__GB2,
-logic__5863: RocketTile__GCB0,
-logic__867: VCU118RocketSystem__GC0,
-case__209: VCU118RocketSystem__GC0,
-logic__4080: FPU__GB2,
-reg__1238: tracking_wrapper,
-reg__1113: APBGpsBlock__GC0,
-reg__662: RocketTile__GCB0,
-PeripheryBus_pbus: VCU118RocketSystem__GC0,
-datapath__430: RocketTile__GCB0,
-reg__73: VCU118RocketSystem__GC0,
-logic__6331: VCU118RocketSystem__GC0,
-reg__339: RocketTile__GCB0,
-logic__6545: VCU118RocketSystem__GC0,
-datapath__243: DCache,
-reg__361: RocketTile__GCB0,
-Queue2_TLBundleD_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__1430: RocketTile__GCB0,
-reg__1267: tracking_wrapper,
-logic__3171: FPU__GB2,
-reg__395: FPU__GB0,
-logic__1363: VCU118RocketSystem__GC0,
-logic__3494: FPU__GB2,
-case__795: VCU118RocketSystem__GC0,
-logic__3969: FPU__GB2, FPU__GB1,
-logic__6881: VCU118RocketSystem__GC0,
-logic__1394: VCU118RocketSystem__GC0,
-logic__5664: RocketTile__GCB0,
-logic__1579: DCache,
-datapath__538: APBGpsBlock__GC0,
-logic__5259: RocketTile__GCB0,
-logic__4729: RocketTile__GCB0,
-logic__4545: RocketTile__GCB0,
-reg__72: VCU118RocketSystem__GC0,
-reg__602: RocketTile__GCB0,
-logic__8379: tracking_wrapper,
-reg__751: RocketTile__GCB0,
-logic__6726: VCU118RocketSystem__GC0,
-logic__2233: DCache,
-case__762: RocketTile__GCB0,
-datapath__485: VCU118RocketSystem__GC0,
-case__1133: APBGpsBlock__GC0,
-datapath__506: VCU118RocketSystem__GC0,
-logic__667: VCU118RocketSystem__GC0,
-reg__146: VCU118RocketSystem__GC0,
-case__573: FPU__GB1,
-case__1126: APBGpsBlock__GC0,
-logic__3823: FPU__GB1,
-datapath__239: DCache,
-reg__826: VCU118RocketSystem__GC0,
-logic__587: VCU118RocketSystem__GC0,
-logic__2969: FPU__GB2, FPU__GB1,
-datapath__46: VCU118RocketSystem__GC0,
-reg__443: FPU__GB2,
-case__294: RocketTile__GCB0,
-DivSqrtRecFN_small: FPU__GB2,
-case__153: VCU118RocketSystem__GC0,
-logic__1762: DCache,
-logic__4093: FPU__GB2,
-case__1503: tracking_wrapper,
-logic__6574: VCU118RocketSystem__GC0,
-case__1289: APBGpsBlock__GC0,
-logic__2608: RocketTile__GCB0,
-reg__924: VCU118RocketSystem__GC0,
-reg__275: DCache,
-case__839: VCU118RocketSystem__GC0,
-case__225: VCU118RocketSystem__GC0,
-logic__2092: DCache,
-logic__6631: VCU118RocketSystem__GC0,
-logic__3232: FPU__GB2,
-logic__5499: RocketTile__GCB0,
-logic__6724: VCU118RocketSystem__GC0,
-logic__6379: VCU118RocketSystem__GC0,
-logic__229: VCU118RocketSystem__GC0,
-logic__6158: VCU118RocketSystem__GC0,
-Arbiter2_Valid_PTWReq: RocketTile__GCB0,
-logic__3758: FPU__GB1,
-logic__7274: VCU118RocketSystem__GC0,
-logic__2839: FPU__GB1,
-case__566: FPU__GB2,
-reg__838: VCU118RocketSystem__GC0,
-logic__3913: FPU__GB2, FPU__GB1,
-logic__4398: FPU__GB1,
-reg__283: DCache,
-logic__2603: RocketTile__GCB0,
-logic__4733: RocketTile__GCB0,
-logic__6181: VCU118RocketSystem__GC0,
-reg__388: FPU__GB0,
-logic__4140: FPU__GB2,
-reg__952: VCU118RocketSystem__GC0,
-logic__6396: VCU118RocketSystem__GC0,
-case__578: FPU__GB2,
-logic__6781: VCU118RocketSystem__GC0,
-case__1061: APBGpsBlock__GC0,
-logic__1022: VCU118RocketSystem__GC0,
-datapath__130: VCU118RocketSystem__GC0,
-logic__3271: FPU__GB2,
-ClockGroupAggregator_aggregator: VCU118RocketSystem__GC0,
-datapath__414: RocketTile__GCB0,
-logic__8723: tracking_wrapper,
-logic__7145: VCU118RocketSystem__GC0,
-logic__2624: RocketTile__GCB0,
-datapath__486: VCU118RocketSystem__GC0,
-logic__245: VCU118RocketSystem__GC0,
-logic__4572: RocketTile__GCB0,
-logic__3057: FPU__GB2,
-reg__476: FPU__GB1,
-logic__6349: VCU118RocketSystem__GC0,
-logic__2903: FPU__GB1,
-case__686: RocketTile__GCB0,
-reg__666: RocketTile__GCB0,
-reg__90: VCU118RocketSystem__GC0,
-logic__141: VCU118RocketSystem__GC0,
-logic__1662: DCache,
-logic__224: VCU118RocketSystem__GC0,
-logic__3668: FPU__GB1,
-reg__1228: tracking_wrapper,
-case__1222: APBGpsBlock__GC0,
-reg__1322: tracking_wrapper,
-logic__1500: DCache,
-TLInterconnectCoupler_pbus_to_fpga_uart: VCU118RocketSystem__GC0,
-case__336: DCache,
-logic__6594: VCU118RocketSystem__GC0,
-logic__2784: FPU__GB1,
-case__721: RocketTile__GCB0,
-logic__101: genesys2_rocket_top__GC0,
-logic__4128: FPU__GB2,
-case__1305: APBGpsBlock__GC0,
-logic__6169: VCU118RocketSystem__GC0,
-reg__30: VCU118RocketSystem__GC0,
-logic__5033: RocketTile__GCB0,
-reg__189: VCU118RocketSystem__GC0,
-logic__4112: FPU__GB2,
-reg__85: VCU118RocketSystem__GC0,
-muxpart__21: FPU__GB0,
-logic__3836: FPU__GB1,
-logic__6805: VCU118RocketSystem__GC0,
-case__126: VCU118RocketSystem__GC0,
-RecFNToIN_1: FPU__GB2,
-AMOALU: DCache,
-reg__351: RocketTile__GCB0,
-case__30: VCU118RocketSystem__GC0,
-logic__1525: DCache,
-logic__7673: APBGpsBlock__GC0,
-logic__4283: FPU__GB1,
-reg__717: RocketTile__GCB0,
-reg__1337: tracking_wrapper,
-reg__558: FPU__GB1,
-reg__884: VCU118RocketSystem__GC0,
-reg__147: VCU118RocketSystem__GC0,
-logic__1000: VCU118RocketSystem__GC0,
-case__1280: APBGpsBlock__GC0,
-logic__3781: FPU__GB1,
-muxpart__65: FPU__GB0,
-reg__626: RocketTile__GCB0,
-logic__3145: FPU__GB2,
-dsp48e1__43: tracking_wrapper,
-case__1430: tracking_wrapper,
-case__426: RocketTile__GCB0,
-case__307: DCache,
-datapath__386: FPU__GB1,
-logic__836: VCU118RocketSystem__GC0,
-case__537: FPU__GB2,
-case__619: RocketTile__GCB0,
-logic__6720: VCU118RocketSystem__GC0,
-logic__6397: VCU118RocketSystem__GC0,
-reg__1317: tracking_wrapper,
-reg__627: RocketTile__GCB0,
-logic__1086: VCU118RocketSystem__GC0,
-datapath__292: FPU__GB1,
-logic__3767: FPU__GB1,
-logic__6374: VCU118RocketSystem__GC0,
-logic__6504: VCU118RocketSystem__GC0,
-reg__694: RocketTile__GCB0,
-case__620: RocketTile__GCB0,
-datapath__605: APBGpsBlock__GC0,
-case__1321: APBGpsBlock__GC0,
-logic__553: VCU118RocketSystem__GC0,
-case__314: DCache,
-reg__261: DCache,
-case__969: VCU118RocketSystem__GC0,
-reg__79: VCU118RocketSystem__GC0,
-reg__1037: APBGpsBlock__GC0,
-logic__6856: VCU118RocketSystem__GC0,
-case__112: VCU118RocketSystem__GC0,
-reg__424: FPU__GB1,
-TLFragmenter_1: RocketTile__GCB0,
-logic__479: VCU118RocketSystem__GC0,
-logic__848: VCU118RocketSystem__GC0,
-TLBuffer_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-muxpart__19: FPU__GB0,
-logic__6163: VCU118RocketSystem__GC0,
-reg__458: FPU__GB1,
-counter__14: APBGpsBlock__GC0,
-case__717: RocketTile__GCB0,
-reg__540: FPU__GB1,
-case__832: VCU118RocketSystem__GC0,
-TLFragmenter_PLIC: VCU118RocketSystem__GC0,
-datapath__136: VCU118RocketSystem__GC0,
-logic__5909: RocketTile__GCB0,
-logic__4385: FPU__GB1,
-logic__3430: FPU__GB2,
-logic__267: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__1269: tracking_wrapper,
-case__1297: APBGpsBlock__GC0,
-case__1377: tracking_wrapper,
-logic__5989: RocketTile__GCB0,
-datapath__87: VCU118RocketSystem__GC0,
-logic__6067: RocketTile__GCB0,
-logic__6980: VCU118RocketSystem__GC0,
-reg__1236: tracking_wrapper,
-logic__5312: RocketTile__GCB0,
-logic__3921: FPU__GB2, FPU__GB1,
-logic__2426: RocketTile__GCB0,
-muxpart__230: tracking_wrapper,
-logic__4141: FPU__GB2,
-logic__6256: VCU118RocketSystem__GC0,
-logic__632: VCU118RocketSystem__GC0,
-reg__985: VCU118RocketSystem__GC0,
-logic__2060: DCache,
-logic__3375: FPU__GB2,
-TLFragmenter_FPGAGPS: VCU118RocketSystem__GC0,
-case__1269: APBGpsBlock__GC0,
-logic__6007: RocketTile__GCB0,
-case__238: VCU118RocketSystem__GC0,
-logic__8502: tracking_wrapper,
-case__282: VCU118RocketSystem__GC0,
-reg__718: RocketTile__GCB0,
-datapath__312: FPU__GB2,
-case__510: FPU__GB1,
-logic__4196: FPU__GB2,
-reg__1151: tracking_wrapper,
-datapath__354: FPU__GB1,
-reg__229: RocketTile__GCB0,
-logic__569: VCU118RocketSystem__GC0,
-logic__2688: FPU__GB1,
-logic__8552: tracking_wrapper,
-case__344: DCache,
-case__625: RocketTile__GCB0,
-reg__839: VCU118RocketSystem__GC0,
-reg__1316: tracking_wrapper,
-datapath__268: RocketTile__GCB0,
-reg__873: VCU118RocketSystem__GC0,
-logic__4763: RocketTile__GCB0,
-reg__214: VCU118RocketSystem__GC0,
-logic__5208: RocketTile__GCB0,
-logic__7619: VCU118RocketSystem__GC0,
-AsyncQueueSource_DebugInternalBundle: VCU118RocketSystem__GC0,
-case__94: VCU118RocketSystem__GC0,
-reg__693: RocketTile__GCB0,
-comp_mult: APBGpsBlock__GC0,
-logic__1381: VCU118RocketSystem__GC0,
-reg__640: RocketTile__GCB0,
-logic__2097: DCache,
-reg__1296: tracking_wrapper,
-logic__6646: VCU118RocketSystem__GC0,
-case__131: VCU118RocketSystem__GC0,
-datapath__388: FPU__GB1,
-logic__8331: tracking_wrapper,
-logic__1277: VCU118RocketSystem__GC0,
-logic__2057: DCache,
-reg__633: RocketTile__GCB0,
-reg__837: VCU118RocketSystem__GC0,
-datapath__327: FPU__GB2,
-reg__404: FPU__GB1,
-case__1510: tracking_wrapper,
-logic__3667: FPU__GB1,
-case__1538: TLToAPB,
-logic__4759: RocketTile__GCB0,
-case__749: RocketTile__GCB0,
-logic__7375: VCU118RocketSystem__GC0,
-case__211: VCU118RocketSystem__GC0,
-logic__5210: RocketTile__GCB0,
-logic__334: VCU118RocketSystem__GC0,
-logic__4812: RocketTile__GCB0,
-logic__4003: FPU__GB2,
-logic__21: genesys2_rocket_top__GC0,
-logic__7387: VCU118RocketSystem__GC0,
-logic__6185: VCU118RocketSystem__GC0,
-case__226: VCU118RocketSystem__GC0,
-logic__1044: VCU118RocketSystem__GC0,
-reg__1172: tracking_wrapper,
-logic__2054: DCache,
-logic__7825: APBGpsBlock__GC0,
-logic__330: VCU118RocketSystem__GC0,
-datapath__97: VCU118RocketSystem__GC0,
-logic__4810: RocketTile__GCB0,
-datapath__220: VCU118RocketSystem__GC0,
-logic__5485: RocketTile__GCB0,
-logic__7911: APBGpsBlock__GC0,
-logic__7536: VCU118RocketSystem__GC0,
-case__852: VCU118RocketSystem__GC0,
-reg__542: FPU__GB1,
-reg__69: VCU118RocketSystem__GC0,
-reg__1024: APBGpsBlock__GC0,
-datapath__603: APBGpsBlock__GC0,
-case__54: VCU118RocketSystem__GC0,
-case__43: VCU118RocketSystem__GC0,
-case__403: RocketTile__GCB0,
-logic__1009: VCU118RocketSystem__GC0,
-logic__3435: FPU__GB2,
-logic__1442: RocketTile__GCB0,
-case__1010: VCU118RocketSystem__GC0,
-logic__2134: DCache,
-logic__6283: VCU118RocketSystem__GC0,
-case__145: VCU118RocketSystem__GC0,
-logic__3946: FPU__GB2, FPU__GB1,
-logic__3244: FPU__GB2,
-case__1136: APBGpsBlock__GC0,
-case__1527: APBGpsBlock__GC0,
-logic__2465: RocketTile__GCB0,
-logic__2035: DCache,
-muxpart__18: FPU__GB0,
-case__618: RocketTile__GCB0,
-logic__4692: RocketTile__GCB0,
-reg__290: RocketTile__GCB0,
-case__1233: APBGpsBlock__GC0,
-case__132: VCU118RocketSystem__GC0,
-logic__5196: RocketTile__GCB0,
-reg__338: RocketTile__GCB0,
-logic__1403: VCU118RocketSystem__GC0,
-reg__419: FPU__GB1,
-case__682: RocketTile__GCB0,
-logic__1140: VCU118RocketSystem__GC0,
-logic__4900: RocketTile__GCB0,
-logic__4718: RocketTile__GCB0,
-case__231: VCU118RocketSystem__GC0,
-logic__105: VCU118RocketSystem__GC0,
-case__267: VCU118RocketSystem__GC0,
-logic__6566: VCU118RocketSystem__GC0,
-case__808: VCU118RocketSystem__GC0,
-logic__1125: VCU118RocketSystem__GC0,
-reg__411: FPU__GB1,
-logic__4898: RocketTile__GCB0,
-logic__5034: RocketTile__GCB0,
-reg__1213: tracking_wrapper,
-logic__2867: FPU__GB1,
-logic__1288: VCU118RocketSystem__GC0,
-logic__6072: RocketTile__GCB0,
-logic__7063: VCU118RocketSystem__GC0,
-logic__8778: tracking_wrapper,
-reg__737: RocketTile__GCB0,
-logic__5328: RocketTile__GCB0,
-case__81: VCU118RocketSystem__GC0,
-logic__2294: DCache,
-logic__5910: RocketTile__GCB0,
-datapath__54: VCU118RocketSystem__GC0,
-logic__5376: RocketTile__GCB0,
-logic__5635: RocketTile__GCB0,
-case__1016: VCU118RocketSystem__GC0,
-case__1102: APBGpsBlock__GC0,
-case__522: FPU__GB2, FPU__GB1,
-logic__6647: VCU118RocketSystem__GC0,
-case__55: VCU118RocketSystem__GC0,
-reg__169: VCU118RocketSystem__GC0,
-logic__85: genesys2_rocket_top__GC0,
-logic__3966: FPU__GB2, FPU__GB1,
-case__986: VCU118RocketSystem__GC0,
-case__93: VCU118RocketSystem__GC0,
-reg__320: RocketTile__GCB0,
-reg__251: DCache,
-reg__561: FPU__GB1,
-logic__5937: RocketTile__GCB0,
-ram_2x120: VCU118RocketSystem__GC0,
-logic__4042: FPU__GB2,
-logic__6120: VCU118RocketSystem__GC0,
-logic__3557: FPU__GB1,
-case__65: VCU118RocketSystem__GC0,
-case__1096: APBGpsBlock__GC0,
-reg__772: TilePRCIDomain__GC0,
-logic__2036: DCache,
-reg__143: VCU118RocketSystem__GC0,
-logic__1415: RocketTile__GCB0,
-logic__4884: RocketTile__GCB0,
-logic__6510: VCU118RocketSystem__GC0,
-datapath__149: VCU118RocketSystem__GC0,
-logic__5410: RocketTile__GCB0,
-logic__4573: RocketTile__GCB0,
-logic__8591: tracking_wrapper,
-logic__1956: DCache,
-reg__850: VCU118RocketSystem__GC0,
-reg__830: VCU118RocketSystem__GC0,
-reg__123: VCU118RocketSystem__GC0,
-logic__2141: DCache,
-case__199: VCU118RocketSystem__GC0,
-logic__3442: FPU__GB2,
-case__501: FPU__GB1,
-logic__8235: tracking_wrapper,
-logic__6075: TilePRCIDomain__GC0,
-reg__186: VCU118RocketSystem__GC0,
-reg__285: DCache,
-reg__1007: APBGpsBlock__GC0,
-datapath__653: tracking_wrapper,
-logic__8813: tracking_wrapper,
-reg__529: FPU__GB1,
-reg__1051: APBGpsBlock__GC0,
-case__853: VCU118RocketSystem__GC0,
-logic__6258: VCU118RocketSystem__GC0,
-case__1324: APBGpsBlock__GC0,
-logic__779: VCU118RocketSystem__GC0,
-case__91: VCU118RocketSystem__GC0,
-reg__1288: tracking_wrapper,
-case__831: VCU118RocketSystem__GC0,
-case__358: DCache,
-ifft_abs_sqr: APBGpsBlock__GC0,
-reg__975: VCU118RocketSystem__GC0,
-IntSyncCrossingSource_n1x1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__3936: FPU__GB2, FPU__GB1,
-logic__2928: FPU__GB1,
-logic__4420: FPU__GB1,
-reg__878: VCU118RocketSystem__GC0,
-logic__4159: FPU__GB2,
-counter__17: APBGpsBlock__GC0,
-logic__5515: RocketTile__GCB0,
-datapath__340: FPU__GB1,
-case__487: FPU__GB2,
-logic__7255: VCU118RocketSystem__GC0,
-logic__1631: DCache,
-case__280: VCU118RocketSystem__GC0,
-logic__999: VCU118RocketSystem__GC0,
-reg__1071: APBGpsBlock__GC0,
-logic__8770: tracking_wrapper,
-reg__1134: tracking_wrapper,
-logic__4899: RocketTile__GCB0,
-logic__1637: DCache,
-datapath__272: RocketTile__GCB0,
-logic__2640: RocketTile__GCB0,
-logic__3709: FPU__GB1,
-reg__976: VCU118RocketSystem__GC0,
-reg__379: FPU__GB0,
-case__675: RocketTile__GCB0,
-case__1026: VCU118RocketSystem__GC0,
-logic__7256: VCU118RocketSystem__GC0,
-logic__6663: VCU118RocketSystem__GC0,
-case__172: VCU118RocketSystem__GC0,
-case__108: VCU118RocketSystem__GC0,
-reg__798: VCU118RocketSystem__GC0,
-logic__7772: APBGpsBlock__GC0,
-logic__7024: VCU118RocketSystem__GC0,
-logic__3851: FPU__GB1,
-reg__660: RocketTile__GCB0,
-logic__5506: RocketTile__GCB0,
-case__791: VCU118RocketSystem__GC0,
-reg__1246: tracking_wrapper,
-datapath__31: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a12d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__3917: FPU__GB2, FPU__GB1,
-logic__2987: FPU__GB2, FPU__GB1,
-rom__6: tracking_wrapper,
-logic__4878: RocketTile__GCB0,
-case__842: VCU118RocketSystem__GC0,
-logic__910: VCU118RocketSystem__GC0,
-logic__6733: VCU118RocketSystem__GC0,
-logic__7030: VCU118RocketSystem__GC0,
-case__792: VCU118RocketSystem__GC0,
-logic__2451: RocketTile__GCB0,
-case__1326: APBGpsBlock__GC0,
-logic__6761: VCU118RocketSystem__GC0,
-reg__780: VCU118RocketSystem__GC0,
-logic__7292: VCU118RocketSystem__GC0,
-logic__6048: RocketTile__GCB0,
-logic__4153: FPU__GB2,
-case__1306: APBGpsBlock__GC0,
-logic__6194: VCU118RocketSystem__GC0,
-datapath__467: VCU118RocketSystem__GC0,
-logic__4587: RocketTile__GCB0,
-logic__1258: VCU118RocketSystem__GC0,
-case__1351: tracking_wrapper,
-logic__5292: RocketTile__GCB0,
-logic__6254: VCU118RocketSystem__GC0,
-logic__932: VCU118RocketSystem__GC0,
-logic__591: VCU118RocketSystem__GC0,
-datapath__47: VCU118RocketSystem__GC0,
-logic__7525: VCU118RocketSystem__GC0,
-logic__6333: VCU118RocketSystem__GC0,
-counter__11: APBGpsBlock__GC0,
-logic__6880: VCU118RocketSystem__GC0,
-reg__343: RocketTile__GCB0,
-logic__469: VCU118RocketSystem__GC0,
-logic__6192: VCU118RocketSystem__GC0,
-datapath__89: VCU118RocketSystem__GC0,
-reg__1289: tracking_wrapper,
-logic__4069: FPU__GB2,
-logic__8766: tracking_wrapper,
-datapath__320: FPU__GB2,
-logic__305: VCU118RocketSystem__GC0,
-logic__3828: FPU__GB1,
-logic__6804: VCU118RocketSystem__GC0,
-case__634: RocketTile__GCB0,
-case__637: RocketTile__GCB0,
-reg__925: VCU118RocketSystem__GC0,
-logic__6191: VCU118RocketSystem__GC0,
-logic__6469: VCU118RocketSystem__GC0,
-logic__6477: VCU118RocketSystem__GC0,
-datapath__523: APBGpsBlock__GC0,
-reg__1159: tracking_wrapper,
-case__1029: VCU118RocketSystem__GC0,
-reg__911: VCU118RocketSystem__GC0,
-case__254: VCU118RocketSystem__GC0,
-logic__2002: DCache,
-reg__658: RocketTile__GCB0,
-logic__5505: RocketTile__GCB0,
-case__1460: tracking_wrapper,
-case__968: VCU118RocketSystem__GC0,
-logic__262: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-fft_radix_2__parameterized1: APBGpsBlock__GC0,
-case__278: VCU118RocketSystem__GC0,
-reg__219: VCU118RocketSystem__GC0,
-datapath__238: RocketTile__GCB0,
-reg__858: VCU118RocketSystem__GC0,
-reg__386: FPU__GB0,
-PLICClockSinkDomain: VCU118RocketSystem__GC0,
-datapath__176: VCU118RocketSystem__GC0,
-reg__62: VCU118RocketSystem__GC0,
-logic__2572: RocketTile__GCB0,
-reg__441: FPU__GB2,
-logic__8739: tracking_wrapper,
-logic__8941: TLToAPB,
-logic__916: VCU118RocketSystem__GC0,
-logic__1491: RocketTile__GCB0,
-reg__1070: APBGpsBlock__GC0,
-logic__7680: APBGpsBlock__GC0,
-case__1008: VCU118RocketSystem__GC0,
-logic__6570: VCU118RocketSystem__GC0,
-case__549: FPU__GB2,
-logic__1228: VCU118RocketSystem__GC0,
-DivSqrtRecFNToRaw_small_1: FPU__GB2,
-case__826: VCU118RocketSystem__GC0,
-reg__113: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__495: FPU__GB2,
-case__623: RocketTile__GCB0,
-reg__394: FPU__GB0,
-logic__3137: FPU__GB2,
-case__272: VCU118RocketSystem__GC0,
-logic__1171: VCU118RocketSystem__GC0,
-case__1484: tracking_wrapper,
-datapath__553: APBGpsBlock__GC0,
-case__186: VCU118RocketSystem__GC0,
-datapath__412: RocketTile__GCB0,
-reg__1008: APBGpsBlock__GC0,
-datapath__478: VCU118RocketSystem__GC0,
-reg__196: VCU118RocketSystem__GC0,
-logic__987: VCU118RocketSystem__GC0,
-logic__8956: TLToAPB,
-case__373: RocketTile__GCB0,
-logic__201: VCU118RocketSystem__GC0,
-logic__3475: FPU__GB2,
-logic__4672: RocketTile__GCB0,
-logic__1428: RocketTile__GCB0,
-logic__4481: FPU__GB1,
-logic__4951: RocketTile__GCB0,
-case__92: VCU118RocketSystem__GC0,
-reg__465: FPU__GB1,
-logic__4028: FPU__GB2,
-logic__8155: APBGpsBlock__GC0,
-logic__2013: DCache,
-logic__4920: RocketTile__GCB0,
-logic__7969: APBGpsBlock__GC0,
-reg__711: RocketTile__GCB0,
-case__984: VCU118RocketSystem__GC0,
-logic__8709: tracking_wrapper,
-case__1164: APBGpsBlock__GC0,
-SynchronizerShiftReg_w1_d3: TilePRCIDomain__GC0,
-logic__4901: RocketTile__GCB0,
-logic__775: VCU118RocketSystem__GC0,
-logic__7490: VCU118RocketSystem__GC0,
-case__1211: APBGpsBlock__GC0,
-reg__715: RocketTile__GCB0,
-case__1534: TLToAPB,
-logic__4355: FPU__GB1,
-case__911: VCU118RocketSystem__GC0,
-datapath__132: VCU118RocketSystem__GC0,
-logic__1221: VCU118RocketSystem__GC0,
-datapath__475: VCU118RocketSystem__GC0,
-reg__855: VCU118RocketSystem__GC0,
-datapath__343: FPU__GB1,
-logic__2296: DCache,
-logic__5395: RocketTile__GCB0,
-logic__5892: RocketTile__GCB0,
-case__1476: tracking_wrapper,
-logic__4374: FPU__GB1,
-logic__3660: FPU__GB1,
-Queue1_RegMapperInput_i23_m8: VCU118RocketSystem__GC0,
-logic__8794: tracking_wrapper,
-reg__749: RocketTile__GCB0,
-reg__1077: APBGpsBlock__GC0,
-logic__3769: FPU__GB1,
-logic__7689: APBGpsBlock__GC0,
-datapath__259: DCache,
-logic__5009: RocketTile__GCB0,
-case__899: VCU118RocketSystem__GC0,
-logic__2680: FPU__GB1,
-case__541: FPU__GB2,
-logic__1687: DCache,
-logic__4446: FPU__GB1,
-datapath__19: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__5150: RocketTile__GCB0,
-logic__2789: FPU__GB1,
-case__48: VCU118RocketSystem__GC0,
-logic__2864: FPU__GB1,
-logic__4413: FPU__GB1,
-logic__4837: RocketTile__GCB0,
-logic__6178: VCU118RocketSystem__GC0,
-TLBuffer_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__1082: VCU118RocketSystem__GC0,
-datapath__260: DCache,
-logic__990: VCU118RocketSystem__GC0,
-reg__714: RocketTile__GCB0,
-case__966: VCU118RocketSystem__GC0,
-logic__202: VCU118RocketSystem__GC0,
-logic__4715: RocketTile__GCB0,
-reg__1073: APBGpsBlock__GC0,
-logic__8437: tracking_wrapper,
-logic__5047: RocketTile__GCB0,
-logic__274: VCU118RocketSystem__GC0,
-logic__4120: FPU__GB2,
-logic__4859: RocketTile__GCB0,
-reg__1006: APBGpsBlock__GC0,
-RoundAnyRawFNToRecFN_1: FPU__GB2,
-datapath__621: tracking_wrapper,
-datapath__26: VCU118RocketSystem__GC0,
-reg__603: RocketTile__GCB0,
-case__1014: VCU118RocketSystem__GC0,
-case__1129: APBGpsBlock__GC0,
-case__1475: tracking_wrapper,
-case__310: DCache,
-logic__6164: VCU118RocketSystem__GC0,
-logic__2170: DCache,
-datapath__356: FPU__GB2, FPU__GB1,
-logic__5037: RocketTile__GCB0,
-reg__1014: APBGpsBlock__GC0,
-case__810: VCU118RocketSystem__GC0,
-case__52: VCU118RocketSystem__GC0,
-logic__1859: RocketTile__GCB0, DCache,
-case__556: FPU__GB2,
-case__491: FPU__GB2,
-case__1469: tracking_wrapper,
-logic__6279: VCU118RocketSystem__GC0,
-case__253: VCU118RocketSystem__GC0,
-reg__663: RocketTile__GCB0,
-logic__6417: VCU118RocketSystem__GC0,
-datapath__644: tracking_wrapper,
-case__59: VCU118RocketSystem__GC0,
-reg__944: VCU118RocketSystem__GC0,
-spill_register_flushable: tracking_wrapper,
-case__453: FPU__GB2, FPU__GB1,
-case__475: FPU__GB2,
-datapath__596: APBGpsBlock__GC0,
-logic__3748: FPU__GB1,
-case__921: VCU118RocketSystem__GC0,
-logic__6810: VCU118RocketSystem__GC0,
-bootromClockSinkDomain: VCU118RocketSystem__GC0,
-logic__5853: RocketTile__GCB0,
-RoundAnyRawFNToRecFN_3: FPU__GB1,
-logic__246: VCU118RocketSystem__GC0,
-logic__2963: FPU__GB2, FPU__GB1,
-logic__6435: VCU118RocketSystem__GC0,
-logic__4407: FPU__GB1,
-logic__238: VCU118RocketSystem__GC0,
-case__101: VCU118RocketSystem__GC0,
-case__509: FPU__GB1,
-case__368: RocketTile__GCB0,
-logic__1097: VCU118RocketSystem__GC0,
-logic__3130: FPU__GB2,
-logic__4866: RocketTile__GCB0,
-logic__6809: VCU118RocketSystem__GC0,
-logic__1012: VCU118RocketSystem__GC0,
-datapath__139: VCU118RocketSystem__GC0,
-logic__5384: RocketTile__GCB0,
-case__135: VCU118RocketSystem__GC0,
-case__547: FPU__GB2,
-logic__6129: VCU118RocketSystem__GC0,
-case__412: RocketTile__GCB0,
-muxpart__88: FPU__GB2,
-logic__2453: RocketTile__GCB0,
-logic__7781: APBGpsBlock__GC0,
-reg__649: RocketTile__GCB0,
-logic__5935: RocketTile__GCB0,
-logic__7178: VCU118RocketSystem__GC0,
-logic__4295: FPU__GB2,
-logic__8242: tracking_wrapper,
-logic__5678: RocketTile__GCB0,
-logic__6596: VCU118RocketSystem__GC0,
-case__1512: tracking_wrapper,
-datapath__16: VCU118RocketSystem__GC0,
-logic__3825: FPU__GB1,
-logic__6498: VCU118RocketSystem__GC0,
-logic__3925: FPU__GB2, FPU__GB1,
-logic__3170: FPU__GB2,
-case__561: FPU__GB2,
-logic__337: VCU118RocketSystem__GC0,
-logic__1872: RocketTile__GCB0, DCache,
-reg__385: FPU__GB0,
-logic__8293: tracking_wrapper,
-logic__1804: DCache,
-logic__8654: tracking_wrapper,
-logic__8112: APBGpsBlock__GC0,
-logic__2614: RocketTile__GCB0,
-rom__5: APBGpsBlock__GC0,
-case__933: VCU118RocketSystem__GC0,
-counter__16: APBGpsBlock__GC0,
-logic__5327: RocketTile__GCB0,
-logic__5203: RocketTile__GCB0,
-logic__2385: RocketTile__GCB0,
-logic__4941: RocketTile__GCB0,
-case__36: VCU118RocketSystem__GC0,
-reg__455: FPU__GB1,
-logic__3704: FPU__GB1,
-logic__2856: FPU__GB1,
-logic__4559: RocketTile__GCB0,
-logic__8113: APBGpsBlock__GC0,
-TLDebugModuleInnerAsync: VCU118RocketSystem__GC0,
-datapath__245: DCache,
-case__733: RocketTile__GCB0,
-reg__1017: APBGpsBlock__GC0,
-dsp48e1__8: APBGpsBlock__GC0,
-logic__4137: FPU__GB2,
-logic__3154: FPU__GB2,
-case__780: VCU118RocketSystem__GC0,
-case__1046: VCU118RocketSystem__GC0,
-reg__918: VCU118RocketSystem__GC0,
-logic__4756: RocketTile__GCB0,
-logic__4696: RocketTile__GCB0,
-reg__946: VCU118RocketSystem__GC0,
-logic__3264: FPU__GB2,
-reg__321: RocketTile__GCB0,
-case__452: FPU__GB2, FPU__GB1,
-nav_solve_timer: tracking_wrapper,
-case__1229: APBGpsBlock__GC0,
-case__1172: APBGpsBlock__GC0,
-logic__5948: RocketTile__GCB0,
-case__643: RocketTile__GCB0,
-reg__1335: tracking_wrapper,
-logic__4667: RocketTile__GCB0,
-case__1458: tracking_wrapper,
-reg__440: FPU__GB2,
-case__1219: APBGpsBlock__GC0,
-reg__733: RocketTile__GCB0,
-logic__4032: FPU__GB2,
-case__1332: tracking_wrapper,
-logic__8555: tracking_wrapper,
-case__812: VCU118RocketSystem__GC0,
-logic__1059: VCU118RocketSystem__GC0,
-reg__236: DCache,
-logic__8051: APBGpsBlock__GC0,
-logic__5481: RocketTile__GCB0,
-logic__8505: tracking_wrapper,
-logic__6731: VCU118RocketSystem__GC0,
-case__1432: tracking_wrapper,
-reg__35: VCU118RocketSystem__GC0,
-logic__3655: FPU__GB1,
-case__498: FPU__GB1,
-logic__6949: VCU118RocketSystem__GC0,
-logic__138: VCU118RocketSystem__GC0,
-muxpart__61: FPU__GB0,
-case__1389: tracking_wrapper,
-reg__257: DCache,
-logic__5478: RocketTile__GCB0,
-reg__1348: VCU118RocketSystem__GC0,
-logic__6661: VCU118RocketSystem__GC0,
-case__151: VCU118RocketSystem__GC0,
-logic__160: VCU118RocketSystem__GC0,
-case__1: genesys2_rocket_top__GC0,
-logic__6341: VCU118RocketSystem__GC0,
-logic__3707: FPU__GB1,
-logic__4612: RocketTile__GCB0,
-logic__4785: RocketTile__GCB0,
-logic__5265: RocketTile__GCB0,
-case__384: RocketTile__GCB0,
-case__822: VCU118RocketSystem__GC0,
-reg__1215: tracking_wrapper,
-ram_2x10: VCU118RocketSystem__GC0,
-datapath__490: VCU118RocketSystem__GC0,
-case__57: VCU118RocketSystem__GC0,
-logic__2402: RocketTile__GCB0,
-reg__790: VCU118RocketSystem__GC0,
-datapath__505: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a28d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__3109: FPU__GB2,
-case__420: RocketTile__GCB0,
-logic__6882: VCU118RocketSystem__GC0,
-logic__3706: FPU__GB1,
-logic__1206: VCU118RocketSystem__GC0,
-case__163: VCU118RocketSystem__GC0,
-case__285: RocketTile__GCB0,
-logic__1719: DCache,
-muxpart__90: FPU__GB2,
-TLFragmenter_Debug: VCU118RocketSystem__GC0,
-reg__1043: APBGpsBlock__GC0,
-logic__1429: RocketTile__GCB0,
-reg__913: VCU118RocketSystem__GC0,
-logic__6991: VCU118RocketSystem__GC0,
-logic__5475: RocketTile__GCB0,
-case__957: VCU118RocketSystem__GC0,
-logic__4350: FPU__GB1,
-case__1325: APBGpsBlock__GC0,
-logic__4829: RocketTile__GCB0,
-logic__6757: VCU118RocketSystem__GC0,
-reg__155: VCU118RocketSystem__GC0,
-reg__987: VCU118RocketSystem__GC0,
-logic__6182: VCU118RocketSystem__GC0,
-logic__4953: RocketTile__GCB0,
-logic__699: VCU118RocketSystem__GC0,
-case__29: VCU118RocketSystem__GC0,
-reg__1040: APBGpsBlock__GC0,
-logic__6879: VCU118RocketSystem__GC0,
-reg__698: RocketTile__GCB0,
-logic__1541: DCache,
-case__1425: tracking_wrapper,
-logic__4691: RocketTile__GCB0,
-logic__1063: VCU118RocketSystem__GC0,
-logic__4045: FPU__GB2,
-TLBuffer_a32d64s2k1z3u: RocketTile__GCB0,
-datapath__679: tracking_wrapper,
-reg__800: VCU118RocketSystem__GC0,
-datapath__94: VCU118RocketSystem__GC0,
-datapath__462: RocketTile__GCB0,
-logic__1416: RocketTile__GCB0,
-logic__5507: RocketTile__GCB0,
-logic__4099: FPU__GB2,
-logic__5284: RocketTile__GCB0,
-reg__970: VCU118RocketSystem__GC0,
-case__1328: APBGpsBlock__GC0,
-muxpart__5: VCU118RocketSystem__GC0,
-datapath__641: tracking_wrapper,
-logic__5377: RocketTile__GCB0,
-logic__4861: RocketTile__GCB0,
-Repeater_TLBundleA_a29d64s2k1z3u_2: VCU118RocketSystem__GC0,
-logic__6292: VCU118RocketSystem__GC0,
-TLXbar_pbus_out_i1_o3_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__2195: DCache,
-muxpart__29: FPU__GB0,
-case__590: FPU__GB1,
-logic__1269: VCU118RocketSystem__GC0,
-logic__4835: RocketTile__GCB0,
-logic__6189: VCU118RocketSystem__GC0,
-logic__3147: FPU__GB2,
-logic__3552: FPU__GB1,
-logic__318: VCU118RocketSystem__GC0,
-case__508: FPU__GB1,
-logic__4780: RocketTile__GCB0,
-logic__2967: FPU__GB2, FPU__GB1,
-logic__8872: tracking_wrapper,
-reg__923: VCU118RocketSystem__GC0,
-logic__8237: tracking_wrapper,
-Repeater_TLBundleD_a32d64s1k1z4u: VCU118RocketSystem__GC0,
-muxpart__80: FPU__GB0,
-datapath__179: VCU118RocketSystem__GC0,
-counter__8: APBGpsBlock__GC0,
-dsp48e1__40: tracking_wrapper,
-logic__6587: VCU118RocketSystem__GC0,
-reg__760: RocketTile__GCB0,
-logic__7677: APBGpsBlock__GC0,
-case__1125: APBGpsBlock__GC0,
-logic__215: VCU118RocketSystem__GC0,
-reg__398: FPU__GB1,
-TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u: RocketTile__GCB0,
-reg__1016: APBGpsBlock__GC0,
-case__774: RocketTile__GCB0,
-logic__619: VCU118RocketSystem__GC0,
-reg__644: RocketTile__GCB0,
-logic__4568: RocketTile__GCB0,
-logic__4776: RocketTile__GCB0,
-case__347: DCache,
-logic__4923: RocketTile__GCB0,
-TLXbar_pbus_in_i1_o1_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-TLBuffer_a32d64s2k1z3u_1: TilePRCIDomain__GC0,
-case__315: DCache,
-logic__1103: VCU118RocketSystem__GC0,
-reg__691: RocketTile__GCB0,
-logic__1131: VCU118RocketSystem__GC0,
-logic__4452: FPU__GB1,
-logic__609: VCU118RocketSystem__GC0,
-logic__494: VCU118RocketSystem__GC0,
-logic__2438: RocketTile__GCB0,
-datapath__402: RocketTile__GCB0,
-logic__4100: FPU__GB2,
-reg__969: VCU118RocketSystem__GC0,
-reg__1247: tracking_wrapper,
-logic__5366: RocketTile__GCB0,
-logic__7120: VCU118RocketSystem__GC0,
-logic__6796: VCU118RocketSystem__GC0,
-logic__117: VCU118RocketSystem__GC0,
-logic__3912: FPU__GB2, FPU__GB1,
-logic__2609: RocketTile__GCB0,
-case__746: RocketTile__GCB0,
-logic__379: VCU118RocketSystem__GC0,
-logic__3469: FPU__GB2,
-logic__8556: tracking_wrapper,
-logic__636: VCU118RocketSystem__GC0,
-muxpart__70: FPU__GB0,
-case__1405: tracking_wrapper,
-logic__7343: VCU118RocketSystem__GC0,
-reg__990: VCU118RocketSystem__GC0,
-reg__712: RocketTile__GCB0,
-logic__6537: VCU118RocketSystem__GC0,
-case__526: FPU__GB2, FPU__GB1,
-reg__935: VCU118RocketSystem__GC0,
-logic__1742: DCache,
-logic__1578: DCache,
-reg__687: RocketTile__GCB0,
-logic__7493: VCU118RocketSystem__GC0,
-datapath__365: FPU__GB2,
-logic__2088: DCache,
-logic__8629: tracking_wrapper,
-case__805: VCU118RocketSystem__GC0,
-datapath__657: tracking_wrapper,
-ram__8: VCU118RocketSystem__GC0,
-reg__803: VCU118RocketSystem__GC0,
-case__61: VCU118RocketSystem__GC0,
-case__105: VCU118RocketSystem__GC0,
-logic__6985: VCU118RocketSystem__GC0,
-logic__6245: VCU118RocketSystem__GC0,
-logic__257: VCU118RocketSystem__GC0,
-case__438: FPU__GB0,
-logic__3800: FPU__GB1,
-logic__2848: FPU__GB1,
-reg__543: FPU__GB1,
-case__514: FPU__GB1,
-case__738: RocketTile__GCB0,
-Queue2_TLBundleD_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2504: RocketTile__GCB0,
-logic__8780: tracking_wrapper,
-reg__635: RocketTile__GCB0,
-logic__8318: tracking_wrapper,
-datapath__342: FPU__GB1,
-rocket_bscan_dmi_tunnel: genesys2_rocket_top__GC0,
-case__399: RocketTile__GCB0,
-logic__5466: RocketTile__GCB0,
-reg__664: RocketTile__GCB0,
-logic__6184: VCU118RocketSystem__GC0,
-logic__4557: RocketTile__GCB0,
-reg__498: FPU__GB2,
-case__564: FPU__GB1,
-reg__1326: tracking_wrapper,
-logic__6575: VCU118RocketSystem__GC0,
-case__1131: APBGpsBlock__GC0,
-logic__8440: tracking_wrapper,
-datapath__418: RocketTile__GCB0,
-reg__872: VCU118RocketSystem__GC0,
-case__422: RocketTile__GCB0,
-logic__3996: FPU__GB2,
-logic__2934: FPU__GB1,
-logic__7088: VCU118RocketSystem__GC0,
-logic__1017: VCU118RocketSystem__GC0,
-logic__2690: FPU__GB1,
-muxpart__63: FPU__GB0,
-logic__5260: RocketTile__GCB0,
-rockettile_dcache_data_arrays_0_131072x64: DCache,
-logic__2102: DCache,
-logic__6598: VCU118RocketSystem__GC0,
-case__133: VCU118RocketSystem__GC0,
-logic__6383: VCU118RocketSystem__GC0,
-logic__4836: RocketTile__GCB0,
-logic__3434: FPU__GB2,
-logic__1360: VCU118RocketSystem__GC0,
-case__76: VCU118RocketSystem__GC0,
-case__516: FPU__GB1,
-reg__500: FPU__GB2,
-reg__352: RocketTile__GCB0,
-reg__896: VCU118RocketSystem__GC0,
-case__714: RocketTile__GCB0,
-reg__725: RocketTile__GCB0,
-reg__1133: tracking_wrapper,
-logic__6304: VCU118RocketSystem__GC0,
-case__1117: APBGpsBlock__GC0,
-logic__2788: FPU__GB1,
-case__1053: APBGpsBlock__GC0,
-case__339: DCache,
-case__425: RocketTile__GCB0,
-reg__1189: tracking_wrapper,
-case__1367: tracking_wrapper,
-datapath__474: VCU118RocketSystem__GC0,
-logic__476: VCU118RocketSystem__GC0,
-logic__2226: DCache,
-code_loop_discriminator: tracking_wrapper,
-reg__37: VCU118RocketSystem__GC0,
-logic__6063: RocketTile__GCB0,
-logic__3681: FPU__GB1,
-logic__7058: VCU118RocketSystem__GC0,
-extram__4: APBGpsBlock__GC0,
-logic__4125: FPU__GB2,
-case__140: VCU118RocketSystem__GC0,
-case__1397: tracking_wrapper,
-datapath__25: VCU118RocketSystem__GC0,
-logic__6284: VCU118RocketSystem__GC0,
-case__80: VCU118RocketSystem__GC0,
-case__827: VCU118RocketSystem__GC0,
-logic__2475: RocketTile__GCB0,
-reg__200: VCU118RocketSystem__GC0,
-logic__2873: FPU__GB1,
-case__1234: APBGpsBlock__GC0,
-logic__1702: DCache,
-logic__6175: VCU118RocketSystem__GC0,
-datapath__689: TLToAPB,
-logic__1329: VCU118RocketSystem__GC0,
-case__818: VCU118RocketSystem__GC0,
-logic__3942: FPU__GB2, FPU__GB1,
-reg__68: VCU118RocketSystem__GC0,
-logic__8300: tracking_wrapper,
-logic__3530: FPU__GB1,
-logic__426: VCU118RocketSystem__GC0,
-logic__686: VCU118RocketSystem__GC0,
-ram__7: TilePRCIDomain__GC0,
-case__972: VCU118RocketSystem__GC0,
-reg__1249: tracking_wrapper,
-case__1098: APBGpsBlock__GC0,
-logic__6438: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_fbus_from_debug_sb: VCU118RocketSystem__GC0,
-logic__4411: FPU__GB1,
-logic__4597: RocketTile__GCB0,
-logic__2782: FPU__GB1,
-logic__8384: tracking_wrapper,
-case__789: VCU118RocketSystem__GC0,
-logic__3657: FPU__GB1,
-logic__3908: FPU__GB2, FPU__GB1,
-logic__1232: VCU118RocketSystem__GC0,
-logic__5288: RocketTile__GCB0,
-datapath__508: VCU118RocketSystem__GC0,
-case__964: VCU118RocketSystem__GC0,
-logic__6066: RocketTile__GCB0,
-reg__368: FPU__GB0,
-logic__7685: APBGpsBlock__GC0,
-logic__7070: VCU118RocketSystem__GC0,
-case__669: RocketTile__GCB0,
-logic__156: VCU118RocketSystem__GC0,
-logic__8046: APBGpsBlock__GC0,
-case__1056: APBGpsBlock__GC0,
-reg__632: RocketTile__GCB0,
-reg__1165: tracking_wrapper,
-logic__5988: RocketTile__GCB0,
-datapath__248: DCache,
-reg__883: VCU118RocketSystem__GC0,
-reg__187: VCU118RocketSystem__GC0,
-reg__1229: tracking_wrapper,
-muxpart__72: FPU__GB0,
-logic__8369: tracking_wrapper,
-logic__1739: DCache,
-case__281: VCU118RocketSystem__GC0,
-logic__6286: VCU118RocketSystem__GC0,
-case__233: VCU118RocketSystem__GC0,
-logic__7099: VCU118RocketSystem__GC0,
-logic__5508: RocketTile__GCB0,
-logic__5280: RocketTile__GCB0,
-logic__4561: RocketTile__GCB0,
-reg__428: FPU__GB1,
-logic__5911: RocketTile__GCB0,
-case__905: VCU118RocketSystem__GC0,
-logic__7919: APBGpsBlock__GC0,
-logic__1573: DCache,
-logic__2140: DCache,
-case__459: FPU__GB2, FPU__GB1,
-datapath__498: VCU118RocketSystem__GC0,
-datapath__106: VCU118RocketSystem__GC0,
-reg__1310: tracking_wrapper,
-reg__74: VCU118RocketSystem__GC0,
-logic__8958: VCU118RocketSystem__GC0,
-TLWidthWidget8_1: VCU118RocketSystem__GC0, RocketTile__GCB0,
-logic__1552: DCache,
-reg__1248: tracking_wrapper,
-logic__6626: VCU118RocketSystem__GC0,
-reg__272: DCache,
-reg__138: VCU118RocketSystem__GC0,
-logic__8750: tracking_wrapper,
-logic__2355: RocketTile__GCB0,
-logic__3585: FPU__GB1,
-logic__6298: VCU118RocketSystem__GC0,
-logic__2227: DCache,
-case__271: VCU118RocketSystem__GC0,
-logic__317: VCU118RocketSystem__GC0,
-logic__617: VCU118RocketSystem__GC0,
-logic__8793: tracking_wrapper,
-case__250: VCU118RocketSystem__GC0,
-reg__939: VCU118RocketSystem__GC0,
-logic__4290: FPU__GB1,
-logic__6637: VCU118RocketSystem__GC0,
-logic__1335: VCU118RocketSystem__GC0,
-logic__2798: FPU__GB1,
-reg__478: FPU__GB1,
-logic__5882: RocketTile__GCB0,
-reg__1298: tracking_wrapper,
-logic__8280: tracking_wrapper,
-logic__696: VCU118RocketSystem__GC0,
-logic__142: VCU118RocketSystem__GC0,
-case__753: RocketTile__GCB0,
-datapath__296: FPU__GB1,
-case__670: RocketTile__GCB0,
-logic__6734: VCU118RocketSystem__GC0,
-reg__805: VCU118RocketSystem__GC0,
-logic__1147: VCU118RocketSystem__GC0,
-logic__4370: FPU__GB1,
-logic__7037: VCU118RocketSystem__GC0,
-logic__1779: DCache,
-reg__64: VCU118RocketSystem__GC0,
-logic__1013: VCU118RocketSystem__GC0,
-datapath__488: VCU118RocketSystem__GC0,
-logic__2319: RocketTile__GCB0,
-logic__5979: RocketTile__GCB0,
-muxpart__223: tracking_wrapper,
-case__881: VCU118RocketSystem__GC0,
-datapath__232: VCU118RocketSystem__GC0,
-logic__2080: DCache,
-case__712: RocketTile__GCB0,
-logic__4811: RocketTile__GCB0,
-datapath__521: VCU118RocketSystem__GC0,
-logic__1990: DCache,
-logic__6538: VCU118RocketSystem__GC0,
-logic__4885: RocketTile__GCB0,
-reg__933: VCU118RocketSystem__GC0,
-reg__625: RocketTile__GCB0,
-TLInterconnectCoupler_cbus_to_clint: VCU118RocketSystem__GC0,
-datapath__133: VCU118RocketSystem__GC0,
-logic__4122: FPU__GB2,
-logic__6910: VCU118RocketSystem__GC0,
-logic__549: VCU118RocketSystem__GC0,
-case__350: DCache,
-case__1369: tracking_wrapper,
-logic__139: VCU118RocketSystem__GC0,
-logic__674: VCU118RocketSystem__GC0,
-muxpart__76: FPU__GB0,
-datapath__224: VCU118RocketSystem__GC0,
-logic__3051: FPU__GB2,
-case__1504: tracking_wrapper,
-datapath__330: FPU__GB2,
-case__252: VCU118RocketSystem__GC0,
-logic__868: VCU118RocketSystem__GC0,
-reg__776: TilePRCIDomain__GC0,
-logic__1606: DCache,
-logic__5927: RocketTile__GCB0,
-logic__7391: VCU118RocketSystem__GC0,
-logic__7019: VCU118RocketSystem__GC0,
-reg__485: FPU__GB1,
-logic__3827: FPU__GB1,
-reg__853: VCU118RocketSystem__GC0,
-extrom: APBGpsBlock__GC0,
-logic__14: genesys2_rocket_top__GC0,
-logic__251: VCU118RocketSystem__GC0,
-case__920: VCU118RocketSystem__GC0,
-case__415: RocketTile__GCB0,
-logic__586: VCU118RocketSystem__GC0,
-logic__4824: RocketTile__GCB0,
-reg__287: RocketTile__GCB0,
-reg__182: VCU118RocketSystem__GC0,
-case__143: VCU118RocketSystem__GC0,
-case__654: RocketTile__GCB0,
-logic__4934: RocketTile__GCB0,
-logic__7273: VCU118RocketSystem__GC0,
-case__74: VCU118RocketSystem__GC0,
-reset_synch: tracking_wrapper,
-logic__3221: FPU__GB2,
-bram: APBGpsBlock__GC0,
-logic__3046: FPU__GB1,
-datapath__674: tracking_wrapper,
-logic__2337: RocketTile__GCB0,
-logic__1135: VCU118RocketSystem__GC0,
-logic__7712: APBGpsBlock__GC0,
-logic__6035: RocketTile__GCB0,
-logic__975: VCU118RocketSystem__GC0,
-logic__7853: APBGpsBlock__GC0,
-logic__7824: APBGpsBlock__GC0,
-case__667: RocketTile__GCB0,
-logic__6737: VCU118RocketSystem__GC0,
-case__913: VCU118RocketSystem__GC0,
-reg__915: VCU118RocketSystem__GC0,
-logic__7721: APBGpsBlock__GC0,
-logic__2414: RocketTile__GCB0,
-datapath__602: APBGpsBlock__GC0,
-reg__936: VCU118RocketSystem__GC0,
-datapath__154: VCU118RocketSystem__GC0,
-logic__3009: FPU__GB2, FPU__GB1,
-datapath__236: RocketTile__GCB0,
-reg__1054: APBGpsBlock__GC0,
-logic__8726: tracking_wrapper,
-ram__6: RocketTile__GCB0,
-logic__6391: VCU118RocketSystem__GC0,
-logic__7012: VCU118RocketSystem__GC0,
-logic__1278: VCU118RocketSystem__GC0,
-reg__1293: tracking_wrapper,
-logic__1155: VCU118RocketSystem__GC0,
-reg__7: genesys2_rocket_top__GC0,
-reg__13: genesys2_rocket_top__GC0,
-case__1059: APBGpsBlock__GC0,
-datapath__368: FPU__GB2,
-case__64: VCU118RocketSystem__GC0,
-muxpart__69: FPU__GB0,
-logic__2459: RocketTile__GCB0,
-case__835: VCU118RocketSystem__GC0,
-reg__211: VCU118RocketSystem__GC0,
-logic__4560: RocketTile__GCB0,
-case__530: FPU__GB2,
-datapath__526: APBGpsBlock__GC0,
-logic__3330: FPU__GB2,
-reg__439: FPU__GB2,
-logic__71: genesys2_rocket_top__GC0,
-case__383: RocketTile__GCB0,
-logic__187: VCU118RocketSystem__GC0,
-reg__674: RocketTile__GCB0,
-logic__7614: VCU118RocketSystem__GC0,
-logic__3910: FPU__GB2, FPU__GB1,
-reg__721: RocketTile__GCB0,
-muxpart__83: FPU__GB0,
-logic__3567: FPU__GB1,
-logic__1162: VCU118RocketSystem__GC0,
-logic__5967: RocketTile__GCB0,
-logic__3656: FPU__GB1,
-case__915: VCU118RocketSystem__GC0,
-logic__3164: FPU__GB2,
-logic__8244: tracking_wrapper,
-logic__3701: FPU__GB1,
-logic__2675: FPU__GB1,
-case__489: FPU__GB2,
-logic__3903: FPU__GB2, FPU__GB1,
-reg__945: VCU118RocketSystem__GC0,
-logic__581: VCU118RocketSystem__GC0,
-logic__5457: RocketTile__GCB0,
-logic__2042: DCache,
-logic__6979: VCU118RocketSystem__GC0,
-datapath__168: VCU118RocketSystem__GC0,
-logic__4935: RocketTile__GCB0,
-logic__1665: DCache,
-logic__3482: FPU__GB2,
-reg__949: VCU118RocketSystem__GC0,
-logic__1100: VCU118RocketSystem__GC0,
-logic__1420: RocketTile__GCB0,
-case__240: VCU118RocketSystem__GC0,
-logic__2779: FPU__GB1,
-logic__4240: FPU__GB2,
-logic__707: VCU118RocketSystem__GC0,
-logic__6277: VCU118RocketSystem__GC0,
-case__1380: tracking_wrapper,
-datapath__623: tracking_wrapper,
-logic__8430: tracking_wrapper,
-logic__3206: FPU__GB2,
-TLInterconnectCoupler_cbus_to_bootrom: VCU118RocketSystem__GC0,
-logic__1886: RocketTile__GCB0, DCache,
-case__1043: VCU118RocketSystem__GC0,
-logic__8897: APBGpsBlock__GC0,
-datapath__520: VCU118RocketSystem__GC0,
-case__838: VCU118RocketSystem__GC0,
-case__1379: tracking_wrapper,
-logic__4086: FPU__GB2,
-reg__270: DCache,
-reg__610: RocketTile__GCB0,
-logic__675: VCU118RocketSystem__GC0,
-logic__2918: FPU__GB1,
-logic__845: VCU118RocketSystem__GC0,
-logic__5044: RocketTile__GCB0,
-logic__6159: VCU118RocketSystem__GC0,
-logic__4886: RocketTile__GCB0,
-TLFpgaUART: VCU118RocketSystem__GC0,
-logic__2581: RocketTile__GCB0,
-case__601: FPU__GB1,
-logic__4717: RocketTile__GCB0,
-NCO_carr: tracking_wrapper,
-logic__2393: RocketTile__GCB0,
-logic__8240: tracking_wrapper,
-logic__6025: RocketTile__GCB0,
-reg__474: FPU__GB1,
-case__1120: APBGpsBlock__GC0,
-case__725: RocketTile__GCB0,
-case__1167: APBGpsBlock__GC0,
-logic__6712: VCU118RocketSystem__GC0,
-datapath__80: VCU118RocketSystem__GC0,
-logic__5213: RocketTile__GCB0,
-logic__7114: VCU118RocketSystem__GC0,
-reg__955: VCU118RocketSystem__GC0,
-logic__7365: VCU118RocketSystem__GC0,
-logic__1004: VCU118RocketSystem__GC0,
-case__719: RocketTile__GCB0,
-datapath__270: RocketTile__GCB0,
-logic__6668: VCU118RocketSystem__GC0,
-logic__7475: VCU118RocketSystem__GC0,
-logic__390: VCU118RocketSystem__GC0,
-reg__445: FPU__GB2,
-logic__1456: RocketTile__GCB0,
-PMPChecker_s2: RocketTile__GCB0,
-logic__4949: RocketTile__GCB0,
-reg__767: RocketTile__GCB0,
-case__1121: APBGpsBlock__GC0,
-logic__6218: VCU118RocketSystem__GC0,
-case__801: VCU118RocketSystem__GC0,
-reg__893: VCU118RocketSystem__GC0,
-logic__8965: genesys2_rocket_top__GC0,
-reg__904: VCU118RocketSystem__GC0,
-logic__3558: FPU__GB1,
-logic__5696: RocketTile__GCB0,
-TilePRCIDomain__GC0: TilePRCIDomain__GC0,
-counter__1: VCU118RocketSystem__GC0,
-logic__4006: FPU__GB2,
-reg__1164: tracking_wrapper,
-logic__2068: DCache,
-reg__1284: tracking_wrapper,
-MulAddRecFNToRaw_preMul_1: FPU__GB1,
-logic__4887: RocketTile__GCB0,
-muxpart__49: FPU__GB0,
-NCO_code: tracking_wrapper,
-case__602: FPU__GB1,
-logic__7707: APBGpsBlock__GC0,
-case__313: DCache,
-logic__2692: FPU__GB1,
-reg__298: RocketTile__GCB0,
-reg__100: VCU118RocketSystem__GC0,
-reg__209: VCU118RocketSystem__GC0,
-muxpart__84: FPU__GB0,
-case__668: RocketTile__GCB0,
-case__993: VCU118RocketSystem__GC0,
-datapath__338: FPU__GB1,
-logic__6588: VCU118RocketSystem__GC0,
-twiddle_ram: APBGpsBlock__GC0,
-logic__8322: tracking_wrapper,
-case__872: VCU118RocketSystem__GC0,
-logic__2206: DCache,
-logic__5341: RocketTile__GCB0,
-logic__5144: RocketTile__GCB0,
-reg__1321: tracking_wrapper,
-divider__parameterized0: tracking_wrapper,
-logic__6709: VCU118RocketSystem__GC0,
-reg__1217: tracking_wrapper,
-case__1134: APBGpsBlock__GC0,
-logic__6452: VCU118RocketSystem__GC0,
-reg__277: DCache,
-reg__887: VCU118RocketSystem__GC0,
-reg__1076: APBGpsBlock__GC0,
-case__1128: APBGpsBlock__GC0,
-reg__359: RocketTile__GCB0,
-reg__423: FPU__GB1,
-logic__2554: RocketTile__GCB0,
-logic__4519: RocketTile__GCB0,
-logic__168: VCU118RocketSystem__GC0,
-logic__8216: APBGpsBlock__GC0,
-muxpart__60: FPU__GB0,
-case__884: VCU118RocketSystem__GC0,
-reg__190: VCU118RocketSystem__GC0,
-logic__4281: FPU__GB1,
-logic__2458: RocketTile__GCB0,
-logic__4230: FPU__GB2,
-reg__1022: APBGpsBlock__GC0,
-datapath__457: RocketTile__GCB0,
-datapath__582: APBGpsBlock__GC0,
-logic__8919: APBGpsBlock__GC0,
-datapath__348: FPU__GB1,
-case__497: FPU__GB1,
-logic__3863: FPU__GB2, FPU__GB1,
-reg__83: VCU118RocketSystem__GC0,
-logic__8305: tracking_wrapper,
-logic__646: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__269: VCU118RocketSystem__GC0,
-logic__575: VCU118RocketSystem__GC0,
-case__1272: APBGpsBlock__GC0,
-case__1030: VCU118RocketSystem__GC0,
-reg__1251: tracking_wrapper,
-logic__539: VCU118RocketSystem__GC0,
-reg__291: RocketTile__GCB0,
-case__873: VCU118RocketSystem__GC0,
-reg__184: VCU118RocketSystem__GC0,
-logic__4693: RocketTile__GCB0,
-logic__4553: RocketTile__GCB0,
-reg__1237: tracking_wrapper,
-MulAddRecFNPipe_l2_e11_s53: FPU__GB1,
-case__273: VCU118RocketSystem__GC0,
-datapath__546: APBGpsBlock__GC0,
-logic__3453: FPU__GB2,
-logic__2142: DCache,
-case__843: VCU118RocketSystem__GC0,
-logic__8568: tracking_wrapper,
-logic__2836: FPU__GB1,
-reg__506: FPU__GB2,
-logic__8818: tracking_wrapper,
-logic__1530: DCache,
-logic__327: VCU118RocketSystem__GC0,
-logic__4823: RocketTile__GCB0,
-reg__670: RocketTile__GCB0,
-datapath__357: FPU__GB2, FPU__GB1,
-datapath__451: RocketTile__GCB0,
-logic__8755: tracking_wrapper,
-case__1366: tracking_wrapper,
-reg__1204: tracking_wrapper,
-logic__6221: VCU118RocketSystem__GC0,
-logic__6350: VCU118RocketSystem__GC0,
-datapath__107: VCU118RocketSystem__GC0,
-logic__8373: tracking_wrapper,
-logic__7159: VCU118RocketSystem__GC0,
-logic__3069: FPU__GB2,
-logic__2567: RocketTile__GCB0,
-reg__1276: tracking_wrapper,
-logic__903: VCU118RocketSystem__GC0,
-logic__109: VCU118RocketSystem__GC0,
-datapath__172: VCU118RocketSystem__GC0,
-logic__186: VCU118RocketSystem__GC0,
-reg__8: genesys2_rocket_top__GC0,
-logic__1132: VCU118RocketSystem__GC0,
-logic__4735: RocketTile__GCB0,
-logic__2678: FPU__GB1,
-reg__1339: TLToAPB,
-case__431: RocketTile__GCB0,
-logic__2411: RocketTile__GCB0,
-case__992: VCU118RocketSystem__GC0,
-logic__8668: tracking_wrapper,
-logic__6705: VCU118RocketSystem__GC0,
-logic__2575: RocketTile__GCB0,
-datapath__9: VCU118RocketSystem__GC0,
-reg__1218: tracking_wrapper,
-muxpart__57: FPU__GB0,
-logic__7705: APBGpsBlock__GC0,
-logic__7171: VCU118RocketSystem__GC0,
-logic__8256: tracking_wrapper,
-logic__5291: RocketTile__GCB0,
-logic__311: VCU118RocketSystem__GC0,
-logic__8442: tracking_wrapper,
-reg__149: VCU118RocketSystem__GC0,
-datapath__397: RocketTile__GCB0,
-reg__278: DCache,
-logic__1584: DCache,
-FPUDecoder: FPU__GB1,
-case__1095: APBGpsBlock__GC0,
-logic__5220: RocketTile__GCB0,
-logic__4820: RocketTile__GCB0,
-reg__700: RocketTile__GCB0,
-reg__380: FPU__GB0,
-case__1025: VCU118RocketSystem__GC0,
-logic__4630: RocketTile__GCB0,
-logic__8696: tracking_wrapper,
-logic__3768: FPU__GB1,
-logic__7544: VCU118RocketSystem__GC0,
-logic__5054: RocketTile__GCB0,
-reg__870: VCU118RocketSystem__GC0,
-muxpart__6: VCU118RocketSystem__GC0,
-case__409: RocketTile__GCB0,
-datapath__128: VCU118RocketSystem__GC0,
-reg__226: RocketTile__GCB0,
-logic__5887: RocketTile__GCB0,
-case__230: VCU118RocketSystem__GC0,
-logic__6352: VCU118RocketSystem__GC0,
-reg__708: RocketTile__GCB0,
-logic__687: VCU118RocketSystem__GC0,
-logic__8401: tracking_wrapper,
-logic__4134: FPU__GB2,
-logic__6009: RocketTile__GCB0,
-case__1168: APBGpsBlock__GC0,
-logic__1139: VCU118RocketSystem__GC0,
-case__1404: tracking_wrapper,
-dsp48e1__4: APBGpsBlock__GC0,
-logic__349: VCU118RocketSystem__GC0,
-logic__7648: VCU118RocketSystem__GC0,
-case__1330: APBGpsBlock__GC0,
-reg__1219: tracking_wrapper,
-logic__3760: FPU__GB1,
-datapath__86: VCU118RocketSystem__GC0,
-case__405: RocketTile__GCB0,
-reg__683: RocketTile__GCB0,
-logic__8822: tracking_wrapper,
-logic__4070: FPU__GB2,
-logic__3746: FPU__GB1,
-case__20: genesys2_rocket_top__GC0,
-logic__1438: RocketTile__GCB0,
-logic__47: genesys2_rocket_top__GC0,
-reg__1119: APBGpsBlock__GC0,
-reg__1171: tracking_wrapper,
-reg__957: VCU118RocketSystem__GC0,
-case__109: VCU118RocketSystem__GC0,
-logic__4132: FPU__GB2,
-datapath__325: FPU__GB2,
-case__406: RocketTile__GCB0,
-logic__6082: TilePRCIDomain__GC0,
-reg__1291: tracking_wrapper,
-case__1300: APBGpsBlock__GC0,
-case__996: VCU118RocketSystem__GC0,
-logic__7189: VCU118RocketSystem__GC0,
-reg__534: FPU__GB1,
-logic__212: VCU118RocketSystem__GC0,
-case__864: VCU118RocketSystem__GC0,
-logic__4084: FPU__GB2,
-logic__1014: VCU118RocketSystem__GC0,
-logic__5667: RocketTile__GCB0,
-logic__5021: RocketTile__GCB0,
-ResetCatchAndSync_d3: APBGpsBlock__GC0,
-logic__7666: VCU118RocketSystem__GC0,
-logic__6889: VCU118RocketSystem__GC0,
-logic__5029: RocketTile__GCB0,
-reg__341: RocketTile__GCB0,
-muxpart__44: FPU__GB0,
-counter__24: tracking_wrapper,
-datapath__432: RocketTile__GCB0,
-logic__5867: RocketTile__GCB0,
-case__898: VCU118RocketSystem__GC0,
-logic__6745: VCU118RocketSystem__GC0,
-reg__174: VCU118RocketSystem__GC0,
-logic__6638: VCU118RocketSystem__GC0,
-logic__4813: RocketTile__GCB0,
-logic__4633: RocketTile__GCB0,
-case__14: genesys2_rocket_top__GC0,
-case__720: RocketTile__GCB0,
-logic__1951: DCache,
-case__276: VCU118RocketSystem__GC0,
-case__628: RocketTile__GCB0,
-logic__2266: DCache,
-logic__8757: tracking_wrapper,
-reg__269: DCache,
-logic__1357: VCU118RocketSystem__GC0,
-logic__8289: tracking_wrapper,
-logic__4950: RocketTile__GCB0,
-case__985: VCU118RocketSystem__GC0,
-logic__6597: VCU118RocketSystem__GC0,
-logic__6411: VCU118RocketSystem__GC0,
-case__1270: APBGpsBlock__GC0,
-logic__7579: VCU118RocketSystem__GC0,
-case__1368: tracking_wrapper,
-logic__4133: FPU__GB2,
-logic__880: VCU118RocketSystem__GC0,
-case__894: VCU118RocketSystem__GC0,
-datapath__581: APBGpsBlock__GC0,
-reg__1177: tracking_wrapper,
-logic__5057: RocketTile__GCB0,
-logic__3074: FPU__GB2,
-reg__349: RocketTile__GCB0,
-logic__936: VCU118RocketSystem__GC0,
-reg__950: VCU118RocketSystem__GC0,
-datapath__129: VCU118RocketSystem__GC0,
-case__640: RocketTile__GCB0,
-datapath__304: FPU__GB2,
-logic__8492: tracking_wrapper,
-logic__6526: VCU118RocketSystem__GC0,
-reg__1255: tracking_wrapper,
-logic__6096: VCU118RocketSystem__GC0,
-logic__1613: DCache,
-logic__2048: DCache,
-logic__8959: genesys2_rocket_top__GC0,
-reg__752: RocketTile__GCB0,
-case__237: VCU118RocketSystem__GC0,
-reg__176: VCU118RocketSystem__GC0,
-case__46: VCU118RocketSystem__GC0,
-logic__2446: RocketTile__GCB0,
-case__1410: tracking_wrapper,
-reg__1060: APBGpsBlock__GC0,
-datapath__421: RocketTile__GCB0,
-case__702: RocketTile__GCB0,
-logic__4065: FPU__GB2,
-datapath__68: VCU118RocketSystem__GC0,
-datapath__372: FPU__GB2,
-logic__287: VCU118RocketSystem__GC0,
-logic__4736: RocketTile__GCB0,
-case__1216: APBGpsBlock__GC0,
-counter__19: tracking_wrapper,
-reg__679: RocketTile__GCB0,
-reg__41: VCU118RocketSystem__GC0,
-datapath__123: VCU118RocketSystem__GC0,
-logic__6214: VCU118RocketSystem__GC0,
-logic__6170: VCU118RocketSystem__GC0,
-logic__5198: RocketTile__GCB0,
-case__1044: VCU118RocketSystem__GC0,
-reg__387: FPU__GB0,
-datapath__548: APBGpsBlock__GC0,
-case__447: FPU__GB1,
-datapath__276: RocketTile__GCB0,
-logic__6073: RocketTile__GCB0,
-logic__8653: tracking_wrapper,
-datapath__331: FPU__GB2,
-case__496: FPU__GB2,
-reg__392: FPU__GB0,
-logic__778: VCU118RocketSystem__GC0,
-datapath__591: APBGpsBlock__GC0,
-reg__201: VCU118RocketSystem__GC0,
-logic__242: VCU118RocketSystem__GC0,
-datapath__556: APBGpsBlock__GC0,
-logic__620: VCU118RocketSystem__GC0,
-case__106: VCU118RocketSystem__GC0,
-datapath__265: RocketTile__GCB0,
-logic__3818: FPU__GB1,
-logic__7441: VCU118RocketSystem__GC0,
-logic__2943: FPU__GB2, FPU__GB1,
-case__301: RocketTile__GCB0,
-logic__4970: RocketTile__GCB0,
-reg__1090: APBGpsBlock__GC0,
-case__67: VCU118RocketSystem__GC0,
-case__1006: VCU118RocketSystem__GC0,
-logic__8035: APBGpsBlock__GC0,
-logic__2880: FPU__GB1,
-logic__5429: RocketTile__GCB0,
-logic__4425: FPU__GB1,
-reg__661: RocketTile__GCB0,
-logic__5972: RocketTile__GCB0,
-logic__7411: VCU118RocketSystem__GC0,
-case__926: VCU118RocketSystem__GC0,
-case__78: VCU118RocketSystem__GC0,
-logic__4127: FPU__GB2,
-logic__3390: FPU__GB2,
-logic__3688: FPU__GB1,
-logic__3478: FPU__GB2,
-reg__624: RocketTile__GCB0,
-case__1454: tracking_wrapper,
-logic__3708: FPU__GB1,
-logic__4868: RocketTile__GCB0,
-ITLB: RocketTile__GCB0,
-logic__1707: DCache,
-reg__463: FPU__GB1,
-logic__8880: APBGpsBlock__GC0,
-reg__705: RocketTile__GCB0,
-reg__391: FPU__GB0,
-datapath__494: VCU118RocketSystem__GC0,
-reg__371: FPU__GB0,
-reg__716: RocketTile__GCB0,
-logic__421: VCU118RocketSystem__GC0,
-logic__249: VCU118RocketSystem__GC0,
-datapath__298: FPU__GB2, FPU__GB1,
-case__374: RocketTile__GCB0,
-RoundRawFNToRecFN_1: FPU__GB2, FPU__GB1,
-logic__2853: FPU__GB1,
-logic__6759: VCU118RocketSystem__GC0,
-case__248: VCU118RocketSystem__GC0,
-datapath__138: VCU118RocketSystem__GC0,
-reg__179: VCU118RocketSystem__GC0,
-logic__4745: RocketTile__GCB0,
-reg__56: VCU118RocketSystem__GC0,
-case__616: RocketTile__GCB0,
-logic__7132: VCU118RocketSystem__GC0,
-case__38: VCU118RocketSystem__GC0,
-case__33: VCU118RocketSystem__GC0,
-reg__1149: tracking_wrapper,
-logic__4185: FPU__GB2,
-datapath__366: FPU__GB2,
-logic__6012: RocketTile__GCB0,
-logic__1294: VCU118RocketSystem__GC0,
-case__1526: APBGpsBlock__GC0,
-datapath__461: RocketTile__GCB0,
-datapath__557: APBGpsBlock__GC0,
-datapath__637: tracking_wrapper,
-case__385: RocketTile__GCB0,
-logic__8234: tracking_wrapper,
-case__1214: APBGpsBlock__GC0,
-logic__1104: VCU118RocketSystem__GC0,
-logic__276: VCU118RocketSystem__GC0,
-logic__7956: APBGpsBlock__GC0,
-logic__2114: DCache,
-logic__3247: FPU__GB2,
-muxpart__48: FPU__GB0,
-datapath__554: APBGpsBlock__GC0,
-case__1472: tracking_wrapper,
-logic__1543: DCache,
-reg__615: RocketTile__GCB0,
-reg__406: FPU__GB1,
-logic__7381: VCU118RocketSystem__GC0,
-case__929: VCU118RocketSystem__GC0,
-logic__5289: RocketTile__GCB0,
-logic__3001: FPU__GB2, FPU__GB1,
-logic__8924: TLToAPB,
-case__1390: tracking_wrapper,
-reg__1003: APBGpsBlock__GC0,
-reg__444: FPU__GB2,
-logic__5403: RocketTile__GCB0,
-logic__6179: VCU118RocketSystem__GC0,
-logic__4507: RocketTile__GCB0,
-logic__6339: VCU118RocketSystem__GC0,
-datapath__266: RocketTile__GCB0,
-logic__2832: FPU__GB1,
-case__400: RocketTile__GCB0,
-datapath__359: FPU__GB2, FPU__GB1,
-datapath__407: RocketTile__GCB0,
-logic__8382: tracking_wrapper,
-reg__402: FPU__GB1,
-logic__610: VCU118RocketSystem__GC0,
-reg__1346: TLToAPB,
-MulAddRecFNPipe_l2_e8_s24: FPU__GB1,
-logic__2783: FPU__GB1,
-logic__1646: DCache,
-case__708: RocketTile__GCB0,
-logic__197: VCU118RocketSystem__GC0,
-datapath__8: VCU118RocketSystem__GC0,
-reg__432: FPU__GB2,
-reg__1023: APBGpsBlock__GC0,
-logic__2913: FPU__GB1,
-logic__1515: DCache,
-logic__6817: VCU118RocketSystem__GC0,
-logic__4078: FPU__GB2,
-logic__8436: tracking_wrapper,
-reg__152: VCU118RocketSystem__GC0,
-logic__557: VCU118RocketSystem__GC0,
-reg__677: RocketTile__GCB0,
-logic__7435: VCU118RocketSystem__GC0,
-logic__7126: VCU118RocketSystem__GC0,
-logic__2995: FPU__GB2, FPU__GB1,
-case__1444: tracking_wrapper,
-reg__750: RocketTile__GCB0,
-reg__686: RocketTile__GCB0,
-reg__771: RocketTile__GCB0,
-datapath__514: VCU118RocketSystem__GC0,
-reg__246: DCache,
-logic__1790: DCache,
-datapath__341: FPU__GB1,
-datapath__84: VCU118RocketSystem__GC0,
-logic__5627: RocketTile__GCB0,
-logic__4289: FPU__GB1,
-logic__6911: VCU118RocketSystem__GC0,
-datapath__346: FPU__GB1,
-logic__3149: FPU__GB2,
-logic__600: VCU118RocketSystem__GC0,
-logic__4586: RocketTile__GCB0,
-logic__3743: FPU__GB1,
-datapath__51: VCU118RocketSystem__GC0,
-case__1271: APBGpsBlock__GC0,
-case__1001: VCU118RocketSystem__GC0,
-logic__1955: DCache,
-reg__1132: tracking_wrapper,
-case__393: RocketTile__GCB0,
-logic__7618: VCU118RocketSystem__GC0,
-logic__3187: FPU__GB2,
-case__251: VCU118RocketSystem__GC0,
-logic__1828: RocketTile__GCB0, DCache,
-logic__4135: FPU__GB2,
-reg__1109: APBGpsBlock__GC0,
-logic__7377: VCU118RocketSystem__GC0,
-logic__5448: RocketTile__GCB0,
-case__936: VCU118RocketSystem__GC0,
-logic__6275: VCU118RocketSystem__GC0,
-case__1411: tracking_wrapper,
-case__528: FPU__GB2, FPU__GB1,
-datapath__522: VCU118RocketSystem__GC0,
-logic__6287: VCU118RocketSystem__GC0,
-reg__692: RocketTile__GCB0,
-reg__93: VCU118RocketSystem__GC0,
-logic__1457: RocketTile__GCB0,
-logic__5340: RocketTile__GCB0,
-case__1473: tracking_wrapper,
-logic__6344: VCU118RocketSystem__GC0,
-case__1428: tracking_wrapper,
-logic__8167: APBGpsBlock__GC0,
-reg__25: VCU118RocketSystem__GC0,
-case__1286: APBGpsBlock__GC0,
-case__790: VCU118RocketSystem__GC0,
-datapath__81: VCU118RocketSystem__GC0,
-logic__882: VCU118RocketSystem__GC0,
-logic__1726: DCache,
-logic__1018: VCU118RocketSystem__GC0,
-dsp48e1__34: tracking_wrapper,
-logic__1334: VCU118RocketSystem__GC0,
-logic__3930: FPU__GB2, FPU__GB1,
-logic__4877: RocketTile__GCB0,
-logic__8939: TLToAPB,
-logic__6093: VCU118RocketSystem__GC0,
-datapath__82: VCU118RocketSystem__GC0,
-logic__2045: DCache,
-logic__2912: FPU__GB1,
-case__755: RocketTile__GCB0,
-logic__5330: RocketTile__GCB0,
-case__382: RocketTile__GCB0,
-case__1440: tracking_wrapper,
-case__164: VCU118RocketSystem__GC0,
-logic__4480: FPU__GB1,
-case__1474: tracking_wrapper,
-reg__875: VCU118RocketSystem__GC0,
-logic__2306: DCache,
-case__1012: VCU118RocketSystem__GC0,
-logic__799: VCU118RocketSystem__GC0,
-reg__859: VCU118RocketSystem__GC0,
-logic__1973: DCache,
-dsp48e1__44: tracking_wrapper,
-muxpart__33: FPU__GB0,
-IntXbar_i1_o1: VCU118RocketSystem__GC0,
-logic__645: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7634: VCU118RocketSystem__GC0,
-logic__8781: tracking_wrapper,
-datapath__326: FPU__GB2,
-logic__1952: DCache,
-cordic_atan_basic: tracking_wrapper,
-reg__1210: tracking_wrapper,
-datapath__655: tracking_wrapper,
-logic__7860: APBGpsBlock__GC0,
-case__207: VCU118RocketSystem__GC0,
-case__1087: APBGpsBlock__GC0,
-datapath__34: VCU118RocketSystem__GC0,
-reg__475: FPU__GB1,
-logic__2536: RocketTile__GCB0,
-reg__1214: tracking_wrapper,
-case__1303: APBGpsBlock__GC0,
-logic__1175: VCU118RocketSystem__GC0,
-logic__865: VCU118RocketSystem__GC0,
-datapath__460: RocketTile__GCB0,
-logic__4362: FPU__GB2,
-case__187: VCU118RocketSystem__GC0,
-logic__5647: RocketTile__GCB0,
-logic__3381: FPU__GB2,
-fft_radix_2: APBGpsBlock__GC0,
-logic__6811: VCU118RocketSystem__GC0,
-reg__1067: APBGpsBlock__GC0,
-reg__1263: tracking_wrapper,
-datapath__4: genesys2_rocket_top__GC0,
-logic__8136: APBGpsBlock__GC0,
-datapath__361: FPU__GB1,
-reg__978: VCU118RocketSystem__GC0,
-case__888: VCU118RocketSystem__GC0,
-case__116: VCU118RocketSystem__GC0,
-logic__5392: RocketTile__GCB0,
-logic__6176: VCU118RocketSystem__GC0,
-logic__8039: APBGpsBlock__GC0,
-case__697: RocketTile__GCB0,
-case__258: VCU118RocketSystem__GC0,
-case__1533: TLToAPB,
-reg__1277: tracking_wrapper,
-logic__6955: VCU118RocketSystem__GC0,
-case__617: RocketTile__GCB0,
-datapath__394: RocketTile__GCB0,
-reg__141: VCU118RocketSystem__GC0,
-case__642: RocketTile__GCB0,
-logic__6434: VCU118RocketSystem__GC0,
-datapath__223: VCU118RocketSystem__GC0,
-datapath__141: VCU118RocketSystem__GC0,
-logic__2598: RocketTile__GCB0,
-datapath__543: APBGpsBlock__GC0,
-logic__8498: tracking_wrapper,
-case__398: RocketTile__GCB0,
-case__1443: tracking_wrapper,
-logic__5428: RocketTile__GCB0,
-reg__564: FPU__GB1,
-logic__1081: VCU118RocketSystem__GC0,
-logic__4129: FPU__GB2,
-reg__494: FPU__GB2,
-reg__799: VCU118RocketSystem__GC0,
-case__1525: APBGpsBlock__GC0,
-case__1471: tracking_wrapper,
-logic__2654: RocketTile__GCB0,
-logic__1623: DCache,
-logic__2022: DCache,
-datapath__164: VCU118RocketSystem__GC0,
-logic__8402: tracking_wrapper,
-logic__3857: FPU__GB1,
-logic__7535: VCU118RocketSystem__GC0,
-logic__7655: VCU118RocketSystem__GC0,
-reg__1184: tracking_wrapper,
-reg__427: FPU__GB1,
-logic__6300: VCU118RocketSystem__GC0,
-logic__1533: DCache,
-logic__2808: FPU__GB1,
-logic__1807: DCache,
-logic__543: VCU118RocketSystem__GC0,
-case__322: DCache,
-case__748: RocketTile__GCB0,
-logic__4104: FPU__GB2,
-logic__3858: FPU__GB1,
-reg__524: FPU__GB1,
-reg__669: RocketTile__GCB0,
-logic__8398: tracking_wrapper,
-logic__3826: FPU__GB1,
-datapath__564: APBGpsBlock__GC0,
-datapath__559: APBGpsBlock__GC0,
-OptimizationBarrier_TLBEntryData: RocketTile__GCB0, DCache,
-case__958: VCU118RocketSystem__GC0,
-logic__8925: TLToAPB,
-case__458: FPU__GB2, FPU__GB1,
-reg__393: FPU__GB0,
-reg__175: VCU118RocketSystem__GC0,
-case__1409: tracking_wrapper,
-datapath__555: APBGpsBlock__GC0,
-reg__993: VCU118RocketSystem__GC0,
-reg__871: VCU118RocketSystem__GC0,
-logic__533: VCU118RocketSystem__GC0,
-addsub__2: tracking_wrapper,
-reg__785: VCU118RocketSystem__GC0,
-reg__486: FPU__GB1,
-AsyncQueueSink_TLBundleA_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__4204: FPU__GB2,
-logic__6282: VCU118RocketSystem__GC0,
-logic__146: VCU118RocketSystem__GC0,
-reg__335: RocketTile__GCB0,
-logic__5380: RocketTile__GCB0,
-case__83: VCU118RocketSystem__GC0,
-reg__563: FPU__GB1,
-case__1429: tracking_wrapper,
-ram__4: VCU118RocketSystem__GC0,
-case__107: VCU118RocketSystem__GC0,
-logic__1972: DCache,
-logic__8036: APBGpsBlock__GC0,
-logic__6006: RocketTile__GCB0,
-case__605: FPU__GB1,
-logic__8874: APBGpsBlock__GC0,
-datapath__664: tracking_wrapper,
-IntSyncSyncCrossingSink_n1x1: TilePRCIDomain__GC0,
-reg__701: RocketTile__GCB0,
-reg__748: RocketTile__GCB0,
-logic__5297: RocketTile__GCB0,
-case__1089: APBGpsBlock__GC0,
-case__690: RocketTile__GCB0,
-logic__1307: VCU118RocketSystem__GC0,
-logic__2470: RocketTile__GCB0,
-reg__690: RocketTile__GCB0,
-datapath__242: DCache,
-logic__5906: RocketTile__GCB0,
-case__688: RocketTile__GCB0,
-reg__249: DCache,
-reg__477: FPU__GB1,
-logic__7031: VCU118RocketSystem__GC0,
-logic__6973: VCU118RocketSystem__GC0,
-logic__681: VCU118RocketSystem__GC0,
-logic__745: VCU118RocketSystem__GC0,
-reg__1340: TLToAPB,
-case__580: FPU__GB1,
-logic__4351: FPU__GB1,
-datapath__529: APBGpsBlock__GC0,
-logic__4558: RocketTile__GCB0,
-case__1536: TLToAPB,
-logic__2825: FPU__GB1,
-reg__1281: tracking_wrapper,
-addsub__6: tracking_wrapper,
-logic__5411: RocketTile__GCB0,
-reg__1334: tracking_wrapper,
-logic__5902: RocketTile__GCB0,
-logic__2930: FPU__GB1,
-logic__8881: APBGpsBlock__GC0,
-logic__290: VCU118RocketSystem__GC0,
-case__783: VCU118RocketSystem__GC0,
-reg__260: DCache,
-reg__675: RocketTile__GCB0,
-logic__869: VCU118RocketSystem__GC0,
-logic__5973: RocketTile__GCB0,
-case__896: VCU118RocketSystem__GC0,
-logic__905: VCU118RocketSystem__GC0,
-datapath__101: VCU118RocketSystem__GC0,
-reg__702: RocketTile__GCB0,
-logic__1075: VCU118RocketSystem__GC0,
-logic__4515: RocketTile__GCB0,
-datapath__391: RocketTile__GCB0,
-reg__548: FPU__GB1,
-logic__3025: FPU__GB2, FPU__GB1,
-logic__3736: FPU__GB1,
-logic__1359: VCU118RocketSystem__GC0,
-logic__3068: FPU__GB2,
-datapath__182: VCU118RocketSystem__GC0,
-datapath__610: APBGpsBlock__GC0,
-datapath__512: VCU118RocketSystem__GC0,
-reg__861: VCU118RocketSystem__GC0,
-muxpart__45: FPU__GB0,
-case__892: VCU118RocketSystem__GC0,
-reg__70: VCU118RocketSystem__GC0,
-logic__572: VCU118RocketSystem__GC0,
-reg__613: RocketTile__GCB0,
-reg__194: VCU118RocketSystem__GC0,
-case__483: FPU__GB2,
-datapath__620: tracking_wrapper,
-muxpart__79: FPU__GB0,
-reg__99: VCU118RocketSystem__GC0,
-datapath__282: RocketTile__GCB0,
-case__1391: tracking_wrapper,
-case__1173: APBGpsBlock__GC0,
-datapath__660: tracking_wrapper,
-logic__2329: RocketTile__GCB0,
-case__1156: APBGpsBlock__GC0,
-datapath__509: VCU118RocketSystem__GC0,
-logic__374: VCU118RocketSystem__GC0,
-case__731: RocketTile__GCB0,
-case__47: VCU118RocketSystem__GC0,
-logic__761: VCU118RocketSystem__GC0,
-logic__5995: RocketTile__GCB0,
-logic__1524: DCache,
-logic__4622: RocketTile__GCB0,
-datapath__445: RocketTile__GCB0,
-case__256: VCU118RocketSystem__GC0,
-logic__243: VCU118RocketSystem__GC0,
-case__565: FPU__GB2,
-logic__8921: APBGpsBlock__GC0,
-logic__988: VCU118RocketSystem__GC0,
-logic__4486: FPU__GB1,
-Repeater_TLBundleA_a29d32s2k1z3u: VCU118RocketSystem__GC0,
-logic__7246: VCU118RocketSystem__GC0,
-logic__4588: RocketTile__GCB0,
-counter__5: VCU118RocketSystem__GC0,
-reg__1309: tracking_wrapper,
-logic__3216: FPU__GB2,
-RecFNToIN: FPU__GB2,
-logic__5176: RocketTile__GCB0,
-datapath__171: VCU118RocketSystem__GC0,
-logic__8283: tracking_wrapper,
-datapath__583: APBGpsBlock__GC0,
-logic__4008: FPU__GB2,
-logic__3503: FPU__GB2,
-datapath__615: APBGpsBlock__GC0,
-logic__2095: DCache,
-counter__21: tracking_wrapper,
-muxpart__226: tracking_wrapper,
-logic__7006: VCU118RocketSystem__GC0,
-logic__5389: RocketTile__GCB0,
-case__799: VCU118RocketSystem__GC0,
-logic__3414: FPU__GB2,
-logic__3564: FPU__GB1,
-datapath__465: TilePRCIDomain__GC0,
-logic__8801: tracking_wrapper,
-reg__791: VCU118RocketSystem__GC0,
-reg__1158: tracking_wrapper,
-logic__3360: FPU__GB2,
-case__1384: tracking_wrapper,
-reg__76: VCU118RocketSystem__GC0,
-datapath__566: APBGpsBlock__GC0,
-reg__628: RocketTile__GCB0,
-case__917: VCU118RocketSystem__GC0,
-logic__5943: RocketTile__GCB0,
-logic__6439: VCU118RocketSystem__GC0,
-TLBusBypass: VCU118RocketSystem__GC0,
-logic__1214: VCU118RocketSystem__GC0,
-logic__5342: RocketTile__GCB0,
-logic__8727: tracking_wrapper,
-case__129: VCU118RocketSystem__GC0,
-reg__462: FPU__GB1,
-reg__1286: tracking_wrapper,
-case__304: DCache,
-logic__6744: VCU118RocketSystem__GC0,
-FixedClockBroadcast_4: VCU118RocketSystem__GC0,
-case__1479: tracking_wrapper,
-logic__6015: RocketTile__GCB0,
-datapath__214: VCU118RocketSystem__GC0,
-datapath__100: VCU118RocketSystem__GC0,
-logic__1270: VCU118RocketSystem__GC0,
-logic__3856: FPU__GB1,
-logic__1971: DCache,
-reg__265: DCache,
-rom__8: tracking_wrapper,
-logic__6803: VCU118RocketSystem__GC0,
-reg__153: VCU118RocketSystem__GC0,
-logic__7836: APBGpsBlock__GC0,
-case__1224: APBGpsBlock__GC0,
-reg__315: RocketTile__GCB0,
-logic__8304: tracking_wrapper,
-logic__5391: RocketTile__GCB0,
-datapath__126: VCU118RocketSystem__GC0,
-datapath__459: RocketTile__GCB0,
-logic__5701: RocketTile__GCB0,
-logic__4019: FPU__GB2,
-case__366: DCache,
-reg__550: FPU__GB1,
-logic__1276: VCU118RocketSystem__GC0,
-TLROM: VCU118RocketSystem__GC0,
-logic__5069: RocketTile__GCB0,
-logic__2588: RocketTile__GCB0,
-logic__4321: FPU__GB1,
-reg__816: VCU118RocketSystem__GC0,
-reg__519: FPU__GB2,
-case__648: RocketTile__GCB0,
-PMPChecker_s3: DCache,
-reg__598: RocketTile__GCB0,
-reg__262: DCache,
-case__763: RocketTile__GCB0,
-reg__908: VCU118RocketSystem__GC0,
-case__1388: tracking_wrapper,
-logic__2685: FPU__GB1,
-reg__247: DCache,
-logic__8315: tracking_wrapper,
-reg__1197: tracking_wrapper,
-logic__7567: VCU118RocketSystem__GC0,
-logic__277: VCU118RocketSystem__GC0,
-logic__292: VCU118RocketSystem__GC0,
-logic__6606: VCU118RocketSystem__GC0,
-logic__6367: VCU118RocketSystem__GC0,
-logic__7785: APBGpsBlock__GC0,
-muxpart__31: FPU__GB0,
-logic__3336: FPU__GB2,
-logic__6269: VCU118RocketSystem__GC0,
-datapath__135: VCU118RocketSystem__GC0,
-logic__3742: FPU__GB1,
-datapath__540: APBGpsBlock__GC0,
-logic__2091: DCache,
-logic__6552: VCU118RocketSystem__GC0,
-case__1457: tracking_wrapper,
-case__1033: VCU118RocketSystem__GC0,
-datapath__587: APBGpsBlock__GC0,
-logic__2777: FPU__GB1,
-logic__876: VCU118RocketSystem__GC0,
-logic__1191: VCU118RocketSystem__GC0,
-reg__1153: tracking_wrapper,
-MulAddRecFNToRaw_postMul: FPU__GB1,
-case__962: VCU118RocketSystem__GC0,
-reg__1221: tracking_wrapper,
-logic__90: genesys2_rocket_top__GC0,
-logic__3750: FPU__GB1,
-logic__6904: VCU118RocketSystem__GC0,
-reg__1144: tracking_wrapper,
-logic__6862: VCU118RocketSystem__GC0,
-logic__8236: tracking_wrapper,
-reg__1026: APBGpsBlock__GC0,
-case__595: FPU__GB1,
-TLXbar_dmixbar_i1_o2_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-case__463: FPU__GB2,
-logic__6395: VCU118RocketSystem__GC0,
-logic__1542: DCache,
-reg__793: VCU118RocketSystem__GC0,
-logic__4632: RocketTile__GCB0,
-case__365: DCache,
-logic__1987: DCache,
-logic__6219: VCU118RocketSystem__GC0,
-reg__1256: tracking_wrapper,
-logic__6710: VCU118RocketSystem__GC0,
-logic__2167: DCache,
-reg__689: RocketTile__GCB0,
-logic__1188: VCU118RocketSystem__GC0,
-logic__5326: RocketTile__GCB0,
-datapath__332: FPU__GB2,
-logic__6635: VCU118RocketSystem__GC0,
-logic__6404: VCU118RocketSystem__GC0,
-FrontBus: VCU118RocketSystem__GC0,
-reg__446: FPU__GB1,
-logic__4138: FPU__GB2,
-reg__188: VCU118RocketSystem__GC0,
-case__914: VCU118RocketSystem__GC0,
-datapath__116: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__582: RocketTile__GCB0,
-logic__3747: FPU__GB1,
-logic__5048: RocketTile__GCB0,
-reg__869: VCU118RocketSystem__GC0,
-logic__7794: APBGpsBlock__GC0,
-logic__4059: FPU__GB2,
-datapath__48: VCU118RocketSystem__GC0,
-datapath__184: VCU118RocketSystem__GC0,
-reg__744: RocketTile__GCB0,
-case__673: RocketTile__GCB0,
-logic__5304: RocketTile__GCB0,
-datapath__334: FPU__GB2,
-logic__1551: DCache,
-logic__4841: RocketTile__GCB0,
-logic__2962: FPU__GB2, FPU__GB1,
-reg__220: VCU118RocketSystem__GC0,
-datapath__124: VCU118RocketSystem__GC0,
-datapath__345: FPU__GB1,
-reg__1314: tracking_wrapper,
-datapath__271: RocketTile__GCB0,
-reg__897: VCU118RocketSystem__GC0,
-datapath__527: APBGpsBlock__GC0,
-reg__812: VCU118RocketSystem__GC0,
-logic__5197: RocketTile__GCB0,
-logic__7337: VCU118RocketSystem__GC0,
-case__236: VCU118RocketSystem__GC0,
-datapath__300: FPU__GB2, FPU__GB1,
-logic__1242: VCU118RocketSystem__GC0,
-datapath__278: RocketTile__GCB0,
-reg__17: genesys2_rocket_top__GC0,
-logic__5404: RocketTile__GCB0,
-logic__6528: VCU118RocketSystem__GC0,
-logic__5324: RocketTile__GCB0,
-case__60: VCU118RocketSystem__GC0,
-logic__6208: VCU118RocketSystem__GC0,
-reg__1196: tracking_wrapper,
-reg__1101: APBGpsBlock__GC0,
-datapath__499: VCU118RocketSystem__GC0,
-logic__2540: RocketTile__GCB0,
-reg__1235: tracking_wrapper,
-logic__6229: VCU118RocketSystem__GC0,
-logic__1257: VCU118RocketSystem__GC0,
-logic__2039: DCache,
-logic__4908: RocketTile__GCB0,
-logic__2812: FPU__GB1,
-logic__3272: FPU__GB2,
-logic__3875: FPU__GB2, FPU__GB1,
-reg__299: RocketTile__GCB0,
-case__983: VCU118RocketSystem__GC0,
-logic__7108: VCU118RocketSystem__GC0,
-logic__2833: FPU__GB1,
-reg__267: DCache,
-logic__8247: tracking_wrapper,
-muxpart__225: tracking_wrapper,
-muxpart__208: tracking_wrapper,
-logic__2994: FPU__GB2, FPU__GB1,
-datapath__533: APBGpsBlock__GC0,
-logic__6377: VCU118RocketSystem__GC0,
-logic__2966: FPU__GB2, FPU__GB1,
-datapath__269: RocketTile__GCB0,
-logic__1198: VCU118RocketSystem__GC0,
-TLFIFOFixer_1: VCU118RocketSystem__GC0,
-logic__4064: FPU__GB2,
-case__343: DCache,
-case__651: RocketTile__GCB0,
-logic__5492: RocketTile__GCB0,
-logic__6134: VCU118RocketSystem__GC0,
-logic__8877: APBGpsBlock__GC0,
-logic__2471: RocketTile__GCB0,
-reg__1034: APBGpsBlock__GC0,
-datapath__183: VCU118RocketSystem__GC0,
-logic__1706: DCache,
-datapath__594: APBGpsBlock__GC0,
-logic__2935: FPU__GB1,
-logic__4039: FPU__GB2,
-case__1401: tracking_wrapper,
-logic__430: VCU118RocketSystem__GC0,
-logic__639: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6161: VCU118RocketSystem__GC0,
-datapath__370: FPU__GB2,
-logic__2949: FPU__GB2, FPU__GB1,
-case__794: VCU118RocketSystem__GC0,
-logic__422: VCU118RocketSystem__GC0,
-logic__8867: tracking_wrapper,
-case__1482: tracking_wrapper,
-reg__1349: genesys2_rocket_top__GC0,
-logic__1318: VCU118RocketSystem__GC0,
-logic__2857: FPU__GB1,
-logic__4790: RocketTile__GCB0,
-logic__4839: RocketTile__GCB0,
-datapath__18: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__365: FPU__GB0,
-logic__383: VCU118RocketSystem__GC0,
-logic__2096: DCache,
-datapath__293: FPU__GB1,
-reg__130: VCU118RocketSystem__GC0,
-case__816: VCU118RocketSystem__GC0,
-logic__2364: RocketTile__GCB0,
-logic__8518: tracking_wrapper,
-logic__2187: DCache,
-case__70: VCU118RocketSystem__GC0,
-logic__4840: RocketTile__GCB0,
-case__502: FPU__GB1,
-case__9: genesys2_rocket_top__GC0,
-logic__6961: VCU118RocketSystem__GC0,
-logic__7654: VCU118RocketSystem__GC0,
-case__750: RocketTile__GCB0,
-reg__504: FPU__GB2,
-logic__4288: FPU__GB1,
-logic__3111: FPU__GB2,
-logic__8395: tracking_wrapper,
-logic__6795: VCU118RocketSystem__GC0,
-reg__417: FPU__GB1,
-logic__8713: tracking_wrapper,
-logic__1338: VCU118RocketSystem__GC0,
-logic__6622: VCU118RocketSystem__GC0,
-logic__6405: VCU118RocketSystem__GC0,
-datapath__121: VCU118RocketSystem__GC0,
-counter__12: APBGpsBlock__GC0,
-datapath__360: FPU__GB2, FPU__GB1,
-reg__1039: APBGpsBlock__GC0,
-logic__1435: RocketTile__GCB0,
-logic__802: VCU118RocketSystem__GC0,
-case__413: RocketTile__GCB0,
-logic__8459: tracking_wrapper,
-datapath__424: RocketTile__GCB0,
-logic__1146: VCU118RocketSystem__GC0,
-logic__4904: RocketTile__GCB0,
-muxpart__56: FPU__GB0,
-logic__2236: DCache,
-reg__1280: tracking_wrapper,
-logic__7094: VCU118RocketSystem__GC0,
-case__1015: VCU118RocketSystem__GC0,
-reg__2: genesys2_rocket_top__GC0,
-reg__217: VCU118RocketSystem__GC0,
-logic__8514: tracking_wrapper,
-case__594: FPU__GB1,
-logic__2916: FPU__GB1,
-logic__3213: FPU__GB2,
-logic__3662: FPU__GB1,
-case__124: VCU118RocketSystem__GC0,
-logic__3229: FPU__GB2,
-dsp48e1__46: tracking_wrapper,
-logic__985: VCU118RocketSystem__GC0,
-cordic_atan_one_stage__parameterized0: tracking_wrapper,
-logic__926: VCU118RocketSystem__GC0,
-logic__5483: RocketTile__GCB0,
-ShiftQueue: RocketTile__GCB0,
-reg__1117: APBGpsBlock__GC0,
-logic__6790: VCU118RocketSystem__GC0,
-reg__207: VCU118RocketSystem__GC0,
-logic__4250: FPU__GB2,
-reg__574: RocketTile__GCB0,
-logic__2649: RocketTile__GCB0,
-logic__6380: VCU118RocketSystem__GC0,
-case__173: VCU118RocketSystem__GC0,
-logic__4031: FPU__GB2,
-TLXbar_cbus_out_i1_o7_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-reg__979: VCU118RocketSystem__GC0,
-reg__173: VCU118RocketSystem__GC0,
-logic__649: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__531: APBGpsBlock__GC0,
-logic__8372: tracking_wrapper,
-case__1041: VCU118RocketSystem__GC0,
-reg__412: FPU__GB1,
-case__1091: APBGpsBlock__GC0,
-reg__903: VCU118RocketSystem__GC0,
-datapath__131: VCU118RocketSystem__GC0,
-logic__1005: VCU118RocketSystem__GC0,
-logic__2679: FPU__GB1,
-logic__7629: VCU118RocketSystem__GC0,
-case__919: VCU118RocketSystem__GC0,
-reg__1185: tracking_wrapper,
-reg__707: RocketTile__GCB0,
-reg__609: RocketTile__GCB0,
-reg__802: VCU118RocketSystem__GC0,
-case__484: FPU__GB2,
-case__318: DCache,
-logic__7036: VCU118RocketSystem__GC0,
-case__868: VCU118RocketSystem__GC0,
-case__1318: APBGpsBlock__GC0,
-datapath__611: APBGpsBlock__GC0,
-muxpart__8: VCU118RocketSystem__GC0,
-reg__450: FPU__GB1,
-reg__434: FPU__GB2,
-reg__868: VCU118RocketSystem__GC0,
-case__1395: tracking_wrapper,
-case__288: RocketTile__GCB0,
-logic__5992: RocketTile__GCB0,
-logic__4391: FPU__GB1,
-logic__534: VCU118RocketSystem__GC0,
-case__214: VCU118RocketSystem__GC0,
-logic__1869: RocketTile__GCB0, DCache,
-case__544: FPU__GB2,
-logic__3387: FPU__GB2,
-logic__3759: FPU__GB1,
-datapath__411: RocketTile__GCB0,
-reg__682: RocketTile__GCB0,
-logic__3672: FPU__GB1,
-logic__1747: DCache,
-logic__3737: FPU__GB1,
-reg__953: VCU118RocketSystem__GC0,
-case__928: VCU118RocketSystem__GC0,
-logic__1220: VCU118RocketSystem__GC0,
-datapath__626: tracking_wrapper,
-TLInterconnectCoupler_cbus_to_plic: VCU118RocketSystem__GC0,
-PeripheryBus_cbus: VCU118RocketSystem__GC0,
-case__1362: tracking_wrapper,
-muxpart__103: RocketTile__GCB0,
-reg__509: FPU__GB2,
-logic__1145: VCU118RocketSystem__GC0,
-logic__8935: TLToAPB,
-logic__1774: DCache,
-logic__119: VCU118RocketSystem__GC0,
-case__632: RocketTile__GCB0,
-datapath__353: FPU__GB1,
-logic__143: VCU118RocketSystem__GC0,
-logic__4063: FPU__GB2,
-muxpart__50: FPU__GB0,
-logic__8161: APBGpsBlock__GC0,
-case__633: RocketTile__GCB0,
-logic__1023: VCU118RocketSystem__GC0,
-reg__722: RocketTile__GCB0,
-case__869: VCU118RocketSystem__GC0,
-logic__227: VCU118RocketSystem__GC0,
-logic__3935: FPU__GB2, FPU__GB1,
-datapath__21: VCU118RocketSystem__GC0,
-logic__3047: FPU__GB1,
-logic__2940: FPU__GB2, FPU__GB1,
-logic__497: VCU118RocketSystem__GC0,
-logic__6366: VCU118RocketSystem__GC0,
-datapath__483: VCU118RocketSystem__GC0,
-logic__5040: RocketTile__GCB0,
-logic__1083: VCU118RocketSystem__GC0,
-logic__8414: tracking_wrapper,
-logic__2312: DCache,
-reg__1174: tracking_wrapper,
-logic__5332: RocketTile__GCB0,
-logic__432: VCU118RocketSystem__GC0,
-logic__442: VCU118RocketSystem__GC0,
-case__277: VCU118RocketSystem__GC0,
-case__325: DCache,
-reg__471: FPU__GB1,
-reg__696: RocketTile__GCB0,
-logic__4494: RocketTile__GCB0,
-case__608: RocketTile__GCB0,
-reg__841: VCU118RocketSystem__GC0,
-logic__5043: RocketTile__GCB0,
-logic__807: VCU118RocketSystem__GC0,
-logic__3132: FPU__GB2,
-reg__94: VCU118RocketSystem__GC0,
-reg__55: VCU118RocketSystem__GC0,
-logic__7600: VCU118RocketSystem__GC0,
-reg__416: FPU__GB1,
-datapath__52: VCU118RocketSystem__GC0,
-case: genesys2_rocket_top__GC0,
-TLFragmenter_CLINT: VCU118RocketSystem__GC0,
-logic__3108: FPU__GB2,
-datapath__362: FPU__GB1,
-case__389: RocketTile__GCB0,
-datapath__625: tracking_wrapper,
-logic__6962: VCU118RocketSystem__GC0,
-logic__6807: VCU118RocketSystem__GC0,
-logic__6567: VCU118RocketSystem__GC0,
-logic__2300: DCache,
-logic__3939: FPU__GB2, FPU__GB1,
-dual_port_ram: APBGpsBlock__GC0,
-case__442: FPU__GB1,
-case__744: RocketTile__GCB0,
-logic__7584: VCU118RocketSystem__GC0,
-datapath__230: VCU118RocketSystem__GC0,
-reg__1186: tracking_wrapper,
-logic__8796: tracking_wrapper,
-logic__1085: VCU118RocketSystem__GC0,
-logic__1207: VCU118RocketSystem__GC0,
-reg__867: VCU118RocketSystem__GC0,
-datapath__468: VCU118RocketSystem__GC0,
-logic__3534: FPU__GB1,
-logic__2174: DCache,
-logic__397: VCU118RocketSystem__GC0,
-logic__7442: VCU118RocketSystem__GC0,
-case__978: VCU118RocketSystem__GC0,
-reg__1156: tracking_wrapper,
-logic__737: VCU118RocketSystem__GC0,
-reg__360: RocketTile__GCB0,
-logic__4393: FPU__GB1,
-logic__6992: VCU118RocketSystem__GC0,
-reg__1005: APBGpsBlock__GC0,
-case__536: FPU__GB2,
-reg__426: FPU__GB1,
-logic__6523: VCU118RocketSystem__GC0,
-logic__6148: VCU118RocketSystem__GC0,
-reg__78: VCU118RocketSystem__GC0,
-ram__5: VCU118RocketSystem__GC0,
-reg__720: RocketTile__GCB0,
-VCU118RocketSystem__GC0: VCU118RocketSystem__GC0,
-reg__302: RocketTile__GCB0,
-reg__38: VCU118RocketSystem__GC0,
-logic__308: VCU118RocketSystem__GC0,
-datapath__573: APBGpsBlock__GC0,
-reg__1290: tracking_wrapper,
-logic__3063: FPU__GB2,
-case__342: DCache,
-logic__5256: RocketTile__GCB0,
-logic__5277: RocketTile__GCB0,
-logic__5362: RocketTile__GCB0,
-logic__6541: VCU118RocketSystem__GC0,
-reg__998: APBGpsBlock__GC0, tracking_wrapper,
-reg__1283: tracking_wrapper,
-logic__2926: FPU__GB1,
-logic__8657: tracking_wrapper,
-logic__1358: VCU118RocketSystem__GC0,
-logic__857: VCU118RocketSystem__GC0,
-datapath__651: tracking_wrapper,
-reg__105: VCU118RocketSystem__GC0,
-logic__8299: tracking_wrapper,
-PLICFanIn: VCU118RocketSystem__GC0,
-datapath__160: VCU118RocketSystem__GC0,
-reg__756: RocketTile__GCB0,
-logic__5368: RocketTile__GCB0,
-case__464: FPU__GB2,
-logic__4225: FPU__GB2,
-muxpart__26: FPU__GB0,
-logic__8712: tracking_wrapper,
-logic__4592: RocketTile__GCB0,
-dsp48e1__25: APBGpsBlock__GC0,
-logic__5261: RocketTile__GCB0,
-datapath__408: RocketTile__GCB0,
-logic__5309: RocketTile__GCB0,
-logic__372: VCU118RocketSystem__GC0,
-logic__3110: FPU__GB2,
-logic__6487: VCU118RocketSystem__GC0,
-logic__6226: VCU118RocketSystem__GC0,
-logic__3929: FPU__GB2, FPU__GB1,
-logic__4392: FPU__GB1,
-reg__292: RocketTile__GCB0,
-logic__7708: APBGpsBlock__GC0,
-logic__2824: FPU__GB1,
-reg__1094: APBGpsBlock__GC0,
-reg__344: RocketTile__GCB0,
-case__1163: APBGpsBlock__GC0,
-logic__6001: RocketTile__GCB0,
-logic__6650: VCU118RocketSystem__GC0,
-logic__3233: FPU__GB2,
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0: VCU118RocketSystem__GC0, APBGpsBlock__GC0,
-dsp48e1__21: APBGpsBlock__GC0,
-logic__7672: VCU118RocketSystem__GC0,
-reg__453: FPU__GB1,
-logic__6760: VCU118RocketSystem__GC0,
-case__104: VCU118RocketSystem__GC0,
-logic__5914: RocketTile__GCB0,
-logic__8021: APBGpsBlock__GC0,
-case__185: VCU118RocketSystem__GC0,
-logic__8493: tracking_wrapper,
-logic__8504: tracking_wrapper,
-case__184: VCU118RocketSystem__GC0,
-logic__5498: RocketTile__GCB0,
-logic__4293: FPU__GB1,
-reg__1163: tracking_wrapper,
-logic__6209: VCU118RocketSystem__GC0,
-logic__3391: FPU__GB2,
-datapath__213: VCU118RocketSystem__GC0,
-logic__8392: tracking_wrapper,
-logic__6669: VCU118RocketSystem__GC0,
-logic__2590: RocketTile__GCB0,
-reg__937: VCU118RocketSystem__GC0,
-NonSyncResetSynchronizerPrimitiveShiftReg_d3: TilePRCIDomain__GC0,
-logic__8221: APBGpsBlock__GC0,
-reg__1324: tracking_wrapper,
-logic__6746: VCU118RocketSystem__GC0,
-logic__2001: DCache,
-logic__4501: RocketTile__GCB0,
-case__198: VCU118RocketSystem__GC0,
-datapath__458: RocketTile__GCB0,
-logic__640: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4090: FPU__GB2,
-datapath__158: VCU118RocketSystem__GC0,
-logic__8031: APBGpsBlock__GC0,
-logic__5285: RocketTile__GCB0,
-reg__968: VCU118RocketSystem__GC0,
-case__204: VCU118RocketSystem__GC0,
-logic__226: VCU118RocketSystem__GC0,
-logic__4326: FPU__GB1,
-datapath__273: RocketTile__GCB0,
-logic__6658: VCU118RocketSystem__GC0,
-logic__6815: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_sbus_from_rockettile: VCU118RocketSystem__GC0,
-logic__7856: APBGpsBlock__GC0,
-logic__3744: FPU__GB1,
-case__1372: tracking_wrapper,
-reg__436: FPU__GB2,
-case__676: RocketTile__GCB0,
-logic__2889: FPU__GB1,
-reg__695: RocketTile__GCB0,
-datapath__20: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__1282: tracking_wrapper,
-logic__8026: APBGpsBlock__GC0,
-reg__1230: tracking_wrapper,
-counter__22: tracking_wrapper,
-case__1034: VCU118RocketSystem__GC0,
-logic__3738: FPU__GB1,
-reg__34: VCU118RocketSystem__GC0,
-datapath__244: DCache,
-logic__263: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4502: RocketTile__GCB0,
-logic__6808: VCU118RocketSystem__GC0,
-datapath__649: tracking_wrapper,
-reg__222: VCU118RocketSystem__GC0,
-logic__5390: RocketTile__GCB0,
-case__72: VCU118RocketSystem__GC0,
-datapath__534: APBGpsBlock__GC0,
-reg__1299: tracking_wrapper,
-case__1515: tracking_wrapper,
-case__889: VCU118RocketSystem__GC0,
-logic__6531: VCU118RocketSystem__GC0,
-TLFIFOFixer_2: VCU118RocketSystem__GC0,
-reg__22: VCU118RocketSystem__GC0,
-muxpart__38: FPU__GB0,
-case__1468: tracking_wrapper,
-case__677: RocketTile__GCB0,
-reg__1143: tracking_wrapper,
-case__1322: APBGpsBlock__GC0,
-logic__6211: VCU118RocketSystem__GC0,
-logic__2800: FPU__GB1,
-reg__815: VCU118RocketSystem__GC0,
-logic__223: VCU118RocketSystem__GC0,
-logic__3148: FPU__GB2,
-logic__8962: genesys2_rocket_top__GC0,
-case__1223: APBGpsBlock__GC0,
-reg__433: FPU__GB2,
-logic__1079: VCU118RocketSystem__GC0,
-case__1291: APBGpsBlock__GC0,
-datapath__83: VCU118RocketSystem__GC0,
-case__66: VCU118RocketSystem__GC0,
-logic__230: VCU118RocketSystem__GC0,
-datapath__579: APBGpsBlock__GC0,
-logic__6816: VCU118RocketSystem__GC0,
-case__363: DCache,
-logic__2412: RocketTile__GCB0,
-datapath__180: VCU118RocketSystem__GC0,
-logic__4847: RocketTile__GCB0,
-logic__4487: FPU__GB1,
-logic__253: VCU118RocketSystem__GC0,
-reg__325: RocketTile__GCB0,
-case__955: VCU118RocketSystem__GC0,
-reg__940: VCU118RocketSystem__GC0,
-case__480: FPU__GB2,
-logic__307: VCU118RocketSystem__GC0,
-case__1132: APBGpsBlock__GC0,
-case__1020: VCU118RocketSystem__GC0,
-case__858: VCU118RocketSystem__GC0,
-case__758: RocketTile__GCB0,
-reg__492: FPU__GB2,
-case__1279: APBGpsBlock__GC0,
-Queue2_TLBundleD_a32d8s1k1z4u: VCU118RocketSystem__GC0,
-reg__296: RocketTile__GCB0,
-reg__469: FPU__GB1,
-reg__973: VCU118RocketSystem__GC0,
-reg__1336: tracking_wrapper,
-logic__1813: DCache,
-logic__4680: RocketTile__GCB0,
-logic__4977: RocketTile__GCB0,
-reg__546: FPU__GB1,
-logic__222: VCU118RocketSystem__GC0,
-case__334: DCache,
-logic__3797: FPU__GB1,
-logic__1654: DCache,
-logic__1015: VCU118RocketSystem__GC0,
-logic__2269: DCache,
-logic__5296: RocketTile__GCB0,
-case__490: FPU__GB2,
-datapath__306: FPU__GB2,
-logic__3091: FPU__GB2,
-logic__6888: VCU118RocketSystem__GC0,
-case__239: VCU118RocketSystem__GC0,
-case__1100: APBGpsBlock__GC0,
-muxpart__30: FPU__GB0,
-logic__4917: RocketTile__GCB0,
-case__1094: APBGpsBlock__GC0,
-case__371: RocketTile__GCB0,
-datapath__169: VCU118RocketSystem__GC0,
-case__477: FPU__GB2,
-dsp48e1__19: APBGpsBlock__GC0,
-logic__5295: RocketTile__GCB0,
-reg__514: FPU__GB2,
-logic__1489: RocketTile__GCB0,
-logic__8219: APBGpsBlock__GC0,
-dual_port_bram__parameterized1: APBGpsBlock__GC0,
-reg__53: VCU118RocketSystem__GC0,
-logic__4746: RocketTile__GCB0,
-logic__5896: RocketTile__GCB0,
-logic__2278: DCache,
-logic__2094: DCache,
-logic__6022: RocketTile__GCB0,
-logic__8548: tracking_wrapper,
-case__626: RocketTile__GCB0,
-logic__4972: RocketTile__GCB0,
-extram__3: APBGpsBlock__GC0,
-logic__8375: tracking_wrapper,
-case__555: FPU__GB2,
-logic__7519: VCU118RocketSystem__GC0,
-logic__6605: VCU118RocketSystem__GC0,
-logic__5452: RocketTile__GCB0,
-logic__1602: DCache,
-reg__1001: APBGpsBlock__GC0,
-logic__4506: RocketTile__GCB0,
-logic__8309: tracking_wrapper,
-logic__5864: RocketTile__GCB0,
-reg__42: VCU118RocketSystem__GC0,
-logic__1248: VCU118RocketSystem__GC0,
-logic__2434: RocketTile__GCB0,
-logic__6789: VCU118RocketSystem__GC0,
-logic__1477: RocketTile__GCB0,
-reg__415: FPU__GB1,
-datapath__43: VCU118RocketSystem__GC0,
-logic__5638: RocketTile__GCB0,
-muxpart__64: FPU__GB0,
-reg__323: RocketTile__GCB0,
-case__593: FPU__GB1,
-logic__816: VCU118RocketSystem__GC0,
-case__436: RocketTile__GCB0,
-reg__1181: tracking_wrapper,
-logic__8042: APBGpsBlock__GC0,
-logic__6167: VCU118RocketSystem__GC0,
-logic__8296: tracking_wrapper,
-logic__6659: VCU118RocketSystem__GC0,
-logic__961: VCU118RocketSystem__GC0,
-logic__8425: tracking_wrapper,
-logic__4168: FPU__GB2,
-logic__1853: RocketTile__GCB0, DCache,
-logic__2673: FPU__GB1,
-case__293: RocketTile__GCB0,
-logic__13: genesys2_rocket_top__GC0,
-logic__3048: FPU__GB1,
-datapath__333: FPU__GB2,
-logic__6041: RocketTile__GCB0,
-muxpart__78: FPU__GB0,
-logic__5005: RocketTile__GCB0,
-datapath__665: tracking_wrapper,
-logic__6168: VCU118RocketSystem__GC0,
-reg__938: VCU118RocketSystem__GC0,
-logic__2203: DCache,
-reg__374: FPU__GB0,
-logic__3222: FPU__GB2,
-MulAddRecFNToRaw_preMul: FPU__GB1,
-logic__2835: FPU__GB1,
-logic__268: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__656: RocketTile__GCB0,
-logic__2778: FPU__GB1,
-reg__1154: tracking_wrapper,
-case__609: RocketTile__GCB0,
-AsyncResetRegVec_w1_i0: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__42: VCU118RocketSystem__GC0,
-logic__7607: VCU118RocketSystem__GC0,
-case__1364: tracking_wrapper,
-logic__2869: FPU__GB1,
-reg__796: VCU118RocketSystem__GC0,
-case__24: VCU118RocketSystem__GC0,
-TLFpgaSPI: VCU118RocketSystem__GC0,
-logic__519: VCU118RocketSystem__GC0,
-muxpart__59: FPU__GB0,
-reg__213: VCU118RocketSystem__GC0,
-acq_corr: APBGpsBlock__GC0,
-logic__923: VCU118RocketSystem__GC0,
-reg__289: RocketTile__GCB0,
-logic__5990: RocketTile__GCB0,
-logic__4027: FPU__GB2,
-reg__1192: tracking_wrapper,
-reg__234: DCache,
-logic__2620: RocketTile__GCB0,
-logic__5427: RocketTile__GCB0,
-muxpart__191: APBGpsBlock__GC0,
-datapath__552: APBGpsBlock__GC0,
-reg__585: RocketTile__GCB0,
-logic__140: VCU118RocketSystem__GC0,
-logic__922: VCU118RocketSystem__GC0,
-logic__306: VCU118RocketSystem__GC0,
-reg__288: RocketTile__GCB0,
-case__909: VCU118RocketSystem__GC0,
-logic__8465: tracking_wrapper,
-logic__4089: FPU__GB2,
-datapath__682: tracking_wrapper,
-reg__1243: tracking_wrapper,
-logic__6040: RocketTile__GCB0,
-case__1023: VCU118RocketSystem__GC0,
-logic__6628: VCU118RocketSystem__GC0,
-datapath__487: VCU118RocketSystem__GC0,
-logic__2827: FPU__GB1,
-logic__8616: tracking_wrapper,
-case__1127: APBGpsBlock__GC0,
-logic__5239: RocketTile__GCB0,
-logic__6721: VCU118RocketSystem__GC0,
-logic__5700: RocketTile__GCB0,
-case__1037: VCU118RocketSystem__GC0,
-logic__1521: DCache,
-logic__2964: FPU__GB2, FPU__GB1,
-logic__8624: tracking_wrapper,
-case__1537: TLToAPB,
-logic__3207: FPU__GB2,
-case__1461: tracking_wrapper,
-logic__5305: RocketTile__GCB0,
-datapath__518: VCU118RocketSystem__GC0,
-logic__145: VCU118RocketSystem__GC0,
-logic__3733: FPU__GB1,
-logic__4725: RocketTile__GCB0,
-logic__5311: RocketTile__GCB0,
-logic__8725: tracking_wrapper,
-datapath__155: VCU118RocketSystem__GC0,
-logic__4436: FPU__GB0,
-reg__263: DCache,
-logic__1890: RocketTile__GCB0, DCache,
-logic__3561: FPU__GB1,
-logic__8875: APBGpsBlock__GC0,
-IBuf: RocketTile__GCB0,
-case__1356: tracking_wrapper,
-datapath__437: RocketTile__GCB0,
-logic__5308: RocketTile__GCB0,
-logic__7307: VCU118RocketSystem__GC0,
-logic__6607: VCU118RocketSystem__GC0,
-Queue1_TLBundleD_a29d32s7k1z2u: TLToAPB,
-logic__1514: DCache,
-reg__1081: APBGpsBlock__GC0,
-TLInterconnectCoupler_sbus_from_bus_named_fbus: VCU118RocketSystem__GC0,
-logic__7510: VCU118RocketSystem__GC0,
-logic__671: VCU118RocketSystem__GC0,
-datapath__504: VCU118RocketSystem__GC0,
-logic__6348: VCU118RocketSystem__GC0,
-reg__742: RocketTile__GCB0,
-reg__1297: tracking_wrapper,
-logic__1173: VCU118RocketSystem__GC0,
-case__895: VCU118RocketSystem__GC0,
-logic__6494: VCU118RocketSystem__GC0,
-case__693: RocketTile__GCB0,
-logic__5045: RocketTile__GCB0,
-logic__7635: VCU118RocketSystem__GC0,
-reg__905: VCU118RocketSystem__GC0,
-reg__528: FPU__GB1,
-case__1350: tracking_wrapper,
-datapath__639: tracking_wrapper,
-cdc_fifo_gray_dst: tracking_wrapper,
-logic__931: VCU118RocketSystem__GC0,
-logic__3735: FPU__GB1,
-reg__206: VCU118RocketSystem__GC0,
-case__370: RocketTile__GCB0,
-logic__5849: RocketTile__GCB0,
-TLAsyncCrossingSink_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__7297: VCU118RocketSystem__GC0,
-logic__2117: DCache,
-case__918: VCU118RocketSystem__GC0,
-case__821: VCU118RocketSystem__GC0,
-datapath__117: VCU118RocketSystem__GC0,
-logic__4611: RocketTile__GCB0,
-datapath__190: VCU118RocketSystem__GC0,
-logic__8737: tracking_wrapper,
-logic__8855: tracking_wrapper,
-logic__6008: RocketTile__GCB0,
-logic__6595: VCU118RocketSystem__GC0,
-logic__3673: FPU__GB1,
-case__857: VCU118RocketSystem__GC0,
-logic__1485: RocketTile__GCB0,
-logic__8667: tracking_wrapper,
-logic__2859: FPU__GB1,
-logic__8271: tracking_wrapper,
-logic__5272: RocketTile__GCB0,
-logic__6509: VCU118RocketSystem__GC0,
-reg__1012: APBGpsBlock__GC0,
-logic__4399: FPU__GB1,
-reg__144: VCU118RocketSystem__GC0,
-IntToFP: FPU__GB2,
-reg__1231: tracking_wrapper,
-logic__147: VCU118RocketSystem__GC0,
-logic__3652: FPU__GB1,
-reg__1092: APBGpsBlock__GC0,
-datapath__415: RocketTile__GCB0,
-logic__7549: VCU118RocketSystem__GC0,
-case__1521: APBGpsBlock__GC0,
-logic__4418: FPU__GB1,
-reg__199: VCU118RocketSystem__GC0,
-datapath__163: VCU118RocketSystem__GC0,
-logic__2205: DCache,
-dsp48e1__20: APBGpsBlock__GC0,
-reg__930: VCU118RocketSystem__GC0,
-case__793: VCU118RocketSystem__GC0,
-reg__306: RocketTile__GCB0,
-datapath__151: VCU118RocketSystem__GC0,
-logic__2469: RocketTile__GCB0,
-logic__3986: FPU__GB1,
-logic__4265: FPU__GB2,
-reg__1145: tracking_wrapper,
-logic__3873: FPU__GB2, FPU__GB1,
-reg__681: RocketTile__GCB0,
-logic__3610: FPU__GB1,
-logic__8162: APBGpsBlock__GC0,
-case__455: FPU__GB2, FPU__GB1,
-logic__1889: RocketTile__GCB0, DCache,
-logic__6735: VCU118RocketSystem__GC0,
-reg__835: VCU118RocketSystem__GC0, APBGpsBlock__GC0,
-reg__413: FPU__GB1,
-logic__1192: VCU118RocketSystem__GC0,
-case__1092: APBGpsBlock__GC0,
-logic__8324: tracking_wrapper,
-case__492: FPU__GB2,
-case__761: RocketTile__GCB0,
-datapath__85: VCU118RocketSystem__GC0,
-logic__3650: FPU__GB1,
-logic__6627: VCU118RocketSystem__GC0,
-logic__1518: DCache,
-case__1217: APBGpsBlock__GC0,
-case__1518: APBGpsBlock__GC0,
-reg__1072: APBGpsBlock__GC0,
-reg__710: RocketTile__GCB0,
-case__268: VCU118RocketSystem__GC0,
-logic__631: VCU118RocketSystem__GC0,
-logic__3179: FPU__GB2,
-IntSyncAsyncCrossingSink_n1x1: TilePRCIDomain__GC0,
-logic__6502: VCU118RocketSystem__GC0,
-datapath__336: FPU__GB1,
-case__16: genesys2_rocket_top__GC0,
-logic__6558: VCU118RocketSystem__GC0,
-case__142: VCU118RocketSystem__GC0,
-reg__984: VCU118RocketSystem__GC0,
-logic__4775: RocketTile__GCB0,
-case__329: DCache,
-case__1007: VCU118RocketSystem__GC0,
-logic__6276: VCU118RocketSystem__GC0,
-case__715: RocketTile__GCB0,
-dsp48e1__22: APBGpsBlock__GC0,
-RoundRawFNToRecFN: FPU__GB2, FPU__GB1,
-datapath__677: tracking_wrapper,
-reg__481: FPU__GB1,
-logic__4862: RocketTile__GCB0,
-case__1281: APBGpsBlock__GC0,
-case__611: RocketTile__GCB0,
-logic__2113: DCache,
-datapath__438: RocketTile__GCB0,
-logic__6630: VCU118RocketSystem__GC0,
-logic__5046: RocketTile__GCB0,
-muxpart__81: FPU__GB0,
-case__760: RocketTile__GCB0,
-logic__2568: RocketTile__GCB0,
-logic__6615: VCU118RocketSystem__GC0,
-logic__5628: RocketTile__GCB0,
-case__870: VCU118RocketSystem__GC0,
-reg__719: RocketTile__GCB0,
-reg__535: FPU__GB2,
-muxpart__52: FPU__GB0,
-logic__6750: VCU118RocketSystem__GC0,
-logic__2795: FPU__GB1,
-logic__3528: FPU__GB1,
-datapath__6: VCU118RocketSystem__GC0,
-counter__10: APBGpsBlock__GC0,
-logic__1566: DCache,
-logic__5406: RocketTile__GCB0,
-reg__1: genesys2_rocket_top__GC0,
-reg__304: RocketTile__GCB0,
-logic__74: genesys2_rocket_top__GC0,
-logic__714: VCU118RocketSystem__GC0,
-logic__676: VCU118RocketSystem__GC0,
-logic__4973: RocketTile__GCB0,
-logic__4744: RocketTile__GCB0,
-logic__2553: RocketTile__GCB0,
-logic__6717: VCU118RocketSystem__GC0,
-dsp48e1__11: APBGpsBlock__GC0,
-logic__3653: FPU__GB1,
-logic__1591: DCache,
-datapath__313: FPU__GB2,
-muxpart__71: FPU__GB0,
-datapath__631: tracking_wrapper,
-logic__431: VCU118RocketSystem__GC0,
-reg__1318: tracking_wrapper,
-datapath__235: VCU118RocketSystem__GC0,
-logic__7931: APBGpsBlock__GC0,
-logic__5477: RocketTile__GCB0,
-logic__5338: RocketTile__GCB0,
-reg__724: RocketTile__GCB0,
-muxpart__224: tracking_wrapper,
-logic__2368: RocketTile__GCB0,
-logic__4384: FPU__GB1,
-muxpart__117: VCU118RocketSystem__GC0,
-datapath__186: VCU118RocketSystem__GC0,
-logic__8220: APBGpsBlock__GC0,
-datapath__661: tracking_wrapper,
-logic__1901: DCache,
-dsp48e1__27: APBGpsBlock__GC0,
-case__379: RocketTile__GCB0,
-logic__1197: VCU118RocketSystem__GC0,
-case__327: DCache,
-reg__244: DCache,
-logic__5367: RocketTile__GCB0,
-reg__1080: APBGpsBlock__GC0,
-datapath__601: APBGpsBlock__GC0,
-spill_register: tracking_wrapper,
-datapath__448: RocketTile__GCB0,
-case__1122: APBGpsBlock__GC0,
-case__1320: APBGpsBlock__GC0,
-case__1370: tracking_wrapper,
-reg__595: RocketTile__GCB0,
-logic__2794: FPU__GB1,
-logic__2477: RocketTile__GCB0,
-case__286: RocketTile__GCB0,
-logic__275: VCU118RocketSystem__GC0,
-reg__1323: tracking_wrapper,
-logic__6497: VCU118RocketSystem__GC0,
-logic__2399: RocketTile__GCB0,
-logic__3332: FPU__GB2,
-reg__1075: APBGpsBlock__GC0,
-logic__7306: VCU118RocketSystem__GC0,
-logic__7588: VCU118RocketSystem__GC0,
-logic__7837: APBGpsBlock__GC0,
-case__551: FPU__GB2,
-logic__1801: DCache,
-logic__4860: RocketTile__GCB0,
-logic__5302: RocketTile__GCB0,
-case__1024: VCU118RocketSystem__GC0,
-INToRecFN: FPU__GB2,
-dsp48e1__33: tracking_wrapper,
-logic__5038: RocketTile__GCB0,
-logic__2855: FPU__GB1,
-logic__7380: VCU118RocketSystem__GC0,
-reg__758: RocketTile__GCB0,
-logic__875: VCU118RocketSystem__GC0,
-logic__8466: tracking_wrapper,
-logic__4761: RocketTile__GCB0,
-reg__1009: APBGpsBlock__GC0,
-datapath__367: FPU__GB2,
-logic__3776: FPU__GB1,
-logic__5343: RocketTile__GCB0,
-logic__5704: RocketTile__GCB0,
-extram__6: APBGpsBlock__GC0,
-reg__58: VCU118RocketSystem__GC0,
-reg__150: VCU118RocketSystem__GC0,
-logic__3698: FPU__GB1,
-datapath__185: VCU118RocketSystem__GC0,
-logic__8508: tracking_wrapper,
-TLXbar_fbus_i1_o1_a32d64s1k1z4u: VCU118RocketSystem__GC0,
-logic__272: VCU118RocketSystem__GC0,
-case__451: FPU__GB2, FPU__GB1,
-datapath__233: VCU118RocketSystem__GC0,
-logic__1537: DCache,
-logic__5929: RocketTile__GCB0,
-logic__921: VCU118RocketSystem__GC0,
-logic__5148: RocketTile__GCB0,
-logic__514: VCU118RocketSystem__GC0,
-reg__991: VCU118RocketSystem__GC0,
-reg__61: VCU118RocketSystem__GC0,
-datapath__92: VCU118RocketSystem__GC0,
-reg__479: FPU__GB1,
-logic__4867: RocketTile__GCB0,
-reg__520: FPU__GB2,
-case__1307: APBGpsBlock__GC0,
-case__297: RocketTile__GCB0,
-reg__164: VCU118RocketSystem__GC0,
-logic__7930: APBGpsBlock__GC0,
-logic__6291: VCU118RocketSystem__GC0,
-TLToAPB: TLToAPB,
-logic__8311: tracking_wrapper,
-logic__8359: tracking_wrapper,
-datapath__307: FPU__GB2,
-logic__6590: VCU118RocketSystem__GC0,
-logic__873: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a26d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__3238: FPU__GB2,
-reg__54: VCU118RocketSystem__GC0,
-reg__584: RocketTile__GCB0,
-datapath__634: tracking_wrapper,
-logic__1644: DCache,
-reg__369: FPU__GB0,
-logic__3999: FPU__GB2,
-datapath__280: RocketTile__GCB0,
-case__1431: tracking_wrapper,
-case__1421: tracking_wrapper,
-logic__6536: VCU118RocketSystem__GC0,
-logic__5273: RocketTile__GCB0,
-case__977: VCU118RocketSystem__GC0,
-logic__6916: VCU118RocketSystem__GC0,
-keep__7: tracking_wrapper,
-logic__5096: RocketTile__GCB0,
-logic__7216: VCU118RocketSystem__GC0,
-DCacheDataArray: DCache,
-logic__4615: RocketTile__GCB0,
-logic__5388: RocketTile__GCB0,
-muxpart__193: APBGpsBlock__GC0,
-logic__6393: VCU118RocketSystem__GC0,
-logic__3840: FPU__GB1,
-reg__239: DCache,
-datapath__433: RocketTile__GCB0,
-logic__3692: FPU__GB1,
-logic__6801: VCU118RocketSystem__GC0,
-logic__4571: RocketTile__GCB0,
-logic__7075: VCU118RocketSystem__GC0,
-dsp48e1__36: tracking_wrapper,
-reg__740: RocketTile__GCB0,
-datapath__159: VCU118RocketSystem__GC0,
-logic__2535: RocketTile__GCB0,
-logic__3243: FPU__GB2,
-reg__1223: tracking_wrapper,
-logic__4751: RocketTile__GCB0,
-reg__237: DCache,
-logic__6738: VCU118RocketSystem__GC0,
-logic__5178: RocketTile__GCB0,
-logic__6621: VCU118RocketSystem__GC0,
-logic__529: VCU118RocketSystem__GC0,
-logic__1596: DCache,
-logic__2847: FPU__GB1,
-logic__2030: DCache,
-logic__2849: FPU__GB1,
-logic__3764: FPU__GB1,
-case__960: VCU118RocketSystem__GC0,
-case__804: VCU118RocketSystem__GC0,
-logic__209: VCU118RocketSystem__GC0,
-datapath__209: VCU118RocketSystem__GC0,
-logic__8683: tracking_wrapper,
-logic__2171: DCache,
-counter__20: tracking_wrapper,
-reg__577: RocketTile__GCB0,
-datapath__37: VCU118RocketSystem__GC0,
-logic__5345: RocketTile__GCB0,
-reg__834: VCU118RocketSystem__GC0, APBGpsBlock__GC0,
-reg__284: DCache,
-logic__8403: tracking_wrapper,
-logic__6076: TilePRCIDomain__GC0,
-datapath__317: FPU__GB2,
-logic__7601: VCU118RocketSystem__GC0,
-logic__3638: FPU__GB1,
-logic__8626: tracking_wrapper,
-logic__1822: DCache,
-logic__5180: RocketTile__GCB0,
-logic__6321: VCU118RocketSystem__GC0,
-datapath__227: VCU118RocketSystem__GC0,
-reg__886: VCU118RocketSystem__GC0,
-logic__629: VCU118RocketSystem__GC0,
-logic__4968: RocketTile__GCB0,
-reg__1211: tracking_wrapper,
-FPU__GB1: FPU__GB1,
-case__567: FPU__GB1,
-reg__464: FPU__GB1,
-logic__8250: tracking_wrapper,
-reg__592: RocketTile__GCB0,
-logic__7459: VCU118RocketSystem__GC0,
-logic__5316: RocketTile__GCB0,
-reg__248: DCache,
-logic__6222: VCU118RocketSystem__GC0,
-TLWidthWidget8_4: VCU118RocketSystem__GC0,
-reg__508: FPU__GB2,
-logic__1223: VCU118RocketSystem__GC0,
-logic__8623: tracking_wrapper,
-logic__1714: DCache,
-logic__700: VCU118RocketSystem__GC0,
-reg__1044: APBGpsBlock__GC0,
-reg__655: RocketTile__GCB0,
-logic__1313: VCU118RocketSystem__GC0,
-case__999: VCU118RocketSystem__GC0,
-datapath__162: VCU118RocketSystem__GC0,
-datapath__476: VCU118RocketSystem__GC0,
-case__534: FPU__GB2,
-logic__3323: FPU__GB2,
-logic__2676: FPU__GB1,
-logic__144: VCU118RocketSystem__GC0,
-logic__6639: VCU118RocketSystem__GC0,
-case__817: VCU118RocketSystem__GC0,
-keep: APBGpsBlock__GC0, tracking_wrapper,
-logic__2887: FPU__GB1,
-logic__6586: VCU118RocketSystem__GC0,
-logic__8879: APBGpsBlock__GC0,
-logic__3140: FPU__GB2,
-logic__5433: RocketTile__GCB0,
-reg__560: FPU__GB1,
-case__635: RocketTile__GCB0,
-case__726: RocketTile__GCB0,
-datapath__539: APBGpsBlock__GC0,
-datapath__264: RocketTile__GCB0,
-datapath__315: FPU__GB2,
-logic__3845: FPU__GB1,
-reg__533: FPU__GB1,
-muxpart__16: RocketTile__GCB0,
-reg__36: VCU118RocketSystem__GC0,
-logic__1414: RocketTile__GCB0,
-reg__1099: APBGpsBlock__GC0,
-datapath__678: tracking_wrapper,
-case__1175: APBGpsBlock__GC0,
-reg__778: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__192: VCU118RocketSystem__GC0,
-case__1057: APBGpsBlock__GC0,
-case__1294: APBGpsBlock__GC0,
-case__392: RocketTile__GCB0,
-ram: VCU118RocketSystem__GC0,
-logic__7154: VCU118RocketSystem__GC0,
-logic__3403: FPU__GB2,
-case__499: FPU__GB1,
-logic__4952: RocketTile__GCB0,
-reg__920: VCU118RocketSystem__GC0,
-logic__6794: VCU118RocketSystem__GC0,
-reg__280: DCache,
-trck_cntrl: tracking_wrapper,
-reg__1262: tracking_wrapper,
-reg__51: VCU118RocketSystem__GC0,
-logic__6559: VCU118RocketSystem__GC0,
-logic__5266: RocketTile__GCB0,
-logic__5899: RocketTile__GCB0,
-logic__2664: RocketTile__GCB0,
-logic__5298: RocketTile__GCB0,
-logic__7395: VCU118RocketSystem__GC0,
-logic__1900: DCache,
-logic__6418: VCU118RocketSystem__GC0,
-logic__2365: RocketTile__GCB0,
-case__34: VCU118RocketSystem__GC0,
-dsp48e1__38: tracking_wrapper,
-case__1005: VCU118RocketSystem__GC0,
-logic__6190: VCU118RocketSystem__GC0,
-reg__1170: tracking_wrapper,
-logic__425: VCU118RocketSystem__GC0,
-case__764: RocketTile__GCB0,
-reg__819: VCU118RocketSystem__GC0,
-reg__118: VCU118RocketSystem__GC0,
-logic__3268: FPU__GB2,
-reg__407: FPU__GB1,
-logic__4334: FPU__GB1,
-logic__6666: VCU118RocketSystem__GC0,
-logic__4700: RocketTile__GCB0,
-logic__2787: FPU__GB1,
-logic__7547: VCU118RocketSystem__GC0,
-datapath__11: VCU118RocketSystem__GC0,
-reg__1141: tracking_wrapper,
-datapath__309: FPU__GB2,
-muxpart__53: FPU__GB0,
-case__1396: tracking_wrapper,
-logic__7606: VCU118RocketSystem__GC0,
-logic__7048: VCU118RocketSystem__GC0,
-case__175: VCU118RocketSystem__GC0,
-logic__4743: RocketTile__GCB0,
-case__540: FPU__GB2,
-datapath__301: FPU__GB2, FPU__GB1,
-datapath__284: RocketTile__GCB0,
-MulDiv: RocketTile__GCB0,
-muxpart__9: VCU118RocketSystem__GC0,
-reg__668: RocketTile__GCB0,
-logic__4528: RocketTile__GCB0,
-muxpart__24: FPU__GB0,
-datapath__22: VCU118RocketSystem__GC0,
-logic__1587: DCache,
-reg__1271: tracking_wrapper,
-reg__709: RocketTile__GCB0,
-keep__8: tracking_wrapper,
-logic__2541: RocketTile__GCB0,
-datapath__316: FPU__GB2,
-rom__7: tracking_wrapper,
-logic__4167: FPU__GB2,
-logic: genesys2_rocket_top__GC0,
-logic__2079: DCache,
-ram_2x115: TilePRCIDomain__GC0,
-logic__6501: VCU118RocketSystem__GC0,
-logic__2067: DCache,
-logic__1816: DCache,
-logic__1666: DCache,
-logic__304: VCU118RocketSystem__GC0,
-dsp48e1__14: APBGpsBlock__GC0,
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/e/elab.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/e/elab.rtd
deleted file mode 100644
index 3294868..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/e/elab.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1220760385.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1220760385.rtd
deleted file mode 100644
index 5f34e35..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index e6a6263..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1294509424.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1294509424.rtd
deleted file mode 100644
index a524ca3..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index b1e86e3..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/136113302.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/136113302.rtd
deleted file mode 100644
index 3776756..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd
deleted file mode 100644
index 9cf52fc..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1672436263.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1672436263.rtd
deleted file mode 100644
index f8b85a5..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index 09b8250..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2438764479.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2438764479.rtd
deleted file mode 100644
index 2adab3b..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2438764479.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd
deleted file mode 100644
index 33fabfe..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2438764479.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2610937407.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2610937407.rtd
deleted file mode 100644
index 29b8096..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index 6e4b38e..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2737226844.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2737226844.rtd
deleted file mode 100644
index cafad1d..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index 04d873b..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2962621930.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2962621930.rtd
deleted file mode 100644
index b188563..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index 72f77d9..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3482045580.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3482045580.rtd
deleted file mode 100644
index b993e3a..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index f08a185..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3990655999.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3990655999.rtd
deleted file mode 100644
index c4bb8ea..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3990655999.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd
deleted file mode 100644
index b614909..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/3990655999.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/976197094.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/976197094.rtd
deleted file mode 100644
index e7a91a9..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd
deleted file mode 100644
index 4285670..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/global_name.straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/global_name.straps.rtd
deleted file mode 100644
index be495e9..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/instToEncGenName.map b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/instToEncGenName.map
deleted file mode 100644
index 991ffa8..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/g/instToEncGenName.map
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/genesys2_rocket_top__GC0:3990655999
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0:2438764479
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/genomeDependencyGraph.out b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/genomeDependencyGraph.out
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/genomes.map b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/genomes.map
deleted file mode 100644
index 61341d1..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/genomes.map
+++ /dev/null
@@ -1,11 +0,0 @@
-FPU__GB0 88C687C0
-FPU__GB1 55CCF5C0
-FPU__GB2 82A8DC80
-RocketTile__GCB0 59376600
-DCache 55D97040
-TilePRCIDomain__GC0 6BE153A0
-tracking_wrapper 79F91720
-APBGpsBlock__GC0 5655A480
-TLToAPB 6D2DBAE0
-VCU118RocketSystem__GC0 5278D140
-genesys2_rocket_top__GC0 7BDD0DC0
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/genomes.txt b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/genomes.txt
deleted file mode 100644
index 52ed2bc..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/genomes.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-FPU__GB0
-FPU__GB1
-FPU__GB2
-RocketTile__GCB0
-DCache
-TilePRCIDomain__GC0
-tracking_wrapper
-APBGpsBlock__GC0
-TLToAPB
-VCU118RocketSystem__GC0
-genesys2_rocket_top__GC0
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/parentModToGenomes.map b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/parentModToGenomes.map
deleted file mode 100644
index 7861bfe..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/parentModToGenomes.map
+++ /dev/null
@@ -1,8 +0,0 @@
-genesys2_rocket_top: FPU__GB2, RocketTile__GCB0, FPU__GB1, APBGpsBlock__GC0, tracking_wrapper, VCU118RocketSystem__GC0, genesys2_rocket_top__GC0, TilePRCIDomain__GC0, DCache, FPU__GB0, TLToAPB,
-VCU118RocketSystem: FPU__GB2, RocketTile__GCB0, FPU__GB1, APBGpsBlock__GC0, tracking_wrapper, VCU118RocketSystem__GC0, TilePRCIDomain__GC0, DCache, FPU__GB0, TLToAPB,
-FPGAGPSClockSinkDomain: TLToAPB, APBGpsBlock__GC0, tracking_wrapper,
-APBGpsBlock: APBGpsBlock__GC0, tracking_wrapper,
-TilePRCIDomain: TilePRCIDomain__GC0, RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-HierarchicalElementResetDomain: RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-RocketTile: RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-FPU: FPU__GB2, FPU__GB1, FPU__GB0,
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/synthNameToElabName.map b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/synthNameToElabName.map
deleted file mode 100644
index 97e3373..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/synthNameToElabName.map
+++ /dev/null
@@ -1,8658 +0,0 @@
-reg__151: reg__151
-case__1295: case__1295
-reg__418: reg__418
-logic__989: logic__989
-logic__3298: logic__3298
-reg__1055: reg__1055
-logic__2683: logic__2683
-logic__6386: logic__6386
-logic__6278: logic__6278
-case__624: case__624
-case__28: case__28
-logic__833: logic__833
-logic__563: logic__563
-datapath__729: datapath__649
-logic__8669: logic__8669
-logic__1163: logic__1163
-datapath__218: datapath__218
-logic__6449: logic__6449
-logic__1819: logic__1819
-dsp48e1__15: dsp48e1__15
-logic__503: logic__503
-logic__4503: logic__4503
-case__168: case__168
-case__354: case__354
-case__1399: case__1399
-reg__1139: reg__1139
-logic__9201: logic__1548
-logic__2627: logic__2627
-logic__6890: logic__6890
-keep__42: keep__1
-logic__5387: logic__5387
-logic__6739: logic__6739
-keep__4: keep__4
-reg__250: reg__250
-datapath__547: datapath__547
-datapath__726: datapath__652
-case__263: case__263
-logic__438: logic__438
-datapath__570: datapath__570
-logic__4226: logic__4226
-logic__9180: logic__1595
-logic__4079: logic__4079
-logic__3849: logic__3849
-logic__7386: logic__7386
-case__224: case__224
-case__1549: case__450
-reg__274: reg__274
-muxpart__228: muxpart__228
-case__1568: case__311
-datapath__586: datapath__586
-case__589: case__589
-reg__168: reg__168
-logic__764: logic__764
-logic__4356: logic__4356
-logic__3516: logic__3516
-case__1575: case__304
-logic__3568: logic__3568
-counter__25: counter__25
-case__647: case__647
-logic__7349: logic__7349
-case__1063: case__1063
-datapath__142: datapath__142
-logic__9110: logic__1804
-cordic_atan_one_stage: cordic_atan_one_stage
-case__386: case__386
-reg__489: reg__489
-reg__1351: reg__778
-reg__425: reg__425
-case__591: case__591
-datapath__194: datapath__194
-logic__9107: logic__1813
-logic__3654: logic__3654
-logic__6394: logic__6394
-logic__2019: logic__2019
-case__519: case__519
-datapath__698: datapath__359
-logic__7210: logic__7210
-reg__1241: reg__1241
-logic__5300: logic__5300
-logic__3815: logic__3815
-reg__544: reg__544
-reg__1220: reg__1220
-logic__6753: logic__6753
-logic__2165: logic__2165
-logic__3745: logic__3745
-datapath__215: datapath__215
-case__69: case__69
-logic__2704: logic__2704
-case__685: case__685
-logic__5317: logic__5317
-reg__1327: reg__1327
-logic__9223: logic__1504
-case__1585: case__1408
-logic__765: logic__765
-case__718: case__718
-keep__40: keep__1
-logic__2413: logic__2413
-keep__35: keep__8
-case__1011: case__1011
-datapath__537: datapath__537
-case__1045: case__1045
-TLInterconnectCoupler_pbus_to_gps: TLInterconnectCoupler_pbus_to_gps
-logic__8448: logic__8448
-logic__9128: logic__1745
-logic__7542: logic__7542
-logic__298: logic__298
-logic__5051: logic__5051
-logic__6751: logic__6751
-logic__6814: logic__6814
-reg__1036: reg__1036
-datapath__187: datapath__187
-logic__5257: logic__5257
-case__424: case__424
-case__562: case__562
-logic__3600: logic__3600
-logic__9235: logic__649
-logic__2191: logic__2191
-case__828: case__828
-logic__1142: logic__1142
-logic__525: logic__525
-case__878: case__878
-logic__4060: logic__4060
-case__478: case__478
-logic__5299: logic__5299
-logic__6071: logic__6071
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__6: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6610: logic__6610
-logic__9196: logic__1559
-logic__6806: logic__6806
-logic__9215: logic__1518
-logic__7363: logic__7363
-ram__12: ram__4
-logic__7777: logic__7777
-logic__4368: logic__4368
-logic__5971: logic__5971
-case__1589: case__1404
-case__1331: case__1331
-datapath__703: datapath__248
-case__1540: case__1540
-logic__7920: logic__7920
-reg__429: reg__429
-logic__6162: logic__6162
-logic__8783: logic__8783
-case__848: case__848
-reg__912: reg__912
-logic__1453: logic__1453
-ClockGroup__1: ClockGroup
-logic__673: logic__673
-logic__4419: logic__4419
-reg__1268: reg__1268
-case__156: case__156
-reg__646: reg__646
-case__1226: case__1226
-reg__960: reg__960
-logic__228: logic__228
-reg__1079: reg__1079
-dsp48e1__9: dsp48e1__9
-logic__5917: logic__5917
-logic__4645: logic__4645
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__16: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__3456: logic__3456
-logic__8656: logic__8656
-logic__6611: logic__6611
-logic__3404: logic__3404
-muxpart__42: muxpart__42
-logic__7383: logic__7383
-counter__4: counter__4
-datapath__152: datapath__152
-logic__3720: logic__3720
-muxpart__54: muxpart__54
-logic__2666: logic__2666
-logic__5301: logic__5301
-logic__9139: logic__1706
-logic__6036: logic__6036
-reg__1432: reg__833
-logic__6309: logic__6309
-logic__971: logic__971
-case__1478: case__1478
-logic__4976: logic__4976
-logic__4591: logic__4591
-datapath__731: datapath__647
-reg__641: reg__641
-reg__941: reg__941
-logic__8052: logic__8052
-datapath__374: datapath__374
-case__1439: case__1439
-reg__806: reg__806
-logic__6612: logic__6612
-logic__915: logic__915
-logic__842: logic__842
-reg__454: reg__454
-reg__1161: reg__1161
-case__1427: case__1427
-datapath__231: datapath__231
-reg__1078: reg__1078
-logic__5293: logic__5293
-logic__1645: logic__1645
-logic__9007: logic__3935
-reg__1064: reg__1064
-reg__334: reg__334
-case__1422: case__1422
-logic__3178: logic__3178
-logic__1974: logic__1974
-AsyncQueueSource_TLBundleA_a9d32s1k1z2u: AsyncQueueSource_TLBundleA_a9d32s1k1z2u
-logic__4529: logic__4529
-logic__5412: logic__5412
-logic__8618: logic__8618
-logic__900: logic__900
-reg__44: reg__44
-datapath__188: datapath__188
-reg__522: reg__522
-logic__4747: logic__4747
-reg__764: reg__764
-logic__1870: logic__1870
-case__1138: case__1138
-logic__7399: logic__7399
-logic__5315: logic__5315
-datapath__497: datapath__497
-datapath__750: datapath__14
-muxpart__25: muxpart__25
-datapath__195: datapath__195
-case__311: case__311
-case__152: case__152
-keep__6: keep__6
-logic__7566: logic__7566
-logic__6098: logic__6098
-case__155: case__155
-reg__40: reg__40
-case__1477: case__1477
-logic__6602: logic__6602
-logic__2653: logic__2653
-reg__525: reg__525
-datapath__17: datapath__17
-logic__9032: logic__3872
-logic__3527: logic__3527
-logic__6812: logic__6812
-datapath__35: datapath__35
-logic__9098: logic__1832
-logic__1983: logic__1983
-logic__3586: logic__3586
-logic__8368: logic__8368
-logic__4704: logic__4704
-datapath__150: datapath__150
-case__1555: case__522
-logic__803: logic__803
-logic__9218: logic__1511
-logic__6313: logic__6313
-logic__1297: logic__1297
-logic__1909: logic__1909
-case__879: case__879
-reg__1245: reg__1245
-logic__3267: logic__3267
-logic__1782: logic__1782
-case__1467: case__1467
-datapath__550: datapath__550
-logic__4195: logic__4195
-reg__1498: reg__833
-logic__2476: logic__2476
-logic__8116: logic__8116
-logic__5294: logic__5294
-reg__162: reg__162
-logic__152: logic__152
-logic__8452: logic__8452
-logic__9313: logic__470
-datapath__575: datapath__575
-reg__685: reg__685
-logic__9141: logic__1702
-reg__32: reg__32
-case__766: case__766
-datapath__120: datapath__120
-case__1292: case__1292
-logic__3237: logic__3237
-reg__1025: reg__1025
-logic__4516: logic__4516
-logic__9292: logic__946
-logic__299: logic__299
-reg__451: reg__451
-logic__4809: logic__4809
-logic__4527: logic__4527
-logic__2356: logic__2356
-logic__8497: logic__8497
-case__671: case__671
-reg__1233: reg__1233
-case__727: case__727
-reg__831: reg__831
-logic__8429: logic__8429
-datapath__515: datapath__515
-logic__630: logic__630
-logic__5465: logic__5465
-case__891: case__891
-muxpart__15: muxpart__15
-logic__3212: logic__3212
-reg__963: reg__963
-logic__8670: logic__8670
-datapath__143: datapath__143
-muxpart__92: muxpart__92
-reg__375: reg__375
-logic__6029: logic__6029
-logic__2628: logic__2628
-logic__6496: logic__6496
-case__639: case__639
-datapath__718: datapath__115
-logic__9152: logic__1665
-datapath__441: datapath__441
-reg__1053: reg__1053
-logic__5857: logic__5857
-logic__5999: logic__5999
-logic__69: logic__69
-reg__367: reg__367
-reg__810: reg__810
-case__261: case__261
-reg__929: reg__929
-case__991: case__991
-logic__8917: logic__8917
-case__217: case__217
-logic__9089: logic__1859
-double_ff_syn: double_ff_syn
-logic__1694: logic__1694
-logic__3987: logic__3987
-logic__339: logic__339
-reg__309: reg__309
-logic__8496: logic__8496
-logic__8262: logic__8262
-reg__612: reg__612
-reg__4: reg__4
-logic__6414: logic__6414
-reg__983: reg__983
-datapath__495: datapath__495
-datapath__114: datapath__114
-logic__7234: logic__7234
-reg__181: reg__181
-logic__7166: logic__7166
-reg__205: reg__205
-datapath__165: datapath__165
-logic__5314: logic__5314
-logic__9273: logic__6125
-logic__1157: logic__1157
-muxpart__115: muxpart__115
-reg__340: reg__340
-logic__3859: logic__3859
-logic__8396: logic__8396
-case__687: case__687
-reg__1450: reg__833
-logic__6614: logic__6614
-logic__1627: logic__1627
-reg__586: reg__586
-reg__814: reg__814
-logic__9127: logic__1746
-logic__8404: logic__8404
-logic__5290: logic__5290
-logic__231: logic__231
-logic__3813: logic__3813
-logic__2418: logic__2418
-case__861: case__861
-case__1486: case__1486
-logic__3739: logic__3739
-logic__7051: logic__7051
-logic__3844: logic__3844
-case__1561: case__318
-logic__8115: logic__8115
-case__520: case__520
-logic__8541: logic__8541
-datapath__189: datapath__189
-datapath__592: datapath__592
-case__446: case__446
-dsp48e1__3: dsp48e1__3
-logic__164: logic__164
-reg__547: reg__547
-logic__7385: logic__7385
-logic__4275: logic__4275
-logic__8914: logic__8914
-datapath__24: datapath__24
-extram__7: extram__7
-case__910: case__910
-logic__4337: logic__4337
-logic__52: logic__52
-logic__9093: logic__1847
-logic__3465: logic__3465
-logic__6557: logic__6557
-logic__295: logic__295
-logic__3163: logic__3163
-logic__5435: logic__5435
-logic__8513: logic__8513
-logic__2569: logic__2569
-ram_2x123__1: ram_2x123
-case__597: case__597
-logic__8711: logic__8711
-datapath__511: datapath__511
-case__471: case__471
-reg__1481: reg__835
-reg__1097: reg__1097
-logic__4335: logic__4335
-logic__3185: logic__3185
-logic__4209: logic__4209
-logic__6752: logic__6752
-logic__1507: logic__1507
-logic__3146: logic__3146
-logic__9183: logic__1588
-logic__7957: logic__7957
-reg__75: reg__75
-logic__5369: logic__5369
-TLFragmenter_FPGAUART: TLFragmenter_FPGAUART
-logic__9254: logic__8234
-logic__8698: logic__8698
-logic__5039: logic__5039
-logic__5991: logic__5991
-logic__871: logic__871
-logic__8126: logic__8126
-case__1363: case__1363
-logic__8817: logic__8817
-case__391: case__391
-AsyncResetSynchronizerShiftReg_w1_d3_i0: AsyncResetSynchronizerShiftReg_w1_d3_i0
-reg__114: reg__114
-datapath__683: datapath__683
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__13: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__4428: logic__4428
-logic__4279: logic__4279
-logic__1785: logic__1785
-logic__3756: logic__3756
-datapath__73: datapath__73
-logic__4336: logic__4336
-reg__882: reg__882
-datapath__240: datapath__240
-logic__7628: logic__7628
-logic__3186: logic__3186
-logic__9199: logic__1552
-logic__250: logic__250
-logic__4174: logic__4174
-case__23: case__23
-case__610: case__610
-case__704: case__704
-reg__962: reg__962
-logic__9279: logic__6125
-logic__7617: logic__7617
-logic__7558: logic__7558
-logic__3361: logic__3361
-logic__3569: logic__3569
-logic__7751: logic__7751
-reg__1524: reg__61
-logic__2971: logic__2971
-logic__6491: logic__6491
-reg__1506: reg__783
-logic__4524: logic__4524
-reg__366: reg__366
-logic__2632: logic__2632
-datapath__119: datapath__119
-logic__8310: logic__8310
-keep__25: keep__6
-case__192: case__192
-logic__9226: logic__269
-logic__7764: logic__7764
-logic__2910: logic__2910
-logic__5936: logic__5936
-reg__1046: reg__1046
-logic__3757: logic__3757
-dsp48e1__30: dsp48e1__30
-logic__9187: logic__1578
-muxpart__32: muxpart__32
-datapath__56: datapath__56
-datapath__593: datapath__593
-logic__3846: logic__3846
-logic__3282: logic__3282
-logic__2659: logic__2659
-logic__5279: logic__5279
-logic__6613: logic__6613
-datapath__30: datapath__30
-reg__1368: reg__1248
-logic__3438: logic__3438
-logic__4158: logic__4158
-logic__4539: logic__4539
-logic__2577: logic__2577
-case__17: case__17
-case__941: case__941
-logic__8127: logic__8127
-reg__881: reg__881
-logic__8467: logic__8467
-case__1335: case__1335
-reg__667: reg__667
-reg__420: reg__420
-logic__2929: logic__2929
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__15: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__171: reg__171
-logic__462: logic__462
-reg__1175: reg__1175
-logic__4603: logic__4603
-reg__1126: reg__1126
-reg__1273: reg__1273
-logic__5407: logic__5407
-logic__3848: logic__3848
-logic__6591: logic__6591
-logic__2694: logic__2694
-logic__9192: logic__1569
-logic__6967: logic__6967
-logic__6850: logic__6850
-muxpart__108: muxpart__108
-reg__972: reg__972
-logic__2122: logic__2122
-reg__383: reg__383
-logic__8230: logic__8230
-logic__654: logic__654
-logic__137: logic__137
-reg__132: reg__132
-case__1481: case__1481
-datapath__507: datapath__507
-logic__8018: logic__8018
-logic__9301: logic__498
-logic__225: logic__225
-reg__1035: reg__1035
-logic__7564: logic__7564
-logic__3450: logic__3450
-datapath__519: datapath__519
-logic__103: logic__103
-logic__1148: logic__1148
-logic__872: logic__872
-IntSyncSyncCrossingSink_n1x2: IntSyncSyncCrossingSink_n1x2
-logic__7042: logic__7042
-logic__6578: logic__6578
-logic__3028: logic__3028
-reg__1015: reg__1015
-case__460: case__460
-case__922: case__922
-logic__8977: logic__2987
-logic__1096: logic__1096
-logic__106: logic__106
-reg__336: reg__336
-logic__2909: logic__2909
-logic__3732: logic__3732
-logic__200: logic__200
-logic__3847: logic__3847
-datapath__196: datapath__196
-logic__7422: logic__7422
-datapath__669: datapath__669
-logic__711: logic__711
-logic__5430: logic__5430
-logic__2487: logic__2487
-case__882: case__882
-datapath__191: datapath__191
-datapath__379: datapath__379
-logic__6740: logic__6740
-logic__677: logic__677
-logic__239: logic__239
-datapath__530: datapath__530
-TLAtomicAutomata_cbus: TLAtomicAutomata_cbus
-case__1564: case__315
-case__472: case__472
-case__781: case__781
-reg__554: reg__554
-case__82: case__82
-logic__9256: logic__8236
-TLBuffer_a32d64s2k1z4u: TLBuffer_a32d64s2k1z4u
-logic__2656: logic__2656
-logic__6023: logic__6023
-logic__1449: logic__1449
-case__1353: case__1353
-logic__866: logic__866
-reg__1312: reg__1312
-reg__362: reg__362
-logic__504: logic__504
-reg__1135: reg__1135
-case__655: case__655
-logic__7700: logic__7700
-logic__7183: logic__7183
-reg__203: reg__203
-logic__1996: logic__1996
-reg__1052: reg__1052
-datapath__704: datapath__247
-case__445: case__445
-logic__8503: logic__8503
-logic__9161: logic__1640
-counter__2: counter__2
-case__1302: case__1302
-logic__7285: logic__7285
-case__249: case__249
-datapath__635: datapath__635
-logic__9269: logic__7549
-reg__107: reg__107
-logic__7013: logic__7013
-logic__3004: logic__3004
-datapath__403: datapath__403
-datapath__324: datapath__324
-logic__2854: logic__2854
-logic__753: logic__753
-logic__2389: logic__2389
-muxpart__17: muxpart__17
-case__31: case__31
-dsp48e1__26: dsp48e1__26
-reg__1483: reg__833
-logic__8915: logic__8915
-logic__3136: logic__3136
-reg__183: reg__183
-TLDebugModuleOuter: TLDebugModuleOuter
-logic__1050: logic__1050
-case__449: case__449
-case__1590: case__1403
-logic__8728: logic__8728
-logic__972: logic__972
-case__706: case__706
-reg__1464: reg__834
-logic__6326: logic__6326
-case__807: case__807
-case__1394: case__1394
-reg__673: reg__673
-logic__8940: logic__8940
-case__427: case__427
-IntSyncCrossingSource_n1x1_Registered: IntSyncCrossingSource_n1x1_Registered
-datapath__670: datapath__670
-logic__8512: logic__8512
-case__11: case__11
-reg__910: reg__910
-case__834: case__834
-logic__4769: logic__4769
-case__752: case__752
-logic__2819: logic__2819
-logic__302: logic__302
-logic__2905: logic__2905
-logic__1312: logic__1312
-logic__9185: logic__1584
-reg__495: reg__495
-case__357: case__357
-logic__1412: logic__1412
-logic__241: logic__241
-logic__5323: logic__5323
-logic__4241: logic__4241
-reg__1419: reg__834
-logic__7593: logic__7593
-case__713: case__713
-logic__2307: logic__2307
-reg__345: reg__345
-logic__8511: logic__8511
-logic__3515: logic__3515
-datapath__249: datapath__249
-datapath__314: datapath__314
-Rocket: Rocket
-datapath__166: datapath__166
-logic__8951: logic__8951
-case__440: case__440
-TLWidthWidget8: TLWidthWidget8
-logic__9286: logic__6120
-reg__448: reg__448
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__18: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-DivSqrtRecFNToRaw_small: DivSqrtRecFNToRaw_small
-case__462: case__462
-logic__8456: logic__8456
-logic__4792: logic__4792
-logic__4257: logic__4257
-logic__4200: logic__4200
-AsyncValidSync__17: AsyncValidSync
-logic__6280: logic__6280
-case__1403: case__1403
-case__1509: case__1509
-reg__354: reg__354
-logic__3918: logic__3918
-logic__7400: logic__7400
-reg__167: reg__167
-case__1433: case__1433
-logic__4728: logic__4728
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__19: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-ClockGroup__2: ClockGroup
-case__709: case__709
-case__954: case__954
-logic__4914: logic__4914
-datapath__528: datapath__528
-case__99: case__99
-ICache: ICache
-logic__9327: logic__253
-reg__24: reg__24
-logic__8985: logic__2970
-logic__4705: logic__4705
-logic__1759: logic__1759
-reg__551: reg__551
-case__1193: case__1193
-logic__4709: logic__4709
-case__854: case__854
-logic__2861: logic__2861
-datapath__40: datapath__40
-logic__9320: logic__268
-logic__7589: logic__7589
-logic__6634: logic__6634
-datapath__588: datapath__588
-logic__3529: logic__3529
-datapath__382: datapath__382
-datapath__627: datapath__627
-datapath__613: datapath__613
-logic__4431: logic__4431
-reg__1125: reg__1125
-datapath__618: datapath__618
-reg__1533: reg__28
-logic__6928: logic__6928
-logic__3731: logic__3731
-datapath__2: datapath__2
-datapath__241: datapath__241
-case__454: case__454
-case__768: case__768
-logic__8328: logic__8328
-logic__6301: logic__6301
-Queue2_TLBundleA_a32d64s1k1z4u: Queue2_TLBundleA_a32d64s1k1z4u
-reg__326: reg__326
-logic__9255: logic__8237
-reg__1374: reg__1141
-logic__3433: logic__3433
-logic__4175: logic__4175
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__5183: logic__5183
-keep__5: keep__5
-TLDebugModuleInner: TLDebugModuleInner
-reg__204: reg__204
-case__259: case__259
-logic__3223: logic__3223
-TLWidthWidget1: TLWidthWidget1
-logic__9010: logic__3928
-keep__10: keep__10
-logic__598: logic__598
-logic__3741: logic__3741
-case__246: case__246
-logic__1856: logic__1856
-reg__1120: reg__1120
-reg__307: reg__307
-logic__7139: logic__7139
-logic__2406: logic__2406
-case__880: case__880
-reg__1198: reg__1198
-reg__437: reg__437
-datapath__199: datapath__199
-logic__7953: logic__7953
-logic__741: logic__741
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__20: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__2980: logic__2980
-reg__792: reg__792
-case__96: case__96
-reg__1369: reg__1247
-logic__3601: logic__3601
-logic__429: logic__429
-logic__2828: logic__2828
-logic__436: logic__436
-datapath__254: datapath__254
-datapath__211: datapath__211
-logic__8222: logic__8222
-datapath__707: datapath__244
-case__729: case__729
-muxpart__111: muxpart__111
-logic__9274: logic__6120
-reg__233: reg__233
-datapath__181: datapath__181
-logic__2071: logic__2071
-logic__3256: logic__3256
-case__1463: case__1463
-logic__6457: logic__6457
-logic__5962: logic__5962
-logic__5036: logic__5036
-logic__64: logic__64
-case__122: case__122
-logic__9034: logic__3863
-logic__1495: logic__1495
-logic__1722: logic__1722
-reg__578: reg__578
-reg__552: reg__552
-reg__18: reg__18
-case__893: case__893
-reg__197: reg__197
-datapath__222: datapath__222
-logic__1016: logic__1016
-case__646: case__646
-reg__1482: reg__834
-reg__1441: reg__833
-logic__5370: logic__5370
-case__1348: case__1348
-logic__6034: logic__6034
-FPU__GB0: FPU__GB0
-rom: rom
-logic__7138: logic__7138
-reg__129: reg__129
-logic__6102: logic__6102
-reg__956: reg__956
-reg__198: reg__198
-logic__5869: logic__5869
-logic__2105: logic__2105
-logic__7868: logic__7868
-logic__78: logic__78
-datapath__541: datapath__541
-logic__8627: logic__8627
-logic__5512: logic__5512
-logic__7543: logic__7543
-LevelGateway: LevelGateway
-logic__6070: logic__6070
-extram__8: extram__8
-logic__4556: logic__4556
-logic__736: logic__736
-case__430: case__430
-muxpart__35: muxpart__35
-logic__4669: logic__4669
-logic__2539: logic__2539
-logic__5431: logic__5431
-logic__2344: logic__2344
-logic__8655: logic__8655
-datapath__38: datapath__38
-SystemBus: SystemBus
-logic__9153: logic__1662
-logic__1298: logic__1298
-case__435: case__435
-logic__3780: logic__3780
-logic__4306: logic__4306
-reg__195: reg__195
-logic__6847: logic__6847
-logic__635: logic__635
-logic__9053: logic__1844
-logic__3331: logic__3331
-case__550: case__550
-reg__738: reg__738
-reg__364: reg__364
-logic__3651: logic__3651
-reg__1487: reg__835
-TLWidthWidget8_2: TLWidthWidget8_2
-datapath__99: datapath__99
-logic__4969: logic__4969
-muxpart__4: muxpart__4
-logic__6456: logic__6456
-logic__1786: logic__1786
-reg__91: reg__91
-reg__1341: reg__1341
-logic__7720: logic__7720
-datapath__62: datapath__62
-Arbiter4_DCacheDataReq: Arbiter4_DCacheDataReq
-logic__2972: logic__2972
-case__1393: case__1393
-reg__1449: reg__834
-logic__9049: logic__1856
-case__1268: case__1268
-datapath__440: datapath__440
-logic__9125: logic__1754
-logic__5970: logic__5970
-reg__773: reg__773
-logic__8363: logic__8363
-logic__3240: logic__3240
-logic__9290: logic__951
-reg__566: reg__566
-logic__312: logic__312
-reg__513: reg__513
-logic__3950: logic__3950
-reg__1460: reg__835
-logic__941: logic__941
-logic__7678: logic__7678
-logic__22: logic__22
-logic__986: logic__986
-case__742: case__742
-logic__9113: logic__1795
-logic__2695: logic__2695
-case__681: case__681
-logic__3468: logic__3468
-logic__1966: logic__1966
-logic__6375: logic__6375
-logic__670: logic__670
-logic__6899: logic__6899
-logic__7533: logic__7533
-case__946: case__946
-logic__851: logic__851
-datapath__3: datapath__3
-logic__6097: logic__6097
-logic__656: logic__656
-logic__233: logic__233
-reg__876: reg__876
-logic__7267: logic__7267
-datapath__93: datapath__93
-case__743: case__743
-muxpart__107: muxpart__107
-logic__1766: logic__1766
-case__931: case__931
-case__1192: case__1192
-logic__382: logic__382
-datapath__489: datapath__489
-reg__311: reg__311
-case__466: case__466
-logic__5228: logic__5228
-logic__6478: logic__6478
-keep__37: keep__6
-reg__1307: reg__1307
-logic__5394: logic__5394
-reg__619: reg__619
-logic__3904: logic__3904
-case__1079: case__1079
-logic__691: logic__691
-muxpart__207: muxpart__207
-ram__11: ram__2
-case__927: case__927
-datapath__161: datapath__161
-case__1283: case__1283
-logic__3398: logic__3398
-logic__5961: logic__5961
-logic__4307: logic__4307
-logic__2871: logic__2871
-case__847: case__847
-datapath__58: datapath__58
-reg__1074: reg__1074
-logic__9095: logic__1841
-case__352: case__352
-logic__8751: logic__8751
-reg__739: reg__739
-case__312: case__312
-reg__403: reg__403
-case__387: case__387
-case__1360: case__1360
-logic__8559: logic__8559
-logic__9039: logic__1874
-reg__565: reg__565
-reg__27: reg__27
-logic__7955: logic__7955
-case__1124: case__1124
-datapath__373: datapath__373
-reg__774: reg__774
-logic__6484: logic__6484
-reg__775: reg__775
-case__735: case__735
-logic__3399: logic__3399
-case__1085: case__1085
-datapath__288: datapath__288
-reg__921: reg__921
-reg__1514: reg__151
-reg__1409: reg__835
-datapath__102: datapath__102
-reg__63: reg__63
-reg__572: reg__572
-logic__1754: logic__1754
-datapath__399: datapath__399
-logic__1222: logic__1222
-logic__6563: logic__6563
-case__557: case__557
-reg__473: reg__473
-reg__271: reg__271
-case__332: case__332
-logic__597: logic__597
-reg__145: reg__145
-logic__7057: logic__7057
-acq_peak_srch: acq_peak_srch
-reg__1362: reg__1254
-logic__2388: logic__2388
-case__723: case__723
-reg__1329: reg__1329
-logic__7537: logic__7537
-logic__6667: logic__6667
-case__302: case__302
-logic__7444: logic__7444
-dsp48e1__24: dsp48e1__24
-reg__895: reg__895
-case__479: case__479
-muxpart__106: muxpart__106
-logic__6582: logic__6582
-logic__9297: logic__504
-logic__3874: logic__3874
-case__924: case__924
-dsp48e1__41: dsp48e1__41
-case__181: case__181
-logic__9312: logic__473
-logic__7524: logic__7524
-logic__7165: logic__7165
-datapath__597: datapath__597
-reg__1443: reg__834
-reg__1082: reg__1082
-logic__9293: logic__945
-logic__2177: logic__2177
-logic__1256: logic__1256
-case__416: case__416
-reg__1401: reg__998
-muxpart__233: muxpart__233
-logic__1508: logic__1508
-logic__4013: logic__4013
-logic__9001: logic__3950
-reg__1033: reg__1033
-sync__4: sync
-AsyncValidSync__1: AsyncValidSync
-logic__7286: logic__7286
-mult_53_53_106: mult_53_53_106
-reg__510: reg__510
-reg__822: reg__822
-keep__1: keep__1
-case__1466: case__1466
-logic__6529: logic__6529
-tracking_wrapper: tracking_wrapper
-reg__1512: reg__783
-logic__6769: logic__6769
-logic__6114: logic__6114
-reg__1225: reg__1225
-logic__4848: logic__4848
-case__995: case__995
-datapath__287: datapath__287
-datapath__503: datapath__503
-logic__2823: logic__2823
-reg__808: reg__808
-logic__2222: logic__2222
-rom__1: rom__1
-reg__557: reg__557
-case__811: case__811
-reg__353: reg__353
-datapath__715: datapath__18
-logic__1765: logic__1765
-case__517: case__517
-logic__6453: logic__6453
-logic__6000: logic__6000
-logic__3777: logic__3777
-reg__178: reg__178
-logic__316: logic__316
-logic__4354: logic__4354
-logic__881: logic__881
-logic__4793: logic__4793
-datapath__738: datapath__136
-reg__1388: reg__996
-case__443: case__443
-logic__5432: logic__5432
-logic__3906: logic__3906
-keep__36: keep__7
-datapath__642: datapath__642
-reg__879: reg__879
-logic__8742: logic__8742
-logic__6372: logic__6372
-muxpart__112: muxpart__112
-logic__477: logic__477
-logic__2230: logic__2230
-logic__690: logic__690
-reg__652: reg__652
-logic__1630: logic__1630
-logic__7423: logic__7423
-datapath__696: datapath__297
-logic__7153: logic__7153
-case__855: case__855
-reg__258: reg__258
-logic__3300: logic__3300
-logic__1674: logic__1674
-logic__957: logic__957
-logic__2263: logic__2263
-logic__877: logic__877
-reg__112: reg__112
-case__751: case__751
-muxpart__99: muxpart__99
-case__695: case__695
-case__58: case__58
-reg__1020: reg__1020
-datapath__686: datapath__686
-reg__332: reg__332
-keep__38: keep__1
-case__7: case__7
-logic__2517: logic__2517
-logic__6571: logic__6571
-logic__5306: logic__5306
-reg__967: reg__967
-case__1381: case__1381
-case__488: case__488
-reg__901: reg__901
-logic__6356: logic__6356
-reg__1458: reg__834
-case__408: case__408
-logic__136: logic__136
-reg__1107: reg__1107
-Queue2_TLBundleD_a29d64s2k1z3u__2: Queue2_TLBundleD_a29d64s2k1z3u
-logic__9234: logic__650
-logic__6485: logic__6485
-logic__4343: logic__4343
-datapath__322: datapath__322
-case__138: case__138
-datapath__706: datapath__245
-reg__1379: reg__1141
-muxpart__46: muxpart__46
-logic__4203: logic__4203
-logic__6788: logic__6788
-case__989: case__989
-logic__9158: logic__1645
-logic__3726: logic__3726
-case__1058: case__1058
-case__1003: case__1003
-logic__4872: logic__4872
-logic__5149: logic__5149
-reg__982: reg__982
-reg__384: reg__384
-case__1191: case__1191
-AsyncValidSync__2: AsyncValidSync
-TLInterconnectCoupler_cbus_to_bus_named_pbus: TLInterconnectCoupler_cbus_to_bus_named_pbus
-case__825: case__825
-datapath__257: datapath__257
-datapath__428: datapath__428
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__18: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__7190: logic__7190
-logic__9019: logic__3910
-reg__765: reg__765
-case__570: case__570
-datapath__721: datapath__112
-reg__753: reg__753
-logic__1374: logic__1374
-reg__60: reg__60
-logic__6974: logic__6974
-case__279: case__279
-logic__3103: logic__3103
-logic__6332: logic__6332
-case__303: case__303
-case__806: case__806
-logic__4034: logic__4034
-case__100: case__100
-case__1535: case__1535
-datapath__717: datapath__116
-datapath__684: datapath__684
-double_ff_syn__2: double_ff_syn
-dsp48e1__45: dsp48e1__45
-logic__3670: logic__3670
-logic__5951: logic__5951
-logic__4956: logic__4956
-logic__960: logic__960
-reg__493: reg__493
-reg__1058: reg__1058
-reg__516: reg__516
-case__1050: case__1050
-case__450: case__450
-logic__2381: logic__2381
-case__1174: case__1174
-case__875: case__875
-logic__560: logic__560
-logic__4239: logic__4239
-reg__245: reg__245
-case__938: case__938
-case__1594: case__105
-datapath__295: datapath__295
-logic__1605: logic__1605
-logic__7577: logic__7577
-logic__9156: logic__1647
-logic__3392: logic__3392
-logic__1397: logic__1397
-logic__1844: logic__1844
-case__1009: case__1009
-logic__3086: logic__3086
-reg__1364: reg__1252
-reg__1395: reg__835
-reg__1038: reg__1038
-CSRFile: CSRFile
-logic__8697: logic__8697
-logic__6525: logic__6525
-reg__843: reg__843
-reg__1089: reg__1089
-reg__795: reg__795
-logic__2172: logic__2172
-datapath__568: datapath__568
-datapath__650: datapath__650
-reg__902: reg__902
-logic__3841: logic__3841
-case__26: case__26
-logic__4838: logic__4838
-datapath__250: datapath__250
-case__1419: case__1419
-logic__689: logic__689
-counter__3: counter__3
-reg__472: reg__472
-case__378: case__378
-logic__2024: logic__2024
-case__951: case__951
-logic__7676: logic__7676
-case__598: case__598
-logic__4929: logic__4929
-logic__6117: logic__6117
-logic__924: logic__924
-datapath__78: datapath__78
-reg__1123: reg__1123
-case__1183: case__1183
-logic__3682: logic__3682
-logic__8671: logic__8671
-logic__3727: logic__3727
-reg__616: reg__616
-logic__879: logic__879
-logic__4800: logic__4800
-datapath__178: datapath__178
-logic__6024: logic__6024
-logic__735: logic__735
-logic__6103: logic__6103
-datapath__275: datapath__275
-datapath__673: datapath__673
-logic__6002: logic__6002
-reg__981: reg__981
-logic__2936: logic__2936
-logic__8860: logic__8860
-case__1435: case__1435
-case__722: case__722
-reg__1187: reg__1187
-reg__310: reg__310
-logic__8815: logic__8815
-logic__5522: logic__5522
-datapath__675: datapath__675
-case__1517: case__1517
-reg__1330: reg__1330
-case__975: case__975
-cordic_angle_lut__parameterized0: cordic_angle_lut__parameterized0
-logic__6080: logic__6080
-logic__1303: logic__1303
-logic__9178: logic__1597
-case__630: case__630
-logic__7682: logic__7682
-case__219: case__219
-datapath__60: datapath__60
-logic__2691: logic__2691
-logic__2380: logic__2380
-logic__733: logic__733
-logic__9303: logic__494
-case__1118: case__1118
-case__511: case__511
-datapath__49: datapath__49
-reg__1108: reg__1108
-datapath__577: datapath__577
-logic__2259: logic__2259
-reg__230: reg__230
-logic__1340: logic__1340
-Repeater_TLBundleA_a29d64s2k1z3u__1: Repeater_TLBundleA_a29d64s2k1z3u
-case__1275: case__1275
-case__1159: case__1159
-cordic_atan_basic__parameterized0__1: cordic_atan_basic__parameterized0
-logic__2976: logic__2976
-reg__49: reg__49
-logic__9230: logic__262
-reg__108: reg__108
-datapath__13: datapath__13
-case__1227: case__1227
-dsp48e1__7: dsp48e1__7
-logic__2927: logic__2927
-reg__636: reg__636
-reg__1244: reg__1244
-logic__7279: logic__7279
-reg__1130: reg__1130
-reg__131: reg__131
-logic__3609: logic__3609
-logic__8970: logic__3004
-AsyncResetRegVec_w1_i0__2: AsyncResetRegVec_w1_i0
-case__283: case__283
-datapath__193: datapath__193
-logic__6216: logic__6216
-logic__1302: logic__1302
-logic__1141: logic__1141
-reg__377: reg__377
-logic__7252: logic__7252
-case__925: case__925
-datapath__600: datapath__600
-logic__3259: logic__3259
-logic__6743: logic__6743
-logic__6004: logic__6004
-logic__6293: logic__6293
-logic__6116: logic__6116
-logic__4251: logic__4251
-logic__4220: logic__4220
-reg__1206: reg__1206
-logic__3447: logic__3447
-datapath__12: datapath__12
-reg__1103: reg__1103
-reg__1358: reg__114
-logic__2083: logic__2083
-reg__828: reg__828
-logic__8930: logic__8930
-case__1160: case__1160
-logic__1905: logic__1905
-datapath__110: datapath__110
-logic__1594: logic__1594
-logic__9054: logic__1841
-case__982: case__982
-logic__1168: logic__1168
-logic__6749: logic__6749
-datapath__463: datapath__463
-logic__2870: logic__2870
-reg__33: reg__33
-case__306: case__306
-reg__319: reg__319
-TLXbar_sbus_i2_o1_a32d64s2k1z4u: TLXbar_sbus_i2_o1_a32d64s2k1z4u
-logic__7976: logic__7976
-logic__3773: logic__3773
-logic__4474: logic__4474
-reg__515: reg__515
-datapath__501: datapath__501
-logic__5528: logic__5528
-reg__314: reg__314
-logic__2185: logic__2185
-datapath__42: datapath__42
-datapath__434: datapath__434
-case__800: case__800
-logic__9209: logic__1530
-logic__2965: logic__2965
-logic__6086: logic__6086
-reg__381: reg__381
-logic__4779: logic__4779
-logic__1344: logic__1344
-logic__734: logic__734
-logic__3787: logic__3787
-reg__483: reg__483
-datapath__308: datapath__308
-reg__1412: reg__835
-logic__1176: logic__1176
-datapath__567: datapath__567
-reg__1308: reg__1308
-case__317: case__317
-logic__2169: logic__2169
-logic__4648: logic__4648
-PlusArgTimeout: PlusArgTimeout
-case__1027: case__1027
-logic__387: logic__387
-logic__3446: logic__3446
-case__37: case__37
-case__182: case__182
-datapath__44: datapath__44
-logic__8386: logic__8386
-datapath__202: datapath__202
-logic__6623: logic__6623
-logic__2129: logic__2129
-datapath__426: datapath__426
-logic__6392: logic__6392
-logic__82: logic__82
-logic__6157: logic__6157
-reg__575: reg__575
-reg__238: reg__238
-reg__1386: reg__998
-logic__2384: logic__2384
-datapath__79: datapath__79
-logic__3671: logic__3671
-reg__1360: reg__112
-logic__9163: logic__1632
-case__1039: case__1039
-muxpart__229: muxpart__229
-TLDebugModuleOuterAsync: TLDebugModuleOuterAsync
-logic__9243: logic__8442
-logic__6419: logic__6419
-datapath__146: datapath__146
-reg__1499: reg__835
-reg__818: reg__818
-logic__6085: logic__6085
-reg__1345: reg__1345
-datapath__177: datapath__177
-logic__4284: logic__4284
-logic__7464: logic__7464
-logic__2386: logic__2386
-logic__2883: logic__2883
-logic__2221: logic__2221
-logic__7342: logic__7342
-case__863: case__863
-logic__502: logic__502
-reg__1250: reg__1250
-reg__951: reg__951
-logic__3481: logic__3481
-logic__5375: logic__5375
-case__3: case__3
-logic__7144: logic__7144
-datapath__502: datapath__502
-logic__415: logic__415
-logic__9073: logic__1900
-AsyncValidSync: AsyncValidSync
-case__461: case__461
-logic__4269: logic__4269
-datapath__443: datapath__443
-logic__7373: logic__7373
-logic__3775: logic__3775
-datapath__297: datapath__297
-logic__6755: logic__6755
-logic__9237: logic__645
-reg__754: reg__754
-logic__6156: logic__6156
-logic__1745: logic__1745
-case__1230: case__1230
-logic__9091: logic__1853
-logic__1588: logic__1588
-logic__5267: logic__5267
-reg__124: reg__124
-logic__6798: logic__6798
-logic__2256: logic__2256
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__36: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__294: datapath__294
-case__290: case__290
-logic__6714: logic__6714
-reg__820: reg__820
-logic__104: logic__104
-logic__6255: logic__6255
-ram_2x77__2: ram_2x77
-case__507: case__507
-reg__587: reg__587
-reg__57: reg__57
-datapath__59: datapath__59
-reg__293: reg__293
-logic__4902: logic__4902
-logic__2396: logic__2396
-LF_carr: LF_carr
-case__35: case__35
-logic__3615: logic__3615
-case__40: case__40
-datapath__7: datapath__7
-case__1456: case__1456
-logic__4598: logic__4598
-logic__806: logic__806
-logic__6365: logic__6365
-logic__5985: logic__5985
-logic__4375: logic__4375
-reg__1124: reg__1124
-reg__917: reg__917
-logic__2858: logic__2858
-logic__4777: logic__4777
-datapath__442: datapath__442
-logic__3884: logic__3884
-datapath__705: datapath__246
-case__299: case__299
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__9: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__1339: logic__1339
-logic__4760: logic__4760
-reg__459: reg__459
-logic__5663: logic__5663
-logic__190: logic__190
-Repeater_TLBundleA_a29d64s2k1z3u: Repeater_TLBundleA_a29d64s2k1z3u
-logic__9309: logic__478
-logic__5382: logic__5382
-logic__5860: logic__5860
-reg__410: reg__410
-MulAddRecFNToRaw_postMul_1: MulAddRecFNToRaw_postMul_1
-logic__1037: logic__1037
-logic__7541: logic__7541
-reg__825: reg__825
-reg__846: reg__846
-datapath__464: datapath__464
-reg__880: reg__880
-logic__6165: logic__6165
-reg__1227: reg__1227
-logic__6010: logic__6010
-logic__1169: logic__1169
-logic__588: logic__588
-logic__3284: logic__3284
-logic__4101: logic__4101
-logic__4247: logic__4247
-reg__1520: reg__65
-muxpart__28: muxpart__28
-case__394: case__394
-reg__779: reg__779
-case__585: case__585
-case__1398: case__1398
-logic__498: logic__498
-datapath__109: datapath__109
-datapath__420: datapath__420
-case__932: case__932
-datapath__321: datapath__321
-logic__3541: logic__3541
-logic__3755: logic__3755
-logic__6540: logic__6540
-case__782: case__782
-lock_detector: lock_detector
-case__577: case__577
-logic__2166: logic__2166
-muxpart__249: muxpart__11
-logic__3749: logic__3749
-case__353: case__353
-reg__252: reg__252
-logic__3070: logic__3070
-logic__4002: logic__4002
-case__178: case__178
-logic__3441: logic__3441
-case__1088: case__1088
-logic__1465: logic__1465
-logic__2093: logic__2093
-logic__6361: logic__6361
-case__890: case__890
-logic__6101: logic__6101
-logic__901: logic__901
-logic__4435: logic__4435
-logic__7204: logic__7204
-logic__6530: logic__6530
-dsp48e1__13: dsp48e1__13
-logic__7115: logic__7115
-reg__1532: reg__29
-case__535: case__535
-logic__890: logic__890
-logic__3850: logic__3850
-reg__329: reg__329
-logic__4219: logic__4219
-logic__9198: logic__1555
-logic__5145: logic__5145
-sample_counter: sample_counter
-reg__847: reg__847
-datapath__98: datapath__98
-OptimizationBarrier_TLBEntryData__2: OptimizationBarrier_TLBEntryData
-logic__3752: logic__3752
-reg__1027: reg__1027
-logic__4205: logic__4205
-logic__9325: logic__258
-reg__788: reg__788
-logic__1217: logic__1217
-case__95: case__95
-case__1235: case__1235
-logic__4631: logic__4631
-DivSqrtRawFN_small_1: DivSqrtRawFN_small_1
-case__1273: case__1273
-logic__7952: logic__7952
-reg__48: reg__48
-reg__539: reg__539
-case__493: case__493
-logic__6220: logic__6220
-logic__8885: logic__8885
-logic__2977: logic__2977
-reg__327: reg__327
-logic__902: logic__902
-logic__9094: logic__1844
-logic__6732: logic__6732
-logic__6174: logic__6174
-case__337: case__337
-case__434: case__434
-logic__1904: logic__1904
-reg__1511: reg__783
-datapath__173: datapath__173
-reg__665: reg__665
-logic__6718: logic__6718
-reg__1357: reg__115
-reg__623: reg__623
-case__300: case__300
-case__657: case__657
-logic__2243: logic__2243
-case__1382: case__1382
-logic__8158: logic__8158
-reg__769: reg__769
-case__1336: case__1336
-reg__333: reg__333
-reg__1521: reg__64
-reg__87: reg__87
-logic__6719: logic__6719
-logic__1908: logic__1908
-logic__8992: logic__2963
-logic__1080: logic__1080
-logic__2840: logic__2840
-logic__3872: logic__3872
-case__330: case__330
-logic__3763: logic__3763
-case__796: case__796
-case__1412: case__1412
-logic__4963: logic__4963
-logic__6660: logic__6660
-RoundAnyRawFNToRecFN__1: RoundAnyRawFNToRecFN
-reg__1465: reg__833
-logic__463: logic__463
-case__1528: case__1528
-reg__1032: reg__1032
-logic__2125: logic__2125
-logic__7427: logic__7427
-logic__5486: logic__5486
-reg__1397: reg__833
-reg__482: reg__482
-Queue2_TLBundleA_a32d64s2k1z3u: Queue2_TLBundleA_a32d64s2k1z3u
-reg__1128: reg__1128
-reg__1188: reg__1188
-logic__6508: logic__6508
-logic__680: logic__680
-datapath__36: datapath__36
-cordic_angle_lut: cordic_angle_lut
-logic__2357: logic__2357
-logic__8411: logic__8411
-logic__9328: logic__252
-logic__1092: logic__1092
-reg__891: reg__891
-logic__7531: logic__7531
-CLINT: CLINT
-case__1084: case__1084
-case__1130: case__1130
-reg__817: reg__817
-datapath__614: datapath__614
-TLInterconnectCoupler_sbus_to_bus_named_cbus: TLInterconnectCoupler_sbus_to_bus_named_cbus
-FixedClockBroadcast_3: FixedClockBroadcast_3
-reg__1414: reg__833
-logic__819: logic__819
-logic__4333: logic__4333
-logic__946: logic__946
-reg__140: reg__140
-reg__1098: reg__1098
-case__1582: case__1411
-logic__8729: logic__8729
-logic__2888: logic__2888
-logic__6470: logic__6470
-logic__3621: logic__3621
-logic__1034: logic__1034
-logic__904: logic__904
-case__529: case__529
-logic__3905: logic__3905
-case__4: case__4
-logic__7081: logic__7081
-case__1083: case__1083
-FPU__GB2: FPU__GB2
-logic__3263: logic__3263
-datapath__714: datapath__19
-logic__6765: logic__6765
-reg__256: reg__256
-datapath__323: datapath__323
-muxpart__93: muxpart__93
-logic__1369: logic__1369
-reg__1474: reg__833
-logic__6104: logic__6104
-reg__597: reg__597
-Queue2_TLBundleA_a32d64s2k1z4u: Queue2_TLBundleA_a32d64s2k1z4u
-logic__8226: logic__8226
-reg__761: reg__761
-logic__8303: logic__8303
-logic__829: logic__829
-reg__456: reg__456
-logic__4546: logic__4546
-logic__1172: logic__1172
-datapath__716: datapath__17
-reg__1069: reg__1069
-logic__9174: logic__1609
-reg__943: reg__943
-logic__3816: logic__3816
-logic__7324: logic__7324
-logic__373: logic__373
-reg__1136: reg__1136
-reg__676: reg__676
-case__987: case__987
-logic__206: logic__206
-ClockCrossingReg_w43: ClockCrossingReg_w43
-reg__1480: reg__833
-case__335: case__335
-reg__1476: reg__834
-case__1141: case__1141
-logic__7640: logic__7640
-logic__4300: logic__4300
-logic__757: logic__757
-muxpart__36: muxpart__36
-logic__9132: logic__1727
-logic__1810: logic__1810
-logic__7318: logic__7318
-reg__1361: reg__111
-reg__1477: reg__833
-logic__1084: logic__1084
-datapath__221: datapath__221
-logic__2282: logic__2282
-logic__2693: logic__2693
-reg__1167: reg__1167
-muxpart__86: muxpart__86
-case__90: case__90
-case__809: case__809
-logic__9092: logic__1850
-reg__442: reg__442
-reg__89: reg__89
-logic__6741: logic__6741
-dsp48e1__18: dsp48e1__18
-logic__6003: logic__6003
-reg__874: reg__874
-logic__127: logic__127
-reg__1382: reg__996
-logic__4990: logic__4990
-logic__6775: logic__6775
-datapath__349: datapath__349
-logic__4458: logic__4458
-case__850: case__850
-datapath__302: datapath__302
-logic__178: logic__178
-reg__322: reg__322
-reg__596: reg__596
-logic__5393: logic__5393
-logic__286: logic__286
-ClockGroupAggregator_pbus: ClockGroupAggregator_pbus
-case__1437: case__1437
-reg__1438: reg__833
-logic__9029: logic__3875
-reg__1200: reg__1200
-datapath__355: datapath__355
-logic__6725: logic__6725
-datapath__589: datapath__589
-logic__3779: logic__3779
-logic__3488: logic__3488
-reg__1356: reg__116
-datapath__90: datapath__90
-case__212: case__212
-logic__1136: logic__1136
-logic__5852: logic__5852
-logic__2797: logic__2797
-case__1587: case__1406
-binary_to_gray__1: binary_to_gray
-logic__1505: logic__1505
-reg__1306: reg__1306
-reg__1049: reg__1049
-logic__794: logic__794
-logic__2109: logic__2109
-logic__8144: logic__8144
-logic__1263: logic__1263
-logic__416: logic__416
-logic__3641: logic__3641
-case__1081: case__1081
-logic__3533: logic__3533
-datapath__75: datapath__75
-case__1567: case__312
-case__724: case__724
-case__88: case__88
-case__45: case__45
-logic__2589: logic__2589
-case__432: case__432
-reg__606: reg__606
-case__114: case__114
-reg__408: reg__408
-logic__798: logic__798
-logic__6722: logic__6722
-datapath__471: datapath__471
-logic__6217: logic__6217
-case__197: case__197
-AsyncValidSync__11: AsyncValidSync
-logic__5928: logic__5928
-logic__7390: logic__7390
-logic__172: logic__172
-reg__1028: reg__1028
-logic__1093: logic__1093
-logic__782: logic__782
-ClockGroup__3: ClockGroup
-butterfly__parameterized1: butterfly__parameterized1
-reg__224: reg__224
-logic__9144: logic__1687
-logic__3860: logic__3860
-logic__4855: logic__4855
-logic__7410: logic__7410
-logic__3814: logic__3814
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__11: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__134: logic__134
-case__1188: case__1188
-twiddle_ram__2: twiddle_ram
-datapath__198: datapath__198
-logic__1685: logic__1685
-reg__1489: reg__833
-reg__845: reg__845
-case__956: case__956
-logic__683: logic__683
-logic__625: logic__625
-datapath__612: datapath__612
-logic__6727: logic__6727
-logic__6005: logic__6005
-logic__1174: logic__1174
-logic__6766: logic__6766
-logic__518: logic__518
-reg__19: reg__19
-logic__8923: logic__8923
-logic__4636: logic__4636
-reg__156: reg__156
-reg__736: reg__736
-case__680: case__680
-sync__3: sync
-logic__7627: logic__7627
-logic__7526: logic__7526
-case__772: case__772
-case__1357: case__1357
-case__592: case__592
-datapath__197: datapath__197
-RoundAnyRawFNToRecFN_2: RoundAnyRawFNToRecFN_2
-logic__6506: logic__6506
-case__1532: case__1532
-logic__1825: logic__1825
-case__1383: case__1383
-case__513: case__513
-reg__300: reg__300
-muxpart__87: muxpart__87
-datapath__208: datapath__208
-logic__9236: logic__646
-logic__95: logic__95
-datapath__680: datapath__680
-logic__4126: logic__4126
-case__417: case__417
-case__136: case__136
-logic__4417: logic__4417
-logic__8385: logic__8385
-case__1212: case__1212
-case__728: case__728
-logic__4261: logic__4261
-logic__6173: logic__6173
-logic__4905: logic__4905
-case__798: case__798
-logic__4495: logic__4495
-reg__397: reg__397
-case__515: case__515
-AsyncQueueSink_DebugInternalBundle: AsyncQueueSink_DebugInternalBundle
-logic__7454: logic__7454
-logic__7532: logic__7532
-reg__1472: reg__835
-logic__1767: logic__1767
-case__243: case__243
-case__1522: case__1522
-PMAChecker__1: PMAChecker
-datapath__350: datapath__350
-reg__12: reg__12
-reg__948: reg__948
-logic__6583: logic__6583
-logic__2712: logic__2712
-logic__1725: logic__1725
-logic__148: logic__148
-keep__34: keep__6
-case__119: case__119
-logic__7793: logic__7793
-logic__6619: logic__6619
-counter__6: counter__6
-reg__576: reg__576
-logic__9088: logic__1862
-logic__874: logic__874
-logic__7228: logic__7228
-logic__1382: logic__1382
-logic__9036: logic__1889
-datapath__452: datapath__452
-logic__2705: logic__2705
-logic__3774: logic__3774
-logic__5329: logic__5329
-reg__421: reg__421
-logic__9080: logic__1874
-logic__1368: logic__1368
-logic__3327: logic__3327
-logic__1682: logic__1682
-logic__4721: logic__4721
-logic__4179: logic__4179
-TLInterconnectCoupler_cbus_to_rockettile: TLInterconnectCoupler_cbus_to_rockettile
-FixedClockBroadcast_5: FixedClockBroadcast_5
-case__470: case__470
-datapath__630: datapath__630
-logic__4302: logic__4302
-reg__1492: reg__833
-logic__6013: logic__6013
-datapath__96: datapath__96
-datapath__693: datapath__300
-logic__303: logic__303
-logic__4117: logic__4117
-logic__6562: logic__6562
-keep__2: keep__2
-case__981: case__981
-logic__9315: logic__463
-fft_radix_2__parameterized0: fft_radix_2__parameterized0
-logic__7553: logic__7553
-logic__9115: logic__1786
-reg__807: reg__807
-reg__1444: reg__833
-reg__134: reg__134
-case__1093: case__1093
-logic__3052: logic__3052
-muxpart__12: muxpart__12
-case__377: case__377
-muxpart__110: muxpart__110
-reg__1406: reg__833
-datapath__561: datapath__561
-logic__6767: logic__6767
-logic__6565: logic__6565
-logic__252: logic__252
-reg__1084: reg__1084
-logic__7771: logic__7771
-logic__8415: logic__8415
-logic__9100: logic__1828
-logic__7336: logic__7336
-logic__7852: logic__7852
-reg__1201: reg__1201
-reg__1199: reg__1199
-logic__599: logic__599
-reg__356: reg__356
-reg__435: reg__435
-logic__1826: logic__1826
-muxpart__114: muxpart__114
-case__345: case__345
-reg__342: reg__342
-dsp48e1__10: dsp48e1__10
-logic__9044: logic__1869
-logic__7177: logic__7177
-logic__6704: logic__6704
-datapath__23: datapath__23
-datapath__246: datapath__246
-logic__7396: logic__7396
-reg__215: reg__215
-logic__2391: logic__2391
-logic__3061: logic__3061
-logic__6030: logic__6030
-logic__5193: logic__5193
-reg__959: reg__959
-reg__811: reg__811
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__9: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__7069: logic__7069
-reg__746: reg__746
-case__787: case__787
-logic__1999: logic__1999
-case__62: case__62
-logic__3909: logic__3909
-keep__43: keep
-case__612: case__612
-datapath__251: datapath__251
-acq_nco_carr: acq_nco_carr
-datapath__629: datapath__629
-reg__430: reg__430
-logic__1158: logic__1158
-logic__513: logic__513
-extram__5: extram__5
-logic__9062: logic__1825
-reg__549: reg__549
-logic__2463: logic__2463
-logic__8025: logic__8025
-logic__7899: logic__7899
-case__154: case__154
-logic__247: logic__247
-logic__9147: logic__1682
-case__629: case__629
-case__877: case__877
-muxpart__11: muxpart__11
-logic__1333: logic__1333
-logic__1899: logic__1899
-case__953: case__953
-LevelGateway__5: LevelGateway
-reg__142: reg__142
-logic__9038: logic__1882
-case__756: case__756
-logic__1982: logic__1982
-datapath__305: datapath__305
-case__411: case__411
-logic__1179: logic__1179
-logic__6505: logic__6505
-case__830: case__830
-logic__8913: logic__8913
-CLINTClockSinkDomain: CLINTClockSinkDomain
-case__79: case__79
-reg__268: reg__268
-Queue1_TLBundleA_a29d32s7k1z2u: Queue1_TLBundleA_a29d32s7k1z2u
-reg__642: reg__642
-case__851: case__851
-logic__5192: logic__5192
-case__705: case__705
-reg__1106: reg__1106
-reg__372: reg__372
-reg__583: reg__583
-logic__2576: logic__2576
-extrom__2: extrom__1
-logic__6662: logic__6662
-reg__604: reg__604
-logic__1490: logic__1490
-reg__1384: reg__997
-logic__9052: logic__1847
-datapath__252: datapath__252
-datapath__450: datapath__450
-logic__2711: logic__2711
-logic__369: logic__369
-datapath__574: datapath__574
-case__1553: case__524
-case__1375: case__1375
-logic__6674: logic__6674
-logic__5383: logic__5383
-logic__7403: logic__7403
-reg__977: reg__977
-logic__6251: logic__6251
-logic__5179: logic__5179
-logic__6385: logic__6385
-logic__3208: logic__3208
-logic__4214: logic__4214
-logic__6763: logic__6763
-datapath__720: datapath__113
-case__1523: case__1523
-logic__3536: logic__3536
-logic__9176: logic__1605
-logic__2246: logic__2246
-reg__1110: reg__1110
-logic__1659: logic__1659
-case__89: case__89
-dsp48e1__28: dsp48e1__28
-logic__1473: logic__1473
-logic__6410: logic__6410
-case__158: case__158
-case__1278: case__1278
-reg__461: reg__461
-reg__1285: reg__1285
-logic__9123: logic__1762
-datapath__277: datapath__277
-logic__6764: logic__6764
-logic__501: logic__501
-case__658: case__658
-logic__1247: logic__1247
-reg__684: reg__684
-logic__6894: logic__6894
-logic__6430: logic__6430
-case__1524: case__1524
-datapath__422: datapath__422
-logic__8993: logic__2962
-datapath__378: datapath__378
-logic__4730: logic__4730
-reg__1410: reg__834
-reg__1266: reg__1266
-case__323: case__323
-logic__6495: logic__6495
-reg__221: reg__221
-case__222: case__222
-case__865: case__865
-logic__2612: logic__2612
-datapath__681: datapath__681
-reg__947: reg__947
-case__97: case__97
-logic__3493: logic__3493
-logic__435: logic__435
-case__1571: case__308
-logic__3784: logic__3784
-logic__5282: logic__5282
-case__737: case__737
-logic__6793: logic__6793
-reg__697: reg__697
-case__401: case__401
-case__1402: case__1402
-case__1221: case__1221
-logic__8701: logic__8701
-logic__4726: logic__4726
-RecFNToRecFN: RecFNToRecFN
-logic__5998: logic__5998
-logic__7937: logic__7937
-case__333: case__333
-reg__1413: reg__834
-logic__6556: logic__6556
-datapath__647: datapath__647
-logic__4530: logic__4530
-logic__3778: logic__3778
-logic__1795: logic__1795
-case__1140: case__1140
-logic__3734: logic__3734
-logic__5648: logic__5648
-logic__5303: logic__5303
-logic__2387: logic__2387
-reg__1416: reg__834
-reg__66: reg__66
-case__32: case__32
-case__421: case__421
-logic__6053: logic__6053
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__15: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__9194: logic__1561
-datapath__156: datapath__156
-logic__5444: logic__5444
-datapath__709: datapath__242
-datapath__384: datapath__384
-datapath__247: datapath__247
-reg__46: reg__46
-logic__3299: logic__3299
-logic__1954: logic__1954
-reg__347: reg__347
-logic__9111: logic__1801
-case__650: case__650
-AsyncResetSynchronizerShiftReg_w1_d3_i0__8: AsyncResetSynchronizerShiftReg_w1_d3_i0
-reg__1518: reg__67
-datapath__466: datapath__466
-case__457: case__457
-datapath__262: datapath__262
-AsyncValidSync__13: AsyncValidSync
-logic__1241: logic__1241
-case__779: case__779
-datapath__724: datapath__109
-muxpart__167: muxpart__167
-case__328: case__328
-case__369: case__369
-logic__7211: logic__7211
-case__745: case__745
-logic__2621: logic__2621
-case__759: case__759
-logic__8366: logic__8366
-logic__9227: logic__268
-logic__8658: logic__8658
-keep__41: keep
-keep__31: keep__6
-logic__5401: logic__5401
-logic__815: logic__815
-logic__4143: logic__4143
-logic__5886: logic__5886
-reg__1484: reg__835
-logic__1873: logic__1873
-reg__885: reg__885
-logic__6968: logic__6968
-reg__854: reg__854
-datapath__103: datapath__103
-logic__2190: logic__2190
-logic__5001: logic__5001
-case__871: case__871
-datapath__607: datapath__607
-case__663: case__663
-datapath__662: datapath__662
-ScratchpadSlavePort: ScratchpadSlavePort
-logic__452: logic__452
-reg__491: reg__491
-logic__4323: logic__4323
-case__504: case__504
-reg__276: reg__276
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__2: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__6599: logic__6599
-case__305: case__305
-reg__1496: reg__835
-logic__1871: logic__1871
-datapath__473: datapath__473
-logic__8946: logic__8946
-reg__1240: reg__1240
-logic__3796: logic__3796
-case__1090: case__1090
-reg__537: reg__537
-logic__2908: logic__2908
-datapath__210: datapath__210
-case__19: case__19
-reg__1041: reg__1041
-logic__1503: logic__1503
-logic__3928: logic__3928
-logic__1388: logic__1388
-logic__3155: logic__3155
-reg__797: reg__797
-reg__1471: reg__833
-logic__5138: logic__5138
-reg__848: reg__848
-case__820: case__820
-logic__3236: logic__3236
-case__169: case__169
-reg__1350: reg__1350
-logic__5866: logic__5866
-case__376: case__376
-reg__264: reg__264
-logic__2950: logic__2950
-logic__8932: logic__8932
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__8: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6941: logic__6941
-Repeater_TLBundleA_a17d64s2k1z3u: Repeater_TLBundleA_a17d64s2k1z3u
-reg__1359: reg__113
-logic__7348: logic__7348
-datapath__311: datapath__311
-logic__5339: logic__5339
-case__604: case__604
-logic__1667: logic__1667
-case__967: case__967
-logic__929: logic__929
-logic__2152: logic__2152
-logic__6081: logic__6081
-logic__7552: logic__7552
-reg__137: reg__137
-case__1361: case__1361
-logic__2128: logic__2128
-datapath__122: datapath__122
-reg__316: reg__316
-bit_gen: bit_gen
-logic__1953: logic__1953
-reg__1160: reg__1160
-logic__3535: logic__3535
-logic__4604: logic__4604
-extladd__1: extladd__1
-datapath__1: datapath__1
-logic__9251: logic__8237
-case__944: case__944
-case__139: case__139
-case__600: case__600
-logic__2874: logic__2874
-logic__8367: logic__8367
-reg__1259: reg__1259
-logic__1447: logic__1447
-dsp48e1__6: dsp48e1__6
-logic__6711: logic__6711
-ram_2x77__1: ram_2x77
-logic__5810: logic__5810
-reg__648: reg__648
-logic__3131: logic__3131
-logic__7000: logic__7000
-logic__1384: logic__1384
-logic__2063: logic__2063
-logic__6728: logic__6728
-logic__3791: logic__3791
-logic__70: logic__70
-datapath__477: datapath__477
-logic__2911: logic__2911
-logic__8976: logic__2988
-case__543: case__543
-reg__1257: reg__1257
-logic__1417: logic__1417
-dsp48e1__1: dsp48e1__1
-logic__6351: logic__6351
-case__845: case__845
-logic__6285: logic__6285
-case__115: case__115
-logic__5385: logic__5385
-datapath__206: datapath__206
-logic__2826: logic__2826
-logic__8699: logic__8699
-logic__6644: logic__6644
-logic__682: logic__682
-datapath__281: datapath__281
-logic__8470: logic__8470
-logic__5110: logic__5110
-muxpart__74: muxpart__74
-reg__571: reg__571
-genesys2_rocket_top__GC0: genesys2_rocket_top__GC0
-logic__7460: logic__7460
-reg__1513: reg__783
-logic__4322: logic__4322
-reg__281: reg__281
-case__524: case__524
-logic__9311: logic__476
-logic__8594: logic__8594
-logic__839: logic__839
-case__902: case__902
-case__897: case__897
-logic__1868: logic__1868
-case__1373: case__1373
-dsp48e1__39: dsp48e1__39
-logic__6696: logic__6696
-LevelGateway__3: LevelGateway
-logic__1041: logic__1041
-logic__749: logic__749
-case__1171: case__1171
-logic__2324: logic__2324
-logic__7778: logic__7778
-logic__1152: logic__1152
-case__1194: case__1194
-reg__1456: reg__833
-logic__3832: logic__3832
-logic__7150: logic__7150
-logic__672: logic__672
-case__840: case__840
-logic__6532: logic__6532
-logic__6302: logic__6302
-logic__6199: logic__6199
-logic__9239: logic__640
-logic__9070: logic__1905
-reg__16: reg__16
-datapath__55: datapath__55
-reg__390: reg__390
-reg__634: reg__634
-DMIToTL: DMIToTL
-logic__6642: logic__6642
-logic__8133: logic__8133
-logic__9208: logic__1533
-logic__4762: logic__4762
-reg__409: reg__409
-logic__1413: logic__1413
-logic__1161: logic__1161
-logic__445: logic__445
-ram__13: ram__1
-logic__8499: logic__8499
-logic__8015: logic__8015
-logic__4004: logic__4004
-logic__4523: logic__4523
-logic__5673: logic__5673
-logic__2253: logic__2253
-reg__1222: reg__1222
-reg__125: reg__125
-logic__3991: logic__3991
-datapath__513: datapath__513
-case__1157: case__1157
-reg__1088: reg__1088
-case__1082: case__1082
-datapath__364: datapath__364
-logic__5997: logic__5997
-reg__821: reg__821
-logic__8308: logic__8308
-datapath__628: datapath__628
-logic__4301: logic__4301
-reg__1216: reg__1216
-logic__9055: logic__1838
-logic__4014: logic__4014
-ResetCatchAndSync_d3__1: ResetCatchAndSync_d3
-datapath__571: datapath__571
-reg__350: reg__350
-reg__934: reg__934
-logic__9232: logic__655
-logic__5872: logic__5872
-logic__7571: logic__7571
-Queue1_TLBundleA_a14d64s2k1z4u: Queue1_TLBundleA_a14d64s2k1z4u
-reg__133: reg__133
-logic__7869: logic__7869
-logic__8274: logic__8274
-case__596: case__596
-reg__102: reg__102
-logic__3795: logic__3795
-case__486: case__486
-muxpart__7: muxpart__7
-TLAtomicAutomata_pbus: TLAtomicAutomata_pbus
-ResetCatchAndSync_d3__3: ResetCatchAndSync_d3
-TLPLIC: TLPLIC
-case__1579: case__1414
-logic__4252: logic__4252
-logic__6099: logic__6099
-logic__2481: logic__2481
-logic__3714: logic__3714
-datapath__205: datapath__205
-case__232: case__232
-datapath__481: datapath__481
-logic__2646: logic__2646
-reg__1488: reg__834
-reg__111: reg__111
-logic__2998: logic__2998
-case__397: case__397
-datapath__532: datapath__532
-logic__131: logic__131
-reg__59: reg__59
-logic__7201: logic__7201
-logic__6950: logic__6950
-logic__5059: logic__5059
-case__653: case__653
-logic__9119: logic__1774
-FPToFP: FPToFP
-logic__3766: logic__3766
-logic__4471: logic__4471
-reg__1523: reg__62
-logic__2586: logic__2586
-reg__313: reg__313
-logic__2983: logic__2983
-reg__1376: reg__1141
-case__71: case__71
-logic__1679: logic__1679
-signinv__2: signinv__2
-logic__9278: logic__6120
-logic__6100: logic__6100
-reg__109: reg__109
-reg__614: reg__614
-logic__4233: logic__4233
-logic__6778: logic__6778
-logic__2665: logic__2665
-reg__589: reg__589
-logic__5344: logic__5344
-case__603: case__603
-logic__6475: logic__6475
-case__1554: case__523
-logic__6423: logic__6423
-datapath__482: datapath__482
-reg__127: reg__127
-logic__596: logic__596
-logic__3716: logic__3716
-logic__9117: logic__1782
-muxpart__231: muxpart__231
-keep__13: keep__6
-logic__5250: logic__5250
-logic__484: logic__484
-case__87: case__87
-logic__2098: logic__2098
-logic__692: logic__692
-case__316: case__316
-plusarg_reader: plusarg_reader
-logic__6742: logic__6742
-case__75: case__75
-FPUFMAPipe_l4_f64: FPUFMAPipe_l4_f64
-case__797: case__797
-logic__17: logic__17
-logic__3283: logic__3283
-muxpart__149: muxpart__149
-logic__5336: logic__5336
-reg__512: reg__512
-reg__1389: reg__998
-reg__966: reg__966
-logic__8995: logic__2950
-keep__28: keep__6
-logic__7369: logic__7369
-logic__7933: logic__7933
-cos2x: cos2x
-reg__1418: reg__835
-reg__170: reg__170
-logic__7018: logic__7018
-rf_31x64: rf_31x64
-logic__4681: logic__4681
-datapath__398: datapath__398
-logic__2442: logic__2442
-logic__8710: logic__8710
-case__1213: case__1213
-logic__6210: logic__6210
-case__679: case__679
-case__689: case__689
-reg__1178: reg__1178
-case__916: case__916
-logic__2149: logic__2149
-logic__6799: logic__6799
-reg__490: reg__490
-case__552: case__552
-logic__65: logic__65
-case__901: case__901
-case__710: case__710
-logic__1319: logic__1319
-mult_46_15_61__3: mult_46_15_61
-case__1135: case__1135
-keep__16: keep__6
-datapath__668: datapath__668
-reg__1417: reg__833
-reg__852: reg__852
-case__266: case__266
-logic__2587: logic__2587
-reg__1169: reg__1169
-logic__7679: logic__7679
-logic__3278: logic__3278
-case__1013: case__1013
-case__291: case__291
-reg__431: reg__431
-case__1296: case__1296
-case__127: case__127
-logic__2262: logic__2262
-keep__27: keep__7
-case__948: case__948
-reg__1102: reg__1102
-reg__631: reg__631
-case__506: case__506
-double_ff_syn__5: double_ff_syn
-case__1231: case__1231
-logic__3762: logic__3762
-logic__8681: logic__8681
-logic__1640: logic__1640
-reg__231: reg__231
-reg__1454: reg__835
-logic__5639: logic__5639
-logic__6581: logic__6581
-reg__163: reg__163
-logic__3833: logic__3833
-logic__6472: logic__6472
-logic__4711: logic__4711
-case__404: case__404
-logic__8563: logic__8563
-logic__2860: logic__2860
-logic__1398: logic__1398
-keep__26: keep__8
-case__1506: case__1506
-datapath__544: datapath__544
-case__538: case__538
-reg__766: reg__766
-logic__628: logic__628
-reg__645: reg__645
-case__754: case__754
-logic__7384: logic__7384
-CompareRecFN: CompareRecFN
-Arbiter8_DCacheMetadataReq: Arbiter8_DCacheMetadataReq
-logic__9131: logic__1734
-logic__8215: logic__8215
-logic__4218: logic__4218
-reg__928: reg__928
-logic__8957: logic__8957
-case__1520: case__1520
-logic__3060: logic__3060
-logic__9164: logic__1631
-logic__3729: logic__3729
-logic__3005: logic__3005
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__27: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__61: datapath__61
-reg__1253: reg__1253
-logic__3852: logic__3852
-reg__1068: reg__1068
-case__381: case__381
-datapath__153: datapath__153
-logic__2410: logic__2410
-case__1559: case__518
-muxpart__14: muxpart__14
-logic__5402: logic__5402
-logic__1454: logic__1454
-Queue2_TLBundleD_a29d64s2k1z3u: Queue2_TLBundleD_a29d64s2k1z3u
-logic__6236: logic__6236
-datapath__105: datapath__105
-reg__1093: reg__1093
-datapath__632: datapath__632
-case__180: case__180
-logic__473: logic__473
-logic__8433: logic__8433
-logic__5509: logic__5509
-case__575: case__575
-reg__971: reg__971
-logic__6149: logic__6149
-case__208: case__208
-logic__4348: logic__4348
-datapath__563: datapath__563
-logic__6527: logic__6527
-reg__538: reg__538
-logic__3831: logic__3831
-logic__6033: logic__6033
-reg__135: reg__135
-logic__4710: logic__4710
-reg__255: reg__255
-reg__328: reg__328
-case__523: case__523
-logic__5876: logic__5876
-reg__1056: reg__1056
-case__162: case__162
-logic__768: logic__768
-muxpart__95: muxpart__95
-logic__5984: logic__5984
-logic__3788: logic__3788
-logic__2225: logic__2225
-datapath__329: datapath__329
-logic__6770: logic__6770
-logic__9167: logic__1624
-logic__4605: logic__4605
-dual_port_bram__parameterized0: dual_port_bram__parameterized0
-case__1022: case__1022
-logic__240: logic__240
-logic__5945: logic__5945
-logic__2486: logic__2486
-datapath__286: datapath__286
-logic__9265: logic__8873
-logic__2249: logic__2249
-logic__1705: logic__1705
-logic__4267: logic__4267
-case__102: case__102
-logic__5996: logic__5996
-case__769: case__769
-logic__772: logic__772
-case__1542: case__458
-reg__241: reg__241
-datapath__551: datapath__551
-reg__331: reg__331
-case__331: case__331
-logic__7229: logic__7229
-case__846: case__846
-ClockGroupAggregator_sbus: ClockGroupAggregator_sbus
-logic__7331: logic__7331
-logic__1246: logic__1246
-logic__4791: logic__4791
-logic__2250: logic__2250
-reg__438: reg__438
-case__740: case__740
-reg__96: reg__96
-logic__4142: logic__4142
-logic__1615: logic__1615
-reg__786: reg__786
-ram_2x123: ram_2x123
-logic__2383: logic__2383
-logic__7845: logic__7845
-logic__3685: logic__3685
-case__775: case__775
-case__974: case__974
-logic__1511: logic__1511
-logic__3614: logic__3614
-reg__1508: reg__783
-datapath__134: datapath__134
-logic__1202: logic__1202
-logic__8933: logic__8933
-sync__9: sync
-case__560: case__560
-datapath__118: datapath__118
-logic__5526: logic__5526
-logic__5944: logic__5944
-logic__3617: logic__3617
-datapath__701: datapath__356
-logic__2872: logic__2872
-logic__7578: logic__7578
-logic__6312: logic__6312
-logic__3712: logic__3712
-FPGASPIClockSinkDomain: FPGASPIClockSinkDomain
-counter__23: counter__23
-logic__812: logic__812
-case__994: case__994
-case__86: case__86
-rockettile_icache_data_arrays_512x32: rockettile_icache_data_arrays_512x32
-logic__5461: logic__5461
-logic__1523: logic__1523
-logic__6997: logic__6997
-logic__6715: logic__6715
-reg__763: reg__763
-logic__3395: logic__3395
-datapath__219: datapath__219
-case__206: case__206
-datapath__687: datapath__687
-logic__5631: logic__5631
-logic__4110: logic__4110
-reg__487: reg__487
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__23: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__833: case__833
-logic__8137: logic__8137
-logic__4551: logic__4551
-logic__3945: logic__3945
-logic__8259: logic__8259
-logic__4268: logic__4268
-TLError: TLError
-logic__7790: logic__7790
-datapath__174: datapath__174
-logic__6695: logic__6695
-case__245: case__245
-logic__3540: logic__3540
-reg__67: reg__67
-case__569: case__569
-muxpart__105: muxpart__105
-logic__7303: logic__7303
-datapath__622: datapath__622
-logic__3730: logic__3730
-PTW: PTW
-case__518: case__518
-logic__4369: logic__4369
-logic__1304: logic__1304
-logic__9193: logic__1566
-logic__6322: logic__6322
-logic__8598: logic__8598
-logic__5378: logic__5378
-logic__1455: logic__1455
-logic__9103: logic__1825
-reg__518: reg__518
-logic__5889: logic__5889
-reg__1503: reg__834
-logic__5135: logic__5135
-reg__1407: reg__972
-case__372: case__372
-muxpart__109: muxpart__109
-IntSyncCrossingSource_n1x1__1: IntSyncCrossingSource_n1x1
-reg__240: reg__240
-logic__6748: logic__6748
-datapath__472: datapath__472
-reg__1063: reg__1063
-reg__422: reg__422
-logic__5035: logic__5035
-logic__1595: logic__1595
-rockettile_icache_tag_array_0_64x21: rockettile_icache_tag_array_0_64x21
-reg__545: reg__545
-logic__4799: logic__4799
-case__859: case__859
-reg__605: reg__605
-datapath__147: datapath__147
-logic__2422: logic__2422
-case__732: case__732
-case__1080: case__1080
-reg__747: reg__747
-logic__2689: logic__2689
-case__1277: case__1277
-reg__466: reg__466
-datapath__310: datapath__310
-logic__9295: logic__512
-logic__232: logic__232
-datapath__318: datapath__318
-logic__1279: logic__1279
-case__803: case__803
-logic__870: logic__870
-reg__223: reg__223
-logic__447: logic__447
-logic__4056: logic__4056
-case__1386: case__1386
-datapath__400: datapath__400
-case__860: case__860
-reg__159: reg__159
-logic__9195: logic__1560
-logic__9120: logic__1767
-case__684: case__684
-case__741: case__741
-logic__1838: logic__1838
-AsyncQueueSink_TLBundleD_a9d32s1k1z2u: AsyncQueueSink_TLBundleD_a9d32s1k1z2u
-datapath__560: datapath__560
-logic__7540: logic__7540
-logic__7402: logic__7402
-logic__6533: logic__6533
-reg__126: reg__126
-logic__1612: logic__1612
-logic__8268: logic__8268
-case__1501: case__1501
-reg__907: reg__907
-logic__5859: logic__5859
-logic__6511: logic__6511
-reg__95: reg__95
-logic__4961: logic__4961
-reg__1320: reg__1320
-logic__785: logic__785
-logic__4001: logic__4001
-logic__1026: logic__1026
-logic__3761: logic__3761
-logic__7763: logic__7763
-datapath__456: datapath__456
-case__63: case__63
-logic__6043: logic__6043
-reg__927: reg__927
-logic__9259: logic__8237
-case__844: case__844
-muxpart__22: muxpart__22
-logic__1245: logic__1245
-logic__8587: logic__8587
-datapath__377: datapath__377
-logic__4154: logic__4154
-reg__1091: reg__1091
-logic__8544: logic__8544
-logic__8912: logic__8912
-logic__7374: logic__7374
-logic__6146: logic__6146
-double_ff_syn__parameterized1: double_ff_syn__parameterized1
-logic__9031: logic__3873
-reg__378: reg__378
-logic__8983: logic__2972
-logic__7235: logic__7235
-logic__2702: logic__2702
-case__1185: case__1185
-logic__3459: logic__3459
-reg__1146: reg__1146
-logic__1558: logic__1558
-case__296: case__296
-case__885: case__885
-logic__9012: logic__3924
-logic__3339: logic__3339
-reg__1294: reg__1294
-logic__9026: logic__3903
-case__1190: case__1190
-logic__2239: logic__2239
-logic__2585: logic__2585
-logic__7523: logic__7523
-reg__657: reg__657
-logic__945: logic__945
-reg__1176: reg__1176
-logic__4074: logic__4074
-logic__3107: logic__3107
-logic__1226: logic__1226
-datapath__598: datapath__598
-keep__3: keep__3
-reg__965: reg__965
-mult_46_15_61: mult_46_15_61
-datapath__439: datapath__439
-logic__2289: logic__2289
-logic__3616: logic__3616
-reg__1430: reg__835
-logic__2343: logic__2343
-logic__9016: logic__3913
-logic__1555: logic__1555
-logic__578: logic__578
-case__298: case__298
-logic__4734: logic__4734
-logic__6186: logic__6186
-case__148: case__148
-case__587: case__587
-logic__2552: logic__2552
-logic__8768: logic__8768
-reg__373: reg__373
-logic__3544: logic__3544
-logic__6771: logic__6771
-logic__2917: logic__2917
-datapath__390: datapath__390
-datapath__371: datapath__371
-logic__2700: logic__2700
-case__568: case__568
-logic__6934: logic__6934
-logic__9258: logic__8234
-logic__7052: logic__7052
-logic__177: logic__177
-reg__303: reg__303
-logic__6643: logic__6643
-case__41: case__41
-logic__6232: logic__6232
-reg__20: reg__20
-case__765: case__765
-logic__6113: logic__6113
-logic__3646: logic__3646
-logic__1504: logic__1504
-reg__656: reg__656
-reg__136: reg__136
-reg__573: reg__573
-logic__8684: logic__8684
-logic__1404: logic__1404
-case__255: case__255
-reg__729: reg__729
-reg__1252: reg__1252
-case__1304: case__1304
-logic__5278: logic__5278
-reg__1442: reg__835
-logic__8241: logic__8241
-logic__4732: logic__4732
-case__505: case__505
-logic__2667: logic__2667
-logic__6699: logic__6699
-case__22: case__22
-logic__6020: logic__6020
-reg__1140: reg__1140
-logic__248: logic__248
-reg__1372: reg__1141
-case__1000: case__1000
-muxpart__43: muxpart__43
-logic__8765: logic__8765
-case__1552: case__526
-logic__2240: logic__2240
-logic__4989: logic__4989
-datapath__608: datapath__608
-logic__244: logic__244
-addsub__1: addsub__1
-datapath__569: datapath__569
-TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u: TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u
-logic__6473: logic__6473
-case__521: case__521
-datapath__742: datapath__95
-datapath__67: datapath__67
-reg__732: reg__732
-case__1576: case__303
-datapath__201: datapath__201
-logic__811: logic__811
-datapath__95: datapath__95
-datapath__654: datapath__654
-logic__9284: logic__6120
-logic__854: logic__854
-logic__1874: logic__1874
-reg__1278: reg__1278
-logic__8625: logic__8625
-case__824: case__824
-datapath__76: datapath__76
-case__1062: case__1062
-muxpart__39: muxpart__39
-logic__2320: logic__2320
-logic__6200: logic__6200
-logic__8175: logic__8175
-logic__3751: logic__3751
-reg: reg
-logic__7330: logic__7330
-logic__6488: logic__6488
-logic__9085: logic__1869
-logic__3715: logic__3715
-reg__227: reg__227
-logic__273: logic__273
-logic__5262: logic__5262
-reg__842: reg__842
-logic__483: logic__483
-reg__1315: reg__1315
-logic__1353: logic__1353
-ram_2x77: ram_2x77
-reg__104: reg__104
-logic__8024: logic__8024
-logic__8814: logic__8814
-reg__777: reg__777
-logic__2332: logic__2332
-reg__499: reg__499
-logic__2178: logic__2178
-DTLB: DTLB
-datapath__633: datapath__633
-logic__2684: logic__2684
-case__829: case__829
-AsyncValidSync__5: AsyncValidSync
-datapath__599: datapath__599
-logic__5177: logic__5177
-sync: sync
-case__235: case__235
-datapath__417: datapath__417
-logic__2315: logic__2315
-reg__452: reg__452
-case__545: case__545
-case__823: case__823
-logic__6087: logic__6087
-logic__8873: logic__8873
-case__1036: case__1036
-logic__5954: logic__5954
-datapath__517: datapath__517
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__24: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__161: reg__161
-logic__4657: logic__4657
-logic__4798: logic__4798
-reg__608: reg__608
-logic__8856: logic__8856
-logic__9257: logic__8235
-logic__3605: logic__3605
-logic__538: logic__538
-logic__1540: logic__1540
-logic__1614: logic__1614
-reg__1224: reg__1224
-reg__1272: reg__1272
-BreakpointUnit: BreakpointUnit
-logic__3633: logic__3633
-logic__1089: logic__1089
-case__532: case__532
-logic__1199: logic__1199
-datapath__444: datapath__444
-datapath__576: datapath__576
-logic__2382: logic__2382
-reg__899: reg__899
-logic__6507: logic__6507
-datapath__33: datapath__33
-logic__5525: logic__5525
-reg__1500: reg__834
-TLXbar_cbus_in_i1_o1_a32d64s2k1z4u: TLXbar_cbus_in_i1_o1_a32d64s2k1z4u
-reg__1100: reg__1100
-case__1170: case__1170
-logic__1461: logic__1461
-DivSqrtRecFN_small_1: DivSqrtRecFN_small_1
-reg__827: reg__827
-reg__210: reg__210
-logic__9148: logic__1679
-reg__45: reg__45
-reg__243: reg__243
-logic__6747: logic__6747
-logic__482: logic__482
-case__940: case__940
-datapath__617: datapath__617
-logic__7717: logic__7717
-case__512: case__512
-logic__1283: logic__1283
-keep__9: keep__9
-datapath__454: datapath__454
-logic__9287: logic__6125
-reg__1301: reg__1301
-reg__92: reg__92
-case__348: case__348
-logic__4274: logic__4274
-counter__26: counter__26
-logic__361: logic__361
-case__21: case__21
-reg__414: reg__414
-datapath__479: datapath__479
-case__161: case__161
-logic__6782: logic__6782
-logic__1481: logic__1481
-logic__1261: logic__1261
-logic__930: logic__930
-logic__8910: logic__8910
-case__1060: case__1060
-logic__2846: logic__2846
-logic__2316: logic__2316
-reg__139: reg__139
-logic__3335: logic__3335
-reg__297: reg__297
-reg__958: reg__958
-muxpart__51: muxpart__51
-logic__6652: logic__6652
-dual_port_bram: dual_port_bram
-logic__1071: logic__1071
-reg__892: reg__892
-logic__6713: logic__6713
-reg__782: reg__782
-logic__693: logic__693
-reg__84: reg__84
-dsp48e1: dsp48e1
-logic__3629: logic__3629
-logic__2213: logic__2213
-logic__8911: logic__8911
-datapath__663: datapath__663
-keep__46: keep__1
-case__739: case__739
-logic__6548: logic__6548
-logic__3445: logic__3445
-logic__6105: logic__6105
-logic__3740: logic__3740
-reg__259: reg__259
-binary_to_gray: binary_to_gray
-logic__6474: logic__6474
-logic__196: logic__196
-logic__6553: logic__6553
-logic__644: logic__644
-logic__8312: logic__8312
-reg__713: reg__713
-reg__405: reg__405
-logic__5188: logic__5188
-rom__3: rom__3
-case__572: case__572
-datapath__217: datapath__217
-logic__8370: logic__8370
-logic__7087: logic__7087
-datapath__41: datapath__41
-case__1048: case__1048
-reg__964: reg__964
-datapath__572: datapath__572
-logic__4315: logic__4315
-logic__5426: logic__5426
-logic__3064: logic__3064
-datapath__226: datapath__226
-logic__18: logic__18
-logic__7518: logic__7518
-logic__8738: logic__8738
-logic__1354: logic__1354
-logic__7247: logic__7247
-case__1187: case__1187
-logic__130: logic__130
-reg__1292: reg__1292
-logic__6133: logic__6133
-reg__1344: reg__1344
-datapath__423: datapath__423
-case__1287: case__1287
-logic__2452: logic__2452
-datapath__381: datapath__381
-logic__5052: logic__5052
-logic__950: logic__950
-logic__8286: logic__8286
-case__247: case__247
-logic__1027: logic__1027
-dsp48e1__32: dsp48e1__32
-logic__7596: logic__7596
-logic__7262: logic__7262
-reg__80: reg__80
-case__773: case__773
-logic__9191: logic__1570
-reg__337: reg__337
-datapath__395: datapath__395
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__4: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__1122: reg__1122
-case__1299: case__1299
-divider_fsm: divider_fsm
-case__559: case__559
-reg__447: reg__447
-logic__5223: logic__5223
-logic__611: logic__611
-logic__8714: logic__8714
-logic__5502: logic__5502
-logic__8944: logic__8944
-case__862: case__862
-logic__8931: logic__8931
-datapath__542: datapath__542
-muxpart__216: muxpart__216
-logic__2530: logic__2530
-reg__1258: reg__1258
-logic__1028: logic__1028
-logic__6547: logic__6547
-case__691: case__691
-reg__922: reg__922
-logic__9068: logic__1909
-case__465: case__465
-muxpart__67: muxpart__67
-addsub__4: addsub__4
-reg__1042: reg__1042
-case__707: case__707
-reg__994: reg__994
-case__473: case__473
-reg__1087: reg__1087
-logic__3418: logic__3418
-reg__1111: reg__1111
-FPUFMAPipe_l3_f32: FPUFMAPipe_l3_f32
-logic__6783: logic__6783
-reg__148: reg__148
-muxpart__62: muxpart__62
-case__1529: case__1529
-logic__8767: logic__8767
-logic__3153: logic__3153
-reg__317: reg__317
-muxpart__55: muxpart__55
-logic__4314: logic__4314
-logic__1375: logic__1375
-case__1078: case__1078
-case__362: case__362
-logic__3697: logic__3697
-reg__637: reg__637
-logic__7217: logic__7217
-reg__1295: reg__1295
-logic__6128: logic__6128
-logic__3514: logic__3514
-logic__7007: logic__7007
-logic__891: logic__891
-datapath__392: datapath__392
-logic__6147: logic__6147
-logic__7848: logic__7848
-case__666: case__666
-reg__14: reg__14
-logic__7103: logic__7103
-reg__1194: reg__1194
-case__542: case__542
-logic__7093: logic__7093
-logic__2204: logic__2204
-logic__6544: logic__6544
-logic__5877: logic__5877
-logic__3765: logic__3765
-signinv__1: signinv__1
-logic__3156: logic__3156
-logic__2354: logic__2354
-logic__4596: logic__4596
-logic__2464: logic__2464
-logic__4643: logic__4643
-reg__39: reg__39
-keep__21: keep__7
-logic__5386: logic__5386
-logic__2561: logic__2561
-case__295: case__295
-case__819: case__819
-logic__3505: logic__3505
-case__950: case__950
-reg__568: reg__568
-logic__2077: logic__2077
-logic__7364: logic__7364
-logic__2223: logic__2223
-logic__3548: logic__3548
-case__1462: case__1462
-logic__118: logic__118
-reg__654: reg__654
-logic__928: logic__928
-logic__6468: logic__6468
-datapath__63: datapath__63
-logic__5803: logic__5803
-logic__795: logic__795
-reg__745: reg__745
-logic__6723: logic__6723
-case__1424: case__1424
-logic__5209: logic__5209
-logic__9268: logic__7550
-logic__612: logic__612
-case__85: case__85
-logic__7551: logic__7551
-AsyncValidSync__12: AsyncValidSync
-reg__1411: reg__833
-logic__9308: logic__479
-logic__5202: logic__5202
-logic__5495: logic__5495
-case__1165: case__1165
-reg__98: reg__98
-logic__2027: logic__2027
-gray_to_binary__2: gray_to_binary
-logic__1570: logic__1570
-muxpart__13: muxpart__13
-logic__5331: logic__5331
-case__970: case__970
-case__228: case__228
-case__205: case__205
-logic__386: logic__386
-logic__6021: logic__6021
-logic__6427: logic__6427
-logic__5423: logic__5423
-logic__8243: logic__8243
-reg__671: reg__671
-case__866: case__866
-Queue2_TLBundleA_a29d64s2k1z3u: Queue2_TLBundleA_a29d64s2k1z3u
-logic__2224: logic__2224
-dsp48e1__17: dsp48e1__17
-datapath__267: datapath__267
-case__698: case__698
-case__571: case__571
-logic__4610: logic__4610
-case__883: case__883
-datapath__64: datapath__64
-AsyncResetSynchronizerShiftReg_w1_d3_i0__1: AsyncResetSynchronizerShiftReg_w1_d3_i0
-case__437: case__437
-datapath__351: datapath__351
-logic__370: logic__370
-logic__2879: logic__2879
-logic__1332: logic__1332
-reg__160: reg__160
-logic__7241: logic__7241
-logic__1548: logic__1548
-logic__1609: logic__1609
-datapath__157: datapath__157
-logic__8481: logic__8481
-case__836: case__836
-case__813: case__813
-case__1018: case__1018
-addsub: addsub
-logic__4619: logic__4619
-logic__8323: logic__8323
-reg__154: reg__154
-datapath__50: datapath__50
-muxpart__75: muxpart__75
-dsp48e1__31: dsp48e1__31
-reg__308: reg__308
-logic__7127: logic__7127
-logic__6873: logic__6873
-logic__9075: logic__1894
-logic__2809: logic__2809
-AsyncValidSync__9: AsyncValidSync
-reg__355: reg__355
-reg__1116: reg__1116
-case__324: case__324
-logic__6233: logic__6233
-reg__919: reg__919
-logic__2447: logic__2447
-logic__4833: logic__4833
-logic__883: logic__883
-logic__8926: logic__8926
-case__1420: case__1420
-Queue2_TLBundleD_a32d64s1k1z4u__1: Queue2_TLBundleD_a32d64s1k1z4u
-logic__9082: logic__1872
-datapath__578: datapath__578
-logic__4881: logic__4881
-datapath__237: datapath__237
-reg__266: reg__266
-datapath__469: datapath__469
-logic__478: logic__478
-rockettile_icache_data_arrays_512x32__1: rockettile_icache_data_arrays_512x32
-logic__962: logic__962
-reg__468: reg__468
-case__195: case__195
-logic__9306: logic__483
-logic__8140: logic__8140
-case__395: case__395
-datapath__658: datapath__658
-logic__6703: logic__6703
-muxpart__104: muxpart__104
-case__703: case__703
-reg__594: reg__594
-logic__7368: logic__7368
-accum_dump: accum_dump
-logic__9283: logic__6125
-reg__1400: reg__833
-logic__3820: logic__3820
-extladd: extladd
-logic__9204: logic__1541
-reg__1429: reg__833
-logic__1282: logic__1282
-logic__182: logic__182
-logic__9059: logic__1828
-logic__8685: logic__8685
-datapath__261: datapath__261
-logic__7559: logic__7559
-logic__6905: logic__6905
-FixedClockBroadcast_1__1: FixedClockBroadcast_1
-datapath__203: datapath__203
-datapath__387: datapath__387
-logic__9140: logic__1705
-case__1505: case__1505
-case__771: case__771
-logic__1894: logic__1894
-muxpart__23: muxpart__23
-case__194: case__194
-reg__1343: reg__1343
-reg__909: reg__909
-logic__5523: logic__5523
-logic__7064: logic__7064
-logic__6378: logic__6378
-case__1563: case__316
-logic__9326: logic__257
-logic__2016: logic__2016
-logic__1213: logic__1213
-case__215: case__215
-logic__3754: logic__3754
-logic__5281: logic__5281
-logic__3126: logic__3126
-datapath__290: datapath__290
-logic__4467: logic__4467
-logic__2696: logic__2696
-logic__6645: logic__6645
-logic__2430: logic__2430
-logic__6110: logic__6110
-datapath__74: datapath__74
-reg__1405: reg__834
-reg__1155: reg__1155
-logic__4980: logic__4980
-logic__9030: logic__3874
-datapath__747: datapath__17
-logic__1632: logic__1632
-Repeater_TLBundleA_a32d64s2k1z3u: Repeater_TLBundleA_a32d64s2k1z3u
-logic__8752: logic__8752
-logic__4294: logic__4294
-case__25: case__25
-logic__4713: logic__4713
-logic__6431: logic__6431
-logic__4550: logic__4550
-reg__1355: reg__31
-muxpart__58: muxpart__58
-case__553: case__553
-datapath__380: datapath__380
-logic__8325: logic__8325
-logic__7693: logic__7693
-reg__502: reg__502
-logic__6358: logic__6358
-logic__5993: logic__5993
-logic__124: logic__124
-logic__4826: logic__4826
-reg__653: reg__653
-logic__933: logic__933
-case__747: case__747
-logic__4554: logic__4554
-case__1338: case__1338
-datapath__609: datapath__609
-logic__1847: logic__1847
-case__346: case__346
-logic__6549: logic__6549
-logic__365: logic__365
-logic__1938: logic__1938
-logic__8277: logic__8277
-logic__3811: logic__3811
-case__356: case__356
-case__234: case__234
-logic__9051: logic__1850
-logic__2511: logic__2511
-reg__225: reg__225
-logic__4459: logic__4459
-logic__8355: logic__8355
-datapath__491: datapath__491
-datapath__470: datapath__470
-logic__6603: logic__6603
-case__887: case__887
-reg__650: reg__650
-ram_2x77__3: ram_2x77
-case__500: case__500
-butterfly: butterfly
-logic__6956: logic__6956
-logic__6774: logic__6774
-case__265: case__265
-logic__2163: logic__2163
-acq_top: acq_top
-logic__1647: logic__1647
-logic__2699: logic__2699
-reg__1242: reg__1242
-logic__2937: logic__2937
-case__1502: case__1502
-logic__353: logic__353
-logic__2032: logic__2032
-logic__8884: logic__8884
-reg__591: reg__591
-logic__8997: logic__2943
-case__1423: case__1423
-case__1019: case__1019
-logic__394: logic__394
-reg__734: reg__734
-logic__8397: logic__8397
-logic__9097: logic__1835
-reg__611: reg__611
-logic__6215: logic__6215
-case__767: case__767
-logic__6016: logic__6016
-logic__748: logic__748
-TLWidthWidget8_3: TLWidthWidget8_3
-case__1548: case__451
-reg__916: reg__916
-logic__808: logic__808
-datapath__666: datapath__666
-logic__1832: logic__1832
-ErrorDeviceWrapper: ErrorDeviceWrapper
-case__1101: case__1101
-logic__3611: logic__3611
-datapath__363: datapath__363
-logic__7636: logic__7636
-logic__8374: logic__8374
-logic__4477: logic__4477
-logic__2672: logic__2672
-muxpart__91: muxpart__91
-case__959: case__959
-logic__6336: logic__6336
-logic__2892: logic__2892
-logic__9214: logic__1521
-reg__688: reg__688
-logic__282: logic__282
-logic__5247: logic__5247
-case__292: case__292
-reg__5: reg__5
-logic__338: logic__338
-reg__11: reg__11
-logic__6940: logic__6940
-reg__1390: reg__997
-datapath__396: datapath__396
-reg__588: reg__588
-datapath__57: datapath__57
-case__1189: case__1189
-logic__5310: logic__5310
-reg__1415: reg__835
-logic__925: logic__925
-case__1097: case__1097
-DCache: DCache
-logic__7966: logic__7966
-logic__1445: logic__1445
-datapath__413: datapath__413
-logic__7527: logic__7527
-case__110: case__110
-case__423: case__423
-logic__2668: logic__2668
-AsyncQueueSource_TLBundleD_a9d32s1k1z2u: AsyncQueueSource_TLBundleD_a9d32s1k1z2u
-logic__6017: logic__6017
-LevelGateway__7: LevelGateway
-reg__128: reg__128
-logic__3992: logic__3992
-logic__4786: logic__4786
-logic__8955: logic__8955
-case__51: case__51
-reg__1112: reg__1112
-reg__1331: reg__1331
-logic__1284: logic__1284
-case__908: case__908
-case__1591: case__1402
-logic__5893: logic__5893
-case__849: case__849
-reg__1328: reg__1328
-logic__2164: logic__2164
-logic__2518: logic__2518
-logic__5025: logic__5025
-logic__5436: logic__5436
-logic__1569: logic__1569
-logic__5379: logic__5379
-ClockCrossingReg_w15: ClockCrossingReg_w15
-reg__678: reg__678
-logic__5888: logic__5888
-logic__4035: logic__4035
-case__1186: case__1186
-datapath__659: datapath__659
-reg__116: reg__116
-logic__2023: logic__2023
-case__170: case__170
-logic__5629: logic__5629
-logic__2527: logic__2527
-case__264: case__264
-logic__6546: logic__6546
-IntSyncCrossingSource_n1x1__2: IntSyncCrossingSource_n1x1
-case__678: case__678
-logic__269: logic__269
-case__1334: case__1334
-logic__7426: logic__7426
-logic__3713: logic__3713
-logic__7625: logic__7625
-logic__8184: logic__8184
-logic__6522: logic__6522
-case__694: case__694
-reg__88: reg__88
-logic__6270: logic__6270
-logic__6768: logic__6768
-datapath__710: datapath__241
-reg__996: reg__996
-case__906: case__906
-reg__370: reg__370
-dsp48e1__42: dsp48e1__42
-cdc_fifo_gray_src: cdc_fifo_gray_src
-case__976: case__976
-reg__26: reg__26
-case__1543: case__457
-logic__4412: logic__4412
-logic__1577: logic__1577
-logic__9101: logic__1827
-case__8: case__8
-datapath__285: datapath__285
-case__308: case__308
-reg__1000: reg__1000
-datapath__525: datapath__525
-logic__9020: logic__3909
-logic__6112: logic__6112
-reg__177: reg__177
-logic__4834: logic__4834
-case__776: case__776
-case__407: case__407
-logic__6929: logic__6929
-logic__9233: logic__654
-logic__7378: logic__7378
-reg__505: reg__505
-case__1378: case__1378
-logic__2706: logic__2706
-reg__77: reg__77
-reg__101: reg__101
-logic__2293: logic__2293
-case__815: case__815
-reg__593: reg__593
-datapath__65: datapath__65
-reg__228: reg__228
-case__900: case__900
-FixedClockBroadcast_1: FixedClockBroadcast_1
-datapath__427: datapath__427
-logic__6604: logic__6604
-reg__672: reg__672
-logic__532: logic__532
-case__118: case__118
-case__856: case__856
-logic__9324: logic__259
-logic__4055: logic__4055
-logic__4644: logic__4644
-logic__8666: logic__8666
-logic__6554: logic__6554
-logic__2701: logic__2701
-logic__4229: logic__4229
-logic__4311: logic__4311
-reg__1205: reg__1205
-case__631: case__631
-reg__1190: reg__1190
-reg__731: reg__731
-logic__9253: logic__8235
-case__1298: case__1298
-reg__517: reg__517
-datapath__258: datapath__258
-logic__4421: logic__4421
-logic__4139: logic__4139
-case__1566: case__313
-logic__3402: logic__3402
-logic__8876: logic__8876
-reg__449: reg__449
-logic__9240: logic__639
-logic__453: logic__453
-case__638: case__638
-case__930: case__930
-logic__3853: logic__3853
-TLBuffer_a32d64s1k1z4u_1: TLBuffer_a32d64s1k1z4u_1
-case__1301: case__1301
-logic__7268: logic__7268
-muxpart__89: muxpart__89
-datapath__697: datapath__360
-logic__6813: logic__6813
-case__1452: case__1452
-reg__358: reg__358
-case__730: case__730
-datapath__739: datapath__135
-logic__7934: logic__7934
-AsyncResetSynchronizerShiftReg_w1_d3_i0__12: AsyncResetSynchronizerShiftReg_w1_d3_i0
-case__1578: case__1415
-logic__2989: logic__2989
-reg__741: reg__741
-case__221: case__221
-logic__8952: logic__8952
-case__1530: case__1530
-RocketTile__GCB0: RocketTile__GCB0
-datapath__749: datapath__15
-reg__216: reg__216
-logic__7962: logic__7962
-logic__7418: logic__7418
-reg__1142: reg__1142
-logic__6670: logic__6670
-logic__1156: logic__1156
-case__876: case__876
-logic__4842: logic__4842
-logic__1827: logic__1827
-logic__6183: logic__6183
-logic__6032: logic__6032
-logic__710: logic__710
-datapath__425: datapath__425
-reg__470: reg__470
-case__190: case__190
-logic__7160: logic__7160
-cordic_angle_lut__parameterized0__1: cordic_angle_lut__parameterized0
-datapath__453: datapath__453
-TLInterconnectCoupler_cbus_to_debug: TLInterconnectCoupler_cbus_to_debug
-logic__7196: logic__7196
-logic__448: logic__448
-logic__7102: logic__7102
-logic__4107: logic__4107
-logic__5527: logic__5527
-reg__1387: reg__997
-logic__9118: logic__1779
-logic__1460: logic__1460
-case__1418: case__1418
-reg__813: reg__813
-logic__7195: logic__7195
-logic__584: logic__584
-datapath__719: datapath__114
-logic__934: logic__934
-logic__8686: logic__8686
-case__574: case__574
-logic__8753: logic__8753
-logic__4273: logic__4273
-logic__3354: logic__3354
-reg__931: reg__931
-case__1602: case__97
-logic__1936: logic__1936
-logic__606: logic__606
-case__441: case__441
-logic__1560: logic__1560
-datapath__204: datapath__204
-logic__2703: logic__2703
-reg__1131: reg__1131
-logic__5204: logic__5204
-logic__8265: logic__8265
-logic__8769: logic__8769
-reg__857: reg__857
-bram__parameterized0: bram__parameterized0
-butterfly__parameterized0: butterfly__parameterized0
-RoundRawFNToRecFN_1__1: RoundRawFNToRecFN_1
-case__615: case__615
-logic__4757: logic__4757
-ram__15: ram
-logic__9145: logic__1686
-logic__9021: logic__3908
-logic__2697: logic__2697
-logic__2818: logic__2818
-gray_to_binary__1: gray_to_binary
-logic__6476: logic__6476
-logic__7855: logic__7855
-muxpart__68: muxpart__68
-logic__8672: logic__8672
-reg__699: reg__699
-extladd__2: extladd__2
-datapath__604: datapath__604
-logic__2677: logic__2677
-case__1049: case__1049
-case__785: case__785
-logic__966: logic__966
-reg__324: reg__324
-logic__2850: logic__2850
-logic__4111: logic__4111
-logic__6730: logic__6730
-datapath__549: datapath__549
-datapath__347: datapath__347
-datapath__580: datapath__580
-logic__2053: logic__2053
-case__341: case__341
-datapath__53: datapath__53
-logic__2333: logic__2333
-reg__986: reg__986
-reg__1270: reg__1270
-ClockCrossingReg_w55: ClockCrossingReg_w55
-logic__4888: logic__4888
-logic__2101: logic__2101
-reg__467: reg__467
-datapath__492: datapath__492
-logic__6355: logic__6355
-logic__7704: logic__7704
-case__998: case__998
-logic__5963: logic__5963
-logic__5994: logic__5994
-logic__6384: logic__6384
-case__201: case__201
-case__1441: case__1441
-logic__6115: logic__6115
-logic__7923: logic__7923
-logic__2220: logic__2220
-logic__5335: logic__5335
-case__980: case__980
-logic__9005: logic__3939
-case__50: case__50
-logic__8973: logic__2995
-datapath__358: datapath__358
-logic__1434: logic__1434
-case__196: case__196
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__13: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__81: reg__81
-logic__7401: logic__7401
-datapath__496: datapath__496
-case__202: case__202
-case__777: case__777
-logic__6160: logic__6160
-reg__1193: reg__1193
-logic__7409: logic__7409
-logic__1934: logic__1934
-logic__2390: logic__2390
-logic__7319: logic__7319
-case__923: case__923
-logic__9186: logic__1579
-FPGAUARTClockSinkDomain: FPGAUARTClockSinkDomain
-logic__259: logic__259
-reg__1002: reg__1002
-datapath__648: datapath__648
-logic__3182: logic__3182
-reg__192: reg__192
-logic__6111: logic__6111
-reg__1059: reg__1059
-logic__1469: logic__1469
-reg__801: reg__801
-reg__1173: reg__1173
-case__159: case__159
-logic__2214: logic__2214
-logic__7844: logic__7844
-logic__6780: logic__6780
-case__700: case__700
-muxpart__102: muxpart__102
-APBGpsBlock__GC0: APBGpsBlock__GC0
-logic__995: logic__995
-reg__1065: reg__1065
-logic__5883: logic__5883
-datapath__409: datapath__409
-case__229: case__229
-logic__6946: logic__6946
-case__39: case__39
-datapath__671: datapath__671
-logic__8590: logic__8590
-logic__1049: logic__1049
-logic__38: logic__38
-logic__659: logic__659
-acq_ca_gen: acq_ca_gen
-reg__1530: reg__31
-ram__3: ram__3
-logic__6241: logic__6241
-case__321: case__321
-logic__3460: logic__3460
-datapath__303: datapath__303
-logic__7082: logic__7082
-logic__1448: logic__1448
-logic__2284: logic__2284
-logic__834: logic__834
-logic__8756: logic__8756
-logic__5258: logic__5258
-case__2: case__2
-datapath__744: datapath__20
-case__319: case__319
-case__171: case__171
-reg__601: reg__601
-logic__4280: logic__4280
-logic__507: logic__507
-logic__6154: logic__6154
-logic__7639: logic__7639
-logic__1850: logic__1850
-RoundAnyRawFNToRecFN: RoundAnyRawFNToRecFN
-logic__3842: logic__3842
-logic__5325: logic__5325
-reg__301: reg__301
-logic__9025: logic__3904
-logic__6758: logic__6758
-logic__3702: logic__3702
-RoundRawFNToRecFN__1: RoundRawFNToRecFN
-reg__348: reg__348
-case__1513: case__1513
-muxpart__37: muxpart__37
-case__5: case__5
-logic__4623: logic__4623
-case__13: case__13
-logic__5865: logic__5865
-logic__4464: logic__4464
-logic__4936: logic__4936
-case__494: case__494
-logic__7312: logic__7312
-logic__6787: logic__6787
-logic__5055: logic__5055
-datapath__690: datapath__690
-logic__8595: logic__8595
-reg__457: reg__457
-case__734: case__734
-logic__1957: logic__1957
-case__1371: case__1371
-logic__3821: logic__3821
-logic__5363: logic__5363
-reg__511: reg__511
-case__644: case__644
-datapath__145: datapath__145
-logic__5440: logic__5440
-reg__97: reg__97
-logic__375: logic__375
-Frontend: Frontend
-logic__5141: logic__5141
-logic__1301: logic__1301
-logic__9130: logic__1739
-logic__3547: logic__3547
-logic__7382: logic__7382
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__3: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__2968: logic__2968
-logic__3359: logic__3359
-reg__995: reg__995
-case__963: case__963
-dsp48e1__12: dsp48e1__12
-reg__1157: reg__1157
-datapath__27: datapath__27
-ram_2x120__1: ram_2x120
-case__1161: case__1161
-datapath__45: datapath__45
-reg__382: reg__382
-logic__8383: logic__8383
-reg__526: reg__526
-logic__6589: logic__6589
-logic__5460: logic__5460
-reg__1148: reg__1148
-logic__4873: logic__4873
-LevelGateway__8: LevelGateway
-logic__1205: logic__1205
-datapath__383: datapath__383
-logic__4085: logic__4085
-logic__8782: logic__8782
-double_ff_syn__parameterized0: double_ff_syn__parameterized0
-datapath__691: datapath__691
-datapath__480: datapath__480
-reg__1507: reg__783
-logic__6655: logic__6655
-ram__2: ram__2
-reg__580: reg__580
-logic__6106: logic__6106
-logic__6177: logic__6177
-reg__376: reg__376
-dsp48e1__47: dsp48e1__47
-reg__1473: reg__834
-reg__120: reg__120
-logic__3907: logic__3907
-logic__6729: logic__6729
-addsub__3: addsub__3
-datapath__339: datapath__339
-logic__585: logic__585
-logic__8964: logic__8964
-reg__6: reg__6
-case__1329: case__1329
-logic__8391: logic__8391
-case__444: case__444
-case__1139: case__1139
-trck_top: trck_top
-reg__1179: reg__1179
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__35: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__262: case__262
-RVCExpander: RVCExpander
-logic__5425: logic__5425
-logic__3719: logic__3719
-muxpart__1: muxpart__1
-logic__9310: logic__477
-case__683: case__683
-logic__4182: logic__4182
-logic__357: logic__357
-logic__9241: logic__8452
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__12: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__9188: logic__1577
-case__904: case__904
-logic__8945: logic__8945
-logic__5630: logic__5630
-logic__7001: logic__7001
-datapath__646: datapath__646
-reg__399: reg__399
-logic__8410: logic__8410
-case__1413: case__1413
-logic__9323: logic__262
-logic__4660: logic__4660
-case__1002: case__1002
-logic__3824: logic__3824
-datapath__14: datapath__14
-reg__279: reg__279
-reg__579: reg__579
-case__1349: case__1349
-datapath__216: datapath__216
-case__554: case__554
-logic__4894: logic__4894
-RoundAnyRawFNToRecFN_4: RoundAnyRawFNToRecFN_4
-logic__9189: logic__1576
-logic__655: logic__655
-case__672: case__672
-logic__1067: logic__1067
-logic__820: logic__820
-reg__1050: reg__1050
-keep__47: keep
-reg__630: reg__630
-logic__6756: logic__6756
-logic__1727: logic__1727
-case__6: case__6
-logic__4895: logic__4895
-datapath__733: datapath__645
-logic__7376: logic__7376
-datapath__207: datapath__207
-logic__5858: logic__5858
-logic__4449: logic__4449
-case__606: case__606
-logic__1912: logic__1912
-case__27: case__27
-reg__781: reg__781
-reg__122: reg__122
-case__120: case__120
-logic__6155: logic__6155
-datapath__393: datapath__393
-case__533: case__533
-case__621: case__621
-logic__5017: logic__5017
-logic__2622: logic__2622
-logic__4121: logic__4121
-logic__4608: logic__4608
-logic__4171: logic__4171
-logic__9102: logic__1826
-logic__1185: logic__1185
-logic__5253: logic__5253
-case__1166: case__1166
-logic__2106: logic__2106
-logic__9205: logic__1540
-logic__6651: logic__6651
-cacode_gen_trck: cacode_gen_trck
-logic__6700: logic__6700
-logic__6145: logic__6145
-reg__926: reg__926
-case__1385: case__1385
-case__1042: case__1042
-case__1416: case__1416
-logic__4616: logic__4616
-dsp48e1__5: dsp48e1__5
-case__907: case__907
-logic__9013: logic__3921
-datapath__447: datapath__447
-case__692: case__692
-logic__5307: logic__5307
-logic__1937: logic__1937
-logic__3817: logic__3817
-logic__8982: logic__2976
-reg__29: reg__29
-logic__6340: logic__6340
-reg__639: reg__639
-logic__1576: logic__1576
-datapath__5: datapath__5
-logic__4738: logic__4738
-logic__9207: logic__1534
-datapath__299: datapath__299
-case__147: case__147
-case__144: case__144
-dsp48e1__37: dsp48e1__37
-reg__10: reg__10
-addsub__5: addsub__5
-logic__3160: logic__3160
-case__1442: case__1442
-logic__8628: logic__8628
-reg__507: reg__507
-case__1004: case__1004
-case__788: case__788
-datapath__645: datapath__645
-logic__8866: logic__8866
-reg__1275: reg__1275
-logic__4349: logic__4349
-reg__86: reg__86
-reg__1127: reg__1127
-logic__5361: logic__5361
-logic__9206: logic__1537
-datapath__200: datapath__200
-mult_30_25_55: mult_30_25_55
-reg__833: reg__833
-reg__980: reg__980
-reg__992: reg__992
-logic__614: logic__614
-logic__4911: logic__4911
-logic__8795: logic__8795
-logic__4262: logic__4262
-reg__954: reg__954
-logic__4656: logic__4656
-logic__2862: logic__2862
-logic__8040: logic__8040
-case__1414: case__1414
-logic__8724: logic__8724
-reg__541: reg__541
-datapath__735: datapath__513
-logic__4880: logic__4880
-logic__1126: logic__1126
-datapath__376: datapath__376
-logic__4455: logic__4455
-logic__9219: logic__1508
-case__1031: case__1031
-reg__1467: reg__834
-logic__5462: logic__5462
-logic__9017: logic__3912
-case__699: case__699
-reg__974: reg__974
-case__563: case__563
-logic__4052: logic__4052
-logic__6357: logic__6357
-muxpart__66: muxpart__66
-case__939: case__939
-logic__7313: logic__7313
-datapath__585: datapath__585
-case__241: case__241
-case__802: case__802
-reg__484: reg__484
-logic__5333: logic__5333
-logic__5062: logic__5062
-reg__900: reg__900
-datapath__32: datapath__32
-case__546: case__546
-logic__8740: logic__8740
-HellaCacheArbiter: HellaCacheArbiter
-reg__1195: reg__1195
-reg__346: reg__346
-reg__357: reg__357
-logic__2674: logic__2674
-logic__6308: logic__6308
-logic__1350: logic__1350
-logic__878: logic__878
-reg__253: reg__253
-reg__312: reg__312
-logic__613: logic__613
-datapath__748: datapath__16
-case__757: case__757
-logic__7240: logic__7240
-dsp48e1__23: dsp48e1__23
-logic__2780: logic__2780
-case__614: case__614
-case__320: case__320
-case__274: case__274
-ram__1: ram__1
-case__997: case__997
-logic__4852: logic__4852
-TLBuffer_a32d64s2k1z4u_1: TLBuffer_a32d64s2k1z4u_1
-logic__4498: logic__4498
-reg__254: reg__254
-datapath__319: datapath__319
-logic__7548: logic__7548
-logic__9015: logic__3917
-reg__1342: reg__1342
-logic__6207: logic__6207
-case__1137: case__1137
-case__1465: case__1465
-logic__6564: logic__6564
-logic__2709: logic__2709
-reg__47: reg__47
-case__418: case__418
-case__360: case__360
-case__287: case__287
-logic__5405: logic__5405
-logic__5268: logic__5268
-case__1352: case__1352
-ClockGroupAggregator_cbus: ClockGroupAggregator_cbus
-logic__2082: logic__2082
-logic__740: logic__740
-reg__1045: reg__1045
-reg__43: reg__43
-reg__1261: reg__1261
-logic__1835: logic__1835
-reg__1004: reg__1004
-logic__2078: logic__2078
-logic__3205: logic__3205
-logic__2557: logic__2557
-logic__6779: logic__6779
-sync__7: sync
-logic__4272: logic__4272
-FPToInt: FPToInt
-datapath__436: datapath__436
-logic__1051: logic__1051
-ClockGroupAggregator_pbus__1: ClockGroupAggregator_pbus
-logic__2988: logic__2988
-logic__9009: logic__3929
-dsp48e1__2: dsp48e1__2
-logic__8785: logic__8785
-logic__8571: logic__8571
-case__275: case__275
-case__429: case__429
-reg__166: reg__166
-logic__5482: logic__5482
-logic__4148: logic__4148
-logic__2681: logic__2681
-datapath__565: datapath__565
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__11: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__111: case__111
-logic__3184: logic__3184
-reg__1166: reg__1166
-datapath__263: datapath__263
-logic__4260: logic__4260
-AsyncValidSync__20: AsyncValidSync
-logic__8916: logic__8916
-reg__556: reg__556
-logic__7865: logic__7865
-logic__5958: logic__5958
-logic__8152: logic__8152
-case__1333: case__1333
-logic__7388: logic__7388
-datapath__446: datapath__446
-logic__9146: logic__1685
-case__1415: case__1415
-logic__6579: logic__6579
-reg__1274: reg__1274
-logic__9066: logic__1917
-logic__5434: logic__5434
-logic__5905: logic__5905
-logic__6019: logic__6019
-reg__1147: reg__1147
-logic__345: logic__345
-logic__4684: logic__4684
-logic__4192: logic__4192
-counter__28: counter__28
-logic__313: logic__313
-logic__5690: logic__5690
-case__149: case__149
-case__73: case__73
-logic__4609: logic__4609
-reg__305: reg__305
-dsp48e1__16: dsp48e1__16
-logic__6785: logic__6785
-case__130: case__130
-reg__1066: reg__1066
-logic__8564: logic__8564
-reg__860: reg__860
-reg__829: reg__829
-reg__218: reg__218
-logic__4655: logic__4655
-case__627: case__627
-logic__3924: logic__3924
-logic__4879: logic__4879
-logic__4189: logic__4189
-logic__2670: logic__2670
-logic__4853: logic__4853
-reg__1504: reg__833
-logic__2829: logic__2829
-case__191: case__191
-logic__8048: logic__8048
-reg__15: reg__15
-case__961: case__961
-datapath__127: datapath__127
-logic__3487: logic__3487
-reg__1428: reg__834
-case__244: case__244
-case__220: case__220
-datapath__140: datapath__140
-reg__643: reg__643
-logic__6054: logic__6054
-case__558: case__558
-case__270: case__270
-logic__2815: logic__2815
-datapath__279: datapath__279
-datapath__69: datapath__69
-reg__1086: reg__1086
-logic__9105: logic__1819
-case__121: case__121
-datapath__536: datapath__536
-logic__1048: logic__1048
-logic__3531: logic__3531
-case__1573: case__306
-case__474: case__474
-reg__567: reg__567
-logic__1273: logic__1273
-logic__1040: logic__1040
-logic__2933: logic__2933
-datapath: datapath
-datapath__77: datapath__77
-case__1274: case__1274
-case__576: case__576
-logic__6153: logic__6153
-logic__458: logic__458
-case__652: case__652
-reg__735: reg__735
-datapath__369: datapath__369
-reg__480: reg__480
-logic__2336: logic__2336
-logic__3358: logic__3358
-datapath__352: datapath__352
-reg__3: reg__3
-ClockGroup: ClockGroup
-logic__3696: logic__3696
-datapath__616: datapath__616
-logic__5254: logic__5254
-logic__661: logic__661
-logic__618: logic__618
-case__1539: case__1539
-datapath__328: datapath__328
-logic__5689: logic__5689
-logic__6773: logic__6773
-datapath__416: datapath__416
-logic__8918: logic__8918
-reg__894: reg__894
-reg__1452: reg__834
-logic__1003: logic__1003
-reg__1394: reg__833
-logic__5058: logic__5058
-reg__618: reg__618
-keep__33: keep__7
-dsp48e1__35: dsp48e1__35
-logic__470: logic__470
-case__396: case__396
-case__935: case__935
-logic__6376: logic__6376
-TLFragmenter_bootrom: TLFragmenter_bootrom
-logic__7205: logic__7205
-logic__8882: logic__8882
-case__1572: case__307
-reg__553: reg__553
-logic__6539: logic__6539
-logic__2710: logic__2710
-datapath__289: datapath__289
-reg__488: reg__488
-logic__4716: logic__4716
-muxpart__96: muxpart__96
-logic__9064: logic__1934
-case__56: case__56
-reg__728: reg__728
-keep__32: keep__8
-reg__914: reg__914
-logic__2110: logic__2110
-reg__1226: reg__1226
-logic__4422: logic__4422
-logic__1193: logic__1193
-logic__2072: logic__2072
-logic__4276: logic__4276
-logic__6373: logic__6373
-datapath__638: datapath__638
-afe_top: afe_top
-reg__28: reg__28
-case__1359: case__1359
-datapath__455: datapath__455
-logic__2698: logic__2698
-logic__1950: logic__1950
-case__128: case__128
-reg__23: reg__23
-case__1123: case__1123
-logic__4737: logic__4737
-logic__5467: logic__5467
-logic__5854: logic__5854
-datapath__535: datapath__535
-logic__6187: logic__6187
-case__1365: case__1365
-logic__2907: logic__2907
-reg__273: reg__273
-logic__2875: logic__2875
-case__176: case__176
-case__945: case__945
-reg__1325: reg__1325
-logic__331: logic__331
-case__1099: case__1099
-logic__2655: logic__2655
-extrom__1: extrom__1
-logic__3990: logic__3990
-reg__1370: reg__1246
-logic__6471: logic__6471
-reg__1422: reg__834
-logic__1746: logic__1746
-logic__9076: logic__1890
-logic__5424: logic__5424
-logic__2351: logic__2351
-case__12: case__12
-extram: extram
-logic__6891: logic__6891
-logic__4244: logic__4244
-logic__6195: logic__6195
-logic__376: logic__376
-logic__8476: logic__8476
-datapath__656: datapath__656
-logic__4504: logic__4504
-case__814: case__814
-datapath__112: datapath__112
-case__1354: case__1354
-reg__1031: reg__1031
-logic__4266: logic__4266
-logic__2799: logic__2799
-logic__5695: logic__5695
-reg__620: reg__620
-logic__7651: logic__7651
-reg__794: reg__794
-logic__1373: logic__1373
-logic__4007: logic__4007
-logic__1227: logic__1227
-datapath__652: datapath__652
-case__979: case__979
-datapath__337: datapath__337
-logic__1862: logic__1862
-muxpart: muxpart
-logic__79: logic__79
-logic__6636: logic__6636
-reg__202: reg__202
-logic__2369: logic__2369
-case__1323: case__1323
-reg__523: reg__523
-logic__927: logic__927
-case__579: case__579
-logic__8812: logic__8812
-logic__6772: logic__6772
-case__123: case__123
-datapath__667: datapath__667
-case__338: case__338
-datapath__449: datapath__449
-case__481: case__481
-datapath__695: datapath__298
-logic__6303: logic__6303
-reg__726: reg__726
-logic__9138: logic__1707
-logic__6193: logic__6193
-datapath__10: datapath__10
-logic__650: logic__650
-logic__2196: logic__2196
-case__351: case__351
-case__1406: case__1406
-logic__1620: logic__1620
-logic__8673: logic__8673
-logic__3305: logic__3305
-datapath__389: datapath__389
-logic__3819: logic__3819
-case__18: case__18
-case__355: case__355
-logic__4404: logic__4404
-reg__1234: reg__1234
-logic__8722: logic__8722
-logic__2: logic__2
-logic__4849: logic__4849
-logic__4380: logic__4380
-case__179: case__179
-extrom__5: extrom
-logic__7184: logic__7184
-logic__8168: logic__8168
-logic__6464: logic__6464
-case__1408: case__1408
-logic__8045: logic__8045
-reg__617: reg__617
-reg__988: reg__988
-case__1232: case__1232
-datapath__545: datapath__545
-case__1162: case__1162
-reg__1304: reg__1304
-case__584: case__584
-logic__2409: logic__2409
-reg__581: reg__581
-logic__4000: logic__4000
-case__284: case__284
-Queue1_RegMapperInput_i9_m8: Queue1_RegMapperInput_i9_m8
-logic__8321: logic__8321
-case__210: case__210
-logic__704: logic__704
-muxpart__143: muxpart__143
-case__586: case__586
-reg__531: reg__531
-logic__6462: logic__6462
-reg__158: reg__158
-logic__8181: logic__8181
-logic__3661: logic__3661
-datapath__745: datapath__19
-case__157: case__157
-logic__9154: logic__1659
-logic__176: logic__176
-reg__295: reg__295
-logic__3371: logic__3371
-case__1290: case__1290
-logic__952: logic__952
-logic__1407: logic__1407
-datapath__71: datapath__71
-ram_2x124: ram_2x124
-logic__2669: logic__2669
-case__837: case__837
-logic__6180: logic__6180
-datapath__253: datapath__253
-reg__1279: reg__1279
-logic__2650: logic__2650
-reg__1105: reg__1105
-reg__401: reg__401
-logic__7900: logic__7900
-TLBusBypassBar: TLBusBypassBar
-case__1355: case__1355
-logic__6555: logic__6555
-reg__759: reg__759
-reg__898: reg__898
-case__1511: case__1511
-muxpart__77: muxpart__77
-reg__1305: reg__1305
-logic__451: logic__451
-logic__3703: logic__3703
-reg__536: reg__536
-case__1601: case__98
-reg__727: reg__727
-logic__31: logic__31
-logic__5484: logic__5484
-logic__7534: logic__7534
-datapath__516: datapath__516
-reg__1423: reg__833
-logic__967: logic__967
-logic__6857: logic__6857
-case__189: case__189
-datapath__113: datapath__113
-logic__8117: logic__8117
-case__947: case__947
-logic__4926: logic__4926
-muxpart__20: muxpart__20
-case__141: case__141
-reg__31: reg__31
-logic__7261: logic__7261
-reg__1209: reg__1209
-logic__7633: logic__7633
-case__213: case__213
-logic__5287: logic__5287
-case__203: case__203
-logic__7370: logic__7370
-logic__8878: logic__8878
-logic__4724: logic__4724
-reg__804: reg__804
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__1: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__134: case__134
-logic__1918: logic__1918
-logic__9210: logic__1525
-logic__8998: logic__2940
-reg__1162: reg__1162
-case__1220: case__1220
-case__467: case__467
-logic__4606: logic__4606
-logic__2970: logic__2970
-case__309: case__309
-logic__5053: logic__5053
-logic__8963: logic__8963
-logic__2173: logic__2173
-reg__157: reg__157
-case__1459: case__1459
-datapath__730: datapath__648
-logic__6388: logic__6388
-logic__5942: logic__5942
-case__125: case__125
-regfile_32x65: regfile_32x65
-logic__2951: logic__2951
-datapath__595: datapath__595
-logic__5381: logic__5381
-reg__172: reg__172
-logic__4136: logic__4136
-logic__9099: logic__1831
-logic__55: logic__55
-logic__1326: logic__1326
-reg__844: reg__844
-reg__110: reg__110
-reg__82: reg__82
-case__98: case__98
-logic__4049: logic__4049
-logic__6132: logic__6132
-case__137: case__137
-logic__8622: logic__8622
-logic__6011: logic__6011
-reg__286: reg__286
-logic__6791: logic__6791
-case__1225: case__1225
-datapath__255: datapath__255
-case__227: case__227
-reg__1264: reg__1264
-reg__1522: reg__63
-logic__3324: logic__3324
-keep__30: keep__7
-logic__968: logic__968
-muxpart__40: muxpart__40
-logic__2186: logic__2186
-logic__5456: logic__5456
-case__874: case__874
-case__1434: case__1434
-logic__8986: logic__2969
-logic__6271: logic__6271
-logic__6353: logic__6353
-logic__940: logic__940
-case__613: case__613
-logic__9155: logic__1654
-reg__521: reg__521
-logic__2000: logic__2000
-logic__9108: logic__1810
-keep__29: keep__8
-logic__2671: logic__2671
-logic__6400: logic__6400
-reg__836: reg__836
-logic__6486: logic__6486
-logic__6387: logic__6387
-logic__526: logic__526
-datapath__672: datapath__672
-logic__4390: logic__4390
-reg__706: reg__706
-case__1184: case__1184
-extram__2: extram__2
-reg__71: reg__71
-IntXbar_i3_o1: IntXbar_i3_o1
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__16: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6524: logic__6524
-keep__18: keep__7
-logic__4758: logic__4758
-case__167: case__167
-logic__6572: logic__6572
-datapath__429: datapath__429
-logic__9002: logic__3946
-logic__4224: logic__4224
-case__1593: case__1400
-logic__6467: logic__6467
-case__645: case__645
-logic__4552: logic__4552
-logic__4581: logic__4581
-logic__5634: logic__5634
-logic__566: logic__566
-logic__7576: logic__7576
-muxpart__82: muxpart__82
-logic__9221: logic__1506
-logic__6629: logic__6629
-logic__2373: logic__2373
-reg__1191: reg__1191
-logic__1522: logic__1522
-logic__4679: logic__4679
-logic__830: logic__830
-reg__530: reg__530
-case__485: case__485
-reg__762: reg__762
-Queue2_TLBundleA_a29d64s2k1z3u__1: Queue2_TLBundleA_a29d64s2k1z3u
-logic__1624: logic__1624
-reg__789: reg__789
-muxpart__41: muxpart__41
-logic__4766: logic__4766
-reg__989: reg__989
-logic__5646: logic__5646
-case__482: case__482
-case__943: case__943
-logic__8030: logic__8030
-logic__2925: logic__2925
-logic__7752: logic__7752
-reg__1021: reg__1021
-muxpart__27: muxpart__27
-logic__6802: logic__6802
-logic__7697: logic__7697
-reg__1265: reg__1265
-logic__51: logic__51
-rom__2: rom__2
-case__649: case__649
-logic__8741: logic__8741
-logic__8352: logic__8352
-logic__7590: logic__7590
-case__784: case__784
-logic__1314: logic__1314
-reg__1347: reg__1347
-logic__3202: logic__3202
-logic__1798: logic__1798
-reg__629: reg__629
-logic__6074: logic__6074
-logic__5068: logic__5068
-case__660: case__660
-logic__1984: logic__1984
-logic__3106: logic__3106
-logic__5286: logic__5286
-logic__2613: logic__2613
-reg__21: reg__21
-case__1218: case__1218
-reg__1402: reg__997
-logic__9307: logic__482
-reg__50: reg__50
-logic__552: logic__552
-reg__1313: reg__1313
-logic__8047: logic__8047
-reg__600: reg__600
-reg__562: reg__562
-case__937: case__937
-logic__835: logic__835
-case__1541: case__459
-logic__6784: logic__6784
-logic__8356: logic__8356
-reg__497: reg__497
-case__1545: case__454
-case__476: case__476
-logic__3053: logic__3053
-case__1453: case__1453
-logic__963: logic__963
-case__439: case__439
-datapath__39: datapath__39
-mult_46_15_61__1: mult_46_15_61
-reg__730: reg__730
-case__428: case__428
-logic__102: logic__102
-logic__2377: logic__2377
-case__146: case__146
-logic__8599: logic__8599
-case__581: case__581
-reg__638: reg__638
-muxpart__3: muxpart__3
-logic__9272: logic__6120
-logic__3551: logic__3551
-logic__4945: logic__4945
-logic__6137: logic__6137
-reg__363: reg__363
-datapath__291: datapath__291
-case__1038: case__1038
-datapath__175: datapath__175
-logic__5686: logic__5686
-reg__866: reg__866
-logic__324: logic__324
-datapath__283: datapath__283
-logic__8032: logic__8032
-logic__3728: logic__3728
-reg__1380: reg__998
-reg__330: reg__330
-reg__1399: reg__834
-logic__1559: logic__1559
-datapath__636: datapath__636
-logic__6109: logic__6109
-logic__1686: logic__1686
-logic__6042: logic__6042
-datapath__256: datapath__256
-logic__5219: logic__5219
-signinv: signinv
-datapath__15: datapath__15
-reg__1013: reg__1013
-case__10: case__10
-logic__123: logic__123
-datapath__685: datapath__685
-logic__446: logic__446
-logic__8682: logic__8682
-case__340: case__340
-datapath__419: datapath__419
-logic__3770: logic__3770
-logic__8883: logic__8883
-logic__4329: logic__4329
-logic__4714: logic__4714
-logic__6463: logic__6463
-reg__282: reg__282
-reg__570: reg__570
-logic__5420: logic__5420
-logic__3102: logic__3102
-logic__4005: logic__4005
-datapath__435: datapath__435
-datapath__643: datapath__643
-ram_2x99: ram_2x99
-logic__2121: logic__2121
-case__886: case__886
-logic__8978: logic__2984
-case__903: case__903
-logic__340: logic__340
-reg__997: reg__997
-case__1169: case__1169
-reg__889: reg__889
-case__659: case__659
-logic__8407: logic__8407
-case__952: case__952
-extram__1: extram__1
-logic__2686: logic__2686
-logic__5199: logic__5199
-datapath__624: datapath__624
-logic__8253: logic__8253
-datapath__606: datapath__606
-logic__4144: logic__4144
-reg__1300: reg__1300
-logic__1597: logic__1597
-datapath__676: datapath__676
-reg__1121: reg__1121
-reg__185: reg__185
-logic__4555: logic__4555
-case__367: case__367
-Queue1_RegMapperInput_i9_m8__1: Queue1_RegMapperInput_i9_m8
-case__166: case__166
-logic__2708: logic__2708
-logic__4332: logic__4332
-logic__3183: logic__3183
-case__736: case__736
-logic__2482: logic__2482
-reg__1083: reg__1083
-reg__809: reg__809
-case__1376: case__1376
-case__223: case__223
-reg__862: reg__862
-datapath__108: datapath__108
-logic__2921: logic__2921
-logic__6257: logic__6257
-logic__4897: logic__4897
-reg__832: reg__832
-reg__1424: reg__835
-reg__117: reg__117
-logic__1383: logic__1383
-logic__371: logic__371
-case__716: case__716
-logic__4199: logic__4199
-acq_wrapper: acq_wrapper
-logic__2635: logic__2635
-logic__955: logic__955
-logic__8567: logic__8567
-reg__400: reg__400
-logic__7172: logic__7172
-case__53: case__53
-reg__1446: reg__834
-case__193: case__193
-cdc_fifo_gray: cdc_fifo_gray
-logic__2370: logic__2370
-logic__4843: logic__4843
-case__174: case__174
-logic__8142: logic__8142
-reg__569: reg__569
-logic__4971: logic__4971
-logic__2361: logic__2361
-logic__1882: logic__1882
-logic__6736: logic__6736
-logic__7912: logic__7912
-logic__7780: logic__7780
-reg__559: reg__559
-case__665: case__665
-logic__66: logic__66
-reg__119: reg__119
-case__242: case__242
-logic__5334: logic__5334
-case__1374: case__1374
-datapath__144: datapath__144
-logic__4668: logic__4668
-TLFIFOFixer: TLFIFOFixer
-logic__1699: logic__1699
-logic__4727: logic__4727
-datapath__590: datapath__590
-logic__6031: logic__6031
-logic__72: logic__72
-logic__1325: logic__1325
-logic__6620: logic__6620
-case__117: case__117
-datapath__524: datapath__524
-logic__6445: logic__6445
-case__1519: case__1519
-muxpart__10: muxpart__10
-logic__4828: logic__4828
-reg__235: reg__235
-reg__651: reg__651
-case__661: case__661
-reg__787: reg__787
-datapath__229: datapath__229
-datapath__562: datapath__562
-gray_to_binary: gray_to_binary
-logic__4401: logic__4401
-logic__2491: logic__2491
-datapath__72: datapath__72
-logic__1441: logic__1441
-Queue2_TLBundleA_a14d64s2k1z4u: Queue2_TLBundleA_a14d64s2k1z4u
-logic__2687: logic__2687
-logic__5271: logic__5271
-case__607: case__607
-reg__1505: reg__783
-logic__703: logic__703
-datapath__619: datapath__619
-muxpart__227: muxpart__227
-IntSyncCrossingSource_n1x2: IntSyncCrossingSource_n1x2
-case__1426: case__1426
-datapath__170: datapath__170
-reg__890: reg__890
-case__786: case__786
-logic__7379: logic__7379
-logic__6448: logic__6448
-logic__2707: logic__2707
-logic__4445: logic__4445
-logic__2868: logic__2868
-logic__8784: logic__8784
-case__622: case__622
-datapath__29: datapath__29
-logic__7043: logic__7043
-case__867: case__867
-reg__849: reg__849
-case__402: case__402
-case__636: case__636
-case__1337: case__1337
-logic__7465: logic__7465
-datapath__115: datapath__115
-SBToTL: SBToTL
-logic__3250: logic__3250
-datapath__225: datapath__225
-logic__5056: logic__5056
-logic__5373: logic__5373
-datapath__500: datapath__500
-case__15: case__15
-logic__437: logic__437
-logic__7681: logic__7681
-datapath__404: datapath__404
-reg__212: reg__212
-datapath__66: datapath__66
-logic__956: logic__956
-reg__1494: reg__834
-reg__703: reg__703
-reg__1260: reg__1260
-case__257: case__257
-reg__659: reg__659
-reg__743: reg__743
-reg__242: reg__242
-logic__2031: logic__2031
-logic__6261: logic__6261
-logic__3812: logic__3812
-case__973: case__973
-logic__6618: logic__6618
-case__359: case__359
-case__448: case__448
-reg__294: reg__294
-reg__1393: reg__834
-logic__5966: logic__5966
-logic__554: logic__554
-logic__1047: logic__1047
-case__1470: case__1470
-logic__6354: logic__6354
-reg__784: reg__784
-case__1119: case__1119
-logic__2984: logic__2984
-case__49: case__49
-logic__1867: logic__1867
-logic__1251: logic__1251
-datapath__167: datapath__167
-reg__103: reg__103
-logic__7325: logic__7325
-logic__1935: logic__1935
-logic__6754: logic__6754
-logic__6923: logic__6923
-counter__15: counter__15
-muxpart__34: muxpart__34
-logic__8171: logic__8171
-logic__203: logic__203
-cordic_atan_basic__parameterized0: cordic_atan_basic__parameterized0
-logic__3608: logic__3608
-logic__7570: logic__7570
-case__113: case__113
-reg__1180: reg__1180
-reg__942: reg__942
-logic__6716: logic__6716
-logic__6018: logic__6018
-case__260: case__260
-logic__441: logic__441
-reg__888: reg__888
-case__380: case__380
-LF_code: LF_code
-logic__1238: logic__1238
-logic__3350: logic__3350
-logic__3753: logic__3753
-datapath__510: datapath__510
-case__388: case__388
-logic__6028: logic__6028
-case__971: case__971
-case__216: case__216
-logic__7932: logic__7932
-logic__3309: logic__3309
-logic__8700: logic__8700
-logic__4731: logic__4731
-logic__96: logic__96
-reg__232: reg__232
-logic__3062: logic__3062
-ram_2x78: ram_2x78
-logic__5491: logic__5491
-counter__27: counter__27
-LevelGateway__6: LevelGateway
-logic__461: logic__461
-case__1547: case__452
-case__1387: case__1387
-logic__3772: logic__3772
-logic__5374: logic__5374
-reg__999: reg__999
-reg__1203: reg__1203
-reg__824: reg__824
-reg__193: reg__193
-logic__258: logic__258
-case__364: case__364
-logic__3705: logic__3705
-reg__318: reg__318
-logic__3998: logic__3998
-logic__3504: logic__3504
-logic__2834: logic__2834
-reg__1208: reg__1208
-logic__8362: logic__8362
-logic__6518: logic__6518
-logic__5065: logic__5065
-logic__1641: logic__1641
-reg__1517: reg__68
-reg__757: reg__757
-logic__7461: logic__7461
-case__160: case__160
-muxpart__206: muxpart__206
-logic__3532: logic__3532
-reg__1353: reg__33
-reg__9: reg__9
-reg__622: reg__622
-reg__496: reg__496
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__12: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__65: reg__65
-datapath__493: datapath__493
-logic__6895: logic__6895
-logic__1734: logic__1734
-ram__10: ram__1
-reg__1150: reg__1150
-case__44: case__44
-reg__1502: reg__835
-reg__1207: reg__1207
-datapath__111: datapath__111
-logic__6166: logic__6166
-datapath__137: datapath__137
-logic__6917: logic__6917
-reg__1137: reg__1137
-logic__2133: logic__2133
-logic__6797: logic__6797
-reg__590: reg__590
-logic__2876: logic__2876
-rom__4: rom__4
-logic__7076: logic__7076
-logic__5255: logic__5255
-case__1400: case__1400
-reg__1202: reg__1202
-logic__6090: logic__6090
-AsyncResetRegVec_w2_i0: AsyncResetRegVec_w2_i0
-datapath__212: datapath__212
-reg__555: reg__555
-reg__1529: reg__32
-TLBuffer_a32d64s1k1z4u: TLBuffer_a32d64s1k1z4u
-logic__8687: logic__8687
-logic__3129: logic__3129
-reg__503: reg__503
-logic__8617: logic__8617
-reg__680: reg__680
-logic__4827: logic__4827
-logic__3691: logic__3691
-logic__3602: logic__3602
-logic__6281: logic__6281
-logic__951: logic__951
-logic__7554: logic__7554
-logic__1561: logic__1561
-case__1028: case__1028
-case__1086: case__1086
-reg__768: reg__768
-AsyncResetRegVec_w1_i0__1: AsyncResetRegVec_w1_i0
-reg__106: reg__106
-logic__8863: logic__8863
-logic__8920: logic__8920
-logic__2863: logic__2863
-logic__7550: logic__7550
-case__949: case__949
-logic__4342: logic__4342
-case__1040: case__1040
-logic__7025: logic__7025
-logic__6144: logic__6144
-datapath__234: datapath__234
-case__1158: case__1158
-AsyncResetSynchronizerShiftReg_w1_d3_i0__2: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__7408: logic__7408
-logic__7849: logic__7849
-case__1021: case__1021
-reg__1057: reg__1057
-datapath__148: datapath__148
-datapath__70: datapath__70
-reg__1375: reg__1141
-case__68: case__68
-case__674: case__674
-logic__393: logic__393
-logic__3508: logic__3508
-RocketALU: RocketALU
-logic__3911: logic__3911
-reg__840: reg__840
-reg__783: reg__783
-logic__488: logic__488
-logic__4933: logic__4933
-logic__1317: logic__1317
-logic__2457: logic__2457
-logic__6776: logic__6776
-case__1054: case__1054
-case__1392: case__1392
-reg__906: reg__906
-reg__1085: reg__1085
-logic__2597: logic__2597
-logic__3669: logic__3669
-case__582: case__582
-logic__135: logic__135
-reg__1516: reg__149
-reg__1311: reg__1311
-case__588: case__588
-case__1516: case__1516
-case__103: case__103
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__4: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__1508: case__1508
-logic__8811: logic__8811
-logic__4607: logic__4607
-logic__6248: logic__6248
-logic__1055: logic__1055
-PMAChecker: PMAChecker
-case__662: case__662
-case__778: case__778
-datapath__28: datapath__28
-logic__2636: logic__2636
-case__701: case__701
-case__599: case__599
-logic__2295: logic__2295
-case__1531: case__1531
-logic__2283: logic__2283
-logic__2866: logic__2866
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__23: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__188: case__188
-logic__5013: logic__5013
-logic__3239: logic__3239
-logic__1534: logic__1534
-DivSqrtRawFN_small: DivSqrtRawFN_small
-datapath__406: datapath__406
-logic__6777: logic__6777
-reg__647: reg__647
-TLAsyncCrossingSource_a9d32s1k1z2u: TLAsyncCrossingSource_a9d32s1k1z2u
-logic__6898: logic__6898
-logic__3699: logic__3699
-logic__1008: logic__1008
-logic__8014: logic__8014
-logic__6307: logic__6307
-logic__4400: logic__4400
-case__1480: case__1480
-logic__1452: logic__1452
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__5: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__344: datapath__344
-reg__1509: reg__783
-reg__1319: reg__1319
-dsp48e1__29: dsp48e1__29
-ram_2x77__4: ram_2x77
-logic__935: logic__935
-datapath__584: datapath__584
-case__1358: case__1358
-datapath__431: datapath__431
-logic__4825: logic__4825
-logic__9008: logic__3930
-logic__9212: logic__1523
-reg__856: reg__856
-logic__8779: logic__8779
-logic__9074: logic__1899
-logic__8922: logic__8922
-case__770: case__770
-reg__1453: reg__833
-datapath__484: datapath__484
-logic__8292: logic__8292
-reg__165: reg__165
-case__1215: case__1215
-logic__2906: logic__2906
-logic__1033: logic__1033
-INToRecFN_1: INToRecFN_1
-datapath__88: datapath__88
-logic__6060: logic__6060
-logic__517: logic__517
-counter: counter
-logic__1401: logic__1401
-reg__501: reg__501
-logic__8114: logic__8114
-logic__323: logic__323
-datapath__558: datapath__558
-case__375: case__375
-logic__6762: logic__6762
-logic__6671: logic__6671
-logic__6409: logic__6409
-logic__1506: logic__1506
-reg__180: reg__180
-datapath__640: datapath__640
-logic__2682: logic__2682
-logic__2781: logic__2781
-datapath__125: datapath__125
-datapath__737: datapath__137
-datapath__104: datapath__104
-reg__1493: reg__835
-case__641: case__641
-datapath__375: datapath__375
-logic__1: logic__1
-case__165: case__165
-logic__4282: logic__4282
-divider: divider
-logic__2623: logic__2623
-logic__8560: logic__8560
-keep__23: keep__8
-case__1417: case__1417
-logic__9211: logic__1524
-reg__1152: reg__1152
-logic__660: logic__660
-case__177: case__177
-datapath__274: datapath__274
-muxpart__47: muxpart__47
-logic__3866: logic__3866
-mult_66_66_66: mult_66_66_66
-logic__8974: logic__2994
-reg__1118: reg__1118
-logic__6792: logic__6792
-logic__6653: logic__6653
-logic__6580: logic__6580
-logic__2796: logic__2796
-muxpart__2: muxpart__2
-reg__864: reg__864
-logic__8371: logic__8371
-logic__1446: logic__1446
-logic__8754: logic__8754
-logic__688: logic__688
-logic__7565: logic__7565
-case__150: case__150
-logic__341: logic__341
-reg__1398: reg__835
-logic__7688: logic__7688
-logic__756: logic__756
-logic__5691: logic__5691
-logic__8816: logic__8816
-logic__7109: logic__7109
-logic__4903: logic__4903
-reg__191: reg__191
-muxpart__94: muxpart__94
-reg__208: reg__208
-logic__9298: logic__503
-logic__3843: logic__3843
-reg__527: reg__527
-logic__5685: logic__5685
-logic__1993: logic__1993
-logic__9134: logic__1725
-logic__7280: logic__7280
-case__1276: case__1276
-datapath__335: datapath__335
-reg__770: reg__770
-logic__9213: logic__1522
-logic__4444: logic__4444
-logic__6188: logic__6188
-logic__9222: logic__1505
-logic__771: logic__771
-logic__6125: logic__6125
-logic__3424: logic__3424
-reg__1129: reg__1129
-logic__7121: logic__7121
-logic__6150: logic__6150
-reg__1212: reg__1212
-case__218: case__218
-logic__5518: logic__5518
-logic__3771: logic__3771
-logic__5313: logic__5313
-datapath__700: datapath__357
-logic__3995: logic__3995
-logic__7626: logic__7626
-reg__389: reg__389
-logic__8421: logic__8421
-AsyncValidSync__6: AsyncValidSync
-logic__1977: logic__1977
-logic__1917: logic__1917
-case__583: case__583
-reg__704: reg__704
-reg__877: reg__877
-logic__1262: logic__1262
-reg__52: reg__52
-case__1407: case__1407
-logic__3273: logic__3273
-case__326: case__326
-logic__6922: logic__6922
-logic__1831: logic__1831
-reg__755: reg__755
-reg__607: reg__607
-logic__6503: logic__6503
-datapath__91: datapath__91
-logic__2865: logic__2865
-muxpart__232: muxpart__232
-sample_align: sample_align
-case__539: case__539
-logic__8979: logic__2983
-logic__4505: logic__4505
-logic__2130: logic__2130
-logic__2405: logic__2405
-logic__9262: logic__8234
-logic__9063: logic__1935
-muxpart__192: muxpart__192
-counter__7: counter__7
-logic__1841: logic__1841
-case__1550: case__528
-logic__5337: logic__5337
-case__965: case__965
-ClockSinkDomain: ClockSinkDomain
-logic__4320: logic__4320
-case__841: case__841
-logic__5524: logic__5524
-logic__7528: logic__7528
-datapath__228: datapath__228
-case__361: case__361
-case__414: case__414
-case__84: case__84
-logic__191: logic__191
-logic__5238: logic__5238
-TLError_1: TLError_1
-reg__1461: reg__834
-reg__1254: reg__1254
-case__912: case__912
-case__1051: case__1051
-logic__2168: logic__2168
-datapath__401: datapath__401
-logic__4018: logic__4018
-logic__7645: logic__7645
-logic__1021: logic__1021
-logic__6573: logic__6573
-reg__932: reg__932
-case__1017: case__1017
-logic__8551: logic__8551
-case__1267: case__1267
-logic__9135: logic__1722
-case__390: case__390
-reg__1491: reg__834
-logic__8572: logic__8572
-case__1293: case__1293
-logic__4896: logic__4896
-datapath__688: datapath__688
-logic__6014: logic__6014
-case__1035: case__1035
-logic__512: logic__512
-reg__621: reg__621
-reg__599: reg__599
-reg__1138: reg__1138
-case__934: case__934
-logic__1107: logic__1107
-reg__1168: reg__1168
-reg__396: reg__396
-logic__2392: logic__2392
-logic__6935: logic__6935
-logic__6786: logic__6786
-logic__1151: logic__1151
-case__988: case__988
-logic__1370: logic__1370
-logic__3700: logic__3700
-AsyncValidSync__7: AsyncValidSync
-logic__291: logic__291
-logic__1170: logic__1170
-case__200: case__200
-reg__1104: reg__1104
-logic__8378: logic__8378
-counter__9: counter__9
-logic__8441: logic__8441
-logic__4817: logic__4817
-reg__460: reg__460
-logic__5679: logic__5679
-logic__5283: logic__5283
-TLDebugModule: TLDebugModule
-logic__6426: logic__6426
-logic__2524: logic__2524
-case__468: case__468
-case__433: case__433
-logic__8130: logic__8130
-case__410: case__410
-logic__5487: logic__5487
-case__942: case__942
-reg__1338: reg__1338
-logic__8695: logic__8695
-logic__4778: logic__4778
-logic__5476: logic__5476
-logic__2347: logic__2347
-logic__8909: logic__8909
-reg__961: reg__961
-logic__3472: logic__3472
-logic__7298: logic__7298
-logic__8934: logic__8934
-case__349: case__349
-counter__13: counter__13
-logic__9248: logic__8433
-logic__4414: logic__4414
-logic__7223: logic__7223
-reg__532: reg__532
-logic__2904: logic__2904
-logic__9121: logic__1766
-logic__6818: logic__6818
-case__77: case__77
-case__1485: case__1485
-reg__115: reg__115
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__8: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__1402: logic__1402
-logic__3822: logic__3822
-logic__4210: logic__4210
-case__527: case__527
-logic__7133: logic__7133
-reg__865: reg__865
-reg__1287: reg__1287
-logic__6299: logic__6299
-logic__5437: logic__5437
-Arbiter3_LLWB: Arbiter3_LLWB
-reg__1239: reg__1239
-keep__22: keep__6
-logic__4468: logic__4468
-addsub__8: addsub__5
-logic__2081: logic__2081
-logic__6223: logic__6223
-case__183: case__183
-logic__3897: logic__3897
-logic__4172: logic__4172
-reg__851: reg__851
-case__1507: case__1507
-keep__12: keep__7
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__25: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__121: reg__121
-logic__6986: logic__6986
-logic__942: logic__942
-case__1483: case__1483
-logic__7389: logic__7389
-logic__5490: logic__5490
-case__419: case__419
-logic__6654: logic__6654
-reg__723: reg__723
-case__469: case__469
-logic__6800: logic__6800
-muxpart__73: muxpart__73
-counter__18: counter__18
-logic__3997: logic__3997
-logic__887: logic__887
-logic__7443: logic__7443
-ResetCatchAndSync_d3__2: ResetCatchAndSync_d3
-muxpart__85: muxpart__85
-logic__5274: logic__5274
-logic__7291: logic__7291
-reg__823: reg__823
-reg__863: reg__863
-reg__1232: reg__1232
-case__289: case__289
-logic__9242: logic__8448
-logic__7222: logic__7222
-logic__4145: logic__4145
-logic__5863: logic__5863
-logic__867: logic__867
-case__209: case__209
-logic__4080: logic__4080
-reg__1238: reg__1238
-reg__1113: reg__1113
-reg__662: reg__662
-PeripheryBus_pbus: PeripheryBus_pbus
-datapath__430: datapath__430
-reg__73: reg__73
-logic__6331: logic__6331
-reg__339: reg__339
-Queue2_TLBundleD_a32d64s2k1z4u__1: Queue2_TLBundleD_a32d64s2k1z4u
-logic__6545: logic__6545
-datapath__243: datapath__243
-reg__361: reg__361
-Queue2_TLBundleD_a32d64s2k1z4u: Queue2_TLBundleD_a32d64s2k1z4u
-datapath__708: datapath__243
-logic__1430: logic__1430
-reg__1267: reg__1267
-logic__3171: logic__3171
-reg__395: reg__395
-logic__1363: logic__1363
-logic__3494: logic__3494
-case__795: case__795
-reg__1404: reg__835
-logic__3969: logic__3969
-logic__6881: logic__6881
-logic__1394: logic__1394
-logic__9043: logic__1870
-logic__5664: logic__5664
-logic__1579: logic__1579
-datapath__538: datapath__538
-logic__5259: logic__5259
-logic__4729: logic__4729
-Queue2_TLBundleA_a32d64s1k1z4u__1: Queue2_TLBundleA_a32d64s1k1z4u
-logic__4545: logic__4545
-reg__72: reg__72
-reg__602: reg__602
-logic__8379: logic__8379
-reg__751: reg__751
-logic__6726: logic__6726
-logic__2233: logic__2233
-case__762: case__762
-datapath__485: datapath__485
-case__1133: case__1133
-datapath__506: datapath__506
-logic__667: logic__667
-reg__146: reg__146
-logic__9159: logic__1644
-case__573: case__573
-case__1126: case__1126
-logic__3823: logic__3823
-datapath__239: datapath__239
-reg__826: reg__826
-logic__587: logic__587
-logic__2969: logic__2969
-datapath__46: datapath__46
-logic__9040: logic__1873
-reg__443: reg__443
-reg__1515: reg__150
-case__294: case__294
-DivSqrtRecFN_small: DivSqrtRecFN_small
-logic__9317: logic__461
-case__153: case__153
-logic__9061: logic__1826
-logic__1762: logic__1762
-logic__4093: logic__4093
-logic__9285: logic__6125
-case__1503: case__1503
-logic__6574: logic__6574
-case__1289: case__1289
-logic__2608: logic__2608
-reg__924: reg__924
-reg__275: reg__275
-case__839: case__839
-case__225: case__225
-logic__9322: logic__263
-logic__2092: logic__2092
-logic__6631: logic__6631
-logic__3232: logic__3232
-LevelGateway__9: LevelGateway
-logic__5499: logic__5499
-logic__6724: logic__6724
-logic__6379: logic__6379
-logic__229: logic__229
-logic__6158: logic__6158
-Arbiter2_Valid_PTWReq: Arbiter2_Valid_PTWReq
-logic__3758: logic__3758
-logic__7274: logic__7274
-logic__2839: logic__2839
-case__566: case__566
-reg__838: reg__838
-logic__3913: logic__3913
-logic__4398: logic__4398
-reg__283: reg__283
-logic__2603: logic__2603
-logic__4733: logic__4733
-logic__6181: logic__6181
-logic__9316: logic__462
-Queue2_TLBundleD_a29d64s2k1z3u__1: Queue2_TLBundleD_a29d64s2k1z3u
-logic__9289: logic__952
-reg__388: reg__388
-logic__4140: logic__4140
-reg__952: reg__952
-logic__6396: logic__6396
-case__578: case__578
-logic__6781: logic__6781
-case__1061: case__1061
-logic__1022: logic__1022
-datapath__130: datapath__130
-logic__3271: logic__3271
-reg__1527: reg__58
-ClockGroupAggregator_aggregator: ClockGroupAggregator_aggregator
-datapath__414: datapath__414
-logic__8723: logic__8723
-logic__7145: logic__7145
-logic__2624: logic__2624
-datapath__486: datapath__486
-logic__245: logic__245
-logic__4572: logic__4572
-datapath__712: datapath__239
-logic__3057: logic__3057
-reg__476: reg__476
-logic__6349: logic__6349
-logic__2903: logic__2903
-twiddle_ram__1: twiddle_ram
-case__686: case__686
-datapath__694: datapath__299
-reg__666: reg__666
-reg__90: reg__90
-logic__141: logic__141
-logic__1662: logic__1662
-logic__224: logic__224
-logic__3668: logic__3668
-reg__1228: reg__1228
-case__1222: case__1222
-reg__1322: reg__1322
-logic__1500: logic__1500
-TLInterconnectCoupler_pbus_to_fpga_uart: TLInterconnectCoupler_pbus_to_fpga_uart
-case__336: case__336
-logic__6594: logic__6594
-logic__2784: logic__2784
-case__721: case__721
-logic__101: logic__101
-logic__9048: logic__1859
-case__1305: case__1305
-logic__4128: logic__4128
-logic__6169: logic__6169
-reg__30: reg__30
-logic__5033: logic__5033
-reg__1531: reg__30
-reg__189: reg__189
-logic__4112: logic__4112
-reg__85: reg__85
-muxpart__21: muxpart__21
-case__1592: case__1401
-logic__3836: logic__3836
-logic__6805: logic__6805
-case__126: case__126
-RecFNToIN_1: RecFNToIN_1
-AMOALU: AMOALU
-reg__351: reg__351
-case__30: case__30
-reg__1385: reg__996
-logic__1525: logic__1525
-logic__7673: logic__7673
-logic__4283: logic__4283
-reg__717: reg__717
-reg__1337: reg__1337
-reg__558: reg__558
-reg__884: reg__884
-reg__147: reg__147
-case__1570: case__309
-logic__1000: logic__1000
-case__1280: case__1280
-logic__3781: logic__3781
-muxpart__65: muxpart__65
-reg__626: reg__626
-logic__9024: logic__3905
-logic__3145: logic__3145
-dsp48e1__43: dsp48e1__43
-case__1430: case__1430
-case__426: case__426
-case__307: case__307
-datapath__386: datapath__386
-logic__836: logic__836
-case__537: case__537
-case__619: case__619
-logic__6720: logic__6720
-logic__6397: logic__6397
-reg__1317: reg__1317
-reg__627: reg__627
-logic__1086: logic__1086
-reg__1437: reg__834
-datapath__292: datapath__292
-logic__3767: logic__3767
-logic__6374: logic__6374
-logic__6504: logic__6504
-datapath__605: datapath__605
-reg__694: reg__694
-case__620: case__620
-case__1321: case__1321
-logic__553: logic__553
-case__314: case__314
-reg__261: reg__261
-case__969: case__969
-reg__79: reg__79
-reg__1037: reg__1037
-logic__6856: logic__6856
-case__112: case__112
-reg__424: reg__424
-reg__1435: reg__833
-TLFragmenter_1: TLFragmenter_1
-logic__479: logic__479
-logic__848: logic__848
-TLBuffer_a14d64s2k1z4u: TLBuffer_a14d64s2k1z4u
-muxpart__19: muxpart__19
-logic__6163: logic__6163
-keep__44: keep__1
-reg__458: reg__458
-counter__14: counter__14
-case__717: case__717
-reg__540: reg__540
-case__832: case__832
-TLFragmenter_PLIC: TLFragmenter_PLIC
-datapath__136: datapath__136
-logic__5909: logic__5909
-logic__4385: logic__4385
-logic__9266: logic__8873
-logic__3430: logic__3430
-logic__267: logic__267
-logic__9104: logic__1822
-reg__1269: reg__1269
-case__1558: case__519
-case__1297: case__1297
-case__1377: case__1377
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__21: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__5989: logic__5989
-datapath__87: datapath__87
-logic__6067: logic__6067
-logic__6980: logic__6980
-reg__1236: reg__1236
-logic__5312: logic__5312
-logic__9305: logic__484
-logic__3921: logic__3921
-logic__2426: logic__2426
-muxpart__230: muxpart__230
-logic__4141: logic__4141
-case__1581: case__1412
-logic__6256: logic__6256
-logic__632: logic__632
-reg__985: reg__985
-logic__2060: logic__2060
-logic__3375: logic__3375
-reg__1440: reg__834
-TLFragmenter_FPGAGPS: TLFragmenter_FPGAGPS
-case__1269: case__1269
-logic__6007: logic__6007
-case__238: case__238
-logic__8502: logic__8502
-case__282: case__282
-logic__9252: logic__8236
-reg__718: reg__718
-datapath__312: datapath__312
-case__510: case__510
-logic__4196: logic__4196
-reg__1151: reg__1151
-datapath__354: datapath__354
-datapath__692: datapath__301
-reg__229: reg__229
-logic__569: logic__569
-logic__2688: logic__2688
-logic__8552: logic__8552
-case__344: case__344
-case__625: case__625
-reg__839: reg__839
-reg__1316: reg__1316
-datapath__268: datapath__268
-reg__873: reg__873
-logic__4763: logic__4763
-reg__214: reg__214
-RoundAnyRawFNToRecFN_4__1: RoundAnyRawFNToRecFN_4
-logic__5208: logic__5208
-logic__7619: logic__7619
-AsyncQueueSource_DebugInternalBundle: AsyncQueueSource_DebugInternalBundle
-case__94: case__94
-comp_mult: comp_mult
-reg__693: reg__693
-logic__1381: logic__1381
-reg__640: reg__640
-LevelGateway__1: LevelGateway
-logic__2097: logic__2097
-counter__29: counter__22
-reg__1296: reg__1296
-logic__6646: logic__6646
-case__131: case__131
-logic__9050: logic__1853
-datapath__388: datapath__388
-logic__8331: logic__8331
-logic__1277: logic__1277
-logic__2057: logic__2057
-reg__633: reg__633
-reg__837: reg__837
-datapath__327: datapath__327
-reg__404: reg__404
-case__1510: case__1510
-logic__3667: logic__3667
-reg__1425: reg__834
-case__1538: case__1538
-logic__4759: logic__4759
-case__749: case__749
-logic__7375: logic__7375
-case__211: case__211
-logic__5210: logic__5210
-logic__334: logic__334
-logic__4812: logic__4812
-logic__4003: logic__4003
-logic__21: logic__21
-logic__7387: logic__7387
-logic__6185: logic__6185
-case__226: case__226
-logic__1044: logic__1044
-logic__9047: logic__1862
-reg__1172: reg__1172
-logic__7825: logic__7825
-logic__2054: logic__2054
-logic__330: logic__330
-datapath__97: datapath__97
-logic__4810: logic__4810
-datapath__220: datapath__220
-logic__7911: logic__7911
-logic__5485: logic__5485
-logic__7536: logic__7536
-case__852: case__852
-reg__542: reg__542
-reg__69: reg__69
-datapath__603: datapath__603
-reg__1024: reg__1024
-case__54: case__54
-case__43: case__43
-logic__9190: logic__1573
-case__403: case__403
-logic__1009: logic__1009
-logic__3435: logic__3435
-logic__1442: logic__1442
-case__1010: case__1010
-reg__1490: reg__835
-logic__2134: logic__2134
-logic__6283: logic__6283
-case__145: case__145
-logic__3946: logic__3946
-logic__3244: logic__3244
-case__1136: case__1136
-case__1527: case__1527
-logic__2465: logic__2465
-logic__2035: logic__2035
-muxpart__18: muxpart__18
-case__618: case__618
-logic__4692: logic__4692
-case__1233: case__1233
-reg__290: reg__290
-logic__8966: logic__3028
-case__132: case__132
-logic__5196: logic__5196
-reg__338: reg__338
-logic__1403: logic__1403
-reg__419: reg__419
-case__682: case__682
-logic__1140: logic__1140
-logic__4900: logic__4900
-logic__4718: logic__4718
-case__231: case__231
-logic__105: logic__105
-case__267: case__267
-logic__6566: logic__6566
-case__808: case__808
-logic__1125: logic__1125
-reg__411: reg__411
-logic__4898: logic__4898
-logic__5034: logic__5034
-reg__1213: reg__1213
-logic__2867: logic__2867
-logic__1288: logic__1288
-logic__6072: logic__6072
-logic__7063: logic__7063
-logic__9045: logic__1868
-logic__8778: logic__8778
-reg__737: reg__737
-logic__5328: logic__5328
-case__81: case__81
-logic__2294: logic__2294
-logic__5910: logic__5910
-datapath__54: datapath__54
-logic__5376: logic__5376
-logic__5635: logic__5635
-case__1016: case__1016
-case__1102: case__1102
-case__522: case__522
-logic__6647: logic__6647
-case__55: case__55
-logic__9037: logic__1886
-sync__1: sync
-reg__169: reg__169
-logic__85: logic__85
-logic__3966: logic__3966
-case__986: case__986
-case__93: case__93
-reg__320: reg__320
-reg__251: reg__251
-reg__561: reg__561
-logic__5937: logic__5937
-ram_2x120: ram_2x120
-logic__4042: logic__4042
-logic__6120: logic__6120
-logic__3557: logic__3557
-case__65: case__65
-case__1096: case__1096
-reg__772: reg__772
-logic__2036: logic__2036
-datapath__711: datapath__240
-reg__143: reg__143
-logic__1415: logic__1415
-logic__8967: logic__3025
-logic__4884: logic__4884
-reg__1486: reg__833
-logic__6510: logic__6510
-datapath__149: datapath__149
-logic__5410: logic__5410
-logic__9238: logic__644
-logic__4573: logic__4573
-extrom__4: extrom__1
-logic__8591: logic__8591
-logic__1956: logic__1956
-reg__850: reg__850
-reg__830: reg__830
-reg__123: reg__123
-logic__2141: logic__2141
-case__199: case__199
-logic__3442: logic__3442
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__1: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__501: case__501
-logic__8235: logic__8235
-logic__6075: logic__6075
-reg__186: reg__186
-reg__285: reg__285
-reg__1007: reg__1007
-datapath__653: datapath__653
-logic__8813: logic__8813
-reg__529: reg__529
-reg__1051: reg__1051
-logic__9133: logic__1726
-case__853: case__853
-logic__6258: logic__6258
-case__1324: case__1324
-logic__9090: logic__1856
-logic__779: logic__779
-case__91: case__91
-reg__1288: reg__1288
-case__831: case__831
-ifft_abs_sqr: ifft_abs_sqr
-case__358: case__358
-reg__975: reg__975
-IntSyncCrossingSource_n1x1: IntSyncCrossingSource_n1x1
-logic__3936: logic__3936
-logic__2928: logic__2928
-logic__4420: logic__4420
-reg__878: reg__878
-counter__17: counter__17
-logic__4159: logic__4159
-logic__5515: logic__5515
-datapath__340: datapath__340
-case__487: case__487
-logic__7255: logic__7255
-datapath__713: datapath__20
-sync__6: sync
-logic__1631: logic__1631
-case__280: case__280
-logic__999: logic__999
-reg__1071: reg__1071
-logic__8770: logic__8770
-reg__1134: reg__1134
-logic__4899: logic__4899
-logic__1637: logic__1637
-datapath__272: datapath__272
-logic__2640: logic__2640
-logic__3709: logic__3709
-reg__976: reg__976
-reg__379: reg__379
-case__675: case__675
-case__1026: case__1026
-logic__7256: logic__7256
-logic__6663: logic__6663
-case__172: case__172
-case__108: case__108
-reg__798: reg__798
-logic__7772: logic__7772
-logic__7024: logic__7024
-logic__3851: logic__3851
-reg__660: reg__660
-logic__5506: logic__5506
-case__791: case__791
-reg__1246: reg__1246
-datapath__31: datapath__31
-logic__9006: logic__3936
-Repeater_TLBundleA_a12d64s2k1z3u: Repeater_TLBundleA_a12d64s2k1z3u
-logic__3917: logic__3917
-logic__2987: logic__2987
-rom__6: rom__6
-logic__4878: logic__4878
-case__842: case__842
-logic__910: logic__910
-logic__6733: logic__6733
-logic__7030: logic__7030
-logic__9175: logic__1606
-case__792: case__792
-case__1326: case__1326
-logic__2451: logic__2451
-logic__6761: logic__6761
-reg__780: reg__780
-logic__9003: logic__3945
-logic__7292: logic__7292
-logic__6048: logic__6048
-reg__1510: reg__783
-logic__8981: logic__2977
-case__1306: case__1306
-logic__4153: logic__4153
-logic__6194: logic__6194
-datapath__467: datapath__467
-logic__9057: logic__1832
-logic__4587: logic__4587
-logic__1258: logic__1258
-case__1351: case__1351
-logic__5292: logic__5292
-logic__8988: logic__2967
-logic__6254: logic__6254
-case__1544: case__455
-logic__932: logic__932
-logic__591: logic__591
-logic__9165: logic__1630
-datapath__47: datapath__47
-logic__7525: logic__7525
-logic__6333: logic__6333
-counter__11: counter__11
-logic__6880: logic__6880
-reg__343: reg__343
-logic__469: logic__469
-reg__1459: reg__833
-logic__6192: logic__6192
-datapath__89: datapath__89
-reg__1289: reg__1289
-logic__4069: logic__4069
-logic__8766: logic__8766
-datapath__320: datapath__320
-logic__305: logic__305
-logic__3828: logic__3828
-logic__6804: logic__6804
-case__634: case__634
-case__637: case__637
-reg__925: reg__925
-logic__6191: logic__6191
-logic__6469: logic__6469
-logic__6477: logic__6477
-reg__1448: reg__835
-datapath__523: datapath__523
-reg__1159: reg__1159
-case__1029: case__1029
-reg__911: reg__911
-reg__1373: reg__1141
-case__254: case__254
-logic__2002: logic__2002
-reg__658: reg__658
-logic__5505: logic__5505
-case__1460: case__1460
-case__968: case__968
-logic__262: logic__262
-fft_radix_2__parameterized1: fft_radix_2__parameterized1
-case__278: case__278
-reg__219: reg__219
-datapath__238: datapath__238
-reg__858: reg__858
-reg__386: reg__386
-extram__9: extram__2
-PLICClockSinkDomain: PLICClockSinkDomain
-datapath__176: datapath__176
-reg__62: reg__62
-logic__2572: logic__2572
-reg__441: reg__441
-logic__8739: logic__8739
-logic__8941: logic__8941
-logic__916: logic__916
-logic__1491: logic__1491
-reg__1070: reg__1070
-logic__7680: logic__7680
-case__1008: case__1008
-logic__6570: logic__6570
-case__549: case__549
-logic__1228: logic__1228
-DivSqrtRecFNToRaw_small_1: DivSqrtRecFNToRaw_small_1
-case__826: case__826
-reg__113: reg__113
-case__495: case__495
-case__623: case__623
-reg__394: reg__394
-logic__3137: logic__3137
-case__272: case__272
-logic__1171: logic__1171
-datapath__553: datapath__553
-case__1484: case__1484
-keep__45: keep
-case__186: case__186
-datapath__412: datapath__412
-reg__1008: reg__1008
-reg__1501: reg__833
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__26: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__478: datapath__478
-reg__196: reg__196
-logic__987: logic__987
-logic__8956: logic__8956
-case__373: case__373
-logic__201: logic__201
-logic__3475: logic__3475
-logic__4672: logic__4672
-logic__1428: logic__1428
-logic__4481: logic__4481
-logic__4951: logic__4951
-case__92: case__92
-reg__465: reg__465
-logic__4028: logic__4028
-logic__8155: logic__8155
-logic__2013: logic__2013
-logic__7969: logic__7969
-logic__4920: logic__4920
-reg__711: reg__711
-case__984: case__984
-logic__8709: logic__8709
-case__1164: case__1164
-SynchronizerShiftReg_w1_d3: SynchronizerShiftReg_w1_d3
-logic__4901: logic__4901
-logic__775: logic__775
-logic__7490: logic__7490
-case__1211: case__1211
-reg__715: reg__715
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__14: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-AsyncValidSync__21: AsyncValidSync
-case__1534: case__1534
-logic__4355: logic__4355
-case__911: case__911
-datapath__132: datapath__132
-logic__1221: logic__1221
-datapath__475: datapath__475
-reg__855: reg__855
-datapath__343: datapath__343
-logic__2296: logic__2296
-logic__5395: logic__5395
-logic__5892: logic__5892
-AsyncValidSync__3: AsyncValidSync
-reg__1396: reg__834
-case__1476: case__1476
-logic__4374: logic__4374
-logic__3660: logic__3660
-Queue1_RegMapperInput_i23_m8: Queue1_RegMapperInput_i23_m8
-logic__8794: logic__8794
-reg__749: reg__749
-reg__1077: reg__1077
-logic__3769: logic__3769
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__3: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__7689: logic__7689
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__34: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__259: datapath__259
-logic__5009: logic__5009
-AsyncValidSync__4: AsyncValidSync
-case__899: case__899
-datapath__19: datapath__19
-logic__2680: logic__2680
-case__541: case__541
-logic__1687: logic__1687
-logic__4446: logic__4446
-logic__5150: logic__5150
-logic__2789: logic__2789
-case__48: case__48
-logic__2864: logic__2864
-logic__9072: logic__1901
-logic__4413: logic__4413
-logic__4837: logic__4837
-logic__6178: logic__6178
-TLBuffer_a29d64s2k1z3u: TLBuffer_a29d64s2k1z3u
-logic__1082: logic__1082
-datapath__260: datapath__260
-logic__990: logic__990
-reg__714: reg__714
-case__966: case__966
-logic__202: logic__202
-logic__4715: logic__4715
-reg__1073: reg__1073
-logic__8437: logic__8437
-logic__5047: logic__5047
-gray_to_binary__3: gray_to_binary
-logic__274: logic__274
-logic__4120: logic__4120
-logic__4859: logic__4859
-reg__1006: reg__1006
-RoundAnyRawFNToRecFN_1: RoundAnyRawFNToRecFN_1
-datapath__621: datapath__621
-datapath__26: datapath__26
-reg__603: reg__603
-case__1014: case__1014
-case__1129: case__1129
-case__1475: case__1475
-case__310: case__310
-logic__6164: logic__6164
-logic__2170: logic__2170
-double_ff_syn__1: double_ff_syn
-reg__1371: reg__1141
-datapath__356: datapath__356
-logic__5037: logic__5037
-reg__1468: reg__833
-reg__1014: reg__1014
-case__810: case__810
-case__52: case__52
-logic__1859: logic__1859
-case__556: case__556
-case__491: case__491
-case__1469: case__1469
-logic__6279: logic__6279
-case__253: case__253
-reg__663: reg__663
-logic__6417: logic__6417
-datapath__644: datapath__644
-case__59: case__59
-reg__944: reg__944
-spill_register_flushable: spill_register_flushable
-case__453: case__453
-case__475: case__475
-datapath__596: datapath__596
-logic__3748: logic__3748
-logic__9302: logic__497
-case__921: case__921
-logic__6810: logic__6810
-bootromClockSinkDomain: bootromClockSinkDomain
-logic__5853: logic__5853
-RoundAnyRawFNToRecFN_3: RoundAnyRawFNToRecFN_3
-logic__246: logic__246
-logic__2963: logic__2963
-logic__6435: logic__6435
-logic__4407: logic__4407
-logic__238: logic__238
-case__101: case__101
-case__509: case__509
-case__368: case__368
-logic__1097: logic__1097
-logic__3130: logic__3130
-logic__4866: logic__4866
-logic__6809: logic__6809
-logic__9182: logic__1591
-logic__1012: logic__1012
-datapath__139: datapath__139
-logic__5384: logic__5384
-logic__9282: logic__6120
-case__135: case__135
-logic__9314: logic__469
-reg__1392: reg__835
-case__547: case__547
-logic__6129: logic__6129
-case__412: case__412
-muxpart__88: muxpart__88
-logic__7781: logic__7781
-logic__2453: logic__2453
-reg__649: reg__649
-logic__5935: logic__5935
-logic__7178: logic__7178
-logic__4295: logic__4295
-logic__8242: logic__8242
-logic__5678: logic__5678
-logic__6596: logic__6596
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__20: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__1512: case__1512
-datapath__16: datapath__16
-logic__3825: logic__3825
-logic__6498: logic__6498
-logic__3925: logic__3925
-logic__3170: logic__3170
-case__561: case__561
-logic__337: logic__337
-logic__1872: logic__1872
-AsyncValidSync__8: AsyncValidSync
-reg__385: reg__385
-logic__8293: logic__8293
-logic__1804: logic__1804
-logic__8112: logic__8112
-logic__8654: logic__8654
-logic__2614: logic__2614
-rom__5: rom__5
-case__933: case__933
-counter__16: counter__16
-logic__5327: logic__5327
-logic__5203: logic__5203
-logic__2385: logic__2385
-logic__4941: logic__4941
-case__36: case__36
-reg__455: reg__455
-logic__3704: logic__3704
-logic__2856: logic__2856
-logic__4559: logic__4559
-logic__8113: logic__8113
-TLDebugModuleInnerAsync: TLDebugModuleInnerAsync
-datapath__245: datapath__245
-case__733: case__733
-reg__1017: reg__1017
-case__1584: case__1409
-logic__9263: logic__8240
-dsp48e1__8: dsp48e1__8
-logic__4137: logic__4137
-logic__3154: logic__3154
-case__780: case__780
-case__1046: case__1046
-reg__918: reg__918
-logic__9300: logic__501
-logic__4756: logic__4756
-logic__4696: logic__4696
-reg__946: reg__946
-logic__3264: logic__3264
-reg__321: reg__321
-case__1229: case__1229
-case__1172: case__1172
-case__452: case__452
-nav_solve_timer: nav_solve_timer
-logic__5948: logic__5948
-case__643: case__643
-reg__1335: reg__1335
-logic__4667: logic__4667
-case__1219: case__1219
-case__1458: case__1458
-reg__440: reg__440
-reg__733: reg__733
-logic__4032: logic__4032
-case__1332: case__1332
-logic__8555: logic__8555
-case__812: case__812
-sync__2: sync
-logic__8999: logic__3969
-logic__1059: logic__1059
-logic__8051: logic__8051
-reg__236: reg__236
-logic__5481: logic__5481
-logic__8505: logic__8505
-logic__6731: logic__6731
-case__1432: case__1432
-reg__35: reg__35
-logic__3655: logic__3655
-case__498: case__498
-logic__6949: logic__6949
-logic__138: logic__138
-muxpart__61: muxpart__61
-case__1389: case__1389
-reg__257: reg__257
-logic__5478: logic__5478
-reg__1348: reg__1348
-logic__6661: logic__6661
-case__151: case__151
-logic__160: logic__160
-case__1: case__1
-logic__6341: logic__6341
-logic__3707: logic__3707
-logic__4612: logic__4612
-logic__4785: logic__4785
-logic__5265: logic__5265
-case__384: case__384
-AsyncValidSync__18: AsyncValidSync
-case__822: case__822
-reg__1215: reg__1215
-ram_2x10: ram_2x10
-datapath__490: datapath__490
-case__57: case__57
-datapath__722: datapath__111
-logic__2402: logic__2402
-reg__790: reg__790
-datapath__505: datapath__505
-Repeater_TLBundleA_a28d64s2k1z3u: Repeater_TLBundleA_a28d64s2k1z3u
-logic__3109: logic__3109
-case__420: case__420
-TLFragmenter_FPGAUART__1: TLFragmenter_FPGAUART
-logic__6882: logic__6882
-logic__3706: logic__3706
-logic__1206: logic__1206
-case__163: case__163
-case__285: case__285
-logic__1719: logic__1719
-muxpart__90: muxpart__90
-TLFragmenter_Debug: TLFragmenter_Debug
-reg__1043: reg__1043
-logic__1429: logic__1429
-reg__913: reg__913
-logic__6991: logic__6991
-logic__5475: logic__5475
-case__957: case__957
-logic__4350: logic__4350
-case__1325: case__1325
-logic__4829: logic__4829
-logic__6757: logic__6757
-logic__8996: logic__2949
-reg__155: reg__155
-reg__987: reg__987
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__33: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6182: logic__6182
-logic__4953: logic__4953
-logic__699: logic__699
-case__29: case__29
-reg__1040: reg__1040
-logic__6879: logic__6879
-reg__698: reg__698
-logic__1541: logic__1541
-AsyncResetSynchronizerShiftReg_w1_d3_i0__7: AsyncResetSynchronizerShiftReg_w1_d3_i0
-case__1425: case__1425
-logic__4691: logic__4691
-logic__1063: logic__1063
-logic__4045: logic__4045
-TLBuffer_a32d64s2k1z3u: TLBuffer_a32d64s2k1z3u
-datapath__679: datapath__679
-reg__800: reg__800
-datapath__94: datapath__94
-datapath__462: datapath__462
-sync__8: sync
-logic__1416: logic__1416
-logic__5507: logic__5507
-logic__4099: logic__4099
-logic__5284: logic__5284
-reg__970: reg__970
-reg__1495: reg__833
-case__1328: case__1328
-muxpart__5: muxpart__5
-datapath__641: datapath__641
-logic__5377: logic__5377
-ram__9: ram__1
-logic__4861: logic__4861
-PMAChecker__2: PMAChecker
-Repeater_TLBundleA_a29d64s2k1z3u_2: Repeater_TLBundleA_a29d64s2k1z3u_2
-logic__6292: logic__6292
-TLXbar_pbus_out_i1_o3_a29d64s2k1z3u: TLXbar_pbus_out_i1_o3_a29d64s2k1z3u
-logic__2195: logic__2195
-muxpart__29: muxpart__29
-case__590: case__590
-logic__1269: logic__1269
-logic__4835: logic__4835
-logic__6189: logic__6189
-logic__3147: logic__3147
-logic__3552: logic__3552
-logic__318: logic__318
-logic__9229: logic__263
-case__508: case__508
-logic__4780: logic__4780
-logic__2967: logic__2967
-logic__8872: logic__8872
-reg__923: reg__923
-logic__8237: logic__8237
-Repeater_TLBundleD_a32d64s1k1z4u: Repeater_TLBundleD_a32d64s1k1z4u
-muxpart__80: muxpart__80
-logic__9169: logic__1620
-datapath__179: datapath__179
-counter__8: counter__8
-dsp48e1__40: dsp48e1__40
-logic__6587: logic__6587
-reg__760: reg__760
-logic__7677: logic__7677
-case__1125: case__1125
-logic__215: logic__215
-reg__398: reg__398
-TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u: TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u
-reg__1016: reg__1016
-case__774: case__774
-logic__619: logic__619
-reg__644: reg__644
-logic__4568: logic__4568
-logic__4776: logic__4776
-case__347: case__347
-logic__4923: logic__4923
-logic__9023: logic__3906
-TLXbar_pbus_in_i1_o1_a29d64s2k1z3u: TLXbar_pbus_in_i1_o1_a29d64s2k1z3u
-TLBuffer_a32d64s2k1z3u_1: TLBuffer_a32d64s2k1z3u_1
-case__315: case__315
-logic__1103: logic__1103
-reg__691: reg__691
-logic__1131: logic__1131
-logic__4452: logic__4452
-logic__9271: logic__6125
-logic__609: logic__609
-logic__494: logic__494
-logic__2438: logic__2438
-datapath__402: datapath__402
-logic__4100: logic__4100
-reg__969: reg__969
-reg__1247: reg__1247
-logic__5366: logic__5366
-logic__7120: logic__7120
-logic__6796: logic__6796
-logic__117: logic__117
-logic__3912: logic__3912
-logic__2609: logic__2609
-case__746: case__746
-logic__379: logic__379
-case__1586: case__1407
-logic__3469: logic__3469
-logic__8556: logic__8556
-logic__636: logic__636
-muxpart__70: muxpart__70
-case__1405: case__1405
-logic__7343: logic__7343
-logic__9171: logic__1614
-reg__990: reg__990
-PMPChecker_s3__1: PMPChecker_s3
-reg__712: reg__712
-logic__6537: logic__6537
-case__526: case__526
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__10: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__935: reg__935
-logic__1742: logic__1742
-logic__1578: logic__1578
-reg__687: reg__687
-logic__7493: logic__7493
-datapath__365: datapath__365
-logic__2088: logic__2088
-logic__8629: logic__8629
-case__805: case__805
-logic__8971: logic__3001
-datapath__657: datapath__657
-ram__8: ram__8
-reg__803: reg__803
-case__61: case__61
-case__105: case__105
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__2: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__9181: logic__1594
-logic__6985: logic__6985
-logic__6245: logic__6245
-logic__257: logic__257
-case__438: case__438
-logic__3800: logic__3800
-logic__2848: logic__2848
-reg__543: reg__543
-case__514: case__514
-case__738: case__738
-Queue2_TLBundleD_a32d64s1k1z4u: Queue2_TLBundleD_a32d64s1k1z4u
-logic__2504: logic__2504
-logic__8780: logic__8780
-reg__635: reg__635
-logic__8318: logic__8318
-datapath__342: datapath__342
-rocket_bscan_dmi_tunnel: rocket_bscan_dmi_tunnel
-case__399: case__399
-logic__5466: logic__5466
-reg__664: reg__664
-logic__6184: logic__6184
-logic__9267: logic__7551
-logic__4557: logic__4557
-reg__498: reg__498
-case__564: case__564
-reg__1326: reg__1326
-logic__6575: logic__6575
-case__1131: case__1131
-logic__8440: logic__8440
-datapath__418: datapath__418
-reg__872: reg__872
-case__422: case__422
-logic__3996: logic__3996
-logic__2934: logic__2934
-logic__7088: logic__7088
-logic__1017: logic__1017
-logic__2690: logic__2690
-muxpart__63: muxpart__63
-logic__5260: logic__5260
-rockettile_dcache_data_arrays_0_131072x64: rockettile_dcache_data_arrays_0_131072x64
-logic__2102: logic__2102
-logic__6598: logic__6598
-case__133: case__133
-logic__6383: logic__6383
-logic__4836: logic__4836
-logic__3434: logic__3434
-logic__1360: logic__1360
-case__76: case__76
-case__516: case__516
-reg__500: reg__500
-reg__352: reg__352
-reg__896: reg__896
-case__714: case__714
-reg__725: reg__725
-reg__1133: reg__1133
-logic__6304: logic__6304
-case__1117: case__1117
-logic__9228: logic__267
-logic__2788: logic__2788
-case__1053: case__1053
-case__339: case__339
-case__425: case__425
-datapath__736: datapath__138
-reg__1189: reg__1189
-datapath__702: datapath__249
-case__1367: case__1367
-datapath__474: datapath__474
-logic__476: logic__476
-logic__2226: logic__2226
-code_loop_discriminator: code_loop_discriminator
-reg__37: reg__37
-logic__6063: logic__6063
-logic__9250: logic__8429
-logic__3681: logic__3681
-logic__7058: logic__7058
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__28: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-extram__4: extram__4
-logic__4125: logic__4125
-case__140: case__140
-case__1397: case__1397
-datapath__25: datapath__25
-reg__1479: reg__834
-logic__6284: logic__6284
-case__80: case__80
-case__827: case__827
-logic__2475: logic__2475
-reg__200: reg__200
-case__1234: case__1234
-logic__2873: logic__2873
-logic__1702: logic__1702
-logic__6175: logic__6175
-datapath__689: datapath__689
-logic__1329: logic__1329
-case__818: case__818
-logic__3942: logic__3942
-reg__68: reg__68
-logic__8300: logic__8300
-logic__3530: logic__3530
-logic__426: logic__426
-ram_2x78__1: ram_2x78
-reg__1462: reg__833
-logic__686: logic__686
-ram__7: ram__7
-case__972: case__972
-reg__1249: reg__1249
-case__1098: case__1098
-logic__9203: logic__1542
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__6: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__6438: logic__6438
-TLInterconnectCoupler_fbus_from_debug_sb: TLInterconnectCoupler_fbus_from_debug_sb
-logic__4411: logic__4411
-logic__4597: logic__4597
-logic__2782: logic__2782
-logic__8384: logic__8384
-case__789: case__789
-addsub__9: addsub__4
-logic__3657: logic__3657
-logic__3908: logic__3908
-logic__9170: logic__1615
-logic__1232: logic__1232
-logic__5288: logic__5288
-datapath__508: datapath__508
-case__964: case__964
-logic__6066: logic__6066
-reg__368: reg__368
-logic__7685: logic__7685
-logic__7070: logic__7070
-case__669: case__669
-logic__156: logic__156
-logic__8046: logic__8046
-case__1056: case__1056
-reg__632: reg__632
-reg__1165: reg__1165
-logic__5988: logic__5988
-datapath__248: datapath__248
-reg__883: reg__883
-reg__1354: reg__32
-reg__187: reg__187
-reg__1229: reg__1229
-muxpart__72: muxpart__72
-logic__8369: logic__8369
-logic__1739: logic__1739
-case__281: case__281
-logic__6286: logic__6286
-case__233: case__233
-logic__7099: logic__7099
-logic__5508: logic__5508
-logic__5280: logic__5280
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__29: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__4561: logic__4561
-reg__428: reg__428
-logic__5911: logic__5911
-case__905: case__905
-logic__7919: logic__7919
-logic__1573: logic__1573
-logic__2140: logic__2140
-case__459: case__459
-datapath__498: datapath__498
-datapath__106: datapath__106
-reg__1310: reg__1310
-reg__74: reg__74
-logic__8958: logic__8958
-TLWidthWidget8_1: TLWidthWidget8_1
-logic__1552: logic__1552
-logic__9246: logic__8437
-reg__1248: reg__1248
-logic__6626: logic__6626
-logic__8994: logic__2951
-reg__272: reg__272
-reg__138: reg__138
-logic__8750: logic__8750
-logic__2355: logic__2355
-logic__3585: logic__3585
-logic__6298: logic__6298
-logic__2227: logic__2227
-case__271: case__271
-logic__317: logic__317
-logic__617: logic__617
-logic__8793: logic__8793
-case__250: case__250
-reg__939: reg__939
-logic__4290: logic__4290
-logic__6637: logic__6637
-logic__1335: logic__1335
-logic__2798: logic__2798
-reg__1377: reg__1141
-reg__478: reg__478
-logic__5882: logic__5882
-reg__1298: reg__1298
-logic__8280: logic__8280
-logic__696: logic__696
-logic__142: logic__142
-case__753: case__753
-datapath__296: datapath__296
-case__670: case__670
-logic__6734: logic__6734
-reg__805: reg__805
-logic__1147: logic__1147
-logic__4370: logic__4370
-logic__7037: logic__7037
-logic__1779: logic__1779
-logic__9022: logic__3907
-AsyncValidSync__23: AsyncValidSync
-reg__64: reg__64
-logic__1013: logic__1013
-datapath__488: datapath__488
-logic__2319: logic__2319
-logic__5979: logic__5979
-reg__1470: reg__834
-muxpart__223: muxpart__223
-case__881: case__881
-datapath__232: datapath__232
-logic__2080: logic__2080
-case__712: case__712
-logic__4811: logic__4811
-datapath__521: datapath__521
-logic__9184: logic__1587
-logic__1990: logic__1990
-logic__6538: logic__6538
-logic__4885: logic__4885
-reg__933: reg__933
-reg__625: reg__625
-datapath__751: datapath__13
-AsyncValidSync__15: AsyncValidSync
-TLInterconnectCoupler_cbus_to_clint: TLInterconnectCoupler_cbus_to_clint
-datapath__133: datapath__133
-logic__4122: logic__4122
-logic__6910: logic__6910
-logic__549: logic__549
-case__350: case__350
-case__1369: case__1369
-LevelGateway__2: LevelGateway
-logic__139: logic__139
-logic__674: logic__674
-muxpart__76: muxpart__76
-datapath__224: datapath__224
-logic__3051: logic__3051
-case__1504: case__1504
-datapath__330: datapath__330
-case__252: case__252
-logic__868: logic__868
-reg__776: reg__776
-logic__1606: logic__1606
-logic__5927: logic__5927
-logic__7391: logic__7391
-logic__7019: logic__7019
-reg__485: reg__485
-logic__9275: logic__6125
-logic__3827: logic__3827
-reg__853: reg__853
-extrom: extrom
-logic__14: logic__14
-logic__251: logic__251
-case__920: case__920
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__7: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__415: case__415
-logic__586: logic__586
-logic__4824: logic__4824
-reg__287: reg__287
-reg__182: reg__182
-case__143: case__143
-case__654: case__654
-AsyncResetSynchronizerShiftReg_w1_d3_i0__3: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__4934: logic__4934
-logic__7273: logic__7273
-case__74: case__74
-bram: bram
-reset_synch: reset_synch
-logic__3221: logic__3221
-logic__3046: logic__3046
-datapath__674: datapath__674
-TLBuffer_a32d64s1k1z4u__1: TLBuffer_a32d64s1k1z4u
-logic__2337: logic__2337
-logic__1135: logic__1135
-logic__7712: logic__7712
-logic__6035: logic__6035
-logic__975: logic__975
-case__1596: case__103
-logic__7853: logic__7853
-logic__7824: logic__7824
-case__667: case__667
-logic__6737: logic__6737
-case__913: case__913
-reg__915: reg__915
-logic__7721: logic__7721
-reg__1365: reg__1251
-logic__9160: logic__1641
-logic__2414: logic__2414
-datapath__602: datapath__602
-reg__936: reg__936
-datapath__154: datapath__154
-logic__3009: logic__3009
-datapath__236: datapath__236
-reg__1054: reg__1054
-logic__8726: logic__8726
-ram__6: ram__6
-logic__6391: logic__6391
-reg__1433: reg__835
-logic__7012: logic__7012
-logic__1278: logic__1278
-reg__1293: reg__1293
-logic__1155: logic__1155
-reg__7: reg__7
-reg__13: reg__13
-case__1059: case__1059
-datapath__368: datapath__368
-case__64: case__64
-muxpart__69: muxpart__69
-logic__2459: logic__2459
-double_ff_syn__4: double_ff_syn
-case__835: case__835
-reg__211: reg__211
-logic__4560: logic__4560
-case__530: case__530
-datapath__526: datapath__526
-logic__3330: logic__3330
-reg__439: reg__439
-logic__71: logic__71
-case__383: case__383
-logic__187: logic__187
-reg__674: reg__674
-logic__7614: logic__7614
-logic__3910: logic__3910
-reg__721: reg__721
-muxpart__83: muxpart__83
-logic__3567: logic__3567
-logic__1162: logic__1162
-logic__5967: logic__5967
-logic__3656: logic__3656
-case__915: case__915
-logic__3164: logic__3164
-logic__9041: logic__1872
-logic__8244: logic__8244
-logic__3701: logic__3701
-logic__2675: logic__2675
-case__489: case__489
-logic__3903: logic__3903
-reg__945: reg__945
-logic__581: logic__581
-logic__5457: logic__5457
-logic__2042: logic__2042
-logic__6979: logic__6979
-datapath__168: datapath__168
-logic__4935: logic__4935
-logic__1665: logic__1665
-logic__3482: logic__3482
-reg__949: reg__949
-logic__1100: logic__1100
-logic__9116: logic__1785
-logic__1420: logic__1420
-case__240: case__240
-logic__2779: logic__2779
-logic__4240: logic__4240
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__17: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__707: logic__707
-logic__6277: logic__6277
-logic__9291: logic__950
-case__1380: case__1380
-datapath__623: datapath__623
-cordic_atan_one_stage__parameterized0__1: cordic_atan_one_stage__parameterized0
-logic__8430: logic__8430
-logic__3206: logic__3206
-TLInterconnectCoupler_cbus_to_bootrom: TLInterconnectCoupler_cbus_to_bootrom
-logic__1886: logic__1886
-case__1043: case__1043
-logic__8897: logic__8897
-datapath__520: datapath__520
-case__838: case__838
-case__1379: case__1379
-logic__4086: logic__4086
-reg__270: reg__270
-datapath__734: datapath__644
-reg__610: reg__610
-logic__675: logic__675
-logic__2918: logic__2918
-logic__845: logic__845
-logic__5044: logic__5044
-logic__6159: logic__6159
-logic__4886: logic__4886
-logic__8980: logic__2980
-TLFpgaUART: TLFpgaUART
-logic__2581: logic__2581
-case__601: case__601
-logic__4717: logic__4717
-NCO_carr: NCO_carr
-logic__2393: logic__2393
-logic__8240: logic__8240
-logic__6025: logic__6025
-reg__474: reg__474
-case__1120: case__1120
-case__725: case__725
-reg__1528: reg__33
-case__1167: case__1167
-logic__6712: logic__6712
-datapath__80: datapath__80
-logic__5213: logic__5213
-logic__7114: logic__7114
-reg__955: reg__955
-logic__7365: logic__7365
-logic__1004: logic__1004
-case__719: case__719
-datapath__270: datapath__270
-logic__6668: logic__6668
-logic__7475: logic__7475
-logic__390: logic__390
-reg__445: reg__445
-logic__1456: logic__1456
-PMPChecker_s2: PMPChecker_s2
-case__1121: case__1121
-logic__4949: logic__4949
-reg__767: reg__767
-logic__6218: logic__6218
-case__1583: case__1410
-reg__1457: reg__835
-case__801: case__801
-reg__893: reg__893
-logic__8965: logic__8965
-reg__904: reg__904
-logic__3558: logic__3558
-logic__5696: logic__5696
-TilePRCIDomain__GC0: TilePRCIDomain__GC0
-counter__1: counter__1
-logic__4006: logic__4006
-reg__1164: reg__1164
-logic__2068: logic__2068
-reg__1284: reg__1284
-MulAddRecFNToRaw_preMul_1: MulAddRecFNToRaw_preMul_1
-logic__4887: logic__4887
-muxpart__49: muxpart__49
-NCO_code: NCO_code
-case__602: case__602
-logic__7707: logic__7707
-case__313: case__313
-logic__2692: logic__2692
-reg__298: reg__298
-reg__100: reg__100
-reg__209: reg__209
-muxpart__84: muxpart__84
-case__668: case__668
-case__993: case__993
-datapath__338: datapath__338
-logic__6588: logic__6588
-logic__9060: logic__1827
-twiddle_ram: twiddle_ram
-logic__8322: logic__8322
-case__872: case__872
-logic__2206: logic__2206
-logic__5341: logic__5341
-logic__5144: logic__5144
-reg__1321: reg__1321
-divider__parameterized0: divider__parameterized0
-logic__6709: logic__6709
-case__1134: case__1134
-reg__1217: reg__1217
-logic__6452: logic__6452
-reg__277: reg__277
-reg__887: reg__887
-reg__1076: reg__1076
-case__1128: case__1128
-reg__359: reg__359
-case__1580: case__1413
-reg__423: reg__423
-logic__2554: logic__2554
-logic__4519: logic__4519
-logic__168: logic__168
-logic__8216: logic__8216
-muxpart__60: muxpart__60
-case__884: case__884
-reg__190: reg__190
-logic__4281: logic__4281
-reg__1022: reg__1022
-logic__2458: logic__2458
-logic__4230: logic__4230
-datapath__582: datapath__582
-datapath__457: datapath__457
-logic__8919: logic__8919
-logic__9177: logic__1602
-datapath__348: datapath__348
-case__497: case__497
-logic__3863: logic__3863
-reg__83: reg__83
-logic__8305: logic__8305
-logic__646: logic__646
-case__269: case__269
-logic__575: logic__575
-case__1272: case__1272
-case__1030: case__1030
-reg__1251: reg__1251
-logic__539: logic__539
-reg__291: reg__291
-case__873: case__873
-reg__184: reg__184
-logic__4693: logic__4693
-logic__4553: logic__4553
-reg__1237: reg__1237
-MulAddRecFNPipe_l2_e11_s53: MulAddRecFNPipe_l2_e11_s53
-case__273: case__273
-datapath__546: datapath__546
-logic__3453: logic__3453
-logic__2142: logic__2142
-case__843: case__843
-logic__8568: logic__8568
-reg__1366: reg__1250
-logic__2836: logic__2836
-reg__506: reg__506
-logic__8818: logic__8818
-logic__1530: logic__1530
-logic__8969: logic__3005
-logic__327: logic__327
-logic__4823: logic__4823
-reg__670: reg__670
-datapath__357: datapath__357
-datapath__451: datapath__451
-logic__8755: logic__8755
-case__1366: case__1366
-reg__1204: reg__1204
-logic__6221: logic__6221
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__32: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6350: logic__6350
-datapath__107: datapath__107
-logic__8373: logic__8373
-logic__7159: logic__7159
-logic__3069: logic__3069
-logic__2567: logic__2567
-reg__1276: reg__1276
-logic__903: logic__903
-logic__109: logic__109
-logic__9264: logic__8873
-datapath__172: datapath__172
-logic__186: logic__186
-reg__8: reg__8
-logic__1132: logic__1132
-logic__4735: logic__4735
-logic__2678: logic__2678
-reg__1339: reg__1339
-case__431: case__431
-logic__2411: logic__2411
-case__992: case__992
-logic__8668: logic__8668
-logic__6705: logic__6705
-logic__2575: logic__2575
-datapath__9: datapath__9
-logic__9046: logic__1867
-logic__9270: logic__7548
-reg__1218: reg__1218
-muxpart__57: muxpart__57
-logic__7705: logic__7705
-logic__7171: logic__7171
-logic__8256: logic__8256
-logic__5291: logic__5291
-logic__311: logic__311
-logic__8442: logic__8442
-AsyncValidSync__16: AsyncValidSync
-reg__149: reg__149
-datapath__397: datapath__397
-reg__278: reg__278
-logic__1584: logic__1584
-FPUDecoder: FPUDecoder
-logic__8990: logic__2965
-case__1095: case__1095
-logic__5220: logic__5220
-logic__4820: logic__4820
-reg__700: reg__700
-reg__380: reg__380
-case__1025: case__1025
-logic__4630: logic__4630
-logic__8696: logic__8696
-logic__8987: logic__2968
-logic__3768: logic__3768
-logic__7544: logic__7544
-logic__5054: logic__5054
-reg__870: reg__870
-muxpart__6: muxpart__6
-case__409: case__409
-datapath__128: datapath__128
-reg__226: reg__226
-logic__5887: logic__5887
-case__230: case__230
-logic__6352: logic__6352
-reg__708: reg__708
-logic__687: logic__687
-logic__8401: logic__8401
-logic__4134: logic__4134
-case__1168: case__1168
-logic__6009: logic__6009
-logic__1139: logic__1139
-case__1404: case__1404
-dsp48e1__4: dsp48e1__4
-logic__349: logic__349
-logic__7648: logic__7648
-case__1330: case__1330
-reg__1219: reg__1219
-logic__3760: logic__3760
-datapath__86: datapath__86
-case__1556: case__521
-case__405: case__405
-reg__683: reg__683
-logic__8822: logic__8822
-logic__4070: logic__4070
-logic__3746: logic__3746
-case__20: case__20
-logic__1438: logic__1438
-logic__47: logic__47
-AsyncValidSync__14: AsyncValidSync
-reg__1119: reg__1119
-reg__1171: reg__1171
-case__1599: case__100
-reg__957: reg__957
-case__109: case__109
-logic__4132: logic__4132
-datapath__325: datapath__325
-case__406: case__406
-logic__6082: logic__6082
-reg__1291: reg__1291
-case__1300: case__1300
-case__996: case__996
-logic__7189: logic__7189
-reg__534: reg__534
-logic__212: logic__212
-case__864: case__864
-logic__4084: logic__4084
-logic__1014: logic__1014
-ResetCatchAndSync_d3: ResetCatchAndSync_d3
-logic__5667: logic__5667
-logic__5021: logic__5021
-logic__7666: logic__7666
-logic__6889: logic__6889
-logic__5029: logic__5029
-reg__341: reg__341
-muxpart__44: muxpart__44
-counter__24: counter__24
-datapath__432: datapath__432
-logic__5867: logic__5867
-case__898: case__898
-logic__6745: logic__6745
-reg__174: reg__174
-logic__6638: logic__6638
-logic__4813: logic__4813
-logic__4633: logic__4633
-case__14: case__14
-case__720: case__720
-logic__1951: logic__1951
-case__276: case__276
-case__628: case__628
-logic__2266: logic__2266
-logic__8757: logic__8757
-reg__269: reg__269
-logic__1357: logic__1357
-logic__8289: logic__8289
-logic__4950: logic__4950
-case__985: case__985
-logic__6597: logic__6597
-logic__6411: logic__6411
-case__1270: case__1270
-logic__7579: logic__7579
-case__1368: case__1368
-logic__4133: logic__4133
-logic__880: logic__880
-case__894: case__894
-datapath__581: datapath__581
-reg__1177: reg__1177
-logic__5057: logic__5057
-logic__3074: logic__3074
-reg__349: reg__349
-logic__936: logic__936
-reg__950: reg__950
-datapath__129: datapath__129
-datapath__741: datapath__96
-case__640: case__640
-datapath__304: datapath__304
-logic__8492: logic__8492
-logic__6526: logic__6526
-reg__1255: reg__1255
-logic__6096: logic__6096
-logic__1613: logic__1613
-logic__2048: logic__2048
-logic__8959: logic__8959
-reg__752: reg__752
-case__237: case__237
-reg__176: reg__176
-case__46: case__46
-logic__2446: logic__2446
-case__1410: case__1410
-reg__1060: reg__1060
-datapath__421: datapath__421
-case__702: case__702
-logic__4065: logic__4065
-logic__9162: logic__1637
-datapath__68: datapath__68
-datapath__372: datapath__372
-logic__287: logic__287
-case__1216: case__1216
-logic__4736: logic__4736
-counter__19: counter__19
-reg__679: reg__679
-reg__41: reg__41
-datapath__123: datapath__123
-logic__6214: logic__6214
-logic__6170: logic__6170
-logic__9318: logic__458
-logic__5198: logic__5198
-case__1044: case__1044
-reg__1352: reg__778
-reg__387: reg__387
-datapath__548: datapath__548
-TLInterconnectCoupler_pbus_to_fpga_uart__1: TLInterconnectCoupler_pbus_to_fpga_uart
-case__447: case__447
-datapath__276: datapath__276
-logic__6073: logic__6073
-logic__8653: logic__8653
-reg__1420: reg__833
-datapath__331: datapath__331
-case__496: case__496
-reg__392: reg__392
-reg__1466: reg__835
-logic__778: logic__778
-datapath__591: datapath__591
-reg__201: reg__201
-logic__242: logic__242
-datapath__556: datapath__556
-logic__620: logic__620
-case__106: case__106
-datapath__265: datapath__265
-reg__1463: reg__835
-logic__3818: logic__3818
-logic__7441: logic__7441
-logic__2943: logic__2943
-case__301: case__301
-logic__4970: logic__4970
-reg__1090: reg__1090
-case__67: case__67
-case__1006: case__1006
-logic__8035: logic__8035
-logic__2880: logic__2880
-logic__5429: logic__5429
-logic__4425: logic__4425
-reg__661: reg__661
-logic__5972: logic__5972
-logic__7411: logic__7411
-logic__9247: logic__8436
-case__926: case__926
-case__78: case__78
-logic__4127: logic__4127
-logic__9011: logic__3925
-logic__3390: logic__3390
-logic__3688: logic__3688
-logic__3478: logic__3478
-reg__624: reg__624
-case__1454: case__1454
-logic__3708: logic__3708
-logic__4868: logic__4868
-ITLB: ITLB
-keep__17: keep__8
-logic__1707: logic__1707
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__22: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__1363: reg__1253
-reg__463: reg__463
-logic__8880: logic__8880
-reg__705: reg__705
-reg__391: reg__391
-datapath__494: datapath__494
-reg__371: reg__371
-reg__716: reg__716
-logic__421: logic__421
-logic__249: logic__249
-datapath__298: datapath__298
-case__374: case__374
-RoundRawFNToRecFN_1: RoundRawFNToRecFN_1
-logic__2853: logic__2853
-logic__6759: logic__6759
-case__248: case__248
-datapath__138: datapath__138
-logic__9173: logic__1612
-reg__179: reg__179
-logic__4745: logic__4745
-reg__56: reg__56
-case__616: case__616
-logic__7132: logic__7132
-case__38: case__38
-case__33: case__33
-reg__1149: reg__1149
-case__1546: case__453
-logic__4185: logic__4185
-datapath__366: datapath__366
-logic__6012: logic__6012
-logic__1294: logic__1294
-case__1526: case__1526
-datapath__557: datapath__557
-datapath__461: datapath__461
-datapath__637: datapath__637
-logic__9244: logic__8441
-case__385: case__385
-case__1598: case__101
-logic__8234: logic__8234
-case__1214: case__1214
-logic__1104: logic__1104
-logic__276: logic__276
-logic__7956: logic__7956
-AsyncValidSync__19: AsyncValidSync
-logic__2114: logic__2114
-logic__3247: logic__3247
-muxpart__48: muxpart__48
-logic__9321: logic__267
-datapath__554: datapath__554
-case__1472: case__1472
-logic__1543: logic__1543
-reg__615: reg__615
-reg__406: reg__406
-logic__7381: logic__7381
-case__929: case__929
-logic__5289: logic__5289
-logic__3001: logic__3001
-logic__8924: logic__8924
-case__1390: case__1390
-reg__1003: reg__1003
-reg__444: reg__444
-logic__5403: logic__5403
-logic__6179: logic__6179
-logic__4507: logic__4507
-logic__6339: logic__6339
-datapath__266: datapath__266
-logic__2832: logic__2832
-case__400: case__400
-logic__9004: logic__3942
-datapath__359: datapath__359
-datapath__407: datapath__407
-logic__8382: logic__8382
-reg__402: reg__402
-logic__610: logic__610
-reg__1346: reg__1346
-MulAddRecFNPipe_l2_e8_s24: MulAddRecFNPipe_l2_e8_s24
-logic__2783: logic__2783
-logic__1646: logic__1646
-case__708: case__708
-logic__197: logic__197
-datapath__8: datapath__8
-reg__1023: reg__1023
-reg__432: reg__432
-logic__2913: logic__2913
-logic__1515: logic__1515
-AsyncResetSynchronizerShiftReg_w1_d3_i0__5: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__6817: logic__6817
-logic__4078: logic__4078
-logic__8436: logic__8436
-reg__1408: reg__971
-reg__152: reg__152
-keep__24: keep__7
-logic__557: logic__557
-reg__677: reg__677
-logic__7435: logic__7435
-logic__7126: logic__7126
-logic__2995: logic__2995
-case__1444: case__1444
-reg__750: reg__750
-reg__686: reg__686
-reg__771: reg__771
-datapath__514: datapath__514
-reg__246: reg__246
-logic__1790: logic__1790
-datapath__341: datapath__341
-datapath__84: datapath__84
-logic__5627: logic__5627
-logic__4289: logic__4289
-logic__6911: logic__6911
-datapath__346: datapath__346
-logic__3149: logic__3149
-logic__600: logic__600
-logic__4586: logic__4586
-logic__3743: logic__3743
-datapath__51: datapath__51
-case__1271: case__1271
-keep__15: keep__7
-case__1001: case__1001
-logic__9058: logic__1831
-logic__9225: logic__1500
-logic__1955: logic__1955
-reg__1132: reg__1132
-case__393: case__393
-logic__7618: logic__7618
-logic__3187: logic__3187
-case__251: case__251
-logic__1828: logic__1828
-logic__4135: logic__4135
-reg__1109: reg__1109
-logic__7377: logic__7377
-logic__5448: logic__5448
-case__936: case__936
-logic__6275: logic__6275
-case__1411: case__1411
-case__528: case__528
-datapath__522: datapath__522
-logic__6287: logic__6287
-reg__692: reg__692
-reg__93: reg__93
-logic__1457: logic__1457
-logic__5340: logic__5340
-case__1473: case__1473
-logic__6344: logic__6344
-logic__8167: logic__8167
-case__1428: case__1428
-reg__25: reg__25
-case__1286: case__1286
-case__790: case__790
-datapath__81: datapath__81
-logic__882: logic__882
-reg__1367: reg__1249
-logic__1726: logic__1726
-logic__1018: logic__1018
-dsp48e1__34: dsp48e1__34
-case__1551: case__527
-logic__1334: logic__1334
-logic__3930: logic__3930
-logic__4877: logic__4877
-logic__8939: logic__8939
-logic__6093: logic__6093
-datapath__82: datapath__82
-logic__2045: logic__2045
-logic__2912: logic__2912
-case__755: case__755
-logic__5330: logic__5330
-case__382: case__382
-case__1440: case__1440
-case__164: case__164
-logic__9304: logic__488
-logic__4480: logic__4480
-sync__5: sync
-case__1474: case__1474
-reg__875: reg__875
-logic__2306: logic__2306
-logic__9150: logic__1667
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__22: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__1012: case__1012
-logic__799: logic__799
-reg__859: reg__859
-logic__1973: logic__1973
-dsp48e1__44: dsp48e1__44
-muxpart__33: muxpart__33
-logic__645: logic__645
-IntXbar_i1_o1: IntXbar_i1_o1
-logic__7634: logic__7634
-logic__8781: logic__8781
-datapath__326: datapath__326
-logic__1952: logic__1952
-cordic_atan_basic: cordic_atan_basic
-reg__1210: reg__1210
-logic__7860: logic__7860
-datapath__655: datapath__655
-case__207: case__207
-case__1087: case__1087
-datapath__34: datapath__34
-reg__475: reg__475
-logic__2536: logic__2536
-reg__1214: reg__1214
-OptimizationBarrier_TLBEntryData__1: OptimizationBarrier_TLBEntryData
-case__1303: case__1303
-logic__1175: logic__1175
-logic__865: logic__865
-datapath__460: datapath__460
-logic__4362: logic__4362
-case__187: case__187
-case__1569: case__310
-logic__5647: logic__5647
-logic__3381: logic__3381
-fft_radix_2: fft_radix_2
-logic__6811: logic__6811
-reg__1067: reg__1067
-reg__1263: reg__1263
-datapath__4: datapath__4
-logic__8136: logic__8136
-datapath__361: datapath__361
-reg__978: reg__978
-case__888: case__888
-case__116: case__116
-reg__1381: reg__997
-logic__5392: logic__5392
-logic__6176: logic__6176
-logic__8039: logic__8039
-case__697: case__697
-case__258: case__258
-case__1533: case__1533
-reg__1277: reg__1277
-logic__6955: logic__6955
-case__617: case__617
-datapath__394: datapath__394
-reg__141: reg__141
-reg__1439: reg__835
-case__642: case__642
-logic__6434: logic__6434
-datapath__223: datapath__223
-datapath__141: datapath__141
-logic__2598: logic__2598
-datapath__543: datapath__543
-logic__8498: logic__8498
-case__398: case__398
-case__1443: case__1443
-logic__5428: logic__5428
-reg__564: reg__564
-logic__1081: logic__1081
-logic__4129: logic__4129
-reg__494: reg__494
-reg__799: reg__799
-case__1525: case__1525
-case__1471: case__1471
-logic__2654: logic__2654
-logic__1623: logic__1623
-logic__2022: logic__2022
-datapath__164: datapath__164
-logic__8402: logic__8402
-logic__3857: logic__3857
-logic__7535: logic__7535
-logic__8975: logic__2989
-logic__7655: logic__7655
-reg__1184: reg__1184
-reg__427: reg__427
-logic__6300: logic__6300
-logic__1533: logic__1533
-logic__2808: logic__2808
-logic__1807: logic__1807
-logic__543: logic__543
-case__322: case__322
-case__748: case__748
-logic__9084: logic__1870
-logic__4104: logic__4104
-logic__3858: logic__3858
-reg__524: reg__524
-reg__669: reg__669
-logic__8398: logic__8398
-logic__3826: logic__3826
-logic__9000: logic__3966
-datapath__564: datapath__564
-datapath__559: datapath__559
-OptimizationBarrier_TLBEntryData: OptimizationBarrier_TLBEntryData
-case__958: case__958
-logic__9299: logic__502
-logic__8925: logic__8925
-logic__9151: logic__1666
-case__458: case__458
-reg__393: reg__393
-reg__175: reg__175
-datapath__555: datapath__555
-case__1409: case__1409
-reg__993: reg__993
-reg__871: reg__871
-logic__533: logic__533
-addsub__2: addsub__2
-reg__785: reg__785
-reg__486: reg__486
-AsyncQueueSink_TLBundleA_a9d32s1k1z2u: AsyncQueueSink_TLBundleA_a9d32s1k1z2u
-reg__1451: reg__835
-reg__1526: reg__59
-logic__4204: logic__4204
-logic__6282: logic__6282
-logic__146: logic__146
-reg__335: reg__335
-logic__5380: logic__5380
-case__83: case__83
-datapath__727: datapath__651
-case__1574: case__305
-logic__9071: logic__1904
-reg__563: reg__563
-case__1429: case__1429
-ram__4: ram__4
-case__107: case__107
-logic__8036: logic__8036
-logic__1972: logic__1972
-logic__6006: logic__6006
-case__605: case__605
-logic__8874: logic__8874
-datapath__664: datapath__664
-IntSyncSyncCrossingSink_n1x1: IntSyncSyncCrossingSink_n1x1
-reg__701: reg__701
-reg__748: reg__748
-addsub__7: addsub__6
-logic__5297: logic__5297
-case__1089: case__1089
-case__690: case__690
-logic__1307: logic__1307
-logic__8972: logic__2998
-logic__2470: logic__2470
-reg__690: reg__690
-datapath__242: datapath__242
-logic__5906: logic__5906
-case__688: case__688
-reg__249: reg__249
-reg__477: reg__477
-logic__7031: logic__7031
-logic__6973: logic__6973
-logic__681: logic__681
-logic__745: logic__745
-logic__9220: logic__1507
-reg__1340: reg__1340
-case__580: case__580
-logic__4351: logic__4351
-datapath__529: datapath__529
-logic__4558: logic__4558
-case__1536: case__1536
-logic__2825: logic__2825
-reg__1281: reg__1281
-reg__1478: reg__835
-addsub__6: addsub__6
-logic__5411: logic__5411
-reg__1334: reg__1334
-logic__5902: logic__5902
-logic__2930: logic__2930
-logic__8881: logic__8881
-logic__290: logic__290
-case__783: case__783
-reg__260: reg__260
-reg__675: reg__675
-logic__869: logic__869
-logic__5973: logic__5973
-case__896: case__896
-logic__905: logic__905
-datapath__101: datapath__101
-reg__702: reg__702
-logic__1075: logic__1075
-logic__4515: logic__4515
-datapath__391: datapath__391
-reg__548: reg__548
-logic__9280: logic__6120
-logic__3025: logic__3025
-logic__3736: logic__3736
-logic__1359: logic__1359
-logic__3068: logic__3068
-datapath__182: datapath__182
-datapath__610: datapath__610
-datapath__512: datapath__512
-reg__1436: reg__835
-AsyncResetSynchronizerShiftReg_w1_d3_i0__10: AsyncResetSynchronizerShiftReg_w1_d3_i0
-reg__861: reg__861
-muxpart__45: muxpart__45
-case__892: case__892
-reg__70: reg__70
-logic__572: logic__572
-reg__613: reg__613
-reg__194: reg__194
-case__483: case__483
-datapath__620: datapath__620
-muxpart__79: muxpart__79
-reg__99: reg__99
-datapath__282: datapath__282
-case__1391: case__1391
-case__1173: case__1173
-datapath__660: datapath__660
-case__1156: case__1156
-logic__2329: logic__2329
-datapath__509: datapath__509
-logic__374: logic__374
-case__731: case__731
-case__47: case__47
-logic__761: logic__761
-logic__5995: logic__5995
-logic__1524: logic__1524
-logic__4622: logic__4622
-datapath__445: datapath__445
-case__256: case__256
-logic__243: logic__243
-case__565: case__565
-logic__8921: logic__8921
-logic__988: logic__988
-logic__4486: logic__4486
-Repeater_TLBundleA_a29d32s2k1z3u: Repeater_TLBundleA_a29d32s2k1z3u
-logic__9261: logic__8235
-logic__7246: logic__7246
-logic__4588: logic__4588
-counter__5: counter__5
-reg__1309: reg__1309
-logic__3216: logic__3216
-RecFNToIN: RecFNToIN
-logic__5176: logic__5176
-datapath__171: datapath__171
-logic__8283: logic__8283
-datapath__583: datapath__583
-logic__4008: logic__4008
-logic__3503: logic__3503
-datapath__615: datapath__615
-logic__2095: logic__2095
-counter__21: counter__21
-muxpart__226: muxpart__226
-logic__7006: logic__7006
-logic__5389: logic__5389
-logic__9136: logic__1719
-case__799: case__799
-logic__3414: logic__3414
-logic__3564: logic__3564
-logic__9249: logic__8430
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__31: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__465: datapath__465
-logic__8801: logic__8801
-reg__791: reg__791
-logic__9172: logic__1613
-reg__1158: reg__1158
-logic__3360: logic__3360
-case__1384: case__1384
-reg__76: reg__76
-datapath__566: datapath__566
-reg__628: reg__628
-case__917: case__917
-logic__5943: logic__5943
-logic__6439: logic__6439
-TLBusBypass: TLBusBypass
-logic__1214: logic__1214
-logic__5342: logic__5342
-logic__8727: logic__8727
-case__129: case__129
-reg__462: reg__462
-reg__1286: reg__1286
-case__304: case__304
-AsyncValidSync__10: AsyncValidSync
-logic__6744: logic__6744
-FixedClockBroadcast_4: FixedClockBroadcast_4
-case__1479: case__1479
-logic__6015: logic__6015
-datapath__214: datapath__214
-datapath__100: datapath__100
-logic__9035: logic__1890
-case__1577: case__1416
-logic__1270: logic__1270
-logic__3856: logic__3856
-logic__1971: logic__1971
-reg__265: reg__265
-rom__8: rom__8
-reg__1421: reg__835
-logic__6803: logic__6803
-reg__153: reg__153
-logic__7836: logic__7836
-case__1224: case__1224
-reg__315: reg__315
-logic__8304: logic__8304
-logic__5391: logic__5391
-datapath__126: datapath__126
-datapath__459: datapath__459
-logic__5701: logic__5701
-logic__9288: logic__6120
-logic__4019: logic__4019
-case__366: case__366
-reg__550: reg__550
-logic__1276: logic__1276
-logic__9018: logic__3911
-AsyncResetSynchronizerShiftReg_w1_d3_i0__11: AsyncResetSynchronizerShiftReg_w1_d3_i0
-TLROM: TLROM
-logic__5069: logic__5069
-logic__2588: logic__2588
-logic__4321: logic__4321
-reg__816: reg__816
-case__1562: case__317
-reg__519: reg__519
-case__648: case__648
-PMPChecker_s3: PMPChecker_s3
-logic__9216: logic__1515
-reg__598: reg__598
-reg__262: reg__262
-case__763: case__763
-reg__908: reg__908
-case__1388: case__1388
-datapath__699: datapath__358
-logic__2685: logic__2685
-reg__247: reg__247
-logic__8315: logic__8315
-reg__1197: reg__1197
-logic__7567: logic__7567
-logic__9149: logic__1674
-logic__277: logic__277
-logic__292: logic__292
-AsyncResetSynchronizerShiftReg_w1_d3_i0__6: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__6606: logic__6606
-logic__6367: logic__6367
-logic__7785: logic__7785
-muxpart__31: muxpart__31
-logic__3336: logic__3336
-logic__6269: logic__6269
-datapath__135: datapath__135
-logic__3742: logic__3742
-datapath__540: datapath__540
-reg__1431: reg__834
-logic__2091: logic__2091
-logic__6552: logic__6552
-case__1457: case__1457
-case__1033: case__1033
-datapath__587: datapath__587
-logic__2777: logic__2777
-logic__876: logic__876
-logic__1191: logic__1191
-reg__1153: reg__1153
-MulAddRecFNToRaw_postMul: MulAddRecFNToRaw_postMul
-case__962: case__962
-reg__1221: reg__1221
-logic__90: logic__90
-logic__3750: logic__3750
-logic__6904: logic__6904
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__10: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__1144: reg__1144
-logic__6862: logic__6862
-logic__8236: logic__8236
-reg__1026: reg__1026
-case__595: case__595
-TLXbar_dmixbar_i1_o2_a9d32s1k1z2u: TLXbar_dmixbar_i1_o2_a9d32s1k1z2u
-case__463: case__463
-logic__6395: logic__6395
-logic__9277: logic__6125
-logic__1542: logic__1542
-reg__793: reg__793
-logic__4632: logic__4632
-case__365: case__365
-logic__1987: logic__1987
-logic__6219: logic__6219
-reg__1256: reg__1256
-logic__6710: logic__6710
-logic__9042: logic__1871
-logic__2167: logic__2167
-reg__689: reg__689
-logic__1188: logic__1188
-logic__5326: logic__5326
-datapath__332: datapath__332
-logic__6635: logic__6635
-logic__6404: logic__6404
-FrontBus: FrontBus
-case__1600: case__99
-reg__446: reg__446
-logic__4138: logic__4138
-reg__188: reg__188
-case__914: case__914
-datapath__116: datapath__116
-logic__9056: logic__1835
-reg__582: reg__582
-logic__3747: logic__3747
-logic__5048: logic__5048
-reg__869: reg__869
-logic__7794: logic__7794
-logic__4059: logic__4059
-logic__9166: logic__1627
-datapath__48: datapath__48
-datapath__184: datapath__184
-reg__744: reg__744
-case__673: case__673
-logic__5304: logic__5304
-datapath__334: datapath__334
-logic__9202: logic__1543
-logic__1551: logic__1551
-logic__9065: logic__1918
-logic__4841: logic__4841
-logic__2962: logic__2962
-reg__220: reg__220
-datapath__124: datapath__124
-datapath__345: datapath__345
-reg__1314: reg__1314
-datapath__271: datapath__271
-reg__897: reg__897
-datapath__527: datapath__527
-reg__812: reg__812
-logic__5197: logic__5197
-logic__9129: logic__1742
-logic__7337: logic__7337
-case__236: case__236
-logic__8989: logic__2966
-datapath__300: datapath__300
-datapath__732: datapath__646
-logic__1242: logic__1242
-datapath__278: datapath__278
-reg__17: reg__17
-logic__5404: logic__5404
-logic__6528: logic__6528
-logic__5324: logic__5324
-case__60: case__60
-logic__6208: logic__6208
-reg__1101: reg__1101
-reg__1196: reg__1196
-datapath__499: datapath__499
-logic__2540: logic__2540
-reg__1235: reg__1235
-logic__6229: logic__6229
-logic__1257: logic__1257
-logic__2039: logic__2039
-logic__4908: logic__4908
-logic__2812: logic__2812
-logic__3272: logic__3272
-logic__3875: logic__3875
-reg__299: reg__299
-case__983: case__983
-keep__39: keep
-logic__7108: logic__7108
-logic__2833: logic__2833
-reg__267: reg__267
-logic__8247: logic__8247
-muxpart__225: muxpart__225
-muxpart__208: muxpart__208
-logic__2994: logic__2994
-logic__9028: logic__3884
-datapath__533: datapath__533
-logic__6377: logic__6377
-logic__2966: logic__2966
-datapath__269: datapath__269
-logic__1198: logic__1198
-TLFIFOFixer_1: TLFIFOFixer_1
-logic__4064: logic__4064
-case__343: case__343
-case__651: case__651
-logic__5492: logic__5492
-logic__6134: logic__6134
-case__1604: case__95
-logic__8877: logic__8877
-reg__1034: reg__1034
-logic__2471: logic__2471
-datapath__183: datapath__183
-logic__1706: logic__1706
-datapath__594: datapath__594
-logic__2935: logic__2935
-logic__4039: logic__4039
-case__1401: case__1401
-logic__430: logic__430
-logic__639: logic__639
-logic__6161: logic__6161
-datapath__370: datapath__370
-logic__2949: logic__2949
-case__794: case__794
-logic__422: logic__422
-logic__8867: logic__8867
-case__1482: case__1482
-reg__1349: reg__1349
-logic__1318: logic__1318
-logic__9179: logic__1596
-logic__2857: logic__2857
-case__1557: case__520
-logic__4790: logic__4790
-datapath__18: datapath__18
-logic__4839: logic__4839
-reg__365: reg__365
-logic__383: logic__383
-logic__2096: logic__2096
-datapath__293: datapath__293
-reg__130: reg__130
-case__816: case__816
-logic__2364: logic__2364
-logic__8518: logic__8518
-logic__2187: logic__2187
-case__70: case__70
-logic__4840: logic__4840
-case__502: case__502
-case__9: case__9
-logic__6961: logic__6961
-logic__7654: logic__7654
-case__750: case__750
-reg__504: reg__504
-logic__4288: logic__4288
-logic__3111: logic__3111
-reg__1445: reg__835
-logic__8395: logic__8395
-logic__6795: logic__6795
-reg__417: reg__417
-logic__8713: logic__8713
-logic__1338: logic__1338
-reg__1497: reg__834
-logic__6622: logic__6622
-logic__6405: logic__6405
-datapath__121: datapath__121
-counter__12: counter__12
-datapath__360: datapath__360
-reg__1039: reg__1039
-logic__1435: logic__1435
-logic__802: logic__802
-case__413: case__413
-logic__8459: logic__8459
-datapath__424: datapath__424
-logic__1146: logic__1146
-logic__9245: logic__8440
-logic__4904: logic__4904
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__21: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-muxpart__56: muxpart__56
-logic__9142: logic__1699
-logic__2236: logic__2236
-reg__1280: reg__1280
-logic__7094: logic__7094
-case__1015: case__1015
-reg__2: reg__2
-reg__217: reg__217
-logic__8514: logic__8514
-case__594: case__594
-logic__2916: logic__2916
-logic__3213: logic__3213
-logic__3662: logic__3662
-case__124: case__124
-logic__3229: logic__3229
-dsp48e1__46: dsp48e1__46
-logic__985: logic__985
-cordic_atan_one_stage__parameterized0: cordic_atan_one_stage__parameterized0
-logic__926: logic__926
-reg__1117: reg__1117
-logic__5483: logic__5483
-ShiftQueue: ShiftQueue
-logic__6790: logic__6790
-logic__9014: logic__3918
-reg__207: reg__207
-logic__4250: logic__4250
-reg__574: reg__574
-logic__2649: logic__2649
-logic__6380: logic__6380
-logic__9077: logic__1889
-case__173: case__173
-logic__4031: logic__4031
-TLXbar_cbus_out_i1_o7_a32d64s2k1z4u: TLXbar_cbus_out_i1_o7_a32d64s2k1z4u
-reg__979: reg__979
-reg__173: reg__173
-logic__649: logic__649
-datapath__531: datapath__531
-logic__8372: logic__8372
-case__1041: case__1041
-reg__412: reg__412
-case__1091: case__1091
-reg__903: reg__903
-datapath__131: datapath__131
-logic__1005: logic__1005
-logic__2679: logic__2679
-logic__7629: logic__7629
-case__919: case__919
-reg__1185: reg__1185
-reg__707: reg__707
-reg__609: reg__609
-reg__802: reg__802
-case__484: case__484
-case__318: case__318
-logic__7036: logic__7036
-case__868: case__868
-case__1318: case__1318
-datapath__611: datapath__611
-muxpart__8: muxpart__8
-case__1603: case__96
-reg__450: reg__450
-reg__434: reg__434
-reg__868: reg__868
-case__1395: case__1395
-case__288: case__288
-logic__5992: logic__5992
-logic__4391: logic__4391
-logic__534: logic__534
-case__214: case__214
-logic__1869: logic__1869
-case__544: case__544
-logic__3387: logic__3387
-logic__3759: logic__3759
-datapath__411: datapath__411
-reg__682: reg__682
-logic__3672: logic__3672
-logic__1747: logic__1747
-logic__3737: logic__3737
-reg__953: reg__953
-case__928: case__928
-logic__1220: logic__1220
-datapath__626: datapath__626
-TLInterconnectCoupler_cbus_to_plic: TLInterconnectCoupler_cbus_to_plic
-PeripheryBus_cbus: PeripheryBus_cbus
-case__1362: case__1362
-muxpart__103: muxpart__103
-reg__509: reg__509
-logic__1145: logic__1145
-logic__8935: logic__8935
-logic__9231: logic__656
-logic__1774: logic__1774
-logic__119: logic__119
-case__632: case__632
-logic__9078: logic__1886
-datapath__353: datapath__353
-logic__143: logic__143
-logic__8161: logic__8161
-logic__4063: logic__4063
-muxpart__50: muxpart__50
-case__633: case__633
-logic__1023: logic__1023
-reg__722: reg__722
-case__869: case__869
-logic__227: logic__227
-logic__3935: logic__3935
-datapath__21: datapath__21
-logic__3047: logic__3047
-logic__2940: logic__2940
-logic__497: logic__497
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__14: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__6366: logic__6366
-datapath__483: datapath__483
-logic__5040: logic__5040
-logic__1083: logic__1083
-logic__8414: logic__8414
-logic__2312: logic__2312
-reg__1174: reg__1174
-logic__5332: logic__5332
-logic__432: logic__432
-logic__442: logic__442
-case__277: case__277
-case__325: case__325
-reg__471: reg__471
-reg__696: reg__696
-logic__4494: logic__4494
-case__608: case__608
-reg__841: reg__841
-logic__5043: logic__5043
-logic__807: logic__807
-logic__9143: logic__1694
-logic__3132: logic__3132
-reg__94: reg__94
-reg__55: reg__55
-logic__7600: logic__7600
-reg__416: reg__416
-datapath__52: datapath__52
-case: case
-reg__1469: reg__835
-TLFragmenter_CLINT: TLFragmenter_CLINT
-logic__3108: logic__3108
-datapath__362: datapath__362
-case__389: case__389
-datapath__625: datapath__625
-logic__6962: logic__6962
-logic__6807: logic__6807
-logic__6567: logic__6567
-logic__2300: logic__2300
-logic__3939: logic__3939
-dual_port_ram: dual_port_ram
-case__442: case__442
-case__744: case__744
-logic__7584: logic__7584
-datapath__230: datapath__230
-reg__1391: reg__996
-reg__1186: reg__1186
-logic__8796: logic__8796
-logic__1085: logic__1085
-case__1588: case__1405
-logic__1207: logic__1207
-reg__867: reg__867
-datapath__468: datapath__468
-ram__14: ram__1
-logic__3534: logic__3534
-logic__2174: logic__2174
-logic__397: logic__397
-logic__9109: logic__1807
-logic__7442: logic__7442
-case__978: case__978
-reg__1156: reg__1156
-logic__737: logic__737
-reg__360: reg__360
-logic__4393: logic__4393
-logic__6992: logic__6992
-reg__1005: reg__1005
-case__536: case__536
-reg__426: reg__426
-logic__6523: logic__6523
-logic__6148: logic__6148
-reg__78: reg__78
-ram__5: ram__5
-reg__720: reg__720
-VCU118RocketSystem__GC0: VCU118RocketSystem__GC0
-reg__302: reg__302
-reg__38: reg__38
-logic__308: logic__308
-datapath__573: datapath__573
-reg__1290: reg__1290
-logic__3063: logic__3063
-case__342: case__342
-logic__9112: logic__1798
-logic__5256: logic__5256
-logic__5277: logic__5277
-logic__5362: logic__5362
-reg__1519: reg__66
-logic__6541: logic__6541
-reg__998: reg__998
-reg__1283: reg__1283
-logic__9137: logic__1714
-logic__2926: logic__2926
-logic__8657: logic__8657
-logic__1358: logic__1358
-logic__857: logic__857
-datapath__651: datapath__651
-reg__105: reg__105
-logic__8299: logic__8299
-PLICFanIn: PLICFanIn
-datapath__160: datapath__160
-reg__756: reg__756
-logic__5368: logic__5368
-case__464: case__464
-logic__4225: logic__4225
-muxpart__26: muxpart__26
-logic__8712: logic__8712
-logic__4592: logic__4592
-dsp48e1__25: dsp48e1__25
-logic__5261: logic__5261
-datapath__408: datapath__408
-logic__5309: logic__5309
-logic__372: logic__372
-logic__3110: logic__3110
-logic__6487: logic__6487
-logic__6226: logic__6226
-logic__3929: logic__3929
-logic__4392: logic__4392
-reg__292: reg__292
-reg__1094: reg__1094
-logic__7708: logic__7708
-logic__2824: logic__2824
-case__1163: case__1163
-reg__344: reg__344
-logic__6001: logic__6001
-logic__6650: logic__6650
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-dsp48e1__21: dsp48e1__21
-logic__3233: logic__3233
-logic__7672: logic__7672
-reg__1485: reg__834
-reg__453: reg__453
-logic__6760: logic__6760
-case__104: case__104
-logic__5914: logic__5914
-logic__8021: logic__8021
-case__185: case__185
-logic__8493: logic__8493
-logic__8504: logic__8504
-case__184: case__184
-logic__5498: logic__5498
-logic__4293: logic__4293
-reg__1163: reg__1163
-logic__6209: logic__6209
-logic__3391: logic__3391
-datapath__213: datapath__213
-logic__8392: logic__8392
-logic__6669: logic__6669
-logic__2590: logic__2590
-reg__937: reg__937
-logic__9096: logic__1838
-NonSyncResetSynchronizerPrimitiveShiftReg_d3: NonSyncResetSynchronizerPrimitiveShiftReg_d3
-datapath__740: datapath__97
-logic__8221: logic__8221
-reg__1324: reg__1324
-logic__6746: logic__6746
-logic__2001: logic__2001
-DTLB__1: DTLB
-logic__4501: logic__4501
-case__198: case__198
-datapath__458: datapath__458
-logic__640: logic__640
-logic__4090: logic__4090
-datapath__158: datapath__158
-logic__8031: logic__8031
-logic__5285: logic__5285
-reg__968: reg__968
-case__204: case__204
-logic__226: logic__226
-logic__4326: logic__4326
-datapath__273: datapath__273
-logic__6658: logic__6658
-logic__6815: logic__6815
-TLInterconnectCoupler_sbus_from_rockettile: TLInterconnectCoupler_sbus_from_rockettile
-logic__7856: logic__7856
-logic__3744: logic__3744
-case__1372: case__1372
-reg__436: reg__436
-case__676: case__676
-logic__2889: logic__2889
-reg__695: reg__695
-datapath__20: datapath__20
-reg__1282: reg__1282
-logic__8026: logic__8026
-reg__1230: reg__1230
-counter__22: counter__22
-case__1034: case__1034
-logic__3738: logic__3738
-reg__34: reg__34
-logic__263: logic__263
-datapath__244: datapath__244
-logic__4502: logic__4502
-logic__6808: logic__6808
-datapath__649: datapath__649
-reg__222: reg__222
-logic__5390: logic__5390
-case__72: case__72
-datapath__534: datapath__534
-reg__1299: reg__1299
-reg__1426: reg__833
-case__1515: case__1515
-case__889: case__889
-logic__6531: logic__6531
-TLFIFOFixer_2: TLFIFOFixer_2
-logic__9122: logic__1765
-reg__22: reg__22
-muxpart__38: muxpart__38
-case__1468: case__1468
-case__677: case__677
-case__1322: case__1322
-reg__1143: reg__1143
-logic__6211: logic__6211
-logic__2800: logic__2800
-reg__815: reg__815
-logic__223: logic__223
-logic__3148: logic__3148
-logic__8962: logic__8962
-case__1223: case__1223
-reg__433: reg__433
-logic__1079: logic__1079
-case__1291: case__1291
-logic__9276: logic__6120
-datapath__83: datapath__83
-case__66: case__66
-logic__230: logic__230
-datapath__579: datapath__579
-logic__6816: logic__6816
-case__363: case__363
-logic__2412: logic__2412
-datapath__180: datapath__180
-logic__4847: logic__4847
-logic__4487: logic__4487
-logic__253: logic__253
-reg__325: reg__325
-case__1597: case__102
-case__955: case__955
-reg__940: reg__940
-case__480: case__480
-logic__307: logic__307
-case__1132: case__1132
-logic__9033: logic__3866
-case__1020: case__1020
-case__858: case__858
-case__758: case__758
-reg__492: reg__492
-case__1279: case__1279
-Queue2_TLBundleD_a32d8s1k1z4u: Queue2_TLBundleD_a32d8s1k1z4u
-logic__9217: logic__1514
-reg__296: reg__296
-reg__469: reg__469
-reg__973: reg__973
-reg__1336: reg__1336
-logic__1813: logic__1813
-logic__4680: logic__4680
-logic__4977: logic__4977
-reg__546: reg__546
-logic__222: logic__222
-case__334: case__334
-logic__9126: logic__1747
-logic__3797: logic__3797
-logic__1654: logic__1654
-logic__1015: logic__1015
-logic__2269: logic__2269
-logic__5296: logic__5296
-case__490: case__490
-datapath__306: datapath__306
-logic__3091: logic__3091
-logic__6888: logic__6888
-case__239: case__239
-case__1100: case__1100
-muxpart__30: muxpart__30
-logic__4917: logic__4917
-case__1094: case__1094
-case__371: case__371
-datapath__169: datapath__169
-case__477: case__477
-dsp48e1__19: dsp48e1__19
-logic__5295: logic__5295
-reg__514: reg__514
-logic__1489: logic__1489
-logic__8219: logic__8219
-dual_port_bram__parameterized1: dual_port_bram__parameterized1
-keep__20: keep__8
-reg__53: reg__53
-logic__4746: logic__4746
-logic__5896: logic__5896
-logic__2278: logic__2278
-logic__2094: logic__2094
-logic__6022: logic__6022
-logic__8548: logic__8548
-case__626: case__626
-logic__4972: logic__4972
-extram__3: extram__3
-logic__8375: logic__8375
-case__555: case__555
-logic__7519: logic__7519
-logic__6605: logic__6605
-datapath__723: datapath__110
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__17: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__5452: logic__5452
-logic__1602: logic__1602
-reg__1001: reg__1001
-logic__4506: logic__4506
-logic__8309: logic__8309
-logic__5864: logic__5864
-reg__42: reg__42
-logic__1248: logic__1248
-logic__2434: logic__2434
-logic__6789: logic__6789
-logic__1477: logic__1477
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__7: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__415: reg__415
-reg__1383: reg__998
-datapath__43: datapath__43
-logic__5638: logic__5638
-reg__1447: reg__833
-muxpart__64: muxpart__64
-reg__323: reg__323
-case__593: case__593
-logic__816: logic__816
-case__1565: case__314
-case__436: case__436
-logic__8042: logic__8042
-reg__1181: reg__1181
-logic__6167: logic__6167
-logic__8296: logic__8296
-AsyncResetSynchronizerShiftReg_w1_d3_i0__4: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__6659: logic__6659
-logic__961: logic__961
-logic__8425: logic__8425
-logic__4168: logic__4168
-logic__1853: logic__1853
-logic__2673: logic__2673
-case__293: case__293
-logic__13: logic__13
-datapath__728: datapath__650
-logic__3048: logic__3048
-datapath__333: datapath__333
-logic__6041: logic__6041
-muxpart__78: muxpart__78
-logic__5005: logic__5005
-logic__9124: logic__1759
-datapath__665: datapath__665
-logic__6168: logic__6168
-logic__9079: logic__1882
-reg__938: reg__938
-logic__2203: logic__2203
-reg__374: reg__374
-logic__3222: logic__3222
-MulAddRecFNToRaw_preMul: MulAddRecFNToRaw_preMul
-logic__2835: logic__2835
-logic__268: logic__268
-case__656: case__656
-logic__2778: logic__2778
-AsyncResetRegVec_w1_i0: AsyncResetRegVec_w1_i0
-logic__9319: logic__269
-reg__1154: reg__1154
-case__609: case__609
-TLWidthWidget8_1__2: TLWidthWidget8_1
-case__42: case__42
-logic__7607: logic__7607
-case__1364: case__1364
-logic__2869: logic__2869
-reg__796: reg__796
-case__24: case__24
-TLFpgaSPI: TLFpgaSPI
-logic__519: logic__519
-muxpart__59: muxpart__59
-reg__213: reg__213
-acq_corr: acq_corr
-logic__923: logic__923
-reg__289: reg__289
-logic__5990: logic__5990
-logic__4027: logic__4027
-reg__1192: reg__1192
-reg__234: reg__234
-logic__2620: logic__2620
-logic__5427: logic__5427
-muxpart__191: muxpart__191
-datapath__552: datapath__552
-logic__9157: logic__1646
-reg__585: reg__585
-logic__140: logic__140
-logic__8984: logic__2971
-logic__922: logic__922
-logic__306: logic__306
-reg__288: reg__288
-case__909: case__909
-logic__8465: logic__8465
-logic__4089: logic__4089
-datapath__682: datapath__682
-reg__1243: reg__1243
-logic__6040: logic__6040
-case__1023: case__1023
-logic__6628: logic__6628
-datapath__487: datapath__487
-logic__2827: logic__2827
-logic__8616: logic__8616
-case__1127: case__1127
-logic__5239: logic__5239
-logic__6721: logic__6721
-logic__9224: logic__1503
-reg__1427: reg__835
-AsyncValidSync__22: AsyncValidSync
-logic__5700: logic__5700
-case__1037: case__1037
-logic__1521: logic__1521
-logic__2964: logic__2964
-logic__8624: logic__8624
-logic__8991: logic__2964
-case__1537: case__1537
-logic__3207: logic__3207
-case__1461: case__1461
-logic__5305: logic__5305
-datapath__518: datapath__518
-logic__145: logic__145
-logic__3733: logic__3733
-logic__4725: logic__4725
-logic__5311: logic__5311
-logic__8725: logic__8725
-datapath__155: datapath__155
-case__1560: case__319
-logic__4436: logic__4436
-reg__263: reg__263
-logic__1890: logic__1890
-logic__3561: logic__3561
-logic__8875: logic__8875
-IBuf: IBuf
-case__1356: case__1356
-datapath__437: datapath__437
-AsyncResetSynchronizerShiftReg_w1_d3_i0__9: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__5308: logic__5308
-logic__7307: logic__7307
-logic__6607: logic__6607
-Queue1_TLBundleD_a29d32s7k1z2u: Queue1_TLBundleD_a29d32s7k1z2u
-logic__1514: logic__1514
-reg__1081: reg__1081
-TLInterconnectCoupler_sbus_from_bus_named_fbus: TLInterconnectCoupler_sbus_from_bus_named_fbus
-logic__7510: logic__7510
-logic__671: logic__671
-logic__9197: logic__1558
-datapath__504: datapath__504
-logic__6348: logic__6348
-reg__742: reg__742
-reg__1297: reg__1297
-logic__1173: logic__1173
-case__895: case__895
-logic__6494: logic__6494
-case__693: case__693
-logic__5045: logic__5045
-logic__7635: logic__7635
-reg__905: reg__905
-reg__528: reg__528
-case__1350: case__1350
-datapath__639: datapath__639
-reg__1455: reg__834
-cdc_fifo_gray_dst: cdc_fifo_gray_dst
-datapath__746: datapath__18
-logic__931: logic__931
-logic__3735: logic__3735
-reg__206: reg__206
-case__370: case__370
-reg__1378: reg__1141
-logic__5849: logic__5849
-TLAsyncCrossingSink_a9d32s1k1z2u: TLAsyncCrossingSink_a9d32s1k1z2u
-logic__7297: logic__7297
-logic__2117: logic__2117
-case__918: case__918
-case__821: case__821
-datapath__117: datapath__117
-logic__4611: logic__4611
-datapath__743: datapath__94
-datapath__190: datapath__190
-logic__8737: logic__8737
-logic__8855: logic__8855
-logic__6008: logic__6008
-logic__6595: logic__6595
-extrom__3: extrom
-logic__3673: logic__3673
-case__857: case__857
-logic__1485: logic__1485
-logic__8667: logic__8667
-logic__2859: logic__2859
-logic__8271: logic__8271
-logic__5272: logic__5272
-reg__1475: reg__835
-logic__6509: logic__6509
-reg__1012: reg__1012
-logic__4399: logic__4399
-reg__144: reg__144
-IntToFP: IntToFP
-reg__1231: reg__1231
-logic__147: logic__147
-logic__3652: logic__3652
-reg__1092: reg__1092
-datapath__415: datapath__415
-logic__7549: logic__7549
-case__1521: case__1521
-logic__4418: logic__4418
-keep__19: keep__6
-reg__199: reg__199
-datapath__163: datapath__163
-logic__2205: logic__2205
-dsp48e1__20: dsp48e1__20
-reg__930: reg__930
-case__793: case__793
-reg__306: reg__306
-datapath__151: datapath__151
-logic__2469: logic__2469
-logic__3986: logic__3986
-logic__4265: logic__4265
-reg__1145: reg__1145
-logic__3873: logic__3873
-reg__681: reg__681
-logic__3610: logic__3610
-logic__8162: logic__8162
-case__455: case__455
-logic__1889: logic__1889
-logic__6735: logic__6735
-reg__835: reg__835
-reg__413: reg__413
-logic__1192: logic__1192
-case__1092: case__1092
-logic__8324: logic__8324
-case__492: case__492
-case__761: case__761
-datapath__85: datapath__85
-logic__3650: logic__3650
-logic__6627: logic__6627
-case__1217: case__1217
-logic__1518: logic__1518
-case__1595: case__104
-case__1518: case__1518
-reg__1072: reg__1072
-reg__710: reg__710
-case__268: case__268
-logic__631: logic__631
-logic__9069: logic__1908
-logic__3179: logic__3179
-IntSyncAsyncCrossingSink_n1x1: IntSyncAsyncCrossingSink_n1x1
-logic__6502: logic__6502
-datapath__336: datapath__336
-case__16: case__16
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__30: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6558: logic__6558
-case__142: case__142
-reg__984: reg__984
-keep__14: keep__8
-logic__4775: logic__4775
-case__329: case__329
-case__1007: case__1007
-logic__6276: logic__6276
-case__715: case__715
-dsp48e1__22: dsp48e1__22
-RoundRawFNToRecFN: RoundRawFNToRecFN
-datapath__677: datapath__677
-reg__481: reg__481
-logic__4862: logic__4862
-case__1281: case__1281
-LevelGateway__4: LevelGateway
-case__611: case__611
-logic__2113: logic__2113
-datapath__438: datapath__438
-logic__6630: logic__6630
-logic__5046: logic__5046
-muxpart__81: muxpart__81
-case__760: case__760
-logic__2568: logic__2568
-logic__6615: logic__6615
-logic__5628: logic__5628
-case__870: case__870
-reg__719: reg__719
-reg__535: reg__535
-muxpart__52: muxpart__52
-logic__6750: logic__6750
-logic__2795: logic__2795
-logic__3528: logic__3528
-datapath__6: datapath__6
-counter__10: counter__10
-logic__1566: logic__1566
-logic__5406: logic__5406
-reg__1: reg__1
-logic__9281: logic__6125
-reg__304: reg__304
-logic__74: logic__74
-logic__714: logic__714
-logic__676: logic__676
-logic__4973: logic__4973
-logic__4744: logic__4744
-logic__2553: logic__2553
-logic__6717: logic__6717
-dsp48e1__11: dsp48e1__11
-logic__3653: logic__3653
-logic__1591: logic__1591
-datapath__313: datapath__313
-muxpart__71: muxpart__71
-datapath__631: datapath__631
-logic__431: logic__431
-reg__1318: reg__1318
-datapath__235: datapath__235
-logic__7931: logic__7931
-logic__5477: logic__5477
-logic__5338: logic__5338
-reg__724: reg__724
-muxpart__224: muxpart__224
-logic__2368: logic__2368
-logic__4384: logic__4384
-muxpart__117: muxpart__117
-datapath__186: datapath__186
-logic__8220: logic__8220
-datapath__661: datapath__661
-dsp48e1__27: dsp48e1__27
-logic__1901: logic__1901
-case__379: case__379
-logic__1197: logic__1197
-case__327: case__327
-reg__244: reg__244
-logic__5367: logic__5367
-reg__1080: reg__1080
-datapath__601: datapath__601
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__5: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-spill_register: spill_register
-case__1320: case__1320
-case__1122: case__1122
-datapath__448: datapath__448
-case__1370: case__1370
-reg__595: reg__595
-logic__2794: logic__2794
-logic__2477: logic__2477
-case__286: case__286
-logic__275: logic__275
-reg__1323: reg__1323
-logic__6497: logic__6497
-logic__2399: logic__2399
-reg__1075: reg__1075
-logic__3332: logic__3332
-logic__8968: logic__3009
-logic__7306: logic__7306
-logic__7588: logic__7588
-logic__7837: logic__7837
-case__551: case__551
-logic__1801: logic__1801
-logic__4860: logic__4860
-logic__5302: logic__5302
-logic__9086: logic__1868
-case__1024: case__1024
-INToRecFN: INToRecFN
-dsp48e1__33: dsp48e1__33
-logic__5038: logic__5038
-logic__2855: logic__2855
-logic__7380: logic__7380
-reg__758: reg__758
-logic__875: logic__875
-logic__8466: logic__8466
-logic__4761: logic__4761
-reg__1009: reg__1009
-datapath__367: datapath__367
-logic__3776: logic__3776
-logic__5343: logic__5343
-extram__6: extram__6
-logic__5704: logic__5704
-reg__58: reg__58
-reg__150: reg__150
-logic__3698: logic__3698
-mult_46_15_61__2: mult_46_15_61
-datapath__185: datapath__185
-logic__8508: logic__8508
-TLXbar_fbus_i1_o1_a32d64s1k1z4u: TLXbar_fbus_i1_o1_a32d64s1k1z4u
-logic__272: logic__272
-case__451: case__451
-datapath__233: datapath__233
-logic__1537: logic__1537
-logic__5929: logic__5929
-logic__921: logic__921
-logic__5148: logic__5148
-logic__514: logic__514
-reg__991: reg__991
-reg__61: reg__61
-datapath__92: datapath__92
-reg__479: reg__479
-logic__4867: logic__4867
-case__1307: case__1307
-reg__520: reg__520
-case__297: case__297
-reg__164: reg__164
-logic__7930: logic__7930
-logic__6291: logic__6291
-TLToAPB: TLToAPB
-logic__8311: logic__8311
-logic__8359: logic__8359
-datapath__307: datapath__307
-logic__6590: logic__6590
-logic__873: logic__873
-Repeater_TLBundleA_a26d64s2k1z3u: Repeater_TLBundleA_a26d64s2k1z3u
-datapath__725: datapath__653
-logic__3238: logic__3238
-reg__54: reg__54
-reg__584: reg__584
-datapath__634: datapath__634
-logic__1644: logic__1644
-reg__369: reg__369
-logic__3999: logic__3999
-datapath__280: datapath__280
-case__1431: case__1431
-case__1421: case__1421
-TLWidthWidget8_1__1: TLWidthWidget8_1
-logic__6536: logic__6536
-logic__5273: logic__5273
-case__977: case__977
-logic__6916: logic__6916
-logic__9296: logic__507
-keep__7: keep__7
-logic__5096: logic__5096
-logic__7216: logic__7216
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__19: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__9067: logic__1912
-DCacheDataArray: DCacheDataArray
-logic__9087: logic__1867
-logic__4615: logic__4615
-reg__1403: reg__996
-logic__5388: logic__5388
-muxpart__193: muxpart__193
-logic__6393: logic__6393
-logic__3840: logic__3840
-reg__239: reg__239
-datapath__433: datapath__433
-logic__3692: logic__3692
-logic__6801: logic__6801
-logic__4571: logic__4571
-logic__7075: logic__7075
-dsp48e1__36: dsp48e1__36
-reg__740: reg__740
-datapath__159: datapath__159
-logic__2535: logic__2535
-logic__3243: logic__3243
-reg__1223: reg__1223
-logic__4751: logic__4751
-reg__237: reg__237
-logic__6738: logic__6738
-logic__5178: logic__5178
-logic__6621: logic__6621
-logic__529: logic__529
-logic__1596: logic__1596
-logic__2847: logic__2847
-logic__2030: logic__2030
-logic__2849: logic__2849
-logic__3764: logic__3764
-case__960: case__960
-case__804: case__804
-logic__209: logic__209
-datapath__209: datapath__209
-logic__8683: logic__8683
-logic__2171: logic__2171
-counter__20: counter__20
-reg__577: reg__577
-datapath__37: datapath__37
-logic__5345: logic__5345
-reg__834: reg__834
-reg__284: reg__284
-logic__8403: logic__8403
-logic__6076: logic__6076
-datapath__317: datapath__317
-logic__7601: logic__7601
-logic__3638: logic__3638
-logic__8626: logic__8626
-logic__1822: logic__1822
-logic__5180: logic__5180
-logic__6321: logic__6321
-datapath__227: datapath__227
-reg__886: reg__886
-logic__629: logic__629
-logic__4968: logic__4968
-reg__1211: reg__1211
-FPU__GB1: FPU__GB1
-case__567: case__567
-reg__464: reg__464
-logic__8250: logic__8250
-reg__592: reg__592
-logic__7459: logic__7459
-logic__5316: logic__5316
-reg__248: reg__248
-logic__6222: logic__6222
-TLWidthWidget8_4: TLWidthWidget8_4
-logic__9081: logic__1873
-TLBuffer_a29d64s2k1z3u__1: TLBuffer_a29d64s2k1z3u
-reg__508: reg__508
-logic__1223: logic__1223
-logic__8623: logic__8623
-logic__1714: logic__1714
-logic__700: logic__700
-reg__1044: reg__1044
-reg__655: reg__655
-logic__1313: logic__1313
-logic__9083: logic__1871
-case__999: case__999
-datapath__162: datapath__162
-datapath__476: datapath__476
-logic__9027: logic__3897
-logic__9294: logic__513
-logic__9168: logic__1623
-case__534: case__534
-logic__3323: logic__3323
-logic__2676: logic__2676
-logic__144: logic__144
-logic__6639: logic__6639
-case__817: case__817
-keep: keep
-logic__2887: logic__2887
-logic__6586: logic__6586
-logic__8879: logic__8879
-logic__3140: logic__3140
-logic__5433: logic__5433
-reg__560: reg__560
-case__635: case__635
-case__726: case__726
-datapath__539: datapath__539
-keep__11: keep__8
-datapath__264: datapath__264
-datapath__315: datapath__315
-logic__3845: logic__3845
-reg__533: reg__533
-muxpart__16: muxpart__16
-reg__36: reg__36
-logic__1414: logic__1414
-muxpart__250: muxpart__10
-reg__1099: reg__1099
-datapath__678: datapath__678
-case__1175: case__1175
-reg__778: reg__778
-datapath__192: datapath__192
-case__1294: case__1294
-case__1057: case__1057
-case__392: case__392
-ram: ram
-logic__7154: logic__7154
-logic__3403: logic__3403
-case__499: case__499
-logic__4952: logic__4952
-reg__920: reg__920
-logic__6794: logic__6794
-reg__280: reg__280
-trck_cntrl: trck_cntrl
-reg__1262: reg__1262
-reg__51: reg__51
-logic__6559: logic__6559
-logic__5266: logic__5266
-logic__5899: logic__5899
-logic__2664: logic__2664
-logic__5298: logic__5298
-logic__9106: logic__1816
-logic__7395: logic__7395
-logic__1900: logic__1900
-logic__6418: logic__6418
-logic__2365: logic__2365
-case__34: case__34
-dsp48e1__38: dsp48e1__38
-case__1005: case__1005
-logic__6190: logic__6190
-reg__1170: reg__1170
-logic__425: logic__425
-case__764: case__764
-reg__819: reg__819
-reg__118: reg__118
-logic__3268: logic__3268
-reg__407: reg__407
-logic__4334: logic__4334
-logic__6666: logic__6666
-logic__4700: logic__4700
-double_ff_syn__3: double_ff_syn
-logic__2787: logic__2787
-logic__9114: logic__1790
-logic__7547: logic__7547
-datapath__11: datapath__11
-reg__1141: reg__1141
-datapath__309: datapath__309
-muxpart__53: muxpart__53
-case__1396: case__1396
-logic__7606: logic__7606
-logic__7048: logic__7048
-case__175: case__175
-logic__4743: logic__4743
-case__540: case__540
-datapath__301: datapath__301
-logic__9260: logic__8236
-datapath__284: datapath__284
-MulDiv: MulDiv
-muxpart__9: muxpart__9
-reg__668: reg__668
-logic__4528: logic__4528
-muxpart__24: muxpart__24
-datapath__22: datapath__22
-logic__1587: logic__1587
-reg__1271: reg__1271
-reg__709: reg__709
-keep__8: keep__8
-logic__9200: logic__1551
-logic__2541: logic__2541
-datapath__316: datapath__316
-rom__7: rom__7
-logic__4167: logic__4167
-logic: logic
-logic__2079: logic__2079
-ram_2x115: ram_2x115
-logic__6501: logic__6501
-logic__2067: logic__2067
-logic__1816: logic__1816
-logic__1666: logic__1666
-reg__1434: reg__834
-reg__1525: reg__60
-logic__304: logic__304
-dsp48e1__14: dsp48e1__14
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/54573100.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/54573100.rtd
deleted file mode 100644
index 48be5c4..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/54573100.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55C42420.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55C42420.rtd
deleted file mode 100644
index afd6069..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55C42420.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55C67420.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55C67420.rtd
deleted file mode 100644
index 99eb6b8..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55C67420.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55DF1B00.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55DF1B00.rtd
deleted file mode 100644
index 0d43435..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55DF1B00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55E32220.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55E32220.rtd
deleted file mode 100644
index 9d963dc..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/55E32220.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/562790E0.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/562790E0.rtd
deleted file mode 100644
index c1c9b25..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/562790E0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/56DC6640.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/56DC6640.rtd
deleted file mode 100644
index ce6ccaf..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/56DC6640.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/59BB7D60.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/59BB7D60.rtd
deleted file mode 100644
index ca04624..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/59BB7D60.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/820E5E00.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/820E5E00.rtd
deleted file mode 100644
index ad03533..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/820E5E00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/9289B660.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/9289B660.rtd
deleted file mode 100644
index 6190b68..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/9289B660.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/93836360.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/93836360.rtd
deleted file mode 100644
index 461e419..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/93836360.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/design.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/design.rtd
deleted file mode 100644
index 1f0f576..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/files.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/files.rtd
deleted file mode 100644
index 48b9873..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/files.rtd
+++ /dev/null
@@ -1,13 +0,0 @@
-design.rtd
-straps.rtd
-54573100.rtd
-56DC6640.rtd
-93836360.rtd
-55C67420.rtd
-562790E0.rtd
-59BB7D60.rtd
-55DF1B00.rtd
-55C42420.rtd
-9289B660.rtd
-820E5E00.rtd
-55E32220.rtd
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/straps.rtd b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/straps.rtd
deleted file mode 100644
index fb7e041..0000000
Binary files a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/topModuleToGenome.map b/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/topModuleToGenome.map
deleted file mode 100644
index 08c97d8..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/1309558296/u/topModuleToGenome.map
+++ /dev/null
@@ -1,10 +0,0 @@
-RocketTile: RocketTile__GCB0, FPU, DCache,
-TilePRCIDomain: TilePRCIDomain__GC0, HierarchicalElementResetDomain,
-tracking_wrapper: tracking_wrapper,
-FPU: FPU__GB2, FPU__GB1, FPU__GB0,
-DCache: DCache,
-HierarchicalElementResetDomain: RocketTile,
-FPGAGPSClockSinkDomain: TLToAPB, APBGpsBlock,
-APBGpsBlock: APBGpsBlock__GC0, tracking_wrapper,
-VCU118RocketSystem: VCU118RocketSystem__GC0, FPGAGPSClockSinkDomain, TilePRCIDomain,
-TLToAPB: TLToAPB,
diff --git a/.Xil/Vivado-7908-onur/incrSyn/soln.nlo b/.Xil/Vivado-7908-onur/incrSyn/soln.nlo
deleted file mode 100644
index 13af484..0000000
--- a/.Xil/Vivado-7908-onur/incrSyn/soln.nlo
+++ /dev/null
@@ -1 +0,0 @@
-1 -2
diff --git a/.Xil/Vivado-7908-onur/wt/synthesis.wdf b/.Xil/Vivado-7908-onur/wt/synthesis.wdf
deleted file mode 100644
index e522e0a..0000000
--- a/.Xil/Vivado-7908-onur/wt/synthesis.wdf
+++ /dev/null
@@ -1,52 +0,0 @@
-version:1
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b333235746666673930302d32:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:67656e65737973325f726f636b65745f746f70:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d53594e544845534953:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7668646c5f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66696c65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f77:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f775f73657474696e6773:64656661756c743a3a6e6f6e65:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c75745f63617363616465:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d676c6f62616c5f726574696d696e67:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30333a313973:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:333337362e3030344d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313735352e3138344d42:00:00
-eof:3464668999
diff --git a/.Xil/Vivado-7908-onur/wt/synthesis_details.wdf b/.Xil/Vivado-7908-onur/wt/synthesis_details.wdf
deleted file mode 100644
index 78f8d66..0000000
--- a/.Xil/Vivado-7908-onur/wt/synthesis_details.wdf
+++ /dev/null
@@ -1,3 +0,0 @@
-version:1
-73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
-eof:2511430288
diff --git a/.Xil/Vivado-818686-ankalab04/.lpr b/.Xil/Vivado-818686-ankalab04/.lpr
deleted file mode 100644
index 04ef66e..0000000
--- a/.Xil/Vivado-818686-ankalab04/.lpr
+++ /dev/null
@@ -1,7 +0,0 @@
-
-
-
-
-
-
-
diff --git a/.Xil/Vivado-818686-ankalab04/elab.rtd b/.Xil/Vivado-818686-ankalab04/elab.rtd
deleted file mode 100644
index 2bbbe07..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/elab.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/gig_ethernet_pcs_pma_0_in_context.xdc b/.Xil/Vivado-818686-ankalab04/gig_ethernet_pcs_pma_0_in_context.xdc
deleted file mode 100644
index 028c969..0000000
--- a/.Xil/Vivado-818686-ankalab04/gig_ethernet_pcs_pma_0_in_context.xdc
+++ /dev/null
@@ -1,20 +0,0 @@
-create_clock -period 1.600 [get_ports {refclk625_p}]
-create_generated_clock -source [get_ports -no_traverse refclk625_p] -edges {1 2 3} -edge_shift {0.000 2.400 4.800} [get_ports -no_traverse {riu_clk_out}]
-create_generated_clock -source [get_ports -no_traverse refclk625_p] -edges {1 2 3} -edge_shift {0.000 0.800 1.600} [get_ports -no_traverse {clk312_out}]
-create_generated_clock -source [get_ports -no_traverse refclk625_p] -edges {1 2 3} -edge_shift {0.000 -0.400 -0.800} [get_ports -no_traverse {tx_pll_clk_out}]
-create_generated_clock -source [get_ports -no_traverse refclk625_p] -edges {1 2 3} -edge_shift {0.000 2.400 4.800} [get_ports -no_traverse {tx_rdclk_out}]
-create_generated_clock -source [get_ports -no_traverse refclk625_p] -edges {1 2 3} -edge_shift {0.000 3.200 6.400} [get_ports -no_traverse {clk125_out}]
-create_generated_clock -source [get_ports -no_traverse refclk625_p] -edges {1 2 3} -edge_shift {0.000 0.000 0.000} [get_ports -no_traverse {rx_pll_clk_out}]
-set_property -quiet IO_BUFFER_TYPE NONE [get_ports -quiet refclk625_n]
-set_property -quiet CLOCK_BUFFER_TYPE NONE [get_ports -quiet refclk625_n]
-set_property -quiet IO_BUFFER_TYPE NONE [get_ports -quiet refclk625_p]
-set_property -quiet CLOCK_BUFFER_TYPE NONE [get_ports -quiet refclk625_p]
-set_property -quiet IO_BUFFER_TYPE NONE [get_ports -quiet rxn_0]
-set_property -quiet CLOCK_BUFFER_TYPE NONE [get_ports -quiet rxn_0]
-set_property -quiet IO_BUFFER_TYPE NONE [get_ports -quiet rxp_0]
-set_property -quiet CLOCK_BUFFER_TYPE NONE [get_ports -quiet rxp_0]
-set_property -quiet IO_BUFFER_TYPE NONE [get_ports -quiet txn_0]
-set_property -quiet CLOCK_BUFFER_TYPE NONE [get_ports -quiet txn_0]
-set_property -quiet IO_BUFFER_TYPE NONE [get_ports -quiet txp_0]
-set_property -quiet CLOCK_BUFFER_TYPE NONE [get_ports -quiet txp_0]
-set_property -quiet IS_IP_OOC_CELL TRUE [get_cells -of [get_ports -no_traverse -quiet an_adv_config_vector_0[0]]]
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/equivDumpFile.info b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/equivDumpFile.info
deleted file mode 100644
index 5f2df82..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/equivDumpFile.info
+++ /dev/null
@@ -1,5 +0,0 @@
-/u_rocket/VCU118RocketSystem__GC0#79:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#0
-/u_rocket/VCU118RocketSystem__GC0#80:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#1
-/u_rocket/VCU118RocketSystem__GC0#293:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#405
-/u_rocket/VCU118RocketSystem__GC0#291:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#403
-/u_rocket/VCU118RocketSystem__GC0#292:/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#404
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1220760385.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1220760385.rtd
deleted file mode 100644
index 7b4331a..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index 6052d5c..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1294509424.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1294509424.rtd
deleted file mode 100644
index fb12f51..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index babf46d..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/136113302.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/136113302.rtd
deleted file mode 100644
index bbedb58..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/136113302.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/136113302.rtd.straps.rtd
deleted file mode 100644
index d49a5db..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1672436263.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1672436263.rtd
deleted file mode 100644
index fb5c739..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index 5da84a1..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2438764479.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2438764479.rtd
deleted file mode 100644
index 8031f43..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2438764479.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2438764479.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2438764479.rtd.straps.rtd
deleted file mode 100644
index 8bf6073..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2438764479.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2438764479.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2438764479.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2438764479.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2438764479.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2438764479.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2610937407.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2610937407.rtd
deleted file mode 100644
index 8881093..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index e05b102..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2737226844.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2737226844.rtd
deleted file mode 100644
index c92a343..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index 5aed6bc..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2962621930.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2962621930.rtd
deleted file mode 100644
index a27633d..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index 773df48..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/3482045580.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/3482045580.rtd
deleted file mode 100644
index 3460581..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index a9c8894..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/944784429.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/944784429.rtd
deleted file mode 100644
index 1bbcb7a..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/944784429.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/944784429.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/944784429.rtd.straps.rtd
deleted file mode 100644
index 5cbac8e..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/944784429.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/944784429.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/944784429.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/944784429.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/944784429.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/944784429.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/976197094.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/976197094.rtd
deleted file mode 100644
index eace5bd..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/976197094.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/976197094.rtd.straps.rtd
deleted file mode 100644
index a47fdb7..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/global_name.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/global_name.straps.rtd
deleted file mode 100644
index 29223e1..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/instToEncGenName.map b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/instToEncGenName.map
deleted file mode 100644
index 8ea6da9..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/g/instToEncGenName.map
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/vcu118_rocket_top__GC0:944784429
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0:2438764479
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/genomeDependencyGraph.out b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/genomeDependencyGraph.out
deleted file mode 100644
index 5183174..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/genomeDependencyGraph.out
+++ /dev/null
@@ -1,58 +0,0 @@
-GENOME NON_GENOME PIN 406: GENOME NON_GENOME PIN 0
-GENOME NON_GENOME PIN 0: GENOME NON_GENOME PIN 406
-GENOME NON_GENOME PIN 407: GENOME NON_GENOME PIN 1
-GENOME NON_GENOME PIN 1: GENOME NON_GENOME PIN 407
-GENOME NON_GENOME PIN 805: GENOME NON_GENOME PIN 403
-GENOME NON_GENOME PIN 403: GENOME NON_GENOME PIN 805
-GENOME NON_GENOME PIN 806: GENOME NON_GENOME PIN 404
-GENOME NON_GENOME PIN 404: GENOME NON_GENOME PIN 806
-GENOME NON_GENOME PIN 807: GENOME NON_GENOME PIN 405
-GENOME NON_GENOME PIN 405: GENOME NON_GENOME PIN 807
-INST TLToAPB PIN 119: INST VCU118RocketSystem__GC0 PIN 83 TYPE 5
-INST TLToAPB PIN 120: INST VCU118RocketSystem__GC0 PIN 84 TYPE 5
-INST TLToAPB PIN 121: INST VCU118RocketSystem__GC0 PIN 85 TYPE 5
-INST TLToAPB PIN 122: INST VCU118RocketSystem__GC0 PIN 86 TYPE 5
-INST TLToAPB PIN 123: INST VCU118RocketSystem__GC0 PIN 87 TYPE 5
-INST TLToAPB PIN 162: INST VCU118RocketSystem__GC0 PIN 126 TYPE 5
-INST TLToAPB PIN 163: INST VCU118RocketSystem__GC0 PIN 127 TYPE 5
-INST TLToAPB PIN 164: INST VCU118RocketSystem__GC0 PIN 128 TYPE 5
-INST TLToAPB PIN 165: INST VCU118RocketSystem__GC0 PIN 129 TYPE 5
-INST TLToAPB PIN 166: INST VCU118RocketSystem__GC0 PIN 130 TYPE 5
-INST TLToAPB PIN 167: INST VCU118RocketSystem__GC0 PIN 131 TYPE 5
-INST TLToAPB PIN 168: INST VCU118RocketSystem__GC0 PIN 132 TYPE 5
-INST TLToAPB PIN 169: INST VCU118RocketSystem__GC0 PIN 133 TYPE 5
-INST TLToAPB PIN 170: INST VCU118RocketSystem__GC0 PIN 134 TYPE 5
-INST TLToAPB PIN 171: INST VCU118RocketSystem__GC0 PIN 135 TYPE 5
-INST TLToAPB PIN 172: INST VCU118RocketSystem__GC0 PIN 136 TYPE 5
-INST TLToAPB PIN 205: INST VCU118RocketSystem__GC0 PIN 169 TYPE 5
-INST TilePRCIDomain__GC0 PIN 728: INST VCU118RocketSystem__GC0 PIN 289 TYPE 5
-INST VCU118RocketSystem__GC0 PIN 79: INST TilePRCIDomain__GC0 PIN 0 TYPE 3 INST FPU__GB0 PIN 301 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST DCache PIN 336 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 80: INST TilePRCIDomain__GC0 PIN 1 TYPE 3 INST FPU__GB1 PIN 323 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST DCache PIN 337 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 293: INST TilePRCIDomain__GC0 PIN 405 TYPE 3 INST RocketTile__GCB0 PIN 1114 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 291: INST TilePRCIDomain__GC0 PIN 403 TYPE 3 INST RocketTile__GCB0 PIN 1115 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 292: INST TilePRCIDomain__GC0 PIN 404 TYPE 3 INST RocketTile__GCB0 PIN 1116 TYPE 4
-INST DCache PIN 340: INST RocketTile__GCB0 PIN 2 TYPE 5
-INST DCache PIN 347: INST RocketTile__GCB0 PIN 9 TYPE 5
-INST DCache PIN 7: INST RocketTile__GCB0 PIN 1125 TYPE 0 GENOME DCache PIN 7
-INST DCache PIN 8: INST RocketTile__GCB0 PIN 1126 TYPE 0 GENOME DCache PIN 8
-INST DCache PIN 43: INST RocketTile__GCB0 PIN 1161 TYPE 0 GENOME DCache PIN 43
-INST DCache PIN 44: INST RocketTile__GCB0 PIN 1162 TYPE 0 GENOME DCache PIN 44
-INST DCache PIN 45: INST RocketTile__GCB0 PIN 1163 TYPE 0 GENOME DCache PIN 45
-INST DCache PIN 46: INST RocketTile__GCB0 PIN 1164 TYPE 0 GENOME DCache PIN 46
-INST DCache PIN 330: INST RocketTile__GCB0 PIN 1644 TYPE 0 GENOME DCache PIN 330
-INST DCache PIN 331: INST RocketTile__GCB0 PIN 1645 TYPE 0 GENOME DCache PIN 331
-INST TLToAPB PIN 2: INST VCU118RocketSystem__GC0 PIN 489 TYPE 0 GENOME TLToAPB PIN 2
-INST TLToAPB PIN 3: INST VCU118RocketSystem__GC0 PIN 490 TYPE 0 GENOME TLToAPB PIN 3
-INST TLToAPB PIN 5: INST VCU118RocketSystem__GC0 PIN 492 TYPE 0 GENOME TLToAPB PIN 5
-INST TLToAPB PIN 6: INST VCU118RocketSystem__GC0 PIN 493 TYPE 0 GENOME TLToAPB PIN 6
-INST TLToAPB PIN 16: INST VCU118RocketSystem__GC0 PIN 503 TYPE 0 GENOME TLToAPB PIN 16
-INST TilePRCIDomain__GC0 PIN 211: INST VCU118RocketSystem__GC0 PIN 543 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 211
-INST TilePRCIDomain__GC0 PIN 212: INST VCU118RocketSystem__GC0 PIN 544 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 212
-INST TilePRCIDomain__GC0 PIN 0: GENOME TilePRCIDomain__GC0 PIN 0
-INST TilePRCIDomain__GC0 PIN 1: GENOME TilePRCIDomain__GC0 PIN 1
-INST TilePRCIDomain__GC0 PIN 403: GENOME TilePRCIDomain__GC0 PIN 403
-INST TilePRCIDomain__GC0 PIN 404: GENOME TilePRCIDomain__GC0 PIN 404
-INST TilePRCIDomain__GC0 PIN 405: GENOME TilePRCIDomain__GC0 PIN 405
-INST TilePRCIDomain__GC0 PIN 805: INST VCU118RocketSystem__GC0 PIN 291 TYPE 5
-INST TilePRCIDomain__GC0 PIN 806: INST VCU118RocketSystem__GC0 PIN 292 TYPE 5
-INST TilePRCIDomain__GC0 PIN 807: INST VCU118RocketSystem__GC0 PIN 293 TYPE 5
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/genomes.map b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/genomes.map
deleted file mode 100644
index cfa766a..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/genomes.map
+++ /dev/null
@@ -1,11 +0,0 @@
-FPU__GB0 829C10A0
-FPU__GB1 9ACCC7C0
-FPU__GB2 9ACCD5C0
-RocketTile__GCB0 6E0210C0
-DCache 6BD9BDC0
-TilePRCIDomain__GC0 A2F48880
-tracking_wrapper 6B840B80
-APBGpsBlock__GC0 83465020
-TLToAPB 6BD21860
-VCU118RocketSystem__GC0 B6EB5CA0
-vcu118_rocket_top__GC0 72B2BB00
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/82910060.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/82910060.rtd
deleted file mode 100644
index da4d53a..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/82910060.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/82910260.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/82910260.rtd
deleted file mode 100644
index 13cc62a..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/82910260.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/82910E00.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/82910E00.rtd
deleted file mode 100644
index 9360f1b..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/82910E00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/8395DBA0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/8395DBA0.rtd
deleted file mode 100644
index 025be7c..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/8395DBA0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/CA7D28A0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/CA7D28A0.rtd
deleted file mode 100644
index b11cdb8..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/CA7D28A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/CA7D3D00.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/CA7D3D00.rtd
deleted file mode 100644
index 65510c5..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/CA7D3D00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/CC7B28E0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/CC7B28E0.rtd
deleted file mode 100644
index 815b6ad..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/CC7B28E0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE4E1080.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE4E1080.rtd
deleted file mode 100644
index dd70bfd..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE4E1080.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE4E10A0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE4E10A0.rtd
deleted file mode 100644
index 5e0d582..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE4E10A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE4E19C0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE4E19C0.rtd
deleted file mode 100644
index b0c8873..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE4E19C0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE51A320.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE51A320.rtd
deleted file mode 100644
index cb5c6ad..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/EE51A320.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/design.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/design.rtd
deleted file mode 100644
index a4b79aa..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/files.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/files.rtd
deleted file mode 100644
index 3f4f6d5..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/files.rtd
+++ /dev/null
@@ -1,13 +0,0 @@
-design.rtd
-straps.rtd
-82910060.rtd
-82910260.rtd
-82910E00.rtd
-EE51A320.rtd
-EE4E19C0.rtd
-EE4E10A0.rtd
-CA7D28A0.rtd
-CA7D3D00.rtd
-EE4E1080.rtd
-CC7B28E0.rtd
-8395DBA0.rtd
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/straps.rtd
deleted file mode 100644
index a6ea42f..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/uniqInferGenToOrigInferGen.map b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/a/uniqInferGenToOrigInferGen.map
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/genomeDependencyGraph.out b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/genomeDependencyGraph.out
deleted file mode 100644
index 194ec18..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/genomeDependencyGraph.out
+++ /dev/null
@@ -1,906 +0,0 @@
-GENOME NON_GENOME PIN 406: GENOME NON_GENOME PIN 0
-GENOME NON_GENOME PIN 0: GENOME NON_GENOME PIN 406
-GENOME NON_GENOME PIN 407: GENOME NON_GENOME PIN 1
-GENOME NON_GENOME PIN 1: GENOME NON_GENOME PIN 407 GENOME NON_GENOME PIN 455
-GENOME NON_GENOME PIN 805: GENOME NON_GENOME PIN 403 GENOME NON_GENOME PIN 867
-GENOME NON_GENOME PIN 403: GENOME NON_GENOME PIN 805 GENOME NON_GENOME PIN 465
-GENOME NON_GENOME PIN 806: GENOME NON_GENOME PIN 404
-GENOME NON_GENOME PIN 404: GENOME NON_GENOME PIN 806
-GENOME NON_GENOME PIN 807: GENOME NON_GENOME PIN 405
-GENOME NON_GENOME PIN 405: GENOME NON_GENOME PIN 807
-INST TLToAPB PIN 119: INST VCU118RocketSystem__GC0 PIN 83 TYPE 5
-INST TLToAPB PIN 120: INST VCU118RocketSystem__GC0 PIN 84 TYPE 5
-INST TLToAPB PIN 121: INST VCU118RocketSystem__GC0 PIN 85 TYPE 5
-INST TLToAPB PIN 122: INST VCU118RocketSystem__GC0 PIN 86 TYPE 5
-INST TLToAPB PIN 123: INST VCU118RocketSystem__GC0 PIN 87 TYPE 5
-INST TLToAPB PIN 162: INST VCU118RocketSystem__GC0 PIN 126 TYPE 5
-INST TLToAPB PIN 163: INST VCU118RocketSystem__GC0 PIN 127 TYPE 5
-INST TLToAPB PIN 164: INST VCU118RocketSystem__GC0 PIN 128 TYPE 5
-INST TLToAPB PIN 165: INST VCU118RocketSystem__GC0 PIN 129 TYPE 5
-INST TLToAPB PIN 166: INST VCU118RocketSystem__GC0 PIN 130 TYPE 5
-INST TLToAPB PIN 167: INST VCU118RocketSystem__GC0 PIN 131 TYPE 5
-INST TLToAPB PIN 168: INST VCU118RocketSystem__GC0 PIN 132 TYPE 5
-INST TLToAPB PIN 169: INST VCU118RocketSystem__GC0 PIN 133 TYPE 5
-INST TLToAPB PIN 170: INST VCU118RocketSystem__GC0 PIN 134 TYPE 5
-INST TLToAPB PIN 171: INST VCU118RocketSystem__GC0 PIN 135 TYPE 5
-INST TLToAPB PIN 172: INST VCU118RocketSystem__GC0 PIN 136 TYPE 5
-INST TLToAPB PIN 205: INST VCU118RocketSystem__GC0 PIN 169 TYPE 5
-INST TilePRCIDomain__GC0 PIN 728: INST VCU118RocketSystem__GC0 PIN 289 TYPE 5
-INST VCU118RocketSystem__GC0 PIN 79: INST TilePRCIDomain__GC0 PIN 0 TYPE 3 INST FPU__GB0 PIN 301 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST DCache PIN 336 TYPE 4 GENOME VCU118RocketSystem__GC0 PIN 79
-INST VCU118RocketSystem__GC0 PIN 80: INST TilePRCIDomain__GC0 PIN 1 TYPE 3 INST FPU__GB1 PIN 323 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST DCache PIN 337 TYPE 4 GENOME VCU118RocketSystem__GC0 PIN 80
-INST VCU118RocketSystem__GC0 PIN 293: INST TilePRCIDomain__GC0 PIN 405 TYPE 3 INST RocketTile__GCB0 PIN 1114 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 291: INST TilePRCIDomain__GC0 PIN 403 TYPE 3 INST RocketTile__GCB0 PIN 1115 TYPE 4
-INST VCU118RocketSystem__GC0 PIN 292: INST TilePRCIDomain__GC0 PIN 404 TYPE 3 INST RocketTile__GCB0 PIN 1116 TYPE 4
-INST DCache PIN 340: INST RocketTile__GCB0 PIN 2 TYPE 5
-INST DCache PIN 347: INST RocketTile__GCB0 PIN 9 TYPE 5
-INST DCache PIN 7: INST RocketTile__GCB0 PIN 1125 TYPE 0 GENOME DCache PIN 7
-INST DCache PIN 8: INST RocketTile__GCB0 PIN 1126 TYPE 0 GENOME DCache PIN 8
-INST DCache PIN 43: INST RocketTile__GCB0 PIN 1161 TYPE 0 GENOME DCache PIN 43
-INST DCache PIN 44: INST RocketTile__GCB0 PIN 1162 TYPE 0 GENOME DCache PIN 44
-INST DCache PIN 45: INST RocketTile__GCB0 PIN 1163 TYPE 0 GENOME DCache PIN 45
-INST DCache PIN 46: INST RocketTile__GCB0 PIN 1164 TYPE 0 GENOME DCache PIN 46
-INST DCache PIN 330: INST RocketTile__GCB0 PIN 1644 TYPE 0 GENOME DCache PIN 330
-INST DCache PIN 331: INST RocketTile__GCB0 PIN 1645 TYPE 0 GENOME DCache PIN 331
-INST TLToAPB PIN 2: INST VCU118RocketSystem__GC0 PIN 489 TYPE 0 GENOME TLToAPB PIN 2
-INST TLToAPB PIN 3: INST VCU118RocketSystem__GC0 PIN 490 TYPE 0 GENOME TLToAPB PIN 3
-INST TLToAPB PIN 5: INST VCU118RocketSystem__GC0 PIN 492 TYPE 0 GENOME TLToAPB PIN 5
-INST TLToAPB PIN 6: INST VCU118RocketSystem__GC0 PIN 493 TYPE 0 GENOME TLToAPB PIN 6
-INST TLToAPB PIN 16: INST VCU118RocketSystem__GC0 PIN 503 TYPE 0 GENOME TLToAPB PIN 16
-INST TilePRCIDomain__GC0 PIN 211: INST VCU118RocketSystem__GC0 PIN 543 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 211
-INST TilePRCIDomain__GC0 PIN 212: INST VCU118RocketSystem__GC0 PIN 544 TYPE 0 GENOME TilePRCIDomain__GC0 PIN 212
-INST TilePRCIDomain__GC0 PIN 0: GENOME TilePRCIDomain__GC0 PIN 0
-INST TilePRCIDomain__GC0 PIN 1: GENOME TilePRCIDomain__GC0 PIN 1
-INST TilePRCIDomain__GC0 PIN 403: GENOME TilePRCIDomain__GC0 PIN 403
-INST TilePRCIDomain__GC0 PIN 404: GENOME TilePRCIDomain__GC0 PIN 404
-INST TilePRCIDomain__GC0 PIN 405: GENOME TilePRCIDomain__GC0 PIN 405
-INST TilePRCIDomain__GC0 PIN 805: INST VCU118RocketSystem__GC0 PIN 291 TYPE 5
-INST TilePRCIDomain__GC0 PIN 806: INST VCU118RocketSystem__GC0 PIN 292 TYPE 5
-INST TilePRCIDomain__GC0 PIN 807: INST VCU118RocketSystem__GC0 PIN 293 TYPE 5
-INST NON_GENOME PIN 22: INST vcu118_rocket_top__GC0 PIN 55 TYPE 3
-INST vcu118_rocket_top__GC0 PIN 44: INST NON_GENOME PIN 102 TYPE 1 GENOME vcu118_rocket_top__GC0 PIN 44
-INST APBGpsBlock__GC0 PIN 110: INST TLToAPB PIN 83 TYPE 5
-INST APBGpsBlock__GC0 PIN 111: INST TLToAPB PIN 84 TYPE 5
-INST APBGpsBlock__GC0 PIN 112: INST TLToAPB PIN 85 TYPE 5
-INST APBGpsBlock__GC0 PIN 113: INST TLToAPB PIN 86 TYPE 5
-INST APBGpsBlock__GC0 PIN 114: INST TLToAPB PIN 87 TYPE 5
-INST APBGpsBlock__GC0 PIN 115: INST TLToAPB PIN 88 TYPE 5
-INST APBGpsBlock__GC0 PIN 116: INST TLToAPB PIN 89 TYPE 5
-INST APBGpsBlock__GC0 PIN 117: INST TLToAPB PIN 90 TYPE 5
-INST APBGpsBlock__GC0 PIN 118: INST TLToAPB PIN 91 TYPE 5
-INST APBGpsBlock__GC0 PIN 119: INST TLToAPB PIN 92 TYPE 5
-INST APBGpsBlock__GC0 PIN 120: INST TLToAPB PIN 93 TYPE 5
-INST APBGpsBlock__GC0 PIN 121: INST TLToAPB PIN 94 TYPE 5
-INST APBGpsBlock__GC0 PIN 122: INST TLToAPB PIN 95 TYPE 5
-INST APBGpsBlock__GC0 PIN 123: INST TLToAPB PIN 96 TYPE 5
-INST APBGpsBlock__GC0 PIN 124: INST TLToAPB PIN 97 TYPE 5
-INST APBGpsBlock__GC0 PIN 125: INST TLToAPB PIN 98 TYPE 5
-INST APBGpsBlock__GC0 PIN 126: INST TLToAPB PIN 99 TYPE 5
-INST APBGpsBlock__GC0 PIN 127: INST TLToAPB PIN 100 TYPE 5
-INST APBGpsBlock__GC0 PIN 128: INST TLToAPB PIN 101 TYPE 5
-INST APBGpsBlock__GC0 PIN 129: INST TLToAPB PIN 102 TYPE 5
-INST APBGpsBlock__GC0 PIN 130: INST TLToAPB PIN 103 TYPE 5
-INST APBGpsBlock__GC0 PIN 131: INST TLToAPB PIN 104 TYPE 5
-INST APBGpsBlock__GC0 PIN 132: INST TLToAPB PIN 105 TYPE 5
-INST APBGpsBlock__GC0 PIN 133: INST TLToAPB PIN 106 TYPE 5
-INST APBGpsBlock__GC0 PIN 134: INST TLToAPB PIN 107 TYPE 5
-INST APBGpsBlock__GC0 PIN 135: INST TLToAPB PIN 108 TYPE 5
-INST APBGpsBlock__GC0 PIN 136: INST TLToAPB PIN 109 TYPE 5
-INST NON_GENOME PIN 51: INST VCU118RocketSystem__GC0 PIN 171 TYPE 3 INST tracking_wrapper PIN 35 TYPE 4 INST APBGpsBlock__GC0 PIN 78 TYPE 4 INST TLToAPB PIN 115 TYPE 4
-INST NON_GENOME PIN 52: INST VCU118RocketSystem__GC0 PIN 172 TYPE 3 INST APBGpsBlock__GC0 PIN 455 TYPE 4 INST TLToAPB PIN 116 TYPE 4
-INST tracking_wrapper PIN 84: INST APBGpsBlock__GC0 PIN 1 TYPE 5
-INST tracking_wrapper PIN 85: INST APBGpsBlock__GC0 PIN 1 TYPE 5
-INST tracking_wrapper PIN 0: INST APBGpsBlock__GC0 PIN 149 TYPE 1 INST APBGpsBlock__GC0 PIN 150 TYPE 1 INST APBGpsBlock__GC0 PIN 151 TYPE 1 INST APBGpsBlock__GC0 PIN 152 TYPE 1 INST APBGpsBlock__GC0 PIN 153 TYPE 1 INST APBGpsBlock__GC0 PIN 154 TYPE 1 INST APBGpsBlock__GC0 PIN 155 TYPE 1 INST APBGpsBlock__GC0 PIN 156 TYPE 1 INST APBGpsBlock__GC0 PIN 157 TYPE 1 GENOME tracking_wrapper PIN 0
-INST NON_GENOME PIN 55: INST VCU118RocketSystem__GC0 PIN 79 TYPE 3 INST DCache PIN 336 TYPE 4 INST RocketTile__GCB0 PIN 1112 TYPE 4 INST FPU__GB2 PIN 311 TYPE 4 INST FPU__GB1 PIN 322 TYPE 4 INST FPU__GB0 PIN 301 TYPE 4 INST TilePRCIDomain__GC0 PIN 406 TYPE 4
-INST NON_GENOME PIN 56: INST VCU118RocketSystem__GC0 PIN 80 TYPE 3 INST DCache PIN 337 TYPE 4 INST RocketTile__GCB0 PIN 1113 TYPE 4 INST FPU__GB2 PIN 310 TYPE 4 INST FPU__GB1 PIN 323 TYPE 4 INST TilePRCIDomain__GC0 PIN 407 TYPE 4
-INST RocketTile__GCB0 PIN 1244: INST TilePRCIDomain__GC0 PIN 7 TYPE 5
-INST RocketTile__GCB0 PIN 1245: INST TilePRCIDomain__GC0 PIN 8 TYPE 5
-INST RocketTile__GCB0 PIN 1251: INST TilePRCIDomain__GC0 PIN 14 TYPE 5
-INST TilePRCIDomain__GC0 PIN 5: INST RocketTile__GCB0 PIN 3 TYPE 3 INST DCache PIN 341 TYPE 4
-INST TilePRCIDomain__GC0 PIN 6: INST RocketTile__GCB0 PIN 4 TYPE 3 INST DCache PIN 342 TYPE 4
-INST TilePRCIDomain__GC0 PIN 9: INST RocketTile__GCB0 PIN 5 TYPE 3 INST DCache PIN 343 TYPE 4
-INST TilePRCIDomain__GC0 PIN 10: INST RocketTile__GCB0 PIN 6 TYPE 3 INST DCache PIN 344 TYPE 4
-INST TilePRCIDomain__GC0 PIN 11: INST RocketTile__GCB0 PIN 7 TYPE 3 INST DCache PIN 345 TYPE 4
-INST TilePRCIDomain__GC0 PIN 12: INST RocketTile__GCB0 PIN 8 TYPE 3 INST DCache PIN 346 TYPE 4
-INST TilePRCIDomain__GC0 PIN 16: INST RocketTile__GCB0 PIN 10 TYPE 3 INST DCache PIN 348 TYPE 4
-INST TilePRCIDomain__GC0 PIN 17: INST RocketTile__GCB0 PIN 11 TYPE 3 INST DCache PIN 349 TYPE 4
-INST TilePRCIDomain__GC0 PIN 18: INST RocketTile__GCB0 PIN 12 TYPE 3 INST DCache PIN 350 TYPE 4
-INST TilePRCIDomain__GC0 PIN 19: INST RocketTile__GCB0 PIN 13 TYPE 3 INST DCache PIN 351 TYPE 4
-INST TilePRCIDomain__GC0 PIN 20: INST RocketTile__GCB0 PIN 14 TYPE 3 INST DCache PIN 352 TYPE 4
-INST TilePRCIDomain__GC0 PIN 21: INST RocketTile__GCB0 PIN 15 TYPE 3 INST DCache PIN 353 TYPE 4
-INST TilePRCIDomain__GC0 PIN 22: INST RocketTile__GCB0 PIN 16 TYPE 3 INST DCache PIN 354 TYPE 4
-INST TilePRCIDomain__GC0 PIN 23: INST RocketTile__GCB0 PIN 17 TYPE 3 INST DCache PIN 355 TYPE 4
-INST TilePRCIDomain__GC0 PIN 24: INST RocketTile__GCB0 PIN 18 TYPE 3 INST DCache PIN 356 TYPE 4
-INST TilePRCIDomain__GC0 PIN 25: INST RocketTile__GCB0 PIN 19 TYPE 3 INST DCache PIN 357 TYPE 4
-INST TilePRCIDomain__GC0 PIN 26: INST RocketTile__GCB0 PIN 20 TYPE 3 INST DCache PIN 358 TYPE 4
-INST TilePRCIDomain__GC0 PIN 27: INST RocketTile__GCB0 PIN 21 TYPE 3 INST DCache PIN 359 TYPE 4
-INST TilePRCIDomain__GC0 PIN 28: INST RocketTile__GCB0 PIN 22 TYPE 3 INST DCache PIN 360 TYPE 4
-INST TilePRCIDomain__GC0 PIN 29: INST RocketTile__GCB0 PIN 23 TYPE 3 INST DCache PIN 361 TYPE 4
-INST TilePRCIDomain__GC0 PIN 30: INST RocketTile__GCB0 PIN 24 TYPE 3 INST DCache PIN 362 TYPE 4
-INST TilePRCIDomain__GC0 PIN 31: INST RocketTile__GCB0 PIN 25 TYPE 3 INST DCache PIN 363 TYPE 4
-INST TilePRCIDomain__GC0 PIN 32: INST RocketTile__GCB0 PIN 26 TYPE 3 INST DCache PIN 364 TYPE 4
-INST TilePRCIDomain__GC0 PIN 33: INST RocketTile__GCB0 PIN 27 TYPE 3 INST DCache PIN 365 TYPE 4
-INST TilePRCIDomain__GC0 PIN 34: INST RocketTile__GCB0 PIN 28 TYPE 3 INST DCache PIN 366 TYPE 4
-INST TilePRCIDomain__GC0 PIN 35: INST RocketTile__GCB0 PIN 29 TYPE 3 INST DCache PIN 367 TYPE 4
-INST TilePRCIDomain__GC0 PIN 36: INST RocketTile__GCB0 PIN 30 TYPE 3 INST DCache PIN 368 TYPE 4
-INST TilePRCIDomain__GC0 PIN 37: INST RocketTile__GCB0 PIN 31 TYPE 3 INST DCache PIN 369 TYPE 4
-INST TilePRCIDomain__GC0 PIN 38: INST RocketTile__GCB0 PIN 32 TYPE 3 INST DCache PIN 370 TYPE 4
-INST TilePRCIDomain__GC0 PIN 39: INST RocketTile__GCB0 PIN 33 TYPE 3 INST DCache PIN 371 TYPE 4
-INST TilePRCIDomain__GC0 PIN 40: INST RocketTile__GCB0 PIN 34 TYPE 3 INST DCache PIN 372 TYPE 4
-INST TilePRCIDomain__GC0 PIN 41: INST RocketTile__GCB0 PIN 35 TYPE 3 INST DCache PIN 373 TYPE 4
-INST TilePRCIDomain__GC0 PIN 42: INST RocketTile__GCB0 PIN 36 TYPE 3 INST DCache PIN 374 TYPE 4
-INST TilePRCIDomain__GC0 PIN 43: INST RocketTile__GCB0 PIN 37 TYPE 3 INST DCache PIN 375 TYPE 4
-INST TilePRCIDomain__GC0 PIN 44: INST RocketTile__GCB0 PIN 38 TYPE 3 INST DCache PIN 376 TYPE 4
-INST TilePRCIDomain__GC0 PIN 45: INST RocketTile__GCB0 PIN 39 TYPE 3 INST DCache PIN 377 TYPE 4
-INST TilePRCIDomain__GC0 PIN 46: INST RocketTile__GCB0 PIN 40 TYPE 3 INST DCache PIN 378 TYPE 4
-INST TilePRCIDomain__GC0 PIN 47: INST RocketTile__GCB0 PIN 41 TYPE 3 INST DCache PIN 379 TYPE 4
-INST TilePRCIDomain__GC0 PIN 48: INST RocketTile__GCB0 PIN 42 TYPE 3 INST DCache PIN 380 TYPE 4
-INST TilePRCIDomain__GC0 PIN 49: INST RocketTile__GCB0 PIN 43 TYPE 3 INST DCache PIN 381 TYPE 4
-INST TilePRCIDomain__GC0 PIN 50: INST RocketTile__GCB0 PIN 44 TYPE 3 INST DCache PIN 382 TYPE 4
-INST TilePRCIDomain__GC0 PIN 51: INST RocketTile__GCB0 PIN 45 TYPE 3 INST DCache PIN 383 TYPE 4
-INST TilePRCIDomain__GC0 PIN 52: INST RocketTile__GCB0 PIN 46 TYPE 3 INST DCache PIN 384 TYPE 4
-INST TilePRCIDomain__GC0 PIN 53: INST RocketTile__GCB0 PIN 47 TYPE 3 INST DCache PIN 385 TYPE 4
-INST TilePRCIDomain__GC0 PIN 54: INST RocketTile__GCB0 PIN 48 TYPE 3 INST DCache PIN 386 TYPE 4
-INST TilePRCIDomain__GC0 PIN 55: INST RocketTile__GCB0 PIN 49 TYPE 3 INST DCache PIN 387 TYPE 4
-INST TilePRCIDomain__GC0 PIN 56: INST RocketTile__GCB0 PIN 50 TYPE 3 INST DCache PIN 388 TYPE 4
-INST TilePRCIDomain__GC0 PIN 57: INST RocketTile__GCB0 PIN 51 TYPE 3 INST DCache PIN 389 TYPE 4
-INST TilePRCIDomain__GC0 PIN 58: INST RocketTile__GCB0 PIN 52 TYPE 3 INST DCache PIN 390 TYPE 4
-INST TilePRCIDomain__GC0 PIN 59: INST RocketTile__GCB0 PIN 53 TYPE 3 INST DCache PIN 391 TYPE 4
-INST TilePRCIDomain__GC0 PIN 60: INST RocketTile__GCB0 PIN 54 TYPE 3 INST DCache PIN 392 TYPE 4
-INST TilePRCIDomain__GC0 PIN 61: INST RocketTile__GCB0 PIN 55 TYPE 3 INST DCache PIN 393 TYPE 4
-INST TilePRCIDomain__GC0 PIN 62: INST RocketTile__GCB0 PIN 56 TYPE 3 INST DCache PIN 394 TYPE 4
-INST TilePRCIDomain__GC0 PIN 63: INST RocketTile__GCB0 PIN 57 TYPE 3 INST DCache PIN 395 TYPE 4
-INST TilePRCIDomain__GC0 PIN 64: INST RocketTile__GCB0 PIN 58 TYPE 3 INST DCache PIN 396 TYPE 4
-INST TilePRCIDomain__GC0 PIN 65: INST RocketTile__GCB0 PIN 59 TYPE 3 INST DCache PIN 397 TYPE 4
-INST TilePRCIDomain__GC0 PIN 66: INST RocketTile__GCB0 PIN 60 TYPE 3 INST DCache PIN 398 TYPE 4
-INST TilePRCIDomain__GC0 PIN 67: INST RocketTile__GCB0 PIN 61 TYPE 3 INST DCache PIN 399 TYPE 4
-INST TilePRCIDomain__GC0 PIN 68: INST RocketTile__GCB0 PIN 62 TYPE 3 INST DCache PIN 400 TYPE 4
-INST TilePRCIDomain__GC0 PIN 69: INST RocketTile__GCB0 PIN 63 TYPE 3 INST DCache PIN 401 TYPE 4
-INST TilePRCIDomain__GC0 PIN 70: INST RocketTile__GCB0 PIN 64 TYPE 3 INST DCache PIN 402 TYPE 4
-INST TilePRCIDomain__GC0 PIN 71: INST RocketTile__GCB0 PIN 65 TYPE 3 INST DCache PIN 403 TYPE 4
-INST TilePRCIDomain__GC0 PIN 72: INST RocketTile__GCB0 PIN 66 TYPE 3 INST DCache PIN 404 TYPE 4
-INST TilePRCIDomain__GC0 PIN 73: INST RocketTile__GCB0 PIN 67 TYPE 3 INST DCache PIN 405 TYPE 4
-INST TilePRCIDomain__GC0 PIN 74: INST RocketTile__GCB0 PIN 68 TYPE 3 INST DCache PIN 406 TYPE 4
-INST TilePRCIDomain__GC0 PIN 75: INST RocketTile__GCB0 PIN 69 TYPE 3 INST DCache PIN 407 TYPE 4
-INST TilePRCIDomain__GC0 PIN 76: INST RocketTile__GCB0 PIN 70 TYPE 3 INST DCache PIN 408 TYPE 4
-INST TilePRCIDomain__GC0 PIN 77: INST RocketTile__GCB0 PIN 71 TYPE 3 INST DCache PIN 409 TYPE 4
-INST TilePRCIDomain__GC0 PIN 78: INST RocketTile__GCB0 PIN 72 TYPE 3 INST DCache PIN 410 TYPE 4
-INST TilePRCIDomain__GC0 PIN 79: INST RocketTile__GCB0 PIN 73 TYPE 3 INST DCache PIN 411 TYPE 4
-INST RocketTile__GCB0 PIN 324: INST RocketTile__GCB0 PIN 325 TYPE 2 INST DCache PIN 463 TYPE 4
-INST RocketTile__GCB0 PIN 315: INST RocketTile__GCB0 PIN 326 TYPE 2 INST DCache PIN 464 TYPE 4
-INST RocketTile__GCB0 PIN 403: INST RocketTile__GCB0 PIN 465 TYPE 2 INST DCache PIN 603 TYPE 4
-INST RocketTile__GCB0 PIN 466: INST DCache PIN 604 TYPE 1 GENOME RocketTile__GCB0 PIN 466
-INST RocketTile__GCB0 PIN 467: INST DCache PIN 605 TYPE 1 GENOME RocketTile__GCB0 PIN 467
-INST RocketTile__GCB0 PIN 470: INST RocketTile__GCB0 PIN 532 TYPE 2 INST DCache PIN 670 TYPE 4
-INST RocketTile__GCB0 PIN 533: INST DCache PIN 671 TYPE 1 GENOME RocketTile__GCB0 PIN 533
-INST RocketTile__GCB0 PIN 534: INST DCache PIN 672 TYPE 1 GENOME RocketTile__GCB0 PIN 534
-INST RocketTile__GCB0 PIN 537: INST RocketTile__GCB0 PIN 599 TYPE 2 INST DCache PIN 737 TYPE 4
-INST RocketTile__GCB0 PIN 600: INST DCache PIN 738 TYPE 1 GENOME RocketTile__GCB0 PIN 600
-INST RocketTile__GCB0 PIN 601: INST DCache PIN 739 TYPE 1 GENOME RocketTile__GCB0 PIN 601
-INST RocketTile__GCB0 PIN 604: INST RocketTile__GCB0 PIN 666 TYPE 2 INST DCache PIN 804 TYPE 4
-INST RocketTile__GCB0 PIN 667: INST DCache PIN 805 TYPE 1 GENOME RocketTile__GCB0 PIN 667
-INST RocketTile__GCB0 PIN 668: INST DCache PIN 806 TYPE 1 GENOME RocketTile__GCB0 PIN 668
-INST RocketTile__GCB0 PIN 671: INST RocketTile__GCB0 PIN 733 TYPE 2 INST DCache PIN 871 TYPE 4
-INST RocketTile__GCB0 PIN 734: INST DCache PIN 872 TYPE 1 GENOME RocketTile__GCB0 PIN 734
-INST RocketTile__GCB0 PIN 735: INST DCache PIN 873 TYPE 1 GENOME RocketTile__GCB0 PIN 735
-INST RocketTile__GCB0 PIN 738: INST RocketTile__GCB0 PIN 800 TYPE 2 INST DCache PIN 938 TYPE 4
-INST RocketTile__GCB0 PIN 801: INST DCache PIN 939 TYPE 1 GENOME RocketTile__GCB0 PIN 801
-INST RocketTile__GCB0 PIN 802: INST DCache PIN 940 TYPE 1 GENOME RocketTile__GCB0 PIN 802
-INST RocketTile__GCB0 PIN 805: INST RocketTile__GCB0 PIN 867 TYPE 2 INST DCache PIN 1005 TYPE 4
-INST RocketTile__GCB0 PIN 868: INST DCache PIN 1006 TYPE 1 GENOME RocketTile__GCB0 PIN 868
-INST RocketTile__GCB0 PIN 869: INST DCache PIN 1007 TYPE 1 GENOME RocketTile__GCB0 PIN 869
-INST RocketTile__GCB0 PIN 872: INST RocketTile__GCB0 PIN 934 TYPE 2 INST DCache PIN 1072 TYPE 4
-INST RocketTile__GCB0 PIN 935: INST DCache PIN 1073 TYPE 1 GENOME RocketTile__GCB0 PIN 935
-INST RocketTile__GCB0 PIN 936: INST DCache PIN 1074 TYPE 1 GENOME RocketTile__GCB0 PIN 936
-INST FPU__GB2 PIN 317: INST FPU__GB1 PIN 163 TYPE 5
-INST FPU__GB2 PIN 323: INST FPU__GB1 PIN 137 TYPE 5
-INST FPU__GB2 PIN 393: INST FPU__GB1 PIN 1 TYPE 5
-INST FPU__GB2 PIN 171: INST FPU__GB1 PIN 525 TYPE 0 GENOME FPU__GB2 PIN 171
-INST FPU__GB2 PIN 172: INST FPU__GB1 PIN 526 TYPE 0 GENOME FPU__GB2 PIN 172
-INST FPU__GB2 PIN 173: INST FPU__GB1 PIN 527 TYPE 0 GENOME FPU__GB2 PIN 173
-INST FPU__GB2 PIN 174: INST FPU__GB1 PIN 528 TYPE 0 GENOME FPU__GB2 PIN 174
-INST FPU__GB2 PIN 306: INST FPU__GB1 PIN 531 TYPE 0 GENOME FPU__GB2 PIN 306
-INST FPU__GB2 PIN 307: INST FPU__GB1 PIN 532 TYPE 0 GENOME FPU__GB2 PIN 307
-INST FPU__GB2 PIN 308: INST FPU__GB1 PIN 533 TYPE 0 GENOME FPU__GB2 PIN 308
-INST RocketTile__GCB0 PIN 967: INST FPU__GB1 PIN 570 TYPE 1 GENOME RocketTile__GCB0 PIN 967
-INST RocketTile__GCB0 PIN 968: INST FPU__GB1 PIN 571 TYPE 1 GENOME RocketTile__GCB0 PIN 968
-INST DCache PIN 124: INST RocketTile__GCB0 PIN 1040 TYPE 3 INST FPU__GB1 PIN 641 TYPE 4
-INST DCache PIN 125: INST RocketTile__GCB0 PIN 1041 TYPE 3 INST FPU__GB1 PIN 642 TYPE 4
-INST DCache PIN 126: INST RocketTile__GCB0 PIN 1042 TYPE 3 INST FPU__GB1 PIN 643 TYPE 4
-INST DCache PIN 127: INST RocketTile__GCB0 PIN 1043 TYPE 3 INST FPU__GB1 PIN 644 TYPE 4
-INST DCache PIN 128: INST RocketTile__GCB0 PIN 1044 TYPE 3 INST FPU__GB1 PIN 645 TYPE 4
-INST DCache PIN 199: INST RocketTile__GCB0 PIN 1045 TYPE 3 INST FPU__GB1 PIN 646 TYPE 4
-INST DCache PIN 200: INST RocketTile__GCB0 PIN 1046 TYPE 3 INST FPU__GB1 PIN 647 TYPE 4
-INST DCache PIN 201: INST RocketTile__GCB0 PIN 1047 TYPE 3 INST FPU__GB1 PIN 648 TYPE 4
-INST DCache PIN 202: INST RocketTile__GCB0 PIN 1048 TYPE 3 INST FPU__GB1 PIN 649 TYPE 4
-INST DCache PIN 203: INST RocketTile__GCB0 PIN 1049 TYPE 3 INST FPU__GB1 PIN 650 TYPE 4
-INST DCache PIN 204: INST RocketTile__GCB0 PIN 1050 TYPE 3 INST FPU__GB1 PIN 651 TYPE 4
-INST DCache PIN 205: INST RocketTile__GCB0 PIN 1051 TYPE 3 INST FPU__GB1 PIN 652 TYPE 4
-INST DCache PIN 206: INST RocketTile__GCB0 PIN 1052 TYPE 3 INST FPU__GB1 PIN 653 TYPE 4
-INST DCache PIN 207: INST RocketTile__GCB0 PIN 1053 TYPE 3 INST FPU__GB1 PIN 654 TYPE 4
-INST DCache PIN 208: INST RocketTile__GCB0 PIN 1054 TYPE 3 INST FPU__GB1 PIN 655 TYPE 4
-INST DCache PIN 209: INST RocketTile__GCB0 PIN 1055 TYPE 3 INST FPU__GB1 PIN 656 TYPE 4
-INST DCache PIN 210: INST RocketTile__GCB0 PIN 1056 TYPE 3 INST FPU__GB1 PIN 657 TYPE 4
-INST DCache PIN 211: INST RocketTile__GCB0 PIN 1057 TYPE 3 INST FPU__GB1 PIN 658 TYPE 4
-INST DCache PIN 212: INST RocketTile__GCB0 PIN 1058 TYPE 3 INST FPU__GB1 PIN 659 TYPE 4
-INST DCache PIN 213: INST RocketTile__GCB0 PIN 1059 TYPE 3 INST FPU__GB1 PIN 660 TYPE 4
-INST DCache PIN 214: INST RocketTile__GCB0 PIN 1060 TYPE 3 INST FPU__GB1 PIN 661 TYPE 4
-INST DCache PIN 215: INST RocketTile__GCB0 PIN 1061 TYPE 3 INST FPU__GB1 PIN 662 TYPE 4
-INST DCache PIN 216: INST RocketTile__GCB0 PIN 1062 TYPE 3 INST FPU__GB1 PIN 663 TYPE 4
-INST DCache PIN 217: INST RocketTile__GCB0 PIN 1063 TYPE 3 INST FPU__GB1 PIN 664 TYPE 4
-INST DCache PIN 218: INST RocketTile__GCB0 PIN 1064 TYPE 3 INST FPU__GB1 PIN 665 TYPE 4
-INST DCache PIN 219: INST RocketTile__GCB0 PIN 1065 TYPE 3 INST FPU__GB1 PIN 666 TYPE 4
-INST DCache PIN 220: INST RocketTile__GCB0 PIN 1066 TYPE 3 INST FPU__GB1 PIN 667 TYPE 4
-INST DCache PIN 221: INST RocketTile__GCB0 PIN 1067 TYPE 3 INST FPU__GB1 PIN 668 TYPE 4
-INST DCache PIN 222: INST RocketTile__GCB0 PIN 1068 TYPE 3 INST FPU__GB1 PIN 669 TYPE 4
-INST DCache PIN 223: INST RocketTile__GCB0 PIN 1069 TYPE 3 INST FPU__GB1 PIN 670 TYPE 4
-INST DCache PIN 224: INST RocketTile__GCB0 PIN 1070 TYPE 3 INST FPU__GB1 PIN 671 TYPE 4
-INST DCache PIN 225: INST RocketTile__GCB0 PIN 1071 TYPE 3 INST FPU__GB1 PIN 672 TYPE 4
-INST DCache PIN 226: INST RocketTile__GCB0 PIN 1072 TYPE 3 INST FPU__GB1 PIN 673 TYPE 4
-INST DCache PIN 227: INST RocketTile__GCB0 PIN 1073 TYPE 3 INST FPU__GB1 PIN 674 TYPE 4
-INST DCache PIN 228: INST RocketTile__GCB0 PIN 1074 TYPE 3 INST FPU__GB1 PIN 675 TYPE 4
-INST DCache PIN 229: INST RocketTile__GCB0 PIN 1075 TYPE 3 INST FPU__GB1 PIN 676 TYPE 4
-INST DCache PIN 230: INST RocketTile__GCB0 PIN 1076 TYPE 3 INST FPU__GB1 PIN 677 TYPE 4
-INST DCache PIN 231: INST RocketTile__GCB0 PIN 1077 TYPE 3 INST FPU__GB1 PIN 678 TYPE 4
-INST DCache PIN 232: INST RocketTile__GCB0 PIN 1078 TYPE 3 INST FPU__GB1 PIN 679 TYPE 4
-INST DCache PIN 233: INST RocketTile__GCB0 PIN 1079 TYPE 3 INST FPU__GB1 PIN 680 TYPE 4
-INST DCache PIN 234: INST RocketTile__GCB0 PIN 1080 TYPE 3 INST FPU__GB1 PIN 681 TYPE 4
-INST DCache PIN 235: INST RocketTile__GCB0 PIN 1081 TYPE 3 INST FPU__GB1 PIN 682 TYPE 4
-INST DCache PIN 236: INST RocketTile__GCB0 PIN 1082 TYPE 3 INST FPU__GB1 PIN 683 TYPE 4
-INST DCache PIN 237: INST RocketTile__GCB0 PIN 1083 TYPE 3 INST FPU__GB1 PIN 684 TYPE 4
-INST DCache PIN 238: INST RocketTile__GCB0 PIN 1084 TYPE 3 INST FPU__GB1 PIN 685 TYPE 4
-INST DCache PIN 239: INST RocketTile__GCB0 PIN 1085 TYPE 3 INST FPU__GB1 PIN 686 TYPE 4
-INST DCache PIN 240: INST RocketTile__GCB0 PIN 1086 TYPE 3 INST FPU__GB1 PIN 687 TYPE 4
-INST DCache PIN 241: INST RocketTile__GCB0 PIN 1087 TYPE 3 INST FPU__GB1 PIN 688 TYPE 4
-INST DCache PIN 242: INST RocketTile__GCB0 PIN 1088 TYPE 3 INST FPU__GB1 PIN 689 TYPE 4
-INST DCache PIN 243: INST RocketTile__GCB0 PIN 1089 TYPE 3 INST FPU__GB1 PIN 690 TYPE 4
-INST DCache PIN 244: INST RocketTile__GCB0 PIN 1090 TYPE 3 INST FPU__GB1 PIN 691 TYPE 4
-INST DCache PIN 245: INST RocketTile__GCB0 PIN 1091 TYPE 3 INST FPU__GB1 PIN 692 TYPE 4
-INST DCache PIN 246: INST RocketTile__GCB0 PIN 1092 TYPE 3 INST FPU__GB1 PIN 693 TYPE 4
-INST DCache PIN 247: INST RocketTile__GCB0 PIN 1093 TYPE 3 INST FPU__GB1 PIN 694 TYPE 4
-INST DCache PIN 248: INST RocketTile__GCB0 PIN 1094 TYPE 3 INST FPU__GB1 PIN 695 TYPE 4
-INST DCache PIN 249: INST RocketTile__GCB0 PIN 1095 TYPE 3 INST FPU__GB1 PIN 696 TYPE 4
-INST DCache PIN 250: INST RocketTile__GCB0 PIN 1096 TYPE 3 INST FPU__GB1 PIN 697 TYPE 4
-INST DCache PIN 251: INST RocketTile__GCB0 PIN 1097 TYPE 3 INST FPU__GB1 PIN 698 TYPE 4
-INST DCache PIN 252: INST RocketTile__GCB0 PIN 1098 TYPE 3 INST FPU__GB1 PIN 699 TYPE 4
-INST DCache PIN 253: INST RocketTile__GCB0 PIN 1099 TYPE 3 INST FPU__GB1 PIN 700 TYPE 4
-INST DCache PIN 254: INST RocketTile__GCB0 PIN 1100 TYPE 3 INST FPU__GB1 PIN 701 TYPE 4
-INST DCache PIN 255: INST RocketTile__GCB0 PIN 1101 TYPE 3 INST FPU__GB1 PIN 702 TYPE 4
-INST DCache PIN 256: INST RocketTile__GCB0 PIN 1102 TYPE 3 INST FPU__GB1 PIN 703 TYPE 4
-INST DCache PIN 257: INST RocketTile__GCB0 PIN 1103 TYPE 3 INST FPU__GB1 PIN 704 TYPE 4
-INST DCache PIN 258: INST RocketTile__GCB0 PIN 1104 TYPE 3 INST FPU__GB1 PIN 705 TYPE 4
-INST DCache PIN 259: INST RocketTile__GCB0 PIN 1105 TYPE 3 INST FPU__GB1 PIN 706 TYPE 4
-INST DCache PIN 260: INST RocketTile__GCB0 PIN 1106 TYPE 3 INST FPU__GB1 PIN 707 TYPE 4
-INST DCache PIN 261: INST RocketTile__GCB0 PIN 1107 TYPE 3 INST FPU__GB1 PIN 708 TYPE 4
-INST DCache PIN 262: INST RocketTile__GCB0 PIN 1108 TYPE 3 INST FPU__GB1 PIN 709 TYPE 4
-INST DCache PIN 132: INST RocketTile__GCB0 PIN 1039 TYPE 3 INST FPU__GB1 PIN 710 TYPE 4
-INST RocketTile__GCB0 PIN 198: INST TilePRCIDomain__GC0 PIN 531 TYPE 0 GENOME RocketTile__GCB0 PIN 198
-INST RocketTile__GCB0 PIN 202: INST TilePRCIDomain__GC0 PIN 732 TYPE 0 GENOME RocketTile__GCB0 PIN 202
-INST RocketTile__GCB0 PIN 203: INST TilePRCIDomain__GC0 PIN 733 TYPE 0 GENOME RocketTile__GCB0 PIN 203
-INST VCU118RocketSystem__GC0 PIN 331: INST NON_GENOME PIN 34 TYPE 0 GENOME VCU118RocketSystem__GC0 PIN 331
-INST VCU118RocketSystem__GC0 PIN 334: INST VCU118RocketSystem__GC0 PIN 335 TYPE 2 INST NON_GENOME PIN 46 TYPE 4 INST VCU118RocketSystem__GC0 PIN 336 TYPE 2 INST NON_GENOME PIN 47 TYPE 4
-INST RocketTile__GCB0 PIN 2: GENOME RocketTile__GCB0 PIN 2
-INST RocketTile__GCB0 PIN 3: GENOME RocketTile__GCB0 PIN 3
-INST RocketTile__GCB0 PIN 4: GENOME RocketTile__GCB0 PIN 4
-INST RocketTile__GCB0 PIN 5: GENOME RocketTile__GCB0 PIN 5
-INST RocketTile__GCB0 PIN 6: GENOME RocketTile__GCB0 PIN 6
-INST RocketTile__GCB0 PIN 7: GENOME RocketTile__GCB0 PIN 7
-INST RocketTile__GCB0 PIN 8: GENOME RocketTile__GCB0 PIN 8
-INST RocketTile__GCB0 PIN 9: GENOME RocketTile__GCB0 PIN 9
-INST RocketTile__GCB0 PIN 10: GENOME RocketTile__GCB0 PIN 10
-INST RocketTile__GCB0 PIN 11: GENOME RocketTile__GCB0 PIN 11
-INST RocketTile__GCB0 PIN 12: GENOME RocketTile__GCB0 PIN 12
-INST RocketTile__GCB0 PIN 13: GENOME RocketTile__GCB0 PIN 13
-INST RocketTile__GCB0 PIN 14: GENOME RocketTile__GCB0 PIN 14
-INST RocketTile__GCB0 PIN 15: GENOME RocketTile__GCB0 PIN 15
-INST RocketTile__GCB0 PIN 16: GENOME RocketTile__GCB0 PIN 16
-INST RocketTile__GCB0 PIN 17: GENOME RocketTile__GCB0 PIN 17
-INST RocketTile__GCB0 PIN 18: GENOME RocketTile__GCB0 PIN 18
-INST RocketTile__GCB0 PIN 19: GENOME RocketTile__GCB0 PIN 19
-INST RocketTile__GCB0 PIN 20: GENOME RocketTile__GCB0 PIN 20
-INST RocketTile__GCB0 PIN 21: GENOME RocketTile__GCB0 PIN 21
-INST RocketTile__GCB0 PIN 22: GENOME RocketTile__GCB0 PIN 22
-INST RocketTile__GCB0 PIN 23: GENOME RocketTile__GCB0 PIN 23
-INST RocketTile__GCB0 PIN 24: GENOME RocketTile__GCB0 PIN 24
-INST RocketTile__GCB0 PIN 25: GENOME RocketTile__GCB0 PIN 25
-INST RocketTile__GCB0 PIN 26: GENOME RocketTile__GCB0 PIN 26
-INST RocketTile__GCB0 PIN 27: GENOME RocketTile__GCB0 PIN 27
-INST RocketTile__GCB0 PIN 28: GENOME RocketTile__GCB0 PIN 28
-INST RocketTile__GCB0 PIN 29: GENOME RocketTile__GCB0 PIN 29
-INST RocketTile__GCB0 PIN 30: GENOME RocketTile__GCB0 PIN 30
-INST RocketTile__GCB0 PIN 31: GENOME RocketTile__GCB0 PIN 31
-INST RocketTile__GCB0 PIN 32: GENOME RocketTile__GCB0 PIN 32
-INST RocketTile__GCB0 PIN 33: GENOME RocketTile__GCB0 PIN 33
-INST RocketTile__GCB0 PIN 34: GENOME RocketTile__GCB0 PIN 34
-INST RocketTile__GCB0 PIN 35: GENOME RocketTile__GCB0 PIN 35
-INST RocketTile__GCB0 PIN 36: GENOME RocketTile__GCB0 PIN 36
-INST RocketTile__GCB0 PIN 37: GENOME RocketTile__GCB0 PIN 37
-INST RocketTile__GCB0 PIN 38: GENOME RocketTile__GCB0 PIN 38
-INST RocketTile__GCB0 PIN 39: GENOME RocketTile__GCB0 PIN 39
-INST RocketTile__GCB0 PIN 40: GENOME RocketTile__GCB0 PIN 40
-INST RocketTile__GCB0 PIN 41: GENOME RocketTile__GCB0 PIN 41
-INST RocketTile__GCB0 PIN 42: GENOME RocketTile__GCB0 PIN 42
-INST RocketTile__GCB0 PIN 43: GENOME RocketTile__GCB0 PIN 43
-INST RocketTile__GCB0 PIN 44: GENOME RocketTile__GCB0 PIN 44
-INST RocketTile__GCB0 PIN 45: GENOME RocketTile__GCB0 PIN 45
-INST RocketTile__GCB0 PIN 46: GENOME RocketTile__GCB0 PIN 46
-INST RocketTile__GCB0 PIN 47: GENOME RocketTile__GCB0 PIN 47
-INST RocketTile__GCB0 PIN 48: GENOME RocketTile__GCB0 PIN 48
-INST RocketTile__GCB0 PIN 49: GENOME RocketTile__GCB0 PIN 49
-INST RocketTile__GCB0 PIN 50: GENOME RocketTile__GCB0 PIN 50
-INST RocketTile__GCB0 PIN 51: GENOME RocketTile__GCB0 PIN 51
-INST RocketTile__GCB0 PIN 52: GENOME RocketTile__GCB0 PIN 52
-INST RocketTile__GCB0 PIN 53: GENOME RocketTile__GCB0 PIN 53
-INST RocketTile__GCB0 PIN 54: GENOME RocketTile__GCB0 PIN 54
-INST RocketTile__GCB0 PIN 55: GENOME RocketTile__GCB0 PIN 55
-INST RocketTile__GCB0 PIN 56: GENOME RocketTile__GCB0 PIN 56
-INST RocketTile__GCB0 PIN 57: GENOME RocketTile__GCB0 PIN 57
-INST RocketTile__GCB0 PIN 58: GENOME RocketTile__GCB0 PIN 58
-INST RocketTile__GCB0 PIN 59: GENOME RocketTile__GCB0 PIN 59
-INST RocketTile__GCB0 PIN 60: GENOME RocketTile__GCB0 PIN 60
-INST RocketTile__GCB0 PIN 61: GENOME RocketTile__GCB0 PIN 61
-INST RocketTile__GCB0 PIN 62: GENOME RocketTile__GCB0 PIN 62
-INST RocketTile__GCB0 PIN 63: GENOME RocketTile__GCB0 PIN 63
-INST RocketTile__GCB0 PIN 64: GENOME RocketTile__GCB0 PIN 64
-INST RocketTile__GCB0 PIN 65: GENOME RocketTile__GCB0 PIN 65
-INST RocketTile__GCB0 PIN 66: GENOME RocketTile__GCB0 PIN 66
-INST RocketTile__GCB0 PIN 67: GENOME RocketTile__GCB0 PIN 67
-INST RocketTile__GCB0 PIN 68: GENOME RocketTile__GCB0 PIN 68
-INST RocketTile__GCB0 PIN 69: GENOME RocketTile__GCB0 PIN 69
-INST RocketTile__GCB0 PIN 70: GENOME RocketTile__GCB0 PIN 70
-INST RocketTile__GCB0 PIN 71: GENOME RocketTile__GCB0 PIN 71
-INST RocketTile__GCB0 PIN 72: GENOME RocketTile__GCB0 PIN 72
-INST RocketTile__GCB0 PIN 73: GENOME RocketTile__GCB0 PIN 73
-INST RocketTile__GCB0 PIN 74: GENOME RocketTile__GCB0 PIN 74
-INST RocketTile__GCB0 PIN 325: GENOME RocketTile__GCB0 PIN 325
-INST RocketTile__GCB0 PIN 326: GENOME RocketTile__GCB0 PIN 326
-INST RocketTile__GCB0 PIN 465: GENOME RocketTile__GCB0 PIN 465
-INST RocketTile__GCB0 PIN 532: GENOME RocketTile__GCB0 PIN 532
-INST RocketTile__GCB0 PIN 599: GENOME RocketTile__GCB0 PIN 599
-INST RocketTile__GCB0 PIN 666: GENOME RocketTile__GCB0 PIN 666
-INST RocketTile__GCB0 PIN 733: GENOME RocketTile__GCB0 PIN 733
-INST RocketTile__GCB0 PIN 800: GENOME RocketTile__GCB0 PIN 800
-INST RocketTile__GCB0 PIN 867: GENOME RocketTile__GCB0 PIN 867
-INST RocketTile__GCB0 PIN 934: GENOME RocketTile__GCB0 PIN 934
-INST RocketTile__GCB0 PIN 1037: GENOME RocketTile__GCB0 PIN 1037
-INST RocketTile__GCB0 PIN 1038: GENOME RocketTile__GCB0 PIN 1038
-INST RocketTile__GCB0 PIN 1039: GENOME RocketTile__GCB0 PIN 1039
-INST RocketTile__GCB0 PIN 1040: GENOME RocketTile__GCB0 PIN 1040
-INST RocketTile__GCB0 PIN 1041: GENOME RocketTile__GCB0 PIN 1041
-INST RocketTile__GCB0 PIN 1042: GENOME RocketTile__GCB0 PIN 1042
-INST RocketTile__GCB0 PIN 1043: GENOME RocketTile__GCB0 PIN 1043
-INST RocketTile__GCB0 PIN 1044: GENOME RocketTile__GCB0 PIN 1044
-INST RocketTile__GCB0 PIN 1045: GENOME RocketTile__GCB0 PIN 1045
-INST RocketTile__GCB0 PIN 1046: GENOME RocketTile__GCB0 PIN 1046
-INST RocketTile__GCB0 PIN 1047: GENOME RocketTile__GCB0 PIN 1047
-INST RocketTile__GCB0 PIN 1048: GENOME RocketTile__GCB0 PIN 1048
-INST RocketTile__GCB0 PIN 1049: GENOME RocketTile__GCB0 PIN 1049
-INST RocketTile__GCB0 PIN 1050: GENOME RocketTile__GCB0 PIN 1050
-INST RocketTile__GCB0 PIN 1051: GENOME RocketTile__GCB0 PIN 1051
-INST RocketTile__GCB0 PIN 1052: GENOME RocketTile__GCB0 PIN 1052
-INST RocketTile__GCB0 PIN 1053: GENOME RocketTile__GCB0 PIN 1053
-INST RocketTile__GCB0 PIN 1054: GENOME RocketTile__GCB0 PIN 1054
-INST RocketTile__GCB0 PIN 1055: GENOME RocketTile__GCB0 PIN 1055
-INST RocketTile__GCB0 PIN 1056: GENOME RocketTile__GCB0 PIN 1056
-INST RocketTile__GCB0 PIN 1057: GENOME RocketTile__GCB0 PIN 1057
-INST RocketTile__GCB0 PIN 1058: GENOME RocketTile__GCB0 PIN 1058
-INST RocketTile__GCB0 PIN 1059: GENOME RocketTile__GCB0 PIN 1059
-INST RocketTile__GCB0 PIN 1060: GENOME RocketTile__GCB0 PIN 1060
-INST RocketTile__GCB0 PIN 1061: GENOME RocketTile__GCB0 PIN 1061
-INST RocketTile__GCB0 PIN 1062: GENOME RocketTile__GCB0 PIN 1062
-INST RocketTile__GCB0 PIN 1063: GENOME RocketTile__GCB0 PIN 1063
-INST RocketTile__GCB0 PIN 1064: GENOME RocketTile__GCB0 PIN 1064
-INST RocketTile__GCB0 PIN 1065: GENOME RocketTile__GCB0 PIN 1065
-INST RocketTile__GCB0 PIN 1066: GENOME RocketTile__GCB0 PIN 1066
-INST RocketTile__GCB0 PIN 1067: GENOME RocketTile__GCB0 PIN 1067
-INST RocketTile__GCB0 PIN 1068: GENOME RocketTile__GCB0 PIN 1068
-INST RocketTile__GCB0 PIN 1069: GENOME RocketTile__GCB0 PIN 1069
-INST RocketTile__GCB0 PIN 1070: GENOME RocketTile__GCB0 PIN 1070
-INST RocketTile__GCB0 PIN 1071: GENOME RocketTile__GCB0 PIN 1071
-INST RocketTile__GCB0 PIN 1072: GENOME RocketTile__GCB0 PIN 1072
-INST RocketTile__GCB0 PIN 1073: GENOME RocketTile__GCB0 PIN 1073
-INST RocketTile__GCB0 PIN 1074: GENOME RocketTile__GCB0 PIN 1074
-INST RocketTile__GCB0 PIN 1075: GENOME RocketTile__GCB0 PIN 1075
-INST RocketTile__GCB0 PIN 1076: GENOME RocketTile__GCB0 PIN 1076
-INST RocketTile__GCB0 PIN 1077: GENOME RocketTile__GCB0 PIN 1077
-INST RocketTile__GCB0 PIN 1078: GENOME RocketTile__GCB0 PIN 1078
-INST RocketTile__GCB0 PIN 1079: GENOME RocketTile__GCB0 PIN 1079
-INST RocketTile__GCB0 PIN 1080: GENOME RocketTile__GCB0 PIN 1080
-INST RocketTile__GCB0 PIN 1081: GENOME RocketTile__GCB0 PIN 1081
-INST RocketTile__GCB0 PIN 1082: GENOME RocketTile__GCB0 PIN 1082
-INST RocketTile__GCB0 PIN 1083: GENOME RocketTile__GCB0 PIN 1083
-INST RocketTile__GCB0 PIN 1084: GENOME RocketTile__GCB0 PIN 1084
-INST RocketTile__GCB0 PIN 1085: GENOME RocketTile__GCB0 PIN 1085
-INST RocketTile__GCB0 PIN 1086: GENOME RocketTile__GCB0 PIN 1086
-INST RocketTile__GCB0 PIN 1087: GENOME RocketTile__GCB0 PIN 1087
-INST RocketTile__GCB0 PIN 1088: GENOME RocketTile__GCB0 PIN 1088
-INST RocketTile__GCB0 PIN 1089: GENOME RocketTile__GCB0 PIN 1089
-INST RocketTile__GCB0 PIN 1090: GENOME RocketTile__GCB0 PIN 1090
-INST RocketTile__GCB0 PIN 1091: GENOME RocketTile__GCB0 PIN 1091
-INST RocketTile__GCB0 PIN 1092: GENOME RocketTile__GCB0 PIN 1092
-INST RocketTile__GCB0 PIN 1093: GENOME RocketTile__GCB0 PIN 1093
-INST RocketTile__GCB0 PIN 1094: GENOME RocketTile__GCB0 PIN 1094
-INST RocketTile__GCB0 PIN 1095: GENOME RocketTile__GCB0 PIN 1095
-INST RocketTile__GCB0 PIN 1096: GENOME RocketTile__GCB0 PIN 1096
-INST RocketTile__GCB0 PIN 1097: GENOME RocketTile__GCB0 PIN 1097
-INST RocketTile__GCB0 PIN 1098: GENOME RocketTile__GCB0 PIN 1098
-INST RocketTile__GCB0 PIN 1099: GENOME RocketTile__GCB0 PIN 1099
-INST RocketTile__GCB0 PIN 1100: GENOME RocketTile__GCB0 PIN 1100
-INST RocketTile__GCB0 PIN 1101: GENOME RocketTile__GCB0 PIN 1101
-INST RocketTile__GCB0 PIN 1102: GENOME RocketTile__GCB0 PIN 1102
-INST RocketTile__GCB0 PIN 1103: GENOME RocketTile__GCB0 PIN 1103
-INST RocketTile__GCB0 PIN 1104: GENOME RocketTile__GCB0 PIN 1104
-INST RocketTile__GCB0 PIN 1105: GENOME RocketTile__GCB0 PIN 1105
-INST RocketTile__GCB0 PIN 1106: GENOME RocketTile__GCB0 PIN 1106
-INST RocketTile__GCB0 PIN 1107: GENOME RocketTile__GCB0 PIN 1107
-INST RocketTile__GCB0 PIN 1108: GENOME RocketTile__GCB0 PIN 1108
-INST RocketTile__GCB0 PIN 1125: GENOME RocketTile__GCB0 PIN 1125
-INST RocketTile__GCB0 PIN 1126: GENOME RocketTile__GCB0 PIN 1126
-INST RocketTile__GCB0 PIN 1161: GENOME RocketTile__GCB0 PIN 1161
-INST RocketTile__GCB0 PIN 1162: GENOME RocketTile__GCB0 PIN 1162
-INST RocketTile__GCB0 PIN 1163: GENOME RocketTile__GCB0 PIN 1163
-INST RocketTile__GCB0 PIN 1164: GENOME RocketTile__GCB0 PIN 1164
-INST RocketTile__GCB0 PIN 1644: GENOME RocketTile__GCB0 PIN 1644
-INST RocketTile__GCB0 PIN 1645: GENOME RocketTile__GCB0 PIN 1645
-GENOME NON_GENOME PIN 1241: GENOME NON_GENOME PIN 2
-GENOME NON_GENOME PIN 2: GENOME NON_GENOME PIN 1241
-GENOME NON_GENOME PIN 1242: GENOME NON_GENOME PIN 3
-GENOME NON_GENOME PIN 3: GENOME NON_GENOME PIN 1242
-GENOME NON_GENOME PIN 1243: GENOME NON_GENOME PIN 4
-GENOME NON_GENOME PIN 4: GENOME NON_GENOME PIN 1243
-GENOME NON_GENOME PIN 1246: GENOME NON_GENOME PIN 5
-GENOME NON_GENOME PIN 5: GENOME NON_GENOME PIN 1246
-GENOME NON_GENOME PIN 1247: GENOME NON_GENOME PIN 6
-GENOME NON_GENOME PIN 6: GENOME NON_GENOME PIN 1247
-GENOME NON_GENOME PIN 1248: GENOME NON_GENOME PIN 7
-GENOME NON_GENOME PIN 7: GENOME NON_GENOME PIN 1248
-GENOME NON_GENOME PIN 1249: GENOME NON_GENOME PIN 8
-GENOME NON_GENOME PIN 8: GENOME NON_GENOME PIN 1249
-GENOME NON_GENOME PIN 1252: GENOME NON_GENOME PIN 9
-GENOME NON_GENOME PIN 9: GENOME NON_GENOME PIN 1252
-GENOME NON_GENOME PIN 1253: GENOME NON_GENOME PIN 10
-GENOME NON_GENOME PIN 10: GENOME NON_GENOME PIN 1253
-GENOME NON_GENOME PIN 1254: GENOME NON_GENOME PIN 11
-GENOME NON_GENOME PIN 11: GENOME NON_GENOME PIN 1254
-GENOME NON_GENOME PIN 1255: GENOME NON_GENOME PIN 12
-GENOME NON_GENOME PIN 12: GENOME NON_GENOME PIN 1255
-GENOME NON_GENOME PIN 1256: GENOME NON_GENOME PIN 13
-GENOME NON_GENOME PIN 13: GENOME NON_GENOME PIN 1256
-GENOME NON_GENOME PIN 1257: GENOME NON_GENOME PIN 14
-GENOME NON_GENOME PIN 14: GENOME NON_GENOME PIN 1257
-GENOME NON_GENOME PIN 1258: GENOME NON_GENOME PIN 15
-GENOME NON_GENOME PIN 15: GENOME NON_GENOME PIN 1258
-GENOME NON_GENOME PIN 1259: GENOME NON_GENOME PIN 16
-GENOME NON_GENOME PIN 16: GENOME NON_GENOME PIN 1259
-GENOME NON_GENOME PIN 1260: GENOME NON_GENOME PIN 17
-GENOME NON_GENOME PIN 17: GENOME NON_GENOME PIN 1260
-GENOME NON_GENOME PIN 1261: GENOME NON_GENOME PIN 18
-GENOME NON_GENOME PIN 18: GENOME NON_GENOME PIN 1261
-GENOME NON_GENOME PIN 1262: GENOME NON_GENOME PIN 19
-GENOME NON_GENOME PIN 19: GENOME NON_GENOME PIN 1262
-GENOME NON_GENOME PIN 1263: GENOME NON_GENOME PIN 20
-GENOME NON_GENOME PIN 20: GENOME NON_GENOME PIN 1263
-GENOME NON_GENOME PIN 1264: GENOME NON_GENOME PIN 21
-GENOME NON_GENOME PIN 21: GENOME NON_GENOME PIN 1264
-GENOME NON_GENOME PIN 1265: GENOME NON_GENOME PIN 22
-GENOME NON_GENOME PIN 22: GENOME NON_GENOME PIN 1265
-GENOME NON_GENOME PIN 1266: GENOME NON_GENOME PIN 23
-GENOME NON_GENOME PIN 23: GENOME NON_GENOME PIN 1266
-GENOME NON_GENOME PIN 1267: GENOME NON_GENOME PIN 24
-GENOME NON_GENOME PIN 24: GENOME NON_GENOME PIN 1267
-GENOME NON_GENOME PIN 1268: GENOME NON_GENOME PIN 25
-GENOME NON_GENOME PIN 25: GENOME NON_GENOME PIN 1268
-GENOME NON_GENOME PIN 1269: GENOME NON_GENOME PIN 26
-GENOME NON_GENOME PIN 26: GENOME NON_GENOME PIN 1269
-GENOME NON_GENOME PIN 1270: GENOME NON_GENOME PIN 27
-GENOME NON_GENOME PIN 27: GENOME NON_GENOME PIN 1270
-GENOME NON_GENOME PIN 1271: GENOME NON_GENOME PIN 28
-GENOME NON_GENOME PIN 28: GENOME NON_GENOME PIN 1271
-GENOME NON_GENOME PIN 1272: GENOME NON_GENOME PIN 29
-GENOME NON_GENOME PIN 29: GENOME NON_GENOME PIN 1272
-GENOME NON_GENOME PIN 1273: GENOME NON_GENOME PIN 30
-GENOME NON_GENOME PIN 30: GENOME NON_GENOME PIN 1273
-GENOME NON_GENOME PIN 1274: GENOME NON_GENOME PIN 31
-GENOME NON_GENOME PIN 31: GENOME NON_GENOME PIN 1274
-GENOME NON_GENOME PIN 1275: GENOME NON_GENOME PIN 32
-GENOME NON_GENOME PIN 32: GENOME NON_GENOME PIN 1275
-GENOME NON_GENOME PIN 1276: GENOME NON_GENOME PIN 33
-GENOME NON_GENOME PIN 33: GENOME NON_GENOME PIN 1276
-GENOME NON_GENOME PIN 1277: GENOME NON_GENOME PIN 34
-GENOME NON_GENOME PIN 34: GENOME NON_GENOME PIN 1277
-GENOME NON_GENOME PIN 1278: GENOME NON_GENOME PIN 35
-GENOME NON_GENOME PIN 35: GENOME NON_GENOME PIN 1278
-GENOME NON_GENOME PIN 1279: GENOME NON_GENOME PIN 36
-GENOME NON_GENOME PIN 36: GENOME NON_GENOME PIN 1279
-GENOME NON_GENOME PIN 1280: GENOME NON_GENOME PIN 37
-GENOME NON_GENOME PIN 37: GENOME NON_GENOME PIN 1280
-GENOME NON_GENOME PIN 1281: GENOME NON_GENOME PIN 38
-GENOME NON_GENOME PIN 38: GENOME NON_GENOME PIN 1281
-GENOME NON_GENOME PIN 1282: GENOME NON_GENOME PIN 39
-GENOME NON_GENOME PIN 39: GENOME NON_GENOME PIN 1282
-GENOME NON_GENOME PIN 1283: GENOME NON_GENOME PIN 40
-GENOME NON_GENOME PIN 40: GENOME NON_GENOME PIN 1283
-GENOME NON_GENOME PIN 1284: GENOME NON_GENOME PIN 41
-GENOME NON_GENOME PIN 41: GENOME NON_GENOME PIN 1284
-GENOME NON_GENOME PIN 1285: GENOME NON_GENOME PIN 42
-GENOME NON_GENOME PIN 42: GENOME NON_GENOME PIN 1285
-GENOME NON_GENOME PIN 1286: GENOME NON_GENOME PIN 43
-GENOME NON_GENOME PIN 43: GENOME NON_GENOME PIN 1286
-GENOME NON_GENOME PIN 1287: GENOME NON_GENOME PIN 44
-GENOME NON_GENOME PIN 44: GENOME NON_GENOME PIN 1287
-GENOME NON_GENOME PIN 1288: GENOME NON_GENOME PIN 45
-GENOME NON_GENOME PIN 45: GENOME NON_GENOME PIN 1288
-GENOME NON_GENOME PIN 1289: GENOME NON_GENOME PIN 46
-GENOME NON_GENOME PIN 46: GENOME NON_GENOME PIN 1289
-GENOME NON_GENOME PIN 1290: GENOME NON_GENOME PIN 47
-GENOME NON_GENOME PIN 47: GENOME NON_GENOME PIN 1290
-GENOME NON_GENOME PIN 1291: GENOME NON_GENOME PIN 48
-GENOME NON_GENOME PIN 48: GENOME NON_GENOME PIN 1291
-GENOME NON_GENOME PIN 1292: GENOME NON_GENOME PIN 49
-GENOME NON_GENOME PIN 49: GENOME NON_GENOME PIN 1292
-GENOME NON_GENOME PIN 1293: GENOME NON_GENOME PIN 50
-GENOME NON_GENOME PIN 50: GENOME NON_GENOME PIN 1293
-GENOME NON_GENOME PIN 1294: GENOME NON_GENOME PIN 51
-GENOME NON_GENOME PIN 51: GENOME NON_GENOME PIN 1294
-GENOME NON_GENOME PIN 1295: GENOME NON_GENOME PIN 52
-GENOME NON_GENOME PIN 52: GENOME NON_GENOME PIN 1295
-GENOME NON_GENOME PIN 1296: GENOME NON_GENOME PIN 53
-GENOME NON_GENOME PIN 53: GENOME NON_GENOME PIN 1296
-GENOME NON_GENOME PIN 1297: GENOME NON_GENOME PIN 54
-GENOME NON_GENOME PIN 54: GENOME NON_GENOME PIN 1297
-GENOME NON_GENOME PIN 1298: GENOME NON_GENOME PIN 55
-GENOME NON_GENOME PIN 55: GENOME NON_GENOME PIN 1298 GENOME NON_GENOME PIN 109
-GENOME NON_GENOME PIN 1299: GENOME NON_GENOME PIN 56
-GENOME NON_GENOME PIN 56: GENOME NON_GENOME PIN 1299
-GENOME NON_GENOME PIN 1300: GENOME NON_GENOME PIN 57
-GENOME NON_GENOME PIN 57: GENOME NON_GENOME PIN 1300
-GENOME NON_GENOME PIN 1301: GENOME NON_GENOME PIN 58
-GENOME NON_GENOME PIN 58: GENOME NON_GENOME PIN 1301
-GENOME NON_GENOME PIN 1302: GENOME NON_GENOME PIN 59
-GENOME NON_GENOME PIN 59: GENOME NON_GENOME PIN 1302
-GENOME NON_GENOME PIN 1303: GENOME NON_GENOME PIN 60
-GENOME NON_GENOME PIN 60: GENOME NON_GENOME PIN 1303
-GENOME NON_GENOME PIN 1304: GENOME NON_GENOME PIN 61
-GENOME NON_GENOME PIN 61: GENOME NON_GENOME PIN 1304
-GENOME NON_GENOME PIN 1305: GENOME NON_GENOME PIN 62
-GENOME NON_GENOME PIN 62: GENOME NON_GENOME PIN 1305
-GENOME NON_GENOME PIN 1306: GENOME NON_GENOME PIN 63
-GENOME NON_GENOME PIN 63: GENOME NON_GENOME PIN 1306
-GENOME NON_GENOME PIN 1307: GENOME NON_GENOME PIN 64
-GENOME NON_GENOME PIN 64: GENOME NON_GENOME PIN 1307
-GENOME NON_GENOME PIN 1308: GENOME NON_GENOME PIN 65
-GENOME NON_GENOME PIN 65: GENOME NON_GENOME PIN 1308
-GENOME NON_GENOME PIN 1309: GENOME NON_GENOME PIN 66
-GENOME NON_GENOME PIN 66: GENOME NON_GENOME PIN 1309
-GENOME NON_GENOME PIN 1310: GENOME NON_GENOME PIN 67
-GENOME NON_GENOME PIN 67: GENOME NON_GENOME PIN 1310
-GENOME NON_GENOME PIN 1311: GENOME NON_GENOME PIN 68
-GENOME NON_GENOME PIN 68: GENOME NON_GENOME PIN 1311
-GENOME NON_GENOME PIN 1312: GENOME NON_GENOME PIN 69
-GENOME NON_GENOME PIN 69: GENOME NON_GENOME PIN 1312
-GENOME NON_GENOME PIN 1313: GENOME NON_GENOME PIN 70
-GENOME NON_GENOME PIN 70: GENOME NON_GENOME PIN 1313
-GENOME NON_GENOME PIN 1314: GENOME NON_GENOME PIN 71
-GENOME NON_GENOME PIN 71: GENOME NON_GENOME PIN 1314
-GENOME NON_GENOME PIN 1315: GENOME NON_GENOME PIN 72
-GENOME NON_GENOME PIN 72: GENOME NON_GENOME PIN 1315
-GENOME NON_GENOME PIN 1316: GENOME NON_GENOME PIN 73
-GENOME NON_GENOME PIN 73: GENOME NON_GENOME PIN 1316
-GENOME NON_GENOME PIN 83: GENOME NON_GENOME PIN 119 GENOME NON_GENOME PIN 120
-GENOME NON_GENOME PIN 119: GENOME NON_GENOME PIN 83
-GENOME NON_GENOME PIN 120: GENOME NON_GENOME PIN 83
-GENOME NON_GENOME PIN 324: GENOME NON_GENOME PIN 315 GENOME NON_GENOME PIN 325
-GENOME NON_GENOME PIN 315: GENOME NON_GENOME PIN 324 GENOME NON_GENOME PIN 326
-GENOME NON_GENOME PIN 325: GENOME NON_GENOME PIN 324
-GENOME NON_GENOME PIN 326: GENOME NON_GENOME PIN 315
-GENOME NON_GENOME PIN 465: GENOME NON_GENOME PIN 403
-GENOME NON_GENOME PIN 470: GENOME NON_GENOME PIN 532
-GENOME NON_GENOME PIN 532: GENOME NON_GENOME PIN 470
-GENOME NON_GENOME PIN 537: GENOME NON_GENOME PIN 599
-GENOME NON_GENOME PIN 599: GENOME NON_GENOME PIN 537
-GENOME NON_GENOME PIN 604: GENOME NON_GENOME PIN 666
-GENOME NON_GENOME PIN 666: GENOME NON_GENOME PIN 604
-GENOME NON_GENOME PIN 671: GENOME NON_GENOME PIN 733
-GENOME NON_GENOME PIN 733: GENOME NON_GENOME PIN 671
-GENOME NON_GENOME PIN 738: GENOME NON_GENOME PIN 800
-GENOME NON_GENOME PIN 800: GENOME NON_GENOME PIN 738
-GENOME NON_GENOME PIN 867: GENOME NON_GENOME PIN 805
-GENOME NON_GENOME PIN 872: GENOME NON_GENOME PIN 934
-GENOME NON_GENOME PIN 934: GENOME NON_GENOME PIN 872
-GENOME NON_GENOME PIN 1445: GENOME NON_GENOME PIN 1038
-GENOME NON_GENOME PIN 1038: GENOME NON_GENOME PIN 1445
-GENOME NON_GENOME PIN 1446: GENOME NON_GENOME PIN 1039
-GENOME NON_GENOME PIN 1039: GENOME NON_GENOME PIN 1446
-GENOME NON_GENOME PIN 1438: GENOME NON_GENOME PIN 1040
-GENOME NON_GENOME PIN 1040: GENOME NON_GENOME PIN 1438
-GENOME NON_GENOME PIN 1439: GENOME NON_GENOME PIN 1041
-GENOME NON_GENOME PIN 1041: GENOME NON_GENOME PIN 1439
-GENOME NON_GENOME PIN 1440: GENOME NON_GENOME PIN 1042
-GENOME NON_GENOME PIN 1042: GENOME NON_GENOME PIN 1440
-GENOME NON_GENOME PIN 1441: GENOME NON_GENOME PIN 1043
-GENOME NON_GENOME PIN 1043: GENOME NON_GENOME PIN 1441
-GENOME NON_GENOME PIN 1442: GENOME NON_GENOME PIN 1044
-GENOME NON_GENOME PIN 1044: GENOME NON_GENOME PIN 1442
-GENOME NON_GENOME PIN 1513: GENOME NON_GENOME PIN 1045
-GENOME NON_GENOME PIN 1045: GENOME NON_GENOME PIN 1513
-GENOME NON_GENOME PIN 1514: GENOME NON_GENOME PIN 1046
-GENOME NON_GENOME PIN 1046: GENOME NON_GENOME PIN 1514
-GENOME NON_GENOME PIN 1515: GENOME NON_GENOME PIN 1047
-GENOME NON_GENOME PIN 1047: GENOME NON_GENOME PIN 1515
-GENOME NON_GENOME PIN 1516: GENOME NON_GENOME PIN 1048
-GENOME NON_GENOME PIN 1048: GENOME NON_GENOME PIN 1516
-GENOME NON_GENOME PIN 1517: GENOME NON_GENOME PIN 1049
-GENOME NON_GENOME PIN 1049: GENOME NON_GENOME PIN 1517
-GENOME NON_GENOME PIN 1518: GENOME NON_GENOME PIN 1050
-GENOME NON_GENOME PIN 1050: GENOME NON_GENOME PIN 1518
-GENOME NON_GENOME PIN 1519: GENOME NON_GENOME PIN 1051
-GENOME NON_GENOME PIN 1051: GENOME NON_GENOME PIN 1519
-GENOME NON_GENOME PIN 1520: GENOME NON_GENOME PIN 1052
-GENOME NON_GENOME PIN 1052: GENOME NON_GENOME PIN 1520
-GENOME NON_GENOME PIN 1521: GENOME NON_GENOME PIN 1053
-GENOME NON_GENOME PIN 1053: GENOME NON_GENOME PIN 1521
-GENOME NON_GENOME PIN 1522: GENOME NON_GENOME PIN 1054
-GENOME NON_GENOME PIN 1054: GENOME NON_GENOME PIN 1522
-GENOME NON_GENOME PIN 1523: GENOME NON_GENOME PIN 1055
-GENOME NON_GENOME PIN 1055: GENOME NON_GENOME PIN 1523
-GENOME NON_GENOME PIN 1524: GENOME NON_GENOME PIN 1056
-GENOME NON_GENOME PIN 1056: GENOME NON_GENOME PIN 1524
-GENOME NON_GENOME PIN 1525: GENOME NON_GENOME PIN 1057
-GENOME NON_GENOME PIN 1057: GENOME NON_GENOME PIN 1525
-GENOME NON_GENOME PIN 1526: GENOME NON_GENOME PIN 1058
-GENOME NON_GENOME PIN 1058: GENOME NON_GENOME PIN 1526
-GENOME NON_GENOME PIN 1527: GENOME NON_GENOME PIN 1059
-GENOME NON_GENOME PIN 1059: GENOME NON_GENOME PIN 1527
-GENOME NON_GENOME PIN 1528: GENOME NON_GENOME PIN 1060
-GENOME NON_GENOME PIN 1060: GENOME NON_GENOME PIN 1528
-GENOME NON_GENOME PIN 1529: GENOME NON_GENOME PIN 1061
-GENOME NON_GENOME PIN 1061: GENOME NON_GENOME PIN 1529
-GENOME NON_GENOME PIN 1530: GENOME NON_GENOME PIN 1062
-GENOME NON_GENOME PIN 1062: GENOME NON_GENOME PIN 1530
-GENOME NON_GENOME PIN 1531: GENOME NON_GENOME PIN 1063
-GENOME NON_GENOME PIN 1063: GENOME NON_GENOME PIN 1531
-GENOME NON_GENOME PIN 1532: GENOME NON_GENOME PIN 1064
-GENOME NON_GENOME PIN 1064: GENOME NON_GENOME PIN 1532
-GENOME NON_GENOME PIN 1533: GENOME NON_GENOME PIN 1065
-GENOME NON_GENOME PIN 1065: GENOME NON_GENOME PIN 1533
-GENOME NON_GENOME PIN 1534: GENOME NON_GENOME PIN 1066
-GENOME NON_GENOME PIN 1066: GENOME NON_GENOME PIN 1534
-GENOME NON_GENOME PIN 1535: GENOME NON_GENOME PIN 1067
-GENOME NON_GENOME PIN 1067: GENOME NON_GENOME PIN 1535
-GENOME NON_GENOME PIN 1536: GENOME NON_GENOME PIN 1068
-GENOME NON_GENOME PIN 1068: GENOME NON_GENOME PIN 1536
-GENOME NON_GENOME PIN 1537: GENOME NON_GENOME PIN 1069
-GENOME NON_GENOME PIN 1069: GENOME NON_GENOME PIN 1537
-GENOME NON_GENOME PIN 1538: GENOME NON_GENOME PIN 1070
-GENOME NON_GENOME PIN 1070: GENOME NON_GENOME PIN 1538
-GENOME NON_GENOME PIN 1539: GENOME NON_GENOME PIN 1071
-GENOME NON_GENOME PIN 1071: GENOME NON_GENOME PIN 1539
-GENOME NON_GENOME PIN 1540: GENOME NON_GENOME PIN 1072
-GENOME NON_GENOME PIN 1072: GENOME NON_GENOME PIN 1540 GENOME NON_GENOME PIN 1010
-GENOME NON_GENOME PIN 1541: GENOME NON_GENOME PIN 1073
-GENOME NON_GENOME PIN 1073: GENOME NON_GENOME PIN 1541
-GENOME NON_GENOME PIN 1542: GENOME NON_GENOME PIN 1074
-GENOME NON_GENOME PIN 1074: GENOME NON_GENOME PIN 1542
-GENOME NON_GENOME PIN 1543: GENOME NON_GENOME PIN 1075
-GENOME NON_GENOME PIN 1075: GENOME NON_GENOME PIN 1543
-GENOME NON_GENOME PIN 1544: GENOME NON_GENOME PIN 1076
-GENOME NON_GENOME PIN 1076: GENOME NON_GENOME PIN 1544
-GENOME NON_GENOME PIN 1545: GENOME NON_GENOME PIN 1077
-GENOME NON_GENOME PIN 1077: GENOME NON_GENOME PIN 1545
-GENOME NON_GENOME PIN 1546: GENOME NON_GENOME PIN 1078
-GENOME NON_GENOME PIN 1078: GENOME NON_GENOME PIN 1546
-GENOME NON_GENOME PIN 1547: GENOME NON_GENOME PIN 1079
-GENOME NON_GENOME PIN 1079: GENOME NON_GENOME PIN 1547
-GENOME NON_GENOME PIN 1548: GENOME NON_GENOME PIN 1080
-GENOME NON_GENOME PIN 1080: GENOME NON_GENOME PIN 1548
-GENOME NON_GENOME PIN 1549: GENOME NON_GENOME PIN 1081
-GENOME NON_GENOME PIN 1081: GENOME NON_GENOME PIN 1549
-GENOME NON_GENOME PIN 1550: GENOME NON_GENOME PIN 1082
-GENOME NON_GENOME PIN 1082: GENOME NON_GENOME PIN 1550
-GENOME NON_GENOME PIN 1551: GENOME NON_GENOME PIN 1083
-GENOME NON_GENOME PIN 1083: GENOME NON_GENOME PIN 1551
-GENOME NON_GENOME PIN 1552: GENOME NON_GENOME PIN 1084
-GENOME NON_GENOME PIN 1084: GENOME NON_GENOME PIN 1552
-GENOME NON_GENOME PIN 1553: GENOME NON_GENOME PIN 1085
-GENOME NON_GENOME PIN 1085: GENOME NON_GENOME PIN 1553
-GENOME NON_GENOME PIN 1554: GENOME NON_GENOME PIN 1086
-GENOME NON_GENOME PIN 1086: GENOME NON_GENOME PIN 1554
-GENOME NON_GENOME PIN 1555: GENOME NON_GENOME PIN 1087
-GENOME NON_GENOME PIN 1087: GENOME NON_GENOME PIN 1555
-GENOME NON_GENOME PIN 1556: GENOME NON_GENOME PIN 1088
-GENOME NON_GENOME PIN 1088: GENOME NON_GENOME PIN 1556
-GENOME NON_GENOME PIN 1557: GENOME NON_GENOME PIN 1089
-GENOME NON_GENOME PIN 1089: GENOME NON_GENOME PIN 1557
-GENOME NON_GENOME PIN 1558: GENOME NON_GENOME PIN 1090
-GENOME NON_GENOME PIN 1090: GENOME NON_GENOME PIN 1558
-GENOME NON_GENOME PIN 1559: GENOME NON_GENOME PIN 1091
-GENOME NON_GENOME PIN 1091: GENOME NON_GENOME PIN 1559
-GENOME NON_GENOME PIN 1560: GENOME NON_GENOME PIN 1092
-GENOME NON_GENOME PIN 1092: GENOME NON_GENOME PIN 1560
-GENOME NON_GENOME PIN 1561: GENOME NON_GENOME PIN 1093
-GENOME NON_GENOME PIN 1093: GENOME NON_GENOME PIN 1561
-GENOME NON_GENOME PIN 1562: GENOME NON_GENOME PIN 1094
-GENOME NON_GENOME PIN 1094: GENOME NON_GENOME PIN 1562
-GENOME NON_GENOME PIN 1563: GENOME NON_GENOME PIN 1095
-GENOME NON_GENOME PIN 1095: GENOME NON_GENOME PIN 1563
-GENOME NON_GENOME PIN 1564: GENOME NON_GENOME PIN 1096
-GENOME NON_GENOME PIN 1096: GENOME NON_GENOME PIN 1564
-GENOME NON_GENOME PIN 1565: GENOME NON_GENOME PIN 1097
-GENOME NON_GENOME PIN 1097: GENOME NON_GENOME PIN 1565
-GENOME NON_GENOME PIN 1566: GENOME NON_GENOME PIN 1098
-GENOME NON_GENOME PIN 1098: GENOME NON_GENOME PIN 1566
-GENOME NON_GENOME PIN 1567: GENOME NON_GENOME PIN 1099
-GENOME NON_GENOME PIN 1099: GENOME NON_GENOME PIN 1567
-GENOME NON_GENOME PIN 1568: GENOME NON_GENOME PIN 1100
-GENOME NON_GENOME PIN 1100: GENOME NON_GENOME PIN 1568
-GENOME NON_GENOME PIN 1569: GENOME NON_GENOME PIN 1101
-GENOME NON_GENOME PIN 1101: GENOME NON_GENOME PIN 1569
-GENOME NON_GENOME PIN 1570: GENOME NON_GENOME PIN 1102
-GENOME NON_GENOME PIN 1102: GENOME NON_GENOME PIN 1570
-GENOME NON_GENOME PIN 1571: GENOME NON_GENOME PIN 1103
-GENOME NON_GENOME PIN 1103: GENOME NON_GENOME PIN 1571
-GENOME NON_GENOME PIN 1572: GENOME NON_GENOME PIN 1104
-GENOME NON_GENOME PIN 1104: GENOME NON_GENOME PIN 1572
-GENOME NON_GENOME PIN 1573: GENOME NON_GENOME PIN 1105
-GENOME NON_GENOME PIN 1105: GENOME NON_GENOME PIN 1573
-GENOME NON_GENOME PIN 1574: GENOME NON_GENOME PIN 1106
-GENOME NON_GENOME PIN 1106: GENOME NON_GENOME PIN 1574
-GENOME NON_GENOME PIN 1575: GENOME NON_GENOME PIN 1107
-GENOME NON_GENOME PIN 1107: GENOME NON_GENOME PIN 1575
-GENOME NON_GENOME PIN 1576: GENOME NON_GENOME PIN 1108
-GENOME NON_GENOME PIN 1108: GENOME NON_GENOME PIN 1576
-INST RocketTile__GCB0 PIN 1241: INST TilePRCIDomain__GC0 PIN 4 TYPE 5
-INST RocketTile__GCB0 PIN 1242: INST TilePRCIDomain__GC0 PIN 5 TYPE 5
-INST RocketTile__GCB0 PIN 1252: INST TilePRCIDomain__GC0 PIN 15 TYPE 5
-INST RocketTile__GCB0 PIN 1445: INST DCache PIN 131 TYPE 5
-INST RocketTile__GCB0 PIN 1446: INST DCache PIN 132 TYPE 5
-INST RocketTile__GCB0 PIN 82: INST TilePRCIDomain__GC0 PIN 415 TYPE 0 GENOME RocketTile__GCB0 PIN 82
-INST RocketTile__GCB0 PIN 121: INST TilePRCIDomain__GC0 PIN 454 TYPE 0 GENOME RocketTile__GCB0 PIN 121
-INST RocketTile__GCB0 PIN 122: INST TilePRCIDomain__GC0 PIN 455 TYPE 0 GENOME RocketTile__GCB0 PIN 122
-INST DCache PIN 131: GENOME DCache PIN 131
-INST DCache PIN 463: GENOME DCache PIN 463 INST RocketTile__GCB0 PIN 324 TYPE 5
-INST DCache PIN 462: GENOME DCache PIN 462
-INST DCache PIN 464: GENOME DCache PIN 464 INST RocketTile__GCB0 PIN 315 TYPE 5
-INST DCache PIN 453: GENOME DCache PIN 453
-INST DCache PIN 603: GENOME DCache PIN 603 INST RocketTile__GCB0 PIN 403 TYPE 5
-INST DCache PIN 541: GENOME DCache PIN 541
-INST DCache PIN 604: GENOME DCache PIN 604
-INST DCache PIN 605: GENOME DCache PIN 605
-INST DCache PIN 670: GENOME DCache PIN 670 INST RocketTile__GCB0 PIN 470 TYPE 5
-INST DCache PIN 608: GENOME DCache PIN 608
-INST DCache PIN 671: GENOME DCache PIN 671
-INST DCache PIN 672: GENOME DCache PIN 672
-INST DCache PIN 737: GENOME DCache PIN 737 INST RocketTile__GCB0 PIN 537 TYPE 5
-INST DCache PIN 675: GENOME DCache PIN 675
-INST DCache PIN 738: GENOME DCache PIN 738
-INST DCache PIN 739: GENOME DCache PIN 739
-INST DCache PIN 804: GENOME DCache PIN 804 INST RocketTile__GCB0 PIN 604 TYPE 5
-INST DCache PIN 742: GENOME DCache PIN 742
-INST DCache PIN 805: GENOME DCache PIN 805
-INST DCache PIN 806: GENOME DCache PIN 806
-INST DCache PIN 871: GENOME DCache PIN 871 INST RocketTile__GCB0 PIN 671 TYPE 5
-INST DCache PIN 809: GENOME DCache PIN 809
-INST DCache PIN 872: GENOME DCache PIN 872
-INST DCache PIN 873: GENOME DCache PIN 873
-INST DCache PIN 938: GENOME DCache PIN 938 INST RocketTile__GCB0 PIN 738 TYPE 5
-INST DCache PIN 876: GENOME DCache PIN 876
-INST DCache PIN 939: GENOME DCache PIN 939
-INST DCache PIN 940: GENOME DCache PIN 940
-INST DCache PIN 1005: GENOME DCache PIN 1005 INST RocketTile__GCB0 PIN 805 TYPE 5
-INST DCache PIN 943: GENOME DCache PIN 943
-INST DCache PIN 1006: GENOME DCache PIN 1006
-INST DCache PIN 1007: GENOME DCache PIN 1007
-INST DCache PIN 1072: GENOME DCache PIN 1072 INST RocketTile__GCB0 PIN 872 TYPE 5
-INST DCache PIN 1010: GENOME DCache PIN 1010
-INST DCache PIN 1073: GENOME DCache PIN 1073
-INST DCache PIN 1074: GENOME DCache PIN 1074
-GENOME NON_GENOME PIN 462: GENOME NON_GENOME PIN 463
-GENOME NON_GENOME PIN 463: GENOME NON_GENOME PIN 462
-GENOME NON_GENOME PIN 453: GENOME NON_GENOME PIN 464 GENOME NON_GENOME PIN 416
-GENOME NON_GENOME PIN 464: GENOME NON_GENOME PIN 453
-GENOME NON_GENOME PIN 541: GENOME NON_GENOME PIN 603
-GENOME NON_GENOME PIN 603: GENOME NON_GENOME PIN 541
-GENOME NON_GENOME PIN 608: GENOME NON_GENOME PIN 670
-GENOME NON_GENOME PIN 670: GENOME NON_GENOME PIN 608
-GENOME NON_GENOME PIN 675: GENOME NON_GENOME PIN 737
-GENOME NON_GENOME PIN 737: GENOME NON_GENOME PIN 675
-GENOME NON_GENOME PIN 742: GENOME NON_GENOME PIN 804
-GENOME NON_GENOME PIN 804: GENOME NON_GENOME PIN 742
-GENOME NON_GENOME PIN 809: GENOME NON_GENOME PIN 871
-GENOME NON_GENOME PIN 871: GENOME NON_GENOME PIN 809
-GENOME NON_GENOME PIN 876: GENOME NON_GENOME PIN 938
-GENOME NON_GENOME PIN 938: GENOME NON_GENOME PIN 876
-GENOME NON_GENOME PIN 943: GENOME NON_GENOME PIN 1005
-GENOME NON_GENOME PIN 1005: GENOME NON_GENOME PIN 943
-GENOME NON_GENOME PIN 1010: GENOME NON_GENOME PIN 1072
-INST VCU118RocketSystem__GC0 PIN 83: GENOME VCU118RocketSystem__GC0 PIN 83
-INST VCU118RocketSystem__GC0 PIN 84: GENOME VCU118RocketSystem__GC0 PIN 84
-INST VCU118RocketSystem__GC0 PIN 85: GENOME VCU118RocketSystem__GC0 PIN 85
-INST VCU118RocketSystem__GC0 PIN 86: GENOME VCU118RocketSystem__GC0 PIN 86
-INST VCU118RocketSystem__GC0 PIN 87: GENOME VCU118RocketSystem__GC0 PIN 87
-INST VCU118RocketSystem__GC0 PIN 126: GENOME VCU118RocketSystem__GC0 PIN 126
-INST VCU118RocketSystem__GC0 PIN 127: GENOME VCU118RocketSystem__GC0 PIN 127
-INST VCU118RocketSystem__GC0 PIN 128: GENOME VCU118RocketSystem__GC0 PIN 128
-INST VCU118RocketSystem__GC0 PIN 129: GENOME VCU118RocketSystem__GC0 PIN 129
-INST VCU118RocketSystem__GC0 PIN 130: GENOME VCU118RocketSystem__GC0 PIN 130
-INST VCU118RocketSystem__GC0 PIN 131: GENOME VCU118RocketSystem__GC0 PIN 131
-INST VCU118RocketSystem__GC0 PIN 132: GENOME VCU118RocketSystem__GC0 PIN 132
-INST VCU118RocketSystem__GC0 PIN 133: GENOME VCU118RocketSystem__GC0 PIN 133
-INST VCU118RocketSystem__GC0 PIN 134: GENOME VCU118RocketSystem__GC0 PIN 134
-INST VCU118RocketSystem__GC0 PIN 135: GENOME VCU118RocketSystem__GC0 PIN 135
-INST VCU118RocketSystem__GC0 PIN 136: GENOME VCU118RocketSystem__GC0 PIN 136
-INST VCU118RocketSystem__GC0 PIN 169: GENOME VCU118RocketSystem__GC0 PIN 169
-INST VCU118RocketSystem__GC0 PIN 171: GENOME VCU118RocketSystem__GC0 PIN 171
-INST VCU118RocketSystem__GC0 PIN 172: GENOME VCU118RocketSystem__GC0 PIN 172
-INST VCU118RocketSystem__GC0 PIN 289: GENOME VCU118RocketSystem__GC0 PIN 289
-INST VCU118RocketSystem__GC0 PIN 335: GENOME VCU118RocketSystem__GC0 PIN 335
-INST VCU118RocketSystem__GC0 PIN 336: GENOME VCU118RocketSystem__GC0 PIN 336
-INST VCU118RocketSystem__GC0 PIN 489: GENOME VCU118RocketSystem__GC0 PIN 489
-INST VCU118RocketSystem__GC0 PIN 490: GENOME VCU118RocketSystem__GC0 PIN 490
-INST VCU118RocketSystem__GC0 PIN 492: GENOME VCU118RocketSystem__GC0 PIN 492
-INST VCU118RocketSystem__GC0 PIN 493: GENOME VCU118RocketSystem__GC0 PIN 493
-INST VCU118RocketSystem__GC0 PIN 503: GENOME VCU118RocketSystem__GC0 PIN 503
-INST VCU118RocketSystem__GC0 PIN 543: GENOME VCU118RocketSystem__GC0 PIN 543
-INST VCU118RocketSystem__GC0 PIN 544: GENOME VCU118RocketSystem__GC0 PIN 544
-GENOME NON_GENOME PIN 360: GENOME NON_GENOME PIN 79
-GENOME NON_GENOME PIN 79: GENOME NON_GENOME PIN 360
-GENOME NON_GENOME PIN 361: GENOME NON_GENOME PIN 80
-GENOME NON_GENOME PIN 80: GENOME NON_GENOME PIN 361
-GENOME NON_GENOME PIN 356: GENOME NON_GENOME PIN 171
-GENOME NON_GENOME PIN 171: GENOME NON_GENOME PIN 356
-GENOME NON_GENOME PIN 357: GENOME NON_GENOME PIN 172
-GENOME NON_GENOME PIN 172: GENOME NON_GENOME PIN 357
-GENOME NON_GENOME PIN 334: GENOME NON_GENOME PIN 335 GENOME NON_GENOME PIN 336
-GENOME NON_GENOME PIN 335: GENOME NON_GENOME PIN 334
-GENOME NON_GENOME PIN 336: GENOME NON_GENOME PIN 334
-INST FPU__GB1 PIN 1: GENOME FPU__GB1 PIN 1
-INST FPU__GB1 PIN 137: GENOME FPU__GB1 PIN 137
-INST FPU__GB1 PIN 163: GENOME FPU__GB1 PIN 163
-INST FPU__GB1 PIN 525: GENOME FPU__GB1 PIN 525
-INST FPU__GB1 PIN 526: GENOME FPU__GB1 PIN 526
-INST FPU__GB1 PIN 527: GENOME FPU__GB1 PIN 527
-INST FPU__GB1 PIN 528: GENOME FPU__GB1 PIN 528
-INST FPU__GB1 PIN 531: GENOME FPU__GB1 PIN 531
-INST FPU__GB1 PIN 532: GENOME FPU__GB1 PIN 532
-INST FPU__GB1 PIN 533: GENOME FPU__GB1 PIN 533
-INST FPU__GB1 PIN 570: GENOME FPU__GB1 PIN 570
-INST FPU__GB1 PIN 571: GENOME FPU__GB1 PIN 571
-GENOME NON_GENOME PIN 536: GENOME NON_GENOME PIN 147
-GENOME NON_GENOME PIN 147: GENOME NON_GENOME PIN 536
-INST APBGpsBlock__GC0 PIN 149: GENOME APBGpsBlock__GC0 PIN 149
-INST APBGpsBlock__GC0 PIN 150: GENOME APBGpsBlock__GC0 PIN 150
-INST APBGpsBlock__GC0 PIN 151: GENOME APBGpsBlock__GC0 PIN 151
-INST APBGpsBlock__GC0 PIN 152: GENOME APBGpsBlock__GC0 PIN 152
-INST APBGpsBlock__GC0 PIN 153: GENOME APBGpsBlock__GC0 PIN 153
-INST APBGpsBlock__GC0 PIN 154: GENOME APBGpsBlock__GC0 PIN 154
-INST APBGpsBlock__GC0 PIN 155: GENOME APBGpsBlock__GC0 PIN 155
-INST APBGpsBlock__GC0 PIN 156: GENOME APBGpsBlock__GC0 PIN 156
-INST APBGpsBlock__GC0 PIN 157: GENOME APBGpsBlock__GC0 PIN 157
-GENOME NON_GENOME PIN 455: GENOME NON_GENOME PIN 1
-INST TilePRCIDomain__GC0 PIN 4: GENOME TilePRCIDomain__GC0 PIN 4
-INST TilePRCIDomain__GC0 PIN 7: GENOME TilePRCIDomain__GC0 PIN 7
-INST TilePRCIDomain__GC0 PIN 8: GENOME TilePRCIDomain__GC0 PIN 8
-INST TilePRCIDomain__GC0 PIN 14: GENOME TilePRCIDomain__GC0 PIN 14
-INST TilePRCIDomain__GC0 PIN 15: GENOME TilePRCIDomain__GC0 PIN 15
-INST TilePRCIDomain__GC0 PIN 415: GENOME TilePRCIDomain__GC0 PIN 415
-INST TilePRCIDomain__GC0 PIN 454: GENOME TilePRCIDomain__GC0 PIN 454
-INST TilePRCIDomain__GC0 PIN 455: GENOME TilePRCIDomain__GC0 PIN 455
-INST TilePRCIDomain__GC0 PIN 531: GENOME TilePRCIDomain__GC0 PIN 531
-INST TilePRCIDomain__GC0 PIN 732: GENOME TilePRCIDomain__GC0 PIN 732
-INST TilePRCIDomain__GC0 PIN 733: GENOME TilePRCIDomain__GC0 PIN 733
-INST vcu118_rocket_top__GC0 PIN 55: GENOME vcu118_rocket_top__GC0 PIN 55
-GENOME NON_GENOME PIN 109: GENOME NON_GENOME PIN 55
-INST vcu118_rocket_top__GC0 PIN 109: INST NON_GENOME PIN 22 TYPE 5
-INST FPU__GB2 PIN 1: INST FPU__GB1 PIN 147 TYPE 3 INST RocketTile__GCB0 PIN 1652 TYPE 4
-INST RocketTile__GCB0 PIN 83: INST RocketTile__GCB0 PIN 119 TYPE 2 INST TilePRCIDomain__GC0 PIN 452 TYPE 4 INST RocketTile__GCB0 PIN 120 TYPE 2 INST TilePRCIDomain__GC0 PIN 453 TYPE 4
-INST RocketTile__GCB0 PIN 119: GENOME RocketTile__GCB0 PIN 119
-INST RocketTile__GCB0 PIN 120: GENOME RocketTile__GCB0 PIN 120
-INST TilePRCIDomain__GC0 PIN 452: GENOME TilePRCIDomain__GC0 PIN 452 INST RocketTile__GCB0 PIN 83 TYPE 5
-INST TilePRCIDomain__GC0 PIN 416: GENOME TilePRCIDomain__GC0 PIN 416
-INST TilePRCIDomain__GC0 PIN 453: GENOME TilePRCIDomain__GC0 PIN 453 INST RocketTile__GCB0 PIN 83 TYPE 5
-GENOME NON_GENOME PIN 416: GENOME NON_GENOME PIN 452 GENOME NON_GENOME PIN 453
-GENOME NON_GENOME PIN 452: GENOME NON_GENOME PIN 416
-INST FPU__GB1 PIN 147: GENOME FPU__GB1 PIN 147
-INST FPU__GB1 PIN 536: INST FPU__GB2 PIN 1 TYPE 5
-INST TilePRCIDomain__GC0 PIN 127: INST VCU118RocketSystem__GC0 PIN 408 TYPE 0
-INST TilePRCIDomain__GC0 PIN 128: INST VCU118RocketSystem__GC0 PIN 409 TYPE 0
-INST TilePRCIDomain__GC0 PIN 208: INST VCU118RocketSystem__GC0 PIN 540 TYPE 0
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/equivDumpFile.info b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/equivDumpFile.info
deleted file mode 100644
index adaa7e3..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/equivDumpFile.info
+++ /dev/null
@@ -1,155 +0,0 @@
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#5:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#3
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#6:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#4
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#9:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#5
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#10:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#6
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#11:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#7
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#12:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#8
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#16:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#10
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#17:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#11
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#18:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#12
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#19:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#13
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#20:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#14
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#21:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#15
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#22:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#16
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#23:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#17
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#24:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#18
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#25:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#19
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#26:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#20
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#27:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#21
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#28:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#22
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#29:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#23
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#30:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#24
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#31:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#25
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#32:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#26
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#33:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#27
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#34:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#28
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#35:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#29
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#36:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#30
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#37:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#31
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#38:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#32
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#39:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#33
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#40:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#34
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#41:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#35
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#42:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#36
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#43:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#37
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#44:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#38
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#45:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#39
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#46:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#40
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#47:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#41
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#48:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#42
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#49:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#43
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#50:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#44
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#51:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#45
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#52:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#46
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#53:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#47
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#54:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#48
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#55:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#49
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#56:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#50
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#57:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#51
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#58:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#52
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#59:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#53
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#60:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#54
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#61:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#55
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#62:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#56
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#63:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#57
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#64:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#58
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#65:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#59
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#66:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#60
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#67:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#61
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#68:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#62
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#69:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#63
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#70:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#64
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#71:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#65
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#72:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#66
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#73:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#67
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#74:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#68
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#75:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#69
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#76:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#70
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#77:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#71
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#78:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#72
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0#79:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#73
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#324:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#325
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#315:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#326
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#403:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#465
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#470:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#532
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#537:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#599
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#604:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#666
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#671:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#733
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#738:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#800
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#805:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#867
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#872:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#934
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#124:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1040
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#125:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1041
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#126:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1042
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#127:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1043
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#128:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1044
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#199:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1045
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#200:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1046
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#201:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1047
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#202:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1048
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#203:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1049
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#204:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1050
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#205:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1051
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#206:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1052
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#207:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1053
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#208:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1054
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#209:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1055
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#210:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1056
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#211:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1057
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#212:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1058
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#213:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1059
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#214:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1060
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#215:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1061
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#216:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1062
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#217:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1063
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#218:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1064
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#219:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1065
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#220:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1066
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#221:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1067
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#222:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1068
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#223:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1069
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#224:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1070
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#225:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1071
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#226:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1072
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#227:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1073
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#228:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1074
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#229:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1075
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#230:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1076
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#231:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1077
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#232:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1078
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#233:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1079
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#234:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1080
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#235:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1081
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#236:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1082
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#237:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1083
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#238:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1084
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#239:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1085
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#240:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1086
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#241:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1087
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#242:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1088
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#243:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1089
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#244:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1090
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#245:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1091
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#246:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1092
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#247:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1093
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#248:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1094
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#249:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1095
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#250:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1096
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#251:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1097
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#252:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1098
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#253:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1099
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#254:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1100
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#255:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1101
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#256:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1102
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#257:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1103
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#258:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1104
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#259:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1105
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#260:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1106
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#261:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1107
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#262:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1108
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache#132:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#1039
-/u_rocket/VCU118RocketSystem__GC0#334:/u_rocket/VCU118RocketSystem__GC0#335
-/u_rocket/VCU118RocketSystem__GC0#334:/u_rocket/VCU118RocketSystem__GC0#336
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2#1:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1#147
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#83:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#119
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#83:/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0#120
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1220760385.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1220760385.rtd
deleted file mode 100644
index c5a7ac8..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index c9cd07d..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1294509424.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1294509424.rtd
deleted file mode 100644
index efdd4b2..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index c3af733..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/136113302.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/136113302.rtd
deleted file mode 100644
index a3f1fb4..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/136113302.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/136113302.rtd.straps.rtd
deleted file mode 100644
index fbe074f..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1672436263.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1672436263.rtd
deleted file mode 100644
index 5e884de..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index be77a87..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2438764479.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2438764479.rtd
deleted file mode 100644
index 99104f6..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2438764479.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2438764479.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2438764479.rtd.straps.rtd
deleted file mode 100644
index a96a922..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2438764479.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2438764479.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2438764479.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2438764479.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2438764479.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2438764479.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2610937407.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2610937407.rtd
deleted file mode 100644
index 13f892e..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index 94bf885..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2737226844.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2737226844.rtd
deleted file mode 100644
index 10b81e3..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index a047b21..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2962621930.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2962621930.rtd
deleted file mode 100644
index 0900b85..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index 55b6a2e..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/3482045580.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/3482045580.rtd
deleted file mode 100644
index 763cce9..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index 57dfef4..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/944784429.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/944784429.rtd
deleted file mode 100644
index 7a63521..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/944784429.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/944784429.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/944784429.rtd.straps.rtd
deleted file mode 100644
index 54ee69a..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/944784429.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/944784429.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/944784429.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/944784429.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/944784429.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/944784429.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/976197094.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/976197094.rtd
deleted file mode 100644
index bbf1f7e..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/976197094.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/976197094.rtd.straps.rtd
deleted file mode 100644
index 2d59936..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/global_name.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/global_name.straps.rtd
deleted file mode 100644
index fd15267..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/instToEncGenName.map b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/instToEncGenName.map
deleted file mode 100644
index 7077034..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/g/instToEncGenName.map
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/vcu118_rocket_top__GC0:944784429
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0:2438764479
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/stitchPoint.lst b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/stitchPoint.lst
deleted file mode 100644
index bfb76ad..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/stitchPoint.lst
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2
-/u_rocket/fpga_gps_domain/dev/tracking_8
-/u_rocket/VCU118RocketSystem__GC0
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache
-/u_rocket/fpga_gps_domain/dev/tracking_7
-/u_rocket/fpga_gps_domain/dev/tracking_6
-/vcu118_rocket_top__GC0
-/u_rocket/fpga_gps_domain/dev/tracking_5
-/u_rocket/fpga_gps_domain/dev/tracking_4
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0
-/u_rocket/fpga_gps_domain/dev/tracking_3
-/u_rocket/fpga_gps_domain/dev/tracking_2
-/u_rocket/fpga_gps_domain/tl2apb
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1
-/u_rocket/fpga_gps_domain/dev/tracking_1
-/u_rocket/fpga_gps_domain/dev/tracking_0
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/82910060.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/82910060.rtd
deleted file mode 100644
index 338950e..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/82910060.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/82910260.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/82910260.rtd
deleted file mode 100644
index 86d12ac..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/82910260.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/82910E00.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/82910E00.rtd
deleted file mode 100644
index e76e61e..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/82910E00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/8395DBA0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/8395DBA0.rtd
deleted file mode 100644
index f8339d7..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/8395DBA0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/CA7D28A0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/CA7D28A0.rtd
deleted file mode 100644
index 33c09b9..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/CA7D28A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/CA7D3D00.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/CA7D3D00.rtd
deleted file mode 100644
index 6d136c2..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/CA7D3D00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/CC7B28E0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/CC7B28E0.rtd
deleted file mode 100644
index 51cef57..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/CC7B28E0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE4E1080.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE4E1080.rtd
deleted file mode 100644
index 62e45f9..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE4E1080.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE4E10A0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE4E10A0.rtd
deleted file mode 100644
index 591d0f2..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE4E10A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE4E19C0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE4E19C0.rtd
deleted file mode 100644
index c0c8bcd..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE4E19C0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE51A320.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE51A320.rtd
deleted file mode 100644
index b12652b..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/EE51A320.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/design.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/design.rtd
deleted file mode 100644
index 03db61a..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/files.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/files.rtd
deleted file mode 100644
index 3f4f6d5..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/files.rtd
+++ /dev/null
@@ -1,13 +0,0 @@
-design.rtd
-straps.rtd
-82910060.rtd
-82910260.rtd
-82910E00.rtd
-EE51A320.rtd
-EE4E19C0.rtd
-EE4E10A0.rtd
-CA7D28A0.rtd
-CA7D3D00.rtd
-EE4E1080.rtd
-CC7B28E0.rtd
-8395DBA0.rtd
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/straps.rtd
deleted file mode 100644
index a139d3e..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/uniqInferGenToOrigInferGen.map b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/o/uniqInferGenToOrigInferGen.map
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/childModToGenomes.map b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/childModToGenomes.map
deleted file mode 100644
index 9af3b51..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/childModToGenomes.map
+++ /dev/null
@@ -1,8236 +0,0 @@
-datapath__13: vcu118_rocket_top__GC0,
-comp_mult: APBGpsBlock__GC0,
-muxpart__70: vcu118_rocket_top__GC0,
-case__631: RocketTile__GCB0,
-datapath__674: tracking_wrapper,
-reg__379: RocketTile__GCB0,
-datapath__372: FPU__GB1,
-logic__1211: VCU118RocketSystem__GC0,
-reg__607: FPU__GB1,
-spill_register_flushable: tracking_wrapper,
-reg__29: vcu118_rocket_top__GC0,
-muxpart__379: tracking_wrapper,
-logic__1433: VCU118RocketSystem__GC0,
-logic__339: vcu118_rocket_top__GC0,
-case__475: VCU118RocketSystem__GC0,
-logic__4971: FPU__GB1,
-logic__8832: tracking_wrapper,
-logic__5448: RocketTile__GCB0,
-logic__6896: VCU118RocketSystem__GC0,
-reg__176: VCU118RocketSystem__GC0,
-logic__1624: VCU118RocketSystem__GC0,
-logic__1590: VCU118RocketSystem__GC0,
-reg__147: VCU118RocketSystem__GC0,
-logic__2270: DCache,
-datapath__84: VCU118RocketSystem__GC0,
-logic__5736: RocketTile__GCB0,
-TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u: RocketTile__GCB0,
-logic__2153: DCache,
-reg__426: RocketTile__GCB0,
-RoundAnyRawFNToRecFN_3: FPU__GB1,
-logic__6852: VCU118RocketSystem__GC0,
-reg__1392: tracking_wrapper,
-lock_detector: tracking_wrapper,
-datapath__582: APBGpsBlock__GC0,
-logic__5453: RocketTile__GCB0,
-AsyncQueueSink_TLBundleA_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-muxpart__79: vcu118_rocket_top__GC0,
-case__1625: tracking_wrapper,
-logic__5412: RocketTile__GCB0,
-logic__3841: FPU__GB2,
-reg__272: VCU118RocketSystem__GC0,
-case__256: VCU118RocketSystem__GC0,
-logic__6674: RocketTile__GCB0,
-case__518: DCache,
-logic__6042: RocketTile__GCB0,
-logic__3805: FPU__GB2,
-case__1294: APBGpsBlock__GC0,
-muxpart__86: vcu118_rocket_top__GC0,
-Queue2_TLBundleA_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-case__630: RocketTile__GCB0,
-case__28: vcu118_rocket_top__GC0,
-logic__7354: VCU118RocketSystem__GC0,
-logic__1712: VCU118RocketSystem__GC0,
-reg__1143: APBGpsBlock__GC0,
-INToRecFN_1: FPU__GB2,
-case__885: RocketTile__GCB0,
-case__290: VCU118RocketSystem__GC0,
-datapath__474: RocketTile__GCB0,
-reg__253: VCU118RocketSystem__GC0,
-case__168: vcu118_rocket_top__GC0,
-logic__4691: FPU__GB2,
-logic__4524: FPU__GB1,
-logic__7611: VCU118RocketSystem__GC0,
-reg__1099: APBGpsBlock__GC0,
-logic__7285: VCU118RocketSystem__GC0,
-case__183: vcu118_rocket_top__GC0,
-datapath__303: RocketTile__GCB0,
-case__1540: tracking_wrapper,
-logic__3491: FPU__GB1,
-case__789: FPU__GB1,
-reg__844: RocketTile__GCB0,
-logic__31: vcu118_rocket_top__GC0,
-logic__4400: FPU__GB1,
-datapath__76: VCU118RocketSystem__GC0,
-reg__496: FPU__GB1,
-logic__8041: VCU118RocketSystem__GC0,
-muxpart__10: vcu118_rocket_top__GC0,
-logic__4696: FPU__GB2,
-logic__6181: RocketTile__GCB0,
-reg__15: vcu118_rocket_top__GC0,
-reg__702: RocketTile__GCB0,
-reg__605: FPU__GB1,
-logic__6043: RocketTile__GCB0,
-muxpart__381: tracking_wrapper,
-case__717: FPU__GB1,
-case__682: FPU__GB2,
-reg__548: FPU__GB1,
-reg__1066: VCU118RocketSystem__GC0,
-logic__8705: APBGpsBlock__GC0,
-case__135: vcu118_rocket_top__GC0,
-reg__1111: APBGpsBlock__GC0,
-reg__124: VCU118RocketSystem__GC0,
-TLAsyncCrossingSource_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__812: VCU118RocketSystem__GC0,
-datapath__594: APBGpsBlock__GC0,
-reg__792: RocketTile__GCB0,
-logic__129: vcu118_rocket_top__GC0,
-logic__6818: VCU118RocketSystem__GC0,
-logic__3216: RocketTile__GCB0,
-reg__624: FPU__GB1,
-logic__670: vcu118_rocket_top__GC0,
-logic__7691: VCU118RocketSystem__GC0,
-reg__1225: tracking_wrapper,
-reg__559: FPU__GB1,
-logic__7228: VCU118RocketSystem__GC0,
-logic__6801: VCU118RocketSystem__GC0,
-datapath__225: VCU118RocketSystem__GC0,
-datapath__593: APBGpsBlock__GC0,
-logic__2494: RocketTile__GCB0, DCache,
-case__1038: VCU118RocketSystem__GC0,
-datapath__325: FPU__GB1,
-datapath__370: FPU__GB1,
-logic__5462: RocketTile__GCB0,
-logic__176: vcu118_rocket_top__GC0,
-reg__793: RocketTile__GCB0,
-logic__6791: VCU118RocketSystem__GC0,
-reg__1224: tracking_wrapper,
-logic__1297: VCU118RocketSystem__GC0,
-logic__6309: RocketTile__GCB0,
-logic__7520: VCU118RocketSystem__GC0,
-logic__9220: tracking_wrapper,
-logic__478: vcu118_rocket_top__GC0,
-reg__1323: tracking_wrapper,
-logic__9407: APBGpsBlock__GC0,
-logic__5458: RocketTile__GCB0,
-logic__3897: FPU__GB2,
-case__296: VCU118RocketSystem__GC0,
-logic__4920: FPU__GB2,
-logic__3461: FPU__GB1,
-reg__229: VCU118RocketSystem__GC0,
-reg__43: vcu118_rocket_top__GC0,
-TLXbar_cbus_in_i1_o1_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__3429: FPU__GB1,
-logic__181: vcu118_rocket_top__GC0,
-logic__4361: FPU__GB1,
-reg__322: DCache,
-datapath__268: DCache,
-datapath__147: VCU118RocketSystem__GC0,
-logic__3159: RocketTile__GCB0,
-case__1571: tracking_wrapper,
-reg__626: FPU__GB1,
-reg__133: VCU118RocketSystem__GC0,
-case__1440: APBGpsBlock__GC0,
-case__961: RocketTile__GCB0,
-case__848: RocketTile__GCB0,
-logic__5647: RocketTile__GCB0,
-logic__8858: tracking_wrapper,
-datapath__716: tracking_wrapper,
-logic__8808: tracking_wrapper,
-case__661: FPU__GB2, FPU__GB1,
-logic__9367: tracking_wrapper,
-case__519: DCache,
-logic__2274: DCache,
-logic__5106: FPU__GB1,
-logic__4021: FPU__GB2,
-logic__6163: RocketTile__GCB0,
-logic__6947: VCU118RocketSystem__GC0,
-logic__6680: RocketTile__GCB0,
-INToRecFN: FPU__GB2,
-datapath__335: FPU__GB2,
-logic__3545: FPU__GB1,
-logic__5307: RocketTile__GCB0,
-MulAddRecFNToRaw_postMul_1: FPU__GB1,
-case__152: vcu118_rocket_top__GC0,
-logic__6965: VCU118RocketSystem__GC0,
-case__1438: APBGpsBlock__GC0,
-case__566: DCache,
-logic__5507: RocketTile__GCB0,
-logic__7174: VCU118RocketSystem__GC0,
-logic__3531: FPU__GB1,
-reg__343: DCache,
-logic__2990: RocketTile__GCB0,
-case__796: FPU__GB1,
-logic__7349: VCU118RocketSystem__GC0,
-logic__5529: RocketTile__GCB0,
-logic__7989: VCU118RocketSystem__GC0,
-case__949: RocketTile__GCB0,
-logic__2669: DCache,
-case__639: RocketTile__GCB0,
-logic__929: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__990: VCU118RocketSystem__GC0,
-reg__57: vcu118_rocket_top__GC0,
-datapath__133: VCU118RocketSystem__GC0,
-datapath__230: VCU118RocketSystem__GC0,
-case__688: FPU__GB2,
-logic__5178: FPU__GB1,
-muxpart__207: FPU__GB0,
-logic__3489: FPU__GB1,
-logic__9221: tracking_wrapper,
-logic__5478: RocketTile__GCB0,
-reg__1350: tracking_wrapper,
-case__379: VCU118RocketSystem__GC0,
-case__1500: APBGpsBlock__GC0,
-case__652: FPU__GB2, FPU__GB1,
-binary_to_gray: tracking_wrapper,
-case__987: VCU118RocketSystem__GC0,
-reg__420: RocketTile__GCB0,
-logic__7429: VCU118RocketSystem__GC0,
-logic__2004: VCU118RocketSystem__GC0,
-logic__8811: tracking_wrapper,
-reg__52: vcu118_rocket_top__GC0,
-logic__801: VCU118RocketSystem__GC0,
-logic__8592: APBGpsBlock__GC0,
-logic__7040: VCU118RocketSystem__GC0,
-datapath__259: VCU118RocketSystem__GC0,
-FixedClockBroadcast_5: VCU118RocketSystem__GC0,
-case__706: FPU__GB1,
-logic__6301: RocketTile__GCB0,
-addsub__4: tracking_wrapper,
-case__428: VCU118RocketSystem__GC0,
-case__1487: APBGpsBlock__GC0,
-case__207: vcu118_rocket_top__GC0,
-case__1064: VCU118RocketSystem__GC0,
-logic__741: vcu118_rocket_top__GC0,
-datapath__11: vcu118_rocket_top__GC0,
-reg__536: FPU__GB1,
-case__69: vcu118_rocket_top__GC0,
-logic__3313: FPU__GB1,
-counter__16: APBGpsBlock__GC0,
-ram_2x78: VCU118RocketSystem__GC0,
-logic__2621: DCache,
-logic__4433: FPU__GB1,
-logic__5304: RocketTile__GCB0,
-case__1582: tracking_wrapper,
-datapath__129: VCU118RocketSystem__GC0,
-logic__9166: tracking_wrapper,
-logic__5653: RocketTile__GCB0,
-datapath__629: APBGpsBlock__GC0,
-datapath__657: APBGpsBlock__GC0,
-datapath__713: tracking_wrapper,
-logic__5459: RocketTile__GCB0,
-logic__4337: FPU__GB1,
-case__666: FPU__GB2,
-datapath__288: DCache,
-logic__4399: FPU__GB1,
-case__1156: VCU118RocketSystem__GC0,
-datapath__237: VCU118RocketSystem__GC0,
-datapath__6: vcu118_rocket_top__GC0,
-reg__77: vcu118_rocket_top__GC0,
-reg__136: VCU118RocketSystem__GC0,
-logic__7412: VCU118RocketSystem__GC0,
-muxpart__83: vcu118_rocket_top__GC0,
-muxpart__51: vcu118_rocket_top__GC0,
-logic__8011: VCU118RocketSystem__GC0,
-logic__5418: RocketTile__GCB0,
-logic__4442: FPU__GB1,
-logic__2643: DCache,
-case__1008: VCU118RocketSystem__GC0,
-case__1003: VCU118RocketSystem__GC0,
-logic__8955: tracking_wrapper,
-logic__4101: FPU__GB2,
-case__650: FPU__GB1,
-RoundRawFNToRecFN_1: FPU__GB2, FPU__GB1,
-logic__271: vcu118_rocket_top__GC0,
-logic__3553: FPU__GB1,
-logic__6135: RocketTile__GCB0,
-logic__8003: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_cbus_to_bus_named_pbus: VCU118RocketSystem__GC0,
-datapath__270: DCache,
-case__901: RocketTile__GCB0,
-logic__3341: FPU__GB1,
-logic__1576: VCU118RocketSystem__GC0,
-logic__2158: DCache,
-muxpart__221: FPU__GB0,
-logic__8051: VCU118RocketSystem__GC0,
-logic__5053: FPU__GB1,
-case__1545: tracking_wrapper,
-reg__901: VCU118RocketSystem__GC0,
-logic__2277: DCache,
-logic__6063: RocketTile__GCB0,
-logic__506: vcu118_rocket_top__GC0,
-logic__7398: VCU118RocketSystem__GC0,
-logic__7199: VCU118RocketSystem__GC0,
-logic__6179: RocketTile__GCB0,
-muxpart__3: vcu118_rocket_top__GC0,
-logic__9088: tracking_wrapper,
-datapath__184: VCU118RocketSystem__GC0,
-logic__1903: VCU118RocketSystem__GC0,
-case__229: VCU118RocketSystem__GC0,
-datapath__611: APBGpsBlock__GC0,
-logic__2966: RocketTile__GCB0,
-reg__747: RocketTile__GCB0,
-rockettile_dcache_data_arrays_0_131072x64: DCache,
-reg__68: vcu118_rocket_top__GC0,
-logic__1639: VCU118RocketSystem__GC0,
-logic__9023: tracking_wrapper,
-logic__5650: RocketTile__GCB0,
-datapath__31: vcu118_rocket_top__GC0,
-logic__6930: VCU118RocketSystem__GC0,
-logic__2623: DCache,
-logic__5944: RocketTile__GCB0,
-logic__7772: VCU118RocketSystem__GC0,
-reg__222: VCU118RocketSystem__GC0,
-reg__188: VCU118RocketSystem__GC0,
-logic__5525: RocketTile__GCB0,
-reg__898: VCU118RocketSystem__GC0,
-logic__3117: RocketTile__GCB0,
-logic__8879: tracking_wrapper,
-case__919: RocketTile__GCB0,
-datapath__122: VCU118RocketSystem__GC0,
-case__228: VCU118RocketSystem__GC0,
-case__898: RocketTile__GCB0,
-logic__2549: DCache,
-logic__270: vcu118_rocket_top__GC0,
-logic__7220: VCU118RocketSystem__GC0,
-reg__725: RocketTile__GCB0,
-reg__1022: VCU118RocketSystem__GC0,
-logic__863: VCU118RocketSystem__GC0,
-logic__3093: RocketTile__GCB0,
-logic__8418: APBGpsBlock__GC0,
-tracking_wrapper: tracking_wrapper,
-logic__8933: tracking_wrapper,
-logic__4387: FPU__GB1,
-case__886: RocketTile__GCB0,
-logic__4213: FPU__GB1,
-reg__54: vcu118_rocket_top__GC0,
-logic__1036: VCU118RocketSystem__GC0,
-reg__1173: APBGpsBlock__GC0,
-logic__6477: RocketTile__GCB0,
-reg__1377: tracking_wrapper,
-logic__3765: FPU__GB2,
-reg__304: VCU118RocketSystem__GC0,
-logic__6051: RocketTile__GCB0,
-logic__3680: FPU__GB1,
-reg__1294: tracking_wrapper,
-datapath__722: tracking_wrapper,
-logic__3872: FPU__GB2,
-reg__1293: tracking_wrapper,
-logic__8704: APBGpsBlock__GC0,
-logic__6910: VCU118RocketSystem__GC0,
-logic__3788: FPU__GB2,
-logic__4707: FPU__GB2,
-case__703: FPU__GB1,
-logic__6730: RocketTile__GCB0,
-logic__4481: FPU__GB1,
-logic__831: VCU118RocketSystem__GC0,
-reg__6: vcu118_rocket_top__GC0,
-logic__8118: VCU118RocketSystem__GC0,
-logic__5172: FPU__GB1,
-MulAddRecFNToRaw_preMul_1: FPU__GB1,
-logic__3016: RocketTile__GCB0,
-RoundAnyRawFNToRecFN_1: FPU__GB2,
-TLXbar_cbus_out_i1_o7_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__3283: RocketTile__GCB0,
-logic__4821: FPU__GB2,
-logic__7341: VCU118RocketSystem__GC0,
-reg__132: VCU118RocketSystem__GC0,
-logic__672: vcu118_rocket_top__GC0,
-logic__1461: VCU118RocketSystem__GC0,
-case__16: vcu118_rocket_top__GC0,
-logic__2834: DCache,
-counter__15: APBGpsBlock__GC0,
-logic__5319: RocketTile__GCB0,
-logic__7074: VCU118RocketSystem__GC0,
-logic__2975: RocketTile__GCB0,
-logic__9197: tracking_wrapper,
-case__915: RocketTile__GCB0,
-logic__1080: VCU118RocketSystem__GC0,
-logic__2259: DCache,
-muxpart__208: FPU__GB0,
-reg__289: VCU118RocketSystem__GC0,
-reg__673: RocketTile__GCB0,
-case__767: FPU__GB2,
-logic__3985: FPU__GB2,
-logic__3227: RocketTile__GCB0,
-muxpart__90: vcu118_rocket_top__GC0,
-logic__3252: RocketTile__GCB0,
-case__533: DCache,
-logic__913: VCU118RocketSystem__GC0,
-datapath__589: APBGpsBlock__GC0,
-logic__1145: VCU118RocketSystem__GC0,
-signinv__1: VCU118RocketSystem__GC0,
-case__1262: APBGpsBlock__GC0,
-logic__8773: APBGpsBlock__GC0,
-logic__619: vcu118_rocket_top__GC0,
-logic__6299: RocketTile__GCB0,
-logic__4390: FPU__GB1,
-logic__5367: RocketTile__GCB0,
-case__1340: APBGpsBlock__GC0,
-muxpart__358: APBGpsBlock__GC0,
-logic__940: VCU118RocketSystem__GC0,
-datapath__480: RocketTile__GCB0,
-reg__1309: tracking_wrapper,
-case__1133: VCU118RocketSystem__GC0,
-case__182: vcu118_rocket_top__GC0,
-reg__614: FPU__GB1,
-reg__768: RocketTile__GCB0,
-logic__2723: DCache,
-logic__4830: FPU__GB2,
-logic__5482: RocketTile__GCB0,
-logic__3411: FPU__GB1,
-logic__7249: VCU118RocketSystem__GC0,
-logic__9239: tracking_wrapper,
-reg__1319: tracking_wrapper,
-logic__1294: VCU118RocketSystem__GC0,
-case__1292: APBGpsBlock__GC0,
-logic__114: vcu118_rocket_top__GC0,
-dsp48e2__26: APBGpsBlock__GC0,
-logic__1923: VCU118RocketSystem__GC0,
-logic__8745: APBGpsBlock__GC0,
-logic__5199: RocketTile__GCB0,
-reg__866: VCU118RocketSystem__GC0,
-logic__1789: VCU118RocketSystem__GC0,
-divider__parameterized0: tracking_wrapper,
-logic__5061: FPU__GB2,
-datapath__327: FPU__GB2, FPU__GB1,
-logic__2923: DCache,
-logic__6923: VCU118RocketSystem__GC0,
-muxpart__197: FPU__GB0,
-reg__928: VCU118RocketSystem__GC0,
-TLFpgaUART: VCU118RocketSystem__GC0,
-datapath__75: VCU118RocketSystem__GC0,
-reg__727: RocketTile__GCB0,
-reg__16: vcu118_rocket_top__GC0,
-datapath__244: VCU118RocketSystem__GC0,
-logic__5638: RocketTile__GCB0,
-logic__4250: FPU__GB1,
-logic__5983: RocketTile__GCB0,
-logic__3251: RocketTile__GCB0,
-logic__3112: RocketTile__GCB0,
-logic__9384: APBGpsBlock__GC0,
-datapath__322: FPU__GB1,
-logic__4693: FPU__GB2,
-logic__7210: VCU118RocketSystem__GC0,
-reg__660: RocketTile__GCB0,
-dsp48e2__30: tracking_wrapper,
-logic__7359: VCU118RocketSystem__GC0,
-logic__802: VCU118RocketSystem__GC0,
-datapath__633: APBGpsBlock__GC0,
-logic__9235: tracking_wrapper,
-reg__1280: tracking_wrapper,
-logic__4428: FPU__GB1,
-reg__1235: tracking_wrapper,
-datapath__545: VCU118RocketSystem__GC0,
-logic__7588: VCU118RocketSystem__GC0,
-logic__7231: VCU118RocketSystem__GC0,
-reg__788: RocketTile__GCB0,
-case__238: VCU118RocketSystem__GC0,
-datapath__443: RocketTile__GCB0,
-case__1661: tracking_wrapper,
-logic__5144: FPU__GB1,
-logic__3424: FPU__GB1,
-DivSqrtRecFN_small_1: FPU__GB2,
-case__57: vcu118_rocket_top__GC0,
-reg__664: RocketTile__GCB0,
-case__1118: VCU118RocketSystem__GC0,
-reg__230: VCU118RocketSystem__GC0,
-addsub__1: tracking_wrapper,
-case__854: RocketTile__GCB0,
-logic__6157: RocketTile__GCB0,
-logic__3458: FPU__GB1,
-logic__6859: VCU118RocketSystem__GC0,
-datapath__661: tracking_wrapper,
-logic__4898: FPU__GB2,
-case__619: RocketTile__GCB0,
-logic__7648: VCU118RocketSystem__GC0,
-reg__183: VCU118RocketSystem__GC0,
-case__863: RocketTile__GCB0,
-logic__6654: RocketTile__GCB0,
-datapath__597: APBGpsBlock__GC0,
-datapath__12: vcu118_rocket_top__GC0,
-logic__9209: tracking_wrapper,
-case__1024: VCU118RocketSystem__GC0,
-logic__780: VCU118RocketSystem__GC0,
-datapath__621: APBGpsBlock__GC0,
-logic__7545: VCU118RocketSystem__GC0,
-logic__1924: VCU118RocketSystem__GC0,
-datapath__569: APBGpsBlock__GC0,
-reg__502: FPU__GB1,
-logic__5491: RocketTile__GCB0,
-logic__3497: FPU__GB1,
-logic__6679: RocketTile__GCB0,
-reg__295: VCU118RocketSystem__GC0,
-logic__2389: DCache,
-counter__24: tracking_wrapper,
-datapath__142: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__1331: tracking_wrapper,
-logic__8442: APBGpsBlock__GC0,
-reg__694: RocketTile__GCB0,
-logic__4402: FPU__GB1,
-reg__377: RocketTile__GCB0,
-logic__8941: tracking_wrapper,
-logic__8998: tracking_wrapper,
-logic__6768: VCU118RocketSystem__GC0,
-case__1489: APBGpsBlock__GC0,
-case__764: FPU__GB2,
-logic__8267: APBGpsBlock__GC0,
-logic__5957: RocketTile__GCB0,
-reg__1166: APBGpsBlock__GC0,
-case__815: RocketTile__GCB0,
-case__219: vcu118_rocket_top__GC0,
-logic__7441: VCU118RocketSystem__GC0,
-reg__1252: tracking_wrapper,
-logic__4254: FPU__GB1,
-logic__2872: DCache,
-logic__2848: DCache,
-logic__8123: VCU118RocketSystem__GC0,
-case__137: vcu118_rocket_top__GC0,
-muxpart__191: FPU__GB0,
-reg__1096: APBGpsBlock__GC0,
-logic__1558: VCU118RocketSystem__GC0,
-case__1621: tracking_wrapper,
-logic__5119: FPU__GB1,
-reg__655: RocketTile__GCB0,
-logic__2982: RocketTile__GCB0,
-counter__2: vcu118_rocket_top__GC0,
-reg__931: VCU118RocketSystem__GC0,
-logic__6134: RocketTile__GCB0,
-case__626: RocketTile__GCB0,
-logic__7599: VCU118RocketSystem__GC0,
-case__1078: VCU118RocketSystem__GC0,
-logic__1874: VCU118RocketSystem__GC0,
-logic__6178: RocketTile__GCB0,
-logic__2559: DCache,
-datapath__304: RocketTile__GCB0,
-case__960: RocketTile__GCB0,
-logic__9383: tracking_wrapper,
-logic__3425: FPU__GB1,
-logic__8355: APBGpsBlock__GC0,
-eth_rf_vcu118: vcu118_rocket_top__GC0,
-reg__4: vcu118_rocket_top__GC0,
-logic__8838: tracking_wrapper,
-logic__9138: tracking_wrapper,
-case__1249: VCU118RocketSystem__GC0,
-logic__2796: DCache,
-logic__1: vcu118_rocket_top__GC0,
-reg__1064: VCU118RocketSystem__GC0,
-datapath__69: VCU118RocketSystem__GC0,
-TLFragmenter_Debug: VCU118RocketSystem__GC0,
-logic__237: vcu118_rocket_top__GC0,
-datapath__515: VCU118RocketSystem__GC0,
-case__882: RocketTile__GCB0,
-case__456: VCU118RocketSystem__GC0,
-logic__2683: DCache,
-counter__19: APBGpsBlock__GC0,
-muxpart__100: vcu118_rocket_top__GC0,
-datapath__668: tracking_wrapper,
-datapath__194: VCU118RocketSystem__GC0,
-muxpart__5: vcu118_rocket_top__GC0,
-muxpart__42: vcu118_rocket_top__GC0,
-logic__106: vcu118_rocket_top__GC0,
-logic__8137: VCU118RocketSystem__GC0,
-case__1588: tracking_wrapper,
-logic__6572: RocketTile__GCB0,
-case__1166: VCU118RocketSystem__GC0,
-counter__23: APBGpsBlock__GC0,
-logic__1845: VCU118RocketSystem__GC0,
-reg__3: vcu118_rocket_top__GC0,
-logic__8232: VCU118RocketSystem__GC0,
-case__1679: APBGpsBlock__GC0,
-case__242: VCU118RocketSystem__GC0,
-reg__636: FPU__GB1,
-datapath__213: VCU118RocketSystem__GC0,
-reg__1100: APBGpsBlock__GC0,
-datapath__535: VCU118RocketSystem__GC0,
-case__787: FPU__GB1,
-reg__509: FPU__GB1,
-reg__720: RocketTile__GCB0,
-logic__6169: RocketTile__GCB0,
-logic__5674: RocketTile__GCB0,
-logic__4990: FPU__GB1,
-logic__1336: VCU118RocketSystem__GC0,
-logic__1187: VCU118RocketSystem__GC0,
-case__301: VCU118RocketSystem__GC0,
-case__576: RocketTile__GCB0,
-case__516: DCache,
-ClockCrossingReg_w43: VCU118RocketSystem__GC0,
-reg__587: FPU__GB2,
-case__19: vcu118_rocket_top__GC0,
-logic__7107: VCU118RocketSystem__GC0,
-logic__7963: VCU118RocketSystem__GC0,
-logic__6808: VCU118RocketSystem__GC0,
-logic__4919: FPU__GB2,
-logic__3736: FPU__GB2,
-logic__4618: FPU__GB2, FPU__GB1,
-logic__5303: RocketTile__GCB0,
-logic__756: vcu118_rocket_top__GC0,
-logic__479: vcu118_rocket_top__GC0,
-case__10: vcu118_rocket_top__GC0,
-logic__9034: tracking_wrapper,
-Repeater_TLBundleA_a17d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__3720: FPU__GB2,
-muxpart__176: DCache,
-case__167: vcu118_rocket_top__GC0,
-logic__459: vcu118_rocket_top__GC0,
-datapath__77: VCU118RocketSystem__GC0,
-case__1084: VCU118RocketSystem__GC0,
-reg__249: VCU118RocketSystem__GC0,
-case__1302: APBGpsBlock__GC0,
-logic__6144: RocketTile__GCB0,
-reg__751: RocketTile__GCB0,
-case__1076: VCU118RocketSystem__GC0,
-case__514: DCache,
-logic__8060: VCU118RocketSystem__GC0,
-case__635: RocketTile__GCB0,
-logic__5010: FPU__GB1,
-reg__467: FPU__GB0,
-case__18: vcu118_rocket_top__GC0,
-case__434: VCU118RocketSystem__GC0,
-logic__1469: VCU118RocketSystem__GC0,
-case__1391: APBGpsBlock__GC0,
-reg__609: FPU__GB1,
-logic__8043: VCU118RocketSystem__GC0,
-datapath__599: APBGpsBlock__GC0,
-reg__1159: APBGpsBlock__GC0,
-reg__994: VCU118RocketSystem__GC0,
-reg__572: FPU__GB1,
-SystemBus: VCU118RocketSystem__GC0,
-logic__3007: RocketTile__GCB0,
-case__392: VCU118RocketSystem__GC0,
-logic__617: vcu118_rocket_top__GC0,
-logic__3697: FPU__GB2,
-logic__3687: FPU__GB2,
-logic__4421: FPU__GB1,
-datapath__55: VCU118RocketSystem__GC0,
-logic__948: VCU118RocketSystem__GC0,
-reg__111: VCU118RocketSystem__GC0,
-logic__5732: RocketTile__GCB0,
-case__866: RocketTile__GCB0,
-logic__6620: RocketTile__GCB0,
-logic__5561: RocketTile__GCB0,
-case__1050: VCU118RocketSystem__GC0,
-case__1321: APBGpsBlock__GC0,
-reg__689: RocketTile__GCB0,
-logic__5345: RocketTile__GCB0,
-logic__1298: VCU118RocketSystem__GC0,
-datapath__207: VCU118RocketSystem__GC0,
-CLINT: VCU118RocketSystem__GC0,
-reg__168: VCU118RocketSystem__GC0,
-reg__456: FPU__GB0,
-logic__972: VCU118RocketSystem__GC0,
-logic__6004: RocketTile__GCB0,
-logic__5366: RocketTile__GCB0,
-case__1112: VCU118RocketSystem__GC0,
-logic__5607: RocketTile__GCB0,
-logic__6789: VCU118RocketSystem__GC0,
-logic__1657: VCU118RocketSystem__GC0,
-logic__2095: RocketTile__GCB0,
-reg__610: FPU__GB1,
-logic__6691: RocketTile__GCB0,
-reg__831: RocketTile__GCB0,
-datapath__47: VCU118RocketSystem__GC0,
-logic__6190: RocketTile__GCB0,
-logic__5940: RocketTile__GCB0,
-logic__3857: FPU__GB2,
-logic__1453: VCU118RocketSystem__GC0,
-logic__8817: tracking_wrapper,
-muxpart__234: FPU__GB0,
-logic__2600: DCache,
-logic__3304: FPU__GB1,
-reg__1042: VCU118RocketSystem__GC0,
-logic__7480: VCU118RocketSystem__GC0,
-logic__3763: FPU__GB2,
-logic__8443: APBGpsBlock__GC0,
-logic__4427: FPU__GB1,
-case__440: VCU118RocketSystem__GC0,
-logic__1474: VCU118RocketSystem__GC0,
-logic__5411: RocketTile__GCB0,
-reg__736: RocketTile__GCB0,
-logic__5766: RocketTile__GCB0,
-datapath__393: FPU__GB2,
-logic__4782: FPU__GB2,
-case__1681: TLToAPB,
-case__1009: VCU118RocketSystem__GC0,
-logic__6671: RocketTile__GCB0,
-logic__2914: DCache,
-logic__2220: DCache,
-logic__7173: VCU118RocketSystem__GC0,
-logic__1316: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-IntSyncSyncCrossingSink_n1x1: TilePRCIDomain__GC0,
-logic__790: VCU118RocketSystem__GC0,
-case__1028: VCU118RocketSystem__GC0,
-logic__4483: FPU__GB1,
-reg__126: VCU118RocketSystem__GC0,
-case__269: VCU118RocketSystem__GC0,
-muxpart__34: vcu118_rocket_top__GC0,
-case__1542: tracking_wrapper,
-logic__3606: FPU__GB2, FPU__GB1,
-case__416: VCU118RocketSystem__GC0,
-logic__2098: RocketTile__GCB0,
-logic__3329: FPU__GB1,
-logic__6349: RocketTile__GCB0,
-muxpart__183: RocketTile__GCB0,
-logic__2601: DCache,
-reg__1069: APBGpsBlock__GC0, tracking_wrapper,
-reg__584: FPU__GB2,
-logic__4302: FPU__GB1,
-case__153: vcu118_rocket_top__GC0,
-logic__7679: VCU118RocketSystem__GC0,
-reg__274: VCU118RocketSystem__GC0,
-reg__648: FPU__GB1,
-logic__5301: RocketTile__GCB0,
-reg__1336: tracking_wrapper,
-logic__2517: RocketTile__GCB0, DCache,
-reg__1047: VCU118RocketSystem__GC0,
-case__1022: VCU118RocketSystem__GC0,
-reg__1264: tracking_wrapper,
-datapath__100: VCU118RocketSystem__GC0,
-logic__5284: RocketTile__GCB0,
-logic__9127: tracking_wrapper,
-case__218: vcu118_rocket_top__GC0,
-gig_ethernet_pcs_pma_0: vcu118_rocket_top__GC0,
-logic__2010: VCU118RocketSystem__GC0,
-logic__1175: VCU118RocketSystem__GC0,
-logic__3257: RocketTile__GCB0,
-reg__1221: tracking_wrapper,
-reg__1194: APBGpsBlock__GC0,
-case__1496: APBGpsBlock__GC0,
-logic__7514: VCU118RocketSystem__GC0,
-TLXbar_fbus_i1_o1_a32d64s1k1z4u: VCU118RocketSystem__GC0,
-logic__4388: FPU__GB1,
-reg__300: VCU118RocketSystem__GC0,
-logic__6648: RocketTile__GCB0,
-logic__5982: RocketTile__GCB0,
-logic__4862: FPU__GB2,
-reg__1160: APBGpsBlock__GC0,
-reg__1179: APBGpsBlock__GC0,
-keep__3: vcu118_rocket_top__GC0,
-logic__137: vcu118_rocket_top__GC0,
-logic__2686: DCache,
-logic__7402: VCU118RocketSystem__GC0,
-case__835: RocketTile__GCB0,
-case__1587: tracking_wrapper,
-reg__1149: APBGpsBlock__GC0,
-datapath__197: VCU118RocketSystem__GC0,
-case__132: vcu118_rocket_top__GC0,
-case__486: RocketTile__GCB0,
-logic__7155: VCU118RocketSystem__GC0,
-case__856: RocketTile__GCB0,
-logic__4174: FPU__GB1,
-datapath__669: tracking_wrapper,
-reg__1033: VCU118RocketSystem__GC0,
-logic__1361: VCU118RocketSystem__GC0,
-logic__5603: RocketTile__GCB0,
-dual_port_bram__parameterized1: APBGpsBlock__GC0,
-muxpart__224: FPU__GB0,
-reg__433: RocketTile__GCB0,
-logic__6596: RocketTile__GCB0,
-logic__5054: FPU__GB1,
-logic__791: VCU118RocketSystem__GC0,
-logic__1982: VCU118RocketSystem__GC0,
-logic__9180: tracking_wrapper,
-logic__7821: VCU118RocketSystem__GC0,
-case__1569: tracking_wrapper,
-logic__9017: tracking_wrapper,
-logic__766: VCU118RocketSystem__GC0,
-datapath__471: RocketTile__GCB0,
-case__471: VCU118RocketSystem__GC0,
-logic__8764: APBGpsBlock__GC0,
-datapath__605: APBGpsBlock__GC0,
-case__484: RocketTile__GCB0,
-datapath__89: VCU118RocketSystem__GC0,
-muxpart__276: VCU118RocketSystem__GC0,
-datapath__336: FPU__GB2,
-reg__812: RocketTile__GCB0,
-logic__6651: RocketTile__GCB0,
-datapath__627: APBGpsBlock__GC0,
-datapath__399: FPU__GB2,
-datapath__660: tracking_wrapper,
-datapath__127: VCU118RocketSystem__GC0,
-logic__1043: VCU118RocketSystem__GC0,
-logic__5166: FPU__GB1,
-logic__5754: RocketTile__GCB0,
-datapath__701: tracking_wrapper,
-logic__7403: VCU118RocketSystem__GC0,
-case__862: RocketTile__GCB0,
-logic__1875: VCU118RocketSystem__GC0,
-case__1367: APBGpsBlock__GC0,
-case__370: VCU118RocketSystem__GC0,
-reg__189: VCU118RocketSystem__GC0,
-reg__160: VCU118RocketSystem__GC0,
-logic__5872: RocketTile__GCB0,
-reg__341: DCache,
-counter__3: vcu118_rocket_top__GC0,
-logic__882: VCU118RocketSystem__GC0,
-case__1004: VCU118RocketSystem__GC0,
-datapath__241: VCU118RocketSystem__GC0,
-reg__399: RocketTile__GCB0,
-reg__1311: tracking_wrapper,
-case__291: VCU118RocketSystem__GC0,
-reg__85: vcu118_rocket_top__GC0,
-logic__2536: RocketTile__GCB0, DCache,
-reg__298: VCU118RocketSystem__GC0,
-reg__265: VCU118RocketSystem__GC0,
-logic__683: vcu118_rocket_top__GC0,
-logic__6041: RocketTile__GCB0,
-logic__2885: DCache,
-logic__4829: FPU__GB2,
-logic__1786: VCU118RocketSystem__GC0,
-logic__9210: tracking_wrapper,
-case__1388: APBGpsBlock__GC0,
-case__1559: tracking_wrapper,
-logic__1120: VCU118RocketSystem__GC0,
-reg__158: VCU118RocketSystem__GC0,
-logic__3635: FPU__GB2, FPU__GB1,
-datapath__80: VCU118RocketSystem__GC0,
-logic__6914: VCU118RocketSystem__GC0,
-case__1479: APBGpsBlock__GC0,
-logic__6690: RocketTile__GCB0,
-case__124: vcu118_rocket_top__GC0,
-reg__833: RocketTile__GCB0,
-reg__1346: tracking_wrapper,
-reg__396: RocketTile__GCB0,
-logic__4578: FPU__GB2, FPU__GB1,
-logic__465: vcu118_rocket_top__GC0,
-case__306: VCU118RocketSystem__GC0,
-logic__3275: RocketTile__GCB0,
-logic__5979: RocketTile__GCB0,
-reg__1228: tracking_wrapper,
-case__31: vcu118_rocket_top__GC0,
-logic__4834: FPU__GB2,
-logic__716: vcu118_rocket_top__GC0,
-logic__2183: DCache,
-case__197: vcu118_rocket_top__GC0,
-muxpart__198: FPU__GB0,
-case__338: VCU118RocketSystem__GC0,
-logic__2754: DCache,
-logic__8241: VCU118RocketSystem__GC0,
-logic__7887: VCU118RocketSystem__GC0,
-logic__6027: RocketTile__GCB0,
-case__1570: tracking_wrapper,
-logic__3045: RocketTile__GCB0,
-logic__5074: FPU__GB1,
-logic__4286: FPU__GB1,
-logic__6715: RocketTile__GCB0,
-ClockCrossingReg_w15: VCU118RocketSystem__GC0,
-logic__930: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__972: VCU118RocketSystem__GC0,
-logic__4987: FPU__GB1,
-case__23: vcu118_rocket_top__GC0,
-case__326: VCU118RocketSystem__GC0,
-muxpart__15: vcu118_rocket_top__GC0,
-reg__630: FPU__GB1,
-case__1425: APBGpsBlock__GC0,
-logic__2957: DCache,
-case__954: RocketTile__GCB0,
-case__670: FPU__GB2,
-reg__88: vcu118_rocket_top__GC0,
-logic__4477: FPU__GB1,
-case__1505: APBGpsBlock__GC0,
-reg__757: RocketTile__GCB0,
-reg__1051: VCU118RocketSystem__GC0,
-reg__753: RocketTile__GCB0,
-reg__821: RocketTile__GCB0,
-case__711: FPU__GB1,
-logic__9387: APBGpsBlock__GC0,
-datapath__366: FPU__GB1,
-logic__4970: FPU__GB1,
-logic__6678: RocketTile__GCB0,
-reg__1027: VCU118RocketSystem__GC0,
-reg__986: VCU118RocketSystem__GC0,
-reg__453: FPU__GB0,
-reg__468: FPU__GB0,
-case__1656: tracking_wrapper,
-logic__5646: RocketTile__GCB0,
-logic__8826: tracking_wrapper,
-datapath__522: VCU118RocketSystem__GC0,
-reg__206: VCU118RocketSystem__GC0,
-Queue2_TLBundleA_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4422: FPU__GB1,
-logic__6165: RocketTile__GCB0,
-reg__487: FPU__GB1,
-reg__651: RocketTile__GCB0,
-case__1416: APBGpsBlock__GC0,
-logic__8170: VCU118RocketSystem__GC0,
-logic__5956: RocketTile__GCB0,
-logic__3418: FPU__GB1,
-logic__7581: VCU118RocketSystem__GC0,
-logic__4278: FPU__GB1,
-logic__8526: APBGpsBlock__GC0,
-datapath__590: APBGpsBlock__GC0,
-case__1170: VCU118RocketSystem__GC0,
-logic__7758: VCU118RocketSystem__GC0,
-datapath__645: APBGpsBlock__GC0,
-case__1103: VCU118RocketSystem__GC0,
-datapath__161: VCU118RocketSystem__GC0,
-logic__4921: FPU__GB2,
-case__307: VCU118RocketSystem__GC0,
-logic__2521: RocketTile__GCB0, DCache,
-datapath__64: VCU118RocketSystem__GC0,
-logic__300: vcu118_rocket_top__GC0,
-reg__1010: VCU118RocketSystem__GC0,
-case__216: vcu118_rocket_top__GC0,
-logic__90: vcu118_rocket_top__GC0,
-datapath__378: FPU__GB1,
-reg__475: FPU__GB0,
-logic__4802: FPU__GB2,
-logic__4326: FPU__GB1,
-case__240: VCU118RocketSystem__GC0,
-case__1580: tracking_wrapper,
-logic__6688: RocketTile__GCB0,
-datapath__728: VCU118RocketSystem__GC0,
-logic__8956: tracking_wrapper,
-logic__8930: tracking_wrapper,
-case__133: vcu118_rocket_top__GC0,
-reg__50: vcu118_rocket_top__GC0,
-logic__3535: FPU__GB1,
-logic__65: vcu118_rocket_top__GC0,
-datapath__665: tracking_wrapper,
-datapath__240: VCU118RocketSystem__GC0,
-logic__4418: FPU__GB1,
-logic__8281: APBGpsBlock__GC0,
-case__494: RocketTile__GCB0,
-datapath__354: FPU__GB2,
-case__709: FPU__GB1,
-case__1282: APBGpsBlock__GC0,
-logic__8216: VCU118RocketSystem__GC0,
-rom__7: tracking_wrapper,
-logic__1261: VCU118RocketSystem__GC0,
-logic__5249: RocketTile__GCB0,
-datapath__461: RocketTile__GCB0,
-reg__666: RocketTile__GCB0,
-logic__6988: VCU118RocketSystem__GC0,
-logic__7538: VCU118RocketSystem__GC0,
-logic__3586: FPU__GB2, FPU__GB1,
-logic__958: VCU118RocketSystem__GC0,
-logic__4086: FPU__GB2,
-logic__173: vcu118_rocket_top__GC0,
-datapath__433: RocketTile__GCB0,
-reg__439: RocketTile__GCB0,
-case__605: RocketTile__GCB0,
-reg__120: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4246: FPU__GB1,
-TLFIFOFixer_2: VCU118RocketSystem__GC0,
-reg__604: FPU__GB1,
-case__1612: tracking_wrapper,
-logic__7882: VCU118RocketSystem__GC0,
-logic__4593: FPU__GB2, FPU__GB1,
-case__308: VCU118RocketSystem__GC0,
-case__1070: VCU118RocketSystem__GC0,
-logic__3863: FPU__GB2,
-logic__6792: VCU118RocketSystem__GC0,
-case__1177: VCU118RocketSystem__GC0,
-logic__1570: VCU118RocketSystem__GC0,
-logic__6115: RocketTile__GCB0,
-logic__7335: VCU118RocketSystem__GC0,
-case__740: FPU__GB2,
-logic__4684: FPU__GB2,
-logic__3846: FPU__GB2,
-addsub__5: tracking_wrapper,
-logic__1740: VCU118RocketSystem__GC0,
-logic__7182: VCU118RocketSystem__GC0,
-logic__9139: tracking_wrapper,
-reg__1115: APBGpsBlock__GC0,
-logic__5508: RocketTile__GCB0,
-reg__232: VCU118RocketSystem__GC0,
-datapath__109: VCU118RocketSystem__GC0,
-TLXbar_sbus_i2_o1_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__6097: RocketTile__GCB0,
-case__857: RocketTile__GCB0,
-case__1199: VCU118RocketSystem__GC0,
-logic__3060: RocketTile__GCB0,
-case__745: FPU__GB2,
-case__584: RocketTile__GCB0,
-logic__319: vcu118_rocket_top__GC0,
-reg__1011: VCU118RocketSystem__GC0,
-case__1114: VCU118RocketSystem__GC0,
-reg__948: VCU118RocketSystem__GC0,
-muxpart__99: vcu118_rocket_top__GC0,
-datapath__245: VCU118RocketSystem__GC0,
-muxpart__12: vcu118_rocket_top__GC0,
-datapath__484: RocketTile__GCB0,
-case__1361: APBGpsBlock__GC0,
-reg__450: FPU__GB0,
-logic__9423: APBGpsBlock__GC0,
-reg__159: VCU118RocketSystem__GC0,
-logic__965: VCU118RocketSystem__GC0,
-logic__6098: RocketTile__GCB0,
-case__1512: APBGpsBlock__GC0,
-logic__2808: DCache,
-datapath__434: RocketTile__GCB0,
-case__805: FPU__GB1,
-reg__1048: VCU118RocketSystem__GC0,
-logic__4747: FPU__GB2,
-logic__6686: RocketTile__GCB0,
-logic__6858: VCU118RocketSystem__GC0,
-logic__1351: VCU118RocketSystem__GC0,
-logic__4530: FPU__GB1,
-datapath__296: RocketTile__GCB0,
-logic__1674: VCU118RocketSystem__GC0,
-case__587: RocketTile__GCB0,
-logic__4928: FPU__GB2,
-logic__5439: RocketTile__GCB0,
-logic__3190: RocketTile__GCB0,
-logic__3308: FPU__GB1,
-logic__6184: RocketTile__GCB0,
-datapath__667: tracking_wrapper,
-reg__936: VCU118RocketSystem__GC0,
-logic__4639: FPU__GB2, FPU__GB1,
-datapath__364: FPU__GB2,
-logic__8770: APBGpsBlock__GC0,
-case__1093: VCU118RocketSystem__GC0,
-muxpart__227: FPU__GB0,
-reg__1349: tracking_wrapper,
-case__1116: VCU118RocketSystem__GC0,
-datapath__70: VCU118RocketSystem__GC0,
-logic__4033: FPU__GB2,
-logic__773: VCU118RocketSystem__GC0,
-reg__107: VCU118RocketSystem__GC0,
-vcu118_rocket_top__GC0: vcu118_rocket_top__GC0,
-datapath__524: VCU118RocketSystem__GC0,
-logic__8932: tracking_wrapper,
-reg__593: FPU__GB2,
-logic__3629: FPU__GB2, FPU__GB1,
-case__178: vcu118_rocket_top__GC0,
-logic__1665: VCU118RocketSystem__GC0,
-logic__6068: RocketTile__GCB0,
-logic__3037: RocketTile__GCB0,
-logic__5583: RocketTile__GCB0,
-logic__9052: tracking_wrapper,
-case__1229: VCU118RocketSystem__GC0,
-reg__1283: tracking_wrapper,
-logic__8928: tracking_wrapper,
-Queue2_TLBundleD_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__1864: VCU118RocketSystem__GC0,
-logic__2938: DCache,
-case__1375: APBGpsBlock__GC0,
-FixedClockBroadcast_4: VCU118RocketSystem__GC0,
-logic__4445: FPU__GB1,
-case__540: DCache,
-muxpart__182: RocketTile__GCB0,
-case__889: RocketTile__GCB0,
-logic__69: vcu118_rocket_top__GC0,
-logic__4863: FPU__GB2,
-reg__555: FPU__GB1,
-logic__1436: VCU118RocketSystem__GC0,
-logic__1037: VCU118RocketSystem__GC0,
-case__1174: VCU118RocketSystem__GC0,
-logic__5341: RocketTile__GCB0,
-muxpart__82: vcu118_rocket_top__GC0,
-reg__186: VCU118RocketSystem__GC0,
-logic__4036: FPU__GB2,
-ram__1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__7062: VCU118RocketSystem__GC0,
-case__488: RocketTile__GCB0,
-reg__463: FPU__GB0,
-logic__2812: DCache,
-reg__243: VCU118RocketSystem__GC0,
-logic__6567: RocketTile__GCB0,
-logic__5542: RocketTile__GCB0,
-ram__6: RocketTile__GCB0,
-logic__814: VCU118RocketSystem__GC0,
-logic__9348: tracking_wrapper,
-case__826: RocketTile__GCB0,
-datapath__559: APBGpsBlock__GC0,
-reg__749: RocketTile__GCB0,
-reg__12: vcu118_rocket_top__GC0,
-logic__7735: VCU118RocketSystem__GC0,
-reg__329: DCache,
-case__217: vcu118_rocket_top__GC0,
-logic__3307: FPU__GB1,
-logic__7002: VCU118RocketSystem__GC0,
-reg__109: VCU118RocketSystem__GC0,
-reg__946: VCU118RocketSystem__GC0,
-reg__238: VCU118RocketSystem__GC0,
-reg__777: RocketTile__GCB0,
-logic__2445: DCache,
-reg__1035: VCU118RocketSystem__GC0,
-logic__3001: RocketTile__GCB0,
-logic__3698: FPU__GB2,
-logic__8543: APBGpsBlock__GC0,
-logic__6563: RocketTile__GCB0,
-logic__6076: RocketTile__GCB0,
-logic__2238: DCache,
-case__455: VCU118RocketSystem__GC0,
-reg__442: RocketTile__GCB0,
-logic__9429: APBGpsBlock__GC0,
-case__1600: tracking_wrapper,
-reg__687: RocketTile__GCB0,
-datapath__222: VCU118RocketSystem__GC0,
-logic__2127: RocketTile__GCB0,
-case__1492: APBGpsBlock__GC0,
-datapath__575: APBGpsBlock__GC0,
-logic__8854: tracking_wrapper,
-logic__9163: tracking_wrapper,
-reg__780: RocketTile__GCB0,
-case__852: RocketTile__GCB0,
-logic__174: vcu118_rocket_top__GC0,
-reg__440: RocketTile__GCB0,
-logic__408: vcu118_rocket_top__GC0,
-logic__6837: VCU118RocketSystem__GC0,
-logic__1350: VCU118RocketSystem__GC0,
-logic__1291: VCU118RocketSystem__GC0,
-logic__4978: FPU__GB1,
-reg__1333: tracking_wrapper,
-reg__392: RocketTile__GCB0,
-reg__1056: VCU118RocketSystem__GC0,
-muxpart__254: FPU__GB2,
-logic__5964: RocketTile__GCB0,
-logic__9176: tracking_wrapper,
-case__730: FPU__GB2, FPU__GB1,
-logic__3621: FPU__GB2, FPU__GB1,
-logic__5601: RocketTile__GCB0,
-logic__5829: RocketTile__GCB0,
-logic__3310: FPU__GB1,
-case__501: RocketTile__GCB0,
-case__333: VCU118RocketSystem__GC0,
-logic__1625: VCU118RocketSystem__GC0,
-muxpart__6: vcu118_rocket_top__GC0,
-logic__9431: TLToAPB,
-case__1094: VCU118RocketSystem__GC0,
-case__437: VCU118RocketSystem__GC0,
-reg__1062: VCU118RocketSystem__GC0,
-case__1168: VCU118RocketSystem__GC0,
-datapath__188: VCU118RocketSystem__GC0,
-case__1180: VCU118RocketSystem__GC0,
-datapath__310: RocketTile__GCB0,
-logic__6072: RocketTile__GCB0,
-logic__4689: FPU__GB2,
-reg__364: DCache,
-logic__7187: VCU118RocketSystem__GC0,
-case__754: FPU__GB2,
-logic__7685: VCU118RocketSystem__GC0,
-case__331: VCU118RocketSystem__GC0,
-reg__1375: tracking_wrapper,
-logic__740: vcu118_rocket_top__GC0,
-reg__573: FPU__GB2,
-logic__7900: VCU118RocketSystem__GC0,
-logic__4599: FPU__GB2, FPU__GB1,
-logic__2878: DCache,
-case__1281: APBGpsBlock__GC0,
-datapath__166: VCU118RocketSystem__GC0,
-logic__5666: RocketTile__GCB0,
-plusarg_reader: RocketTile__GCB0,
-muxpart__367: tracking_wrapper,
-case__921: RocketTile__GCB0,
-logic__7283: VCU118RocketSystem__GC0,
-muxpart__264: RocketTile__GCB0,
-datapath__301: RocketTile__GCB0,
-case__978: RocketTile__GCB0,
-logic__6077: RocketTile__GCB0,
-logic__6344: RocketTile__GCB0,
-logic__2017: VCU118RocketSystem__GC0,
-logic__1176: VCU118RocketSystem__GC0,
-logic__952: VCU118RocketSystem__GC0,
-datapath__617: APBGpsBlock__GC0,
-logic__5566: RocketTile__GCB0,
-logic__9470: vcu118_rocket_top__GC0,
-DMIToTL: VCU118RocketSystem__GC0,
-case__1664: tracking_wrapper,
-logic__4934: FPU__GB2,
-logic__5346: RocketTile__GCB0,
-logic__5825: RocketTile__GCB0,
-reg__451: FPU__GB0,
-logic__5536: RocketTile__GCB0,
-case__1036: VCU118RocketSystem__GC0,
-logic__7851: VCU118RocketSystem__GC0,
-case__689: FPU__GB2,
-logic__6994: VCU118RocketSystem__GC0,
-case__255: VCU118RocketSystem__GC0,
-logic__6698: RocketTile__GCB0,
-logic__1406: VCU118RocketSystem__GC0,
-reg__787: RocketTile__GCB0,
-logic__8746: APBGpsBlock__GC0,
-logic__5976: RocketTile__GCB0,
-reg__1085: APBGpsBlock__GC0,
-logic__1040: VCU118RocketSystem__GC0,
-case__241: VCU118RocketSystem__GC0,
-reg__608: FPU__GB1,
-reg__595: FPU__GB2,
-case__797: FPU__GB1,
-reg__361: DCache,
-muxpart__377: tracking_wrapper,
-datapath__694: tracking_wrapper,
-reg__1207: tracking_wrapper,
-logic__3740: FPU__GB2,
-logic__3299: FPU__GB1,
-reg__499: FPU__GB1,
-logic__9132: tracking_wrapper,
-logic__6626: RocketTile__GCB0,
-logic__6868: VCU118RocketSystem__GC0,
-logic__5621: RocketTile__GCB0,
-datapath__673: tracking_wrapper,
-reg__621: FPU__GB1,
-case__335: VCU118RocketSystem__GC0,
-datapath__651: APBGpsBlock__GC0,
-logic__6661: RocketTile__GCB0,
-dsp48e2__39: tracking_wrapper,
-ErrorDeviceWrapper: VCU118RocketSystem__GC0,
-logic__3413: FPU__GB1,
-datapath__154: VCU118RocketSystem__GC0,
-logic__5358: RocketTile__GCB0,
-logic__5300: RocketTile__GCB0,
-eth_rf_async_fifo: vcu118_rocket_top__GC0,
-reg__1128: APBGpsBlock__GC0,
-logic__9135: tracking_wrapper,
-muxpart__56: vcu118_rocket_top__GC0,
-reg__378: RocketTile__GCB0,
-logic__5137: FPU__GB1,
-case__874: RocketTile__GCB0,
-logic__7801: VCU118RocketSystem__GC0,
-logic__2451: DCache,
-logic__9126: tracking_wrapper,
-reg__261: VCU118RocketSystem__GC0,
-logic__3264: RocketTile__GCB0,
-case__1129: VCU118RocketSystem__GC0,
-muxpart__185: FPU__GB0,
-reg__1007: VCU118RocketSystem__GC0,
-logic__1748: VCU118RocketSystem__GC0,
-logic__2172: DCache,
-case__778: FPU__GB1,
-logic__1895: VCU118RocketSystem__GC0,
-datapath__646: APBGpsBlock__GC0,
-case__224: VCU118RocketSystem__GC0,
-reg__1186: APBGpsBlock__GC0,
-logic__4867: FPU__GB2,
-logic__4465: FPU__GB1,
-case__40: vcu118_rocket_top__GC0,
-logic__6034: RocketTile__GCB0,
-reg__518: FPU__GB2,
-logic__6943: VCU118RocketSystem__GC0,
-logic__4314: FPU__GB1,
-case__1214: VCU118RocketSystem__GC0,
-reg__155: VCU118RocketSystem__GC0,
-logic__7839: VCU118RocketSystem__GC0,
-case__74: vcu118_rocket_top__GC0,
-muxpart__94: vcu118_rocket_top__GC0,
-datapath__586: APBGpsBlock__GC0,
-logic__7999: VCU118RocketSystem__GC0,
-logic__2497: RocketTile__GCB0, DCache,
-case__1417: APBGpsBlock__GC0,
-logic__3121: RocketTile__GCB0,
-logic__5734: RocketTile__GCB0,
-logic__7119: VCU118RocketSystem__GC0,
-logic__6632: RocketTile__GCB0,
-muxpart__375: tracking_wrapper,
-case__363: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_fbus_from_debug_sb: VCU118RocketSystem__GC0,
-case__974: RocketTile__GCB0,
-case__357: VCU118RocketSystem__GC0,
-datapath__400: FPU__GB2,
-case__825: RocketTile__GCB0,
-case__17: vcu118_rocket_top__GC0,
-logic__7716: VCU118RocketSystem__GC0,
-case__822: RocketTile__GCB0,
-logic__3023: RocketTile__GCB0,
-logic__9439: TLToAPB,
-reg__39: vcu118_rocket_top__GC0,
-logic__6170: RocketTile__GCB0,
-logic__3764: FPU__GB2,
-logic__978: VCU118RocketSystem__GC0,
-reg__119: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__832: RocketTile__GCB0,
-case__879: RocketTile__GCB0,
-logic__7011: VCU118RocketSystem__GC0,
-reg__1136: APBGpsBlock__GC0,
-logic__4986: FPU__GB1,
-reg__1256: tracking_wrapper,
-logic__5538: RocketTile__GCB0,
-logic__5752: RocketTile__GCB0,
-logic__2044: VCU118RocketSystem__GC0,
-logic__1393: VCU118RocketSystem__GC0,
-case__147: vcu118_rocket_top__GC0,
-logic__4486: FPU__GB1,
-case__63: vcu118_rocket_top__GC0,
-logic__7022: VCU118RocketSystem__GC0,
-logic__3643: FPU__GB2, FPU__GB1,
-logic__1465: VCU118RocketSystem__GC0,
-dsp48e2__22: APBGpsBlock__GC0,
-case__1169: VCU118RocketSystem__GC0,
-case__1115: VCU118RocketSystem__GC0,
-logic__3890: FPU__GB2,
-logic__7686: VCU118RocketSystem__GC0,
-reg__939: VCU118RocketSystem__GC0,
-logic__2554: DCache,
-logic__2940: DCache,
-case__1414: APBGpsBlock__GC0,
-logic__9315: tracking_wrapper,
-reg__449: FPU__GB0,
-reg__1057: VCU118RocketSystem__GC0,
-logic__8844: tracking_wrapper,
-reg__632: FPU__GB1,
-logic__1123: VCU118RocketSystem__GC0,
-logic__5686: RocketTile__GCB0,
-datapath__267: RocketTile__GCB0,
-reg__1006: VCU118RocketSystem__GC0,
-TLXbar_pbus_in_i1_o1_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__1537: VCU118RocketSystem__GC0,
-logic__7299: VCU118RocketSystem__GC0,
-logic__1693: VCU118RocketSystem__GC0,
-case__884: RocketTile__GCB0,
-dsp48e2__5: APBGpsBlock__GC0,
-logic__7024: VCU118RocketSystem__GC0,
-case__1662: tracking_wrapper,
-case__497: RocketTile__GCB0,
-case__7: vcu118_rocket_top__GC0,
-logic__7346: VCU118RocketSystem__GC0,
-logic__9191: tracking_wrapper,
-case__1213: VCU118RocketSystem__GC0,
-reg__896: VCU118RocketSystem__GC0,
-logic__2555: DCache,
-case__491: RocketTile__GCB0,
-logic__1869: VCU118RocketSystem__GC0,
-datapath__220: VCU118RocketSystem__GC0,
-logic__8595: APBGpsBlock__GC0,
-reg__144: VCU118RocketSystem__GC0,
-case__1278: APBGpsBlock__GC0,
-case__1119: VCU118RocketSystem__GC0,
-logic__858: VCU118RocketSystem__GC0,
-reg__843: RocketTile__GCB0,
-bram__parameterized0: APBGpsBlock__GC0,
-logic__7300: VCU118RocketSystem__GC0,
-reg__878: VCU118RocketSystem__GC0,
-datapath__199: VCU118RocketSystem__GC0,
-reg__237: VCU118RocketSystem__GC0,
-logic__4744: FPU__GB2,
-logic__4312: FPU__GB1,
-datapath__534: VCU118RocketSystem__GC0,
-case__721: FPU__GB1,
-logic__3321: FPU__GB1,
-reg__628: FPU__GB1,
-logic__5429: RocketTile__GCB0,
-datapath__684: tracking_wrapper,
-dsp48e2__35: tracking_wrapper,
-logic__72: vcu118_rocket_top__GC0,
-reg__1041: VCU118RocketSystem__GC0,
-reg__146: VCU118RocketSystem__GC0,
-extram__8: APBGpsBlock__GC0,
-logic__4111: FPU__GB2,
-reg__72: vcu118_rocket_top__GC0,
-logic__4415: FPU__GB1,
-reg__464: FPU__GB0,
-logic__909: VCU118RocketSystem__GC0,
-logic__9373: tracking_wrapper,
-reg__141: VCU118RocketSystem__GC0,
-logic__9329: tracking_wrapper,
-case__64: vcu118_rocket_top__GC0,
-case__575: RocketTile__GCB0,
-case__1120: VCU118RocketSystem__GC0,
-logic__1237: VCU118RocketSystem__GC0,
-logic__6075: RocketTile__GCB0,
-reg__1227: tracking_wrapper,
-logic__2523: RocketTile__GCB0, DCache,
-reg__400: RocketTile__GCB0,
-logic__5847: RocketTile__GCB0,
-logic__9279: tracking_wrapper,
-logic__6922: VCU118RocketSystem__GC0,
-case__528: DCache,
-reg__42: vcu118_rocket_top__GC0,
-logic__3534: FPU__GB1,
-datapath__112: VCU118RocketSystem__GC0,
-datapath__382: FPU__GB1,
-logic__8135: VCU118RocketSystem__GC0,
-case__131: vcu118_rocket_top__GC0,
-divider_fsm: APBGpsBlock__GC0,
-muxpart__357: APBGpsBlock__GC0,
-datapath__397: FPU__GB2,
-logic__5631: RocketTile__GCB0,
-logic__6113: RocketTile__GCB0,
-reg__1181: APBGpsBlock__GC0,
-logic__4914: FPU__GB2,
-logic__7428: VCU118RocketSystem__GC0,
-logic__9046: tracking_wrapper,
-case__782: FPU__GB2,
-case__543: DCache,
-logic__2868: DCache,
-logic__1249: VCU118RocketSystem__GC0,
-datapath__139: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__3632: FPU__GB2, FPU__GB1,
-case__1257: APBGpsBlock__GC0,
-reg__418: RocketTile__GCB0,
-case__602: RocketTile__GCB0,
-case__873: RocketTile__GCB0,
-datapath__192: VCU118RocketSystem__GC0,
-logic__8473: APBGpsBlock__GC0,
-logic__1174: VCU118RocketSystem__GC0,
-reg__1109: APBGpsBlock__GC0,
-dsp48e2__32: tracking_wrapper,
-datapath__647: APBGpsBlock__GC0,
-logic__8036: VCU118RocketSystem__GC0,
-logic__1247: VCU118RocketSystem__GC0,
-reg__454: FPU__GB0,
-reg__1126: APBGpsBlock__GC0,
-datapath__720: tracking_wrapper,
-logic__3295: FPU__GB1,
-eth_rf_core: vcu118_rocket_top__GC0,
-logic__5239: RocketTile__GCB0,
-case__1548: tracking_wrapper,
-Queue1_TLBundleA_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-case__294: VCU118RocketSystem__GC0,
-reg__1118: APBGpsBlock__GC0,
-logic__264: vcu118_rocket_top__GC0,
-case__695: FPU__GB2,
-reg__1345: tracking_wrapper,
-muxpart__57: vcu118_rocket_top__GC0,
-logic__1349: VCU118RocketSystem__GC0,
-logic__919: VCU118RocketSystem__GC0,
-case__746: FPU__GB2,
-reg__774: RocketTile__GCB0,
-logic__2376: DCache,
-FPU__GB2: FPU__GB2,
-logic__6861: VCU118RocketSystem__GC0,
-logic__357: vcu118_rocket_top__GC0,
-reg__616: FPU__GB1,
-logic__7815: VCU118RocketSystem__GC0,
-logic__2652: DCache,
-logic__7179: VCU118RocketSystem__GC0,
-case__526: DCache,
-case__29: vcu118_rocket_top__GC0,
-datapath__604: APBGpsBlock__GC0,
-logic__9167: tracking_wrapper,
-case__536: DCache,
-extrom: APBGpsBlock__GC0,
-case__979: RocketTile__GCB0,
-datapath__95: VCU118RocketSystem__GC0,
-logic__5125: FPU__GB1,
-reg__1107: APBGpsBlock__GC0,
-case__1113: VCU118RocketSystem__GC0,
-logic__4969: FPU__GB1,
-reg__212: VCU118RocketSystem__GC0,
-logic__1169: VCU118RocketSystem__GC0,
-case__1002: VCU118RocketSystem__GC0,
-logic__2001: VCU118RocketSystem__GC0,
-logic__1667: VCU118RocketSystem__GC0,
-case__236: VCU118RocketSystem__GC0,
-logic__8213: VCU118RocketSystem__GC0,
-reg__282: VCU118RocketSystem__GC0,
-logic__3638: FPU__GB2, FPU__GB1,
-logic__2377: DCache,
-logic__9051: tracking_wrapper,
-case__336: VCU118RocketSystem__GC0,
-reg__547: FPU__GB1,
-reg__376: RocketTile__GCB0,
-bram: APBGpsBlock__GC0,
-case__657: FPU__GB2, FPU__GB1,
-logic__2245: DCache,
-logic__1487: VCU118RocketSystem__GC0,
-datapath__700: tracking_wrapper,
-logic__9391: APBGpsBlock__GC0,
-reg__358: DCache,
-reg__996: VCU118RocketSystem__GC0,
-reg__766: RocketTile__GCB0,
-logic__5426: RocketTile__GCB0,
-reg__1334: tracking_wrapper,
-logic__9334: tracking_wrapper,
-logic__4283: FPU__GB1,
-reg__1328: tracking_wrapper,
-logic__3182: RocketTile__GCB0,
-logic__4607: FPU__GB2, FPU__GB1,
-reg__671: RocketTile__GCB0,
-logic__7327: VCU118RocketSystem__GC0,
-logic__1628: VCU118RocketSystem__GC0,
-datapath__557: APBGpsBlock__GC0,
-reg__823: RocketTile__GCB0,
-datapath__337: FPU__GB2,
-logic__4610: FPU__GB2, FPU__GB1,
-datapath__48: VCU118RocketSystem__GC0,
-datapath__618: APBGpsBlock__GC0,
-case__432: VCU118RocketSystem__GC0,
-case__714: FPU__GB1,
-case__532: DCache,
-datapath__239: VCU118RocketSystem__GC0,
-logic__6851: VCU118RocketSystem__GC0,
-logic__926: VCU118RocketSystem__GC0,
-case__282: VCU118RocketSystem__GC0,
-reg__765: RocketTile__GCB0,
-logic__82: vcu118_rocket_top__GC0,
-logic__9461: TLToAPB,
-TLFragmenter_1: RocketTile__GCB0,
-logic__4659: FPU__GB2, FPU__GB1,
-logic__8600: APBGpsBlock__GC0,
-reg__180: VCU118RocketSystem__GC0,
-logic__2472: DCache,
-muxpart__204: FPU__GB0,
-logic__1580: VCU118RocketSystem__GC0,
-reg__786: RocketTile__GCB0,
-logic__6980: VCU118RocketSystem__GC0,
-case__1098: VCU118RocketSystem__GC0,
-logic__9356: tracking_wrapper,
-reg__296: VCU118RocketSystem__GC0,
-reg__154: VCU118RocketSystem__GC0,
-reg__1374: tracking_wrapper,
-reg__888: VCU118RocketSystem__GC0,
-case__503: RocketTile__GCB0,
-logic__5116: FPU__GB1,
-datapath__343: FPU__GB2,
-case__1608: tracking_wrapper,
-reg__932: VCU118RocketSystem__GC0,
-reg__1276: tracking_wrapper,
-logic__5465: RocketTile__GCB0,
-case__692: FPU__GB2,
-keep__4: vcu118_rocket_top__GC0,
-logic__3339: FPU__GB1,
-logic__1343: VCU118RocketSystem__GC0,
-Queue2_TLBundleD_a29d64s2k1z3u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-dsp48e2__24: APBGpsBlock__GC0,
-case__995: VCU118RocketSystem__GC0,
-muxpart__259: FPU__GB1,
-logic__7437: VCU118RocketSystem__GC0,
-reg__617: FPU__GB2,
-logic__1758: VCU118RocketSystem__GC0,
-reg__532: FPU__GB1,
-logic__3555: FPU__GB1,
-logic__8138: VCU118RocketSystem__GC0,
-datapath__179: VCU118RocketSystem__GC0,
-muxpart__268: RocketTile__GCB0,
-case__509: DCache,
-logic__7066: VCU118RocketSystem__GC0,
-reg__412: RocketTile__GCB0,
-case__831: RocketTile__GCB0,
-muxpart__39: vcu118_rocket_top__GC0,
-logic__6936: VCU118RocketSystem__GC0,
-logic__1716: VCU118RocketSystem__GC0,
-logic__6631: RocketTile__GCB0,
-logic__3197: RocketTile__GCB0,
-logic__1181: VCU118RocketSystem__GC0,
-logic__5224: RocketTile__GCB0,
-case__465: VCU118RocketSystem__GC0,
-logic__9344: tracking_wrapper,
-reg__597: FPU__GB2,
-logic__4253: FPU__GB1,
-logic__8354: APBGpsBlock__GC0,
-logic__2865: DCache,
-logic__728: vcu118_rocket_top__GC0,
-case__611: RocketTile__GCB0,
-muxpart__17: vcu118_rocket_top__GC0,
-reg__927: VCU118RocketSystem__GC0,
-logic__3787: FPU__GB2,
-logic__6530: RocketTile__GCB0,
-logic__425: vcu118_rocket_top__GC0,
-logic__1493: VCU118RocketSystem__GC0,
-datapath__416: FPU__GB1,
-logic__6897: VCU118RocketSystem__GC0,
-logic__1640: VCU118RocketSystem__GC0,
-logic__6112: RocketTile__GCB0,
-logic__8422: APBGpsBlock__GC0,
-logic__5978: RocketTile__GCB0,
-logic__3932: FPU__GB2,
-logic__7717: VCU118RocketSystem__GC0,
-case__646: FPU__GB1,
-logic__5520: RocketTile__GCB0,
-reg__86: vcu118_rocket_top__GC0,
-reg__771: RocketTile__GCB0,
-logic__5540: RocketTile__GCB0,
-logic__329: vcu118_rocket_top__GC0,
-mult_30_25_55: tracking_wrapper,
-logic__8192: VCU118RocketSystem__GC0,
-logic__7029: VCU118RocketSystem__GC0,
-logic__1821: VCU118RocketSystem__GC0,
-logic__8265: APBGpsBlock__GC0,
-logic__5480: RocketTile__GCB0,
-case__78: vcu118_rocket_top__GC0,
-reg__1038: VCU118RocketSystem__GC0,
-case__1645: tracking_wrapper,
-case__1441: APBGpsBlock__GC0,
-logic__6126: RocketTile__GCB0,
-reg__704: RocketTile__GCB0,
-logic__3516: FPU__GB1,
-logic__6520: RocketTile__GCB0,
-reg__215: VCU118RocketSystem__GC0,
-keep__14: tracking_wrapper,
-reg__633: FPU__GB1,
-reg__758: RocketTile__GCB0,
-case__821: RocketTile__GCB0,
-logic__2725: DCache,
-reg__511: FPU__GB1,
-logic__1275: VCU118RocketSystem__GC0,
-dsp48e2__34: tracking_wrapper,
-logic__8866: tracking_wrapper,
-reg__1015: VCU118RocketSystem__GC0,
-reg__1232: tracking_wrapper,
-case__239: VCU118RocketSystem__GC0,
-datapath__42: VCU118RocketSystem__GC0,
-TLFIFOFixer_1: VCU118RocketSystem__GC0,
-logic__6111: RocketTile__GCB0,
-logic__1885: VCU118RocketSystem__GC0,
-datapath__243: VCU118RocketSystem__GC0,
-reg__988: VCU118RocketSystem__GC0,
-logic__6066: RocketTile__GCB0,
-logic__3088: RocketTile__GCB0,
-datapath__517: VCU118RocketSystem__GC0,
-datapath__215: VCU118RocketSystem__GC0,
-datapath__131: VCU118RocketSystem__GC0,
-logic__3328: FPU__GB1,
-dsp48e2__2: APBGpsBlock__GC0,
-logic__8266: APBGpsBlock__GC0,
-case__1693: VCU118RocketSystem__GC0,
-logic__8868: tracking_wrapper,
-case__846: RocketTile__GCB0,
-reg__596: FPU__GB2,
-case__989: VCU118RocketSystem__GC0,
-Repeater_TLBundleD_a32d64s1k1z4u: VCU118RocketSystem__GC0,
-datapath__383: FPU__GB1,
-muxpart__61: vcu118_rocket_top__GC0,
-case__9: vcu118_rocket_top__GC0,
-reg__138: VCU118RocketSystem__GC0,
-case__872: RocketTile__GCB0,
-muxpart__170: vcu118_rocket_top__GC0,
-case__777: FPU__GB1,
-reg__677: RocketTile__GCB0,
-logic__2429: DCache,
-logic__1987: VCU118RocketSystem__GC0,
-logic__2491: RocketTile__GCB0, DCache,
-case__1066: VCU118RocketSystem__GC0,
-logic__2485: RocketTile__GCB0, DCache,
-muxpart__13: vcu118_rocket_top__GC0,
-case__502: RocketTile__GCB0,
-case__591: RocketTile__GCB0,
-reg__96: vcu118_rocket_top__GC0,
-reg__1114: APBGpsBlock__GC0,
-logic__9464: vcu118_rocket_top__GC0,
-reg__70: vcu118_rocket_top__GC0,
-case__776: FPU__GB1,
-logic__1253: VCU118RocketSystem__GC0,
-logic__4845: FPU__GB2,
-logic__3416: FPU__GB1,
-muxpart__249: FPU__GB0,
-logic__2945: DCache,
-logic__2448: DCache,
-logic__8726: APBGpsBlock__GC0,
-logic__4407: FPU__GB1,
-logic__2265: DCache,
-logic__4625: FPU__GB2, FPU__GB1,
-logic__7243: VCU118RocketSystem__GC0,
-logic__7230: VCU118RocketSystem__GC0,
-muxpart__203: FPU__GB0,
-case__844: RocketTile__GCB0,
-muxpart__267: RocketTile__GCB0,
-case__1394: APBGpsBlock__GC0,
-reg__525: FPU__GB2,
-logic__4327: FPU__GB1,
-counter__12: VCU118RocketSystem__GC0,
-logic__3316: FPU__GB1,
-case__1578: tracking_wrapper,
-reg__703: RocketTile__GCB0,
-logic__4259: FPU__GB1,
-logic__9293: tracking_wrapper,
-logic__3780: FPU__GB2,
-datapath__231: VCU118RocketSystem__GC0,
-logic__246: vcu118_rocket_top__GC0,
-datapath__208: VCU118RocketSystem__GC0,
-logic__3116: RocketTile__GCB0,
-datapath__699: tracking_wrapper,
-case__1068: VCU118RocketSystem__GC0,
-reg__942: VCU118RocketSystem__GC0,
-acq_peak_srch: APBGpsBlock__GC0,
-case__1258: APBGpsBlock__GC0,
-case__654: FPU__GB2, FPU__GB1,
-logic__4209: FPU__GB1,
-datapath__465: RocketTile__GCB0,
-case__46: vcu118_rocket_top__GC0,
-datapath__462: RocketTile__GCB0,
-reg__1058: VCU118RocketSystem__GC0,
-datapath__22: vcu118_rocket_top__GC0,
-logic__4544: FPU__GB2, FPU__GB1,
-muxpart__266: RocketTile__GCB0,
-logic__5993: RocketTile__GCB0,
-logic__3917: FPU__GB2,
-ram__7: RocketTile__GCB0,
-case__996: VCU118RocketSystem__GC0,
-logic__2816: DCache,
-logic__2392: DCache,
-logic__7088: VCU118RocketSystem__GC0,
-reg__69: vcu118_rocket_top__GC0,
-logic__8598: APBGpsBlock__GC0,
-reg__1201: APBGpsBlock__GC0,
-logic__4537: FPU__GB2, FPU__GB1,
-logic__391: vcu118_rocket_top__GC0,
-logic__5509: RocketTile__GCB0,
-reg__447: FPU__GB0,
-case__999: VCU118RocketSystem__GC0,
-logic__6824: VCU118RocketSystem__GC0,
-logic__7278: VCU118RocketSystem__GC0,
-logic__7418: VCU118RocketSystem__GC0,
-case__418: VCU118RocketSystem__GC0,
-logic__6058: RocketTile__GCB0,
-logic__4835: FPU__GB2,
-reg__405: RocketTile__GCB0,
-case__327: VCU118RocketSystem__GC0,
-case__1589: tracking_wrapper,
-logic__2746: DCache,
-logic__979: VCU118RocketSystem__GC0,
-case__1372: APBGpsBlock__GC0,
-reg__1009: VCU118RocketSystem__GC0,
-logic__3335: FPU__GB1,
-logic__9025: tracking_wrapper,
-case__713: FPU__GB1,
-logic__3499: FPU__GB1,
-logic__2041: VCU118RocketSystem__GC0,
-logic__1391: VCU118RocketSystem__GC0,
-logic__7019: VCU118RocketSystem__GC0,
-case__1104: VCU118RocketSystem__GC0,
-reg__961: VCU118RocketSystem__GC0,
-logic__4833: FPU__GB2,
-datapath__598: APBGpsBlock__GC0,
-datapath__591: APBGpsBlock__GC0,
-RecFNToRecFN: FPU__GB1,
-case__1105: VCU118RocketSystem__GC0,
-logic__7385: VCU118RocketSystem__GC0,
-case__814: RocketTile__GCB0,
-case__1437: APBGpsBlock__GC0,
-logic__5888: RocketTile__GCB0,
-logic__1545: VCU118RocketSystem__GC0,
-logic__5310: RocketTile__GCB0,
-logic__8960: tracking_wrapper,
-muxpart__242: FPU__GB0,
-logic__4420: FPU__GB1,
-logic__1798: VCU118RocketSystem__GC0,
-logic__262: vcu118_rocket_top__GC0,
-reg__910: VCU118RocketSystem__GC0,
-logic__9265: tracking_wrapper,
-muxpart__196: FPU__GB0,
-logic__3218: RocketTile__GCB0,
-logic__7649: VCU118RocketSystem__GC0,
-logic__1817: VCU118RocketSystem__GC0,
-CSRFile: RocketTile__GCB0,
-logic__9264: tracking_wrapper,
-TLWidthWidget8_4: VCU118RocketSystem__GC0,
-reg__501: FPU__GB1,
-logic__4836: FPU__GB2,
-logic__2227: DCache,
-reg__401: RocketTile__GCB0,
-reg__575: FPU__GB2,
-reg__1005: VCU118RocketSystem__GC0,
-logic__9277: tracking_wrapper,
-logic__2875: DCache,
-datapath__128: VCU118RocketSystem__GC0,
-logic__7864: VCU118RocketSystem__GC0,
-case__983: VCU118RocketSystem__GC0,
-butterfly__parameterized0: APBGpsBlock__GC0,
-logic__7576: VCU118RocketSystem__GC0,
-case__232: VCU118RocketSystem__GC0,
-logic__3507: FPU__GB1,
-logic__7340: VCU118RocketSystem__GC0,
-logic__4478: FPU__GB1,
-logic__5578: RocketTile__GCB0,
-logic__3410: FPU__GB1,
-logic__6128: RocketTile__GCB0,
-logic__4756: FPU__GB2,
-logic__6862: VCU118RocketSystem__GC0,
-logic__6089: RocketTile__GCB0,
-case__1318: APBGpsBlock__GC0,
-logic__4695: FPU__GB2,
-logic__8242: VCU118RocketSystem__GC0,
-logic__5994: RocketTile__GCB0,
-logic__5036: FPU__GB1,
-logic__7729: VCU118RocketSystem__GC0,
-logic__3099: RocketTile__GCB0,
-logic__5417: RocketTile__GCB0,
-logic__4295: FPU__GB1,
-reg__393: RocketTile__GCB0,
-case__1623: tracking_wrapper,
-logic__2833: DCache,
-logic__245: vcu118_rocket_top__GC0,
-logic__5687: RocketTile__GCB0,
-logic__8689: APBGpsBlock__GC0,
-logic__5718: RocketTile__GCB0,
-datapath__91: VCU118RocketSystem__GC0,
-datapath__685: tracking_wrapper,
-logic__6553: RocketTile__GCB0,
-case__684: FPU__GB2,
-case__1139: VCU118RocketSystem__GC0,
-logic__257: vcu118_rocket_top__GC0,
-reg__1065: VCU118RocketSystem__GC0,
-reg__308: VCU118RocketSystem__GC0,
-logic__3933: FPU__GB2,
-case__286: VCU118RocketSystem__GC0,
-logic__3543: FPU__GB1,
-case__571: RocketTile__GCB0,
-logic__5906: RocketTile__GCB0,
-logic__5138: FPU__GB1,
-reg__1356: tracking_wrapper,
-logic__9266: tracking_wrapper,
-logic__3708: FPU__GB2,
-reg__919: VCU118RocketSystem__GC0,
-muxpart__97: vcu118_rocket_top__GC0,
-reg__263: VCU118RocketSystem__GC0,
-case__1564: tracking_wrapper,
-datapath__544: VCU118RocketSystem__GC0,
-logic__1820: VCU118RocketSystem__GC0,
-logic__5532: RocketTile__GCB0,
-logic__5614: RocketTile__GCB0,
-logic__827: VCU118RocketSystem__GC0,
-logic__8913: tracking_wrapper,
-logic__6570: RocketTile__GCB0,
-muxpart__102: vcu118_rocket_top__GC0,
-muxpart__310: APBGpsBlock__GC0,
-reg__503: FPU__GB1,
-logic__2007: VCU118RocketSystem__GC0,
-logic__3282: RocketTile__GCB0,
-datapath__469: RocketTile__GCB0,
-logic__5194: RocketTile__GCB0,
-logic__8215: VCU118RocketSystem__GC0,
-logic__2150: DCache,
-logic__8881: tracking_wrapper,
-logic__5021: FPU__GB1,
-case__810: RocketTile__GCB0,
-reg__1395: tracking_wrapper,
-reg__1406: VCU118RocketSystem__GC0,
-logic__9353: tracking_wrapper,
-case__663: FPU__GB1,
-reg__858: VCU118RocketSystem__GC0,
-case__384: VCU118RocketSystem__GC0,
-reg__966: VCU118RocketSystem__GC0,
-logic__1703: VCU118RocketSystem__GC0,
-logic__4602: FPU__GB2, FPU__GB1,
-logic__1804: VCU118RocketSystem__GC0,
-case__22: vcu118_rocket_top__GC0,
-datapath__217: VCU118RocketSystem__GC0,
-case__427: VCU118RocketSystem__GC0,
-logic__5626: RocketTile__GCB0,
-case__1666: tracking_wrapper,
-logic__8730: APBGpsBlock__GC0,
-reg__568: FPU__GB1,
-logic__3325: FPU__GB1,
-reg__1248: tracking_wrapper,
-case__799: FPU__GB1,
-logic__3965: FPU__GB2,
-logic__2228: DCache,
-case__1535: tracking_wrapper,
-logic__7336: VCU118RocketSystem__GC0,
-logic__7383: VCU118RocketSystem__GC0,
-case__934: RocketTile__GCB0,
-case__1517: tracking_wrapper,
-logic__494: vcu118_rocket_top__GC0,
-logic__7575: VCU118RocketSystem__GC0,
-reg__920: VCU118RocketSystem__GC0,
-case__893: RocketTile__GCB0,
-logic__375: vcu118_rocket_top__GC0,
-case__37: vcu118_rocket_top__GC0,
-case__1602: tracking_wrapper,
-datapath__419: FPU__GB1,
-logic__7918: VCU118RocketSystem__GC0,
-logic__3437: FPU__GB1,
-case__1552: tracking_wrapper,
-datapath__316: FPU__GB1,
-logic__1395: VCU118RocketSystem__GC0,
-logic__6024: RocketTile__GCB0,
-logic__5945: RocketTile__GCB0,
-case__632: RocketTile__GCB0,
-reg__1368: tracking_wrapper,
-logic__5398: RocketTile__GCB0,
-case__263: VCU118RocketSystem__GC0,
-datapath__320: FPU__GB1,
-logic__6687: RocketTile__GCB0,
-logic__1930: VCU118RocketSystem__GC0,
-muxpart__229: FPU__GB0,
-logic__2607: DCache,
-logic__7888: VCU118RocketSystem__GC0,
-case__1151: VCU118RocketSystem__GC0,
-logic__5118: FPU__GB1,
-reg__662: RocketTile__GCB0,
-case__1568: tracking_wrapper,
-logic__3766: FPU__GB2,
-logic__3604: FPU__GB2, FPU__GB1,
-datapath__318: FPU__GB1,
-TLInterconnectCoupler_cbus_to_bootrom: VCU118RocketSystem__GC0,
-logic__5463: RocketTile__GCB0,
-logic__1107: VCU118RocketSystem__GC0,
-logic__3490: FPU__GB1,
-datapath__113: VCU118RocketSystem__GC0,
-reg__320: DCache,
-logic__178: vcu118_rocket_top__GC0,
-logic__7978: VCU118RocketSystem__GC0,
-logic__4298: FPU__GB1,
-logic__3457: FPU__GB1,
-reg__284: VCU118RocketSystem__GC0,
-logic__8029: VCU118RocketSystem__GC0,
-case__1546: tracking_wrapper,
-datapath__417: FPU__GB1,
-datapath__516: VCU118RocketSystem__GC0,
-logic__1656: VCU118RocketSystem__GC0,
-logic__4973: FPU__GB1,
-logic__5447: RocketTile__GCB0,
-reg__862: VCU118RocketSystem__GC0,
-logic__1736: VCU118RocketSystem__GC0,
-logic__2839: DCache,
-reg__1308: tracking_wrapper,
-case__769: FPU__GB2,
-case__943: RocketTile__GCB0,
-logic__3663: FPU__GB2, FPU__GB1,
-datapath__387: FPU__GB2, FPU__GB1,
-logic__9362: tracking_wrapper,
-muxpart__98: vcu118_rocket_top__GC0,
-reg__778: RocketTile__GCB0,
-reg__817: RocketTile__GCB0,
-case__788: FPU__GB1,
-reg__1199: APBGpsBlock__GC0,
-reg__73: vcu118_rocket_top__GC0,
-logic__6755: VCU118RocketSystem__GC0,
-muxpart__265: RocketTile__GCB0,
-logic__2256: DCache,
-logic__8536: APBGpsBlock__GC0,
-case__477: VCU118RocketSystem__GC0,
-logic__3938: FPU__GB2,
-datapath__314: RocketTile__GCB0,
-logic__7722: VCU118RocketSystem__GC0,
-logic__426: vcu118_rocket_top__GC0,
-reg__500: FPU__GB1,
-reg__923: VCU118RocketSystem__GC0,
-datapath__137: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__176: VCU118RocketSystem__GC0,
-reg__941: VCU118RocketSystem__GC0,
-case__659: FPU__GB2, FPU__GB1,
-reg__692: RocketTile__GCB0,
-datapath__572: APBGpsBlock__GC0,
-logic__8291: APBGpsBlock__GC0,
-reg__665: RocketTile__GCB0,
-case__276: VCU118RocketSystem__GC0,
-case__1574: tracking_wrapper,
-logic__9010: tracking_wrapper,
-logic__3533: FPU__GB1,
-logic__7913: VCU118RocketSystem__GC0,
-ClockSinkDomain: VCU118RocketSystem__GC0,
-logic__9024: tracking_wrapper,
-logic__8419: APBGpsBlock__GC0,
-logic__6033: RocketTile__GCB0,
-reg__712: RocketTile__GCB0,
-logic__6813: VCU118RocketSystem__GC0,
-logic__1234: VCU118RocketSystem__GC0,
-logic__7814: VCU118RocketSystem__GC0,
-logic__3704: FPU__GB2,
-logic__5073: FPU__GB1,
-logic__5105: FPU__GB1,
-reg__1150: APBGpsBlock__GC0,
-datapath__202: VCU118RocketSystem__GC0,
-reg__428: RocketTile__GCB0,
-logic__4203: FPU__GB1,
-case__1590: tracking_wrapper,
-datapath__65: VCU118RocketSystem__GC0,
-datapath__193: VCU118RocketSystem__GC0,
-datapath__724: tracking_wrapper,
-logic__5602: RocketTile__GCB0,
-logic__1658: VCU118RocketSystem__GC0,
-logic__3774: FPU__GB2,
-logic__365: vcu118_rocket_top__GC0,
-case__1549: tracking_wrapper,
-case__1230: VCU118RocketSystem__GC0,
-logic__4299: FPU__GB1,
-logic__2022: VCU118RocketSystem__GC0,
-logic__934: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-TLToAPB: TLToAPB,
-logic__5381: RocketTile__GCB0,
-logic__9028: tracking_wrapper,
-logic__2192: DCache,
-case__523: DCache,
-datapath__253: VCU118RocketSystem__GC0,
-logic__3893: FPU__GB2,
-datapath__216: VCU118RocketSystem__GC0,
-logic__9181: tracking_wrapper,
-reg__455: FPU__GB0,
-logic__6630: RocketTile__GCB0,
-logic__7661: VCU118RocketSystem__GC0,
-case__500: RocketTile__GCB0,
-logic__4404: FPU__GB1,
-logic__4594: FPU__GB2, FPU__GB1,
-logic__7302: VCU118RocketSystem__GC0,
-reg__859: VCU118RocketSystem__GC0,
-reg__129: VCU118RocketSystem__GC0,
-datapath__14: vcu118_rocket_top__GC0,
-reg__953: VCU118RocketSystem__GC0,
-logic__4866: FPU__GB2,
-case__655: FPU__GB2, FPU__GB1,
-logic__3816: FPU__GB2,
-logic__5406: RocketTile__GCB0,
-datapath__566: APBGpsBlock__GC0,
-logic__9330: tracking_wrapper,
-logic__7893: VCU118RocketSystem__GC0,
-logic__7728: VCU118RocketSystem__GC0,
-logic__3035: RocketTile__GCB0,
-logic__3934: FPU__GB2,
-logic__1058: VCU118RocketSystem__GC0,
-logic__1047: VCU118RocketSystem__GC0,
-case__212: vcu118_rocket_top__GC0,
-logic__6860: VCU118RocketSystem__GC0,
-datapath__475: RocketTile__GCB0,
-logic__3087: RocketTile__GCB0,
-logic__5354: RocketTile__GCB0,
-reg__814: RocketTile__GCB0,
-PLICFanIn: VCU118RocketSystem__GC0,
-datapath__610: APBGpsBlock__GC0,
-logic__6849: VCU118RocketSystem__GC0,
-logic__3703: FPU__GB2,
-reg__711: RocketTile__GCB0,
-logic__4955: FPU__GB2,
-reg__318: DCache,
-logic__2476: RocketTile__GCB0, DCache,
-logic__6121: RocketTile__GCB0,
-logic__2255: DCache,
-reg__302: VCU118RocketSystem__GC0,
-datapath__420: RocketTile__GCB0,
-reg__108: VCU118RocketSystem__GC0,
-DivSqrtRecFNToRaw_small_1: FPU__GB2,
-case__780: FPU__GB1,
-reg__1372: tracking_wrapper,
-logic__8088: VCU118RocketSystem__GC0,
-datapath__361: FPU__GB2,
-logic__9193: tracking_wrapper,
-logic__8121: VCU118RocketSystem__GC0,
-case__483: VCU118RocketSystem__GC0,
-datapath__187: VCU118RocketSystem__GC0,
-logic__3623: FPU__GB2, FPU__GB1,
-logic__3618: FPU__GB2, FPU__GB1,
-logic__3427: FPU__GB1,
-logic__1578: VCU118RocketSystem__GC0,
-reg__739: RocketTile__GCB0,
-muxpart__200: FPU__GB0,
-logic__873: VCU118RocketSystem__GC0,
-case__561: DCache,
-logic__8359: APBGpsBlock__GC0,
-case__1219: VCU118RocketSystem__GC0,
-logic__5340: RocketTile__GCB0,
-logic__7582: VCU118RocketSystem__GC0,
-logic__7557: VCU118RocketSystem__GC0,
-reg__317: RocketTile__GCB0,
-datapath__451: RocketTile__GCB0,
-logic__4484: FPU__GB1,
-logic__7631: VCU118RocketSystem__GC0,
-reg__1089: APBGpsBlock__GC0,
-datapath__409: FPU__GB2,
-logic__3487: FPU__GB1,
-cordic_atan_basic__parameterized0: tracking_wrapper,
-logic__7790: VCU118RocketSystem__GC0,
-logic__6722: RocketTile__GCB0,
-datapath__19: vcu118_rocket_top__GC0,
-case__1194: VCU118RocketSystem__GC0,
-logic__4300: FPU__GB1,
-logic__5759: RocketTile__GCB0,
-logic__8530: APBGpsBlock__GC0,
-logic__6000: RocketTile__GCB0,
-case__998: VCU118RocketSystem__GC0,
-logic__515: vcu118_rocket_top__GC0,
-case__55: vcu118_rocket_top__GC0,
-reg__1284: tracking_wrapper,
-logic__3031: RocketTile__GCB0,
-logic__5123: FPU__GB1,
-logic__6303: RocketTile__GCB0,
-logic__7741: VCU118RocketSystem__GC0,
-datapath__29: vcu118_rocket_top__GC0,
-logic__7507: VCU118RocketSystem__GC0,
-reg__481: FPU__GB1,
-datapath__612: APBGpsBlock__GC0,
-case__923: RocketTile__GCB0,
-reg__1001: VCU118RocketSystem__GC0,
-datapath__727: TLToAPB,
-logic__3804: FPU__GB2,
-logic__977: VCU118RocketSystem__GC0,
-muxpart__213: FPU__GB0,
-logic__1702: VCU118RocketSystem__GC0,
-reg__1234: tracking_wrapper,
-logic__2030: VCU118RocketSystem__GC0,
-logic__5233: RocketTile__GCB0,
-logic__5934: RocketTile__GCB0,
-case__772: FPU__GB1,
-logic__7973: VCU118RocketSystem__GC0,
-reg__259: VCU118RocketSystem__GC0,
-reg__767: RocketTile__GCB0,
-logic__6676: RocketTile__GCB0,
-logic__3094: RocketTile__GCB0,
-datapath__135: VCU118RocketSystem__GC0,
-logic__9333: tracking_wrapper,
-logic__6806: VCU118RocketSystem__GC0,
-case__1396: APBGpsBlock__GC0,
-logic__9278: tracking_wrapper,
-case__1644: tracking_wrapper,
-datapath__189: VCU118RocketSystem__GC0,
-case__75: vcu118_rocket_top__GC0,
-case__1245: VCU118RocketSystem__GC0,
-reg__231: VCU118RocketSystem__GC0,
-case__274: VCU118RocketSystem__GC0,
-case__1691: TLToAPB,
-logic__6822: VCU118RocketSystem__GC0,
-logic__5128: FPU__GB0,
-reg__1140: APBGpsBlock__GC0,
-case__198: vcu118_rocket_top__GC0,
-case__1323: APBGpsBlock__GC0,
-logic__7061: VCU118RocketSystem__GC0,
-datapath__658: APBGpsBlock__GC0,
-RoundAnyRawFNToRecFN: FPU__GB2, FPU__GB1,
-logic__7215: VCU118RocketSystem__GC0,
-logic__1394: VCU118RocketSystem__GC0,
-reg__314: RocketTile__GCB0,
-logic__9057: tracking_wrapper,
-logic__5567: RocketTile__GCB0,
-case__361: VCU118RocketSystem__GC0,
-logic__3480: FPU__GB1,
-logic__5022: FPU__GB2,
-case__581: RocketTile__GCB0,
-keep__1: vcu118_rocket_top__GC0,
-logic__7380: VCU118RocketSystem__GC0,
-case__348: VCU118RocketSystem__GC0,
-TLBuffer_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-case__693: FPU__GB2,
-logic__8295: APBGpsBlock__GC0,
-cos2x: tracking_wrapper,
-case__4: vcu118_rocket_top__GC0,
-logic__4357: FPU__GB1,
-reg__1393: tracking_wrapper,
-datapath__450: RocketTile__GCB0,
-reg__524: FPU__GB2,
-datapath__681: tracking_wrapper,
-reg__639: FPU__GB1,
-logic__4854: FPU__GB2,
-case__1215: VCU118RocketSystem__GC0,
-reg__1208: tracking_wrapper,
-logic__2558: DCache,
-logic__7992: VCU118RocketSystem__GC0,
-datapath__196: VCU118RocketSystem__GC0,
-logic__3011: RocketTile__GCB0,
-reg__448: FPU__GB0,
-logic__3989: FPU__GB2,
-logic__6367: RocketTile__GCB0,
-datapath__30: vcu118_rocket_top__GC0,
-datapath__104: VCU118RocketSystem__GC0,
-case__34: vcu118_rocket_top__GC0,
-datapath__275: DCache,
-logic__6361: RocketTile__GCB0,
-reg__1405: TLToAPB,
-reg__911: VCU118RocketSystem__GC0,
-logic__5528: RocketTile__GCB0,
-logic__1262: VCU118RocketSystem__GC0,
-counter__30: tracking_wrapper,
-logic__5231: RocketTile__GCB0,
-logic__2616: DCache,
-logic__878: VCU118RocketSystem__GC0,
-muxpart__184: FPU__GB0,
-case__489: RocketTile__GCB0,
-reg__58: vcu118_rocket_top__GC0,
-datapath__510: VCU118RocketSystem__GC0,
-dsp48e2__19: APBGpsBlock__GC0,
-cdc_fifo_gray: tracking_wrapper,
-reg__484: FPU__GB1,
-logic__8937: tracking_wrapper,
-reg__462: FPU__GB0,
-case__1609: tracking_wrapper,
-reg__781: RocketTile__GCB0,
-acq_wrapper: APBGpsBlock__GC0,
-case__1288: APBGpsBlock__GC0,
-reg__67: vcu118_rocket_top__GC0,
-reg__971: VCU118RocketSystem__GC0,
-case__472: VCU118RocketSystem__GC0,
-reg__1040: VCU118RocketSystem__GC0,
-logic__7838: VCU118RocketSystem__GC0,
-logic__4957: FPU__GB2,
-logic__9393: APBGpsBlock__GC0,
-logic__2304: DCache,
-logic__1160: VCU118RocketSystem__GC0,
-reg__785: RocketTile__GCB0,
-logic__3320: FPU__GB1,
-logic__8968: tracking_wrapper,
-reg__1164: APBGpsBlock__GC0,
-logic__8999: tracking_wrapper,
-reg__1269: tracking_wrapper,
-reg__339: DCache,
-reg__372: DCache,
-logic__9426: APBGpsBlock__GC0,
-logic__240: vcu118_rocket_top__GC0,
-case__1030: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_pbus_to_fpga_uart: VCU118RocketSystem__GC0,
-twiddle_ram: APBGpsBlock__GC0,
-logic__6103: RocketTile__GCB0,
-case__1106: VCU118RocketSystem__GC0,
-logic__2131: RocketTile__GCB0,
-logic__5327: RocketTile__GCB0,
-reg__1013: VCU118RocketSystem__GC0,
-logic__1686: VCU118RocketSystem__GC0,
-AsyncValidSync: VCU118RocketSystem__GC0,
-datapath__169: VCU118RocketSystem__GC0,
-reg__950: VCU118RocketSystem__GC0,
-case__904: RocketTile__GCB0,
-logic__6823: VCU118RocketSystem__GC0,
-logic__5943: RocketTile__GCB0,
-case__565: DCache,
-logic__1039: VCU118RocketSystem__GC0,
-logic__3565: FPU__GB2, FPU__GB1,
-datapath__254: VCU118RocketSystem__GC0,
-logic__1648: VCU118RocketSystem__GC0,
-logic__1457: VCU118RocketSystem__GC0,
-logic__1240: VCU118RocketSystem__GC0,
-logic__427: vcu118_rocket_top__GC0,
-datapath__719: tracking_wrapper,
-logic__3911: FPU__GB2,
-reg__1088: APBGpsBlock__GC0,
-logic__8235: VCU118RocketSystem__GC0,
-datapath__195: VCU118RocketSystem__GC0,
-case__1015: VCU118RocketSystem__GC0,
-case__1493: APBGpsBlock__GC0,
-case__339: VCU118RocketSystem__GC0,
-logic__5876: RocketTile__GCB0,
-logic__5831: RocketTile__GCB0,
-case__804: FPU__GB1,
-reg__27: vcu118_rocket_top__GC0,
-case__480: VCU118RocketSystem__GC0,
-logic__1523: VCU118RocketSystem__GC0,
-logic__6781: VCU118RocketSystem__GC0,
-reg__1028: VCU118RocketSystem__GC0,
-logic__2384: DCache,
-logic__9291: tracking_wrapper,
-reg__1220: tracking_wrapper,
-reg__14: vcu118_rocket_top__GC0,
-datapath__68: VCU118RocketSystem__GC0,
-logic__8619: APBGpsBlock__GC0,
-reg__374: RocketTile__GCB0,
-logic__1666: VCU118RocketSystem__GC0,
-logic__4009: FPU__GB2,
-logic__2085: RocketTile__GCB0,
-reg__682: RocketTile__GCB0,
-logic__7035: VCU118RocketSystem__GC0,
-datapath__579: APBGpsBlock__GC0,
-case__673: FPU__GB2,
-case__1173: VCU118RocketSystem__GC0,
-logic__1797: VCU118RocketSystem__GC0,
-reg__371: DCache,
-case__1111: VCU118RocketSystem__GC0,
-case__439: VCU118RocketSystem__GC0,
-case__756: FPU__GB2,
-reg__713: RocketTile__GCB0,
-logic__6071: RocketTile__GCB0,
-datapath__541: VCU118RocketSystem__GC0,
-case__453: VCU118RocketSystem__GC0,
-case__1615: tracking_wrapper,
-logic__724: vcu118_rocket_top__GC0,
-logic__4692: FPU__GB2,
-logic__3309: FPU__GB1,
-case__161: vcu118_rocket_top__GC0,
-reg__699: RocketTile__GCB0,
-reg__207: VCU118RocketSystem__GC0,
-logic__876: VCU118RocketSystem__GC0,
-case__1475: APBGpsBlock__GC0,
-reg__1070: APBGpsBlock__GC0,
-logic__6903: VCU118RocketSystem__GC0,
-muxpart__171: VCU118RocketSystem__GC0,
-datapath__265: RocketTile__GCB0,
-case__394: VCU118RocketSystem__GC0,
-logic__1951: VCU118RocketSystem__GC0,
-logic__5830: RocketTile__GCB0,
-case__275: VCU118RocketSystem__GC0,
-reg__1282: tracking_wrapper,
-logic__3082: RocketTile__GCB0,
-case__1682: TLToAPB,
-reg__44: vcu118_rocket_top__GC0,
-reg__294: VCU118RocketSystem__GC0,
-logic__7037: VCU118RocketSystem__GC0,
-logic__6684: RocketTile__GCB0,
-logic__786: VCU118RocketSystem__GC0,
-logic__4831: FPU__GB2,
-logic__8991: tracking_wrapper,
-logic__2375: DCache,
-logic__3033: RocketTile__GCB0,
-case__613: RocketTile__GCB0,
-case__1201: VCU118RocketSystem__GC0,
-reg__809: RocketTile__GCB0,
-IntSyncSyncCrossingSink_n1x2: TilePRCIDomain__GC0,
-datapath__177: VCU118RocketSystem__GC0,
-case__139: vcu118_rocket_top__GC0,
-case__234: VCU118RocketSystem__GC0,
-case__1260: APBGpsBlock__GC0,
-logic__2769: DCache,
-case__56: vcu118_rocket_top__GC0,
-logic__6037: RocketTile__GCB0,
-logic__5597: RocketTile__GCB0,
-case__417: VCU118RocketSystem__GC0,
-logic__907: VCU118RocketSystem__GC0,
-datapath__331: FPU__GB2, FPU__GB1,
-logic__6571: RocketTile__GCB0,
-logic__1086: VCU118RocketSystem__GC0,
-logic__3610: FPU__GB2, FPU__GB1,
-logic__5027: FPU__GB1,
-logic__3327: FPU__GB1,
-reg__1369: tracking_wrapper,
-case__1097: VCU118RocketSystem__GC0,
-PeripheryBus_cbus: VCU118RocketSystem__GC0,
-logic__8177: VCU118RocketSystem__GC0,
-datapath__227: VCU118RocketSystem__GC0,
-logic__3032: RocketTile__GCB0,
-logic__8988: tracking_wrapper,
-logic__1089: VCU118RocketSystem__GC0,
-reg__557: FPU__GB1,
-logic__4173: FPU__GB1,
-logic__8924: tracking_wrapper,
-reg__760: RocketTile__GCB0,
-logic__9178: tracking_wrapper,
-logic__3426: FPU__GB1,
-case__847: RocketTile__GCB0,
-logic__1531: VCU118RocketSystem__GC0,
-case__1011: VCU118RocketSystem__GC0,
-logic__8294: APBGpsBlock__GC0,
-case__423: VCU118RocketSystem__GC0,
-case__636: RocketTile__GCB0,
-case__755: FPU__GB2,
-case__496: RocketTile__GCB0,
-case__328: VCU118RocketSystem__GC0,
-logic__5420: RocketTile__GCB0,
-reg__1275: tracking_wrapper,
-ram__3: VCU118RocketSystem__GC0,
-muxpart__179: DCache,
-datapath__348: FPU__GB2,
-reg__34: vcu118_rocket_top__GC0,
-logic__8869: tracking_wrapper,
-TLDebugModuleInner: VCU118RocketSystem__GC0,
-rom__1: APBGpsBlock__GC0,
-case__53: vcu118_rocket_top__GC0,
-logic__4029: FPU__GB2,
-logic__3000: RocketTile__GCB0,
-logic__480: vcu118_rocket_top__GC0,
-reg__577: FPU__GB2,
-FixedClockBroadcast_1: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__238: vcu118_rocket_top__GC0,
-TLDebugModuleOuter: VCU118RocketSystem__GC0,
-logic__3311: FPU__GB1,
-logic__5141: FPU__GB1,
-reg__985: VCU118RocketSystem__GC0,
-datapath__159: VCU118RocketSystem__GC0,
-logic__4687: FPU__GB2,
-logic__4849: FPU__GB2,
-logic__115: vcu118_rocket_top__GC0,
-datapath__488: RocketTile__GCB0,
-logic__3204: RocketTile__GCB0,
-logic__5244: RocketTile__GCB0,
-logic__8798: tracking_wrapper,
-datapath__5: vcu118_rocket_top__GC0,
-logic__7400: VCU118RocketSystem__GC0,
-logic__4416: FPU__GB1,
-case__1478: APBGpsBlock__GC0,
-reg__875: VCU118RocketSystem__GC0,
-case__1083: VCU118RocketSystem__GC0,
-logic__6156: RocketTile__GCB0,
-datapath__697: tracking_wrapper,
-reg__479: FPU__GB1,
-logic__3106: RocketTile__GCB0,
-case__850: RocketTile__GCB0,
-case__546: DCache,
-reg__1210: tracking_wrapper,
-datapath__389: FPU__GB2, FPU__GB1,
-logic__7372: VCU118RocketSystem__GC0,
-logic__961: VCU118RocketSystem__GC0,
-logic__2477: RocketTile__GCB0, DCache,
-case__542: DCache,
-muxpart__18: vcu118_rocket_top__GC0,
-logic__808: VCU118RocketSystem__GC0,
-logic__2096: RocketTile__GCB0,
-case__1092: VCU118RocketSystem__GC0,
-reg__834: RocketTile__GCB0,
-case__1150: VCU118RocketSystem__GC0,
-logic__1836: VCU118RocketSystem__GC0,
-logic__8183: VCU118RocketSystem__GC0,
-case__1171: VCU118RocketSystem__GC0,
-case__1077: VCU118RocketSystem__GC0,
-logic__3323: FPU__GB1,
-logic__8599: APBGpsBlock__GC0,
-case__210: vcu118_rocket_top__GC0,
-logic__7512: VCU118RocketSystem__GC0,
-datapath__212: VCU118RocketSystem__GC0,
-logic__7948: VCU118RocketSystem__GC0,
-logic__6945: VCU118RocketSystem__GC0,
-case__44: vcu118_rocket_top__GC0,
-logic__5986: RocketTile__GCB0,
-logic__5484: RocketTile__GCB0,
-case__1524: tracking_wrapper,
-logic__4315: FPU__GB1,
-logic__121: vcu118_rocket_top__GC0,
-reg__1378: tracking_wrapper,
-case__206: vcu118_rocket_top__GC0,
-logic__8725: APBGpsBlock__GC0,
-acq_ca_gen: APBGpsBlock__GC0,
-logic__5565: RocketTile__GCB0,
-logic__1584: VCU118RocketSystem__GC0,
-logic__3544: FPU__GB1,
-logic__2165: DCache,
-logic__2356: DCache,
-case__1358: APBGpsBlock__GC0,
-case__1123: VCU118RocketSystem__GC0,
-logic__2847: DCache,
-logic__7668: VCU118RocketSystem__GC0,
-logic__6748: VCU118RocketSystem__GC0,
-case__900: RocketTile__GCB0,
-logic__1687: VCU118RocketSystem__GC0,
-reg__885: VCU118RocketSystem__GC0,
-reg__857: VCU118RocketSystem__GC0,
-logic__5702: RocketTile__GCB0,
-case__977: RocketTile__GCB0,
-logic__3302: FPU__GB1,
-logic__7438: VCU118RocketSystem__GC0,
-logic__1662: VCU118RocketSystem__GC0,
-logic__6064: RocketTile__GCB0,
-logic__2296: DCache,
-logic__5698: RocketTile__GCB0,
-datapath__258: VCU118RocketSystem__GC0,
-reg__562: FPU__GB1,
-logic__5435: RocketTile__GCB0,
-datapath__686: tracking_wrapper,
-logic__2722: DCache,
-dsp48e2__13: APBGpsBlock__GC0,
-logic__823: VCU118RocketSystem__GC0,
-datapath__272: DCache,
-fft_radix_2: APBGpsBlock__GC0,
-reg__10: vcu118_rocket_top__GC0,
-logic__7667: VCU118RocketSystem__GC0,
-logic__4656: FPU__GB2, FPU__GB1,
-logic__7141: VCU118RocketSystem__GC0,
-case__1603: tracking_wrapper,
-reg__815: RocketTile__GCB0,
-case__1204: VCU118RocketSystem__GC0,
-logic__7990: VCU118RocketSystem__GC0,
-logic__974: VCU118RocketSystem__GC0,
-datapath__204: VCU118RocketSystem__GC0,
-datapath__622: APBGpsBlock__GC0,
-logic__1591: VCU118RocketSystem__GC0,
-reg__47: vcu118_rocket_top__GC0,
-logic__6094: RocketTile__GCB0,
-logic__5619: RocketTile__GCB0,
-logic__8841: tracking_wrapper,
-case__220: vcu118_rocket_top__GC0,
-case__140: vcu118_rocket_top__GC0,
-logic__6664: RocketTile__GCB0,
-logic__9462: TLToAPB,
-reg__328: DCache,
-logic__7279: VCU118RocketSystem__GC0,
-logic__7606: VCU118RocketSystem__GC0,
-logic__3943: FPU__GB2,
-muxpart__76: vcu118_rocket_top__GC0,
-case__1617: tracking_wrapper,
-logic__7350: VCU118RocketSystem__GC0,
-logic__6065: RocketTile__GCB0,
-logic__8851: tracking_wrapper,
-logic__2234: DCache,
-logic__4417: FPU__GB1,
-logic__1694: VCU118RocketSystem__GC0,
-datapath__96: VCU118RocketSystem__GC0,
-datapath__483: RocketTile__GCB0,
-logic__6898: VCU118RocketSystem__GC0,
-logic__4956: FPU__GB2,
-datapath__116: VCU118RocketSystem__GC0,
-logic__2364: DCache,
-logic__4793: FPU__GB2,
-datapath__444: RocketTile__GCB0,
-logic__6832: VCU118RocketSystem__GC0,
-muxpart__261: RocketTile__GCB0,
-logic__3147: RocketTile__GCB0,
-logic__7120: VCU118RocketSystem__GC0,
-reg__174: VCU118RocketSystem__GC0,
-logic__6612: RocketTile__GCB0,
-extladd__1: tracking_wrapper,
-logic__6306: RocketTile__GCB0,
-case__324: VCU118RocketSystem__GC0,
-logic__1618: VCU118RocketSystem__GC0,
-reg__472: FPU__GB0,
-datapath__470: RocketTile__GCB0,
-logic__8550: APBGpsBlock__GC0,
-keep__8: APBGpsBlock__GC0, tracking_wrapper,
-logic__5714: RocketTile__GCB0,
-case__976: RocketTile__GCB0,
-reg__103: vcu118_rocket_top__GC0,
-logic__3083: RocketTile__GCB0,
-logic__3540: FPU__GB1,
-case__1654: tracking_wrapper,
-logic__6875: VCU118RocketSystem__GC0,
-reg__115: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a12d64s2k1z3u: VCU118RocketSystem__GC0,
-case__982: RocketTile__GCB0,
-logic__96: vcu118_rocket_top__GC0,
-datapath__63: VCU118RocketSystem__GC0,
-SynchronizerShiftReg_w1_d3: TilePRCIDomain__GC0,
-datapath__514: VCU118RocketSystem__GC0,
-logic__4382: FPU__GB1,
-case__1061: VCU118RocketSystem__GC0,
-reg__256: VCU118RocketSystem__GC0,
-datapath__162: VCU118RocketSystem__GC0,
-logic__2372: DCache,
-muxpart__260: RocketTile__GCB0,
-logic__2105: RocketTile__GCB0,
-logic__1061: VCU118RocketSystem__GC0,
-logic__2164: DCache,
-datapath__648: APBGpsBlock__GC0,
-logic__4260: FPU__GB1,
-logic__8814: tracking_wrapper,
-logic__518: vcu118_rocket_top__GC0,
-case__1430: APBGpsBlock__GC0,
-logic__7479: VCU118RocketSystem__GC0,
-reg__1289: tracking_wrapper,
-logic__2475: RocketTile__GCB0, DCache,
-reg__1320: tracking_wrapper,
-logic__2154: DCache,
-case__600: RocketTile__GCB0,
-datapath__342: FPU__GB2,
-logic__9468: vcu118_rocket_top__GC0,
-case__747: FPU__GB2,
-logic__1201: VCU118RocketSystem__GC0,
-logic__1124: VCU118RocketSystem__GC0,
-logic__7876: VCU118RocketSystem__GC0,
-logic__5371: RocketTile__GCB0,
-reg__98: vcu118_rocket_top__GC0,
-logic__5163: FPU__GB1,
-logic__3101: RocketTile__GCB0,
-logic__1587: VCU118RocketSystem__GC0,
-logic__5667: RocketTile__GCB0,
-reg__23: vcu118_rocket_top__GC0,
-reg__855: VCU118RocketSystem__GC0,
-logic__7899: VCU118RocketSystem__GC0,
-logic__4126: FPU__GB2,
-datapath__198: VCU118RocketSystem__GC0,
-muxpart__77: vcu118_rocket_top__GC0,
-logic__9352: tracking_wrapper,
-case__715: FPU__GB1,
-logic__4074: FPU__GB2,
-logic__1690: VCU118RocketSystem__GC0,
-logic__2074: RocketTile__GCB0,
-logic__5620: RocketTile__GCB0,
-case__1377: APBGpsBlock__GC0,
-datapath__508: VCU118RocketSystem__GC0,
-rom__3: APBGpsBlock__GC0,
-case__583: RocketTile__GCB0,
-logic__5419: RocketTile__GCB0,
-case__1191: VCU118RocketSystem__GC0,
-datapath__362: FPU__GB2,
-logic__1092: VCU118RocketSystem__GC0,
-case__1555: tracking_wrapper,
-reg__1391: tracking_wrapper,
-TLBuffer_a32d64s2k1z3u_1: TilePRCIDomain__GC0,
-logic__8883: tracking_wrapper,
-logic__3995: FPU__GB2,
-datapath__570: APBGpsBlock__GC0,
-logic__9343: tracking_wrapper,
-RoundAnyRawFNToRecFN_4: FPU__GB2, FPU__GB1,
-logic__6718: RocketTile__GCB0,
-logic__7967: VCU118RocketSystem__GC0,
-logic__5952: RocketTile__GCB0,
-logic__109: vcu118_rocket_top__GC0,
-logic__6956: VCU118RocketSystem__GC0,
-dsp48e2__18: APBGpsBlock__GC0,
-logic__291: vcu118_rocket_top__GC0,
-DivSqrtRecFNToRaw_small: FPU__GB2,
-logic__6649: RocketTile__GCB0,
-logic__3319: FPU__GB1,
-logic__7044: VCU118RocketSystem__GC0,
-reg__1036: VCU118RocketSystem__GC0,
-datapath__175: VCU118RocketSystem__GC0,
-reg__362: DCache,
-case__386: VCU118RocketSystem__GC0,
-dsp48e2__11: APBGpsBlock__GC0,
-reg__336: DCache,
-case__916: RocketTile__GCB0,
-logic__3481: FPU__GB1,
-logic__7303: VCU118RocketSystem__GC0,
-logic__1095: VCU118RocketSystem__GC0,
-logic__8279: APBGpsBlock__GC0,
-logic__7234: VCU118RocketSystem__GC0,
-logic__1354: VCU118RocketSystem__GC0,
-logic__3818: FPU__GB2,
-logic__1341: VCU118RocketSystem__GC0,
-reg__388: RocketTile__GCB0,
-logic__3153: RocketTile__GCB0,
-case__61: vcu118_rocket_top__GC0,
-datapath__402: FPU__GB2,
-logic__5206: RocketTile__GCB0,
-logic__1653: VCU118RocketSystem__GC0,
-reg__386: RocketTile__GCB0,
-logic__3183: RocketTile__GCB0,
-logic__2349: DCache,
-logic__3918: FPU__GB2,
-datapath__120: VCU118RocketSystem__GC0,
-logic__911: VCU118RocketSystem__GC0,
-logic__8105: VCU118RocketSystem__GC0,
-logic__3198: RocketTile__GCB0,
-logic__2735: DCache,
-logic__7827: VCU118RocketSystem__GC0,
-logic__1491: VCU118RocketSystem__GC0,
-reg__1203: APBGpsBlock__GC0,
-case__1091: VCU118RocketSystem__GC0,
-logic__1812: VCU118RocketSystem__GC0,
-logic__2229: DCache,
-logic__71: vcu118_rocket_top__GC0,
-logic__6815: VCU118RocketSystem__GC0,
-reg__313: VCU118RocketSystem__GC0,
-logic__5954: RocketTile__GCB0,
-case__1047: VCU118RocketSystem__GC0,
-datapath__634: APBGpsBlock__GC0,
-logic__8085: VCU118RocketSystem__GC0,
-logic__9247: tracking_wrapper,
-reg__937: VCU118RocketSystem__GC0,
-logic__870: VCU118RocketSystem__GC0,
-case__1521: tracking_wrapper,
-keep__9: APBGpsBlock__GC0, tracking_wrapper,
-reg__22: vcu118_rocket_top__GC0,
-case__702: FPU__GB1,
-logic__3572: FPU__GB2, FPU__GB1,
-logic__2927: DCache,
-case__430: VCU118RocketSystem__GC0,
-logic__5915: RocketTile__GCB0,
-case__1167: VCU118RocketSystem__GC0,
-logic__7723: VCU118RocketSystem__GC0,
-logic__5970: RocketTile__GCB0,
-logic__7711: VCU118RocketSystem__GC0,
-logic__1478: VCU118RocketSystem__GC0,
-logic__6048: RocketTile__GCB0,
-logic__8835: tracking_wrapper,
-logic__5186: RocketTile__GCB0,
-Queue1_RegMapperInput_i23_m8: VCU118RocketSystem__GC0,
-logic__7642: VCU118RocketSystem__GC0,
-logic__4848: FPU__GB2,
-logic__6070: RocketTile__GCB0,
-reg__394: RocketTile__GCB0,
-datapath__165: VCU118RocketSystem__GC0,
-case__836: RocketTile__GCB0,
-case__277: VCU118RocketSystem__GC0,
-logic__273: vcu118_rocket_top__GC0,
-logic__120: vcu118_rocket_top__GC0,
-logic__7115: VCU118RocketSystem__GC0,
-NCO_code: tracking_wrapper,
-logic__3467: FPU__GB1,
-TLDebugModuleOuterAsync: VCU118RocketSystem__GC0,
-logic__4762: FPU__GB2,
-case__625: RocketTile__GCB0,
-logic__6777: VCU118RocketSystem__GC0,
-logic__4595: FPU__GB2, FPU__GB1,
-logic__2273: DCache,
-case__305: VCU118RocketSystem__GC0,
-reg__606: FPU__GB1,
-reg__1044: VCU118RocketSystem__GC0,
-logic__3322: FPU__GB1,
-case__751: FPU__GB2,
-muxpart__181: RocketTile__GCB0,
-cordic_atan_basic: tracking_wrapper,
-logic__376: vcu118_rocket_top__GC0,
-reg__437: RocketTile__GCB0,
-logic__4449: FPU__GB1,
-logic__1680: VCU118RocketSystem__GC0,
-logic__1505: VCU118RocketSystem__GC0,
-reg__552: FPU__GB1,
-datapath__41: VCU118RocketSystem__GC0,
-spill_register: tracking_wrapper,
-logic__720: vcu118_rocket_top__GC0,
-case__508: DCache,
-logic__7858: VCU118RocketSystem__GC0,
-case__638: RocketTile__GCB0,
-logic__3333: FPU__GB1,
-logic__3598: FPU__GB2, FPU__GB1,
-logic__244: vcu118_rocket_top__GC0,
-logic__7404: VCU118RocketSystem__GC0,
-logic__3306: FPU__GB1,
-reg__1162: APBGpsBlock__GC0,
-case__644: FPU__GB1,
-case__1557: tracking_wrapper,
-logic__1959: VCU118RocketSystem__GC0,
-logic__2416: DCache,
-logic__2432: DCache,
-datapath__368: FPU__GB1,
-datapath__330: FPU__GB2, FPU__GB1,
-logic__5733: RocketTile__GCB0,
-Arbiter3_LLWB: RocketTile__GCB0,
-case__1082: VCU118RocketSystem__GC0,
-logic__8688: APBGpsBlock__GC0,
-case__311: VCU118RocketSystem__GC0,
-datapath__103: VCU118RocketSystem__GC0,
-logic__7662: VCU118RocketSystem__GC0,
-logic__1960: VCU118RocketSystem__GC0,
-case__1576: tracking_wrapper,
-case__1016: VCU118RocketSystem__GC0,
-reg__870: VCU118RocketSystem__GC0,
-reg__131: VCU118RocketSystem__GC0,
-logic__9039: tracking_wrapper,
-logic__7248: VCU118RocketSystem__GC0,
-logic__7192: VCU118RocketSystem__GC0,
-logic__8268: APBGpsBlock__GC0,
-reg__1314: tracking_wrapper,
-logic__2156: DCache,
-reg__1322: tracking_wrapper,
-datapath__329: FPU__GB2, FPU__GB1,
-logic__4178: FPU__GB1,
-reg__90: vcu118_rocket_top__GC0,
-logic__7660: VCU118RocketSystem__GC0,
-datapath__432: RocketTile__GCB0,
-logic__7172: VCU118RocketSystem__GC0,
-ram__5: VCU118RocketSystem__GC0,
-logic__8278: APBGpsBlock__GC0,
-reg__281: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a29d64s2k1z3u_2: VCU118RocketSystem__GC0,
-logic__5510: RocketTile__GCB0,
-logic__1586: VCU118RocketSystem__GC0,
-logic__3219: RocketTile__GCB0,
-case__1263: APBGpsBlock__GC0,
-datapath__635: APBGpsBlock__GC0,
-reg__874: VCU118RocketSystem__GC0,
-datapath__255: VCU118RocketSystem__GC0,
-logic__8120: VCU118RocketSystem__GC0,
-datapath__418: FPU__GB1,
-case__58: vcu118_rocket_top__GC0,
-reg__181: VCU118RocketSystem__GC0,
-logic__726: vcu118_rocket_top__GC0,
-case__1018: VCU118RocketSystem__GC0,
-logic__254: vcu118_rocket_top__GC0,
-logic__6318: RocketTile__GCB0,
-logic__5580: RocketTile__GCB0,
-case__125: vcu118_rocket_top__GC0,
-case__1161: VCU118RocketSystem__GC0,
-logic__2951: DCache,
-mult_46_15_61: APBGpsBlock__GC0,
-logic__7153: VCU118RocketSystem__GC0,
-reg__691: RocketTile__GCB0,
-logic__2736: DCache,
-logic__7826: VCU118RocketSystem__GC0,
-case__912: RocketTile__GCB0,
-reg__350: DCache,
-logic__5527: RocketTile__GCB0,
-case__1179: VCU118RocketSystem__GC0,
-logic__1604: VCU118RocketSystem__GC0,
-logic__7796: VCU118RocketSystem__GC0,
-case__637: RocketTile__GCB0,
-case__806: FPU__GB1,
-logic__1661: VCU118RocketSystem__GC0,
-case__1328: APBGpsBlock__GC0,
-case__1439: APBGpsBlock__GC0,
-muxpart__211: FPU__GB0,
-logic__3305: FPU__GB1,
-reg__958: VCU118RocketSystem__GC0,
-logic__8410: APBGpsBlock__GC0,
-reg__431: RocketTile__GCB0,
-logic__8337: APBGpsBlock__GC0,
-datapath__287: DCache,
-logic__1516: VCU118RocketSystem__GC0,
-cordic_angle_lut__parameterized0: tracking_wrapper,
-datapath__560: APBGpsBlock__GC0,
-logic__8113: VCU118RocketSystem__GC0,
-reg__434: RocketTile__GCB0,
-dsp48e2__40: tracking_wrapper,
-case__1287: APBGpsBlock__GC0,
-reg__740: RocketTile__GCB0,
-case__577: RocketTile__GCB0,
-logic__439: vcu118_rocket_top__GC0,
-reg__619: FPU__GB1,
-reg__1097: APBGpsBlock__GC0,
-case__994: VCU118RocketSystem__GC0,
-logic__3483: FPU__GB1,
-logic__6810: VCU118RocketSystem__GC0,
-PMPChecker_s3: DCache,
-logic__3314: FPU__GB1,
-logic__9222: tracking_wrapper,
-logic__3029: RocketTile__GCB0,
-logic__5255: RocketTile__GCB0,
-datapath__580: APBGpsBlock__GC0,
-logic__1508: VCU118RocketSystem__GC0,
-reg__705: RocketTile__GCB0,
-logic__4781: FPU__GB2,
-logic__4870: FPU__GB2,
-case__720: FPU__GB1,
-reg__565: FPU__GB1,
-logic__5938: RocketTile__GCB0,
-logic__4877: FPU__GB2,
-datapath__313: RocketTile__GCB0,
-logic__5379: RocketTile__GCB0,
-case__412: VCU118RocketSystem__GC0,
-logic__3847: FPU__GB2,
-reg__1240: tracking_wrapper,
-reg__275: VCU118RocketSystem__GC0,
-logic__3659: FPU__GB2, FPU__GB1,
-datapath__38: VCU118RocketSystem__GC0,
-logic__9309: tracking_wrapper,
-datapath__87: VCU118RocketSystem__GC0,
-datapath__35: VCU118RocketSystem__GC0,
-datapath__333: FPU__GB2,
-muxpart__150: vcu118_rocket_top__GC0,
-logic__7016: VCU118RocketSystem__GC0,
-reg__236: VCU118RocketSystem__GC0,
-logic__2666: DCache,
-reg__959: VCU118RocketSystem__GC0,
-case__1159: VCU118RocketSystem__GC0,
-datapath__422: RocketTile__GCB0,
-logic__7778: VCU118RocketSystem__GC0,
-logic__6639: RocketTile__GCB0,
-case__205: vcu118_rocket_top__GC0,
-logic__6929: VCU118RocketSystem__GC0,
-logic__2287: DCache,
-reg__1049: VCU118RocketSystem__GC0,
-case__204: vcu118_rocket_top__GC0,
-logic__1917: VCU118RocketSystem__GC0,
-logic__1098: VCU118RocketSystem__GC0,
-reg__92: vcu118_rocket_top__GC0,
-case__1189: VCU118RocketSystem__GC0,
-reg__993: VCU118RocketSystem__GC0,
-reg__686: RocketTile__GCB0,
-reg__24: vcu118_rocket_top__GC0,
-reg__357: DCache,
-logic__234: vcu118_rocket_top__GC0,
-case__342: VCU118RocketSystem__GC0,
-logic__5530: RocketTile__GCB0,
-case__895: RocketTile__GCB0,
-reg__1341: tracking_wrapper,
-logic__1810: VCU118RocketSystem__GC0,
-reg__872: VCU118RocketSystem__GC0,
-reg__360: DCache,
-logic__7338: VCU118RocketSystem__GC0,
-datapath__40: VCU118RocketSystem__GC0,
-logic__8175: VCU118RocketSystem__GC0,
-logic__7073: VCU118RocketSystem__GC0,
-logic__9136: tracking_wrapper,
-logic__8070: VCU118RocketSystem__GC0,
-case__809: RocketTile__GCB0,
-case__387: VCU118RocketSystem__GC0,
-logic__4466: FPU__GB1,
-logic__7082: VCU118RocketSystem__GC0,
-datapath__60: VCU118RocketSystem__GC0,
-logic__3996: FPU__GB2,
-logic__5579: RocketTile__GCB0,
-reg__25: vcu118_rocket_top__GC0,
-datapath__641: APBGpsBlock__GC0,
-logic__9432: TLToAPB,
-datapath__107: VCU118RocketSystem__GC0,
-reg__123: VCU118RocketSystem__GC0,
-case__1685: TLToAPB,
-logic__2928: DCache,
-logic__4521: FPU__GB1,
-case__731: FPU__GB2, FPU__GB1,
-dsp48e2__42: tracking_wrapper,
-logic__4992: FPU__GB2,
-reg__861: VCU118RocketSystem__GC0,
-case__1087: VCU118RocketSystem__GC0,
-logic__1248: VCU118RocketSystem__GC0,
-rom__6: tracking_wrapper,
-logic__5055: FPU__GB1,
-NCO_carr: tracking_wrapper,
-muxpart__275: VCU118RocketSystem__GC0,
-reg__157: VCU118RocketSystem__GC0,
-logic__2726: DCache,
-logic__4490: FPU__GB1,
-reg__510: FPU__GB1,
-case: vcu118_rocket_top__GC0,
-TLBuffer_a32d64s2k1z4u_1: VCU118RocketSystem__GC0,
-logic__3794: FPU__GB2,
-case__1368: APBGpsBlock__GC0,
-reg__1347: tracking_wrapper,
-reg__216: VCU118RocketSystem__GC0,
-logic__2263: DCache,
-case__1227: VCU118RocketSystem__GC0,
-logic__7039: VCU118RocketSystem__GC0,
-case__289: VCU118RocketSystem__GC0,
-reg__902: VCU118RocketSystem__GC0,
-case__141: vcu118_rocket_top__GC0,
-reg__1295: tracking_wrapper,
-reg__1153: APBGpsBlock__GC0,
-datapath__388: FPU__GB2, FPU__GB1,
-case__1126: VCU118RocketSystem__GC0,
-IntToFP: FPU__GB2,
-AsyncQueueSink_DebugInternalBundle: VCU118RocketSystem__GC0,
-reg__718: RocketTile__GCB0,
-datapath__158: VCU118RocketSystem__GC0,
-logic__6899: VCU118RocketSystem__GC0,
-logic__2989: RocketTile__GCB0,
-reg__1059: VCU118RocketSystem__GC0,
-muxpart__174: VCU118RocketSystem__GC0,
-logic__6129: RocketTile__GCB0,
-reg__904: VCU118RocketSystem__GC0,
-logic__6362: RocketTile__GCB0,
-case__5: vcu118_rocket_top__GC0,
-logic__857: VCU118RocketSystem__GC0,
-reg__74: vcu118_rocket_top__GC0,
-datapath__445: RocketTile__GCB0,
-TLError: VCU118RocketSystem__GC0,
-reg__756: RocketTile__GCB0,
-reg__625: FPU__GB1,
-reg__1399: TLToAPB,
-logic__7980: VCU118RocketSystem__GC0,
-logic__7423: VCU118RocketSystem__GC0,
-case__845: RocketTile__GCB0,
-reg__652: RocketTile__GCB0,
-logic__7673: VCU118RocketSystem__GC0,
-logic__6924: VCU118RocketSystem__GC0,
-datapath__607: APBGpsBlock__GC0,
-logic__5670: RocketTile__GCB0,
-counter__9: DCache,
-logic__6728: RocketTile__GCB0,
-case__1649: tracking_wrapper,
-datapath__119: VCU118RocketSystem__GC0,
-reg__13: vcu118_rocket_top__GC0,
-case__1378: APBGpsBlock__GC0,
-reg__171: VCU118RocketSystem__GC0,
-reg__623: FPU__GB1,
-reg__977: VCU118RocketSystem__GC0,
-case__443: VCU118RocketSystem__GC0,
-DTLB: DCache,
-logic__4318: FPU__GB1,
-reg__283: VCU118RocketSystem__GC0,
-logic__2678: DCache,
-muxpart__271: RocketTile__GCB0,
-logic__5436: RocketTile__GCB0,
-logic__7259: VCU118RocketSystem__GC0,
-logic__8953: tracking_wrapper,
-logic__5598: RocketTile__GCB0,
-logic__5314: RocketTile__GCB0,
-logic__5306: RocketTile__GCB0,
-logic__1497: VCU118RocketSystem__GC0,
-logic__7619: VCU118RocketSystem__GC0,
-logic__7252: VCU118RocketSystem__GC0,
-logic__6523: RocketTile__GCB0,
-reg__1398: TLToAPB,
-case__487: RocketTile__GCB0,
-reg__495: FPU__GB1,
-datapath__490: RocketTile__GCB0,
-reg__1095: APBGpsBlock__GC0,
-reg__365: DCache,
-case__732: FPU__GB2, FPU__GB1,
-reg__1324: tracking_wrapper,
-logic__2898: DCache,
-logic__7993: VCU118RocketSystem__GC0,
-reg__508: FPU__GB1,
-logic__7981: VCU118RocketSystem__GC0,
-logic__7245: VCU118RocketSystem__GC0,
-logic__4351: FPU__GB1,
-reg__580: FPU__GB2,
-reg__930: VCU118RocketSystem__GC0,
-reg__312: VCU118RocketSystem__GC0,
-reg__382: RocketTile__GCB0,
-muxpart__247: FPU__GB0,
-reg__1075: APBGpsBlock__GC0,
-reg__1074: APBGpsBlock__GC0,
-reg__1288: tracking_wrapper,
-muxpart__352: APBGpsBlock__GC0,
-case__728: FPU__GB2, FPU__GB1,
-case__837: RocketTile__GCB0,
-case__1155: VCU118RocketSystem__GC0,
-case__332: VCU118RocketSystem__GC0,
-reg__1060: VCU118RocketSystem__GC0,
-logic__7532: VCU118RocketSystem__GC0,
-reg__653: RocketTile__GCB0,
-datapath__573: APBGpsBlock__GC0,
-muxpart__262: RocketTile__GCB0,
-datapath__294: RocketTile__GCB0,
-Repeater_TLBundleA_a29d32s2k1z3u: VCU118RocketSystem__GC0,
-logic__6560: RocketTile__GCB0,
-reg__82: vcu118_rocket_top__GC0,
-logic__7845: VCU118RocketSystem__GC0,
-logic__2357: DCache,
-logic__7096: VCU118RocketSystem__GC0,
-logic__8272: APBGpsBlock__GC0,
-datapath__693: tracking_wrapper,
-logic__6652: RocketTile__GCB0,
-logic__2704: DCache,
-reg__782: RocketTile__GCB0,
-reg__649: FPU__GB1,
-reg__32: vcu118_rocket_top__GC0,
-datapath__190: VCU118RocketSystem__GC0,
-datapath__494: TilePRCIDomain__GC0,
-muxpart__65: vcu118_rocket_top__GC0,
-datapath__4: vcu118_rocket_top__GC0,
-logic__7703: VCU118RocketSystem__GC0,
-case__1686: TLToAPB,
-logic__5498: RocketTile__GCB0,
-reg__1243: tracking_wrapper,
-logic__4963: FPU__GB2,
-reg__742: RocketTile__GCB0,
-logic__4785: FPU__GB2,
-datapath__706: tracking_wrapper,
-logic__102: vcu118_rocket_top__GC0,
-logic__3107: RocketTile__GCB0,
-logic__6609: RocketTile__GCB0,
-logic__4702: FPU__GB2,
-logic__7613: VCU118RocketSystem__GC0,
-logic__1888: VCU118RocketSystem__GC0,
-logic__6173: RocketTile__GCB0,
-logic__3324: FPU__GB1,
-case__1676: APBGpsBlock__GC0,
-logic__6038: RocketTile__GCB0,
-reg__177: VCU118RocketSystem__GC0,
-reg__1400: TLToAPB,
-reg__1147: APBGpsBlock__GC0,
-muxpart__189: FPU__GB0,
-reg__247: VCU118RocketSystem__GC0,
-TLFragmenter_FPGAGPS: VCU118RocketSystem__GC0,
-case__1338: APBGpsBlock__GC0,
-logic__2054: VCU118RocketSystem__GC0,
-logic__4947: FPU__GB2,
-datapath__625: APBGpsBlock__GC0,
-logic__1571: VCU118RocketSystem__GC0,
-logic__4706: FPU__GB2,
-logic__6778: VCU118RocketSystem__GC0,
-case__447: VCU118RocketSystem__GC0,
-logic__6001: RocketTile__GCB0,
-reg__466: FPU__GB0,
-case__1154: VCU118RocketSystem__GC0,
-logic__7134: VCU118RocketSystem__GC0,
-logic__6650: RocketTile__GCB0,
-reg__654: RocketTile__GCB0,
-logic__2822: DCache,
-case__513: DCache,
-reg__81: vcu118_rocket_top__GC0,
-reg__916: VCU118RocketSystem__GC0,
-case__1598: tracking_wrapper,
-reg__208: VCU118RocketSystem__GC0,
-case__933: RocketTile__GCB0,
-muxpart__243: FPU__GB0,
-reg__917: VCU118RocketSystem__GC0,
-case__391: VCU118RocketSystem__GC0,
-logic__3798: FPU__GB2,
-logic__2123: RocketTile__GCB0,
-case__422: VCU118RocketSystem__GC0,
-case__877: RocketTile__GCB0,
-logic__332: vcu118_rocket_top__GC0,
-datapath__539: VCU118RocketSystem__GC0,
-logic__6524: RocketTile__GCB0,
-reg__1195: APBGpsBlock__GC0,
-logic__5511: RocketTile__GCB0,
-case__1117: VCU118RocketSystem__GC0,
-logic__1945: VCU118RocketSystem__GC0,
-reg__1016: VCU118RocketSystem__GC0,
-reg__1219: tracking_wrapper,
-logic__2103: RocketTile__GCB0,
-reg__1054: VCU118RocketSystem__GC0,
-logic__1589: VCU118RocketSystem__GC0,
-reg__1050: VCU118RocketSystem__GC0,
-logic__912: VCU118RocketSystem__GC0,
-reg__1131: APBGpsBlock__GC0,
-datapath__478: RocketTile__GCB0,
-logic__4803: FPU__GB2,
-logic__5595: RocketTile__GCB0,
-datapath__350: FPU__GB2,
-reg__1296: tracking_wrapper,
-logic__7395: VCU118RocketSystem__GC0,
-logic__843: VCU118RocketSystem__GC0,
-reg__465: FPU__GB0,
-logic__230: vcu118_rocket_top__GC0,
-logic__4719: FPU__GB2,
-logic__4545: FPU__GB2, FPU__GB1,
-muxpart__60: vcu118_rocket_top__GC0,
-logic__1910: VCU118RocketSystem__GC0,
-case__770: FPU__GB2,
-case__1031: VCU118RocketSystem__GC0,
-logic__5496: RocketTile__GCB0,
-case__493: RocketTile__GCB0,
-logic__5270: RocketTile__GCB0,
-logic__6769: VCU118RocketSystem__GC0,
-case__433: VCU118RocketSystem__GC0,
-logic__1392: VCU118RocketSystem__GC0,
-logic__2060: RocketTile__GCB0,
-extram__9: APBGpsBlock__GC0,
-reg__143: VCU118RocketSystem__GC0,
-logic__8164: VCU118RocketSystem__GC0,
-case__1376: APBGpsBlock__GC0,
-logic__5461: RocketTile__GCB0,
-logic__4255: FPU__GB1,
-datapath__682: tracking_wrapper,
-case__723: FPU__GB2, FPU__GB1,
-logic__7296: VCU118RocketSystem__GC0,
-case__547: DCache,
-reg__813: RocketTile__GCB0,
-case__1293: APBGpsBlock__GC0,
-logic__5762: RocketTile__GCB0,
-case__1538: tracking_wrapper,
-logic__5997: RocketTile__GCB0,
-logic__5977: RocketTile__GCB0,
-logic__4894: FPU__GB2,
-reg__1018: VCU118RocketSystem__GC0,
-logic__1007: VCU118RocketSystem__GC0,
-logic__5523: RocketTile__GCB0,
-logic__1222: VCU118RocketSystem__GC0,
-logic__9331: tracking_wrapper,
-logic__4247: FPU__GB1,
-logic__7832: VCU118RocketSystem__GC0,
-TLXbar_dmixbar_i1_o2_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__6744: VCU118RocketSystem__GC0,
-reg__830: RocketTile__GCB0,
-reg__667: RocketTile__GCB0,
-datapath__426: RocketTile__GCB0,
-datapath__584: APBGpsBlock__GC0,
-rockettile_icache_data_arrays_512x32: RocketTile__GCB0,
-case__1648: tracking_wrapper,
-case__1553: tracking_wrapper,
-logic__5302: RocketTile__GCB0,
-logic__2084: RocketTile__GCB0,
-reg__602: FPU__GB2,
-reg__214: VCU118RocketSystem__GC0,
-logic__5706: RocketTile__GCB0,
-logic__7894: VCU118RocketSystem__GC0,
-logic__6827: VCU118RocketSystem__GC0,
-datapath__51: VCU118RocketSystem__GC0,
-reg__422: RocketTile__GCB0,
-reg__512: FPU__GB2,
-logic__4778: FPU__GB2,
-logic__1258: VCU118RocketSystem__GC0,
-logic__5267: RocketTile__GCB0,
-reg__784: RocketTile__GCB0,
-PMPChecker_s2: RocketTile__GCB0,
-datapath__274: DCache,
-case__594: RocketTile__GCB0,
-logic__7777: VCU118RocketSystem__GC0,
-logic__8275: APBGpsBlock__GC0,
-reg__770: RocketTile__GCB0,
-case__130: vcu118_rocket_top__GC0,
-logic__5877: RocketTile__GCB0,
-case__1200: VCU118RocketSystem__GC0,
-case__1095: VCU118RocketSystem__GC0,
-logic__4398: FPU__GB1,
-logic__4480: FPU__GB1,
-logic__4614: FPU__GB2, FPU__GB1,
-DCacheDataArray: DCache,
-logic__5283: RocketTile__GCB0,
-logic__1115: VCU118RocketSystem__GC0,
-reg__354: DCache,
-case__1503: APBGpsBlock__GC0,
-muxpart__63: vcu118_rocket_top__GC0,
-logic__183: vcu118_rocket_top__GC0,
-logic__8127: VCU118RocketSystem__GC0,
-datapath__36: VCU118RocketSystem__GC0,
-reg__918: VCU118RocketSystem__GC0,
-logic__835: VCU118RocketSystem__GC0,
-case__1037: VCU118RocketSystem__GC0,
-logic__6604: RocketTile__GCB0,
-reg__488: FPU__GB1,
-case__1255: APBGpsBlock__GC0,
-reg__458: FPU__GB0,
-reg__1263: tracking_wrapper,
-case__1207: VCU118RocketSystem__GC0,
-logic__2721: DCache,
-TLFpgaSPI: VCU118RocketSystem__GC0,
-case__991: VCU118RocketSystem__GC0,
-datapath__289: DCache,
-counter__13: APBGpsBlock__GC0,
-case__906: RocketTile__GCB0,
-logic__6740: VCU118RocketSystem__GC0,
-reg__772: RocketTile__GCB0,
-logic__7556: VCU118RocketSystem__GC0,
-logic__3205: RocketTile__GCB0,
-reg__1278: tracking_wrapper,
-reg__1355: tracking_wrapper,
-reg__1184: APBGpsBlock__GC0,
-logic__1668: VCU118RocketSystem__GC0,
-LF_carr: tracking_wrapper,
-logic__8198: VCU118RocketSystem__GC0,
-reg__301: VCU118RocketSystem__GC0,
-reg__460: FPU__GB0,
-logic__6476: RocketTile__GCB0,
-reg__611: FPU__GB1,
-logic__5446: RocketTile__GCB0,
-logic__2817: DCache,
-logic__2190: DCache,
-logic__2000: VCU118RocketSystem__GC0,
-logic__6623: RocketTile__GCB0,
-logic__3318: FPU__GB1,
-logic__7030: VCU118RocketSystem__GC0,
-datapath__280: DCache,
-logic__6050: RocketTile__GCB0,
-case__1007: VCU118RocketSystem__GC0,
-case__1185: VCU118RocketSystem__GC0,
-logic__6725: RocketTile__GCB0,
-logic__8972: tracking_wrapper,
-muxpart__67: vcu118_rocket_top__GC0,
-case__1149: VCU118RocketSystem__GC0,
-datapath__99: VCU118RocketSystem__GC0,
-logic__186: vcu118_rocket_top__GC0,
-logic__8368: APBGpsBlock__GC0,
-logic__6703: RocketTile__GCB0,
-logic__6557: RocketTile__GCB0,
-logic__4766: FPU__GB2,
-logic__3597: FPU__GB2, FPU__GB1,
-logic__3840: FPU__GB2,
-logic__2237: DCache,
-datapath__554: VCU118RocketSystem__GC0,
-reg__1259: tracking_wrapper,
-logic__4755: FPU__GB2,
-logic__8742: APBGpsBlock__GC0,
-case__795: FPU__GB1,
-reg__37: vcu118_rocket_top__GC0,
-logic__5342: RocketTile__GCB0,
-logic__4826: FPU__GB2,
-logic__9421: APBGpsBlock__GC0,
-logic__7367: VCU118RocketSystem__GC0,
-logic__5660: RocketTile__GCB0,
-logic__5468: RocketTile__GCB0,
-logic__8954: tracking_wrapper,
-case__211: vcu118_rocket_top__GC0,
-logic__3243: RocketTile__GCB0,
-logic__3500: FPU__GB1,
-logic__4409: FPU__GB1,
-logic__1522: VCU118RocketSystem__GC0,
-logic__3695: FPU__GB2,
-reg__1002: VCU118RocketSystem__GC0,
-datapath__163: VCU118RocketSystem__GC0,
-reg__63: vcu118_rocket_top__GC0,
-reg__319: DCache,
-datapath__568: APBGpsBlock__GC0,
-reg__773: RocketTile__GCB0,
-logic__767: VCU118RocketSystem__GC0,
-case__1032: VCU118RocketSystem__GC0,
-logic__7105: VCU118RocketSystem__GC0,
-logic__7023: VCU118RocketSystem__GC0,
-reg__678: RocketTile__GCB0,
-logic__5533: RocketTile__GCB0,
-muxpart__251: FPU__GB0,
-logic__6054: RocketTile__GCB0,
-logic__3797: FPU__GB2,
-logic__3820: FPU__GB2,
-muxpart__23: vcu118_rocket_top__GC0,
-datapath__649: APBGpsBlock__GC0,
-datapath__178: VCU118RocketSystem__GC0,
-case__517: DCache,
-case__175: vcu118_rocket_top__GC0,
-logic__7942: VCU118RocketSystem__GC0,
-case__1027: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_sbus_from_bus_named_fbus: VCU118RocketSystem__GC0,
-logic__9236: tracking_wrapper,
-Repeater_TLBundleA_a26d64s2k1z3u: VCU118RocketSystem__GC0,
-datapath__79: VCU118RocketSystem__GC0,
-reg__1342: tracking_wrapper,
-reg__1408: vcu118_rocket_top__GC0,
-logic__3602: FPU__GB2, FPU__GB1,
-logic__9385: APBGpsBlock__GC0,
-cacode_gen_trck: tracking_wrapper,
-reg__359: DCache,
-logic__6603: RocketTile__GCB0,
-reg__1077: APBGpsBlock__GC0,
-logic__941: VCU118RocketSystem__GC0,
-PeripheryBus_pbus: VCU118RocketSystem__GC0,
-logic__8987: tracking_wrapper,
-logic__123: vcu118_rocket_top__GC0,
-logic__7106: VCU118RocketSystem__GC0,
-case__1579: tracking_wrapper,
-logic__721: vcu118_rocket_top__GC0,
-case__1073: VCU118RocketSystem__GC0,
-datapath__675: tracking_wrapper,
-case__347: VCU118RocketSystem__GC0,
-case__550: DCache,
-reg__537: FPU__GB1,
-logic__2544: DCache,
-logic__2079: RocketTile__GCB0,
-case__1610: tracking_wrapper,
-muxpart__186: FPU__GB0,
-logic__768: VCU118RocketSystem__GC0,
-datapath__39: VCU118RocketSystem__GC0,
-reg__856: VCU118RocketSystem__GC0,
-logic__8823: tracking_wrapper,
-logic__2651: DCache,
-muxpart__241: FPU__GB0,
-FPGASPIClockSinkDomain: VCU118RocketSystem__GC0,
-reg__1052: VCU118RocketSystem__GC0,
-reg__228: VCU118RocketSystem__GC0,
-logic__1538: VCU118RocketSystem__GC0,
-logic__4231: FPU__GB1,
-logic__4037: FPU__GB2,
-datapath__652: APBGpsBlock__GC0,
-case__1339: APBGpsBlock__GC0,
-logic__8505: APBGpsBlock__GC0,
-logic__6552: RocketTile__GCB0,
-logic__5416: RocketTile__GCB0,
-case__159: vcu118_rocket_top__GC0,
-case__3: vcu118_rocket_top__GC0,
-logic__1330: VCU118RocketSystem__GC0,
-logic__6605: RocketTile__GCB0,
-logic__3034: RocketTile__GCB0,
-TLBusBypass: VCU118RocketSystem__GC0,
-logic__1941: VCU118RocketSystem__GC0,
-datapath__710: tracking_wrapper,
-logic__925: VCU118RocketSystem__GC0,
-logic__5151: FPU__GB1,
-case__1197: VCU118RocketSystem__GC0,
-logic__7424: VCU118RocketSystem__GC0,
-logic__1477: VCU118RocketSystem__GC0,
-case__871: RocketTile__GCB0,
-case__946: RocketTile__GCB0,
-reg__323: DCache,
-muxpart__26: vcu118_rocket_top__GC0,
-reg__800: RocketTile__GCB0,
-reg__586: FPU__GB2,
-reg__1321: tracking_wrapper,
-logic__6754: VCU118RocketSystem__GC0,
-logic__437: vcu118_rocket_top__GC0,
-reg__887: VCU118RocketSystem__GC0,
-logic__2758: DCache,
-case__1020: VCU118RocketSystem__GC0,
-logic__1596: VCU118RocketSystem__GC0,
-case__485: RocketTile__GCB0,
-CompareRecFN: FPU__GB2,
-logic__666: vcu118_rocket_top__GC0,
-logic__1577: VCU118RocketSystem__GC0,
-datapath__385: FPU__GB1,
-datapath__725: tracking_wrapper,
-reg__293: VCU118RocketSystem__GC0,
-case__280: VCU118RocketSystem__GC0,
-logic__5004: FPU__GB1,
-logic__405: vcu118_rocket_top__GC0,
-reg__764: RocketTile__GCB0,
-logic__1777: VCU118RocketSystem__GC0,
-logic__1403: VCU118RocketSystem__GC0,
-muxpart__187: FPU__GB0,
-logic__6865: VCU118RocketSystem__GC0,
-logic__4401: FPU__GB1,
-logic__5332: RocketTile__GCB0,
-logic__5826: RocketTile__GCB0,
-logic__2145: RocketTile__GCB0,
-reg__59: vcu118_rocket_top__GC0,
-logic__4024: FPU__GB2,
-muxpart__52: vcu118_rocket_top__GC0,
-logic__1827: VCU118RocketSystem__GC0,
-reg__1148: APBGpsBlock__GC0,
-reg__1397: TLToAPB,
-logic__8055: VCU118RocketSystem__GC0,
-reg__164: VCU118RocketSystem__GC0,
-logic__5623: RocketTile__GCB0,
-TLFragmenter_PLIC: VCU118RocketSystem__GC0,
-reg__679: RocketTile__GCB0,
-logic__5521: RocketTile__GCB0,
-logic__4850: FPU__GB2,
-logic__6998: VCU118RocketSystem__GC0,
-reg__1019: VCU118RocketSystem__GC0,
-case__752: FPU__GB2,
-logic__4686: FPU__GB2,
-logic__2605: DCache,
-reg__1167: APBGpsBlock__GC0,
-logic__5014: FPU__GB1,
-logic__3501: FPU__GB1,
-logic__2851: DCache,
-case__1238: VCU118RocketSystem__GC0,
-logic__7789: VCU118RocketSystem__GC0,
-logic__8326: APBGpsBlock__GC0,
-logic__3958: FPU__GB2,
-reg__1080: APBGpsBlock__GC0,
-accum_dump: tracking_wrapper,
-reg__1394: tracking_wrapper,
-logic__869: VCU118RocketSystem__GC0,
-case__1563: tracking_wrapper,
-datapath__630: APBGpsBlock__GC0,
-muxpart__240: FPU__GB0,
-logic__4141: FPU__GB1,
-reg__992: VCU118RocketSystem__GC0,
-datapath__614: APBGpsBlock__GC0,
-logic__5925: RocketTile__GCB0,
-case__634: RocketTile__GCB0,
-logic__3146: RocketTile__GCB0,
-logic__5234: RocketTile__GCB0,
-reg__676: RocketTile__GCB0,
-case__1211: VCU118RocketSystem__GC0,
-datapath__306: RocketTile__GCB0,
-case__1613: tracking_wrapper,
-logic__712: vcu118_rocket_top__GC0,
-logic__8162: VCU118RocketSystem__GC0,
-datapath__583: APBGpsBlock__GC0,
-case__585: RocketTile__GCB0,
-logic__1281: VCU118RocketSystem__GC0,
-logic__7747: VCU118RocketSystem__GC0,
-logic__1311: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__515: FPU__GB2,
-datapath__553: VCU118RocketSystem__GC0,
-muxpart__91: vcu118_rocket_top__GC0,
-keep__6: vcu118_rocket_top__GC0,
-logic__4393: FPU__GB1,
-TLAtomicAutomata_cbus: VCU118RocketSystem__GC0,
-counter__6: vcu118_rocket_top__GC0,
-case__1025: VCU118RocketSystem__GC0,
-logic__9336: tracking_wrapper,
-reg__335: DCache,
-case__1510: APBGpsBlock__GC0,
-reg__991: VCU118RocketSystem__GC0,
-logic__4827: FPU__GB2,
-case__1071: VCU118RocketSystem__GC0,
-reg__684: RocketTile__GCB0,
-logic__8959: tracking_wrapper,
-case__1418: APBGpsBlock__GC0,
-datapath__638: APBGpsBlock__GC0,
-case__597: RocketTile__GCB0,
-case__297: VCU118RocketSystem__GC0,
-reg__498: FPU__GB1,
-logic__5606: RocketTile__GCB0,
-logic__807: VCU118RocketSystem__GC0,
-logic__2698: DCache,
-reg__737: RocketTile__GCB0,
-logic__6588: RocketTile__GCB0,
-logic__1503: VCU118RocketSystem__GC0,
-reg__657: RocketTile__GCB0,
-reg__750: RocketTile__GCB0,
-logic__6164: RocketTile__GCB0,
-logic__7433: VCU118RocketSystem__GC0,
-logic__1243: VCU118RocketSystem__GC0,
-logic__4818: FPU__GB2,
-reg__915: VCU118RocketSystem__GC0,
-logic__6984: VCU118RocketSystem__GC0,
-case__1101: VCU118RocketSystem__GC0,
-reg__1245: tracking_wrapper,
-case__396: VCU118RocketSystem__GC0,
-logic__4467: FPU__GB1,
-datapath__643: APBGpsBlock__GC0,
-case__647: FPU__GB1,
-case__990: VCU118RocketSystem__GC0,
-logic__9128: tracking_wrapper,
-muxpart__378: tracking_wrapper,
-reg__326: DCache,
-logic__4162: FPU__GB1,
-logic__3455: FPU__GB1,
-muxpart__78: vcu118_rocket_top__GC0,
-logic__7209: VCU118RocketSystem__GC0,
-reg__351: DCache,
-reg__805: RocketTile__GCB0,
-case__1299: APBGpsBlock__GC0,
-case__222: vcu118_rocket_top__GC0,
-logic__7057: VCU118RocketSystem__GC0,
-case__446: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_sbus_from_rockettile: VCU118RocketSystem__GC0,
-logic__2807: DCache,
-logic__7258: VCU118RocketSystem__GC0,
-logic__7625: VCU118RocketSystem__GC0,
-reg__600: FPU__GB2,
-datapath__689: tracking_wrapper,
-case__935: RocketTile__GCB0,
-logic__5219: RocketTile__GCB0,
-reg__1093: APBGpsBlock__GC0,
-logic__7490: VCU118RocketSystem__GC0,
-muxpart__225: FPU__GB0,
-case__1673: APBGpsBlock__GC0,
-logic__2415: DCache,
-muxpart__87: vcu118_rocket_top__GC0,
-case__1005: VCU118RocketSystem__GC0,
-logic__6615: RocketTile__GCB0,
-case__1237: VCU118RocketSystem__GC0,
-logic__2488: RocketTile__GCB0, DCache,
-logic__3482: FPU__GB1,
-logic__78: vcu118_rocket_top__GC0,
-case__548: DCache,
-logic__4356: FPU__GB1,
-case__622: RocketTile__GCB0,
-logic__2532: RocketTile__GCB0, DCache,
-reg__292: VCU118RocketSystem__GC0,
-logic__973: VCU118RocketSystem__GC0,
-case__270: VCU118RocketSystem__GC0,
-logic__1015: VCU118RocketSystem__GC0,
-fft_radix_2__parameterized0: APBGpsBlock__GC0,
-logic__2440: DCache,
-logic__5665: RocketTile__GCB0,
-logic__5005: FPU__GB1,
-reg__564: FPU__GB1,
-case__612: RocketTile__GCB0,
-logic__6900: VCU118RocketSystem__GC0,
-reg__211: VCU118RocketSystem__GC0,
-datapath__496: TilePRCIDomain__GC0,
-logic__3601: FPU__GB2, FPU__GB1,
-logic__5755: RocketTile__GCB0,
-datapath__152: VCU118RocketSystem__GC0,
-case__278: VCU118RocketSystem__GC0,
-case__833: RocketTile__GCB0,
-case__858: RocketTile__GCB0,
-case__1182: VCU118RocketSystem__GC0,
-reg__873: VCU118RocketSystem__GC0,
-logic__2028: VCU118RocketSystem__GC0,
-logic__1807: VCU118RocketSystem__GC0,
-logic__1500: VCU118RocketSystem__GC0,
-reg__1310: tracking_wrapper,
-logic__1038: VCU118RocketSystem__GC0,
-reg__1267: tracking_wrapper,
-datapath__248: VCU118RocketSystem__GC0,
-logic__6662: RocketTile__GCB0,
-reg__685: RocketTile__GCB0,
-logic__3486: FPU__GB1,
-reg__100: vcu118_rocket_top__GC0,
-case__595: RocketTile__GCB0,
-case__323: VCU118RocketSystem__GC0,
-case__265: VCU118RocketSystem__GC0,
-datapath__328: FPU__GB2, FPU__GB1,
-muxpart__29: vcu118_rocket_top__GC0,
-reg__117: VCU118RocketSystem__GC0,
-case__309: VCU118RocketSystem__GC0,
-Frontend: RocketTile__GCB0,
-logic__7201: VCU118RocketSystem__GC0,
-case__356: VCU118RocketSystem__GC0,
-reg__389: RocketTile__GCB0,
-logic__1801: VCU118RocketSystem__GC0,
-case__436: VCU118RocketSystem__GC0,
-muxpart__384: tracking_wrapper,
-case__507: DCache,
-case__35: vcu118_rocket_top__GC0,
-reg__1285: tracking_wrapper,
-logic__393: vcu118_rocket_top__GC0,
-logic__2627: DCache,
-case__1206: VCU118RocketSystem__GC0,
-reg__1340: tracking_wrapper,
-logic__6925: VCU118RocketSystem__GC0,
-datapath__587: APBGpsBlock__GC0,
-case__1108: VCU118RocketSystem__GC0,
-logic__3510: FPU__GB1,
-logic__7345: VCU118RocketSystem__GC0,
-logic__8493: APBGpsBlock__GC0,
-datapath__639: APBGpsBlock__GC0,
-case__1055: VCU118RocketSystem__GC0,
-reg__883: VCU118RocketSystem__GC0,
-logic__2031: VCU118RocketSystem__GC0,
-case__950: RocketTile__GCB0,
-logic__2092: RocketTile__GCB0,
-case__1506: APBGpsBlock__GC0,
-case__474: VCU118RocketSystem__GC0,
-case__610: RocketTile__GCB0,
-datapath__537: VCU118RocketSystem__GC0,
-logic__6132: RocketTile__GCB0,
-logic__448: vcu118_rocket_top__GC0,
-logic__7994: VCU118RocketSystem__GC0,
-logic__1867: VCU118RocketSystem__GC0,
-reg__242: VCU118RocketSystem__GC0,
-logic__5271: RocketTile__GCB0,
-reg__895: VCU118RocketSystem__GC0,
-datapath__460: RocketTile__GCB0,
-datapath__273: DCache,
-case__325: VCU118RocketSystem__GC0,
-logic__1140: VCU118RocketSystem__GC0,
-reg__1262: tracking_wrapper,
-logic__2435: DCache,
-logic__5193: RocketTile__GCB0,
-logic__915: VCU118RocketSystem__GC0,
-logic__7905: VCU118RocketSystem__GC0,
-logic__2155: DCache,
-datapath__430: RocketTile__GCB0,
-logic__4392: FPU__GB1,
-counter__33: VCU118RocketSystem__GC0,
-logic__3010: RocketTile__GCB0,
-logic__1342: VCU118RocketSystem__GC0,
-logic__2933: DCache,
-logic__7339: VCU118RocketSystem__GC0,
-IntSyncAsyncCrossingSink_n1x1: TilePRCIDomain__GC0,
-logic__6335: RocketTile__GCB0,
-logic__2198: DCache,
-datapath__455: RocketTile__GCB0,
-logic__7637: VCU118RocketSystem__GC0,
-reg__353: DCache,
-case__470: VCU118RocketSystem__GC0,
-case__520: DCache,
-logic__2409: DCache,
-muxpart__328: APBGpsBlock__GC0,
-logic__7276: VCU118RocketSystem__GC0,
-datapath__191: VCU118RocketSystem__GC0,
-case__758: FPU__GB2,
-logic__1894: VCU118RocketSystem__GC0,
-logic__1796: VCU118RocketSystem__GC0,
-logic__5948: RocketTile__GCB0,
-logic__3250: RocketTile__GCB0,
-logic__6995: VCU118RocketSystem__GC0,
-logic__7010: VCU118RocketSystem__GC0,
-logic__4349: FPU__GB1,
-case__1148: VCU118RocketSystem__GC0,
-logic__5430: RocketTile__GCB0,
-logic__9332: tracking_wrapper,
-case__1604: tracking_wrapper,
-muxpart__188: FPU__GB0,
-reg__200: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__1071: APBGpsBlock__GC0,
-reg__151: VCU118RocketSystem__GC0,
-logic__7147: VCU118RocketSystem__GC0,
-reg__1260: tracking_wrapper,
-reg__277: VCU118RocketSystem__GC0,
-logic__5936: RocketTile__GCB0,
-logic__935: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-muxpart__149: vcu118_rocket_top__GC0,
-case__244: VCU118RocketSystem__GC0,
-logic__3063: RocketTile__GCB0,
-logic__5256: RocketTile__GCB0,
-logic__3454: FPU__GB1,
-logic__7405: VCU118RocketSystem__GC0,
-logic__2335: DCache,
-reg__28: vcu118_rocket_top__GC0,
-logic__8710: APBGpsBlock__GC0,
-logic__403: vcu118_rocket_top__GC0,
-muxpart__25: vcu118_rocket_top__GC0,
-logic__4935: FPU__GB2,
-case__851: RocketTile__GCB0,
-logic__4380: FPU__GB1,
-datapath__466: RocketTile__GCB0,
-reg__722: RocketTile__GCB0,
-logic__6996: VCU118RocketSystem__GC0,
-datapath__164: VCU118RocketSystem__GC0,
-datapath__623: APBGpsBlock__GC0,
-logic__8779: APBGpsBlock__GC0,
-logic__3030: RocketTile__GCB0,
-logic__7881: VCU118RocketSystem__GC0,
-reg__952: VCU118RocketSystem__GC0,
-reg__368: DCache,
-logic__7266: VCU118RocketSystem__GC0,
-logic__651: vcu118_rocket_top__GC0,
-case__558: DCache,
-case__1137: VCU118RocketSystem__GC0,
-dsp48e2__15: APBGpsBlock__GC0,
-logic__6819: VCU118RocketSystem__GC0,
-reg__832: RocketTile__GCB0,
-logic__3288: RocketTile__GCB0,
-logic__2355: DCache,
-case__678: FPU__GB2,
-case__1223: VCU118RocketSystem__GC0,
-reg__1008: VCU118RocketSystem__GC0,
-datapath__277: DCache,
-case__150: vcu118_rocket_top__GC0,
-muxpart__40: vcu118_rocket_top__GC0,
-datapath__183: VCU118RocketSystem__GC0,
-logic__3842: FPU__GB2,
-reg__733: RocketTile__GCB0,
-reg__544: FPU__GB1,
-logic__8260: APBGpsBlock__GC0,
-logic__7343: VCU118RocketSystem__GC0,
-logic__8920: tracking_wrapper,
-logic__1595: VCU118RocketSystem__GC0,
-datapath__123: VCU118RocketSystem__GC0,
-logic__5433: RocketTile__GCB0,
-logic__8700: APBGpsBlock__GC0,
-case__1393: APBGpsBlock__GC0,
-reg__810: RocketTile__GCB0,
-logic__1104: VCU118RocketSystem__GC0,
-case__1046: VCU118RocketSystem__GC0,
-muxpart__68: vcu118_rocket_top__GC0,
-logic__7293: VCU118RocketSystem__GC0,
-case__262: VCU118RocketSystem__GC0,
-counter__1: vcu118_rocket_top__GC0,
-logic__4075: FPU__GB2,
-logic__2110: RocketTile__GCB0,
-case__1646: tracking_wrapper,
-dsp48e2__4: APBGpsBlock__GC0,
-keep: vcu118_rocket_top__GC0,
-case__932: RocketTile__GCB0,
-logic__1704: VCU118RocketSystem__GC0,
-case__1135: VCU118RocketSystem__GC0,
-reg__1012: VCU118RocketSystem__GC0,
-logic__2062: RocketTile__GCB0,
-logic__4899: FPU__GB2,
-reg__570: FPU__GB1,
-case__640: FPU__GB0,
-logic__7765: VCU118RocketSystem__GC0,
-logic__7411: VCU118RocketSystem__GC0,
-case__1125: VCU118RocketSystem__GC0,
-logic__3519: FPU__GB1,
-reg__698: RocketTile__GCB0,
-logic__7740: VCU118RocketSystem__GC0,
-logic__7527: VCU118RocketSystem__GC0,
-reg__1200: APBGpsBlock__GC0,
-logic__6790: VCU118RocketSystem__GC0,
-datapath__530: VCU118RocketSystem__GC0,
-logic__443: vcu118_rocket_top__GC0,
-case__763: FPU__GB2,
-datapath__542: VCU118RocketSystem__GC0,
-case__429: VCU118RocketSystem__GC0,
-reg__837: RocketTile__GCB0,
-ram: VCU118RocketSystem__GC0,
-logic__1792: VCU118RocketSystem__GC0,
-logic__1411: VCU118RocketSystem__GC0,
-reg__618: FPU__GB1,
-case__248: VCU118RocketSystem__GC0,
-cordic_angle_lut: tracking_wrapper,
-logic__7506: VCU118RocketSystem__GC0,
-logic__1979: VCU118RocketSystem__GC0,
-logic__1250: VCU118RocketSystem__GC0,
-logic__5851: RocketTile__GCB0,
-logic__4587: FPU__GB2, FPU__GB1,
-logic__3871: FPU__GB2,
-logic__616: vcu118_rocket_top__GC0,
-case__1054: VCU118RocketSystem__GC0,
-logic__3452: FPU__GB1,
-logic__7227: VCU118RocketSystem__GC0,
-datapath__263: VCU118RocketSystem__GC0,
-logic__2997: RocketTile__GCB0,
-case__967: RocketTile__GCB0,
-logic__458: vcu118_rocket_top__GC0,
-logic__1268: VCU118RocketSystem__GC0,
-logic__7224: VCU118RocketSystem__GC0,
-logic__3296: FPU__GB1,
-logic__1101: VCU118RocketSystem__GC0,
-reg__852: VCU118RocketSystem__GC0,
-reg__305: VCU118RocketSystem__GC0,
-logic__5187: RocketTile__GCB0,
-datapath__532: VCU118RocketSystem__GC0,
-logic__7399: VCU118RocketSystem__GC0,
-case__1687: TLToAPB,
-logic__7138: VCU118RocketSystem__GC0,
-logic__7009: VCU118RocketSystem__GC0,
-logic__6366: RocketTile__GCB0,
-reg__1193: APBGpsBlock__GC0,
-case__942: RocketTile__GCB0,
-datapath__705: tracking_wrapper,
-reg__121: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__425: RocketTile__GCB0,
-logic__6029: RocketTile__GCB0,
-datapath__246: VCU118RocketSystem__GC0,
-logic__4353: FPU__GB1,
-reg__402: RocketTile__GCB0,
-reg__1359: tracking_wrapper,
-datapath__550: VCU118RocketSystem__GC0,
-logic__7752: VCU118RocketSystem__GC0,
-case__554: DCache,
-logic__9430: APBGpsBlock__GC0,
-logic__5434: RocketTile__GCB0,
-muxpart__24: vcu118_rocket_top__GC0,
-logic__4488: FPU__GB1,
-logic__6731: TilePRCIDomain__GC0,
-logic__2926: DCache,
-muxpart__43: vcu118_rocket_top__GC0,
-muxpart__38: vcu118_rocket_top__GC0,
-case__431: VCU118RocketSystem__GC0,
-logic__6155: RocketTile__GCB0,
-TLInterconnectCoupler_cbus_to_rockettile: VCU118RocketSystem__GC0,
-datapath__501: VCU118RocketSystem__GC0,
-case__1502: APBGpsBlock__GC0,
-logic: vcu118_rocket_top__GC0,
-logic__2049: VCU118RocketSystem__GC0,
-logic__8610: APBGpsBlock__GC0,
-reg__457: FPU__GB0,
-logic__7272: VCU118RocketSystem__GC0,
-logic__5547: RocketTile__GCB0,
-logic__4770: FPU__GB2,
-logic__7569: VCU118RocketSystem__GC0,
-case__249: VCU118RocketSystem__GC0,
-reg__828: RocketTile__GCB0,
-logic__6123: RocketTile__GCB0,
-case__529: DCache,
-logic__2168: DCache,
-logic__5020: FPU__GB1,
-case__245: VCU118RocketSystem__GC0,
-case__1534: tracking_wrapper,
-logic__5479: RocketTile__GCB0,
-datapath__173: VCU118RocketSystem__GC0,
-case__1516: APBGpsBlock__GC0,
-Queue1_RegMapperInput_i9_m8: VCU118RocketSystem__GC0,
-reg__735: RocketTile__GCB0,
-logic__7907: VCU118RocketSystem__GC0,
-case__1295: APBGpsBlock__GC0,
-logic__5173: FPU__GB1,
-logic__9424: APBGpsBlock__GC0,
-reg__196: VCU118RocketSystem__GC0,
-logic__8018: VCU118RocketSystem__GC0,
-logic__9340: tracking_wrapper,
-logic__659: vcu118_rocket_top__GC0,
-reg__40: vcu118_rocket_top__GC0,
-case__458: VCU118RocketSystem__GC0,
-datapath__290: DCache,
-logic__5846: RocketTile__GCB0,
-case__25: vcu118_rocket_top__GC0,
-logic__1619: VCU118RocketSystem__GC0,
-reg__210: VCU118RocketSystem__GC0,
-logic__6052: RocketTile__GCB0,
-case__1065: VCU118RocketSystem__GC0,
-logic__5577: RocketTile__GCB0,
-logic__8222: VCU118RocketSystem__GC0,
-logic__6997: VCU118RocketSystem__GC0,
-logic__6920: VCU118RocketSystem__GC0,
-muxpart__37: vcu118_rocket_top__GC0,
-logic__144: vcu118_rocket_top__GC0,
-logic__1334: VCU118RocketSystem__GC0,
-logic__4531: FPU__GB1,
-logic__3477: FPU__GB1,
-case__510: DCache,
-logic__5989: RocketTile__GCB0,
-reg__380: RocketTile__GCB0,
-logic__8792: tracking_wrapper,
-logic__3217: RocketTile__GCB0,
-logic__2099: RocketTile__GCB0,
-logic__316: vcu118_rocket_top__GC0,
-logic__3770: FPU__GB2,
-datapath__506: VCU118RocketSystem__GC0,
-logic__2606: DCache,
-case__700: FPU__GB2,
-logic__1852: VCU118RocketSystem__GC0,
-case__586: RocketTile__GCB0,
-case__1599: tracking_wrapper,
-muxpart__223: FPU__GB0,
-counter__11: VCU118RocketSystem__GC0,
-case__1164: VCU118RocketSystem__GC0,
-logic__7364: VCU118RocketSystem__GC0,
-case__318: VCU118RocketSystem__GC0,
-case__1176: VCU118RocketSystem__GC0,
-logic__5793: RocketTile__GCB0,
-logic__8042: VCU118RocketSystem__GC0,
-logic__9456: TLToAPB,
-logic__5576: RocketTile__GCB0,
-reg__553: FPU__GB1,
-logic__7636: VCU118RocketSystem__GC0,
-datapath__536: VCU118RocketSystem__GC0,
-logic__1935: VCU118RocketSystem__GC0,
-logic__1006: VCU118RocketSystem__GC0,
-logic__886: VCU118RocketSystem__GC0,
-logic__6302: RocketTile__GCB0,
-logic__969: VCU118RocketSystem__GC0,
-logic__5427: RocketTile__GCB0,
-case__828: RocketTile__GCB0,
-reg__1360: tracking_wrapper,
-logic__2682: DCache,
-reg__1286: tracking_wrapper,
-logic__2866: DCache,
-case__21: vcu118_rocket_top__GC0,
-logic__5257: RocketTile__GCB0,
-logic__9207: tracking_wrapper,
-reg__779: RocketTile__GCB0,
-acq_top: APBGpsBlock__GC0,
-case__687: FPU__GB2,
-reg__250: VCU118RocketSystem__GC0,
-case__373: VCU118RocketSystem__GC0,
-reg__790: RocketTile__GCB0,
-logic__4771: FPU__GB2,
-case__54: vcu118_rocket_top__GC0,
-logic__7194: VCU118RocketSystem__GC0,
-gray_to_binary: tracking_wrapper,
-case__773: FPU__GB1,
-case__993: VCU118RocketSystem__GC0,
-case__1690: TLToAPB,
-reg__836: RocketTile__GCB0,
-case__134: vcu118_rocket_top__GC0,
-case__292: VCU118RocketSystem__GC0,
-case__1511: APBGpsBlock__GC0,
-case__988: VCU118RocketSystem__GC0,
-datapath__233: VCU118RocketSystem__GC0,
-case__1331: APBGpsBlock__GC0,
-datapath__412: FPU__GB2,
-logic__8145: VCU118RocketSystem__GC0,
-logic__7998: VCU118RocketSystem__GC0,
-datapath__592: APBGpsBlock__GC0,
-case__1335: APBGpsBlock__GC0,
-reg__1297: tracking_wrapper,
-case__1575: tracking_wrapper,
-logic__8147: VCU118RocketSystem__GC0,
-logic__2732: DCache,
-logic__4083: FPU__GB2,
-logic__9263: tracking_wrapper,
-logic__6622: RocketTile__GCB0,
-TLBuffer_a32d64s2k1z3u: RocketTile__GCB0,
-logic__3214: RocketTile__GCB0,
-case__158: vcu118_rocket_top__GC0,
-logic__3498: FPU__GB1,
-case__76: vcu118_rocket_top__GC0,
-logic__5030: FPU__GB1,
-reg__441: RocketTile__GCB0,
-logic__7337: VCU118RocketSystem__GC0,
-logic__4662: FPU__GB2, FPU__GB1,
-case__169: vcu118_rocket_top__GC0,
-reg__148: VCU118RocketSystem__GC0,
-case__1256: APBGpsBlock__GC0,
-logic__2846: DCache,
-reg__724: RocketTile__GCB0,
-logic__7550: VCU118RocketSystem__GC0,
-logic__1292: VCU118RocketSystem__GC0,
-logic__2223: DCache,
-logic__996: VCU118RocketSystem__GC0,
-case__830: RocketTile__GCB0,
-logic__9262: tracking_wrapper,
-logic__5437: RocketTile__GCB0,
-logic__9335: tracking_wrapper,
-logic__893: VCU118RocketSystem__GC0,
-case__330: VCU118RocketSystem__GC0,
-logic__9295: tracking_wrapper,
-logic__1422: VCU118RocketSystem__GC0,
-AMOALU: DCache,
-datapath__50: VCU118RocketSystem__GC0,
-logic__8497: APBGpsBlock__GC0,
-Repeater_TLBundleA_a32d64s2k1z3u: RocketTile__GCB0,
-reg__1144: APBGpsBlock__GC0,
-muxpart__73: vcu118_rocket_top__GC0,
-logic__8044: VCU118RocketSystem__GC0,
-datapath__403: FPU__GB2,
-logic__6825: VCU118RocketSystem__GC0,
-logic__5947: RocketTile__GCB0,
-logic__1854: VCU118RocketSystem__GC0,
-reg__1023: VCU118RocketSystem__GC0,
-datapath__276: DCache,
-logic__6053: RocketTile__GCB0,
-logic__6953: VCU118RocketSystem__GC0,
-case__589: RocketTile__GCB0,
-reg__669: RocketTile__GCB0,
-logic__8862: tracking_wrapper,
-case__853: RocketTile__GCB0,
-logic__328: vcu118_rocket_top__GC0,
-logic__283: vcu118_rocket_top__GC0,
-logic__7292: VCU118RocketSystem__GC0,
-datapath__677: tracking_wrapper,
-datapath__111: VCU118RocketSystem__GC0,
-case__1591: tracking_wrapper,
-reg__825: RocketTile__GCB0,
-reg__221: VCU118RocketSystem__GC0,
-logic__993: VCU118RocketSystem__GC0,
-case__1638: tracking_wrapper,
-muxpart__53: vcu118_rocket_top__GC0,
-logic__7408: VCU118RocketSystem__GC0,
-reg__280: VCU118RocketSystem__GC0,
-dsp48e2__27: APBGpsBlock__GC0,
-reg__64: vcu118_rocket_top__GC0,
-datapath__136: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__1136: VCU118RocketSystem__GC0,
-case__1051: VCU118RocketSystem__GC0,
-logic__7361: VCU118RocketSystem__GC0,
-case__1618: tracking_wrapper,
-case__233: VCU118RocketSystem__GC0,
-logic__7077: VCU118RocketSystem__GC0,
-case__1041: VCU118RocketSystem__GC0,
-logic__1600: VCU118RocketSystem__GC0,
-datapath__407: FPU__GB2,
-logic__2460: DCache,
-logic__5963: RocketTile__GCB0,
-reg__938: VCU118RocketSystem__GC0,
-reg__868: VCU118RocketSystem__GC0,
-logic__1833: VCU118RocketSystem__GC0,
-logic__5438: RocketTile__GCB0,
-logic__3476: FPU__GB1,
-reg__926: VCU118RocketSystem__GC0,
-reg__1209: tracking_wrapper,
-logic__8979: tracking_wrapper,
-logic__2336: DCache,
-case__1096: VCU118RocketSystem__GC0,
-reg__65: vcu118_rocket_top__GC0,
-reg__182: VCU118RocketSystem__GC0,
-trck_top: tracking_wrapper,
-muxpart__20: vcu118_rocket_top__GC0,
-logic__1954: VCU118RocketSystem__GC0,
-logic__4067: FPU__GB2,
-case__1593: tracking_wrapper,
-datapath__186: VCU118RocketSystem__GC0,
-reg__695: RocketTile__GCB0,
-ram__8: TilePRCIDomain__GC0,
-logic__9232: tracking_wrapper,
-TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u: RocketTile__GCB0,
-logic__2742: DCache,
-case__1537: tracking_wrapper,
-logic__7857: VCU118RocketSystem__GC0,
-reg__877: VCU118RocketSystem__GC0,
-reg__118: VCU118RocketSystem__GC0,
-logic__1456: VCU118RocketSystem__GC0,
-logic__6660: RocketTile__GCB0,
-reg__763: RocketTile__GCB0,
-logic__7508: VCU118RocketSystem__GC0,
-logic__7159: VCU118RocketSystem__GC0,
-case__411: VCU118RocketSystem__GC0,
-logic__5245: RocketTile__GCB0,
-logic__6749: VCU118RocketSystem__GC0,
-case__460: VCU118RocketSystem__GC0,
-datapath__151: VCU118RocketSystem__GC0,
-logic__6554: RocketTile__GCB0,
-case__316: VCU118RocketSystem__GC0,
-dsp48e2__41: tracking_wrapper,
-logic__5980: RocketTile__GCB0,
-logic__5384: RocketTile__GCB0,
-reg__1046: VCU118RocketSystem__GC0,
-logic__6670: RocketTile__GCB0,
-logic__3993: FPU__GB2,
-case__674: FPU__GB2,
-reg__551: FPU__GB1,
-case__783: FPU__GB1,
-logic__1620: VCU118RocketSystem__GC0,
-logic__908: VCU118RocketSystem__GC0,
-datapath__54: VCU118RocketSystem__GC0,
-logic__6160: RocketTile__GCB0,
-case__1178: VCU118RocketSystem__GC0,
-logic__5924: RocketTile__GCB0,
-reg__167: VCU118RocketSystem__GC0,
-logic__6726: RocketTile__GCB0,
-reg__827: RocketTile__GCB0,
-logic__6127: RocketTile__GCB0,
-logic__18: vcu118_rocket_top__GC0,
-case__1220: VCU118RocketSystem__GC0,
-logic__6667: RocketTile__GCB0,
-bit_gen: tracking_wrapper,
-reg__940: VCU118RocketSystem__GC0,
-logic__989: VCU118RocketSystem__GC0,
-case__171: vcu118_rocket_top__GC0,
-logic__970: VCU118RocketSystem__GC0,
-reg__1317: tracking_wrapper,
-case__572: RocketTile__GCB0,
-logic__3970: FPU__GB2,
-rf_31x64: RocketTile__GCB0,
-case__552: DCache,
-datapath__232: VCU118RocketSystem__GC0,
-case__1216: VCU118RocketSystem__GC0,
-reg__670: RocketTile__GCB0,
-muxpart__206: FPU__GB0,
-reg__513: FPU__GB2,
-logic__2424: DCache,
-datapath__424: RocketTile__GCB0,
-reg__506: FPU__GB1,
-FPUFMAPipe_l3_f32: FPU__GB1,
-counter__21: APBGpsBlock__GC0,
-reg__1204: APBGpsBlock__GC0,
-reg__438: RocketTile__GCB0,
-logic__7135: VCU118RocketSystem__GC0,
-case__524: DCache,
-logic__1372: VCU118RocketSystem__GC0,
-reg__1003: VCU118RocketSystem__GC0,
-logic__3428: FPU__GB1,
-reg__324: DCache,
-datapath__28: vcu118_rocket_top__GC0,
-reg__880: VCU118RocketSystem__GC0,
-logic__2035: VCU118RocketSystem__GC0,
-datapath__62: VCU118RocketSystem__GC0,
-case__642: FPU__GB1,
-datapath__631: APBGpsBlock__GC0,
-case__1048: VCU118RocketSystem__GC0,
-logic__6194: RocketTile__GCB0,
-logic__899: VCU118RocketSystem__GC0,
-reg__1154: APBGpsBlock__GC0,
-logic__5085: FPU__GB1,
-case__51: vcu118_rocket_top__GC0,
-reg__1117: APBGpsBlock__GC0,
-logic__3681: FPU__GB1,
-logic__5860: RocketTile__GCB0,
-datapath__285: DCache,
-datapath__297: RocketTile__GCB0,
-logic__6850: VCU118RocketSystem__GC0,
-logic__4945: FPU__GB2,
-case__319: VCU118RocketSystem__GC0,
-logic__4193: FPU__GB1,
-reg__738: RocketTile__GCB0,
-logic__2753: DCache,
-datapath__452: RocketTile__GCB0,
-reg__527: FPU__GB2,
-logic__6300: RocketTile__GCB0,
-logic__1681: VCU118RocketSystem__GC0,
-reg__1382: tracking_wrapper,
-case__842: RocketTile__GCB0,
-case__1203: VCU118RocketSystem__GC0,
-logic__5259: RocketTile__GCB0,
-reg__646: FPU__GB1,
-logic__7178: VCU118RocketSystem__GC0,
-logic__7618: VCU118RocketSystem__GC0,
-logic__5819: RocketTile__GCB0,
-muxpart__237: FPU__GB0,
-logic__9275: tracking_wrapper,
-case__1668: tracking_wrapper,
-logic__1114: VCU118RocketSystem__GC0,
-IntXbar_i3_o1: RocketTile__GCB0,
-logic__2141: RocketTile__GCB0,
-logic__7207: VCU118RocketSystem__GC0,
-logic__6797: VCU118RocketSystem__GC0,
-logic__918: VCU118RocketSystem__GC0,
-logic__4192: FPU__GB1,
-case__986: VCU118RocketSystem__GC0,
-case__555: DCache,
-logic__5225: RocketTile__GCB0,
-datapath__708: tracking_wrapper,
-logic__7417: VCU118RocketSystem__GC0,
-logic__4362: FPU__GB1,
-logic__5254: RocketTile__GCB0,
-case__1620: tracking_wrapper,
-logic__732: vcu118_rocket_top__GC0,
-logic__6856: VCU118RocketSystem__GC0,
-muxpart__173: VCU118RocketSystem__GC0,
-reg__811: RocketTile__GCB0,
-logic__3196: RocketTile__GCB0,
-case__505: DCache,
-case__1432: APBGpsBlock__GC0,
-case__1172: VCU118RocketSystem__GC0,
-reg__976: VCU118RocketSystem__GC0,
-datapath__526: VCU118RocketSystem__GC0,
-reg__175: VCU118RocketSystem__GC0,
-datapath__37: VCU118RocketSystem__GC0,
-logic__4924: FPU__GB2,
-case__704: FPU__GB1,
-case__1477: APBGpsBlock__GC0,
-logic__6143: RocketTile__GCB0,
-logic__803: VCU118RocketSystem__GC0,
-reg__1108: APBGpsBlock__GC0,
-logic__7017: VCU118RocketSystem__GC0,
-case__903: RocketTile__GCB0,
-logic__6834: VCU118RocketSystem__GC0,
-case__1337: APBGpsBlock__GC0,
-reg__529: FPU__GB1,
-case__511: DCache,
-logic__4333: FPU__GB1,
-logic__6804: VCU118RocketSystem__GC0,
-datapath__282: DCache,
-logic__7353: VCU118RocketSystem__GC0,
-logic__7269: VCU118RocketSystem__GC0,
-case__1010: VCU118RocketSystem__GC0,
-reg__311: VCU118RocketSystem__GC0,
-logic__5260: RocketTile__GCB0,
-logic__9289: tracking_wrapper,
-logic__2312: DCache,
-case__421: VCU118RocketSystem__GC0,
-logic__982: VCU118RocketSystem__GC0,
-reg__2: vcu118_rocket_top__GC0,
-reg__1135: APBGpsBlock__GC0,
-reg__142: VCU118RocketSystem__GC0,
-logic__4245: FPU__GB1,
-logic__8739: APBGpsBlock__GC0,
-case__984: VCU118RocketSystem__GC0,
-logic__3028: RocketTile__GCB0,
-logic__6821: VCU118RocketSystem__GC0,
-case__467: VCU118RocketSystem__GC0,
-logic__1166: VCU118RocketSystem__GC0,
-logic__3300: FPU__GB1,
-logic__6927: VCU118RocketSystem__GC0,
-logic__2524: RocketTile__GCB0, DCache,
-logic__2463: DCache,
-datapath__271: DCache,
-datapath__90: VCU118RocketSystem__GC0,
-logic__8794: tracking_wrapper,
-datapath__356: FPU__GB2,
-datapath__181: VCU118RocketSystem__GC0,
-reg__706: RocketTile__GCB0,
-logic__4358: FPU__GB1,
-case__1261: APBGpsBlock__GC0,
-logic__1819: VCU118RocketSystem__GC0,
-reg__170: VCU118RocketSystem__GC0,
-logic__8795: tracking_wrapper,
-logic__7421: VCU118RocketSystem__GC0,
-case__971: RocketTile__GCB0,
-case__1369: APBGpsBlock__GC0,
-logic__7795: VCU118RocketSystem__GC0,
-logic__2715: DCache,
-datapath__321: FPU__GB1,
-case__349: VCU118RocketSystem__GC0,
-logic__3026: RocketTile__GCB0,
-logic__6060: RocketTile__GCB0,
-datapath__602: APBGpsBlock__GC0,
-muxpart__218: FPU__GB0,
-case__541: DCache,
-datapath__105: VCU118RocketSystem__GC0,
-logic__8749: APBGpsBlock__GC0,
-case__261: VCU118RocketSystem__GC0,
-logic__2091: RocketTile__GCB0,
-case__1243: VCU118RocketSystem__GC0,
-reg__907: VCU118RocketSystem__GC0,
-logic__6765: VCU118RocketSystem__GC0,
-logic__2104: RocketTile__GCB0,
-logic__2663: DCache,
-logic__251: vcu118_rocket_top__GC0,
-case__1039: VCU118RocketSystem__GC0,
-logic__1904: VCU118RocketSystem__GC0,
-logic__3249: RocketTile__GCB0,
-logic__3326: FPU__GB1,
-logic__3215: RocketTile__GCB0,
-case__1592: tracking_wrapper,
-logic__3856: FPU__GB2,
-logic__3503: FPU__GB1,
-logic__5845: RocketTile__GCB0,
-logic__4369: FPU__GB1,
-reg__1190: APBGpsBlock__GC0,
-case__345: VCU118RocketSystem__GC0,
-logic__1195: VCU118RocketSystem__GC0,
-datapath__252: VCU118RocketSystem__GC0,
-logic__5584: RocketTile__GCB0,
-logic__7430: VCU118RocketSystem__GC0,
-logic__1670: VCU118RocketSystem__GC0,
-datapath__377: FPU__GB1,
-datapath__249: VCU118RocketSystem__GC0,
-reg__105: vcu118_rocket_top__GC0,
-RVCExpander: RocketTile__GCB0,
-Rocket: RocketTile__GCB0,
-case__902: RocketTile__GCB0,
-logic__990: VCU118RocketSystem__GC0,
-case__1669: tracking_wrapper,
-reg__675: RocketTile__GCB0,
-reg__613: FPU__GB1,
-logic__8226: VCU118RocketSystem__GC0,
-logic__38: vcu118_rocket_top__GC0,
-case__329: VCU118RocketSystem__GC0,
-logic__2881: DCache,
-logic__7151: VCU118RocketSystem__GC0,
-NonSyncResetSynchronizerPrimitiveShiftReg_d3: TilePRCIDomain__GC0,
-muxpart__84: vcu118_rocket_top__GC0,
-logic__7223: VCU118RocketSystem__GC0,
-reg__413: RocketTile__GCB0,
-logic__5531: RocketTile__GCB0,
-logic__5745: RocketTile__GCB0,
-logic__8494: APBGpsBlock__GC0,
-reg__854: VCU118RocketSystem__GC0,
-logic__1873: VCU118RocketSystem__GC0,
-reg__672: RocketTile__GCB0,
-logic__3256: RocketTile__GCB0,
-case__1561: tracking_wrapper,
-datapath__613: APBGpsBlock__GC0,
-logic__7264: VCU118RocketSystem__GC0,
-case__869: RocketTile__GCB0,
-reg__680: RocketTile__GCB0,
-logic__5095: FPU__GB1,
-logic__7833: VCU118RocketSystem__GC0,
-logic__2015: VCU118RocketSystem__GC0,
-logic__2337: DCache,
-logic__6890: VCU118RocketSystem__GC0,
-logic__7526: VCU118RocketSystem__GC0,
-logic__2540: RocketTile__GCB0, DCache,
-case__1059: VCU118RocketSystem__GC0,
-reg__187: VCU118RocketSystem__GC0,
-muxpart__7: vcu118_rocket_top__GC0,
-logic__1536: VCU118RocketSystem__GC0,
-divider: tracking_wrapper,
-datapath__94: VCU118RocketSystem__GC0,
-datapath__279: DCache,
-logic__4214: FPU__GB1,
-logic__7157: VCU118RocketSystem__GC0,
-logic__8034: VCU118RocketSystem__GC0,
-reg__162: VCU118RocketSystem__GC0,
-logic__2674: DCache,
-logic__2750: DCache,
-reg__1025: VCU118RocketSystem__GC0,
-case__1221: VCU118RocketSystem__GC0,
-logic__6761: VCU118RocketSystem__GC0,
-logic__5737: RocketTile__GCB0,
-logic__4751: FPU__GB2,
-case__409: VCU118RocketSystem__GC0,
-logic__3317: FPU__GB1,
-case__816: RocketTile__GCB0,
-logic__9249: tracking_wrapper,
-case__1100: VCU118RocketSystem__GC0,
-logic__5537: RocketTile__GCB0,
-reg__490: FPU__GB1,
-AsyncQueueSource_DebugInternalBundle: VCU118RocketSystem__GC0,
-ShiftQueue: RocketTile__GCB0,
-logic__4386: FPU__GB1,
-case__72: vcu118_rocket_top__GC0,
-datapath__88: VCU118RocketSystem__GC0,
-logic__7001: VCU118RocketSystem__GC0,
-case__1329: APBGpsBlock__GC0,
-reg__944: VCU118RocketSystem__GC0,
-reg__257: VCU118RocketSystem__GC0,
-datapath__482: RocketTile__GCB0,
-logic__5991: RocketTile__GCB0,
-datapath__507: VCU118RocketSystem__GC0,
-logic__6666: RocketTile__GCB0,
-case__454: VCU118RocketSystem__GC0,
-reg__804: RocketTile__GCB0,
-logic__9370: tracking_wrapper,
-logic__7041: VCU118RocketSystem__GC0,
-reg__116: VCU118RocketSystem__GC0,
-logic__2469: DCache,
-logic__3493: FPU__GB1,
-logic__5311: RocketTile__GCB0,
-logic__5328: RocketTile__GCB0,
-reg__1367: tracking_wrapper,
-case__1423: APBGpsBlock__GC0,
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1: VCU118RocketSystem__GC0,
-reg__315: RocketTile__GCB0,
-logic__5907: RocketTile__GCB0,
-datapath__404: FPU__GB2,
-logic__3484: FPU__GB1,
-case__1285: APBGpsBlock__GC0,
-case__1210: VCU118RocketSystem__GC0,
-logic__6028: RocketTile__GCB0,
-reg__1371: tracking_wrapper,
-logic__4752: FPU__GB2,
-logic__6800: VCU118RocketSystem__GC0,
-logic__8059: VCU118RocketSystem__GC0,
-logic__7746: VCU118RocketSystem__GC0,
-logic__7331: VCU118RocketSystem__GC0,
-logic__8427: APBGpsBlock__GC0,
-reg__190: VCU118RocketSystem__GC0,
-logic__1535: VCU118RocketSystem__GC0,
-datapath__431: RocketTile__GCB0,
-logic__6130: RocketTile__GCB0,
-reg__153: VCU118RocketSystem__GC0,
-case__1665: tracking_wrapper,
-muxpart__272: RocketTile__GCB0,
-reg__26: vcu118_rocket_top__GC0,
-logic__5981: RocketTile__GCB0,
-reg__969: VCU118RocketSystem__GC0,
-logic__9419: APBGpsBlock__GC0,
-logic__7426: VCU118RocketSystem__GC0,
-case__970: RocketTile__GCB0,
-case__1670: tracking_wrapper,
-case__466: VCU118RocketSystem__GC0,
-case__1324: APBGpsBlock__GC0,
-reg__1116: APBGpsBlock__GC0,
-reg__193: VCU118RocketSystem__GC0,
-case__938: RocketTile__GCB0,
-case__750: FPU__GB2,
-datapath__373: FPU__GB1,
-reg__890: VCU118RocketSystem__GC0,
-nav_solve_timer: tracking_wrapper,
-TLXbar_pbus_out_i1_o3_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__2737: DCache,
-logic__6102: RocketTile__GCB0,
-logic__7698: VCU118RocketSystem__GC0,
-logic__9045: tracking_wrapper,
-logic__839: VCU118RocketSystem__GC0,
-logic__4946: FPU__GB2,
-logic__3462: FPU__GB1,
-logic__4517: FPU__GB1,
-logic__5216: RocketTile__GCB0,
-logic__623: vcu118_rocket_top__GC0,
-logic__3967: FPU__GB2,
-logic__7181: VCU118RocketSystem__GC0,
-logic__1985: VCU118RocketSystem__GC0,
-logic__3742: FPU__GB2,
-muxpart__209: FPU__GB0,
-reg__89: vcu118_rocket_top__GC0,
-ClockGroupAggregator_cbus: VCU118RocketSystem__GC0,
-reg__425: RocketTile__GCB0,
-TLWidthWidget8_3: VCU118RocketSystem__GC0,
-logic__4913: FPU__GB2,
-TLFragmenter_CLINT: VCU118RocketSystem__GC0,
-datapath__369: FPU__GB1,
-reg__483: FPU__GB1,
-logic__7251: VCU118RocketSystem__GC0,
-datapath__486: RocketTile__GCB0,
-datapath__73: VCU118RocketSystem__GC0,
-logic__5250: RocketTile__GCB0,
-case__607: RocketTile__GCB0,
-reg__224: VCU118RocketSystem__GC0,
-case__304: VCU118RocketSystem__GC0,
-datapath__596: APBGpsBlock__GC0,
-logic__6782: VCU118RocketSystem__GC0,
-logic__2587: DCache,
-logic__892: VCU118RocketSystem__GC0,
-Queue1_TLBundleD_a29d32s7k1z2u: TLToAPB,
-logic__7158: VCU118RocketSystem__GC0,
-case__920: RocketTile__GCB0,
-logic__7200: VCU118RocketSystem__GC0,
-case__672: FPU__GB2,
-logic__4619: FPU__GB2, FPU__GB1,
-logic__310: vcu118_rocket_top__GC0,
-logic__7290: VCU118RocketSystem__GC0,
-case__880: RocketTile__GCB0,
-datapath__261: VCU118RocketSystem__GC0,
-case__164: vcu118_rocket_top__GC0,
-case__1659: tracking_wrapper,
-logic__9288: tracking_wrapper,
-logic__2679: DCache,
-case__849: RocketTile__GCB0,
-logic__6751: VCU118RocketSystem__GC0,
-case__395: VCU118RocketSystem__GC0,
-muxpart__45: vcu118_rocket_top__GC0,
-reg__41: vcu118_rocket_top__GC0,
-reg__1273: tracking_wrapper,
-MulAddRecFNToRaw_postMul: FPU__GB1,
-logic__9438: TLToAPB,
-logic__7217: VCU118RocketSystem__GC0,
-reg__876: VCU118RocketSystem__GC0,
-logic__6131: RocketTile__GCB0,
-reg__398: RocketTile__GCB0,
-datapath__427: RocketTile__GCB0,
-logic__8142: VCU118RocketSystem__GC0,
-logic__250: vcu118_rocket_top__GC0,
-reg__590: FPU__GB2,
-reg__965: VCU118RocketSystem__GC0,
-logic__5753: RocketTile__GCB0,
-case__549: DCache,
-reg__1182: APBGpsBlock__GC0,
-case__538: DCache,
-logic__3530: FPU__GB1,
-datapath__46: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__6993: VCU118RocketSystem__GC0,
-logic__356: vcu118_rocket_top__GC0,
-logic__2711: DCache,
-reg__716: RocketTile__GCB0,
-reg__486: FPU__GB1,
-case__476: VCU118RocketSystem__GC0,
-reg__1073: APBGpsBlock__GC0,
-logic__1135: VCU118RocketSystem__GC0,
-case__1042: VCU118RocketSystem__GC0,
-logic__7054: VCU118RocketSystem__GC0,
-datapath__721: tracking_wrapper,
-logic__3702: FPU__GB2,
-extram__1: DCache,
-datapath__428: RocketTile__GCB0,
-eth_rf_mdio_init: vcu118_rocket_top__GC0,
-logic__5613: RocketTile__GCB0,
-case__1341: APBGpsBlock__GC0,
-logic__4961: FPU__GB2,
-case__38: vcu118_rocket_top__GC0,
-TLROM: VCU118RocketSystem__GC0,
-logic__175: vcu118_rocket_top__GC0,
-datapath__125: VCU118RocketSystem__GC0,
-reg__528: FPU__GB1,
-logic__7270: VCU118RocketSystem__GC0,
-logic__7021: VCU118RocketSystem__GC0,
-logic__890: VCU118RocketSystem__GC0,
-case__578: RocketTile__GCB0,
-logic__7406: VCU118RocketSystem__GC0,
-logic__6809: VCU118RocketSystem__GC0,
-logic__6759: VCU118RocketSystem__GC0,
-logic__2294: DCache,
-logic__9365: tracking_wrapper,
-logic__1159: VCU118RocketSystem__GC0,
-logic__2604: DCache,
-logic__2397: DCache,
-case__742: FPU__GB2,
-muxpart__244: FPU__GB0,
-case__317: VCU118RocketSystem__GC0,
-Repeater_TLBundleA_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__2509: RocketTile__GCB0, DCache,
-logic__5122: FPU__GB1,
-logic__7177: VCU118RocketSystem__GC0,
-reg__127: VCU118RocketSystem__GC0,
-case__553: DCache,
-logic__1920: VCU118RocketSystem__GC0,
-logic__4518: FPU__GB1,
-logic__3164: RocketTile__GCB0,
-logic__6683: RocketTile__GCB0,
-logic__2208: DCache,
-reg__332: DCache,
-logic__8926: tracking_wrapper,
-datapath__235: VCU118RocketSystem__GC0,
-case__60: vcu118_rocket_top__GC0,
-datapath__548: VCU118RocketSystem__GC0,
-logic__116: vcu118_rocket_top__GC0,
-reg__962: VCU118RocketSystem__GC0,
-reg__850: TilePRCIDomain__GC0,
-logic__420: vcu118_rocket_top__GC0,
-logic__2960: RocketTile__GCB0,
-reg__505: FPU__GB1,
-datapath__458: RocketTile__GCB0,
-logic__4617: FPU__GB2, FPU__GB1,
-datapath__85: VCU118RocketSystem__GC0,
-datapath__284: DCache,
-logic__1697: VCU118RocketSystem__GC0,
-logic__6167: RocketTile__GCB0,
-logic__636: vcu118_rocket_top__GC0,
-case__669: FPU__GB2,
-logic__4355: FPU__GB1,
-logic__8880: tracking_wrapper,
-reg__541: FPU__GB1,
-reg__279: VCU118RocketSystem__GC0,
-datapath__3: vcu118_rocket_top__GC0,
-case__407: VCU118RocketSystem__GC0,
-logic__3628: FPU__GB2, FPU__GB1,
-case__1601: tracking_wrapper,
-logic__6946: VCU118RocketSystem__GC0,
-datapath__218: VCU118RocketSystem__GC0,
-logic__1555: VCU118RocketSystem__GC0,
-logic__1423: VCU118RocketSystem__GC0,
-logic__6311: RocketTile__GCB0,
-logic__8820: tracking_wrapper,
-logic__6928: VCU118RocketSystem__GC0,
-reg__745: RocketTile__GCB0,
-case__1495: APBGpsBlock__GC0,
-logic__5445: RocketTile__GCB0,
-reg__1265: tracking_wrapper,
-ScratchpadSlavePort: RocketTile__GCB0,
-case__691: FPU__GB2,
-logic__4635: FPU__GB2, FPU__GB1,
-logic__1100: VCU118RocketSystem__GC0,
-case__1508: APBGpsBlock__GC0,
-reg__1387: tracking_wrapper,
-reg__1383: tracking_wrapper,
-logic__654: vcu118_rocket_top__GC0,
-logic__921: VCU118RocketSystem__GC0,
-logic__676: vcu118_rocket_top__GC0,
-logic__6758: VCU118RocketSystem__GC0,
-reg__820: RocketTile__GCB0,
-cdc_fifo_gray_dst: tracking_wrapper,
-case__531: DCache,
-datapath__236: VCU118RocketSystem__GC0,
-reg__526: FPU__GB2,
-datapath__396: FPU__GB2,
-case__641: FPU__GB0,
-muxpart__216: FPU__GB0,
-reg__150: VCU118RocketSystem__GC0,
-reg__1000: VCU118RocketSystem__GC0,
-logic__1534: VCU118RocketSystem__GC0,
-logic__5315: RocketTile__GCB0,
-datapath__384: FPU__GB1,
-logic__5587: RocketTile__GCB0,
-logic__7875: VCU118RocketSystem__GC0,
-rom: VCU118RocketSystem__GC0,
-logic__5918: RocketTile__GCB0,
-case__313: VCU118RocketSystem__GC0,
-logic__4180: FPU__GB1,
-case__537: DCache,
-logic__9192: tracking_wrapper,
-case__1158: VCU118RocketSystem__GC0,
-muxpart__353: APBGpsBlock__GC0,
-logic__7643: VCU118RocketSystem__GC0,
-logic__5159: FPU__GB1,
-logic__1452: VCU118RocketSystem__GC0,
-case__1365: APBGpsBlock__GC0,
-logic__9395: APBGpsBlock__GC0,
-case__1043: VCU118RocketSystem__GC0,
-logic__3186: RocketTile__GCB0,
-counter__31: tracking_wrapper,
-logic__3873: FPU__GB2,
-case__1499: APBGpsBlock__GC0,
-case__1481: APBGpsBlock__GC0,
-logic__7161: VCU118RocketSystem__GC0,
-reg__227: VCU118RocketSystem__GC0,
-logic__455: vcu118_rocket_top__GC0,
-datapath__242: VCU118RocketSystem__GC0,
-reg__791: RocketTile__GCB0,
-logic__6551: RocketTile__GCB0,
-logic__4092: FPU__GB2,
-datapath__540: VCU118RocketSystem__GC0,
-logic__1652: VCU118RocketSystem__GC0,
-logic__4359: FPU__GB1,
-logic__6658: RocketTile__GCB0,
-datapath__538: VCU118RocketSystem__GC0,
-reg__922: VCU118RocketSystem__GC0,
-logic__3315: FPU__GB1,
-case__246: VCU118RocketSystem__GC0,
-datapath__413: FPU__GB1,
-logic__2520: RocketTile__GCB0, DCache,
-reg__688: RocketTile__GCB0,
-logic__4408: FPU__GB1,
-logic__2813: DCache,
-case__498: RocketTile__GCB0,
-logic__7257: VCU118RocketSystem__GC0,
-logic__6799: VCU118RocketSystem__GC0,
-logic__3532: FPU__GB1,
-reg__1271: tracking_wrapper,
-logic__3072: RocketTile__GCB0,
-reg__554: FPU__GB1,
-logic__797: VCU118RocketSystem__GC0,
-reg__1079: APBGpsBlock__GC0,
-logic__6721: RocketTile__GCB0,
-logic__2670: DCache,
-reg__33: vcu118_rocket_top__GC0,
-datapath__472: RocketTile__GCB0,
-logic__3488: FPU__GB1,
-logic__9319: tracking_wrapper,
-case__77: vcu118_rocket_top__GC0,
-logic__8214: VCU118RocketSystem__GC0,
-logic__8876: tracking_wrapper,
-datapath__286: DCache,
-datapath__457: RocketTile__GCB0,
-logic__2119: RocketTile__GCB0,
-datapath__121: VCU118RocketSystem__GC0,
-logic__1110: VCU118RocketSystem__GC0,
-BreakpointUnit: RocketTile__GCB0,
-case__1239: VCU118RocketSystem__GC0,
-reg__913: VCU118RocketSystem__GC0,
-logic__8931: tracking_wrapper,
-datapath__449: RocketTile__GCB0,
-logic__4720: FPU__GB2,
-logic__6133: RocketTile__GCB0,
-logic__7415: VCU118RocketSystem__GC0,
-logic__1585: VCU118RocketSystem__GC0,
-case__936: RocketTile__GCB0,
-logic__7000: VCU118RocketSystem__GC0,
-acq_corr: APBGpsBlock__GC0,
-logic__6334: RocketTile__GCB0,
-case__680: FPU__GB2,
-case__1023: VCU118RocketSystem__GC0,
-case__226: VCU118RocketSystem__GC0,
-case__300: VCU118RocketSystem__GC0,
-logic__1057: VCU118RocketSystem__GC0,
-reg__327: DCache,
-logic__3042: RocketTile__GCB0,
-IntSyncCrossingSource_n1x2: VCU118RocketSystem__GC0,
-case__382: VCU118RocketSystem__GC0,
-DCache: DCache,
-logic__769: VCU118RocketSystem__GC0,
-logic__4373: FPU__GB1,
-logic__9233: tracking_wrapper,
-logic__4890: FPU__GB2,
-case__1667: tracking_wrapper,
-logic__5987: RocketTile__GCB0,
-reg__112: VCU118RocketSystem__GC0,
-reg__1029: VCU118RocketSystem__GC0,
-reg__432: RocketTile__GCB0,
-datapath__504: VCU118RocketSystem__GC0,
-muxpart__22: vcu118_rocket_top__GC0,
-reg__1180: APBGpsBlock__GC0,
-case__1363: APBGpsBlock__GC0,
-datapath__57: VCU118RocketSystem__GC0,
-reg__556: FPU__GB1,
-datapath__185: VCU118RocketSystem__GC0,
-logic__4705: FPU__GB2,
-ClockGroupAggregator_pbus: VCU118RocketSystem__GC0,
-logic__5726: RocketTile__GCB0,
-logic__6835: VCU118RocketSystem__GC0,
-reg__1292: tracking_wrapper,
-logic__3261: RocketTile__GCB0,
-logic__3407: FPU__GB1,
-logic__4952: FPU__GB2,
-logic__313: vcu118_rocket_top__GC0,
-datapath__551: VCU118RocketSystem__GC0,
-case__1427: APBGpsBlock__GC0,
-logic__7355: VCU118RocketSystem__GC0,
-case__314: VCU118RocketSystem__GC0,
-case__627: RocketTile__GCB0,
-Arbiter8_DCacheMetadataReq: DCache,
-logic__7291: VCU118RocketSystem__GC0,
-reg__163: VCU118RocketSystem__GC0,
-logic__2766: DCache,
-logic__7196: VCU118RocketSystem__GC0,
-reg__566: FPU__GB1,
-logic__6853: VCU118RocketSystem__GC0,
-datapath__247: VCU118RocketSystem__GC0,
-reg__60: vcu118_rocket_top__GC0,
-logic__22: vcu118_rocket_top__GC0,
-logic__713: vcu118_rocket_top__GC0,
-logic__4137: FPU__GB2,
-case__2: vcu118_rocket_top__GC0,
-reg__975: VCU118RocketSystem__GC0,
-case__266: VCU118RocketSystem__GC0,
-logic__9000: tracking_wrapper,
-case__463: VCU118RocketSystem__GC0,
-case__151: vcu118_rocket_top__GC0,
-reg__1155: APBGpsBlock__GC0,
-logic__4482: FPU__GB1,
-case__1435: APBGpsBlock__GC0,
-datapath__150: VCU118RocketSystem__GC0,
-case__146: vcu118_rocket_top__GC0,
-case__247: VCU118RocketSystem__GC0,
-FixedClockBroadcast_3: VCU118RocketSystem__GC0,
-logic__122: vcu118_rocket_top__GC0,
-case__896: RocketTile__GCB0,
-logic__9390: APBGpsBlock__GC0,
-reg__269: VCU118RocketSystem__GC0,
-logic__1464: VCU118RocketSystem__GC0,
-logic__9290: tracking_wrapper,
-logic__8613: APBGpsBlock__GC0,
-logic__4114: FPU__GB2,
-cordic_atan_one_stage: tracking_wrapper,
-case__567: RocketTile__GCB0,
-logic__6805: VCU118RocketSystem__GC0,
-logic__5856: RocketTile__GCB0,
-keep__2: vcu118_rocket_top__GC0,
-logic__355: vcu118_rocket_top__GC0,
-case__914: RocketTile__GCB0,
-logic__2246: DCache,
-case__1157: VCU118RocketSystem__GC0,
-keep__10: tracking_wrapper,
-logic__7110: VCU118RocketSystem__GC0,
-logic__7028: VCU118RocketSystem__GC0,
-logic__6949: VCU118RocketSystem__GC0,
-reg__818: RocketTile__GCB0,
-reg__796: RocketTile__GCB0,
-logic__6883: VCU118RocketSystem__GC0,
-logic__668: vcu118_rocket_top__GC0,
-case__1212: VCU118RocketSystem__GC0,
-case__1057: VCU118RocketSystem__GC0,
-logic__7943: VCU118RocketSystem__GC0,
-logic__5861: RocketTile__GCB0,
-reg__297: VCU118RocketSystem__GC0,
-logic__7160: VCU118RocketSystem__GC0,
-case__1006: VCU118RocketSystem__GC0,
-datapath__108: VCU118RocketSystem__GC0,
-dsp48e2__17: APBGpsBlock__GC0,
-logic__381: vcu118_rocket_top__GC0,
-TLBuffer_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__1671: VCU118RocketSystem__GC0,
-datapath__695: tracking_wrapper,
-dsp48e2__25: APBGpsBlock__GC0,
-case__452: VCU118RocketSystem__GC0,
-datapath__655: APBGpsBlock__GC0,
-logic__2568: DCache,
-reg__714: RocketTile__GCB0,
-logic__5440: RocketTile__GCB0,
-case__371: VCU118RocketSystem__GC0,
-case__1622: tracking_wrapper,
-logic__9251: tracking_wrapper,
-case__1234: VCU118RocketSystem__GC0,
-reg__731: RocketTile__GCB0,
-logic__916: VCU118RocketSystem__GC0,
-logic__70: vcu118_rocket_top__GC0,
-logic__6590: RocketTile__GCB0,
-reg__879: VCU118RocketSystem__GC0,
-reg__225: VCU118RocketSystem__GC0,
-datapath__58: VCU118RocketSystem__GC0,
-case__1074: VCU118RocketSystem__GC0,
-logic__5096: FPU__GB1,
-case__1366: APBGpsBlock__GC0,
-datapath__214: VCU118RocketSystem__GC0,
-logic__2765: DCache,
-logic__4256: FPU__GB1,
-case__499: RocketTile__GCB0,
-reg__1390: tracking_wrapper,
-logic__4025: FPU__GB2,
-muxpart__263: RocketTile__GCB0,
-reg__1185: APBGpsBlock__GC0,
-case__299: VCU118RocketSystem__GC0,
-logic__2784: DCache,
-logic__5625: RocketTile__GCB0,
-logic__2059: VCU118RocketSystem__GC0,
-logic__5571: RocketTile__GCB0,
-logic__5926: RocketTile__GCB0,
-case__580: RocketTile__GCB0,
-logic__6763: VCU118RocketSystem__GC0,
-case__495: RocketTile__GCB0,
-logic__4757: FPU__GB2,
-logic__3237: RocketTile__GCB0,
-case__1419: APBGpsBlock__GC0,
-logic__3639: FPU__GB2, FPU__GB1,
-reg__808: RocketTile__GCB0,
-logic__3293: RocketTile__GCB0,
-case__582: RocketTile__GCB0,
-case__1547: tracking_wrapper,
-case__818: RocketTile__GCB0,
-case__1184: VCU118RocketSystem__GC0,
-logic__7175: VCU118RocketSystem__GC0,
-cdc_fifo_gray_src: tracking_wrapper,
-case__312: VCU118RocketSystem__GC0,
-logic__2697: DCache,
-logic__7783: VCU118RocketSystem__GC0,
-logic__7256: VCU118RocketSystem__GC0,
-logic__3265: RocketTile__GCB0,
-reg__912: VCU118RocketSystem__GC0,
-reg__1090: APBGpsBlock__GC0,
-logic__8973: tracking_wrapper,
-reg__102: vcu118_rocket_top__GC0,
-logic__2295: DCache,
-logic__1909: VCU118RocketSystem__GC0,
-reg__1353: tracking_wrapper,
-logic__7977: VCU118RocketSystem__GC0,
-logic__6069: RocketTile__GCB0,
-reg__149: VCU118RocketSystem__GC0,
-logic__9304: tracking_wrapper,
-logic__4385: FPU__GB1,
-case__629: RocketTile__GCB0,
-reg__145: VCU118RocketSystem__GC0,
-datapath__101: VCU118RocketSystem__GC0,
-case__530: DCache,
-reg__1270: tracking_wrapper,
-logic__4791: FPU__GB2,
-logic__5973: RocketTile__GCB0,
-case__451: VCU118RocketSystem__GC0,
-logic__1443: VCU118RocketSystem__GC0,
-datapath__367: FPU__GB1,
-logic__2506: RocketTile__GCB0, DCache,
-muxpart__233: FPU__GB0,
-logic__896: VCU118RocketSystem__GC0,
-logic__3453: FPU__GB1,
-logic__5209: RocketTile__GCB0,
-logic__8511: APBGpsBlock__GC0,
-logic__7176: VCU118RocketSystem__GC0,
-case__337: VCU118RocketSystem__GC0,
-logic__4809: FPU__GB2,
-case__525: DCache,
-datapath__654: APBGpsBlock__GC0,
-case__424: VCU118RocketSystem__GC0,
-logic__6356: RocketTile__GCB0,
-case__948: RocketTile__GCB0,
-reg__743: RocketTile__GCB0,
-reg__473: FPU__GB0,
-datapath__149: VCU118RocketSystem__GC0,
-logic__7995: VCU118RocketSystem__GC0,
-reg__567: FPU__GB1,
-reg__906: VCU118RocketSystem__GC0,
-logic__3406: FPU__GB1,
-logic__302: vcu118_rocket_top__GC0,
-logic__4291: FPU__GB1,
-logic__6196: RocketTile__GCB0,
-case__676: FPU__GB2,
-logic__1980: VCU118RocketSystem__GC0,
-case__33: vcu118_rocket_top__GC0,
-logic__5423: RocketTile__GCB0,
-muxpart__152: vcu118_rocket_top__GC0,
-reg__1061: VCU118RocketSystem__GC0,
-logic__1559: VCU118RocketSystem__GC0,
-reg__334: DCache,
-reg__546: FPU__GB1,
-logic__317: vcu118_rocket_top__GC0,
-logic__206: vcu118_rocket_top__GC0,
-logic__4814: FPU__GB2,
-logic__5930: RocketTile__GCB0,
-case__1551: tracking_wrapper,
-logic__6762: VCU118RocketSystem__GC0,
-case__149: vcu118_rocket_top__GC0,
-logic__7271: VCU118RocketSystem__GC0,
-logic__4825: FPU__GB2,
-logic__256: vcu118_rocket_top__GC0,
-case__1144: VCU118RocketSystem__GC0,
-datapath__130: VCU118RocketSystem__GC0,
-case__230: VCU118RocketSystem__GC0,
-reg__1318: tracking_wrapper,
-logic__7937: VCU118RocketSystem__GC0,
-TLWidthWidget1: VCU118RocketSystem__GC0,
-logic__4057: FPU__GB2,
-logic__5489: RocketTile__GCB0,
-OptimizationBarrier_TLBEntryData: RocketTile__GCB0, DCache,
-logic__734: vcu118_rocket_top__GC0,
-reg__1344: tracking_wrapper,
-logic__8914: tracking_wrapper,
-case__1209: VCU118RocketSystem__GC0,
-datapath__72: VCU118RocketSystem__GC0,
-case__633: RocketTile__GCB0,
-logic__7036: VCU118RocketSystem__GC0,
-logic__3850: FPU__GB2,
-case__859: RocketTile__GCB0,
-logic__1000: VCU118RocketSystem__GC0,
-logic__2106: RocketTile__GCB0,
-logic__1782: VCU118RocketSystem__GC0,
-logic__5060: FPU__GB1,
-case__738: FPU__GB2,
-logic__7976: VCU118RocketSystem__GC0,
-reg__951: VCU118RocketSystem__GC0,
-logic__3298: FPU__GB1,
-case__1134: VCU118RocketSystem__GC0,
-logic__7357: VCU118RocketSystem__GC0,
-logic__5287: RocketTile__GCB0,
-logic__1125: VCU118RocketSystem__GC0,
-reg__1305: tracking_wrapper,
-logic__8604: APBGpsBlock__GC0,
-logic__3685: FPU__GB2,
-logic__236: vcu118_rocket_top__GC0,
-case__1175: VCU118RocketSystem__GC0,
-logic__8927: tracking_wrapper,
-logic__6829: VCU118RocketSystem__GC0,
-logic__4676: FPU__GB1,
-datapath__707: tracking_wrapper,
-case__173: vcu118_rocket_top__GC0,
-reg__268: VCU118RocketSystem__GC0,
-logic__8174: VCU118RocketSystem__GC0,
-case__408: VCU118RocketSystem__GC0,
-logic__714: vcu118_rocket_top__GC0,
-counter__5: vcu118_rocket_top__GC0,
-logic__2585: DCache,
-logic__753: vcu118_rocket_top__GC0,
-case__1236: VCU118RocketSystem__GC0,
-datapath__32: VCU118RocketSystem__GC0,
-logic__6548: RocketTile__GCB0,
-reg__169: VCU118RocketSystem__GC0,
-case__1692: TLToAPB,
-logic__1196: VCU118RocketSystem__GC0,
-FPToInt: FPU__GB2,
-logic__4977: FPU__GB1,
-reg__235: VCU118RocketSystem__GC0,
-case__67: vcu118_rocket_top__GC0,
-case__925: RocketTile__GCB0,
-case__1121: VCU118RocketSystem__GC0,
-logic__765: vcu118_rocket_top__GC0,
-logic__7365: VCU118RocketSystem__GC0,
-logic__2412: DCache,
-reg__179: VCU118RocketSystem__GC0,
-TLAsyncCrossingSink_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__6938: VCU118RocketSystem__GC0,
-SBToTL: VCU118RocketSystem__GC0,
-case__908: RocketTile__GCB0,
-case__1684: TLToAPB,
-logic__1113: VCU118RocketSystem__GC0,
-logic__5127: FPU__GB0,
-logic__7049: VCU118RocketSystem__GC0,
-logic__5056: FPU__GB1,
-logic__7924: VCU118RocketSystem__GC0,
-logic__2772: DCache,
-logic__8995: tracking_wrapper,
-case__620: RocketTile__GCB0,
-logic__5941: RocketTile__GCB0,
-ram_2x99: VCU118RocketSystem__GC0,
-reg__137: VCU118RocketSystem__GC0,
-logic__3502: FPU__GB1,
-reg__894: VCU118RocketSystem__GC0,
-logic__1003: VCU118RocketSystem__GC0,
-MulAddRecFNToRaw_preMul: FPU__GB1,
-datapath__302: RocketTile__GCB0,
-logic__1579: VCU118RocketSystem__GC0,
-logic__8527: APBGpsBlock__GC0,
-logic__231: vcu118_rocket_top__GC0,
-case__811: RocketTile__GCB0,
-counter__29: tracking_wrapper,
-logic__4102: FPU__GB2,
-logic__9133: tracking_wrapper,
-logic__7242: VCU118RocketSystem__GC0,
-logic__8504: APBGpsBlock__GC0,
-logic__5368: RocketTile__GCB0,
-logic__3303: FPU__GB1,
-logic__5026: FPU__GB1,
-logic__7396: VCU118RocketSystem__GC0,
-logic__5599: RocketTile__GCB0,
-datapath__588: APBGpsBlock__GC0,
-logic__1529: VCU118RocketSystem__GC0,
-logic__8264: APBGpsBlock__GC0,
-case__945: RocketTile__GCB0,
-case__624: RocketTile__GCB0,
-logic__6708: RocketTile__GCB0,
-case__482: VCU118RocketSystem__GC0,
-case__419: VCU118RocketSystem__GC0,
-reg__1191: APBGpsBlock__GC0,
-logic__5037: FPU__GB1,
-logic__3015: RocketTile__GCB0,
-case__39: vcu118_rocket_top__GC0,
-datapath__463: RocketTile__GCB0,
-case__1619: tracking_wrapper,
-logic__338: vcu118_rocket_top__GC0,
-muxpart__28: vcu118_rocket_top__GC0,
-case__1424: APBGpsBlock__GC0,
-logic__1908: VCU118RocketSystem__GC0,
-logic__1892: VCU118RocketSystem__GC0,
-case__679: FPU__GB2,
-case__377: VCU118RocketSystem__GC0,
-reg__1287: tracking_wrapper,
-muxpart__59: vcu118_rocket_top__GC0,
-case__667: FPU__GB2,
-datapath__93: VCU118RocketSystem__GC0,
-reg__1404: TLToAPB,
-logic__2649: DCache,
-logic__7473: VCU118RocketSystem__GC0,
-reg__1141: APBGpsBlock__GC0,
-reg__578: FPU__GB2,
-logic__4360: FPU__GB1,
-logic__8221: VCU118RocketSystem__GC0,
-logic__8784: APBGpsBlock__GC0,
-logic__5160: FPU__GB1,
-datapath__170: VCU118RocketSystem__GC0,
-logic__8485: APBGpsBlock__GC0,
-logic__9437: TLToAPB,
-logic__3232: RocketTile__GCB0,
-logic__733: vcu118_rocket_top__GC0,
-case__66: vcu118_rocket_top__GC0,
-logic__243: vcu118_rocket_top__GC0,
-logic__7347: VCU118RocketSystem__GC0,
-logic__6709: RocketTile__GCB0,
-case__1635: tracking_wrapper,
-case__156: vcu118_rocket_top__GC0,
-datapath__353: FPU__GB2,
-logic__4181: FPU__GB1,
-case__1536: tracking_wrapper,
-muxpart__148: vcu118_rocket_top__GC0,
-reg__199: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__2859: DCache,
-reg__954: VCU118RocketSystem__GC0,
-logic__8767: APBGpsBlock__GC0,
-datapath__340: FPU__GB2,
-TLInterconnectCoupler_cbus_to_clint: VCU118RocketSystem__GC0,
-datapath__114: VCU118RocketSystem__GC0,
-logic__9238: tracking_wrapper,
-logic__5946: RocketTile__GCB0,
-logic__6543: RocketTile__GCB0,
-case__1235: VCU118RocketSystem__GC0,
-reg__647: FPU__GB1,
-logic__3496: FPU__GB1,
-logic__9050: tracking_wrapper,
-logic__1986: VCU118RocketSystem__GC0,
-logic__1898: VCU118RocketSystem__GC0,
-case__744: FPU__GB2,
-logic__7146: VCU118RocketSystem__GC0,
-case__398: VCU118RocketSystem__GC0,
-logic__2539: RocketTile__GCB0, DCache,
-muxpart__192: FPU__GB0,
-case__574: RocketTile__GCB0,
-logic__8352: APBGpsBlock__GC0,
-logic__7936: VCU118RocketSystem__GC0,
-case__793: FPU__GB1,
-logic__5735: RocketTile__GCB0,
-datapath__205: VCU118RocketSystem__GC0,
-logic__2970: RocketTile__GCB0,
-logic__1612: VCU118RocketSystem__GC0,
-logic__4368: FPU__GB1,
-datapath__511: VCU118RocketSystem__GC0,
-logic__3551: FPU__GB1,
-case__1611: tracking_wrapper,
-datapath__221: VCU118RocketSystem__GC0,
-muxpart__190: FPU__GB0,
-logic__4812: FPU__GB2,
-case__1153: VCU118RocketSystem__GC0,
-case__1226: VCU118RocketSystem__GC0,
-logic__2777: DCache,
-logic__5460: RocketTile__GCB0,
-logic__4485: FPU__GB1,
-logic__272: vcu118_rocket_top__GC0,
-reg__276: VCU118RocketSystem__GC0,
-logic__849: VCU118RocketSystem__GC0,
-reg__775: RocketTile__GCB0,
-case__521: DCache,
-case__481: VCU118RocketSystem__GC0,
-reg__411: RocketTile__GCB0,
-datapath__619: APBGpsBlock__GC0,
-logic__5975: RocketTile__GCB0,
-logic__2201: DCache,
-dsp48e2__37: tracking_wrapper,
-logic__2503: RocketTile__GCB0, DCache,
-reg__622: FPU__GB1,
-reg__91: vcu118_rocket_top__GC0,
-case__128: vcu118_rocket_top__GC0,
-logic__784: VCU118RocketSystem__GC0,
-muxpart__252: FPU__GB1,
-reg__1222: tracking_wrapper,
-logic__4098: FPU__GB2,
-datapath__438: RocketTile__GCB0,
-logic__388: vcu118_rocket_top__GC0,
-datapath__10: vcu118_rocket_top__GC0,
-datapath__519: VCU118RocketSystem__GC0,
-datapath__67: VCU118RocketSystem__GC0,
-reset_synch: tracking_wrapper,
-case__1550: tracking_wrapper,
-logic__4711: FPU__GB2,
-case__1110: VCU118RocketSystem__GC0,
-case__52: vcu118_rocket_top__GC0,
-logic__4880: FPU__GB2,
-logic__5958: RocketTile__GCB0,
-case__775: FPU__GB1,
-logic__1046: VCU118RocketSystem__GC0,
-logic__6975: VCU118RocketSystem__GC0,
-case__592: RocketTile__GCB0,
-logic__5415: RocketTile__GCB0,
-datapath__17: vcu118_rocket_top__GC0,
-logic__7986: VCU118RocketSystem__GC0,
-logic__7193: VCU118RocketSystem__GC0,
-reg__1300: tracking_wrapper,
-Queue2_TLBundleA_a29d64s2k1z3u: VCU118RocketSystem__GC0,
-logic__2907: DCache,
-logic__9165: tracking_wrapper,
-case__890: RocketTile__GCB0,
-logic__2324: DCache,
-case__1326: APBGpsBlock__GC0,
-logic__4939: FPU__GB2,
-reg__981: VCU118RocketSystem__GC0,
-reg__255: VCU118RocketSystem__GC0,
-logic__1337: VCU118RocketSystem__GC0,
-datapath__555: VCU118RocketSystem__GC0,
-case__45: vcu118_rocket_top__GC0,
-reg__1370: tracking_wrapper,
-logic__8626: APBGpsBlock__GC0,
-logic__4964: FPU__GB2,
-logic__8801: tracking_wrapper,
-case__623: RocketTile__GCB0,
-logic__4136: FPU__GB2,
-logic__7180: VCU118RocketSystem__GC0,
-logic__1279: VCU118RocketSystem__GC0,
-logic__9092: tracking_wrapper,
-case__1642: tracking_wrapper,
-logic__305: vcu118_rocket_top__GC0,
-logic__7630: VCU118RocketSystem__GC0,
-case__1045: VCU118RocketSystem__GC0,
-logic__7375: VCU118RocketSystem__GC0,
-logic__5605: RocketTile__GCB0,
-case__897: RocketTile__GCB0,
-logic__4080: FPU__GB2,
-case__701: FPU__GB1,
-logic__7185: VCU118RocketSystem__GC0,
-datapath__298: RocketTile__GCB0,
-reg__370: DCache,
-reg__1187: APBGpsBlock__GC0,
-logic__1027: VCU118RocketSystem__GC0,
-logic__5215: RocketTile__GCB0,
-case__201: vcu118_rocket_top__GC0,
-logic__4997: FPU__GB1,
-logic__2210: DCache,
-logic__5744: RocketTile__GCB0,
-logic__8805: tracking_wrapper,
-logic__6621: RocketTile__GCB0,
-reg__1379: tracking_wrapper,
-logic__9085: tracking_wrapper,
-reg__978: VCU118RocketSystem__GC0,
-logic__9250: tracking_wrapper,
-logic__759: vcu118_rocket_top__GC0,
-logic__3492: FPU__GB1,
-case__686: FPU__GB2,
-reg__829: RocketTile__GCB0,
-reg__1351: tracking_wrapper,
-logic__8690: APBGpsBlock__GC0,
-logic__7870: VCU118RocketSystem__GC0,
-reg__594: FPU__GB2,
-reg__656: RocketTile__GCB0,
-logic__5921: RocketTile__GCB0,
-logic__5047: FPU__GB1,
-logic__2067: RocketTile__GCB0,
-ClockGroup: VCU118RocketSystem__GC0,
-logic__745: vcu118_rocket_top__GC0,
-logic__6647: RocketTile__GCB0,
-logic__112: vcu118_rocket_top__GC0,
-datapath__260: VCU118RocketSystem__GC0,
-logic__7544: VCU118RocketSystem__GC0,
-muxpart__228: FPU__GB0,
-datapath__659: tracking_wrapper,
-logic__2080: RocketTile__GCB0,
-reg__741: RocketTile__GCB0,
-datapath__363: FPU__GB2,
-logic__7991: VCU118RocketSystem__GC0,
-logic__9422: APBGpsBlock__GC0,
-muxpart__41: vcu118_rocket_top__GC0,
-regfile_32x65: FPU__GB0,
-logic__7420: VCU118RocketSystem__GC0,
-logic__6817: VCU118RocketSystem__GC0,
-logic__5618: RocketTile__GCB0,
-MulAddRecFNPipe_l2_e11_s53: FPU__GB1,
-case__544: DCache,
-logic__2050: VCU118RocketSystem__GC0,
-reg__1299: tracking_wrapper,
-case__1636: tracking_wrapper,
-reg__640: FPU__GB1,
-logic__794: VCU118RocketSystem__GC0,
-logic__3474: FPU__GB1,
-logic__95: vcu118_rocket_top__GC0,
-logic__6537: RocketTile__GCB0,
-logic__3905: FPU__GB2,
-datapath__349: FPU__GB2,
-logic__7244: VCU118RocketSystem__GC0,
-logic__5960: RocketTile__GCB0,
-reg__375: RocketTile__GCB0,
-reg__514: FPU__GB2,
-logic__5147: FPU__GB1,
-logic__3089: RocketTile__GCB0,
-logic__1079: VCU118RocketSystem__GC0,
-logic__2161: DCache,
-reg__893: VCU118RocketSystem__GC0,
-logic__7680: VCU118RocketSystem__GC0,
-logic__9206: tracking_wrapper,
-logic__3412: FPU__GB1,
-logic__2140: RocketTile__GCB0,
-logic__8857: tracking_wrapper,
-muxpart__74: vcu118_rocket_top__GC0,
-logic__180: vcu118_rocket_top__GC0,
-extram__5: APBGpsBlock__GC0,
-reg__934: VCU118RocketSystem__GC0,
-logic__6166: RocketTile__GCB0,
-logic__8917: tracking_wrapper,
-logic__8474: APBGpsBlock__GC0,
-muxpart__255: FPU__GB2,
-logic__7280: VCU118RocketSystem__GC0,
-reg__248: VCU118RocketSystem__GC0,
-case__284: VCU118RocketSystem__GC0,
-logic__2317: DCache,
-logic__4354: FPU__GB1,
-logic__6527: RocketTile__GCB0,
-dsp48e2__12: APBGpsBlock__GC0,
-case__1142: VCU118RocketSystem__GC0,
-logic__682: vcu118_rocket_top__GC0,
-case__808: RocketTile__GCB0,
-muxpart__89: vcu118_rocket_top__GC0,
-logic__1950: VCU118RocketSystem__GC0,
-logic__3550: FPU__GB1,
-datapath__360: FPU__GB2,
-logic__3241: RocketTile__GCB0,
-logic__5333: RocketTile__GCB0,
-logic__4476: FPU__GB1,
-logic__1320: VCU118RocketSystem__GC0,
-logic__2622: DCache,
-muxpart__49: vcu118_rocket_top__GC0,
-case__1303: APBGpsBlock__GC0,
-logic__637: vcu118_rocket_top__GC0,
-datapath__146: VCU118RocketSystem__GC0,
-reg__1211: tracking_wrapper,
-logic__6871: VCU118RocketSystem__GC0,
-reg__443: RocketTile__GCB0,
-logic__5969: RocketTile__GCB0,
-logic__8507: APBGpsBlock__GC0,
-case__975: RocketTile__GCB0,
-logic__392: vcu118_rocket_top__GC0,
-logic__1414: VCU118RocketSystem__GC0,
-logic__1179: VCU118RocketSystem__GC0,
-reg__974: VCU118RocketSystem__GC0,
-logic__6878: VCU118RocketSystem__GC0,
-logic__864: VCU118RocketSystem__GC0,
-logic__3744: FPU__GB2,
-logic__1755: VCU118RocketSystem__GC0,
-logic__2818: DCache,
-logic__1530: VCU118RocketSystem__GC0,
-datapath__653: APBGpsBlock__GC0,
-logic__7863: VCU118RocketSystem__GC0,
-reg__723: RocketTile__GCB0,
-logic__635: vcu118_rocket_top__GC0,
-logic__6370: RocketTile__GCB0,
-logic__7112: VCU118RocketSystem__GC0,
-logic__5627: RocketTile__GCB0,
-datapath__571: APBGpsBlock__GC0,
-logic__3737: FPU__GB2,
-logic__1494: VCU118RocketSystem__GC0,
-datapath__106: VCU118RocketSystem__GC0,
-case__279: VCU118RocketSystem__GC0,
-logic__134: vcu118_rocket_top__GC0,
-muxpart__92: vcu118_rocket_top__GC0,
-muxpart__71: vcu118_rocket_top__GC0,
-logic__1916: VCU118RocketSystem__GC0,
-logic__7387: VCU118RocketSystem__GC0,
-logic__4197: FPU__GB1,
-case__70: vcu118_rocket_top__GC0,
-case__381: VCU118RocketSystem__GC0,
-logic__4869: FPU__GB2,
-logic__642: vcu118_rocket_top__GC0,
-logic__8345: APBGpsBlock__GC0,
-reg__967: VCU118RocketSystem__GC0,
-logic__9194: tracking_wrapper,
-logic__4397: FPU__GB1,
-logic__4520: FPU__GB1,
-datapath__376: FPU__GB1,
-logic__7100: VCU118RocketSystem__GC0,
-logic__1860: VCU118RocketSystem__GC0,
-case__1428: APBGpsBlock__GC0,
-logic__7189: VCU118RocketSystem__GC0,
-case__1250: APBGpsBlock__GC0,
-case__1652: tracking_wrapper,
-case__1583: tracking_wrapper,
-datapath__562: APBGpsBlock__GC0,
-counter__10: VCU118RocketSystem__GC0,
-case__1327: APBGpsBlock__GC0,
-datapath__636: APBGpsBlock__GC0,
-logic__3294: RocketTile__GCB0,
-logic__415: vcu118_rocket_top__GC0,
-logic__2586: DCache,
-datapath__61: VCU118RocketSystem__GC0,
-reg__1189: APBGpsBlock__GC0,
-case__819: RocketTile__GCB0,
-logic__6757: VCU118RocketSystem__GC0,
-logic__2692: DCache,
-reg__1335: tracking_wrapper,
-datapath__505: VCU118RocketSystem__GC0,
-logic__6357: RocketTile__GCB0,
-case__506: DCache,
-rockettile_icache_tag_array_64x21: RocketTile__GCB0,
-logic__3898: FPU__GB2,
-reg__1247: tracking_wrapper,
-logic__3605: FPU__GB2, FPU__GB1,
-logic__2205: DCache,
-logic__4497: FPU__GB1,
-reg__1169: APBGpsBlock__GC0,
-datapath__203: VCU118RocketSystem__GC0,
-case__929: RocketTile__GCB0,
-case__664: FPU__GB2,
-rom__4: APBGpsBlock__GC0,
-logic__4185: FPU__GB1,
-datapath__45: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__5922: RocketTile__GCB0,
-datapath__168: VCU118RocketSystem__GC0,
-muxpart__383: tracking_wrapper,
-case__142: vcu118_rocket_top__GC0,
-case__214: vcu118_rocket_top__GC0,
-logic__3855: FPU__GB2,
-reg__1337: tracking_wrapper,
-logic__8606: APBGpsBlock__GC0,
-case__562: DCache,
-AsyncResetRegVec_w1_i0: VCU118RocketSystem__GC0,
-muxpart__256: FPU__GB2,
-reg__430: RocketTile__GCB0,
-logic__4429: FPU__GB1,
-case__1650: tracking_wrapper,
-logic__2978: RocketTile__GCB0,
-muxpart__220: FPU__GB0,
-logic__7850: VCU118RocketSystem__GC0,
-case__1300: APBGpsBlock__GC0,
-logic__4962: FPU__GB2,
-logic__2904: DCache,
-datapath__391: FPU__GB1,
-logic__8949: tracking_wrapper,
-logic__7593: VCU118RocketSystem__GC0,
-logic__4148: FPU__GB1,
-logic__8152: VCU118RocketSystem__GC0,
-case__1196: VCU118RocketSystem__GC0,
-case__1132: VCU118RocketSystem__GC0,
-reg__347: DCache,
-logic__1879: VCU118RocketSystem__GC0,
-logic__9394: APBGpsBlock__GC0,
-logic__6047: RocketTile__GCB0,
-case__468: VCU118RocketSystem__GC0,
-reg__260: VCU118RocketSystem__GC0,
-logic__1526: VCU118RocketSystem__GC0,
-logic__2157: DCache,
-case__1647: tracking_wrapper,
-logic__1365: VCU118RocketSystem__GC0,
-logic__8165: VCU118RocketSystem__GC0,
-logic__4741: FPU__GB2,
-logic__6999: VCU118RocketSystem__GC0,
-ifft_abs_sqr: APBGpsBlock__GC0,
-logic__4391: FPU__GB1,
-logic__7344: VCU118RocketSystem__GC0,
-reg__381: RocketTile__GCB0,
-logic__5985: RocketTile__GCB0,
-case__1242: VCU118RocketSystem__GC0,
-case__997: VCU118RocketSystem__GC0,
-logic__7930: VCU118RocketSystem__GC0,
-logic__6944: VCU118RocketSystem__GC0,
-case__435: VCU118RocketSystem__GC0,
-logic__6689: RocketTile__GCB0,
-logic__2677: DCache,
-logic__9294: tracking_wrapper,
-logic__235: vcu118_rocket_top__GC0,
-datapath__264: VCU118RocketSystem__GC0,
-DivSqrtRawFN_small: FPU__GB2,
-reg__806: RocketTile__GCB0,
-dsp48e2__33: tracking_wrapper,
-logic__6932: VCU118RocketSystem__GC0,
-logic__5251: RocketTile__GCB0,
-logic__770: VCU118RocketSystem__GC0,
-case__888: RocketTile__GCB0,
-logic__9134: tracking_wrapper,
-logic__3078: RocketTile__GCB0,
-case__956: RocketTile__GCB0,
-case__354: VCU118RocketSystem__GC0,
-case__1195: VCU118RocketSystem__GC0,
-logic__1368: VCU118RocketSystem__GC0,
-logic__1011: VCU118RocketSystem__GC0,
-logic__55: vcu118_rocket_top__GC0,
-logic__5407: RocketTile__GCB0,
-reg__1177: APBGpsBlock__GC0,
-logic__8800: tracking_wrapper,
-reg__589: FPU__GB2,
-logic__7975: VCU118RocketSystem__GC0,
-reg__1206: APBGpsBlock__GC0,
-reg__638: FPU__GB1,
-logic__2624: DCache,
-logic__7330: VCU118RocketSystem__GC0,
-case__1146: VCU118RocketSystem__GC0,
-datapath__141: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__1599: VCU118RocketSystem__GC0,
-logic__735: vcu118_rocket_top__GC0,
-reg__891: VCU118RocketSystem__GC0,
-case__473: VCU118RocketSystem__GC0,
-logic__2979: RocketTile__GCB0,
-logic__7439: VCU118RocketSystem__GC0,
-reg__897: VCU118RocketSystem__GC0,
-logic__8802: tracking_wrapper,
-datapath__485: RocketTile__GCB0,
-reg__1163: APBGpsBlock__GC0,
-logic__1889: VCU118RocketSystem__GC0,
-case__675: FPU__GB2,
-logic__5075: FPU__GB1,
-logic__8227: VCU118RocketSystem__GC0,
-logic__2962: RocketTile__GCB0,
-logic__5642: RocketTile__GCB0,
-logic__4176: FPU__GB1,
-logic__5282: RocketTile__GCB0,
-datapath__637: APBGpsBlock__GC0,
-reg__1251: tracking_wrapper,
-datapath__83: VCU118RocketSystem__GC0,
-logic__3817: FPU__GB2,
-logic__8220: VCU118RocketSystem__GC0,
-reg__494: FPU__GB1,
-reg__251: VCU118RocketSystem__GC0,
-logic__2481: RocketTile__GCB0, DCache,
-logic__7654: VCU118RocketSystem__GC0,
-logic__4968: FPU__GB2,
-case__15: vcu118_rocket_top__GC0,
-logic__8146: VCU118RocketSystem__GC0,
-logic__1868: VCU118RocketSystem__GC0,
-case__1671: APBGpsBlock__GC0,
-datapath__18: vcu118_rocket_top__GC0,
-logic__6983: VCU118RocketSystem__GC0,
-reg__391: RocketTile__GCB0,
-logic__5554: RocketTile__GCB0,
-logic__7379: VCU118RocketSystem__GC0,
-reg__1237: tracking_wrapper,
-logic__4430: FPU__GB1,
-logic__8540: APBGpsBlock__GC0,
-case__834: RocketTile__GCB0,
-logic__4038: FPU__GB2,
-logic__2858: DCache,
-logic__7470: VCU118RocketSystem__GC0,
-case__252: VCU118RocketSystem__GC0,
-logic__8944: tracking_wrapper,
-muxpart__72: vcu118_rocket_top__GC0,
-AsyncResetRegVec_w2_i0: VCU118RocketSystem__GC0,
-datapath__148: VCU118RocketSystem__GC0,
-logic__4395: FPU__GB1,
-logic__6830: VCU118RocketSystem__GC0,
-logic__7427: VCU118RocketSystem__GC0,
-logic__618: vcu118_rocket_top__GC0,
-case__1145: VCU118RocketSystem__GC0,
-case__784: FPU__GB1,
-logic__2436: DCache,
-case__32: vcu118_rocket_top__GC0,
-logic__3571: FPU__GB2, FPU__GB1,
-logic__5449: RocketTile__GCB0,
-datapath__66: VCU118RocketSystem__GC0,
-reg__1106: APBGpsBlock__GC0,
-case__1044: VCU118RocketSystem__GC0,
-reg__1119: APBGpsBlock__GC0,
-logic__2745: DCache,
-reg__980: VCU118RocketSystem__GC0,
-datapath__702: tracking_wrapper,
-logic__6764: VCU118RocketSystem__GC0,
-logic__1231: VCU118RocketSystem__GC0,
-case__303: VCU118RocketSystem__GC0,
-logic__1728: VCU118RocketSystem__GC0,
-reg__291: VCU118RocketSystem__GC0,
-logic__7369: VCU118RocketSystem__GC0,
-logic__2522: RocketTile__GCB0, DCache,
-logic__6067: RocketTile__GCB0,
-FPToFP: FPU__GB1,
-logic__8950: tracking_wrapper,
-extram__6: APBGpsBlock__GC0,
-logic__1528: VCU118RocketSystem__GC0,
-logic__9044: tracking_wrapper,
-datapath__521: VCU118RocketSystem__GC0,
-datapath__34: VCU118RocketSystem__GC0,
-logic__21: vcu118_rocket_top__GC0,
-ITLB: RocketTile__GCB0,
-case__618: RocketTile__GCB0,
-logic__5974: RocketTile__GCB0,
-case__820: RocketTile__GCB0,
-logic__9374: tracking_wrapper,
-ram__9: VCU118RocketSystem__GC0,
-logic__1849: VCU118RocketSystem__GC0,
-logic__906: VCU118RocketSystem__GC0,
-case__1422: APBGpsBlock__GC0,
-reg__387: RocketTile__GCB0,
-logic__1415: VCU118RocketSystem__GC0,
-case__157: vcu118_rocket_top__GC0,
-logic__7032: VCU118RocketSystem__GC0,
-logic__5079: FPU__GB1,
-logic__7386: VCU118RocketSystem__GC0,
-logic__1617: VCU118RocketSystem__GC0,
-logic__3962: FPU__GB2,
-dsp48e2__31: tracking_wrapper,
-logic__4450: FPU__GB1,
-logic__1139: VCU118RocketSystem__GC0,
-logic__4015: FPU__GB2,
-datapath__206: VCU118RocketSystem__GC0,
-muxpart__95: vcu118_rocket_top__GC0,
-datapath__339: FPU__GB2,
-logic__4396: FPU__GB1,
-logic__8965: tracking_wrapper,
-logic__9062: tracking_wrapper,
-logic__7624: VCU118RocketSystem__GC0,
-logic__8399: APBGpsBlock__GC0,
-case__969: RocketTile__GCB0,
-logic__6863: VCU118RocketSystem__GC0,
-logic__9055: tracking_wrapper,
-case__573: RocketTile__GCB0,
-logic__7213: VCU118RocketSystem__GC0,
-case__1436: APBGpsBlock__GC0,
-datapath__25: vcu118_rocket_top__GC0,
-case__268: VCU118RocketSystem__GC0,
-logic__5616: RocketTile__GCB0,
-logic__4405: FPU__GB1,
-logic__4727: FPU__GB2,
-case__1325: APBGpsBlock__GC0,
-logic__7432: VCU118RocketSystem__GC0,
-case__1017: VCU118RocketSystem__GC0,
-logic__1931: VCU118RocketSystem__GC0,
-RecFNToIN_1: FPU__GB2,
-logic__8486: APBGpsBlock__GC0,
-logic__2603: DCache,
-reg__1358: tracking_wrapper,
-counter__22: APBGpsBlock__GC0,
-logic__8925: tracking_wrapper,
-logic__9471: vcu118_rocket_top__GC0,
-reg__708: RocketTile__GCB0,
-logic__9463: VCU118RocketSystem__GC0,
-reg__819: RocketTile__GCB0,
-reg__522: FPU__GB2,
-case__1486: APBGpsBlock__GC0,
-logic__1560: VCU118RocketSystem__GC0,
-TLWidthWidget8: VCU118RocketSystem__GC0,
-logic__2478: RocketTile__GCB0, DCache,
-logic__4202: FPU__GB1,
-logic__7277: VCU118RocketSystem__GC0,
-logic__5967: RocketTile__GCB0,
-logic__895: VCU118RocketSystem__GC0,
-logic__4840: FPU__GB2,
-logic__750: vcu118_rocket_top__GC0,
-logic__5596: RocketTile__GCB0,
-logic__3441: FPU__GB1,
-case__298: VCU118RocketSystem__GC0,
-case__962: RocketTile__GCB0,
-datapath__229: VCU118RocketSystem__GC0,
-case__385: VCU118RocketSystem__GC0,
-logic__7195: VCU118RocketSystem__GC0,
-logic__4634: FPU__GB2, FPU__GB1,
-datapath__283: DCache,
-reg__721: RocketTile__GCB0,
-case__1286: APBGpsBlock__GC0,
-logic__5551: RocketTile__GCB0,
-PlusArgTimeout: RocketTile__GCB0,
-logic__7425: VCU118RocketSystem__GC0,
-logic__8621: APBGpsBlock__GC0,
-datapath__525: VCU118RocketSystem__GC0,
-logic__2051: VCU118RocketSystem__GC0,
-logic__4817: FPU__GB2,
-logic__894: VCU118RocketSystem__GC0,
-reg__491: FPU__GB1,
-reg__226: VCU118RocketSystem__GC0,
-case__1395: APBGpsBlock__GC0,
-datapath__97: VCU118RocketSystem__GC0,
-datapath__324: FPU__GB1,
-datapath__497: VCU118RocketSystem__GC0,
-cordic_atan_one_stage__parameterized0: tracking_wrapper,
-logic__4546: FPU__GB2, FPU__GB1,
-logic__1492: VCU118RocketSystem__GC0,
-logic__9440: TLToAPB,
-logic__5413: RocketTile__GCB0,
-logic__207: vcu118_rocket_top__GC0,
-datapath__698: tracking_wrapper,
-logic__7605: VCU118RocketSystem__GC0,
-logic__6779: VCU118RocketSystem__GC0,
-logic__5765: RocketTile__GCB0,
-logic__3743: FPU__GB2,
-logic__2869: DCache,
-reg__984: VCU118RocketSystem__GC0,
-reg__838: RocketTile__GCB0,
-logic__3902: FPU__GB2,
-case__1218: VCU118RocketSystem__GC0,
-logic__2211: DCache,
-case__1514: APBGpsBlock__GC0,
-logic__4489: FPU__GB1,
-TLInterconnectCoupler_cbus_to_plic: VCU118RocketSystem__GC0,
-logic__7363: VCU118RocketSystem__GC0,
-logic__7060: VCU118RocketSystem__GC0,
-counter__28: tracking_wrapper,
-datapath__715: tracking_wrapper,
-logic__2244: DCache,
-datapath__442: RocketTile__GCB0,
-counter__14: APBGpsBlock__GC0,
-logic__8736: APBGpsBlock__GC0,
-logic__5953: RocketTile__GCB0,
-logic__1050: VCU118RocketSystem__GC0,
-logic__6200: RocketTile__GCB0,
-logic__9056: tracking_wrapper,
-reg__842: RocketTile__GCB0,
-reg__1130: APBGpsBlock__GC0,
-case__504: DCache,
-case__883: RocketTile__GCB0,
-logic__7382: VCU118RocketSystem__GC0,
-logic__2020: VCU118RocketSystem__GC0,
-logic__4206: FPU__GB1,
-logic__881: VCU118RocketSystem__GC0,
-logic__5881: RocketTile__GCB0,
-case__727: FPU__GB2, FPU__GB1,
-reg__61: vcu118_rocket_top__GC0,
-muxpart__1: vcu118_rocket_top__GC0,
-datapath__520: VCU118RocketSystem__GC0,
-FPUDecoder: FPU__GB1,
-logic__7374: VCU118RocketSystem__GC0,
-reg__165: VCU118RocketSystem__GC0,
-logic__4406: FPU__GB1,
-logic__815: VCU118RocketSystem__GC0,
-reg__650: FPU__GB1,
-case__1279: APBGpsBlock__GC0,
-logic__7128: VCU118RocketSystem__GC0,
-PLICClockSinkDomain: VCU118RocketSystem__GC0,
-logic__1732: VCU118RocketSystem__GC0,
-logic__4597: FPU__GB2, FPU__GB1,
-logic__5292: RocketTile__GCB0,
-datapath__102: VCU118RocketSystem__GC0,
-logic__868: VCU118RocketSystem__GC0,
-logic__278: vcu118_rocket_top__GC0,
-case__972: RocketTile__GCB0,
-logic__7539: VCU118RocketSystem__GC0,
-case__251: VCU118RocketSystem__GC0,
-datapath__717: tracking_wrapper,
-reg__1142: APBGpsBlock__GC0,
-logic__7237: VCU118RocketSystem__GC0,
-case__768: FPU__GB2,
-reg__383: RocketTile__GCB0,
-TLDebugModuleInnerAsync: VCU118RocketSystem__GC0,
-reg__45: vcu118_rocket_top__GC0,
-case__215: vcu118_rocket_top__GC0,
-case__320: VCU118RocketSystem__GC0,
-reg__746: RocketTile__GCB0,
-reg__620: FPU__GB1,
-logic__7368: VCU118RocketSystem__GC0,
-sample_counter: APBGpsBlock__GC0,
-case__1069: VCU118RocketSystem__GC0,
-logic__1259: VCU118RocketSystem__GC0,
-reg__865: VCU118RocketSystem__GC0,
-case__891: RocketTile__GCB0,
-logic__3201: RocketTile__GCB0,
-case__861: RocketTile__GCB0,
-logic__8910: tracking_wrapper,
-case__1063: VCU118RocketSystem__GC0,
-case__1026: VCU118RocketSystem__GC0,
-datapath__491: RocketTile__GCB0,
-logic__8286: APBGpsBlock__GC0,
-logic__2262: DCache,
-reg__446: RocketTile__GCB0,
-logic__760: vcu118_rocket_top__GC0,
-case__1181: VCU118RocketSystem__GC0,
-logic__3095: RocketTile__GCB0,
-reg__46: vcu118_rocket_top__GC0,
-datapath__124: VCU118RocketSystem__GC0,
-reg__1332: tracking_wrapper,
-logic__3559: FPU__GB1,
-logic__3819: FPU__GB2,
-reg__999: VCU118RocketSystem__GC0,
-reg__1216: tracking_wrapper,
-reg__576: FPU__GB2,
-logic__7229: VCU118RocketSystem__GC0,
-case__671: FPU__GB2,
-logic__1744: VCU118RocketSystem__GC0,
-datapath__439: RocketTile__GCB0,
-datapath__26: vcu118_rocket_top__GC0,
-logic__140: vcu118_rocket_top__GC0,
-logic__1274: VCU118RocketSystem__GC0,
-logic__7371: VCU118RocketSystem__GC0,
-LevelGateway: VCU118RocketSystem__GC0,
-reg__429: RocketTile__GCB0,
-datapath__1: vcu118_rocket_top__GC0,
-logic__1504: VCU118RocketSystem__GC0,
-reg__366: DCache,
-logic__5939: RocketTile__GCB0,
-logic__4734: FPU__GB2,
-reg__707: RocketTile__GCB0,
-case__129: vcu118_rocket_top__GC0,
-logic__6760: VCU118RocketSystem__GC0,
-logic__8019: VCU118RocketSystem__GC0,
-case__926: RocketTile__GCB0,
-case__781: FPU__GB2,
-case__1639: tracking_wrapper,
-reg__668: RocketTile__GCB0,
-logic__3839: FPU__GB2,
-logic__3779: FPU__GB2,
-logic__7968: VCU118RocketSystem__GC0,
-logic__3901: FPU__GB2,
-logic__3014: RocketTile__GCB0,
-reg__476: FPU__GB0,
-case__1554: tracking_wrapper,
-logic__1191: VCU118RocketSystem__GC0,
-case__725: FPU__GB2, FPU__GB1,
-case__1160: VCU118RocketSystem__GC0,
-addsub__2: tracking_wrapper,
-logic__5044: FPU__GB1,
-logic__125: vcu118_rocket_top__GC0,
-logic__7587: VCU118RocketSystem__GC0,
-logic__1700: VCU118RocketSystem__GC0,
-logic__9260: tracking_wrapper,
-datapath__374: FPU__GB1,
-logic__2396: DCache,
-case__1128: VCU118RocketSystem__GC0,
-logic__4261: FPU__GB1,
-reg__947: VCU118RocketSystem__GC0,
-case__560: DCache,
-reg__404: RocketTile__GCB0,
-logic__6798: VCU118RocketSystem__GC0,
-case__924: RocketTile__GCB0,
-logic__9305: tracking_wrapper,
-logic__7203: VCU118RocketSystem__GC0,
-logic__4601: FPU__GB2, FPU__GB1,
-logic__1301: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__909: VCU118RocketSystem__GC0,
-reg__1354: tracking_wrapper,
-reg__631: FPU__GB1,
-datapath__405: FPU__GB2,
-logic__725: vcu118_rocket_top__GC0,
-logic__4078: FPU__GB2,
-case__801: FPU__GB1,
-logic__6842: VCU118RocketSystem__GC0,
-reg__681: RocketTile__GCB0,
-reg__140: VCU118RocketSystem__GC0,
-case__6: vcu118_rocket_top__GC0,
-reg__1146: APBGpsBlock__GC0,
-logic__3036: RocketTile__GCB0,
-reg__1380: tracking_wrapper,
-logic__9183: tracking_wrapper,
-reg__178: VCU118RocketSystem__GC0,
-logic__7150: VCU118RocketSystem__GC0,
-case__1297: APBGpsBlock__GC0,
-datapath__117: VCU118RocketSystem__GC0,
-case__698: FPU__GB2,
-logic__7499: VCU118RocketSystem__GC0,
-datapath__209: VCU118RocketSystem__GC0,
-datapath__595: APBGpsBlock__GC0,
-logic__4796: FPU__GB2,
-logic__74: vcu118_rocket_top__GC0,
-logic__938: VCU118RocketSystem__GC0,
-logic__854: VCU118RocketSystem__GC0,
-logic__8364: APBGpsBlock__GC0,
-reg__1215: tracking_wrapper,
-reg__574: FPU__GB2,
-logic__6177: RocketTile__GCB0,
-reg__957: VCU118RocketSystem__GC0,
-reg__964: VCU118RocketSystem__GC0,
-logic__7388: VCU118RocketSystem__GC0,
-logic__1621: VCU118RocketSystem__GC0,
-reg__761: RocketTile__GCB0,
-case__1560: tracking_wrapper,
-case__1060: VCU118RocketSystem__GC0,
-logic__9316: tracking_wrapper,
-IBuf: RocketTile__GCB0,
-logic__5080: FPU__GB1,
-reg__1229: tracking_wrapper,
-datapath__640: APBGpsBlock__GC0,
-logic__7562: VCU118RocketSystem__GC0,
-logic__6753: VCU118RocketSystem__GC0,
-muxpart__217: FPU__GB0,
-datapath__171: VCU118RocketSystem__GC0,
-logic__5038: FPU__GB1,
-case__43: vcu118_rocket_top__GC0,
-logic__680: vcu118_rocket_top__GC0,
-logic__6948: VCU118RocketSystem__GC0,
-logic__1347: VCU118RocketSystem__GC0,
-case__1370: APBGpsBlock__GC0,
-datapath__160: VCU118RocketSystem__GC0,
-datapath__134: VCU118RocketSystem__GC0,
-logic__6864: VCU118RocketSystem__GC0,
-case__1252: APBGpsBlock__GC0,
-case__785: FPU__GB1,
-logic__6977: VCU118RocketSystem__GC0,
-logic__6803: VCU118RocketSystem__GC0,
-muxpart__21: vcu118_rocket_top__GC0,
-reg__267: VCU118RocketSystem__GC0,
-reg__1031: VCU118RocketSystem__GC0,
-logic__6566: RocketTile__GCB0,
-TLAtomicAutomata_pbus: VCU118RocketSystem__GC0,
-logic__2738: DCache,
-case__981: RocketTile__GCB0,
-case__614: RocketTile__GCB0,
-case__957: RocketTile__GCB0,
-logic__4296: FPU__GB1,
-MulDiv: RocketTile__GCB0,
-logic__470: vcu118_rocket_top__GC0,
-reg__286: VCU118RocketSystem__GC0,
-case__823: RocketTile__GCB0,
-logic__8411: APBGpsBlock__GC0,
-case__180: vcu118_rocket_top__GC0,
-reg__53: vcu118_rocket_top__GC0,
-datapath__16: vcu118_rocket_top__GC0,
-reg__783: RocketTile__GCB0,
-logic__5112: FPU__GB1,
-TLInterconnectCoupler_cbus_to_debug: VCU118RocketSystem__GC0,
-reg__795: RocketTile__GCB0,
-logic__1225: VCU118RocketSystem__GC0,
-logic__4262: FPU__GB1,
-case__724: FPU__GB2, FPU__GB1,
-logic__3870: FPU__GB2,
-logic__7515: VCU118RocketSystem__GC0,
-logic__7152: VCU118RocketSystem__GC0,
-datapath__201: VCU118RocketSystem__GC0,
-logic__5608: RocketTile__GCB0,
-extram__3: RocketTile__GCB0,
-reg__18: vcu118_rocket_top__GC0,
-datapath__528: VCU118RocketSystem__GC0,
-logic__2757: DCache,
-reg__409: RocketTile__GCB0,
-reg__330: DCache,
-logic__1321: VCU118RocketSystem__GC0,
-logic__9058: tracking_wrapper,
-case__177: vcu118_rocket_top__GC0,
-logic__2774: DCache,
-reg__517: FPU__GB2,
-logic__3599: FPU__GB2, FPU__GB1,
-logic__7116: VCU118RocketSystem__GC0,
-datapath__600: APBGpsBlock__GC0,
-logic__1131: VCU118RocketSystem__GC0,
-datapath__513: VCU118RocketSystem__GC0,
-logic__4960: FPU__GB2,
-datapath__334: FPU__GB2,
-logic__2454: DCache,
-logic__4066: FPU__GB2,
-muxpart__55: vcu118_rocket_top__GC0,
-reg__307: VCU118RocketSystem__GC0,
-datapath__543: VCU118RocketSystem__GC0,
-logic__7301: VCU118RocketSystem__GC0,
-logic__5622: RocketTile__GCB0,
-logic__1893: VCU118RocketSystem__GC0,
-reg__195: VCU118RocketSystem__GC0,
-logic__3297: FPU__GB1,
-reg__569: FPU__GB1,
-datapath__531: VCU118RocketSystem__GC0,
-muxpart__215: FPU__GB0,
-FrontBus: VCU118RocketSystem__GC0,
-logic__7820: VCU118RocketSystem__GC0,
-muxpart__248: FPU__GB0,
-logic__4425: FPU__GB1,
-case__1584: tracking_wrapper,
-case__598: RocketTile__GCB0,
-datapath__644: APBGpsBlock__GC0,
-case__681: FPU__GB2,
-datapath__670: tracking_wrapper,
-logic__6697: RocketTile__GCB0,
-logic__6921: VCU118RocketSystem__GC0,
-reg__239: VCU118RocketSystem__GC0,
-reg__427: RocketTile__GCB0,
-logic__4330: FPU__GB1,
-logic__7186: VCU118RocketSystem__GC0,
-logic__5999: RocketTile__GCB0,
-case__1626: tracking_wrapper,
-case__741: FPU__GB2,
-logic__7414: VCU118RocketSystem__GC0,
-case__1062: VCU118RocketSystem__GC0,
-reg__331: DCache,
-logic__6319: RocketTile__GCB0,
-datapath__549: VCU118RocketSystem__GC0,
-logic__8614: APBGpsBlock__GC0,
-reg__533: FPU__GB1,
-logic__3238: RocketTile__GCB0,
-logic__7760: VCU118RocketSystem__GC0,
-case__599: RocketTile__GCB0,
-logic__6696: RocketTile__GCB0,
-logic__8886: tracking_wrapper,
-reg__99: vcu118_rocket_top__GC0,
-muxpart__238: FPU__GB0,
-logic__6085: RocketTile__GCB0,
-logic__2005: VCU118RocketSystem__GC0,
-case__1562: tracking_wrapper,
-logic__2993: RocketTile__GCB0,
-logic__9388: APBGpsBlock__GC0,
-case__803: FPU__GB1,
-logic__6970: VCU118RocketSystem__GC0,
-case__405: VCU118RocketSystem__GC0,
-logic__7600: VCU118RocketSystem__GC0,
-logic__1737: VCU118RocketSystem__GC0,
-muxpart__154: vcu118_rocket_top__GC0,
-case__559: DCache,
-logic__3959: FPU__GB2,
-reg__1129: APBGpsBlock__GC0,
-logic__2216: DCache,
-case__1680: APBGpsBlock__GC0,
-muxpart__269: RocketTile__GCB0,
-muxpart__62: vcu118_rocket_top__GC0,
-datapath__143: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__1322: APBGpsBlock__GC0,
-reg__166: VCU118RocketSystem__GC0,
-logic__5624: RocketTile__GCB0,
-logic__9392: APBGpsBlock__GC0,
-muxpart__88: vcu118_rocket_top__GC0,
-muxpart__50: vcu118_rocket_top__GC0,
-logic__6931: VCU118RocketSystem__GC0,
-case__1541: tracking_wrapper,
-case__1566: tracking_wrapper,
-logic__1419: VCU118RocketSystem__GC0,
-logic__6199: RocketTile__GCB0,
-reg__700: RocketTile__GCB0,
-logic__7674: VCU118RocketSystem__GC0,
-case__1049: VCU118RocketSystem__GC0,
-logic__2404: DCache,
-case__1289: APBGpsBlock__GC0,
-muxpart__257: FPU__GB1,
-logic__9310: tracking_wrapper,
-Queue2_TLBundleD_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__3003: RocketTile__GCB0,
-reg__1004: VCU118RocketSystem__GC0,
-logic__1839: VCU118RocketSystem__GC0,
-case__1390: APBGpsBlock__GC0,
-logic__7564: VCU118RocketSystem__GC0,
-logic__1583: VCU118RocketSystem__GC0,
-logic__3600: FPU__GB2, FPU__GB1,
-case__643: FPU__GB1,
-logic__1426: VCU118RocketSystem__GC0,
-datapath__468: RocketTile__GCB0,
-logic__9014: tracking_wrapper,
-datapath__156: VCU118RocketSystem__GC0,
-logic__5117: FPU__GB1,
-reg__1315: tracking_wrapper,
-logic__7095: VCU118RocketSystem__GC0,
-case__1193: VCU118RocketSystem__GC0,
-logic__7925: VCU118RocketSystem__GC0,
-case__172: vcu118_rocket_top__GC0,
-case__617: RocketTile__GCB0,
-reg__87: vcu118_rocket_top__GC0,
-reg__246: VCU118RocketSystem__GC0,
-case__1040: VCU118RocketSystem__GC0,
-reg__603: FPU__GB1,
-datapath__718: tracking_wrapper,
-logic__891: VCU118RocketSystem__GC0,
-logic__7533: VCU118RocketSystem__GC0,
-logic__1164: VCU118RocketSystem__GC0,
-TLWidthWidget8_1: VCU118RocketSystem__GC0, RocketTile__GCB0,
-reg__285: VCU118RocketSystem__GC0,
-logic__8616: APBGpsBlock__GC0,
-logic__5600: RocketTile__GCB0,
-logic__5305: RocketTile__GCB0,
-reg__93: vcu118_rocket_top__GC0,
-case__1127: VCU118RocketSystem__GC0,
-logic__624: vcu118_rocket_top__GC0,
-datapath__398: FPU__GB2,
-logic__295: vcu118_rocket_top__GC0,
-logic__7306: VCU118RocketSystem__GC0,
-logic__2006: VCU118RocketSystem__GC0,
-reg__410: RocketTile__GCB0,
-logic__182: vcu118_rocket_top__GC0,
-reg__134: VCU118RocketSystem__GC0,
-muxpart__304: APBGpsBlock__GC0,
-logic__3048: RocketTile__GCB0,
-logic__7410: VCU118RocketSystem__GC0,
-reg__1226: tracking_wrapper,
-logic__2701: DCache,
-logic__2838: DCache,
-logic__4887: FPU__GB2,
-muxpart__101: vcu118_rocket_top__GC0,
-case__41: vcu118_rocket_top__GC0,
-case__444: VCU118RocketSystem__GC0,
-case__870: RocketTile__GCB0,
-case__683: FPU__GB2,
-case__662: FPU__GB2, FPU__GB1,
-datapath__300: RocketTile__GCB0,
-datapath__20: vcu118_rocket_top__GC0,
-case__1162: VCU118RocketSystem__GC0,
-logic__5610: RocketTile__GCB0,
-logic__6469: RocketTile__GCB0,
-datapath__683: tracking_wrapper,
-logic__5043: FPU__GB1,
-case__1675: APBGpsBlock__GC0,
-case__322: VCU118RocketSystem__GC0,
-logic__3790: FPU__GB2,
-datapath__503: VCU118RocketSystem__GC0,
-case__1334: APBGpsBlock__GC0,
-reg__220: VCU118RocketSystem__GC0,
-case__343: VCU118RocketSystem__GC0,
-Queue1_TLBundleA_a29d32s7k1z2u: TLToAPB,
-case__122: vcu118_rocket_top__GC0,
-case__403: VCU118RocketSystem__GC0,
-logic__2965: RocketTile__GCB0,
-logic__4426: FPU__GB1,
-reg__436: RocketTile__GCB0,
-case__690: FPU__GB2,
-logic__4026: FPU__GB2,
-logic__7378: VCU118RocketSystem__GC0,
-logic__3447: FPU__GB1,
-logic__5649: RocketTile__GCB0,
-case__973: RocketTile__GCB0,
-case__321: VCU118RocketSystem__GC0,
-logic__8588: APBGpsBlock__GC0,
-reg__309: VCU118RocketSystem__GC0,
-logic__942: VCU118RocketSystem__GC0,
-case__829: RocketTile__GCB0,
-case__841: RocketTile__GCB0,
-logic__4777: FPU__GB2,
-datapath__626: APBGpsBlock__GC0,
-logic__6538: RocketTile__GCB0,
-logic__514: vcu118_rocket_top__GC0,
-logic__4514: FPU__GB1,
-case__710: FPU__GB1,
-logic__6174: RocketTile__GCB0,
-logic__4108: FPU__GB2,
-case__1248: VCU118RocketSystem__GC0,
-logic__7497: VCU118RocketSystem__GC0,
-logic__9177: tracking_wrapper,
-reg__863: VCU118RocketSystem__GC0,
-logic__4384: FPU__GB1,
-logic__4068: FPU__GB2,
-datapath__347: FPU__GB2,
-case__1389: APBGpsBlock__GC0,
-reg__1230: tracking_wrapper,
-logic__6741: VCU118RocketSystem__GC0,
-datapath__489: RocketTile__GCB0,
-case__719: FPU__GB1,
-case__827: RocketTile__GCB0,
-logic__3054: RocketTile__GCB0,
-logic__3515: FPU__GB1,
-logic__9261: tracking_wrapper,
-TLBuffer_a32d64s1k1z4u: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-MulAddRecFNPipe_l2_e8_s24: FPU__GB1,
-case__478: VCU118RocketSystem__GC0,
-datapath__464: RocketTile__GCB0,
-logic__5033: FPU__GB1,
-logic__762: vcu118_rocket_top__GC0,
-logic__5648: RocketTile__GCB0,
-datapath__546: VCU118RocketSystem__GC0,
-logic__7710: VCU118RocketSystem__GC0,
-case__462: VCU118RocketSystem__GC0,
-datapath__157: VCU118RocketSystem__GC0,
-case__628: RocketTile__GCB0,
-logic__4596: FPU__GB2, FPU__GB1,
-logic__7394: VCU118RocketSystem__GC0,
-datapath__690: tracking_wrapper,
-case__166: vcu118_rocket_top__GC0,
-reg__539: FPU__GB1,
-logic__5990: RocketTile__GCB0,
-logic__4724: FPU__GB2,
-logic__4900: FPU__GB2,
-logic__3140: RocketTile__GCB0,
-datapath__167: VCU118RocketSystem__GC0,
-logic__6533: RocketTile__GCB0,
-logic__1747: VCU118RocketSystem__GC0,
-logic__2191: DCache,
-case__1224: VCU118RocketSystem__GC0,
-logic__2021: VCU118RocketSystem__GC0,
-logic__5935: RocketTile__GCB0,
-logic__7498: VCU118RocketSystem__GC0,
-muxpart__47: vcu118_rocket_top__GC0,
-muxpart__4: vcu118_rocket_top__GC0,
-reg__968: VCU118RocketSystem__GC0,
-case__1507: APBGpsBlock__GC0,
-RocketTile__GCB0: RocketTile__GCB0,
-logic__6841: VCU118RocketSystem__GC0,
-Arbiter4_DCacheDataReq: DCache,
-case__792: FPU__GB1,
-logic__5933: RocketTile__GCB0,
-dual_port_bram__parameterized0: APBGpsBlock__GC0,
-reg__1217: tracking_wrapper,
-logic__2727: DCache,
-datapath__502: VCU118RocketSystem__GC0,
-logic__1556: VCU118RocketSystem__GC0,
-logic__1180: VCU118RocketSystem__GC0,
-logic__5518: RocketTile__GCB0,
-logic__1302: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-rocket_bscan_dmi_tunnel: vcu118_rocket_top__GC0,
-logic__8780: APBGpsBlock__GC0,
-datapath__487: RocketTile__GCB0,
-logic__4832: FPU__GB2,
-logic__8620: APBGpsBlock__GC0,
-reg__752: RocketTile__GCB0,
-reg__355: DCache,
-reg__1178: APBGpsBlock__GC0,
-reg__591: FPU__GB2,
-case__694: FPU__GB2,
-case__1688: TLToAPB,
-logic__5751: RocketTile__GCB0,
-reg__1076: APBGpsBlock__GC0,
-case__939: RocketTile__GCB0,
-logic__6812: VCU118RocketSystem__GC0,
-datapath__477: RocketTile__GCB0,
-logic__5932: RocketTile__GCB0,
-logic__1981: VCU118RocketSystem__GC0,
-case__1426: APBGpsBlock__GC0,
-logic__9211: tracking_wrapper,
-reg__520: FPU__GB2,
-logic__432: vcu118_rocket_top__GC0,
-datapath__359: FPU__GB2,
-case__438: VCU118RocketSystem__GC0,
-logic__6547: RocketTile__GCB0,
-case__980: RocketTile__GCB0,
-logic__2937: DCache,
-case__464: VCU118RocketSystem__GC0,
-logic__8119: VCU118RocketSystem__GC0,
-logic__5393: RocketTile__GCB0,
-logic__5611: RocketTile__GCB0,
-logic__8017: VCU118RocketSystem__GC0,
-logic__8829: tracking_wrapper,
-datapath__632: APBGpsBlock__GC0,
-logic__6124: RocketTile__GCB0,
-logic__5221: RocketTile__GCB0,
-logic__3027: RocketTile__GCB0,
-datapath__581: APBGpsBlock__GC0,
-logic__4175: FPU__GB1,
-logic__5288: RocketTile__GCB0,
-case__905: RocketTile__GCB0,
-case__1081: VCU118RocketSystem__GC0,
-case__1283: APBGpsBlock__GC0,
-datapath__379: FPU__GB1,
-keep__15: vcu118_rocket_top__GC0,
-reg__1014: VCU118RocketSystem__GC0,
-datapath__678: tracking_wrapper,
-case__1672: APBGpsBlock__GC0,
-logic__3463: FPU__GB1,
-reg__886: VCU118RocketSystem__GC0,
-reg__271: VCU118RocketSystem__GC0,
-case__1522: tracking_wrapper,
-logic__2097: RocketTile__GCB0,
-datapath__257: VCU118RocketSystem__GC0,
-logic__5615: RocketTile__GCB0,
-case__515: DCache,
-reg__989: VCU118RocketSystem__GC0,
-logic__4737: FPU__GB2,
-logic__7807: VCU118RocketSystem__GC0,
-reg__1053: VCU118RocketSystem__GC0,
-logic__7362: VCU118RocketSystem__GC0,
-reg__929: VCU118RocketSystem__GC0,
-TLFIFOFixer: VCU118RocketSystem__GC0,
-case__1033: VCU118RocketSystem__GC0,
-logic__1751: VCU118RocketSystem__GC0,
-logic__5871: RocketTile__GCB0,
-logic__152: vcu118_rocket_top__GC0,
-logic__2809: DCache,
-case__911: RocketTile__GCB0,
-reg__900: VCU118RocketSystem__GC0,
-case__1689: TLToAPB,
-muxpart__253: FPU__GB2,
-case__49: vcu118_rocket_top__GC0,
-logic__7373: VCU118RocketSystem__GC0,
-logic__1611: VCU118RocketSystem__GC0,
-logic__4967: FPU__GB2,
-case__393: VCU118RocketSystem__GC0,
-dsp48e2__7: APBGpsBlock__GC0,
-muxpart__214: FPU__GB0,
-datapath__624: APBGpsBlock__GC0,
-logic__2202: DCache,
-logic__145: vcu118_rocket_top__GC0,
-logic__6887: VCU118RocketSystem__GC0,
-logic__4189: FPU__GB1,
-logic__4435: FPU__GB1,
-logic__5722: RocketTile__GCB0,
-reg__943: VCU118RocketSystem__GC0,
-reg__1249: tracking_wrapper,
-logic__3552: FPU__GB1,
-logic__6736: TilePRCIDomain__GC0,
-datapath__556: APBGpsBlock__GC0,
-logic__7440: VCU118RocketSystem__GC0,
-logic__6793: VCU118RocketSystem__GC0,
-logic__8921: tracking_wrapper,
-case__295: VCU118RocketSystem__GC0,
-case__250: VCU118RocketSystem__GC0,
-datapath__365: FPU__GB2,
-logic__7692: VCU118RocketSystem__GC0,
-logic__867: VCU118RocketSystem__GC0,
-logic__4828: FPU__GB2,
-case__596: RocketTile__GCB0,
-datapath__436: RocketTile__GCB0,
-reg__1161: APBGpsBlock__GC0,
-muxpart__194: FPU__GB0,
-datapath__671: tracking_wrapper,
-datapath__182: VCU118RocketSystem__GC0,
-logic__1085: VCU118RocketSystem__GC0,
-logic__5277: RocketTile__GCB0,
-logic__5998: RocketTile__GCB0,
-datapath__394: FPU__GB2,
-case__894: RocketTile__GCB0,
-logic__8625: APBGpsBlock__GC0,
-reg__234: VCU118RocketSystem__GC0,
-logic__4804: FPU__GB2,
-reg__445: RocketTile__GCB0,
-logic__1310: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__495: vcu118_rocket_top__GC0,
-logic__1613: VCU118RocketSystem__GC0,
-logic__9428: APBGpsBlock__GC0,
-code_loop_discriminator: tracking_wrapper,
-logic__2773: DCache,
-case__383: VCU118RocketSystem__GC0,
-keep__11: tracking_wrapper,
-ram_2x115: TilePRCIDomain__GC0,
-case__1364: APBGpsBlock__GC0,
-logic__2637: DCache,
-logic__1357: VCU118RocketSystem__GC0,
-reg__1133: APBGpsBlock__GC0,
-TLBuffer_a32d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__9347: tracking_wrapper,
-case__1498: APBGpsBlock__GC0,
-datapath__512: VCU118RocketSystem__GC0,
-logic__1272: VCU118RocketSystem__GC0,
-logic__4820: FPU__GB2,
-logic__5522: RocketTile__GCB0,
-reg__1339: tracking_wrapper,
-logic__4813: FPU__GB2,
-logic__5432: RocketTile__GCB0,
-logic__1949: VCU118RocketSystem__GC0,
-logic__3539: FPU__GB1,
-logic__4434: FPU__GB1,
-logic__1054: VCU118RocketSystem__GC0,
-logic__2078: RocketTile__GCB0,
-logic__7655: VCU118RocketSystem__GC0,
-AsyncQueueSink_TLBundleD_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-reg__213: VCU118RocketSystem__GC0,
-datapath__98: VCU118RocketSystem__GC0,
-reg__1098: APBGpsBlock__GC0,
-datapath__43: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-muxpart__246: FPU__GB0,
-logic__8002: VCU118RocketSystem__GC0,
-datapath__704: tracking_wrapper,
-logic__5035: FPU__GB1,
-logic__521: vcu118_rocket_top__GC0,
-counter__7: VCU118RocketSystem__GC0,
-logic__7513: VCU118RocketSystem__GC0,
-reg__924: VCU118RocketSystem__GC0,
-case__375: VCU118RocketSystem__GC0,
-afe_top: APBGpsBlock__GC0,
-logic__8793: tracking_wrapper,
-reg__1239: tracking_wrapper,
-reg__76: vcu118_rocket_top__GC0,
-logic__1521: VCU118RocketSystem__GC0,
-reg__492: FPU__GB1,
-case__170: vcu118_rocket_top__GC0,
-muxpart__273: VCU118RocketSystem__GC0,
-case__603: RocketTile__GCB0,
-logic__811: VCU118RocketSystem__GC0,
-reg__734: RocketTile__GCB0,
-logic__485: vcu118_rocket_top__GC0,
-reg__925: VCU118RocketSystem__GC0,
-logic__6598: RocketTile__GCB0,
-datapath__250: VCU118RocketSystem__GC0,
-case__344: VCU118RocketSystem__GC0,
-logic__3279: RocketTile__GCB0,
-logic__7771: VCU118RocketSystem__GC0,
-dsp48e2__6: APBGpsBlock__GC0,
-reg__1352: tracking_wrapper,
-muxpart__235: FPU__GB0,
-reg__726: RocketTile__GCB0,
-logic__910: VCU118RocketSystem__GC0,
-case__231: VCU118RocketSystem__GC0,
-reg__717: RocketTile__GCB0,
-logic__3546: FPU__GB1,
-logic__1582: VCU118RocketSystem__GC0,
-case__258: VCU118RocketSystem__GC0,
-case__1420: APBGpsBlock__GC0,
-reg__585: FPU__GB2,
-case__887: RocketTile__GCB0,
-logic__7358: VCU118RocketSystem__GC0,
-logic__66: vcu118_rocket_top__GC0,
-logic__5253: RocketTile__GCB0,
-reg__485: FPU__GB1,
-datapath__390: FPU__GB2, FPU__GB1,
-logic__4424: FPU__GB1,
-logic__3867: FPU__GB2,
-logic__3562: FPU__GB2, FPU__GB1,
-reg__333: DCache,
-logic__3423: FPU__GB1,
-case__1336: APBGpsBlock__GC0,
-logic__7273: VCU118RocketSystem__GC0,
-logic__3603: FPU__GB2, FPU__GB1,
-case__181: vcu118_rocket_top__GC0,
-logic__6663: RocketTile__GCB0,
-reg__1017: VCU118RocketSystem__GC0,
-case__1392: APBGpsBlock__GC0,
-logic__5067: FPU__GB2,
-logic__3494: FPU__GB1,
-logic__1246: VCU118RocketSystem__GC0,
-logic__5195: RocketTile__GCB0,
-case__697: FPU__GB2,
-muxpart__278: VCU118RocketSystem__GC0,
-datapath__495: TilePRCIDomain__GC0,
-logic__3226: RocketTile__GCB0,
-muxpart__85: vcu118_rocket_top__GC0,
-datapath__234: VCU118RocketSystem__GC0,
-case__1152: VCU118RocketSystem__GC0,
-logic__2135: RocketTile__GCB0,
-logic__4454: FPU__GB1,
-datapath__344: FPU__GB2,
-logic__2646: DCache,
-case__604: RocketTile__GCB0,
-TLFragmenter_FPGAUART: VCU118RocketSystem__GC0,
-logic__5668: RocketTile__GCB0,
-case__293: VCU118RocketSystem__GC0,
-reg__507: FPU__GB1,
-ram_2x120: VCU118RocketSystem__GC0,
-case__259: VCU118RocketSystem__GC0,
-reg__346: DCache,
-case__1473: APBGpsBlock__GC0,
-logic__422: vcu118_rocket_top__GC0,
-logic__3611: FPU__GB2, FPU__GB1,
-reg__523: FPU__GB2,
-muxpart__250: FPU__GB0,
-logic__6915: VCU118RocketSystem__GC0,
-logic__3741: FPU__GB2,
-logic__6747: VCU118RocketSystem__GC0,
-logic__7912: VCU118RocketSystem__GC0,
-case__1165: VCU118RocketSystem__GC0,
-logic__7286: VCU118RocketSystem__GC0,
-reg__730: RocketTile__GCB0,
-datapath__269: DCache,
-case__126: vcu118_rocket_top__GC0,
-datapath__601: APBGpsBlock__GC0,
-logic__2369: DCache,
-logic__6338: RocketTile__GCB0,
-reg__1156: APBGpsBlock__GC0,
-logic__9306: tracking_wrapper,
-reg__94: vcu118_rocket_top__GC0,
-logic__3558: FPU__GB1,
-reg__1254: tracking_wrapper,
-reg__1272: tracking_wrapper,
-logic__6729: RocketTile__GCB0,
-reg__192: VCU118RocketSystem__GC0,
-reg__729: RocketTile__GCB0,
-case__875: RocketTile__GCB0,
-case__968: RocketTile__GCB0,
-logic__3975: FPU__GB2,
-logic__6122: RocketTile__GCB0,
-case__20: vcu118_rocket_top__GC0,
-datapath__411: FPU__GB2,
-logic__6606: RocketTile__GCB0,
-Queue2_TLBundleA_a32d64s2k1z3u: TilePRCIDomain__GC0,
-logic__4824: FPU__GB2,
-case__757: FPU__GB2,
-reg__299: VCU118RocketSystem__GC0,
-logic__6619: RocketTile__GCB0,
-logic__2724: DCache,
-logic__5867: RocketTile__GCB0,
-case__365: VCU118RocketSystem__GC0,
-logic__2107: RocketTile__GCB0,
-logic__5329: RocketTile__GCB0,
-logic__4496: FPU__GB1,
-logic__8605: APBGpsBlock__GC0,
-logic__7393: VCU118RocketSystem__GC0,
-PTW: RocketTile__GCB0,
-datapath__565: APBGpsBlock__GC0,
-case__716: FPU__GB1,
-datapath__448: RocketTile__GCB0,
-logic__7856: VCU118RocketSystem__GC0,
-reg__139: VCU118RocketSystem__GC0,
-reg__489: FPU__GB1,
-reg__599: FPU__GB2,
-logic__7236: VCU118RocketSystem__GC0,
-logic__2821: DCache,
-datapath__386: FPU__GB2, FPU__GB1,
-reg__1213: tracking_wrapper,
-logic__2344: DCache,
-logic__2061: RocketTile__GCB0,
-reg__1301: tracking_wrapper,
-muxpart__11: vcu118_rocket_top__GC0,
-case__1099: VCU118RocketSystem__GC0,
-case__1012: VCU118RocketSystem__GC0,
-logic__1973: VCU118RocketSystem__GC0,
-extram__7: APBGpsBlock__GC0,
-reg__588: FPU__GB2,
-logic__2115: RocketTile__GCB0,
-logic__4606: FPU__GB2, FPU__GB1,
-datapath__351: FPU__GB2,
-logic__4032: FPU__GB2,
-logic__7384: VCU118RocketSystem__GC0,
-muxpart__33: vcu118_rocket_top__GC0,
-case__621: RocketTile__GCB0,
-muxpart__177: DCache,
-AsyncQueueSource_TLBundleA_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-datapath__86: VCU118RocketSystem__GC0,
-reg__1403: TLToAPB,
-logic__3284: RocketTile__GCB0,
-muxpart__48: vcu118_rocket_top__GC0,
-counter__18: APBGpsBlock__GC0,
-logic__3760: FPU__GB2,
-counter__8: VCU118RocketSystem__GC0,
-logic__1165: VCU118RocketSystem__GC0,
-logic__5104: FPU__GB1,
-logic__7202: VCU118RocketSystem__GC0,
-case__1565: tracking_wrapper,
-reg__444: RocketTile__GCB0,
-logic__7496: VCU118RocketSystem__GC0,
-logic__5750: RocketTile__GCB0,
-logic__6874: VCU118RocketSystem__GC0,
-APBGpsBlock__GC0: APBGpsBlock__GC0,
-logic__5743: RocketTile__GCB0,
-logic__1608: VCU118RocketSystem__GC0,
-datapath__145: VCU118RocketSystem__GC0,
-logic__6828: VCU118RocketSystem__GC0,
-logic__5559: RocketTile__GCB0,
-logic__5929: RocketTile__GCB0,
-case__774: FPU__GB1,
-datapath__395: FPU__GB2,
-muxpart__219: FPU__GB0,
-datapath__473: RocketTile__GCB0,
-logic__209: vcu118_rocket_top__GC0,
-muxpart__96: vcu118_rocket_top__GC0,
-reg__635: FPU__GB1,
-logic__2048: VCU118RocketSystem__GC0,
-logic__7697: VCU118RocketSystem__GC0,
-case__8: vcu118_rocket_top__GC0,
-logic__3884: FPU__GB2,
-reg: vcu118_rocket_top__GC0,
-case__665: FPU__GB2,
-logic__9366: tracking_wrapper,
-logic__4063: FPU__GB2,
-logic__13: vcu118_rocket_top__GC0,
-logic__3133: RocketTile__GCB0,
-reg__273: VCU118RocketSystem__GC0,
-logic__4998: FPU__GB1,
-reg__754: RocketTile__GCB0,
-case__445: VCU118RocketSystem__GC0,
-logic__3331: FPU__GB1,
-reg__5: vcu118_rocket_top__GC0,
-reg__921: VCU118RocketSystem__GC0,
-case__253: VCU118RocketSystem__GC0,
-logic__7140: VCU118RocketSystem__GC0,
-IntSyncCrossingSource_n1x1: VCU118RocketSystem__GC0,
-reg__1212: tracking_wrapper,
-DivSqrtRecFN_small: FPU__GB2,
-logic__4383: FPU__GB1,
-case__1594: tracking_wrapper,
-reg__1039: VCU118RocketSystem__GC0,
-butterfly__parameterized1: APBGpsBlock__GC0,
-logic__6081: RocketTile__GCB0,
-logic__5949: RocketTile__GCB0,
-case__380: VCU118RocketSystem__GC0,
-logic__1669: VCU118RocketSystem__GC0,
-reg__710: RocketTile__GCB0,
-PMAChecker: RocketTile__GCB0, DCache,
-logic__9450: TLToAPB,
-logic__1141: VCU118RocketSystem__GC0,
-reg__395: RocketTile__GCB0,
-case__1655: tracking_wrapper,
-reg__693: RocketTile__GCB0,
-case__1605: tracking_wrapper,
-logic__4598: FPU__GB2, FPU__GB1,
-reg__550: FPU__GB1,
-logic__7356: VCU118RocketSystem__GC0,
-logic__877: VCU118RocketSystem__GC0,
-LF_code: tracking_wrapper,
-case__1240: VCU118RocketSystem__GC0,
-logic__9234: tracking_wrapper,
-case__512: DCache,
-logic__8722: APBGpsBlock__GC0,
-keep__16: vcu118_rocket_top__GC0,
-reg__598: FPU__GB2,
-case__958: RocketTile__GCB0,
-logic__1925: VCU118RocketSystem__GC0,
-logic__7121: VCU118RocketSystem__GC0,
-logic__8176: VCU118RocketSystem__GC0,
-logic__7390: VCU118RocketSystem__GC0,
-reg__340: DCache,
-logic__3994: FPU__GB2,
-case__1034: VCU118RocketSystem__GC0,
-reg__435: RocketTile__GCB0,
-logic__2811: DCache,
-reg__78: vcu118_rocket_top__GC0,
-reg__95: vcu118_rocket_top__GC0,
-logic__7131: VCU118RocketSystem__GC0,
-logic__7208: VCU118RocketSystem__GC0,
-reg__801: RocketTile__GCB0,
-logic__8184: VCU118RocketSystem__GC0,
-logic__7129: VCU118RocketSystem__GC0,
-datapath__479: RocketTile__GCB0,
-logic__5353: RocketTile__GCB0,
-case__358: VCU118RocketSystem__GC0,
-reg__423: RocketTile__GCB0,
-reg__851: TilePRCIDomain__GC0,
-case__145: vcu118_rocket_top__GC0,
-reg__338: DCache,
-logic__7118: VCU118RocketSystem__GC0,
-logic__4079: FPU__GB2,
-logic__3745: FPU__GB2,
-datapath__564: APBGpsBlock__GC0,
-logic__3536: FPU__GB1,
-reg__161: VCU118RocketSystem__GC0,
-reg__581: FPU__GB2,
-logic__6833: VCU118RocketSystem__GC0,
-logic__4895: FPU__GB2,
-datapath__726: TLToAPB,
-logic__6657: RocketTile__GCB0,
-logic__3105: RocketTile__GCB0,
-case__73: vcu118_rocket_top__GC0,
-case__1202: VCU118RocketSystem__GC0,
-case__237: VCU118RocketSystem__GC0,
-logic__3039: RocketTile__GCB0,
-case__1208: VCU118RocketSystem__GC0,
-logic__1948: VCU118RocketSystem__GC0,
-logic__5942: RocketTile__GCB0,
-logic__3332: FPU__GB1,
-logic__7381: VCU118RocketSystem__GC0,
-reg__35: vcu118_rocket_top__GC0,
-logic__1260: VCU118RocketSystem__GC0,
-logic__8850: tracking_wrapper,
-logic__7295: VCU118RocketSystem__GC0,
-reg__403: RocketTile__GCB0,
-logic__7342: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_sbus_to_bus_named_cbus: VCU118RocketSystem__GC0,
-logic__290: vcu118_rocket_top__GC0,
-reg__36: vcu118_rocket_top__GC0,
-datapath__74: VCU118RocketSystem__GC0,
-logic__4230: FPU__GB1,
-logic__7265: VCU118RocketSystem__GC0,
-logic__1019: VCU118RocketSystem__GC0,
-logic__5955: RocketTile__GCB0,
-logic__3285: RocketTile__GCB0,
-case__160: vcu118_rocket_top__GC0,
-logic__17: vcu118_rocket_top__GC0,
-logic__3168: RocketTile__GCB0,
-reg__373: RocketTile__GCB0,
-logic__2226: DCache,
-logic__8346: APBGpsBlock__GC0,
-case__360: VCU118RocketSystem__GC0,
-dsp48e2: FPU__GB1,
-reg__97: vcu118_rocket_top__GC0,
-logic__2457: DCache,
-datapath__712: tracking_wrapper,
-logic__370: vcu118_rocket_top__GC0,
-reg__908: VCU118RocketSystem__GC0,
-logic__6147: RocketTile__GCB0,
-logic__6673: RocketTile__GCB0,
-datapath__437: RocketTile__GCB0,
-logic__344: vcu118_rocket_top__GC0,
-Queue2_TLBundleA_a14d64s2k1z4u: VCU118RocketSystem__GC0,
-logic__4688: FPU__GB2,
-reg__278: VCU118RocketSystem__GC0,
-logic__4891: FPU__GB2,
-case__1143: VCU118RocketSystem__GC0,
-reg__979: VCU118RocketSystem__GC0,
-reg__223: VCU118RocketSystem__GC0,
-logic__5089: FPU__GB1,
-logic__3781: FPU__GB2,
-logic__658: vcu118_rocket_top__GC0,
-logic__2829: DCache,
-reg__1281: tracking_wrapper,
-case__136: vcu118_rocket_top__GC0,
-case__760: FPU__GB2,
-logic__8506: APBGpsBlock__GC0,
-case__390: VCU118RocketSystem__GC0,
-logic__632: vcu118_rocket_top__GC0,
-case__36: vcu118_rocket_top__GC0,
-logic__8774: APBGpsBlock__GC0,
-reg__1363: tracking_wrapper,
-logic__4370: FPU__GB1,
-reg__79: vcu118_rocket_top__GC0,
-case__668: FPU__GB2,
-dual_port_bram: APBGpsBlock__GC0,
-logic__4516: FPU__GB1,
-logic__5923: RocketTile__GCB0,
-logic__6197: RocketTile__GCB0,
-logic__914: VCU118RocketSystem__GC0,
-reg__1205: APBGpsBlock__GC0,
-reg__769: RocketTile__GCB0,
-logic__8143: VCU118RocketSystem__GC0,
-logic__7709: VCU118RocketSystem__GC0,
-logic__1861: VCU118RocketSystem__GC0,
-reg__1348: tracking_wrapper,
-logic__4423: FPU__GB1,
-case__1013: VCU118RocketSystem__GC0,
-muxpart__359: tracking_wrapper,
-datapath__319: FPU__GB1,
-logic__4006: FPU__GB2,
-datapath__15: vcu118_rocket_top__GC0,
-logic__4274: FPU__GB1,
-reg__1094: APBGpsBlock__GC0,
-case__733: FPU__GB2, FPU__GB1,
-case__1319: APBGpsBlock__GC0,
-datapath__153: VCU118RocketSystem__GC0,
-datapath__563: APBGpsBlock__GC0,
-case__213: vcu118_rocket_top__GC0,
-logic__3506: FPU__GB1,
-logic__1460: VCU118RocketSystem__GC0,
-case__285: VCU118RocketSystem__GC0,
-reg__9: vcu118_rocket_top__GC0,
-logic__920: VCU118RocketSystem__GC0,
-reg__1233: tracking_wrapper,
-logic__3019: RocketTile__GCB0,
-case__351: VCU118RocketSystem__GC0,
-reg__337: DCache,
-logic__1533: VCU118RocketSystem__GC0,
-reg__935: VCU118RocketSystem__GC0,
-AsyncResetSynchronizerShiftReg_w1_d3_i0: VCU118RocketSystem__GC0,
-case__367: VCU118RocketSystem__GC0,
-datapath__577: APBGpsBlock__GC0,
-logic__4681: FPU__GB1,
-case__653: FPU__GB2, FPU__GB1,
-logic__1675: VCU118RocketSystem__GC0,
-reg__755: RocketTile__GCB0,
-logic__678: vcu118_rocket_top__GC0,
-datapath__447: RocketTile__GCB0,
-datapath__423: RocketTile__GCB0,
-datapath__262: VCU118RocketSystem__GC0,
-reg__194: VCU118RocketSystem__GC0,
-logic__5394: RocketTile__GCB0,
-logic__3907: FPU__GB2,
-reg__191: VCU118RocketSystem__GC0,
-reg__1214: tracking_wrapper,
-reg__531: FPU__GB1,
-logic__1524: VCU118RocketSystem__GC0,
-datapath__680: tracking_wrapper,
-case__699: FPU__GB2,
-case__966: RocketTile__GCB0,
-logic__132: vcu118_rocket_top__GC0,
-logic__4297: FPU__GB1,
-logic__2810: DCache,
-logic__8139: VCU118RocketSystem__GC0,
-datapath__656: APBGpsBlock__GC0,
-case__606: RocketTile__GCB0,
-logic__1023: VCU118RocketSystem__GC0,
-double_ff_syn__parameterized0: tracking_wrapper,
-logic__5059: FPU__GB1,
-logic__1398: VCU118RocketSystem__GC0,
-reg__1250: tracking_wrapper,
-RocketALU: RocketTile__GCB0,
-reg__390: RocketTile__GCB0,
-case__127: vcu118_rocket_top__GC0,
-reg__1127: APBGpsBlock__GC0,
-datapath__608: APBGpsBlock__GC0,
-reg__516: FPU__GB2,
-case__907: RocketTile__GCB0,
-logic__4624: FPU__GB2, FPU__GB1,
-case__878: RocketTile__GCB0,
-logic__5669: RocketTile__GCB0,
-logic__4179: FPU__GB1,
-logic__8687: APBGpsBlock__GC0,
-logic__8889: tracking_wrapper,
-logic__8429: APBGpsBlock__GC0,
-logic__1701: VCU118RocketSystem__GC0,
-case__1480: APBGpsBlock__GC0,
-logic__8197: VCU118RocketSystem__GC0,
-logic__4694: FPU__GB2,
-logic__2175: DCache,
-ClockCrossingReg_w55: VCU118RocketSystem__GC0,
-logic__1287: VCU118RocketSystem__GC0,
-reg__8: vcu118_rocket_top__GC0,
-case__176: vcu118_rocket_top__GC0,
-logic__3169: RocketTile__GCB0,
-case__1296: APBGpsBlock__GC0,
-counter__27: tracking_wrapper,
-logic__5293: RocketTile__GCB0,
-datapath__140: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__606: APBGpsBlock__GC0,
-reg__125: VCU118RocketSystem__GC0,
-logic__2264: DCache,
-logic__809: VCU118RocketSystem__GC0,
-logic__8128: VCU118RocketSystem__GC0,
-logic__7018: VCU118RocketSystem__GC0,
-reg__1362: tracking_wrapper,
-logic__409: vcu118_rocket_top__GC0,
-case__24: vcu118_rocket_top__GC0,
-Queue2_TLBundleD_a32d8s1k1z4u: VCU118RocketSystem__GC0,
-logic__5098: FPU__GB1,
-reg__201: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-case__817: RocketTile__GCB0,
-logic__2551: DCache,
-muxpart__9: vcu118_rocket_top__GC0,
-logic__2793: DCache,
-case__388: VCU118RocketSystem__GC0,
-counter__32: tracking_wrapper,
-muxpart__195: FPU__GB0,
-case__302: VCU118RocketSystem__GC0,
-logic__729: vcu118_rocket_top__GC0,
-logic__1818: VCU118RocketSystem__GC0,
-case__1484: APBGpsBlock__GC0,
-case__951: RocketTile__GCB0,
-logic__4522: FPU__GB1,
-case__271: VCU118RocketSystem__GC0,
-logic__6006: RocketTile__GCB0,
-case__1515: APBGpsBlock__GC0,
-case__762: FPU__GB2,
-reg__421: RocketTile__GCB0,
-reg__240: VCU118RocketSystem__GC0,
-logic__1219: VCU118RocketSystem__GC0,
-logic__6675: RocketTile__GCB0,
-logic__4942: FPU__GB2,
-case__404: VCU118RocketSystem__GC0,
-case__1330: APBGpsBlock__GC0,
-logic__4799: FPU__GB2,
-logic__442: vcu118_rocket_top__GC0,
-logic__5011: FPU__GB1,
-logic__4723: FPU__GB2,
-logic__5220: RocketTile__GCB0,
-reg__1313: tracking_wrapper,
-logic__7505: VCU118RocketSystem__GC0,
-logic__1346: VCU118RocketSystem__GC0,
-muxpart__270: RocketTile__GCB0,
-reg__945: VCU118RocketSystem__GC0,
-addsub: APBGpsBlock__GC0,
-reg__663: RocketTile__GCB0,
-case__26: vcu118_rocket_top__GC0,
-reg__1231: tracking_wrapper,
-logic__1307: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__3877: FPU__GB2,
-reg__114: VCU118RocketSystem__GC0,
-reg__1343: tracking_wrapper,
-logic__4498: FPU__GB1,
-case__1585: tracking_wrapper,
-logic__5490: RocketTile__GCB0,
-logic__7919: VCU118RocketSystem__GC0,
-logic__1215: VCU118RocketSystem__GC0,
-datapath__309: RocketTile__GCB0,
-logic__253: vcu118_rocket_top__GC0,
-logic__6597: RocketTile__GCB0,
-logic__9276: tracking_wrapper,
-datapath__311: RocketTile__GCB0,
-reg__864: VCU118RocketSystem__GC0,
-logic__5326: RocketTile__GCB0,
-logic__3812: FPU__GB2,
-muxpart__14: vcu118_rocket_top__GC0,
-datapath__567: APBGpsBlock__GC0,
-case__705: FPU__GB1,
-reg__1: vcu118_rocket_top__GC0,
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0: VCU118RocketSystem__GC0,
-logic__956: VCU118RocketSystem__GC0,
-datapath__615: APBGpsBlock__GC0,
-logic__3002: RocketTile__GCB0,
-reg__759: RocketTile__GCB0,
-reg__461: FPU__GB0,
-muxpart__32: vcu118_rocket_top__GC0,
-datapath__174: VCU118RocketSystem__GC0,
-logic__4350: FPU__GB1,
-logic__901: VCU118RocketSystem__GC0,
-logic__1429: VCU118RocketSystem__GC0,
-logic__3038: RocketTile__GCB0,
-logic__6807: VCU118RocketSystem__GC0,
-logic__5887: RocketTile__GCB0,
-reg__1329: tracking_wrapper,
-logic__8788: APBGpsBlock__GC0,
-muxpart__75: vcu118_rocket_top__GC0,
-logic__9137: tracking_wrapper,
-logic__7869: VCU118RocketSystem__GC0,
-case__1290: APBGpsBlock__GC0,
-case__1056: VCU118RocketSystem__GC0,
-extladd: RocketTile__GCB0,
-datapath__110: VCU118RocketSystem__GC0,
-reg__1063: VCU118RocketSystem__GC0,
-logic__7969: VCU118RocketSystem__GC0,
-logic__2712: DCache,
-case__739: FPU__GB2,
-datapath__481: RocketTile__GCB0,
-reg__1068: APBGpsBlock__GC0, tracking_wrapper,
-case__79: vcu118_rocket_top__GC0,
-logic__674: vcu118_rocket_top__GC0,
-logic__7352: VCU118RocketSystem__GC0,
-logic__2961: RocketTile__GCB0,
-logic__2171: DCache,
-logic__4431: FPU__GB1,
-case__399: VCU118RocketSystem__GC0,
-logic__3409: FPU__GB1,
-case__1421: APBGpsBlock__GC0,
-case__1523: tracking_wrapper,
-case__1483: APBGpsBlock__GC0,
-datapath__78: VCU118RocketSystem__GC0,
-logic__4904: FPU__GB2,
-logic__9457: TLToAPB,
-logic__2180: DCache,
-logic__2584: DCache,
-logic__229: vcu118_rocket_top__GC0,
-logic__5937: RocketTile__GCB0,
-case__200: vcu118_rocket_top__GC0,
-reg__288: VCU118RocketSystem__GC0,
-logic__2184: DCache,
-datapath__21: vcu118_rocket_top__GC0,
-logic__6745: VCU118RocketSystem__GC0,
-logic__3408: FPU__GB1,
-logic__4414: FPU__GB1,
-logic__953: VCU118RocketSystem__GC0,
-muxpart__64: vcu118_rocket_top__GC0,
-logic__7413: VCU118RocketSystem__GC0,
-logic__2830: DCache,
-logic__2045: VCU118RocketSystem__GC0,
-logic__4675: FPU__GB1,
-datapath__709: tracking_wrapper,
-logic__6198: RocketTile__GCB0,
-case__839: RocketTile__GCB0,
-case__1674: APBGpsBlock__GC0,
-case__199: vcu118_rocket_top__GC0,
-muxpart__35: vcu118_rocket_top__GC0,
-logic__8589: APBGpsBlock__GC0,
-case__1476: APBGpsBlock__GC0,
-reg__1253: tracking_wrapper,
-datapath__381: FPU__GB1,
-reg__643: FPU__GB1,
-logic__8423: APBGpsBlock__GC0,
-logic__6544: RocketTile__GCB0,
-case__1019: VCU118RocketSystem__GC0,
-case__1291: APBGpsBlock__GC0,
-reg__264: VCU118RocketSystem__GC0,
-datapath__578: APBGpsBlock__GC0,
-muxpart__232: FPU__GB0,
-logic__1509: VCU118RocketSystem__GC0,
-logic__2291: DCache,
-reg__198: VCU118RocketSystem__GC0,
-logic__804: VCU118RocketSystem__GC0,
-sync: tracking_wrapper,
-logic__9219: tracking_wrapper,
-logic__2518: RocketTile__GCB0, DCache,
-logic__5741: RocketTile__GCB0,
-case__535: DCache,
-muxpart__202: FPU__GB0,
-logic__2815: DCache,
-logic__1280: VCU118RocketSystem__GC0,
-case__1678: APBGpsBlock__GC0,
-logic__7392: VCU118RocketSystem__GC0,
-logic__917: VCU118RocketSystem__GC0,
-case__955: RocketTile__GCB0,
-case__953: RocketTile__GCB0,
-logic__4513: FPU__GB1,
-reg__1366: tracking_wrapper,
-logic__5962: RocketTile__GCB0,
-logic__1031: VCU118RocketSystem__GC0,
-logic__6575: RocketTile__GCB0,
-logic__5749: RocketTile__GCB0,
-logic__4905: FPU__GB2,
-logic__5355: RocketTile__GCB0,
-reg__1122: APBGpsBlock__GC0,
-logic__853: VCU118RocketSystem__GC0,
-counter__20: APBGpsBlock__GC0,
-case__1107: VCU118RocketSystem__GC0,
-logic__4628: FPU__GB2, FPU__GB1,
-reg__80: vcu118_rocket_top__GC0,
-logic__7982: VCU118RocketSystem__GC0,
-logic__5156: FPU__GB1,
-logic__1512: VCU118RocketSystem__GC0,
-logic__5034: FPU__GB1,
-ram_2x77: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__4336: FPU__GB1,
-logic__5103: FPU__GB1,
-logic__1734: VCU118RocketSystem__GC0,
-logic__4138: FPU__GB1,
-case__448: VCU118RocketSystem__GC0,
-logic__7436: VCU118RocketSystem__GC0,
-reg__1407: vcu118_rocket_top__GC0,
-case__243: VCU118RocketSystem__GC0,
-logic__5519: RocketTile__GCB0,
-case__14: vcu118_rocket_top__GC0,
-reg__1386: tracking_wrapper,
-reg__845: RocketTile__GCB0,
-case__273: VCU118RocketSystem__GC0,
-logic__3206: RocketTile__GCB0,
-logic__1676: VCU118RocketSystem__GC0,
-reg__629: FPU__GB1,
-datapath__44: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__52: VCU118RocketSystem__GC0,
-reg__728: RocketTile__GCB0,
-case__568: RocketTile__GCB0,
-case__47: vcu118_rocket_top__GC0,
-logic__52: vcu118_rocket_top__GC0,
-logic__6857: VCU118RocketSystem__GC0,
-case__287: VCU118RocketSystem__GC0,
-logic__2174: DCache,
-logic__5023: FPU__GB2,
-logic__4726: FPU__GB2,
-logic__1440: VCU118RocketSystem__GC0,
-case__965: RocketTile__GCB0,
-logic__1961: VCU118RocketSystem__GC0,
-reg__397: RocketTile__GCB0,
-case__1597: tracking_wrapper,
-logic__2640: DCache,
-logic__6774: VCU118RocketSystem__GC0,
-reg__1081: APBGpsBlock__GC0,
-logic__4105: FPU__GB2,
-reg__543: FPU__GB1,
-logic__3813: FPU__GB2,
-case__1474: APBGpsBlock__GC0,
-reg__306: VCU118RocketSystem__GC0,
-logic__5497: RocketTile__GCB0,
-logic__5169: FPU__GB1,
-logic__6529: RocketTile__GCB0,
-case__843: RocketTile__GCB0,
-reg__1325: tracking_wrapper,
-logic__8847: tracking_wrapper,
-logic__5896: RocketTile__GCB0,
-logic__7979: VCU118RocketSystem__GC0,
-logic__1964: VCU118RocketSystem__GC0,
-logic__1005: VCU118RocketSystem__GC0,
-logic__648: vcu118_rocket_top__GC0,
-case__1001: VCU118RocketSystem__GC0,
-logic__6481: RocketTile__GCB0,
-logic__8426: APBGpsBlock__GC0,
-logic__6756: VCU118RocketSystem__GC0,
-logic__1743: VCU118RocketSystem__GC0,
-case__910: RocketTile__GCB0,
-logic__9168: tracking_wrapper,
-logic__8163: VCU118RocketSystem__GC0,
-reg__1132: APBGpsBlock__GC0,
-ClockGroupAggregator_aggregator: VCU118RocketSystem__GC0,
-logic__2740: DCache,
-logic__4316: FPU__GB1,
-logic__8430: APBGpsBlock__GC0,
-fft_radix_2__parameterized1: APBGpsBlock__GC0,
-logic__5585: RocketTile__GCB0,
-logic__1163: VCU118RocketSystem__GC0,
-case__1658: tracking_wrapper,
-logic__6114: RocketTile__GCB0,
-logic__6966: VCU118RocketSystem__GC0,
-logic__9049: tracking_wrapper,
-datapath__459: RocketTile__GCB0,
-logic__5740: RocketTile__GCB0,
-logic__4120: FPU__GB2,
-datapath__499: VCU118RocketSystem__GC0,
-logic__1348: VCU118RocketSystem__GC0,
-reg__209: VCU118RocketSystem__GC0,
-acq_nco_carr: APBGpsBlock__GC0,
-logic__5252: RocketTile__GCB0,
-logic__3438: FPU__GB1,
-logic__2173: DCache,
-logic__1532: VCU118RocketSystem__GC0,
-logic__9093: tracking_wrapper,
-case__1616: tracking_wrapper,
-datapath__345: FPU__GB2,
-logic__7391: VCU118RocketSystem__GC0,
-case__1397: APBGpsBlock__GC0,
-case__154: vcu118_rocket_top__GC0,
-counter__4: vcu118_rocket_top__GC0,
-logic__9425: APBGpsBlock__GC0,
-logic__340: vcu118_rocket_top__GC0,
-logic__9420: APBGpsBlock__GC0,
-logic__5048: FPU__GB1,
-logic__3069: RocketTile__GCB0,
-logic__1823: VCU118RocketSystem__GC0,
-reg__197: VCU118RocketSystem__GC0,
-logic__819: VCU118RocketSystem__GC0,
-logic__1293: VCU118RocketSystem__GC0,
-case__208: vcu118_rocket_top__GC0,
-logic__85: vcu118_rocket_top__GC0,
-logic__7156: VCU118RocketSystem__GC0,
-reg__963: VCU118RocketSystem__GC0,
-reg__66: vcu118_rocket_top__GC0,
-logic__4837: FPU__GB2,
-case__376: VCU118RocketSystem__GC0,
-muxpart__236: FPU__GB0,
-logic__9303: tracking_wrapper,
-logic__8863: tracking_wrapper,
-logic__7070: VCU118RocketSystem__GC0,
-logic__6737: TilePRCIDomain__GC0,
-datapath__371: FPU__GB1,
-logic__2241: DCache,
-logic__4419: FPU__GB1,
-reg__882: VCU118RocketSystem__GC0,
-logic__322: vcu118_rocket_top__GC0,
-reg__789: RocketTile__GCB0,
-logic__79: vcu118_rocket_top__GC0,
-logic__1470: VCU118RocketSystem__GC0,
-muxpart__175: VCU118RocketSystem__GC0,
-logic__6093: RocketTile__GCB0,
-logic__252: vcu118_rocket_top__GC0,
-reg__19: vcu118_rocket_top__GC0,
-logic__4301: FPU__GB1,
-logic__7612: VCU118RocketSystem__GC0,
-datapath__251: VCU118RocketSystem__GC0,
-logic__4266: FPU__GB1,
-case__288: VCU118RocketSystem__GC0,
-reg__1266: tracking_wrapper,
-logic__8870: tracking_wrapper,
-reg__290: VCU118RocketSystem__GC0,
-logic__1735: VCU118RocketSystem__GC0,
-case__341: VCU118RocketSystem__GC0,
-dsp48e2__9: APBGpsBlock__GC0,
-logic__1527: VCU118RocketSystem__GC0,
-case__1482: APBGpsBlock__GC0,
-reg__1087: APBGpsBlock__GC0,
-muxpart__46: vcu118_rocket_top__GC0,
-case__389: VCU118RocketSystem__GC0,
-logic__64: vcu118_rocket_top__GC0,
-logic__9196: tracking_wrapper,
-case__718: FPU__GB1,
-logic__5546: RocketTile__GCB0,
-case__940: RocketTile__GCB0,
-logic__3057: RocketTile__GCB0,
-reg__1376: tracking_wrapper,
-mult_53_53_106: FPU__GB1,
-logic__2602: DCache,
-reg__1290: tracking_wrapper,
-case__696: FPU__GB2,
-logic__7521: VCU118RocketSystem__GC0,
-logic__7407: VCU118RocketSystem__GC0,
-datapath__292: RocketTile__GCB0,
-logic__3495: FPU__GB1,
-case__1187: VCU118RocketSystem__GC0,
-logic__9446: TLToAPB,
-reg__987: VCU118RocketSystem__GC0,
-logic__3682: FPU__GB1,
-logic__5196: RocketTile__GCB0,
-logic__6633: RocketTile__GCB0,
-reg__627: FPU__GB1,
-logic__5593: RocketTile__GCB0,
-ram_2x10: VCU118RocketSystem__GC0,
-case__165: vcu118_rocket_top__GC0,
-logic__7005: VCU118RocketSystem__GC0,
-case__406: VCU118RocketSystem__GC0,
-logic__5928: RocketTile__GCB0,
-datapath__476: RocketTile__GCB0,
-RecFNToIN: FPU__GB2,
-logic__7802: VCU118RocketSystem__GC0,
-case__1131: VCU118RocketSystem__GC0,
-case__1088: VCU118RocketSystem__GC0,
-logic__761: vcu118_rocket_top__GC0,
-logic__2187: DCache,
-logic__7931: VCU118RocketSystem__GC0,
-datapath__155: VCU118RocketSystem__GC0,
-logic__4381: FPU__GB1,
-logic__6992: VCU118RocketSystem__GC0,
-case__1000: VCU118RocketSystem__GC0,
-logic__1319: VCU118RocketSystem__GC0,
-reg__348: DCache,
-logic__289: vcu118_rocket_top__GC0,
-logic__8253: VCU118RocketSystem__GC0,
-logic__7370: VCU118RocketSystem__GC0,
-dsp48e2__28: APBGpsBlock__GC0,
-case__1641: tracking_wrapper,
-logic__844: VCU118RocketSystem__GC0,
-case__1362: APBGpsBlock__GC0,
-case__1259: APBGpsBlock__GC0,
-reg__417: RocketTile__GCB0,
-logic__7431: VCU118RocketSystem__GC0,
-reg__601: FPU__GB2,
-logic__1156: VCU118RocketSystem__GC0,
-logic__1997: VCU118RocketSystem__GC0,
-datapath__650: APBGpsBlock__GC0,
-reg__798: RocketTile__GCB0,
-case__449: VCU118RocketSystem__GC0,
-logic__6056: RocketTile__GCB0,
-logic__2567: DCache,
-case__1147: VCU118RocketSystem__GC0,
-case__963: RocketTile__GCB0,
-logic__1783: VCU118RocketSystem__GC0,
-logic__8701: APBGpsBlock__GC0,
-logic__9252: tracking_wrapper,
-case__1595: tracking_wrapper,
-logic__6937: VCU118RocketSystem__GC0,
-muxpart__226: FPU__GB0,
-logic__2739: DCache,
-logic__1846: VCU118RocketSystem__GC0,
-datapath__315: RocketTile__GCB0,
-case__1217: VCU118RocketSystem__GC0,
-datapath__392: FPU__GB1,
-reg__321: DCache,
-case__283: VCU118RocketSystem__GC0,
-case__123: vcu118_rocket_top__GC0,
-case__656: FPU__GB2, FPU__GB1,
-reg__549: FPU__GB1,
-IntSyncCrossingSource_n1x1_Registered: VCU118RocketSystem__GC0,
-logic__845: VCU118RocketSystem__GC0,
-logic__8777: APBGpsBlock__GC0,
-logic__4186: FPU__GB1,
-case__722: FPU__GB2, FPU__GB1,
-logic__5931: RocketTile__GCB0,
-case__1359: APBGpsBlock__GC0,
-datapath__561: APBGpsBlock__GC0,
-logic__4479: FPU__GB1,
-logic__5235: RocketTile__GCB0,
-logic__5402: RocketTile__GCB0,
-case__415: VCU118RocketSystem__GC0,
-logic__2209: DCache,
-logic__3448: FPU__GB1,
-logic__2395: DCache,
-extram__4: APBGpsBlock__GC0,
-case__1333: APBGpsBlock__GC0,
-case__824: RocketTile__GCB0,
-reg__1158: APBGpsBlock__GC0,
-case__798: FPU__GB1,
-reg__1306: tracking_wrapper,
-logic__2867: DCache,
-logic__4071: FPU__GB2,
-logic__7092: VCU118RocketSystem__GC0,
-logic__1099: VCU118RocketSystem__GC0,
-reg__204: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__846: TilePRCIDomain__GC0,
-logic__6695: RocketTile__GCB0,
-datapath__492: RocketTile__GCB0,
-logic__9377: tracking_wrapper,
-logic__5483: RocketTile__GCB0,
-reg__867: VCU118RocketSystem__GC0,
-datapath__53: VCU118RocketSystem__GC0,
-reg__732: RocketTile__GCB0,
-logic__4690: FPU__GB2,
-case__522: DCache,
-logic__2064: RocketTile__GCB0,
-logic__4115: FPU__GB2,
-logic__8259: VCU118RocketSystem__GC0,
-logic__351: vcu118_rocket_top__GC0,
-logic__7031: VCU118RocketSystem__GC0,
-ram_2x124: VCU118RocketSystem__GC0,
-logic__8114: VCU118RocketSystem__GC0,
-logic__7401: VCU118RocketSystem__GC0,
-case__786: FPU__GB1,
-logic__5179: FPU__GB1,
-logic__1605: VCU118RocketSystem__GC0,
-case__221: vcu118_rocket_top__GC0,
-logic__7906: VCU118RocketSystem__GC0,
-logic__3771: FPU__GB2,
-case__1683: TLToAPB,
-reg__245: VCU118RocketSystem__GC0,
-datapath__59: VCU118RocketSystem__GC0,
-logic__1358: VCU118RocketSystem__GC0,
-logic__5492: RocketTile__GCB0,
-case__257: VCU118RocketSystem__GC0,
-reg__839: RocketTile__GCB0,
-reg__1174: APBGpsBlock__GC0,
-logic__1138: VCU118RocketSystem__GC0,
-logic__2707: DCache,
-TLError_1: VCU118RocketSystem__GC0,
-logic__6916: VCU118RocketSystem__GC0,
-case__400: VCU118RocketSystem__GC0,
-ram_2x123: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-logic__5891: RocketTile__GCB0,
-reg__1134: APBGpsBlock__GC0,
-logic__2870: DCache,
-logic__2650: DCache,
-muxpart__19: vcu118_rocket_top__GC0,
-reg__853: VCU118RocketSystem__GC0,
-logic__2741: DCache,
-reg__75: vcu118_rocket_top__GC0,
-logic__124: vcu118_rocket_top__GC0,
-logic__1473: VCU118RocketSystem__GC0,
-logic__210: vcu118_rocket_top__GC0,
-logic__255: vcu118_rocket_top__GC0,
-logic__7997: VCU118RocketSystem__GC0,
-reg__217: VCU118RocketSystem__GC0,
-logic__4884: FPU__GB2,
-case__588: RocketTile__GCB0,
-datapath__256: VCU118RocketSystem__GC0,
-logic__372: vcu118_rocket_top__GC0,
-logic__2512: RocketTile__GCB0, DCache,
-case__838: RocketTile__GCB0,
-logic__8969: tracking_wrapper,
-logic__473: vcu118_rocket_top__GC0,
-reg__1303: tracking_wrapper,
-logic__3170: RocketTile__GCB0,
-logic__2088: RocketTile__GCB0,
-reg__482: FPU__GB1,
-case__737: FPU__GB2,
-case__1677: APBGpsBlock__GC0,
-logic__6036: RocketTile__GCB0,
-logic__4909: FPU__GB2,
-reg__407: RocketTile__GCB0,
-reg__1121: APBGpsBlock__GC0,
-logic__7416: VCU118RocketSystem__GC0,
-case__1634: tracking_wrapper,
-logic__1614: VCU118RocketSystem__GC0,
-trck_cntrl: tracking_wrapper,
-logic__9469: vcu118_rocket_top__GC0,
-logic__634: vcu118_rocket_top__GC0,
-logic__8144: VCU118RocketSystem__GC0,
-datapath__138: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__826: RocketTile__GCB0,
-logic__2247: DCache,
-logic__1822: VCU118RocketSystem__GC0,
-logic__1795: VCU118RocketSystem__GC0,
-logic__3228: RocketTile__GCB0,
-case__1607: tracking_wrapper,
-logic__4121: FPU__GB2,
-logic__5865: RocketTile__GCB0,
-reg__478: FPU__GB0,
-datapath__467: RocketTile__GCB0,
-logic__2316: DCache,
-reg__960: VCU118RocketSystem__GC0,
-logic__8130: VCU118RocketSystem__GC0,
-logic__984: VCU118RocketSystem__GC0,
-reg__905: VCU118RocketSystem__GC0,
-logic__1643: VCU118RocketSystem__GC0,
-logic__1205: VCU118RocketSystem__GC0,
-case__11: vcu118_rocket_top__GC0,
-datapath__527: VCU118RocketSystem__GC0,
-reg__1361: tracking_wrapper,
-case__1567: tracking_wrapper,
-logic__1638: VCU118RocketSystem__GC0,
-case__225: VCU118RocketSystem__GC0,
-reg__471: FPU__GB0,
-logic__4655: FPU__GB2, FPU__GB1,
-reg__1067: APBGpsBlock__GC0, tracking_wrapper,
-logic__5258: RocketTile__GCB0,
-logic__2871: DCache,
-logic__2814: DCache,
-logic__7154: VCU118RocketSystem__GC0,
-logic__4534: FPU__GB2, FPU__GB1,
-logic__4212: FPU__GB1,
-logic__5552: RocketTile__GCB0,
-muxpart__8: vcu118_rocket_top__GC0,
-reg__719: RocketTile__GCB0,
-case__1222: VCU118RocketSystem__GC0,
-datapath__308: RocketTile__GCB0,
-case__1614: tracking_wrapper,
-logic__4147: FPU__GB1,
-logic__1407: VCU118RocketSystem__GC0,
-case__334: VCU118RocketSystem__GC0,
-case__12: vcu118_rocket_top__GC0,
-reg__1218: tracking_wrapper,
-logic__6049: RocketTile__GCB0,
-reg__156: VCU118RocketSystem__GC0,
-logic__2941: DCache,
-logic__4051: FPU__GB2,
-reg__1291: tracking_wrapper,
-logic__3466: FPU__GB1,
-muxpart__172: VCU118RocketSystem__GC0,
-datapath__679: tracking_wrapper,
-logic__2952: DCache,
-reg__642: FPU__GB1,
-logic__746: vcu118_rocket_top__GC0,
-logic__6811: VCU118RocketSystem__GC0,
-reg__816: RocketTile__GCB0,
-datapath__307: RocketTile__GCB0,
-logic__4776: FPU__GB2,
-logic__4972: FPU__GB1,
-logic__9386: APBGpsBlock__GC0,
-logic__6118: RocketTile__GCB0,
-logic__5015: FPU__GB1,
-logic__2063: RocketTile__GCB0,
-reg__799: RocketTile__GCB0,
-counter__25: tracking_wrapper,
-logic__5380: RocketTile__GCB0,
-reg__1396: tracking_wrapper,
-logic__6480: RocketTile__GCB0,
-muxpart__44: vcu118_rocket_top__GC0,
-datapath__293: RocketTile__GCB0,
-reg__20: vcu118_rocket_top__GC0,
-reg__659: RocketTile__GCB0,
-logic__2633: DCache,
-case__1342: APBGpsBlock__GC0,
-logic__1976: VCU118RocketSystem__GC0,
-logic__5617: RocketTile__GCB0,
-reg__172: VCU118RocketSystem__GC0,
-logic__4515: FPU__GB1,
-case__749: FPU__GB2,
-case__1556: tracking_wrapper,
-reg__997: VCU118RocketSystem__GC0,
-logic__8778: APBGpsBlock__GC0,
-logic__7262: VCU118RocketSystem__GC0,
-logic__744: vcu118_rocket_top__GC0,
-logic__6814: VCU118RocketSystem__GC0,
-logic__6668: RocketTile__GCB0,
-logic__2309: DCache,
-reg__1183: APBGpsBlock__GC0,
-datapath__446: RocketTile__GCB0,
-case__459: VCU118RocketSystem__GC0,
-reg__802: RocketTile__GCB0,
-logic__7360: VCU118RocketSystem__GC0,
-logic__2550: DCache,
-case__1653: tracking_wrapper,
-reg__1307: tracking_wrapper,
-logic__8351: APBGpsBlock__GC0,
-reg__497: FPU__GB1,
-logic__3622: FPU__GB2, FPU__GB1,
-VCU118RocketSystem__GC0: VCU118RocketSystem__GC0,
-reg__106: vcu118_rocket_top__GC0,
-logic__5673: RocketTile__GCB0,
-case__615: RocketTile__GCB0,
-logic__4196: FPU__GB1,
-datapath__453: RocketTile__GCB0,
-logic__4413: FPU__GB1,
-reg__128: VCU118RocketSystem__GC0,
-reg__367: DCache,
-muxpart__36: vcu118_rocket_top__GC0,
-logic__7027: VCU118RocketSystem__GC0,
-logic__8942: tracking_wrapper,
-logic__5636: RocketTile__GCB0,
-logic__4307: FPU__GB1,
-case__1280: APBGpsBlock__GC0,
-dual_port_ram: APBGpsBlock__GC0,
-logic__4731: FPU__GB2,
-datapath__666: tracking_wrapper,
-case__1343: APBGpsBlock__GC0,
-logic__5428: RocketTile__GCB0,
-logic__7137: VCU118RocketSystem__GC0,
-datapath__228: VCU118RocketSystem__GC0,
-dsp48e2__14: APBGpsBlock__GC0,
-logic__141: vcu118_rocket_top__GC0,
-logic__1708: VCU118RocketSystem__GC0,
-case__616: RocketTile__GCB0,
-logic__9237: tracking_wrapper,
-case__1072: VCU118RocketSystem__GC0,
-logic__7099: VCU118RocketSystem__GC0,
-keep__12: tracking_wrapper,
-case__609: RocketTile__GCB0,
-muxpart__27: vcu118_rocket_top__GC0,
-logic__2016: VCU118RocketSystem__GC0,
-logic__9195: tracking_wrapper,
-logic__5560: RocketTile__GCB0,
-logic__3836: FPU__GB2,
-reg__11: vcu118_rocket_top__GC0,
-logic__8622: APBGpsBlock__GC0,
-reg__344: DCache,
-reg__1105: APBGpsBlock__GC0,
-case__726: FPU__GB2, FPU__GB1,
-reg__202: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__995: VCU118RocketSystem__GC0,
-TLBusBypassBar: VCU118RocketSystem__GC0,
-reg__1112: APBGpsBlock__GC0,
-logic__8961: tracking_wrapper,
-case__557: DCache,
-logic__3473: FPU__GB1,
-logic__5961: RocketTile__GCB0,
-reg__1170: APBGpsBlock__GC0,
-case__1663: tracking_wrapper,
-logic__8187: VCU118RocketSystem__GC0,
-case__254: VCU118RocketSystem__GC0,
-case__735: FPU__GB2,
-reg__545: FPU__GB1,
-logic__8191: VCU118RocketSystem__GC0,
-case__771: FPU__GB1,
-case__1298: APBGpsBlock__GC0,
-logic__5385: RocketTile__GCB0,
-ClockGroupAggregator_sbus: VCU118RocketSystem__GC0,
-case__1429: APBGpsBlock__GC0,
-logic__4613: FPU__GB2, FPU__GB1,
-logic__7366: VCU118RocketSystem__GC0,
-logic__6752: VCU118RocketSystem__GC0,
-datapath__211: VCU118RocketSystem__GC0,
-logic__3614: FPU__GB2, FPU__GB1,
-muxpart__245: FPU__GB0,
-logic__4177: FPU__GB1,
-reg__542: FPU__GB1,
-case__27: vcu118_rocket_top__GC0,
-datapath__429: RocketTile__GCB0,
-logic__9267: tracking_wrapper,
-logic__5136: FPU__GB1,
-logic__3334: FPU__GB1,
-reg__1171: APBGpsBlock__GC0,
-logic__1991: VCU118RocketSystem__GC0,
-reg__385: RocketTile__GCB0,
-reg__1202: APBGpsBlock__GC0,
-reg__38: vcu118_rocket_top__GC0,
-logic__5097: FPU__GB1,
-logic__6836: VCU118RocketSystem__GC0,
-logic__715: vcu118_rocket_top__GC0,
-datapath__688: tracking_wrapper,
-logic__2297: DCache,
-logic__410: vcu118_rocket_top__GC0,
-logic__4685: FPU__GB2,
-dsp48e2__16: APBGpsBlock__GC0,
-case__964: RocketTile__GCB0,
-logic__7844: VCU118RocketSystem__GC0,
-TilePRCIDomain__GC0: TilePRCIDomain__GC0,
-logic__747: vcu118_rocket_top__GC0,
-case__179: vcu118_rocket_top__GC0,
-logic__7397: VCU118RocketSystem__GC0,
-logic__9179: tracking_wrapper,
-logic__8717: APBGpsBlock__GC0,
-logic__5190: RocketTile__GCB0,
-logic__8338: APBGpsBlock__GC0,
-datapath__172: VCU118RocketSystem__GC0,
-logic__5464: RocketTile__GCB0,
-reg__1357: tracking_wrapper,
-logic__4631: FPU__GB2, FPU__GB1,
-logic__2500: RocketTile__GCB0, DCache,
-IntXbar_i1_o1: VCU118RocketSystem__GC0,
-logic__8529: APBGpsBlock__GC0,
-logic__6137: RocketTile__GCB0,
-case__1485: APBGpsBlock__GC0,
-TLBuffer_a32d64s1k1z4u_1: RocketTile__GCB0,
-reg__744: RocketTile__GCB0,
-datapath__662: tracking_wrapper,
-logic__805: VCU118RocketSystem__GC0,
-extrom__1: APBGpsBlock__GC0,
-reg__807: RocketTile__GCB0,
-case__864: RocketTile__GCB0,
-case__143: vcu118_rocket_top__GC0,
-case__1067: VCU118RocketSystem__GC0,
-datapath__223: VCU118RocketSystem__GC0,
-mult_66_66_66: RocketTile__GCB0,
-case__931: RocketTile__GCB0,
-logic__150: vcu118_rocket_top__GC0,
-logic__1150: VCU118RocketSystem__GC0,
-reg__1302: tracking_wrapper,
-reg__892: VCU118RocketSystem__GC0,
-logic__7020: VCU118RocketSystem__GC0,
-case__378: VCU118RocketSystem__GC0,
-logic__6589: RocketTile__GCB0,
-logic__5995: RocketTile__GCB0,
-logic__3278: RocketTile__GCB0,
-logic__7255: VCU118RocketSystem__GC0,
-reg__1084: APBGpsBlock__GC0,
-case__1657: tracking_wrapper,
-logic__727: vcu118_rocket_top__GC0,
-logic__7222: VCU118RocketSystem__GC0,
-logic__806: VCU118RocketSystem__GC0,
-logic__4543: FPU__GB2, FPU__GB1,
-reg__592: FPU__GB2,
-case__1233: VCU118RocketSystem__GC0,
-logic__7435: VCU118RocketSystem__GC0,
-logic__3666: FPU__GB2, FPU__GB1,
-logic__1546: VCU118RocketSystem__GC0,
-logic__2632: DCache,
-reg__1120: APBGpsBlock__GC0,
-datapath__441: RocketTile__GCB0,
-RoundAnyRawFNToRecFN_2: FPU__GB2,
-logic__4792: FPU__GB2,
-logic__5612: RocketTile__GCB0,
-case__202: vcu118_rocket_top__GC0,
-logic__4313: FPU__GB1,
-reg__709: RocketTile__GCB0,
-logic__6653: RocketTile__GCB0,
-logic__4748: FPU__GB2,
-logic__4985: FPU__GB1,
-logic__7594: VCU118RocketSystem__GC0,
-logic__6780: VCU118RocketSystem__GC0,
-reg__1327: tracking_wrapper,
-logic__5586: RocketTile__GCB0,
-logic__5951: RocketTile__GCB0,
-logic__3253: RocketTile__GCB0,
-datapath__8: vcu118_rocket_top__GC0,
-logic__7238: VCU118RocketSystem__GC0,
-reg__521: FPU__GB2,
-reg__1145: APBGpsBlock__GC0,
-case__677: FPU__GB2,
-case__1572: tracking_wrapper,
-logic__9106: tracking_wrapper,
-case__1109: VCU118RocketSystem__GC0,
-logic__4511: FPU__GB1,
-logic__1520: VCU118RocketSystem__GC0,
-reg__674: RocketTile__GCB0,
-logic__4680: FPU__GB1,
-logic__5604: RocketTile__GCB0,
-reg__579: FPU__GB2,
-datapath__408: FPU__GB2,
-dsp48e2__43: tracking_wrapper,
-logic__5526: RocketTile__GCB0,
-reg__848: TilePRCIDomain__GC0,
-logic__2417: DCache,
-muxpart__93: vcu118_rocket_top__GC0,
-logic__2888: DCache,
-muxpart__231: FPU__GB0,
-logic__5477: RocketTile__GCB0,
-logic__7808: VCU118RocketSystem__GC0,
-logic__1306: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-reg__1241: tracking_wrapper,
-case__310: VCU118RocketSystem__GC0,
-logic__1200: VCU118RocketSystem__GC0,
-logic__4487: FPU__GB1,
-reg__1298: tracking_wrapper,
-reg__1389: tracking_wrapper,
-logic__6125: RocketTile__GCB0,
-logic__5397: RocketTile__GCB0,
-reg__701: RocketTile__GCB0,
-reg__173: VCU118RocketSystem__GC0,
-muxpart__380: tracking_wrapper,
-reg__1196: APBGpsBlock__GC0,
-case__1513: APBGpsBlock__GC0,
-logic__6746: VCU118RocketSystem__GC0,
-logic__2901: DCache,
-datapath__696: tracking_wrapper,
-logic__5822: RocketTile__GCB0,
-logic__6985: VCU118RocketSystem__GC0,
-reg__697: RocketTile__GCB0,
-logic__5124: FPU__GB1,
-logic__3866: FPU__GB2,
-case__1247: VCU118RocketSystem__GC0,
-reg__1032: VCU118RocketSystem__GC0,
-reg__1113: APBGpsBlock__GC0,
-logic__1331: VCU118RocketSystem__GC0,
-logic__7114: VCU118RocketSystem__GC0,
-logic__5539: RocketTile__GCB0,
-reg__683: RocketTile__GCB0,
-reg__645: FPU__GB1,
-logic__2983: RocketTile__GCB0,
-logic__3916: FPU__GB2,
-case__1090: VCU118RocketSystem__GC0,
-case__1253: APBGpsBlock__GC0,
-datapath__711: tracking_wrapper,
-logic__6732: TilePRCIDomain__GC0,
-case__1433: APBGpsBlock__GC0,
-case__800: FPU__GB0,
-reg__973: VCU118RocketSystem__GC0,
-reg__152: VCU118RocketSystem__GC0,
-HellaCacheArbiter: RocketTile__GCB0,
-case__807: FPU__GB1,
-reg__252: VCU118RocketSystem__GC0,
-logic__1565: VCU118RocketSystem__GC0,
-logic__9164: tracking_wrapper,
-logic__6005: RocketTile__GCB0,
-keep__13: tracking_wrapper,
-reg__17: vcu118_rocket_top__GC0,
-datapath__7: vcu118_rocket_top__GC0,
-reg__637: FPU__GB1,
-logic__2029: VCU118RocketSystem__GC0,
-logic__1853: VCU118RocketSystem__GC0,
-reg__363: DCache,
-logic__3417: FPU__GB1,
-logic__5109: FPU__GB1,
-logic__7563: VCU118RocketSystem__GC0,
-logic__2749: DCache,
-logic__6627: RocketTile__GCB0,
-datapath__82: VCU118RocketSystem__GC0,
-logic__4679: FPU__GB1,
-logic__1228: VCU118RocketSystem__GC0,
-logic__4761: FPU__GB2,
-muxpart__356: APBGpsBlock__GC0,
-reg__583: FPU__GB2,
-logic__4305: FPU__GB1,
-case__1198: VCU118RocketSystem__GC0,
-logic__4874: FPU__GB2,
-case__1089: VCU118RocketSystem__GC0,
-reg__884: VCU118RocketSystem__GC0,
-logic__1430: VCU118RocketSystem__GC0,
-logic__7949: VCU118RocketSystem__GC0,
-logic__1216: VCU118RocketSystem__GC0,
-case__1320: APBGpsBlock__GC0,
-datapath__326: FPU__GB1,
-reg__1125: APBGpsBlock__GC0,
-logic__6195: RocketTile__GCB0,
-case__155: vcu118_rocket_top__GC0,
-logic__8609: APBGpsBlock__GC0,
-datapath__200: VCU118RocketSystem__GC0,
-reg__424: RocketTile__GCB0,
-logic__7551: VCU118RocketSystem__GC0,
-reg__7: vcu118_rocket_top__GC0,
-case__372: VCU118RocketSystem__GC0,
-reg__414: RocketTile__GCB0,
-logic__7294: VCU118RocketSystem__GC0,
-reg__49: vcu118_rocket_top__GC0,
-logic__7434: VCU118RocketSystem__GC0,
-reg__1172: APBGpsBlock__GC0,
-case__712: FPU__GB1,
-logic__9349: tracking_wrapper,
-addsub__3: tracking_wrapper,
-logic__3111: RocketTile__GCB0,
-case__564: DCache,
-reg__469: FPU__GB0,
-logic__8861: tracking_wrapper,
-case__362: VCU118RocketSystem__GC0,
-reg__1165: APBGpsBlock__GC0,
-case__1434: APBGpsBlock__GC0,
-reg__349: DCache,
-logic__8867: tracking_wrapper,
-logic__5632: RocketTile__GCB0,
-reg__477: FPU__GB0,
-datapath__603: APBGpsBlock__GC0,
-case__1520: tracking_wrapper,
-logic__2671: DCache,
-case__1: vcu118_rocket_top__GC0,
-logic__1641: VCU118RocketSystem__GC0,
-reg__1244: tracking_wrapper,
-reg__480: FPU__GB1,
-datapath: vcu118_rocket_top__GC0,
-case__350: VCU118RocketSystem__GC0,
-logic__4936: FPU__GB2,
-double_ff_syn: APBGpsBlock__GC0, tracking_wrapper,
-logic__3725: FPU__GB2,
-logic__6180: RocketTile__GCB0,
-logic__4441: FPU__GB1,
-reg__205: VCU118RocketSystem__GC0,
-datapath__118: VCU118RocketSystem__GC0,
-logic__9445: TLToAPB,
-reg__316: RocketTile__GCB0,
-logic__7111: VCU118RocketSystem__GC0,
-logic__1557: VCU118RocketSystem__GC0,
-case__1651: tracking_wrapper,
-datapath__126: VCU118RocketSystem__GC0,
-reg__122: VCU118RocketSystem__GC0,
-logic__5927: RocketTile__GCB0,
-logic__1051: VCU118RocketSystem__GC0,
-datapath__509: VCU118RocketSystem__GC0,
-reg__563: FPU__GB1,
-logic__5950: RocketTile__GCB0,
-logic__3301: FPU__GB1,
-logic__8398: APBGpsBlock__GC0,
-logic__6046: RocketTile__GCB0,
-logic__2716: DCache,
-muxpart__178: DCache,
-logic__8799: tracking_wrapper,
-datapath__358: FPU__GB2,
-dsp48e2__8: APBGpsBlock__GC0,
-logic__2785: DCache,
-logic__8994: tracking_wrapper,
-logic__4389: FPU__GB1,
-logic__8282: APBGpsBlock__GC0,
-reg__1268: tracking_wrapper,
-reg__1402: TLToAPB,
-logic__265: vcu118_rocket_top__GC0,
-logic__1362: VCU118RocketSystem__GC0,
-logic__3783: FPU__GB2,
-logic__3444: FPU__GB1,
-logic__2352: DCache,
-case__1544: tracking_wrapper,
-logic__9223: tracking_wrapper,
-logic__6057: RocketTile__GCB0,
-reg__1236: tracking_wrapper,
-case__138: vcu118_rocket_top__GC0,
-logic__5481: RocketTile__GCB0,
-logic__633: vcu118_rocket_top__GC0,
-logic__2786: DCache,
-reg__1078: APBGpsBlock__GC0,
-muxpart__151: vcu118_rocket_top__GC0,
-logic__3821: FPU__GB2,
-datapath__92: VCU118RocketSystem__GC0,
-reg__415: RocketTile__GCB0,
-case__791: FPU__GB1,
-logic__352: vcu118_rocket_top__GC0,
-reg__871: VCU118RocketSystem__GC0,
-logic__1642: VCU118RocketSystem__GC0,
-reg__615: FPU__GB1,
-logic__8238: VCU118RocketSystem__GC0,
-reg__982: VCU118RocketSystem__GC0,
-reg__949: VCU118RocketSystem__GC0,
-logic__8132: VCU118RocketSystem__GC0,
-datapath__295: RocketTile__GCB0,
-case__1052: VCU118RocketSystem__GC0,
-case__340: VCU118RocketSystem__GC0,
-logic__9449: TLToAPB,
-logic__3554: FPU__GB1,
-logic__7389: VCU118RocketSystem__GC0,
-extladd__2: tracking_wrapper,
-reg__1110: APBGpsBlock__GC0,
-case__860: RocketTile__GCB0,
-reg__776: RocketTile__GCB0,
-logic__2281: DCache,
-muxpart__147: vcu118_rocket_top__GC0,
-counter__17: APBGpsBlock__GC0,
-dsp48e2__1: FPU__GB1,
-case__1241: VCU118RocketSystem__GC0,
-ram__2: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-muxpart__81: vcu118_rocket_top__GC0,
-logic__8035: VCU118RocketSystem__GC0,
-logic__2884: DCache,
-case__563: DCache,
-muxpart__205: FPU__GB0,
-datapath__27: vcu118_rocket_top__GC0,
-datapath__454: RocketTile__GCB0,
-case__1122: VCU118RocketSystem__GC0,
-case__1014: VCU118RocketSystem__GC0,
-TLFragmenter_bootrom: VCU118RocketSystem__GC0,
-case__397: VCU118RocketSystem__GC0,
-datapath__663: tracking_wrapper,
-extram: vcu118_rocket_top__GC0,
-case__952: RocketTile__GCB0,
-logic__4512: FPU__GB1,
-logic__7964: VCU118RocketSystem__GC0,
-reg__1188: APBGpsBlock__GC0,
-logic__6007: RocketTile__GCB0,
-logic__5609: RocketTile__GCB0,
-case__1301: APBGpsBlock__GC0,
-case__414: VCU118RocketSystem__GC0,
-logic__3066: RocketTile__GCB0,
-datapath__410: FPU__GB2,
-logic__4352: FPU__GB1,
-datapath__24: vcu118_rocket_top__GC0,
-reg__560: FPU__GB1,
-logic__5988: RocketTile__GCB0,
-logic__1132: VCU118RocketSystem__GC0,
-case__235: VCU118RocketSystem__GC0,
-logic__7139: VCU118RocketSystem__GC0,
-logic__1972: VCU118RocketSystem__GC0,
-case__539: DCache,
-reg__1223: tracking_wrapper,
-dsp48e2__36: tracking_wrapper,
-muxpart__2: vcu118_rocket_top__GC0,
-reg__847: TilePRCIDomain__GC0,
-bootromClockSinkDomain: VCU118RocketSystem__GC0,
-muxpart: vcu118_rocket_top__GC0,
-muxpart__31: vcu118_rocket_top__GC0,
-datapath__518: VCU118RocketSystem__GC0,
-reg__519: FPU__GB2,
-logic__4991: FPU__GB2,
-datapath__558: APBGpsBlock__GC0,
-reg__1034: VCU118RocketSystem__GC0,
-logic__7422: VCU118RocketSystem__GC0,
-logic__330: vcu118_rocket_top__GC0,
-TLWidthWidget8_2: VCU118RocketSystem__GC0,
-logic__2891: DCache,
-logic__3538: FPU__GB1,
-logic__8136: VCU118RocketSystem__GC0,
-logic__5485: RocketTile__GCB0,
-logic__2139: RocketTile__GCB0,
-case__527: DCache,
-logic__7376: VCU118RocketSystem__GC0,
-datapath__317: FPU__GB1,
-reg__452: FPU__GB0,
-logic__968: VCU118RocketSystem__GC0,
-logic__4089: FPU__GB2,
-logic__8940: tracking_wrapper,
-case__1244: VCU118RocketSystem__GC0,
-case__569: RocketTile__GCB0,
-case__1085: VCU118RocketSystem__GC0,
-logic__1369: VCU118RocketSystem__GC0,
-reg__1198: APBGpsBlock__GC0,
-case__1225: VCU118RocketSystem__GC0,
-case__1660: tracking_wrapper,
-logic__9389: APBGpsBlock__GC0,
-logic__813: VCU118RocketSystem__GC0,
-logic__2290: DCache,
-case__1183: VCU118RocketSystem__GC0,
-case__1163: VCU118RocketSystem__GC0,
-logic__7351: VCU118RocketSystem__GC0,
-logic__453: vcu118_rocket_top__GC0,
-reg__824: RocketTile__GCB0,
-logic__3694: FPU__GB2,
-logic__2466: DCache,
-logic__3156: RocketTile__GCB0,
-logic__9441: TLToAPB,
-logic__6669: RocketTile__GCB0,
-logic__1581: VCU118RocketSystem__GC0,
-logic__9451: TLToAPB,
-logic__7974: VCU118RocketSystem__GC0,
-reg__1373: tracking_wrapper,
-case__401: VCU118RocketSystem__GC0,
-FPUFMAPipe_l4_f64: FPU__GB1,
-reg__762: RocketTile__GCB0,
-logic__8873: tracking_wrapper,
-muxpart__239: FPU__GB0,
-reg__21: vcu118_rocket_top__GC0,
-muxpart__230: FPU__GB0,
-logic__5878: RocketTile__GCB0,
-reg__634: FPU__GB1,
-logic__1327: VCU118RocketSystem__GC0,
-reg__113: VCU118RocketSystem__GC0,
-case__794: FPU__GB1,
-reg__110: VCU118RocketSystem__GC0,
-AsyncQueueSource_TLBundleD_a9d32s1k1z2u: VCU118RocketSystem__GC0,
-logic__8936: tracking_wrapper,
-case__1386: APBGpsBlock__GC0,
-reg__696: RocketTile__GCB0,
-FPU__GB0: FPU__GB0,
-logic__2282: DCache,
-logic__3051: RocketTile__GCB0,
-case__1543: tracking_wrapper,
-reg__1021: VCU118RocketSystem__GC0,
-logic__6816: VCU118RocketSystem__GC0,
-datapath__714: tracking_wrapper,
-logic__6655: RocketTile__GCB0,
-datapath__692: tracking_wrapper,
-logic__3485: FPU__GB1,
-datapath__672: tracking_wrapper,
-logic__6952: VCU118RocketSystem__GC0,
-datapath__281: DCache,
-logic__9248: tracking_wrapper,
-case__1371: APBGpsBlock__GC0,
-muxpart__374: tracking_wrapper,
-rom__8: tracking_wrapper,
-logic__1720: VCU118RocketSystem__GC0,
-logic__4432: FPU__GB1,
-reg__1055: VCU118RocketSystem__GC0,
-logic__7206: VCU118RocketSystem__GC0,
-reg__244: VCU118RocketSystem__GC0,
-datapath__71: VCU118RocketSystem__GC0,
-logic__971: VCU118RocketSystem__GC0,
-case__425: VCU118RocketSystem__GC0,
-case__867: RocketTile__GCB0,
-reg__582: FPU__GB2,
-reg__1326: tracking_wrapper,
-reg__310: VCU118RocketSystem__GC0,
-case__941: RocketTile__GCB0,
-logic__3312: FPU__GB1,
-case__163: vcu118_rocket_top__GC0,
-reg__835: RocketTile__GCB0,
-logic__7570: VCU118RocketSystem__GC0,
-logic__5431: RocketTile__GCB0,
-case__918: RocketTile__GCB0,
-counter__26: tracking_wrapper,
-muxpart__54: vcu118_rocket_top__GC0,
-logic__4438: FPU__GB1,
-logic__7250: VCU118RocketSystem__GC0,
-case__1596: tracking_wrapper,
-case__1558: tracking_wrapper,
-reg__356: DCache,
-datapath__414: FPU__GB1,
-TLPLIC: VCU118RocketSystem__GC0,
-case__1539: tracking_wrapper,
-logic__754: vcu118_rocket_top__GC0,
-logic__6727: RocketTile__GCB0,
-logic__1333: VCU118RocketSystem__GC0,
-case__556: DCache,
-reg__1045: VCU118RocketSystem__GC0,
-case__685: FPU__GB2,
-reg__369: DCache,
-case__1504: APBGpsBlock__GC0,
-logic__8367: APBGpsBlock__GC0,
-logic__1290: VCU118RocketSystem__GC0,
-logic__4772: FPU__GB2,
-reg__62: vcu118_rocket_top__GC0,
-case__1140: VCU118RocketSystem__GC0,
-datapath__406: FPU__GB2,
-case__1497: APBGpsBlock__GC0,
-muxpart__58: vcu118_rocket_top__GC0,
-case__1190: VCU118RocketSystem__GC0,
-case__1501: APBGpsBlock__GC0,
-case__813: RocketTile__GCB0,
-reg__71: vcu118_rocket_top__GC0,
-case__645: FPU__GB1,
-case__364: VCU118RocketSystem__GC0,
-reg__661: RocketTile__GCB0,
-datapath__723: tracking_wrapper,
-reg__1338: tracking_wrapper,
-datapath__620: APBGpsBlock__GC0,
-case__148: vcu118_rocket_top__GC0,
-reg__1255: tracking_wrapper,
-reg__849: TilePRCIDomain__GC0,
-logic__631: vcu118_rocket_top__GC0,
-logic__5756: RocketTile__GCB0,
-logic__7287: VCU118RocketSystem__GC0,
-case__359: VCU118RocketSystem__GC0,
-logic__5594: RocketTile__GCB0,
-logic__1035: VCU118RocketSystem__GC0,
-case__985: VCU118RocketSystem__GC0,
-reg__254: VCU118RocketSystem__GC0,
-logic__1188: VCU118RocketSystem__GC0,
-case__944: RocketTile__GCB0,
-logic__3181: RocketTile__GCB0,
-case__708: FPU__GB1,
-logic__1811: VCU118RocketSystem__GC0,
-reg__1388: tracking_wrapper,
-logic__9224: tracking_wrapper,
-logic__8707: APBGpsBlock__GC0,
-muxpart__180: DCache,
-logic__7188: VCU118RocketSystem__GC0,
-reg__530: FPU__GB1,
-datapath__291: DCache,
-datapath__628: APBGpsBlock__GC0,
-logic__5844: RocketTile__GCB0,
-logic__1335: VCU118RocketSystem__GC0,
-logic__4394: FPU__GB1,
-logic__939: VCU118RocketSystem__GC0,
-muxpart__258: FPU__GB1,
-case__759: FPU__GB2,
-reg__1261: tracking_wrapper,
-case__1102: VCU118RocketSystem__GC0,
-datapath__547: VCU118RocketSystem__GC0,
-logic__1271: VCU118RocketSystem__GC0,
-case__1124: VCU118RocketSystem__GC0,
-case__1573: tracking_wrapper,
-reg__203: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-datapath__352: FPU__GB2,
-logic__3789: FPU__GB2,
-datapath__676: tracking_wrapper,
-reg__1137: APBGpsBlock__GC0,
-case__1518: tracking_wrapper,
-reg__1197: APBGpsBlock__GC0,
-case__1284: APBGpsBlock__GC0,
-logic__9460: TLToAPB,
-datapath__338: FPU__GB2,
-logic__5541: RocketTile__GCB0,
-logic__3337: FPU__GB1,
-logic__6672: RocketTile__GCB0,
-reg__841: RocketTile__GCB0,
-case__13: vcu118_rocket_top__GC0,
-ICache: RocketTile__GCB0,
-case__1130: VCU118RocketSystem__GC0,
-logic__5392: RocketTile__GCB0,
-DivSqrtRawFN_small_1: FPU__GB2,
-case__1186: VCU118RocketSystem__GC0,
-datapath__226: VCU118RocketSystem__GC0,
-reg__1086: APBGpsBlock__GC0,
-logic__7136: VCU118RocketSystem__GC0,
-muxpart__193: FPU__GB0,
-logic__4499: FPU__GB1,
-datapath__703: tracking_wrapper,
-case__267: VCU118RocketSystem__GC0,
-muxpart__385: tracking_wrapper,
-case__840: RocketTile__GCB0,
-case__601: RocketTile__GCB0,
-reg__184: VCU118RocketSystem__GC0,
-reg__1020: VCU118RocketSystem__GC0,
-logic__1966: VCU118RocketSystem__GC0,
-reg__258: VCU118RocketSystem__GC0,
-logic__6055: RocketTile__GCB0,
-logic__6794: VCU118RocketSystem__GC0,
-reg__1330: tracking_wrapper,
-reg__933: VCU118RocketSystem__GC0,
-case__223: VCU118RocketSystem__GC0,
-case__734: FPU__GB1,
-logic__3210: RocketTile__GCB0,
-logic__2761: DCache,
-datapath__2: vcu118_rocket_top__GC0,
-case__570: RocketTile__GCB0,
-logic__6002: RocketTile__GCB0,
-case__410: VCU118RocketSystem__GC0,
-case__534: DCache,
-logic__1926: VCU118RocketSystem__GC0,
-case__937: RocketTile__GCB0,
-logic__7766: VCU118RocketSystem__GC0,
-reg__1246: tracking_wrapper,
-logic__318: vcu118_rocket_top__GC0,
-logic__9292: tracking_wrapper,
-case__917: RocketTile__GCB0,
-case__1332: APBGpsBlock__GC0,
-logic__3475: FPU__GB1,
-reg__797: RocketTile__GCB0,
-reg__345: DCache,
-datapath__278: DCache,
-case__766: FPU__GB2,
-logic__6723: RocketTile__GCB0,
-case__1415: APBGpsBlock__GC0,
-logic__1679: VCU118RocketSystem__GC0,
-logic__5372: RocketTile__GCB0,
-reg__384: RocketTile__GCB0,
-logic__3336: FPU__GB1,
-case__928: RocketTile__GCB0,
-datapath__305: RocketTile__GCB0,
-logic__4374: FPU__GB1,
-reg__1384: tracking_wrapper,
-reg__558: FPU__GB1,
-logic__4697: FPU__GB2,
-logic__8691: APBGpsBlock__GC0,
-logic__5677: RocketTile__GCB0,
-logic__3617: FPU__GB2, FPU__GB1,
-logic__8151: VCU118RocketSystem__GC0,
-reg__1316: tracking_wrapper,
-logic__2329: DCache,
-case__346: VCU118RocketSystem__GC0,
-reg__1152: APBGpsBlock__GC0,
-logic__4048: FPU__GB2,
-logic__964: VCU118RocketSystem__GC0,
-logic__8126: VCU118RocketSystem__GC0,
-case__420: VCU118RocketSystem__GC0,
-logic__5968: RocketTile__GCB0,
-reg__914: VCU118RocketSystem__GC0,
-logic__3338: FPU__GB1,
-logic__6350: RocketTile__GCB0,
-datapath__312: RocketTile__GCB0,
-logic__9280: tracking_wrapper,
-case__281: VCU118RocketSystem__GC0,
-logic__386: vcu118_rocket_top__GC0,
-logic__51: vcu118_rocket_top__GC0,
-logic__2219: DCache,
-reg__233: VCU118RocketSystem__GC0,
-logic__7214: VCU118RocketSystem__GC0,
-logic__1273: VCU118RocketSystem__GC0,
-reg__342: DCache,
-logic__2111: RocketTile__GCB0,
-datapath__33: VCU118RocketSystem__GC0,
-butterfly: APBGpsBlock__GC0,
-logic__3340: FPU__GB1,
-logic__2280: DCache,
-reg__1030: VCU118RocketSystem__GC0,
-logic__5959: RocketTile__GCB0,
-logic__6310: RocketTile__GCB0,
-case__608: RocketTile__GCB0,
-logic__7734: VCU118RocketSystem__GC0,
-reg__1102: APBGpsBlock__GC0,
-case__1188: VCU118RocketSystem__GC0,
-logic__2519: RocketTile__GCB0, DCache,
-logic__1276: VCU118RocketSystem__GC0,
-logic__9427: APBGpsBlock__GC0,
-case__1035: VCU118RocketSystem__GC0,
-logic__9208: tracking_wrapper,
-reg__881: VCU118RocketSystem__GC0,
-logic__1944: VCU118RocketSystem__GC0,
-logic__269: vcu118_rocket_top__GC0,
-logic__7241: VCU118RocketSystem__GC0,
-datapath__664: tracking_wrapper,
-logic__7409: VCU118RocketSystem__GC0,
-reg__903: VCU118RocketSystem__GC0,
-logic__810: VCU118RocketSystem__GC0,
-logic__5548: RocketTile__GCB0,
-logic__6665: RocketTile__GCB0,
-case__593: RocketTile__GCB0,
-reg__419: RocketTile__GCB0,
-case__264: VCU118RocketSystem__GC0,
-signinv: RocketTile__GCB0,
-reg__101: vcu118_rocket_top__GC0,
-case__492: RocketTile__GCB0,
-logic__47: vcu118_rocket_top__GC0,
-logic__5272: RocketTile__GCB0,
-case__765: FPU__GB2,
-logic__2895: DCache,
-logic__5637: RocketTile__GCB0,
-logic__5359: RocketTile__GCB0,
-logic__7078: VCU118RocketSystem__GC0,
-reg__48: vcu118_rocket_top__GC0,
-logic__2778: DCache,
-logic__3456: FPU__GB1,
-case__315: VCU118RocketSystem__GC0,
-reg__1274: tracking_wrapper,
-case__748: FPU__GB2,
-reg__658: RocketTile__GCB0,
-logic__7284: VCU118RocketSystem__GC0,
-reg__241: VCU118RocketSystem__GC0,
-case__355: VCU118RocketSystem__GC0,
-logic__4306: FPU__GB1,
-Repeater_TLBundleA_a28d64s2k1z3u: VCU118RocketSystem__GC0,
-reg__416: RocketTile__GCB0,
-datapath__616: APBGpsBlock__GC0,
-logic__4093: FPU__GB2,
-reg__1151: APBGpsBlock__GC0,
-logic__5197: RocketTile__GCB0,
-datapath__576: APBGpsBlock__GC0,
-logic__6059: RocketTile__GCB0,
-logic__6802: VCU118RocketSystem__GC0,
-logic__1733: VCU118RocketSystem__GC0,
-logic__2193: DCache,
-muxpart__16: vcu118_rocket_top__GC0,
-reg__1157: APBGpsBlock__GC0,
-logic__8962: tracking_wrapper,
-logic__898: VCU118RocketSystem__GC0,
-datapath__609: APBGpsBlock__GC0,
-logic__7784: VCU118RocketSystem__GC0,
-logic__3537: FPU__GB1,
-logic__2252: DCache,
-logic__6032: RocketTile__GCB0,
-datapath__498: VCU118RocketSystem__GC0,
-reg__325: DCache,
-muxpart__30: vcu118_rocket_top__GC0,
-reg__31: vcu118_rocket_top__GC0,
-logic__1194: VCU118RocketSystem__GC0,
-logic__2588: DCache,
-reg__1072: APBGpsBlock__GC0,
-logic__8131: VCU118RocketSystem__GC0,
-reg__135: VCU118RocketSystem__GC0,
-case__1577: tracking_wrapper,
-reg__869: VCU118RocketSystem__GC0,
-logic__5299: RocketTile__GCB0,
-datapath__355: FPU__GB2,
-logic__3874: FPU__GB2,
-ram__4: VCU118RocketSystem__GC0,
-case__461: VCU118RocketSystem__GC0,
-datapath__115: VCU118RocketSystem__GC0,
-reg__970: VCU118RocketSystem__GC0,
-datapath__56: VCU118RocketSystem__GC0,
-case__1624: tracking_wrapper,
-logic__7263: VCU118RocketSystem__GC0,
-logic__6976: VCU118RocketSystem__GC0,
-datapath__523: VCU118RocketSystem__GC0,
-case__992: VCU118RocketSystem__GC0,
-logic__5984: RocketTile__GCB0,
-case__1360: APBGpsBlock__GC0,
-case__1509: APBGpsBlock__GC0,
-logic__4925: FPU__GB2,
-logic__5748: RocketTile__GCB0,
-datapath__493: TilePRCIDomain__GC0,
-case__1058: VCU118RocketSystem__GC0,
-datapath__323: FPU__GB1,
-muxpart__199: FPU__GB0,
-logic__4411: FPU__GB1,
-datapath__81: VCU118RocketSystem__GC0,
-logic__6003: RocketTile__GCB0,
-logic__1870: VCU118RocketSystem__GC0,
-case__802: FPU__GB1,
-logic__2102: RocketTile__GCB0,
-case__441: VCU118RocketSystem__GC0,
-FPGAUARTClockSinkDomain: VCU118RocketSystem__GC0,
-logic__8056: VCU118RocketSystem__GC0,
-reg__535: FPU__GB1,
-logic__2911: DCache,
-datapath__585: APBGpsBlock__GC0,
-case__545: DCache,
-logic__4451: FPU__GB1,
-logic__2634: DCache,
-case__1643: tracking_wrapper,
-logic__5232: RocketTile__GCB0,
-case__590: RocketTile__GCB0,
-sample_align: APBGpsBlock__GC0,
-case__1519: tracking_wrapper,
-logic__1724: VCU118RocketSystem__GC0,
-logic__6099: RocketTile__GCB0,
-logic__3242: RocketTile__GCB0,
-logic__6136: RocketTile__GCB0,
-logic__5150: FPU__GB1,
-case__402: VCU118RocketSystem__GC0,
-case__469: VCU118RocketSystem__GC0,
-reg__459: FPU__GB0,
-logic__8269: APBGpsBlock__GC0,
-reg__1312: tracking_wrapper,
-logic__1776: VCU118RocketSystem__GC0,
-case__352: VCU118RocketSystem__GC0,
-reg__840: RocketTile__GCB0,
-case__144: vcu118_rocket_top__GC0,
-reg__266: VCU118RocketSystem__GC0,
-case__1581: tracking_wrapper,
-case__648: FPU__GB1,
-case__761: FPU__GB2,
-logic__4403: FPU__GB1,
-case__1586: tracking_wrapper,
-reg__822: RocketTile__GCB0,
-case__927: RocketTile__GCB0,
-case__1374: APBGpsBlock__GC0,
-logic__1588: VCU118RocketSystem__GC0,
-reg__561: FPU__GB1,
-logic__8882: tracking_wrapper,
-logic__1399: VCU118RocketSystem__GC0,
-datapath__687: tracking_wrapper,
-RoundRawFNToRecFN: FPU__GB2, FPU__GB1,
-datapath__132: VCU118RocketSystem__GC0,
-logic__4127: FPU__GB2,
-logic__8325: APBGpsBlock__GC0,
-logic__6826: VCU118RocketSystem__GC0,
-logic__3165: RocketTile__GCB0,
-logic__6035: RocketTile__GCB0,
-case__426: VCU118RocketSystem__GC0,
-reg__1385: tracking_wrapper,
-logic__7130: VCU118RocketSystem__GC0,
-case__227: VCU118RocketSystem__GC0,
-case__272: VCU118RocketSystem__GC0,
-datapath__421: RocketTile__GCB0,
-logic__1214: VCU118RocketSystem__GC0,
-logic__2908: DCache,
-datapath__224: VCU118RocketSystem__GC0,
-logic__7972: VCU118RocketSystem__GC0,
-logic__7081: VCU118RocketSystem__GC0,
-logic__1315: VCU118RocketSystem__GC0, TilePRCIDomain__GC0,
-TLDebugModule: VCU118RocketSystem__GC0,
-dsp48e2__21: APBGpsBlock__GC0,
-logic__7704: VCU118RocketSystem__GC0,
-logic__4412: FPU__GB1,
-logic__3269: RocketTile__GCB0,
-datapath__299: RocketTile__GCB0,
-logic__7235: VCU118RocketSystem__GC0,
-logic__6168: RocketTile__GCB0,
-CLINTClockSinkDomain: VCU118RocketSystem__GC0,
-case__413: VCU118RocketSystem__GC0,
-logic__6926: VCU118RocketSystem__GC0,
-logic__1332: VCU118RocketSystem__GC0,
-logic__4317: FPU__GB1,
-case__450: VCU118RocketSystem__GC0,
-logic__7348: VCU118RocketSystem__GC0,
-logic__1437: VCU118RocketSystem__GC0,
-reg__1024: VCU118RocketSystem__GC0,
-logic__6659: RocketTile__GCB0,
-case__1606: tracking_wrapper,
-logic__511: vcu118_rocket_top__GC0,
-logic__5864: RocketTile__GCB0,
-logic__2332: DCache,
-logic__7091: VCU118RocketSystem__GC0,
-reg__889: VCU118RocketSystem__GC0,
-dsp48e2__3: APBGpsBlock__GC0,
-datapath__346: FPU__GB2,
-datapath__180: VCU118RocketSystem__GC0,
-case__892: RocketTile__GCB0,
-logic__2315: DCache,
-logic__5710: RocketTile__GCB0,
-keep__7: vcu118_rocket_top__GC0,
-logic__208: vcu118_rocket_top__GC0,
-case__660: FPU__GB2, FPU__GB1,
-logic__6893: VCU118RocketSystem__GC0,
-logic__5848: RocketTile__GCB0,
-reg__1026: VCU118RocketSystem__GC0,
-case__366: VCU118RocketSystem__GC0,
-case__922: RocketTile__GCB0,
-datapath__9: vcu118_rocket_top__GC0,
-logic__4600: FPU__GB2, FPU__GB1,
-case__1387: APBGpsBlock__GC0,
-reg__104: vcu118_rocket_top__GC0,
-logic__2562: DCache,
-case__1053: VCU118RocketSystem__GC0,
-reg__287: VCU118RocketSystem__GC0,
-logic__1824: VCU118RocketSystem__GC0,
-logic__1965: VCU118RocketSystem__GC0,
-datapath__500: VCU118RocketSystem__GC0,
-reg__218: VCU118RocketSystem__GC0,
-reg__406: RocketTile__GCB0,
-case__1029: VCU118RocketSystem__GC0,
-rom__5: APBGpsBlock__GC0,
-muxpart__66: vcu118_rocket_top__GC0,
-logic__7809: VCU118RocketSystem__GC0,
-logic__7127: VCU118RocketSystem__GC0,
-logic__6750: VCU118RocketSystem__GC0,
-TLInterconnectCoupler_pbus_to_gps: VCU118RocketSystem__GC0,
-extram__2: RocketTile__GCB0,
-logic__4519: FPU__GB1,
-reg__1401: TLToAPB,
-case__1373: APBGpsBlock__GC0,
-dsp48e2__38: tracking_wrapper,
-logic__5572: RocketTile__GCB0,
-logic__3073: RocketTile__GCB0,
-case__649: FPU__GB1,
-case__490: RocketTile__GCB0,
-case__1075: VCU118RocketSystem__GC0,
-datapath__238: VCU118RocketSystem__GC0,
-reg__998: VCU118RocketSystem__GC0,
-case__743: FPU__GB2,
-datapath__533: VCU118RocketSystem__GC0,
-reg__571: FPU__GB1,
-logic__3660: FPU__GB2, FPU__GB1,
-reg__1043: VCU118RocketSystem__GC0,
-logic__900: VCU118RocketSystem__GC0,
-logic__5870: RocketTile__GCB0,
-case__790: FPU__GB1,
-logic__1146: VCU118RocketSystem__GC0,
-datapath__266: RocketTile__GCB0,
-logic__6724: RocketTile__GCB0,
-reg__538: FPU__GB1,
-reg__303: VCU118RocketSystem__GC0,
-logic__285: vcu118_rocket_top__GC0,
-reg__955: VCU118RocketSystem__GC0,
-logic__9006: tracking_wrapper,
-dsp48e2__23: APBGpsBlock__GC0,
-reg__408: RocketTile__GCB0,
-datapath__456: RocketTile__GCB0,
-reg__470: FPU__GB0,
-reg__1304: tracking_wrapper,
-logic__3878: FPU__GB2,
-logic__14: vcu118_rocket_top__GC0,
-logic__9433: TLToAPB,
-logic__8508: APBGpsBlock__GC0,
-datapath__49: VCU118RocketSystem__GC0,
-reg__690: RocketTile__GCB0,
-logic__8759: APBGpsBlock__GC0,
-datapath__332: FPU__GB1,
-reg__540: FPU__GB1,
-logic__8983: tracking_wrapper,
-logic__4232: FPU__GB1,
-logic__5996: RocketTile__GCB0,
-logic__6656: RocketTile__GCB0,
-reg__612: FPU__GB1,
-case__479: VCU118RocketSystem__GC0,
-logic__8223: VCU118RocketSystem__GC0,
-reg__1168: APBGpsBlock__GC0,
-reg__644: FPU__GB1,
-case__855: RocketTile__GCB0,
-logic__266: vcu118_rocket_top__GC0,
-logic__1282: VCU118RocketSystem__GC0,
-reg__860: VCU118RocketSystem__GC0,
-logic__3881: FPU__GB2,
-logic__8709: APBGpsBlock__GC0,
-logic__7113: VCU118RocketSystem__GC0,
-logic__8212: VCU118RocketSystem__GC0,
-logic__1340: VCU118RocketSystem__GC0,
-case__1080: VCU118RocketSystem__GC0,
-reg__803: RocketTile__GCB0,
-logic__7419: VCU118RocketSystem__GC0,
-logic__1929: VCU118RocketSystem__GC0,
-logic__1466: VCU118RocketSystem__GC0,
-reg__130: VCU118RocketSystem__GC0,
-logic__9182: tracking_wrapper,
-logic__3966: FPU__GB2,
-logic__2939: DCache,
-case__30: vcu118_rocket_top__GC0,
-dsp48e2__29: tracking_wrapper,
-logic__3906: FPU__GB2,
-logic__5515: RocketTile__GCB0,
-logic__6578: RocketTile__GCB0,
-logic__4915: FPU__GB2,
-reg__1279: tracking_wrapper,
-addsub__6: tracking_wrapper,
-logic__1542: VCU118RocketSystem__GC0,
-muxpart__222: FPU__GB0,
-logic__6820: VCU118RocketSystem__GC0,
-logic__5992: RocketTile__GCB0,
-logic__8129: VCU118RocketSystem__GC0,
-case__579: RocketTile__GCB0,
-reg__794: RocketTile__GCB0,
-case__442: VCU118RocketSystem__GC0,
-logic__3077: RocketTile__GCB0,
-case__1205: VCU118RocketSystem__GC0,
-reg__899: VCU118RocketSystem__GC0,
-logic__3330: FPU__GB1,
-logic__1004: VCU118RocketSystem__GC0,
-logic__897: VCU118RocketSystem__GC0,
-logic__6644: RocketTile__GCB0,
-reg__1238: tracking_wrapper,
-logic__5742: RocketTile__GCB0,
-reg__1101: APBGpsBlock__GC0,
-datapath__574: APBGpsBlock__GC0,
-logic__4410: FPU__GB1,
-logic__5126: FPU__GB1,
-datapath__552: VCU118RocketSystem__GC0,
-reg__474: FPU__GB0,
-reg__534: FPU__GB1,
-reg__748: RocketTile__GCB0,
-case__1079: VCU118RocketSystem__GC0,
-case__457: VCU118RocketSystem__GC0,
-case__1228: VCU118RocketSystem__GC0,
-logic__7221: VCU118RocketSystem__GC0,
-reg__185: VCU118RocketSystem__GC0,
-reg__51: vcu118_rocket_top__GC0,
-logic__1905: VCU118RocketSystem__GC0,
-reg__1192: APBGpsBlock__GC0,
-logic__8686: APBGpsBlock__GC0,
-logic__139: vcu118_rocket_top__GC0,
-logic__997: VCU118RocketSystem__GC0,
-FPU__GB1: FPU__GB1,
-case__1086: VCU118RocketSystem__GC0,
-logic__3972: FPU__GB2,
-logic__7996: VCU118RocketSystem__GC0,
-case__353: VCU118RocketSystem__GC0,
-logic__4819: FPU__GB2,
-reg__956: VCU118RocketSystem__GC0,
-logic__798: VCU118RocketSystem__GC0,
-logic__6677: RocketTile__GCB0,
-logic__3100: RocketTile__GCB0,
-case__812: RocketTile__GCB0,
-logic__6528: RocketTile__GCB0,
-logic__7753: VCU118RocketSystem__GC0,
-logic__7069: VCU118RocketSystem__GC0,
-case__1021: VCU118RocketSystem__GC0,
-datapath__691: tracking_wrapper,
-logic__3514: FPU__GB1,
-logic__8929: tracking_wrapper,
-case__260: VCU118RocketSystem__GC0,
-case__203: vcu118_rocket_top__GC0,
-muxpart__80: vcu118_rocket_top__GC0,
-muxpart__212: FPU__GB0,
-logic__8943: tracking_wrapper,
-reg__270: VCU118RocketSystem__GC0,
-case__1138: VCU118RocketSystem__GC0,
-logic__4523: FPU__GB1,
-case__779: FPU__GB1,
-logic__8263: APBGpsBlock__GC0,
-logic__5524: RocketTile__GCB0,
-logic__8122: VCU118RocketSystem__GC0,
-reg__1277: tracking_wrapper,
-datapath__23: vcu118_rocket_top__GC0,
-logic__101: vcu118_rocket_top__GC0,
-logic__7053: VCU118RocketSystem__GC0,
-case__909: RocketTile__GCB0,
-logic__7759: VCU118RocketSystem__GC0,
-logic__1144: VCU118RocketSystem__GC0,
-datapath__357: FPU__GB2,
-logic__5090: FPU__GB1,
-reg__30: vcu118_rocket_top__GC0,
-logic__3691: FPU__GB2,
-logic__7117: VCU118RocketSystem__GC0,
-logic__2482: RocketTile__GCB0, DCache,
-logic__6831: VCU118RocketSystem__GC0,
-logic__983: VCU118RocketSystem__GC0,
-logic__943: VCU118RocketSystem__GC0,
-datapath__642: APBGpsBlock__GC0,
-case__930: RocketTile__GCB0,
-logic__4981: FPU__GB1,
-logic__3696: FPU__GB2,
-case__1141: VCU118RocketSystem__GC0,
-muxpart__201: FPU__GB0,
-signinv__2: APBGpsBlock__GC0,
-case__174: vcu118_rocket_top__GC0,
-logic__7048: VCU118RocketSystem__GC0,
-datapath__219: VCU118RocketSystem__GC0,
-reg__504: FPU__GB1,
-logic__1525: VCU118RocketSystem__GC0,
-muxpart__376: tracking_wrapper,
-muxpart__210: FPU__GB0,
-logic__7168: VCU118RocketSystem__GC0,
-logic__8439: APBGpsBlock__GC0,
-case__369: VCU118RocketSystem__GC0,
-logic__5866: RocketTile__GCB0,
-logic__2: vcu118_rocket_top__GC0,
-logic__7216: VCU118RocketSystem__GC0,
-logic__957: VCU118RocketSystem__GC0,
-keep__5: vcu118_rocket_top__GC0,
-case__209: vcu118_rocket_top__GC0,
-logic__4982: FPU__GB1,
-reg__262: VCU118RocketSystem__GC0,
-datapath__144: VCU118RocketSystem__GC0,
-datapath__401: FPU__GB2,
-case__881: RocketTile__GCB0,
-datapath__529: VCU118RocketSystem__GC0,
-logic__1488: VCU118RocketSystem__GC0,
-logic__5731: RocketTile__GCB0,
-case__959: RocketTile__GCB0,
-logic__2894: DCache,
-counter: vcu118_rocket_top__GC0,
-logic__1754: VCU118RocketSystem__GC0,
-logic__3686: FPU__GB2,
-logic__5730: RocketTile__GCB0,
-case__551: DCache,
-logic__7377: VCU118RocketSystem__GC0,
-datapath__210: VCU118RocketSystem__GC0,
-case__374: VCU118RocketSystem__GC0,
-logic__5471: RocketTile__GCB0,
-datapath__341: FPU__GB2,
-logic__8434: APBGpsBlock__GC0,
-reg__1037: VCU118RocketSystem__GC0,
-logic__8531: APBGpsBlock__GC0,
-logic__2689: DCache,
-case__1232: VCU118RocketSystem__GC0,
-reg__219: VCU118RocketSystem__GC0,
-logic__7038: VCU118RocketSystem__GC0,
-logic__1841: VCU118RocketSystem__GC0,
-logic__6685: RocketTile__GCB0,
-logic__5198: RocketTile__GCB0,
-muxpart__69: vcu118_rocket_top__GC0,
-logic__5658: RocketTile__GCB0,
-dsp48e2__10: APBGpsBlock__GC0,
-case__947: RocketTile__GCB0,
-reg__641: FPU__GB1,
-logic__5318: RocketTile__GCB0,
-case__162: vcu118_rocket_top__GC0,
-reg__1381: tracking_wrapper,
-logic__398: vcu118_rocket_top__GC0,
-reg__983: VCU118RocketSystem__GC0,
-case__368: VCU118RocketSystem__GC0,
-datapath__375: FPU__GB1,
-reg__493: FPU__GB1,
-logic__5294: RocketTile__GCB0,
-datapath__380: FPU__GB1,
-reg__715: RocketTile__GCB0,
-logic__5558: RocketTile__GCB0,
-dsp48e2__20: APBGpsBlock__GC0,
-case__876: RocketTile__GCB0,
-logic__8180: VCU118RocketSystem__GC0,
-logic__6187: RocketTile__GCB0,
-rom__2: APBGpsBlock__GC0,
-logic__3782: FPU__GB2,
-logic__1840: VCU118RocketSystem__GC0,
-logic__785: VCU118RocketSystem__GC0,
-reg__1242: tracking_wrapper,
-logic__9205: tracking_wrapper,
-reg__352: DCache,
-case__651: FPU__GB1,
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/e/elab.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/e/elab.rtd
deleted file mode 100644
index e013a1a..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/e/elab.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1220760385.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1220760385.rtd
deleted file mode 100644
index 9289538..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1220760385.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1220760385.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1220760385.rtd.straps.rtd
deleted file mode 100644
index ec2b996..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1220760385.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1220760385.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1220760385.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1220760385.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1220760385.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1220760385.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1294509424.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1294509424.rtd
deleted file mode 100644
index ac80bac..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1294509424.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1294509424.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1294509424.rtd.straps.rtd
deleted file mode 100644
index 9c1ba5e..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1294509424.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1294509424.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1294509424.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1294509424.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1294509424.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1294509424.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/136113302.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/136113302.rtd
deleted file mode 100644
index d9f011a..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/136113302.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/136113302.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/136113302.rtd.straps.rtd
deleted file mode 100644
index 0dda5e1..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/136113302.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/136113302.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/136113302.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/136113302.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/136113302.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/136113302.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1672436263.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1672436263.rtd
deleted file mode 100644
index cd23ea4..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1672436263.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1672436263.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1672436263.rtd.straps.rtd
deleted file mode 100644
index db06d2c..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1672436263.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1672436263.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1672436263.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1672436263.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1672436263.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/1672436263.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2438764479.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2438764479.rtd
deleted file mode 100644
index 9a2413e..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2438764479.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2438764479.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2438764479.rtd.straps.rtd
deleted file mode 100644
index 3f6db86..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2438764479.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2438764479.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2438764479.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2438764479.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2438764479.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2438764479.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2610937407.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2610937407.rtd
deleted file mode 100644
index 82bfd4e..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2610937407.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2610937407.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2610937407.rtd.straps.rtd
deleted file mode 100644
index b4f1fa9..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2610937407.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2610937407.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2610937407.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2610937407.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2610937407.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2610937407.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2737226844.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2737226844.rtd
deleted file mode 100644
index 2fb3bb2..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2737226844.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2737226844.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2737226844.rtd.straps.rtd
deleted file mode 100644
index 68d2b14..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2737226844.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2737226844.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2737226844.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2737226844.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2737226844.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2737226844.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2962621930.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2962621930.rtd
deleted file mode 100644
index 35eedca..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2962621930.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2962621930.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2962621930.rtd.straps.rtd
deleted file mode 100644
index 7dd0cf2..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2962621930.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2962621930.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2962621930.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2962621930.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2962621930.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/2962621930.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/3482045580.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/3482045580.rtd
deleted file mode 100644
index 8459167..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/3482045580.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/3482045580.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/3482045580.rtd.straps.rtd
deleted file mode 100644
index ae97144..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/3482045580.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/3482045580.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/3482045580.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/3482045580.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/3482045580.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/3482045580.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/944784429.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/944784429.rtd
deleted file mode 100644
index 3f6eba5..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/944784429.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/944784429.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/944784429.rtd.straps.rtd
deleted file mode 100644
index cbf2ba7..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/944784429.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/944784429.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/944784429.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/944784429.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/944784429.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/944784429.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/976197094.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/976197094.rtd
deleted file mode 100644
index 7780d21..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/976197094.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/976197094.rtd.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/976197094.rtd.straps.rtd
deleted file mode 100644
index bf13ed8..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/976197094.rtd.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/976197094.rtd.straps.rtd.pb b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/976197094.rtd.straps.rtd.pb
deleted file mode 100644
index b155e40..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/976197094.rtd.straps.rtd.pb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-
-
-End Record
\ No newline at end of file
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/976197094.rtd.straps.rtd.pb.log b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/976197094.rtd.straps.rtd.pb.log
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/global_name.straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/global_name.straps.rtd
deleted file mode 100644
index e710bd2..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/global_name.straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/instToEncGenName.map b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/instToEncGenName.map
deleted file mode 100644
index 9a94bf1..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/g/instToEncGenName.map
+++ /dev/null
@@ -1,19 +0,0 @@
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache:1672436263
-/u_rocket/fpga_gps_domain/dev/tracking_1:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_6:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_2:2962621930
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB0:1294509424
-/u_rocket/tile_prci_domain/TilePRCIDomain__GC0:1220760385
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB2:2737226844
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/RocketTile__GCB0:2610937407
-/u_rocket/fpga_gps_domain/tl2apb:3482045580
-/u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/FPU__GB1:976197094
-/u_rocket/fpga_gps_domain/dev/tracking_4:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_3:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_0:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_7:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_8:2962621930
-/u_rocket/fpga_gps_domain/dev/tracking_5:2962621930
-/u_rocket/VCU118RocketSystem__GC0:136113302
-/vcu118_rocket_top__GC0:944784429
-/u_rocket/fpga_gps_domain/dev/APBGpsBlock__GC0:2438764479
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/genomeDependencyGraph.out b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/genomeDependencyGraph.out
deleted file mode 100644
index e69de29..0000000
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/genomes.map b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/genomes.map
deleted file mode 100644
index cfa766a..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/genomes.map
+++ /dev/null
@@ -1,11 +0,0 @@
-FPU__GB0 829C10A0
-FPU__GB1 9ACCC7C0
-FPU__GB2 9ACCD5C0
-RocketTile__GCB0 6E0210C0
-DCache 6BD9BDC0
-TilePRCIDomain__GC0 A2F48880
-tracking_wrapper 6B840B80
-APBGpsBlock__GC0 83465020
-TLToAPB 6BD21860
-VCU118RocketSystem__GC0 B6EB5CA0
-vcu118_rocket_top__GC0 72B2BB00
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/genomes.txt b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/genomes.txt
deleted file mode 100644
index fd17ae6..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/genomes.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-FPU__GB0
-FPU__GB1
-FPU__GB2
-RocketTile__GCB0
-DCache
-TilePRCIDomain__GC0
-tracking_wrapper
-APBGpsBlock__GC0
-TLToAPB
-VCU118RocketSystem__GC0
-vcu118_rocket_top__GC0
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/parentModToGenomes.map b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/parentModToGenomes.map
deleted file mode 100644
index 0d2efbc..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/parentModToGenomes.map
+++ /dev/null
@@ -1,8 +0,0 @@
-vcu118_rocket_top: vcu118_rocket_top__GC0, TilePRCIDomain__GC0, TLToAPB, DCache, FPU__GB1, tracking_wrapper, FPU__GB2, VCU118RocketSystem__GC0, APBGpsBlock__GC0, FPU__GB0, RocketTile__GCB0,
-VCU118RocketSystem: TilePRCIDomain__GC0, TLToAPB, DCache, FPU__GB1, tracking_wrapper, FPU__GB2, VCU118RocketSystem__GC0, APBGpsBlock__GC0, FPU__GB0, RocketTile__GCB0,
-FPGAGPSClockSinkDomain: TLToAPB, APBGpsBlock__GC0, tracking_wrapper,
-APBGpsBlock: APBGpsBlock__GC0, tracking_wrapper,
-TilePRCIDomain: TilePRCIDomain__GC0, RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-HierarchicalElementResetDomain: RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-RocketTile: RocketTile__GCB0, FPU__GB2, FPU__GB1, FPU__GB0, DCache,
-FPU: FPU__GB2, FPU__GB1, FPU__GB0,
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/synthNameToElabName.map b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/synthNameToElabName.map
deleted file mode 100644
index 8c53321..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/synthNameToElabName.map
+++ /dev/null
@@ -1,8902 +0,0 @@
-datapath__13: datapath__13
-comp_mult: comp_mult
-muxpart__70: muxpart__70
-case__631: case__631
-datapath__674: datapath__674
-reg__379: reg__379
-datapath__372: datapath__372
-sync__1: sync
-logic__1211: logic__1211
-reg__607: reg__607
-spill_register_flushable: spill_register_flushable
-reg__29: reg__29
-muxpart__379: muxpart__379
-logic__1433: logic__1433
-logic__339: logic__339
-case__475: case__475
-logic__4971: logic__4971
-logic__8832: logic__8832
-logic__5448: logic__5448
-logic__6896: logic__6896
-TLWidthWidget8_1__2: TLWidthWidget8_1
-reg__176: reg__176
-logic__9646: logic__1140
-logic__1624: logic__1624
-logic__9475: logic__3659
-logic__1590: logic__1590
-reg__147: reg__147
-logic__2270: logic__2270
-datapath__84: datapath__84
-extrom__3: extrom
-logic__5736: logic__5736
-TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u: TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u
-logic__2153: logic__2153
-reg__426: reg__426
-RoundAnyRawFNToRecFN_3: RoundAnyRawFNToRecFN_3
-logic__6852: logic__6852
-datapath__756: datapath__688
-reg__1392: reg__1392
-lock_detector: lock_detector
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__21: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-datapath__582: datapath__582
-logic__5453: logic__5453
-Queue2_TLBundleD_a32d64s2k1z4u__1: Queue2_TLBundleD_a32d64s2k1z4u
-AsyncQueueSink_TLBundleA_a9d32s1k1z2u: AsyncQueueSink_TLBundleA_a9d32s1k1z2u
-muxpart__79: muxpart__79
-case__1625: case__1625
-logic__5412: logic__5412
-logic__3841: logic__3841
-reg__272: reg__272
-case__256: case__256
-logic__6674: logic__6674
-case__518: case__518
-logic__6042: logic__6042
-logic__9587: logic__8998
-logic__3805: logic__3805
-case__1294: case__1294
-muxpart__86: muxpart__86
-Queue2_TLBundleA_a32d64s2k1z4u: Queue2_TLBundleA_a32d64s2k1z4u
-case__630: case__630
-case__28: case__28
-logic__7354: logic__7354
-logic__1712: logic__1712
-reg__1143: reg__1143
-INToRecFN_1: INToRecFN_1
-case__885: case__885
-case__290: case__290
-datapath__474: datapath__474
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__6: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__253: reg__253
-case__168: case__168
-logic__4691: logic__4691
-logic__4524: logic__4524
-logic__7611: logic__7611
-reg__1099: reg__1099
-logic__7285: logic__7285
-case__183: case__183
-datapath__303: datapath__303
-case__1540: case__1540
-RoundRawFNToRecFN_1__1: RoundRawFNToRecFN_1
-logic__3491: logic__3491
-case__789: case__789
-reg__1458: reg__906
-reg__844: reg__844
-logic__31: logic__31
-logic__4400: logic__4400
-datapath__76: datapath__76
-reg__496: reg__496
-logic__8041: logic__8041
-datapath__737: datapath__387
-muxpart__10: muxpart__10
-logic__4696: logic__4696
-logic__6181: logic__6181
-reg__15: reg__15
-reg__702: reg__702
-case__1739: case__299
-reg__605: reg__605
-logic__6043: logic__6043
-muxpart__381: muxpart__381
-reg__1434: reg__1216
-logic__9519: logic__4617
-case__717: case__717
-case__682: case__682
-reg__548: reg__548
-reg__1066: reg__1066
-logic__8705: logic__8705
-case__135: case__135
-reg__1111: reg__1111
-reg__124: reg__124
-TLAsyncCrossingSource_a9d32s1k1z2u: TLAsyncCrossingSource_a9d32s1k1z2u
-logic__812: logic__812
-datapath__594: datapath__594
-reg__792: reg__792
-logic__129: logic__129
-logic__6818: logic__6818
-logic__3216: logic__3216
-reg__624: reg__624
-logic__670: logic__670
-logic__7691: logic__7691
-reg__1225: reg__1225
-reg__559: reg__559
-logic__7228: logic__7228
-logic__6801: logic__6801
-datapath__225: datapath__225
-datapath__593: datapath__593
-logic__2494: logic__2494
-case__1038: case__1038
-datapath__325: datapath__325
-datapath__370: datapath__370
-logic__5462: logic__5462
-logic__176: logic__176
-reg__793: reg__793
-logic__6791: logic__6791
-reg__1224: reg__1224
-logic__1297: logic__1297
-logic__6309: logic__6309
-logic__7520: logic__7520
-logic__9220: logic__9220
-logic__478: logic__478
-reg__1323: reg__1323
-logic__9407: logic__9407
-logic__5458: logic__5458
-logic__3897: logic__3897
-case__296: case__296
-logic__4920: logic__4920
-logic__3461: logic__3461
-reg__229: reg__229
-reg__43: reg__43
-TLXbar_cbus_in_i1_o1_a32d64s2k1z4u: TLXbar_cbus_in_i1_o1_a32d64s2k1z4u
-logic__3429: logic__3429
-logic__181: logic__181
-logic__4361: logic__4361
-reg__322: reg__322
-datapath__268: datapath__268
-datapath__147: datapath__147
-logic__3159: logic__3159
-case__1571: case__1571
-logic__9478: logic__3638
-reg__626: reg__626
-logic__9492: logic__3605
-reg__133: reg__133
-case__1440: case__1440
-case__961: case__961
-case__848: case__848
-logic__5647: logic__5647
-logic__8858: logic__8858
-datapath__716: datapath__716
-reg__1426: reg__1320
-logic__8808: logic__8808
-case__661: case__661
-logic__9367: logic__9367
-case__519: case__519
-logic__2274: logic__2274
-logic__5106: logic__5106
-logic__4021: logic__4021
-logic__6163: logic__6163
-AsyncResetSynchronizerShiftReg_w1_d3_i0__1: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__6947: logic__6947
-logic__6680: logic__6680
-logic__9611: logic__6774
-INToRecFN: INToRecFN
-datapath__335: datapath__335
-reg__1513: reg__908
-logic__3545: logic__3545
-logic__5307: logic__5307
-MulAddRecFNToRaw_postMul_1: MulAddRecFNToRaw_postMul_1
-case__152: case__152
-logic__6965: logic__6965
-case__1438: case__1438
-case__566: case__566
-logic__5507: logic__5507
-logic__7174: logic__7174
-logic__3531: logic__3531
-reg__343: reg__343
-logic__2990: logic__2990
-case__796: case__796
-logic__7349: logic__7349
-logic__5529: logic__5529
-logic__7989: logic__7989
-case__949: case__949
-logic__2669: logic__2669
-logic__9624: logic__6769
-logic__929: logic__929
-case__639: case__639
-reg__990: reg__990
-reg__57: reg__57
-datapath__133: datapath__133
-datapath__230: datapath__230
-case__688: case__688
-logic__5178: logic__5178
-muxpart__207: muxpart__207
-logic__3489: logic__3489
-logic__9221: logic__9221
-logic__5478: logic__5478
-reg__1350: reg__1350
-reg__1519: reg__908
-case__379: case__379
-case__1500: case__1500
-case__652: case__652
-binary_to_gray: binary_to_gray
-case__987: case__987
-reg__420: reg__420
-logic__9648: logic__1138
-logic__7429: logic__7429
-logic__2004: logic__2004
-logic__8811: logic__8811
-reg__52: reg__52
-logic__801: logic__801
-logic__8592: logic__8592
-logic__7040: logic__7040
-datapath__259: datapath__259
-FixedClockBroadcast_5: FixedClockBroadcast_5
-case__706: case__706
-logic__6301: logic__6301
-addsub__4: addsub__4
-case__428: case__428
-case__1487: case__1487
-case__207: case__207
-case__1064: case__1064
-logic__741: logic__741
-datapath__11: datapath__11
-reg__536: reg__536
-case__69: case__69
-logic__3313: logic__3313
-counter__16: counter__16
-ram_2x78: ram_2x78
-logic__2621: logic__2621
-logic__4433: logic__4433
-logic__5304: logic__5304
-case__1582: case__1582
-datapath__129: datapath__129
-logic__9166: logic__9166
-logic__5653: logic__5653
-datapath__629: datapath__629
-datapath__657: datapath__657
-datapath__713: datapath__713
-logic__5459: logic__5459
-logic__4337: logic__4337
-case__666: case__666
-datapath__288: datapath__288
-logic__4399: logic__4399
-case__1156: case__1156
-datapath__237: datapath__237
-datapath__6: datapath__6
-logic__9488: logic__3614
-reg__77: reg__77
-reg__1442: reg__1069
-reg__136: reg__136
-logic__7412: logic__7412
-muxpart__83: muxpart__83
-muxpart__51: muxpart__51
-logic__8011: logic__8011
-AsyncValidSync__14: AsyncValidSync
-logic__5418: logic__5418
-logic__4442: logic__4442
-logic__2643: logic__2643
-case__1008: case__1008
-case__1003: case__1003
-logic__8955: logic__8955
-logic__4101: logic__4101
-case__650: case__650
-RoundRawFNToRecFN_1: RoundRawFNToRecFN_1
-logic__271: logic__271
-logic__3553: logic__3553
-logic__6135: logic__6135
-logic__8003: logic__8003
-TLInterconnectCoupler_cbus_to_bus_named_pbus: TLInterconnectCoupler_cbus_to_bus_named_pbus
-datapath__270: datapath__270
-case__901: case__901
-logic__3341: logic__3341
-logic__1576: logic__1576
-logic__2158: logic__2158
-muxpart__221: muxpart__221
-logic__8051: logic__8051
-datapath__766: datapath__124
-logic__5053: logic__5053
-case__1545: case__1545
-reg__901: reg__901
-logic__2277: logic__2277
-logic__6063: logic__6063
-logic__506: logic__506
-logic__7398: logic__7398
-logic__7199: logic__7199
-logic__6179: logic__6179
-muxpart__3: muxpart__3
-logic__9088: logic__9088
-datapath__184: datapath__184
-logic__1903: logic__1903
-case__229: case__229
-datapath__611: datapath__611
-logic__2966: logic__2966
-reg__747: reg__747
-rockettile_dcache_data_arrays_0_131072x64: rockettile_dcache_data_arrays_0_131072x64
-reg__68: reg__68
-logic__1639: logic__1639
-logic__9023: logic__9023
-logic__5650: logic__5650
-datapath__31: datapath__31
-logic__6930: logic__6930
-logic__2623: logic__2623
-logic__5944: logic__5944
-case__1705: case__732
-logic__7772: logic__7772
-reg__222: reg__222
-reg__188: reg__188
-logic__5525: logic__5525
-reg__898: reg__898
-logic__3117: logic__3117
-logic__8879: logic__8879
-addsub__9: addsub__4
-case__919: case__919
-datapath__122: datapath__122
-case__228: case__228
-case__898: case__898
-logic__2549: logic__2549
-logic__270: logic__270
-logic__7220: logic__7220
-reg__725: reg__725
-keep__40: keep__12
-sync__7: sync
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__2: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__1022: reg__1022
-logic__863: logic__863
-logic__3093: logic__3093
-logic__8418: logic__8418
-tracking_wrapper: tracking_wrapper
-logic__8933: logic__8933
-logic__4387: logic__4387
-case__886: case__886
-logic__4213: logic__4213
-reg__54: reg__54
-logic__1036: logic__1036
-reg__1498: reg__908
-reg__1173: reg__1173
-logic__6477: logic__6477
-reg__1377: reg__1377
-logic__3765: logic__3765
-reg__304: reg__304
-case__1741: case__297
-logic__9634: logic__1166
-logic__6051: logic__6051
-reg__1439: reg__1069
-logic__3680: logic__3680
-reg__1294: reg__1294
-datapath__722: datapath__722
-reg__1473: reg__906
-logic__3872: logic__3872
-reg__1293: reg__1293
-logic__8704: logic__8704
-logic__9572: logic__934
-logic__6910: logic__6910
-logic__3788: logic__3788
-logic__4707: logic__4707
-case__703: case__703
-logic__6730: logic__6730
-logic__4481: logic__4481
-logic__831: logic__831
-reg__6: reg__6
-logic__8118: logic__8118
-logic__5172: logic__5172
-MulAddRecFNToRaw_preMul_1: MulAddRecFNToRaw_preMul_1
-logic__3016: logic__3016
-gray_to_binary__1: gray_to_binary
-RoundAnyRawFNToRecFN_1: RoundAnyRawFNToRecFN_1
-TLXbar_cbus_out_i1_o7_a32d64s2k1z4u: TLXbar_cbus_out_i1_o7_a32d64s2k1z4u
-logic__3283: logic__3283
-logic__4821: logic__4821
-extrom__4: extrom__1
-logic__7341: logic__7341
-reg__132: reg__132
-logic__672: logic__672
-logic__1461: logic__1461
-case__16: case__16
-ram__16: ram
-reg__1445: reg__1069
-logic__2834: logic__2834
-counter__15: counter__15
-logic__5319: logic__5319
-logic__7074: logic__7074
-reg__1560: reg__237
-logic__2975: logic__2975
-logic__9197: logic__9197
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__11: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__915: case__915
-logic__1080: logic__1080
-logic__2259: logic__2259
-muxpart__208: muxpart__208
-reg__289: reg__289
-reg__673: reg__673
-case__767: case__767
-logic__3985: logic__3985
-logic__3227: logic__3227
-muxpart__90: muxpart__90
-logic__3252: logic__3252
-case__533: case__533
-logic__913: logic__913
-datapath__589: datapath__589
-logic__1145: logic__1145
-signinv__1: signinv__1
-logic__8773: logic__8773
-case__1262: case__1262
-logic__619: logic__619
-logic__6299: logic__6299
-logic__4390: logic__4390
-logic__5367: logic__5367
-case__1340: case__1340
-muxpart__358: muxpart__358
-logic__940: logic__940
-datapath__480: datapath__480
-reg__1309: reg__1309
-case__1133: case__1133
-logic__9594: logic__8794
-case__182: case__182
-reg__614: reg__614
-reg__768: reg__768
-reg__1425: reg__1321
-logic__2723: logic__2723
-logic__4830: logic__4830
-logic__5482: logic__5482
-logic__3411: logic__3411
-logic__7249: logic__7249
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__28: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__9239: logic__9239
-reg__1319: reg__1319
-reg__1534: reg__908
-logic__1294: logic__1294
-case__1292: case__1292
-logic__114: logic__114
-dsp48e2__26: dsp48e2__26
-AsyncResetSynchronizerShiftReg_w1_d3_i0__2: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__1923: logic__1923
-logic__8745: logic__8745
-logic__5199: logic__5199
-reg__866: reg__866
-logic__1789: logic__1789
-divider__parameterized0: divider__parameterized0
-logic__5061: logic__5061
-datapath__327: datapath__327
-logic__2923: logic__2923
-logic__6923: logic__6923
-muxpart__197: muxpart__197
-reg__928: reg__928
-TLFpgaUART: TLFpgaUART
-datapath__75: datapath__75
-reg__727: reg__727
-reg__16: reg__16
-datapath__244: datapath__244
-logic__5638: logic__5638
-logic__4250: logic__4250
-keep__21: keep__13
-logic__5983: logic__5983
-logic__3251: logic__3251
-logic__9641: logic__1150
-logic__9384: logic__9384
-logic__3112: logic__3112
-datapath__322: datapath__322
-logic__4693: logic__4693
-logic__7210: logic__7210
-reg__660: reg__660
-dsp48e2__30: dsp48e2__30
-logic__7359: logic__7359
-logic__802: logic__802
-datapath__633: datapath__633
-logic__9235: logic__9235
-reg__1280: reg__1280
-reg__1409: reg__121
-logic__4428: logic__4428
-reg__1235: reg__1235
-datapath__545: datapath__545
-logic__7588: logic__7588
-logic__7231: logic__7231
-reg__788: reg__788
-case__238: case__238
-datapath__443: datapath__443
-case__1661: case__1661
-logic__5144: logic__5144
-case__1698: case__657
-logic__3424: logic__3424
-DivSqrtRecFN_small_1: DivSqrtRecFN_small_1
-case__57: case__57
-reg__664: reg__664
-case__1118: case__1118
-reg__230: reg__230
-addsub__1: addsub__1
-case__854: case__854
-reg__1576: reg__117
-logic__6157: logic__6157
-logic__3458: logic__3458
-logic__6859: logic__6859
-datapath__661: datapath__661
-reg__1520: reg__907
-logic__4898: logic__4898
-case__619: case__619
-logic__7648: logic__7648
-reg__183: reg__183
-case__863: case__863
-logic__6654: logic__6654
-datapath__597: datapath__597
-datapath__12: datapath__12
-logic__9209: logic__9209
-case__1024: case__1024
-logic__780: logic__780
-datapath__621: datapath__621
-logic__7545: logic__7545
-logic__1924: logic__1924
-datapath__569: datapath__569
-reg__502: reg__502
-logic__5491: logic__5491
-logic__3497: logic__3497
-logic__6679: logic__6679
-reg__295: reg__295
-logic__2389: logic__2389
-ram_2x77__3: ram_2x77
-logic__9515: logic__4625
-logic__9597: logic__8795
-counter__24: counter__24
-logic__9559: logic__2500
-datapath__142: datapath__142
-reg__1331: reg__1331
-logic__8442: logic__8442
-reg__694: reg__694
-logic__4402: logic__4402
-reg__377: reg__377
-logic__8941: logic__8941
-logic__8998: logic__8998
-logic__6768: logic__6768
-case__1489: case__1489
-reg__1166: reg__1166
-case__764: case__764
-logic__8267: logic__8267
-logic__5957: logic__5957
-case__815: case__815
-case__219: case__219
-logic__9596: logic__8792
-logic__7441: logic__7441
-reg__1252: reg__1252
-logic__4254: logic__4254
-logic__2872: logic__2872
-logic__2848: logic__2848
-logic__8123: logic__8123
-case__137: case__137
-muxpart__191: muxpart__191
-reg__1096: reg__1096
-logic__1558: logic__1558
-case__1621: case__1621
-logic__5119: logic__5119
-reg__655: reg__655
-logic__2982: logic__2982
-counter__2: counter__2
-reg__931: reg__931
-reg__1573: reg__120
-logic__6134: logic__6134
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__13: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__626: case__626
-logic__7599: logic__7599
-case__1078: case__1078
-logic__1874: logic__1874
-logic__6178: logic__6178
-logic__2559: logic__2559
-datapath__304: datapath__304
-case__960: case__960
-logic__9383: logic__9383
-logic__3425: logic__3425
-logic__8355: logic__8355
-eth_rf_vcu118: eth_rf_vcu118
-reg__4: reg__4
-logic__8838: logic__8838
-logic__9138: logic__9138
-case__1249: case__1249
-logic__2796: logic__2796
-logic__1: logic__1
-reg__1064: reg__1064
-datapath__69: datapath__69
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__3: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-TLFragmenter_Debug: TLFragmenter_Debug
-logic__9658: logic__930
-logic__237: logic__237
-datapath__515: datapath__515
-case__882: case__882
-TLBuffer_a29d64s2k1z3u__1: TLBuffer_a29d64s2k1z3u
-case__456: case__456
-logic__2683: logic__2683
-counter__19: counter__19
-muxpart__100: muxpart__100
-datapath__668: datapath__668
-datapath__194: datapath__194
-muxpart__5: muxpart__5
-logic__9660: logic__926
-muxpart__42: muxpart__42
-logic__106: logic__106
-logic__8137: logic__8137
-case__1588: case__1588
-logic__6572: logic__6572
-case__1166: case__1166
-counter__23: counter__23
-logic__1845: logic__1845
-logic__9530: logic__4597
-reg__3: reg__3
-logic__8232: logic__8232
-case__1679: case__1679
-case__242: case__242
-logic__9520: logic__4614
-reg__636: reg__636
-AsyncValidSync__11: AsyncValidSync
-datapath__213: datapath__213
-reg__1100: reg__1100
-case__1712: case__724
-AsyncValidSync__22: AsyncValidSync
-datapath__535: datapath__535
-case__787: case__787
-reg__509: reg__509
-reg__720: reg__720
-logic__6169: logic__6169
-logic__5674: logic__5674
-logic__4990: logic__4990
-logic__1336: logic__1336
-logic__1187: logic__1187
-case__301: case__301
-case__576: case__576
-case__516: case__516
-ClockCrossingReg_w43: ClockCrossingReg_w43
-reg__587: reg__587
-case__19: case__19
-logic__7107: logic__7107
-logic__7963: logic__7963
-logic__6808: logic__6808
-logic__4919: logic__4919
-logic__3736: logic__3736
-logic__4618: logic__4618
-logic__5303: logic__5303
-logic__756: logic__756
-logic__479: logic__479
-case__10: case__10
-logic__9034: logic__9034
-Repeater_TLBundleA_a17d64s2k1z3u: Repeater_TLBundleA_a17d64s2k1z3u
-logic__9547: logic__2524
-logic__3720: logic__3720
-muxpart__176: muxpart__176
-case__167: case__167
-logic__459: logic__459
-datapath__77: datapath__77
-case__1084: case__1084
-reg__249: reg__249
-case__1302: case__1302
-logic__6144: logic__6144
-reg__751: reg__751
-logic__9507: logic__4659
-case__1076: case__1076
-case__514: case__514
-logic__8060: logic__8060
-case__635: case__635
-logic__5010: logic__5010
-reg__467: reg__467
-case__18: case__18
-case__434: case__434
-logic__1469: logic__1469
-case__1391: case__1391
-reg__609: reg__609
-logic__8043: logic__8043
-datapath__599: datapath__599
-reg__1159: reg__1159
-reg__994: reg__994
-reg__572: reg__572
-SystemBus: SystemBus
-logic__3007: logic__3007
-case__392: case__392
-reg__1416: reg__200
-logic__617: logic__617
-logic__3697: logic__3697
-logic__3687: logic__3687
-logic__4421: logic__4421
-datapath__55: datapath__55
-logic__948: logic__948
-reg__111: reg__111
-logic__5732: logic__5732
-case__866: case__866
-logic__6620: logic__6620
-logic__5561: logic__5561
-case__1050: case__1050
-case__1321: case__1321
-reg__689: reg__689
-logic__5345: logic__5345
-logic__1298: logic__1298
-datapath__207: datapath__207
-CLINT: CLINT
-reg__168: reg__168
-reg__456: reg__456
-logic__972: logic__972
-logic__6004: logic__6004
-logic__5366: logic__5366
-case__1112: case__1112
-logic__5607: logic__5607
-logic__6789: logic__6789
-logic__1657: logic__1657
-logic__2095: logic__2095
-reg__610: reg__610
-logic__6691: logic__6691
-reg__831: reg__831
-datapath__47: datapath__47
-logic__6190: logic__6190
-logic__5940: logic__5940
-logic__3857: logic__3857
-logic__1453: logic__1453
-logic__8817: logic__8817
-muxpart__234: muxpart__234
-logic__2600: logic__2600
-logic__3304: logic__3304
-reg__1042: reg__1042
-logic__7480: logic__7480
-logic__3763: logic__3763
-logic__8443: logic__8443
-logic__4427: logic__4427
-case__440: case__440
-logic__1474: logic__1474
-logic__5411: logic__5411
-reg__736: reg__736
-logic__5766: logic__5766
-datapath__393: datapath__393
-logic__4782: logic__4782
-case__1681: case__1681
-case__1009: case__1009
-logic__6671: logic__6671
-logic__2914: logic__2914
-logic__2220: logic__2220
-logic__7173: logic__7173
-logic__1316: logic__1316
-IntSyncSyncCrossingSink_n1x1: IntSyncSyncCrossingSink_n1x1
-logic__790: logic__790
-case__1028: case__1028
-logic__4483: logic__4483
-reg__126: reg__126
-case__269: case__269
-muxpart__34: muxpart__34
-case__1542: case__1542
-logic__3606: logic__3606
-case__416: case__416
-logic__2098: logic__2098
-logic__3329: logic__3329
-logic__6349: logic__6349
-muxpart__183: muxpart__183
-logic__2601: logic__2601
-reg__1069: reg__1069
-reg__584: reg__584
-logic__4302: logic__4302
-case__153: case__153
-logic__7679: logic__7679
-reg__274: reg__274
-keep__38: keep__14
-reg__648: reg__648
-logic__5301: logic__5301
-reg__1336: reg__1336
-logic__2517: logic__2517
-reg__1047: reg__1047
-case__1022: case__1022
-reg__1264: reg__1264
-datapath__100: datapath__100
-logic__5284: logic__5284
-logic__9127: logic__9127
-case__218: case__218
-gig_ethernet_pcs_pma_0: gig_ethernet_pcs_pma_0
-logic__2010: logic__2010
-logic__1175: logic__1175
-logic__3257: logic__3257
-reg__1221: reg__1221
-reg__1194: reg__1194
-case__1496: case__1496
-logic__7514: logic__7514
-TLXbar_fbus_i1_o1_a32d64s1k1z4u: TLXbar_fbus_i1_o1_a32d64s1k1z4u
-logic__4388: logic__4388
-reg__300: reg__300
-logic__6648: logic__6648
-logic__5982: logic__5982
-reg__1160: reg__1160
-logic__4862: logic__4862
-reg__1179: reg__1179
-keep__3: keep__3
-logic__137: logic__137
-logic__2686: logic__2686
-logic__7402: logic__7402
-case__835: case__835
-case__1587: case__1587
-reg__1149: reg__1149
-datapath__197: datapath__197
-case__132: case__132
-case__486: case__486
-logic__7155: logic__7155
-case__856: case__856
-logic__4174: logic__4174
-datapath__669: datapath__669
-reg__1033: reg__1033
-logic__1361: logic__1361
-logic__5603: logic__5603
-dual_port_bram__parameterized1: dual_port_bram__parameterized1
-muxpart__224: muxpart__224
-reg__433: reg__433
-logic__6596: logic__6596
-logic__5054: logic__5054
-logic__791: logic__791
-logic__1982: logic__1982
-logic__9180: logic__9180
-logic__9599: logic__8793
-logic__7821: logic__7821
-logic__9613: logic__6774
-case__1569: case__1569
-logic__9017: logic__9017
-logic__766: logic__766
-datapath__471: datapath__471
-case__471: case__471
-logic__8764: logic__8764
-datapath__605: datapath__605
-case__484: case__484
-ram_2x120__1: ram_2x120
-datapath__89: datapath__89
-muxpart__276: muxpart__276
-datapath__336: datapath__336
-reg__812: reg__812
-logic__6651: logic__6651
-datapath__627: datapath__627
-datapath__399: datapath__399
-datapath__660: datapath__660
-datapath__127: datapath__127
-logic__1043: logic__1043
-logic__5166: logic__5166
-keep__31: keep__12
-logic__5754: logic__5754
-datapath__701: datapath__701
-logic__7403: logic__7403
-case__862: case__862
-logic__1875: logic__1875
-case__1367: case__1367
-case__370: case__370
-reg__189: reg__189
-reg__160: reg__160
-logic__5872: logic__5872
-reg__341: reg__341
-counter__3: counter__3
-datapath__771: datapath__45
-logic__882: logic__882
-case__1004: case__1004
-datapath__241: datapath__241
-reg__399: reg__399
-reg__1311: reg__1311
-case__291: case__291
-reg__85: reg__85
-logic__2536: logic__2536
-reg__1490: reg__907
-reg__298: reg__298
-reg__265: reg__265
-logic__683: logic__683
-logic__6041: logic__6041
-logic__2885: logic__2885
-logic__4829: logic__4829
-logic__1786: logic__1786
-logic__9210: logic__9210
-case__1388: case__1388
-case__1559: case__1559
-logic__1120: logic__1120
-reg__158: reg__158
-logic__3635: logic__3635
-datapath__741: datapath__44
-datapath__80: datapath__80
-logic__6914: logic__6914
-case__1479: case__1479
-case__1696: case__660
-logic__6690: logic__6690
-case__124: case__124
-reg__833: reg__833
-reg__1346: reg__1346
-reg__396: reg__396
-logic__4578: logic__4578
-logic__465: logic__465
-case__306: case__306
-logic__3275: logic__3275
-logic__5979: logic__5979
-reg__1228: reg__1228
-case__31: case__31
-logic__4834: logic__4834
-logic__716: logic__716
-logic__2183: logic__2183
-case__197: case__197
-logic__9595: logic__8793
-muxpart__198: muxpart__198
-case__338: case__338
-logic__2754: logic__2754
-logic__8241: logic__8241
-logic__7887: logic__7887
-logic__6027: logic__6027
-case__1570: case__1570
-logic__3045: logic__3045
-logic__5074: logic__5074
-logic__4286: logic__4286
-logic__6715: logic__6715
-ClockCrossingReg_w15: ClockCrossingReg_w15
-logic__930: logic__930
-reg__972: reg__972
-logic__4987: logic__4987
-reg__1430: reg__1216
-case__23: case__23
-case__326: case__326
-ClockGroupAggregator_pbus__1: ClockGroupAggregator_pbus
-muxpart__15: muxpart__15
-case__1719: case__1598
-reg__630: reg__630
-case__1425: case__1425
-logic__2957: logic__2957
-case__954: case__954
-case__670: case__670
-logic__9575: logic__1316
-reg__88: reg__88
-logic__4477: logic__4477
-case__1505: case__1505
-reg__757: reg__757
-reg__1051: reg__1051
-reg__753: reg__753
-reg__821: reg__821
-logic__9387: logic__9387
-case__711: case__711
-datapath__366: datapath__366
-logic__4970: logic__4970
-logic__6678: logic__6678
-reg__1027: reg__1027
-reg__986: reg__986
-reg__453: reg__453
-reg__468: reg__468
-case__1656: case__1656
-logic__5646: logic__5646
-logic__8826: logic__8826
-datapath__522: datapath__522
-reg__206: reg__206
-Queue2_TLBundleA_a32d64s1k1z4u: Queue2_TLBundleA_a32d64s1k1z4u
-logic__4422: logic__4422
-logic__6165: logic__6165
-reg__487: reg__487
-reg__651: reg__651
-case__1416: case__1416
-logic__8170: logic__8170
-logic__5956: logic__5956
-logic__3418: logic__3418
-logic__7581: logic__7581
-logic__4278: logic__4278
-logic__8526: logic__8526
-datapath__590: datapath__590
-case__1170: case__1170
-logic__7758: logic__7758
-datapath__645: datapath__645
-case__1103: case__1103
-datapath__161: datapath__161
-logic__4921: logic__4921
-case__307: case__307
-logic__2521: logic__2521
-reg__1553: reg__856
-reg__1577: reg__116
-datapath__64: datapath__64
-logic__300: logic__300
-reg__1010: reg__1010
-case__216: case__216
-logic__90: logic__90
-datapath__378: datapath__378
-reg__475: reg__475
-logic__4802: logic__4802
-logic__4326: logic__4326
-case__240: case__240
-case__1580: case__1580
-logic__6688: logic__6688
-datapath__728: datapath__728
-logic__8956: logic__8956
-datapath__762: datapath__166
-logic__8930: logic__8930
-case__133: case__133
-reg__50: reg__50
-logic__3535: logic__3535
-logic__65: logic__65
-datapath__665: datapath__665
-datapath__240: datapath__240
-logic__4418: logic__4418
-logic__8281: logic__8281
-FixedClockBroadcast_1__1: FixedClockBroadcast_1
-case__494: case__494
-datapath__354: datapath__354
-case__709: case__709
-case__1282: case__1282
-logic__8216: logic__8216
-rom__7: rom__7
-logic__1261: logic__1261
-logic__5249: logic__5249
-datapath__461: datapath__461
-reg__666: reg__666
-logic__6988: logic__6988
-logic__7538: logic__7538
-logic__3586: logic__3586
-logic__958: logic__958
-logic__4086: logic__4086
-logic__173: logic__173
-datapath__433: datapath__433
-reg__439: reg__439
-reg__120: reg__120
-case__605: case__605
-logic__4246: logic__4246
-TLFIFOFixer_2: TLFIFOFixer_2
-reg__604: reg__604
-case__1612: case__1612
-LevelGateway__6: LevelGateway
-logic__7882: logic__7882
-logic__9486: logic__3618
-logic__9607: logic__8144
-logic__4593: logic__4593
-case__308: case__308
-case__1070: case__1070
-logic__3863: logic__3863
-logic__6792: logic__6792
-case__1177: case__1177
-logic__1570: logic__1570
-logic__6115: logic__6115
-logic__7335: logic__7335
-case__740: case__740
-logic__4684: logic__4684
-case__1734: case__304
-AsyncValidSync__23: AsyncValidSync
-logic__3846: logic__3846
-addsub__5: addsub__5
-logic__1740: logic__1740
-logic__7182: logic__7182
-logic__9139: logic__9139
-reg__1115: reg__1115
-logic__5508: logic__5508
-reg__232: reg__232
-datapath__109: datapath__109
-TLXbar_sbus_i2_o1_a32d64s2k1z4u: TLXbar_sbus_i2_o1_a32d64s2k1z4u
-logic__6097: logic__6097
-case__857: case__857
-case__1199: case__1199
-logic__3060: logic__3060
-case__745: case__745
-case__584: case__584
-logic__319: logic__319
-reg__1011: reg__1011
-case__1114: case__1114
-reg__948: reg__948
-muxpart__99: muxpart__99
-datapath__245: datapath__245
-logic__9563: logic__2488
-muxpart__12: muxpart__12
-datapath__484: datapath__484
-case__1361: case__1361
-reg__450: reg__450
-logic__9423: logic__9423
-reg__159: reg__159
-logic__965: logic__965
-case__1512: case__1512
-logic__6098: logic__6098
-logic__9573: logic__930
-logic__2808: logic__2808
-datapath__434: datapath__434
-case__805: case__805
-reg__1048: reg__1048
-logic__4747: logic__4747
-logic__6686: logic__6686
-logic__6858: logic__6858
-logic__1351: logic__1351
-logic__4530: logic__4530
-datapath__296: datapath__296
-logic__1674: logic__1674
-case__587: case__587
-logic__4928: logic__4928
-logic__5439: logic__5439
-logic__3190: logic__3190
-logic__3308: logic__3308
-logic__6184: logic__6184
-datapath__667: datapath__667
-reg__936: reg__936
-logic__4639: logic__4639
-logic__8770: logic__8770
-datapath__364: datapath__364
-case__1093: case__1093
-muxpart__227: muxpart__227
-reg__1349: reg__1349
-case__1116: case__1116
-datapath__70: datapath__70
-logic__4033: logic__4033
-logic__773: logic__773
-reg__107: reg__107
-case__1697: case__659
-vcu118_rocket_top__GC0: vcu118_rocket_top__GC0
-datapath__524: datapath__524
-logic__8932: logic__8932
-reg__593: reg__593
-logic__9540: logic__4543
-logic__3629: logic__3629
-case__178: case__178
-logic__1665: logic__1665
-logic__6068: logic__6068
-logic__3037: logic__3037
-logic__5583: logic__5583
-logic__9052: logic__9052
-case__1229: case__1229
-reg__1283: reg__1283
-logic__8928: logic__8928
-Queue2_TLBundleD_a32d64s2k1z4u: Queue2_TLBundleD_a32d64s2k1z4u
-logic__1864: logic__1864
-logic__2938: logic__2938
-case__1375: case__1375
-FixedClockBroadcast_4: FixedClockBroadcast_4
-logic__4445: logic__4445
-case__540: case__540
-muxpart__182: muxpart__182
-case__889: case__889
-logic__69: logic__69
-logic__4863: logic__4863
-reg__555: reg__555
-LevelGateway__8: LevelGateway
-logic__1436: logic__1436
-logic__1037: logic__1037
-case__1174: case__1174
-logic__5341: logic__5341
-muxpart__82: muxpart__82
-reg__186: reg__186
-ram__1: ram__1
-logic__4036: logic__4036
-logic__7062: logic__7062
-case__488: case__488
-reg__463: reg__463
-logic__2812: logic__2812
-reg__243: reg__243
-logic__6567: logic__6567
-logic__5542: logic__5542
-ram__6: ram__6
-logic__814: logic__814
-logic__9348: logic__9348
-case__826: case__826
-datapath__559: datapath__559
-reg__749: reg__749
-reg__12: reg__12
-logic__7735: logic__7735
-logic__9533: logic__4594
-reg__329: reg__329
-case__217: case__217
-logic__3307: logic__3307
-logic__7002: logic__7002
-reg__109: reg__109
-reg__946: reg__946
-reg__238: reg__238
-reg__777: reg__777
-logic__2445: logic__2445
-reg__1035: reg__1035
-logic__3001: logic__3001
-logic__8543: logic__8543
-logic__3698: logic__3698
-logic__6563: logic__6563
-logic__6076: logic__6076
-logic__2238: logic__2238
-case__455: case__455
-reg__442: reg__442
-logic__9429: logic__9429
-logic__9523: logic__4607
-case__1600: case__1600
-reg__687: reg__687
-datapath__222: datapath__222
-case__1492: case__1492
-logic__2127: logic__2127
-datapath__575: datapath__575
-logic__8854: logic__8854
-AsyncValidSync__5: AsyncValidSync
-logic__9163: logic__9163
-reg__780: reg__780
-case__852: case__852
-logic__174: logic__174
-reg__440: reg__440
-logic__408: logic__408
-logic__6837: logic__6837
-logic__1350: logic__1350
-logic__1291: logic__1291
-logic__4978: logic__4978
-reg__1333: reg__1333
-reg__392: reg__392
-reg__1056: reg__1056
-muxpart__254: muxpart__254
-logic__5964: logic__5964
-logic__9176: logic__9176
-case__730: case__730
-logic__3621: logic__3621
-logic__5601: logic__5601
-logic__5829: logic__5829
-logic__3310: logic__3310
-case__501: case__501
-case__333: case__333
-logic__1625: logic__1625
-muxpart__6: muxpart__6
-logic__9431: logic__9431
-case__1094: case__1094
-case__437: case__437
-reg__1062: reg__1062
-case__1168: case__1168
-datapath__188: datapath__188
-case__1180: case__1180
-datapath__310: datapath__310
-logic__6072: logic__6072
-logic__4689: logic__4689
-reg__364: reg__364
-logic__7187: logic__7187
-case__754: case__754
-logic__7685: logic__7685
-case__331: case__331
-reg__1375: reg__1375
-logic__740: logic__740
-reg__573: reg__573
-keep__45: keep__8
-logic__7900: logic__7900
-logic__4599: logic__4599
-logic__2878: logic__2878
-reg__1429: reg__1216
-case__1281: case__1281
-datapath__166: datapath__166
-logic__5666: logic__5666
-plusarg_reader: plusarg_reader
-muxpart__367: muxpart__367
-case__921: case__921
-logic__7283: logic__7283
-muxpart__264: muxpart__264
-datapath__301: datapath__301
-case__978: case__978
-logic__6077: logic__6077
-logic__6344: logic__6344
-logic__2017: logic__2017
-logic__1176: logic__1176
-logic__952: logic__952
-datapath__617: datapath__617
-logic__5566: logic__5566
-logic__9470: logic__9470
-DMIToTL: DMIToTL
-case__1664: case__1664
-logic__4934: logic__4934
-logic__5346: logic__5346
-logic__5825: logic__5825
-reg__451: reg__451
-sync__2: sync
-logic__5536: logic__5536
-case__1036: case__1036
-logic__7851: logic__7851
-case__689: case__689
-logic__6994: logic__6994
-case__255: case__255
-logic__6698: logic__6698
-logic__1406: logic__1406
-logic__8746: logic__8746
-reg__787: reg__787
-logic__5976: logic__5976
-reg__1085: reg__1085
-logic__1040: logic__1040
-case__241: case__241
-reg__608: reg__608
-logic__9490: logic__3610
-reg__595: reg__595
-case__797: case__797
-reg__361: reg__361
-muxpart__377: muxpart__377
-datapath__694: datapath__694
-reg__1207: reg__1207
-logic__3740: logic__3740
-logic__3299: logic__3299
-reg__499: reg__499
-logic__9132: logic__9132
-logic__6626: logic__6626
-logic__6868: logic__6868
-logic__5621: logic__5621
-datapath__673: datapath__673
-reg__621: reg__621
-case__335: case__335
-datapath__651: datapath__651
-logic__6661: logic__6661
-dsp48e2__39: dsp48e2__39
-ErrorDeviceWrapper: ErrorDeviceWrapper
-logic__3413: logic__3413
-datapath__154: datapath__154
-logic__5358: logic__5358
-logic__5300: logic__5300
-eth_rf_async_fifo: eth_rf_async_fifo
-reg__1128: reg__1128
-cordic_atan_one_stage__parameterized0__1: cordic_atan_one_stage__parameterized0
-logic__9135: logic__9135
-muxpart__56: muxpart__56
-reg__378: reg__378
-logic__5137: logic__5137
-case__874: case__874
-logic__7801: logic__7801
-logic__2451: logic__2451
-logic__9126: logic__9126
-reg__261: reg__261
-logic__3264: logic__3264
-case__1129: case__1129
-logic__9609: logic__6774
-muxpart__185: muxpart__185
-reg__1007: reg__1007
-logic__1748: logic__1748
-logic__2172: logic__2172
-case__778: case__778
-logic__1895: logic__1895
-datapath__646: datapath__646
-case__224: case__224
-reg__1186: reg__1186
-logic__4867: logic__4867
-logic__4465: logic__4465
-case__40: case__40
-logic__6034: logic__6034
-reg__1484: reg__907
-reg__518: reg__518
-logic__6943: logic__6943
-logic__4314: logic__4314
-case__1214: case__1214
-reg__155: reg__155
-logic__7839: logic__7839
-case__74: case__74
-muxpart__94: muxpart__94
-datapath__586: datapath__586
-logic__7999: logic__7999
-logic__2497: logic__2497
-case__1417: case__1417
-logic__3121: logic__3121
-logic__5734: logic__5734
-logic__7119: logic__7119
-logic__6632: logic__6632
-muxpart__375: muxpart__375
-case__363: case__363
-TLInterconnectCoupler_fbus_from_debug_sb: TLInterconnectCoupler_fbus_from_debug_sb
-case__974: case__974
-case__357: case__357
-reg__1561: reg__156
-datapath__400: datapath__400
-case__825: case__825
-logic__9484: logic__3622
-case__17: case__17
-logic__7716: logic__7716
-case__822: case__822
-logic__3023: logic__3023
-logic__9439: logic__9439
-keep__29: keep__14
-reg__39: reg__39
-logic__6170: logic__6170
-logic__3764: logic__3764
-reg__119: reg__119
-logic__978: logic__978
-case__832: case__832
-case__879: case__879
-logic__7011: logic__7011
-reg__1136: reg__1136
-reg__1499: reg__907
-logic__4986: logic__4986
-reg__1256: reg__1256
-logic__5538: logic__5538
-logic__5752: logic__5752
-logic__2044: logic__2044
-logic__1393: logic__1393
-case__147: case__147
-logic__4486: logic__4486
-case__63: case__63
-LevelGateway__2: LevelGateway
-logic__7022: logic__7022
-logic__3643: logic__3643
-logic__1465: logic__1465
-dsp48e2__22: dsp48e2__22
-case__1169: case__1169
-case__1115: case__1115
-logic__3890: logic__3890
-logic__7686: logic__7686
-reg__939: reg__939
-logic__2554: logic__2554
-case__1414: case__1414
-logic__2940: logic__2940
-logic__9315: logic__9315
-reg__449: reg__449
-reg__1057: reg__1057
-logic__8844: logic__8844
-reg__632: reg__632
-logic__1123: logic__1123
-logic__5686: logic__5686
-datapath__267: datapath__267
-reg__1006: reg__1006
-TLXbar_pbus_in_i1_o1_a29d64s2k1z3u: TLXbar_pbus_in_i1_o1_a29d64s2k1z3u
-logic__1537: logic__1537
-logic__7299: logic__7299
-logic__1693: logic__1693
-case__884: case__884
-dsp48e2__5: dsp48e2__5
-logic__7024: logic__7024
-case__1662: case__1662
-case__497: case__497
-case__7: case__7
-logic__7346: logic__7346
-logic__9191: logic__9191
-reg__1449: reg__1068
-case__1213: case__1213
-reg__896: reg__896
-logic__2555: logic__2555
-case__491: case__491
-logic__1869: logic__1869
-datapath__220: datapath__220
-logic__8595: logic__8595
-reg__144: reg__144
-case__1278: case__1278
-case__1119: case__1119
-logic__9480: logic__3632
-logic__858: logic__858
-reg__843: reg__843
-bram__parameterized0: bram__parameterized0
-logic__7300: logic__7300
-reg__878: reg__878
-datapath__199: datapath__199
-reg__237: reg__237
-logic__4744: logic__4744
-logic__4312: logic__4312
-datapath__534: datapath__534
-case__721: case__721
-logic__3321: logic__3321
-reg__628: reg__628
-logic__5429: logic__5429
-datapath__684: datapath__684
-dsp48e2__35: dsp48e2__35
-logic__72: logic__72
-reg__1509: reg__906
-reg__1041: reg__1041
-reg__146: reg__146
-extram__8: extram__8
-logic__4111: logic__4111
-reg__72: reg__72
-logic__4415: logic__4415
-reg__464: reg__464
-logic__909: logic__909
-logic__9373: logic__9373
-reg__141: reg__141
-logic__9329: logic__9329
-case__64: case__64
-case__575: case__575
-twiddle_ram__1: twiddle_ram
-case__1120: case__1120
-logic__1237: logic__1237
-logic__6075: logic__6075
-reg__1227: reg__1227
-logic__2523: logic__2523
-reg__400: reg__400
-logic__5847: logic__5847
-logic__9279: logic__9279
-AsyncValidSync__4: AsyncValidSync
-logic__6922: logic__6922
-case__528: case__528
-reg__42: reg__42
-logic__3534: logic__3534
-datapath__748: datapath__138
-datapath__112: datapath__112
-datapath__382: datapath__382
-logic__8135: logic__8135
-case__131: case__131
-muxpart__357: muxpart__357
-divider_fsm: divider_fsm
-datapath__397: datapath__397
-logic__5631: logic__5631
-logic__6113: logic__6113
-reg__1181: reg__1181
-logic__4914: logic__4914
-logic__9615: logic__6774
-logic__7428: logic__7428
-logic__9046: logic__9046
-case__782: case__782
-case__543: case__543
-logic__2868: logic__2868
-datapath__139: datapath__139
-logic__1249: logic__1249
-logic__3632: logic__3632
-case__1257: case__1257
-datapath__757: datapath__687
-reg__418: reg__418
-case__602: case__602
-case__873: case__873
-datapath__192: datapath__192
-logic__8473: logic__8473
-reg__1478: reg__907
-logic__1174: logic__1174
-reg__1109: reg__1109
-dsp48e2__32: dsp48e2__32
-datapath__647: datapath__647
-logic__8036: logic__8036
-logic__1247: logic__1247
-reg__454: reg__454
-reg__1126: reg__1126
-datapath__720: datapath__720
-logic__3295: logic__3295
-eth_rf_core: eth_rf_core
-logic__5239: logic__5239
-case__1548: case__1548
-Queue1_TLBundleA_a14d64s2k1z4u: Queue1_TLBundleA_a14d64s2k1z4u
-case__294: case__294
-reg__1118: reg__1118
-logic__264: logic__264
-case__695: case__695
-reg__1345: reg__1345
-muxpart__57: muxpart__57
-logic__1349: logic__1349
-logic__919: logic__919
-case__746: case__746
-reg__774: reg__774
-reg__1486: reg__908
-logic__2376: logic__2376
-keep__53: keep__8
-FPU__GB2: FPU__GB2
-logic__6861: logic__6861
-logic__357: logic__357
-reg__616: reg__616
-logic__7815: logic__7815
-logic__2652: logic__2652
-logic__7179: logic__7179
-case__526: case__526
-case__29: case__29
-datapath__604: datapath__604
-reg__1491: reg__906
-logic__9167: logic__9167
-case__536: case__536
-extrom: extrom
-case__979: case__979
-datapath__95: datapath__95
-logic__5125: logic__5125
-reg__1107: reg__1107
-case__1113: case__1113
-AsyncResetSynchronizerShiftReg_w1_d3_i0__7: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__4969: logic__4969
-logic__9525: logic__4602
-reg__212: reg__212
-logic__1169: logic__1169
-case__1002: case__1002
-logic__2001: logic__2001
-logic__1667: logic__1667
-case__236: case__236
-logic__8213: logic__8213
-reg__282: reg__282
-logic__3638: logic__3638
-logic__2377: logic__2377
-logic__9051: logic__9051
-case__336: case__336
-reg__547: reg__547
-reg__376: reg__376
-AsyncValidSync__10: AsyncValidSync
-bram: bram
-case__657: case__657
-logic__2245: logic__2245
-logic__1487: logic__1487
-datapath__700: datapath__700
-logic__9391: logic__9391
-reg__358: reg__358
-reg__996: reg__996
-keep__28: keep__12
-reg__766: reg__766
-logic__5426: logic__5426
-reg__1334: reg__1334
-logic__9334: logic__9334
-logic__4283: logic__4283
-reg__1328: reg__1328
-logic__3182: logic__3182
-logic__4607: logic__4607
-reg__1428: reg__1216
-reg__671: reg__671
-logic__7327: logic__7327
-logic__1628: logic__1628
-datapath__557: datapath__557
-reg__823: reg__823
-mult_46_15_61__3: mult_46_15_61
-datapath__337: datapath__337
-logic__4610: logic__4610
-datapath__48: datapath__48
-datapath__618: datapath__618
-case__432: case__432
-case__714: case__714
-case__532: case__532
-datapath__239: datapath__239
-logic__6851: logic__6851
-logic__926: logic__926
-case__282: case__282
-reg__765: reg__765
-logic__82: logic__82
-logic__9461: logic__9461
-TLFragmenter_1: TLFragmenter_1
-logic__4659: logic__4659
-logic__8600: logic__8600
-reg__180: reg__180
-logic__2472: logic__2472
-muxpart__204: muxpart__204
-logic__1580: logic__1580
-reg__786: reg__786
-logic__6980: logic__6980
-case__1098: case__1098
-logic__9356: logic__9356
-reg__296: reg__296
-reg__154: reg__154
-reg__1374: reg__1374
-reg__888: reg__888
-case__503: case__503
-logic__5116: logic__5116
-datapath__343: datapath__343
-case__1608: case__1608
-reg__932: reg__932
-reg__1276: reg__1276
-logic__5465: logic__5465
-reg__1575: reg__118
-case__692: case__692
-keep__4: keep__4
-logic__3339: logic__3339
-logic__1343: logic__1343
-logic__9528: logic__4599
-Queue2_TLBundleD_a29d64s2k1z3u: Queue2_TLBundleD_a29d64s2k1z3u
-dsp48e2__24: dsp48e2__24
-case__995: case__995
-muxpart__259: muxpart__259
-logic__7437: logic__7437
-reg__617: reg__617
-logic__1758: logic__1758
-reg__532: reg__532
-logic__3555: logic__3555
-AsyncValidSync__1: AsyncValidSync
-logic__8138: logic__8138
-datapath__179: datapath__179
-muxpart__268: muxpart__268
-case__509: case__509
-logic__7066: logic__7066
-reg__412: reg__412
-case__831: case__831
-muxpart__39: muxpart__39
-logic__9536: logic__4578
-logic__6936: logic__6936
-logic__1716: logic__1716
-logic__6631: logic__6631
-logic__3197: logic__3197
-logic__1181: logic__1181
-logic__5224: logic__5224
-case__465: case__465
-logic__9344: logic__9344
-reg__597: reg__597
-logic__4253: logic__4253
-logic__8354: logic__8354
-logic__2865: logic__2865
-logic__728: logic__728
-case__611: case__611
-muxpart__17: muxpart__17
-reg__927: reg__927
-logic__3787: logic__3787
-logic__6530: logic__6530
-logic__425: logic__425
-logic__1493: logic__1493
-datapath__416: datapath__416
-logic__6897: logic__6897
-logic__1640: logic__1640
-logic__6112: logic__6112
-logic__8422: logic__8422
-logic__5978: logic__5978
-logic__3932: logic__3932
-logic__7717: logic__7717
-case__646: case__646
-logic__5520: logic__5520
-reg__86: reg__86
-logic__9535: logic__4587
-reg__771: reg__771
-logic__5540: logic__5540
-logic__329: logic__329
-mult_30_25_55: mult_30_25_55
-logic__8192: logic__8192
-logic__7029: logic__7029
-logic__1821: logic__1821
-logic__8265: logic__8265
-logic__5480: logic__5480
-case__78: case__78
-reg__1038: reg__1038
-case__1441: case__1441
-case__1645: case__1645
-logic__6126: logic__6126
-reg__704: reg__704
-datapath__735: datapath__389
-extrom__5: extrom
-logic__3516: logic__3516
-logic__6520: logic__6520
-reg__215: reg__215
-keep__14: keep__14
-reg__633: reg__633
-reg__758: reg__758
-case__821: case__821
-logic__2725: logic__2725
-reg__511: reg__511
-logic__1275: logic__1275
-dsp48e2__34: dsp48e2__34
-logic__8866: logic__8866
-reg__1015: reg__1015
-reg__1232: reg__1232
-case__239: case__239
-datapath__42: datapath__42
-TLFIFOFixer_1: TLFIFOFixer_1
-logic__6111: logic__6111
-logic__1885: logic__1885
-datapath__243: datapath__243
-reg__988: reg__988
-logic__6066: logic__6066
-logic__3088: logic__3088
-datapath__517: datapath__517
-datapath__215: datapath__215
-datapath__131: datapath__131
-logic__3328: logic__3328
-dsp48e2__2: dsp48e2__2
-logic__8266: logic__8266
-case__1693: case__1693
-logic__8868: logic__8868
-case__846: case__846
-reg__596: reg__596
-case__989: case__989
-Repeater_TLBundleD_a32d64s1k1z4u: Repeater_TLBundleD_a32d64s1k1z4u
-datapath__383: datapath__383
-muxpart__61: muxpart__61
-case__9: case__9
-reg__138: reg__138
-case__872: case__872
-muxpart__170: muxpart__170
-case__777: case__777
-reg__677: reg__677
-logic__2429: logic__2429
-logic__1987: logic__1987
-logic__2491: logic__2491
-reg__1451: reg__1045
-case__1066: case__1066
-logic__2485: logic__2485
-muxpart__13: muxpart__13
-case__502: case__502
-case__591: case__591
-reg__96: reg__96
-reg__1114: reg__1114
-logic__9464: logic__9464
-reg__70: reg__70
-reg__1472: reg__907
-case__776: case__776
-logic__1253: logic__1253
-logic__4845: logic__4845
-logic__3416: logic__3416
-logic__9586: logic__8999
-muxpart__249: muxpart__249
-case__1728: case__1589
-logic__2945: logic__2945
-logic__2448: logic__2448
-logic__8726: logic__8726
-logic__4407: logic__4407
-logic__2265: logic__2265
-logic__4625: logic__4625
-logic__7243: logic__7243
-logic__7230: logic__7230
-muxpart__203: muxpart__203
-case__844: case__844
-case__1394: case__1394
-muxpart__267: muxpart__267
-reg__525: reg__525
-logic__4327: logic__4327
-counter__12: counter__12
-logic__3316: logic__3316
-case__1578: case__1578
-reg__703: reg__703
-logic__4259: logic__4259
-keep__39: keep__13
-logic__9293: logic__9293
-logic__3780: logic__3780
-datapath__231: datapath__231
-logic__246: logic__246
-datapath__208: datapath__208
-logic__3116: logic__3116
-datapath__699: datapath__699
-case__1068: case__1068
-reg__942: reg__942
-acq_peak_srch: acq_peak_srch
-case__1258: case__1258
-case__654: case__654
-logic__4209: logic__4209
-datapath__465: datapath__465
-case__46: case__46
-datapath__462: datapath__462
-reg__1058: reg__1058
-datapath__22: datapath__22
-logic__4544: logic__4544
-muxpart__266: muxpart__266
-logic__5993: logic__5993
-logic__3917: logic__3917
-ram__7: ram__7
-case__996: case__996
-logic__2816: logic__2816
-logic__2392: logic__2392
-logic__7088: logic__7088
-reg__69: reg__69
-logic__8598: logic__8598
-reg__1201: reg__1201
-logic__4537: logic__4537
-logic__9512: logic__4634
-logic__391: logic__391
-logic__5509: logic__5509
-reg__447: reg__447
-case__999: case__999
-logic__6824: logic__6824
-logic__7278: logic__7278
-logic__7418: logic__7418
-case__418: case__418
-logic__6058: logic__6058
-logic__4835: logic__4835
-reg__405: reg__405
-case__327: case__327
-case__1589: case__1589
-logic__2746: logic__2746
-logic__979: logic__979
-case__1372: case__1372
-reg__1009: reg__1009
-logic__3335: logic__3335
-logic__9025: logic__9025
-case__713: case__713
-logic__3499: logic__3499
-reg__1539: reg__906
-logic__2041: logic__2041
-logic__1391: logic__1391
-logic__7019: logic__7019
-case__1104: case__1104
-reg__961: reg__961
-logic__4833: logic__4833
-reg__1492: reg__908
-datapath__598: datapath__598
-datapath__591: datapath__591
-RecFNToRecFN: RecFNToRecFN
-case__1105: case__1105
-logic__7385: logic__7385
-case__814: case__814
-case__1437: case__1437
-logic__5888: logic__5888
-logic__1545: logic__1545
-logic__5310: logic__5310
-logic__8960: logic__8960
-muxpart__242: muxpart__242
-logic__4420: logic__4420
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__10: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__1798: logic__1798
-logic__262: logic__262
-reg__910: reg__910
-logic__9265: logic__9265
-muxpart__196: muxpart__196
-logic__3218: logic__3218
-logic__7649: logic__7649
-logic__1817: logic__1817
-CSRFile: CSRFile
-logic__9264: logic__9264
-TLWidthWidget8_4: TLWidthWidget8_4
-reg__501: reg__501
-logic__4836: logic__4836
-logic__2227: logic__2227
-reg__401: reg__401
-reg__575: reg__575
-reg__1005: reg__1005
-logic__9277: logic__9277
-logic__2875: logic__2875
-datapath__128: datapath__128
-logic__7864: logic__7864
-case__983: case__983
-butterfly__parameterized0: butterfly__parameterized0
-logic__7576: logic__7576
-case__232: case__232
-logic__3507: logic__3507
-logic__7340: logic__7340
-logic__4478: logic__4478
-logic__5578: logic__5578
-logic__3410: logic__3410
-logic__6128: logic__6128
-TLBuffer_a32d64s1k1z4u__1: TLBuffer_a32d64s1k1z4u
-logic__4756: logic__4756
-logic__6862: logic__6862
-logic__6089: logic__6089
-case__1318: case__1318
-logic__4695: logic__4695
-logic__8242: logic__8242
-logic__5994: logic__5994
-logic__5036: logic__5036
-logic__7729: logic__7729
-logic__3099: logic__3099
-logic__5417: logic__5417
-logic__4295: logic__4295
-reg__393: reg__393
-case__1623: case__1623
-logic__2833: logic__2833
-reg__1444: reg__1067
-logic__245: logic__245
-logic__5687: logic__5687
-logic__8689: logic__8689
-logic__5718: logic__5718
-datapath__91: datapath__91
-datapath__685: datapath__685
-logic__6553: logic__6553
-case__684: case__684
-case__1139: case__1139
-logic__257: logic__257
-reg__1065: reg__1065
-reg__308: reg__308
-logic__3933: logic__3933
-case__286: case__286
-logic__3543: logic__3543
-case__571: case__571
-logic__5906: logic__5906
-logic__5138: logic__5138
-reg__1356: reg__1356
-logic__9266: logic__9266
-logic__3708: logic__3708
-reg__919: reg__919
-ram__14: ram__1
-muxpart__97: muxpart__97
-reg__263: reg__263
-case__1564: case__1564
-datapath__544: datapath__544
-logic__1820: logic__1820
-logic__5532: logic__5532
-logic__5614: logic__5614
-logic__827: logic__827
-logic__8913: logic__8913
-logic__6570: logic__6570
-muxpart__102: muxpart__102
-muxpart__310: muxpart__310
-reg__503: reg__503
-logic__2007: logic__2007
-logic__3282: logic__3282
-datapath__469: datapath__469
-logic__5194: logic__5194
-logic__8215: logic__8215
-keep__49: keep__8
-logic__2150: logic__2150
-logic__8881: logic__8881
-logic__5021: logic__5021
-LevelGateway__7: LevelGateway
-case__810: case__810
-logic__9588: logic__8995
-reg__1395: reg__1395
-reg__1406: reg__1406
-logic__9353: logic__9353
-case__663: case__663
-reg__858: reg__858
-case__384: case__384
-reg__966: reg__966
-logic__1703: logic__1703
-logic__4602: logic__4602
-logic__1804: logic__1804
-case__22: case__22
-datapath__217: datapath__217
-case__427: case__427
-logic__5626: logic__5626
-logic__8730: logic__8730
-case__1666: case__1666
-reg__568: reg__568
-logic__3325: logic__3325
-reg__1248: reg__1248
-case__799: case__799
-logic__3965: logic__3965
-logic__2228: logic__2228
-case__1535: case__1535
-logic__7336: logic__7336
-logic__7383: logic__7383
-case__934: case__934
-case__1517: case__1517
-logic__494: logic__494
-logic__7575: logic__7575
-reg__920: reg__920
-case__893: case__893
-logic__375: logic__375
-case__37: case__37
-case__1602: case__1602
-datapath__419: datapath__419
-logic__7918: logic__7918
-logic__3437: logic__3437
-case__1552: case__1552
-reg__1462: reg__908
-logic__9498: logic__3599
-datapath__316: datapath__316
-logic__1395: logic__1395
-logic__6024: logic__6024
-logic__5945: logic__5945
-case__632: case__632
-reg__1368: reg__1368
-logic__5398: logic__5398
-case__263: case__263
-datapath__320: datapath__320
-logic__6687: logic__6687
-logic__1930: logic__1930
-muxpart__229: muxpart__229
-logic__2607: logic__2607
-logic__7888: logic__7888
-case__1151: case__1151
-logic__5118: logic__5118
-reg__662: reg__662
-case__1568: case__1568
-logic__3766: logic__3766
-logic__3604: logic__3604
-datapath__318: datapath__318
-TLInterconnectCoupler_cbus_to_bootrom: TLInterconnectCoupler_cbus_to_bootrom
-logic__5463: logic__5463
-logic__1107: logic__1107
-logic__3490: logic__3490
-datapath__113: datapath__113
-reg__320: reg__320
-logic__178: logic__178
-logic__7978: logic__7978
-logic__4298: logic__4298
-logic__3457: logic__3457
-reg__284: reg__284
-logic__8029: logic__8029
-logic__9656: logic__935
-case__1546: case__1546
-datapath__417: datapath__417
-datapath__516: datapath__516
-logic__1656: logic__1656
-reg__1566: reg__151
-logic__4973: logic__4973
-logic__5447: logic__5447
-reg__862: reg__862
-logic__1736: logic__1736
-logic__2839: logic__2839
-reg__1308: reg__1308
-case__769: case__769
-case__943: case__943
-logic__3663: logic__3663
-datapath__387: datapath__387
-logic__9362: logic__9362
-muxpart__98: muxpart__98
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__18: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__778: reg__778
-reg__817: reg__817
-case__788: case__788
-reg__1199: reg__1199
-reg__73: reg__73
-logic__6755: logic__6755
-logic__8536: logic__8536
-muxpart__265: muxpart__265
-logic__2256: logic__2256
-reg__1497: reg__906
-case__477: case__477
-logic__9513: logic__4631
-logic__3938: logic__3938
-datapath__314: datapath__314
-logic__7722: logic__7722
-keep__30: keep__13
-logic__426: logic__426
-reg__500: reg__500
-reg__923: reg__923
-datapath__137: datapath__137
-datapath__176: datapath__176
-reg__941: reg__941
-case__659: case__659
-double_ff_syn__5: double_ff_syn
-reg__692: reg__692
-datapath__572: datapath__572
-logic__8291: logic__8291
-reg__665: reg__665
-case__276: case__276
-case__1574: case__1574
-logic__9010: logic__9010
-logic__3533: logic__3533
-logic__7913: logic__7913
-ClockSinkDomain: ClockSinkDomain
-logic__9024: logic__9024
-logic__8419: logic__8419
-logic__6033: logic__6033
-reg__712: reg__712
-logic__6813: logic__6813
-logic__1234: logic__1234
-logic__7814: logic__7814
-logic__3704: logic__3704
-logic__5073: logic__5073
-reg__1150: reg__1150
-logic__5105: logic__5105
-datapath__202: datapath__202
-reg__428: reg__428
-logic__4203: logic__4203
-case__1590: case__1590
-datapath__65: datapath__65
-datapath__193: datapath__193
-datapath__724: datapath__724
-logic__5602: logic__5602
-logic__1658: logic__1658
-logic__3774: logic__3774
-logic__365: logic__365
-case__1549: case__1549
-case__1230: case__1230
-logic__4299: logic__4299
-logic__2022: logic__2022
-logic__934: logic__934
-TLToAPB: TLToAPB
-Queue2_TLBundleA_a29d64s2k1z3u__1: Queue2_TLBundleA_a29d64s2k1z3u
-logic__5381: logic__5381
-logic__9028: logic__9028
-logic__2192: logic__2192
-case__523: case__523
-datapath__253: datapath__253
-logic__3893: logic__3893
-datapath__216: datapath__216
-logic__9181: logic__9181
-reg__455: reg__455
-logic__6630: logic__6630
-logic__7661: logic__7661
-case__500: case__500
-logic__4404: logic__4404
-logic__4594: logic__4594
-logic__7302: logic__7302
-reg__859: reg__859
-reg__129: reg__129
-datapath__14: datapath__14
-reg__953: reg__953
-logic__9635: logic__1165
-logic__4866: logic__4866
-case__655: case__655
-logic__3816: logic__3816
-logic__5406: logic__5406
-datapath__566: datapath__566
-logic__9330: logic__9330
-logic__7893: logic__7893
-logic__7728: logic__7728
-logic__3035: logic__3035
-logic__3934: logic__3934
-logic__1058: logic__1058
-logic__1047: logic__1047
-case__212: case__212
-logic__6860: logic__6860
-datapath__475: datapath__475
-logic__3087: logic__3087
-logic__5354: logic__5354
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__4: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__814: reg__814
-PLICFanIn: PLICFanIn
-datapath__610: datapath__610
-logic__6849: logic__6849
-logic__3703: logic__3703
-reg__711: reg__711
-logic__4955: logic__4955
-reg__318: reg__318
-logic__2476: logic__2476
-logic__6121: logic__6121
-logic__2255: logic__2255
-reg__302: reg__302
-datapath__420: datapath__420
-reg__108: reg__108
-DivSqrtRecFNToRaw_small_1: DivSqrtRecFNToRaw_small_1
-logic__9602: logic__8794
-case__780: case__780
-reg__1372: reg__1372
-datapath__761: datapath__548
-logic__8088: logic__8088
-datapath__361: datapath__361
-logic__9193: logic__9193
-logic__8121: logic__8121
-case__483: case__483
-datapath__187: datapath__187
-logic__3623: logic__3623
-logic__3618: logic__3618
-logic__3427: logic__3427
-logic__1578: logic__1578
-reg__739: reg__739
-muxpart__200: muxpart__200
-keep__32: keep__14
-logic__873: logic__873
-case__561: case__561
-logic__8359: logic__8359
-case__1219: case__1219
-logic__5340: logic__5340
-logic__7582: logic__7582
-logic__7557: logic__7557
-reg__317: reg__317
-datapath__451: datapath__451
-logic__4484: logic__4484
-logic__7631: logic__7631
-reg__1089: reg__1089
-datapath__409: datapath__409
-logic__9485: logic__3621
-logic__3487: logic__3487
-cordic_atan_basic__parameterized0: cordic_atan_basic__parameterized0
-logic__7790: logic__7790
-logic__6722: logic__6722
-datapath__19: datapath__19
-case__1194: case__1194
-logic__8530: logic__8530
-logic__4300: logic__4300
-logic__5759: logic__5759
-logic__6000: logic__6000
-case__998: case__998
-logic__515: logic__515
-case__55: case__55
-logic__9600: logic__8792
-reg__1284: reg__1284
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__27: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__3031: logic__3031
-logic__5123: logic__5123
-logic__6303: logic__6303
-logic__7741: logic__7741
-datapath__29: datapath__29
-logic__7507: logic__7507
-counter__34: counter__28
-reg__481: reg__481
-datapath__612: datapath__612
-reg__1412: reg__204
-case__923: case__923
-reg__1001: reg__1001
-datapath__727: datapath__727
-logic__3804: logic__3804
-logic__977: logic__977
-muxpart__213: muxpart__213
-logic__1702: logic__1702
-reg__1234: reg__1234
-datapath__738: datapath__386
-logic__2030: logic__2030
-logic__5233: logic__5233
-logic__5934: logic__5934
-case__772: case__772
-logic__7973: logic__7973
-reg__259: reg__259
-reg__767: reg__767
-logic__6676: logic__6676
-logic__3094: logic__3094
-datapath__135: datapath__135
-logic__9333: logic__9333
-logic__6806: logic__6806
-case__1396: case__1396
-logic__9278: logic__9278
-case__1644: case__1644
-datapath__189: datapath__189
-reg__1415: reg__201
-case__75: case__75
-case__1245: case__1245
-reg__231: reg__231
-case__274: case__274
-case__1691: case__1691
-logic__6822: logic__6822
-reg__1140: reg__1140
-logic__5128: logic__5128
-case__198: case__198
-case__1323: case__1323
-logic__7061: logic__7061
-datapath__658: datapath__658
-RoundAnyRawFNToRecFN: RoundAnyRawFNToRecFN
-logic__7215: logic__7215
-logic__1394: logic__1394
-reg__314: reg__314
-reg__1495: reg__908
-logic__9057: logic__9057
-logic__5567: logic__5567
-case__361: case__361
-logic__3480: logic__3480
-logic__5022: logic__5022
-case__581: case__581
-keep__1: keep__1
-logic__7380: logic__7380
-case__348: case__348
-case__1738: case__300
-logic__9604: logic__8792
-TLBuffer_a29d64s2k1z3u: TLBuffer_a29d64s2k1z3u
-case__693: case__693
-logic__8295: logic__8295
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__19: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-cos2x: cos2x
-logic__9584: logic__9006
-case__4: case__4
-logic__4357: logic__4357
-reg__1393: reg__1393
-datapath__450: datapath__450
-reg__524: reg__524
-keep__48: keep__9
-datapath__681: datapath__681
-reg__639: reg__639
-logic__4854: logic__4854
-case__1215: case__1215
-logic__9651: logic__1131
-reg__1208: reg__1208
-logic__2558: logic__2558
-logic__7992: logic__7992
-datapath__196: datapath__196
-logic__3011: logic__3011
-reg__448: reg__448
-logic__3989: logic__3989
-logic__6367: logic__6367
-datapath__30: datapath__30
-datapath__104: datapath__104
-case__34: case__34
-datapath__275: datapath__275
-logic__6361: logic__6361
-reg__1405: reg__1405
-reg__911: reg__911
-reg__1571: reg__146
-logic__5528: logic__5528
-logic__1262: logic__1262
-counter__30: counter__30
-logic__5231: logic__5231
-logic__2616: logic__2616
-logic__878: logic__878
-muxpart__184: muxpart__184
-case__489: case__489
-reg__1441: reg__1067
-reg__58: reg__58
-datapath__510: datapath__510
-dsp48e2__19: dsp48e2__19
-cdc_fifo_gray: cdc_fifo_gray
-reg__484: reg__484
-logic__8937: logic__8937
-reg__462: reg__462
-case__1609: case__1609
-reg__781: reg__781
-acq_wrapper: acq_wrapper
-case__1288: case__1288
-reg__67: reg__67
-reg__971: reg__971
-case__472: case__472
-reg__1040: reg__1040
-logic__7838: logic__7838
-logic__9653: logic__1124
-logic__9393: logic__9393
-logic__4957: logic__4957
-logic__2304: logic__2304
-logic__1160: logic__1160
-reg__785: reg__785
-logic__3320: logic__3320
-logic__8968: logic__8968
-reg__1164: reg__1164
-logic__8999: logic__8999
-reg__1269: reg__1269
-LevelGateway__9: LevelGateway
-case__1727: case__1590
-logic__9426: logic__9426
-reg__339: reg__339
-reg__372: reg__372
-logic__240: logic__240
-case__1030: case__1030
-TLInterconnectCoupler_pbus_to_fpga_uart: TLInterconnectCoupler_pbus_to_fpga_uart
-twiddle_ram: twiddle_ram
-logic__6103: logic__6103
-case__1106: case__1106
-logic__2131: logic__2131
-logic__5327: logic__5327
-reg__1013: reg__1013
-logic__1686: logic__1686
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__9: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__1476: reg__906
-AsyncValidSync: AsyncValidSync
-datapath__169: datapath__169
-reg__950: reg__950
-case__904: case__904
-logic__6823: logic__6823
-logic__5943: logic__5943
-case__565: case__565
-logic__1039: logic__1039
-logic__3565: logic__3565
-datapath__254: datapath__254
-logic__1648: logic__1648
-logic__1457: logic__1457
-logic__1240: logic__1240
-logic__427: logic__427
-datapath__719: datapath__719
-logic__3911: logic__3911
-reg__1088: reg__1088
-logic__8235: logic__8235
-datapath__195: datapath__195
-case__1015: case__1015
-case__1493: case__1493
-case__339: case__339
-logic__5876: logic__5876
-logic__5831: logic__5831
-case__804: case__804
-reg__27: reg__27
-case__480: case__480
-logic__1523: logic__1523
-logic__6781: logic__6781
-reg__1028: reg__1028
-keep__35: keep__14
-logic__2384: logic__2384
-logic__9291: logic__9291
-reg__1220: reg__1220
-reg__14: reg__14
-datapath__68: datapath__68
-logic__8619: logic__8619
-reg__374: reg__374
-logic__1666: logic__1666
-logic__4009: logic__4009
-logic__2085: logic__2085
-reg__682: reg__682
-logic__7035: logic__7035
-datapath__579: datapath__579
-case__673: case__673
-case__1173: case__1173
-logic__1797: logic__1797
-reg__371: reg__371
-case__1111: case__1111
-case__439: case__439
-case__756: case__756
-reg__713: reg__713
-logic__6071: logic__6071
-keep__18: keep__13
-datapath__541: datapath__541
-case__453: case__453
-case__1615: case__1615
-logic__724: logic__724
-logic__4692: logic__4692
-logic__3309: logic__3309
-case__161: case__161
-reg__699: reg__699
-reg__207: reg__207
-logic__876: logic__876
-case__1475: case__1475
-reg__1070: reg__1070
-logic__6903: logic__6903
-muxpart__171: muxpart__171
-datapath__265: datapath__265
-case__394: case__394
-logic__1951: logic__1951
-logic__5830: logic__5830
-case__275: case__275
-reg__1282: reg__1282
-logic__3082: logic__3082
-case__1682: case__1682
-reg__44: reg__44
-reg__294: reg__294
-logic__7037: logic__7037
-logic__6684: logic__6684
-logic__786: logic__786
-logic__4831: logic__4831
-logic__8991: logic__8991
-logic__2375: logic__2375
-logic__3033: logic__3033
-case__613: case__613
-case__1201: case__1201
-reg__809: reg__809
-IntSyncSyncCrossingSink_n1x2: IntSyncSyncCrossingSink_n1x2
-datapath__177: datapath__177
-reg__1446: reg__1068
-case__139: case__139
-case__234: case__234
-case__1260: case__1260
-logic__2769: logic__2769
-case__56: case__56
-logic__6037: logic__6037
-logic__5597: logic__5597
-case__417: case__417
-logic__907: logic__907
-datapath__331: datapath__331
-logic__6571: logic__6571
-logic__1086: logic__1086
-logic__3610: logic__3610
-logic__5027: logic__5027
-logic__3327: logic__3327
-reg__1526: reg__907
-reg__1369: reg__1369
-case__1097: case__1097
-PeripheryBus_cbus: PeripheryBus_cbus
-logic__8177: logic__8177
-datapath__227: datapath__227
-logic__3032: logic__3032
-logic__8988: logic__8988
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__3: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__1089: logic__1089
-reg__557: reg__557
-logic__4173: logic__4173
-logic__8924: logic__8924
-reg__760: reg__760
-logic__9178: logic__9178
-logic__3426: logic__3426
-case__847: case__847
-logic__1531: logic__1531
-datapath__775: datapath__41
-case__1011: case__1011
-logic__8294: logic__8294
-case__423: case__423
-case__636: case__636
-case__755: case__755
-case__496: case__496
-case__328: case__328
-logic__5420: logic__5420
-reg__1275: reg__1275
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__16: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-ram__3: ram__3
-muxpart__179: muxpart__179
-datapath__348: datapath__348
-reg__34: reg__34
-logic__8869: logic__8869
-TLDebugModuleInner: TLDebugModuleInner
-rom__1: rom__1
-case__53: case__53
-logic__4029: logic__4029
-logic__3000: logic__3000
-logic__480: logic__480
-reg__577: reg__577
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__14: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-FixedClockBroadcast_1: FixedClockBroadcast_1
-logic__238: logic__238
-TLDebugModuleOuter: TLDebugModuleOuter
-logic__3311: logic__3311
-logic__5141: logic__5141
-reg__985: reg__985
-datapath__159: datapath__159
-logic__4687: logic__4687
-logic__4849: logic__4849
-logic__115: logic__115
-datapath__488: datapath__488
-logic__3204: logic__3204
-logic__5244: logic__5244
-logic__8798: logic__8798
-datapath__5: datapath__5
-logic__7400: logic__7400
-case__1478: case__1478
-logic__4416: logic__4416
-reg__875: reg__875
-case__1083: case__1083
-logic__6156: logic__6156
-datapath__697: datapath__697
-reg__1505: reg__907
-reg__479: reg__479
-logic__3106: logic__3106
-gray_to_binary__3: gray_to_binary
-case__850: case__850
-case__546: case__546
-reg__1210: reg__1210
-datapath__389: datapath__389
-logic__7372: logic__7372
-logic__961: logic__961
-logic__2477: logic__2477
-case__542: case__542
-logic__9561: logic__2494
-muxpart__18: muxpart__18
-logic__808: logic__808
-logic__2096: logic__2096
-case__1092: case__1092
-reg__834: reg__834
-case__1150: case__1150
-logic__1836: logic__1836
-logic__8183: logic__8183
-case__1171: case__1171
-case__1077: case__1077
-logic__3323: logic__3323
-logic__8599: logic__8599
-case__210: case__210
-logic__7512: logic__7512
-datapath__212: datapath__212
-logic__7948: logic__7948
-logic__6945: logic__6945
-case__44: case__44
-logic__5986: logic__5986
-logic__5484: logic__5484
-case__1524: case__1524
-logic__4315: logic__4315
-logic__121: logic__121
-reg__1378: reg__1378
-case__206: case__206
-logic__8725: logic__8725
-acq_ca_gen: acq_ca_gen
-logic__5565: logic__5565
-logic__1584: logic__1584
-logic__3544: logic__3544
-logic__2165: logic__2165
-logic__2356: logic__2356
-case__1358: case__1358
-case__1123: case__1123
-logic__2847: logic__2847
-logic__7668: logic__7668
-logic__6748: logic__6748
-case__900: case__900
-logic__1687: logic__1687
-reg__885: reg__885
-reg__857: reg__857
-logic__5702: logic__5702
-case__977: case__977
-logic__3302: logic__3302
-keep__23: keep__14
-reg__1572: reg__121
-logic__7438: logic__7438
-logic__1662: logic__1662
-logic__6064: logic__6064
-logic__2296: logic__2296
-logic__5698: logic__5698
-datapath__258: datapath__258
-reg__562: reg__562
-logic__5435: logic__5435
-datapath__686: datapath__686
-logic__2722: logic__2722
-dsp48e2__13: dsp48e2__13
-logic__823: logic__823
-datapath__272: datapath__272
-fft_radix_2: fft_radix_2
-reg__10: reg__10
-logic__7667: logic__7667
-logic__9649: logic__1135
-logic__4656: logic__4656
-logic__7141: logic__7141
-case__1603: case__1603
-reg__815: reg__815
-case__1204: case__1204
-logic__7990: logic__7990
-logic__974: logic__974
-datapath__204: datapath__204
-datapath__622: datapath__622
-reg__1506: reg__906
-logic__1591: logic__1591
-reg__47: reg__47
-logic__6094: logic__6094
-logic__5619: logic__5619
-logic__8841: logic__8841
-case__220: case__220
-case__140: case__140
-logic__6664: logic__6664
-logic__9462: logic__9462
-reg__328: reg__328
-logic__7279: logic__7279
-logic__7606: logic__7606
-logic__3943: logic__3943
-muxpart__76: muxpart__76
-case__1617: case__1617
-logic__7350: logic__7350
-logic__6065: logic__6065
-logic__8851: logic__8851
-logic__2234: logic__2234
-logic__4417: logic__4417
-logic__1694: logic__1694
-datapath__96: datapath__96
-logic__9550: logic__2521
-datapath__483: datapath__483
-logic__6898: logic__6898
-logic__4956: logic__4956
-datapath__116: datapath__116
-reg__1532: reg__907
-logic__2364: logic__2364
-logic__4793: logic__4793
-datapath__444: datapath__444
-logic__6832: logic__6832
-muxpart__261: muxpart__261
-logic__3147: logic__3147
-logic__7120: logic__7120
-keep__26: keep__14
-reg__174: reg__174
-logic__9489: logic__3611
-logic__6612: logic__6612
-extladd__1: extladd__1
-logic__6306: logic__6306
-case__324: case__324
-logic__1618: logic__1618
-reg__472: reg__472
-logic__9546: logic__2532
-logic__8550: logic__8550
-datapath__470: datapath__470
-keep__8: keep__8
-logic__5714: logic__5714
-case__976: case__976
-logic__9505: logic__3562
-reg__103: reg__103
-logic__3083: logic__3083
-logic__3540: logic__3540
-case__1654: case__1654
-datapath__743: datapath__143
-logic__6875: logic__6875
-reg__115: reg__115
-Repeater_TLBundleA_a12d64s2k1z3u: Repeater_TLBundleA_a12d64s2k1z3u
-case__982: case__982
-logic__96: logic__96
-datapath__63: datapath__63
-reg__1554: reg__856
-SynchronizerShiftReg_w1_d3: SynchronizerShiftReg_w1_d3
-datapath__514: datapath__514
-logic__4382: logic__4382
-case__1061: case__1061
-reg__256: reg__256
-datapath__162: datapath__162
-logic__2372: logic__2372
-muxpart__260: muxpart__260
-logic__2105: logic__2105
-logic__1061: logic__1061
-datapath__648: datapath__648
-logic__2164: logic__2164
-logic__4260: logic__4260
-logic__8814: logic__8814
-logic__518: logic__518
-case__1430: case__1430
-logic__7479: logic__7479
-reg__1289: reg__1289
-logic__2475: logic__2475
-reg__1320: reg__1320
-logic__2154: logic__2154
-case__600: case__600
-datapath__342: datapath__342
-logic__9468: logic__9468
-case__747: case__747
-logic__1201: logic__1201
-logic__1124: logic__1124
-logic__7876: logic__7876
-logic__9541: logic__4537
-logic__5371: logic__5371
-reg__98: reg__98
-logic__5163: logic__5163
-logic__3101: logic__3101
-logic__1587: logic__1587
-logic__5667: logic__5667
-reg__23: reg__23
-reg__855: reg__855
-logic__7899: logic__7899
-logic__4126: logic__4126
-datapath__198: datapath__198
-muxpart__77: muxpart__77
-logic__9352: logic__9352
-case__715: case__715
-logic__4074: logic__4074
-logic__1690: logic__1690
-logic__9592: logic__8987
-logic__2074: logic__2074
-logic__5620: logic__5620
-case__1377: case__1377
-logic__9481: logic__3629
-datapath__508: datapath__508
-case__1699: case__656
-rom__3: rom__3
-case__583: case__583
-logic__5419: logic__5419
-AsyncResetSynchronizerShiftReg_w1_d3_i0__4: AsyncResetSynchronizerShiftReg_w1_d3_i0
-case__1191: case__1191
-datapath__362: datapath__362
-logic__1092: logic__1092
-case__1555: case__1555
-reg__1391: reg__1391
-TLBuffer_a32d64s2k1z3u_1: TLBuffer_a32d64s2k1z3u_1
-logic__8883: logic__8883
-logic__3995: logic__3995
-datapath__570: datapath__570
-logic__9343: logic__9343
-RoundAnyRawFNToRecFN_4: RoundAnyRawFNToRecFN_4
-logic__6718: logic__6718
-logic__7967: logic__7967
-logic__5952: logic__5952
-case__1704: case__733
-logic__109: logic__109
-logic__6956: logic__6956
-dsp48e2__18: dsp48e2__18
-logic__291: logic__291
-DivSqrtRecFNToRaw_small: DivSqrtRecFNToRaw_small
-logic__6649: logic__6649
-logic__3319: logic__3319
-logic__7044: logic__7044
-reg__1036: reg__1036
-datapath__175: datapath__175
-reg__362: reg__362
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__5: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__386: case__386
-dsp48e2__11: dsp48e2__11
-reg__336: reg__336
-case__916: case__916
-logic__3481: logic__3481
-reg__1530: reg__906
-logic__7303: logic__7303
-logic__1095: logic__1095
-logic__8279: logic__8279
-logic__7234: logic__7234
-logic__1354: logic__1354
-logic__3818: logic__3818
-logic__1341: logic__1341
-reg__388: reg__388
-logic__3153: logic__3153
-case__61: case__61
-datapath__402: datapath__402
-logic__5206: logic__5206
-logic__1653: logic__1653
-reg__386: reg__386
-logic__3183: logic__3183
-logic__2349: logic__2349
-logic__3918: logic__3918
-datapath__120: datapath__120
-logic__911: logic__911
-logic__8105: logic__8105
-logic__3198: logic__3198
-logic__2735: logic__2735
-logic__7827: logic__7827
-logic__1491: logic__1491
-reg__1203: reg__1203
-reg__1543: reg__908
-case__1091: case__1091
-logic__1812: logic__1812
-logic__2229: logic__2229
-logic__71: logic__71
-logic__6815: logic__6815
-reg__313: reg__313
-logic__9557: logic__2506
-logic__5954: logic__5954
-case__1047: case__1047
-datapath__634: datapath__634
-logic__8085: logic__8085
-datapath__764: datapath__164
-logic__9247: logic__9247
-reg__937: reg__937
-logic__870: logic__870
-case__1521: case__1521
-keep__9: keep__9
-reg__1410: reg__120
-reg__22: reg__22
-case__702: case__702
-logic__3572: logic__3572
-logic__2927: logic__2927
-case__430: case__430
-reg__1450: reg__1067
-logic__5915: logic__5915
-case__1167: case__1167
-logic__7723: logic__7723
-logic__5970: logic__5970
-logic__7711: logic__7711
-logic__1478: logic__1478
-logic__6048: logic__6048
-logic__8835: logic__8835
-logic__5186: logic__5186
-Queue1_RegMapperInput_i23_m8: Queue1_RegMapperInput_i23_m8
-logic__7642: logic__7642
-logic__4848: logic__4848
-logic__6070: logic__6070
-case__1722: case__1595
-reg__394: reg__394
-datapath__165: datapath__165
-case__836: case__836
-case__277: case__277
-logic__273: logic__273
-logic__120: logic__120
-logic__7115: logic__7115
-NCO_code: NCO_code
-logic__3467: logic__3467
-TLDebugModuleOuterAsync: TLDebugModuleOuterAsync
-logic__4762: logic__4762
-case__625: case__625
-logic__6777: logic__6777
-logic__4595: logic__4595
-logic__2273: logic__2273
-case__305: case__305
-logic__9554: logic__2517
-reg__606: reg__606
-reg__1044: reg__1044
-logic__3322: logic__3322
-case__751: case__751
-logic__9571: logic__935
-muxpart__181: muxpart__181
-cordic_atan_basic: cordic_atan_basic
-logic__376: logic__376
-reg__437: reg__437
-logic__4449: logic__4449
-logic__1680: logic__1680
-logic__1505: logic__1505
-reg__552: reg__552
-datapath__41: datapath__41
-spill_register: spill_register
-logic__720: logic__720
-case__508: case__508
-logic__7858: logic__7858
-case__638: case__638
-logic__3333: logic__3333
-reg__1494: reg__906
-logic__3598: logic__3598
-logic__244: logic__244
-logic__7404: logic__7404
-logic__3306: logic__3306
-reg__1162: reg__1162
-case__644: case__644
-case__1557: case__1557
-logic__1959: logic__1959
-logic__2416: logic__2416
-logic__2432: logic__2432
-datapath__368: datapath__368
-datapath__330: datapath__330
-logic__9564: logic__2485
-logic__5733: logic__5733
-Arbiter3_LLWB: Arbiter3_LLWB
-case__1082: case__1082
-logic__8688: logic__8688
-case__311: case__311
-datapath__103: datapath__103
-logic__7662: logic__7662
-logic__1960: logic__1960
-case__1576: case__1576
-case__1016: case__1016
-reg__870: reg__870
-reg__131: reg__131
-logic__9039: logic__9039
-logic__7248: logic__7248
-logic__7192: logic__7192
-logic__8268: logic__8268
-reg__1314: reg__1314
-logic__2156: logic__2156
-AsyncValidSync__13: AsyncValidSync
-reg__1322: reg__1322
-datapath__329: datapath__329
-logic__4178: logic__4178
-reg__90: reg__90
-logic__7660: logic__7660
-datapath__432: datapath__432
-logic__7172: logic__7172
-ram__5: ram__5
-logic__8278: logic__8278
-reg__281: reg__281
-Repeater_TLBundleA_a29d64s2k1z3u_2: Repeater_TLBundleA_a29d64s2k1z3u_2
-logic__5510: logic__5510
-logic__1586: logic__1586
-logic__3219: logic__3219
-case__1263: case__1263
-datapath__635: datapath__635
-reg__874: reg__874
-datapath__255: datapath__255
-logic__8120: logic__8120
-datapath__418: datapath__418
-case__58: case__58
-reg__1479: reg__906
-reg__181: reg__181
-logic__726: logic__726
-case__1018: case__1018
-logic__254: logic__254
-logic__6318: logic__6318
-logic__5580: logic__5580
-case__125: case__125
-case__1161: case__1161
-logic__2951: logic__2951
-mult_46_15_61: mult_46_15_61
-logic__7153: logic__7153
-reg__691: reg__691
-logic__2736: logic__2736
-logic__7826: logic__7826
-datapath__773: datapath__43
-logic__9558: logic__2503
-case__912: case__912
-reg__350: reg__350
-logic__5527: logic__5527
-case__1179: case__1179
-logic__1604: logic__1604
-logic__7796: logic__7796
-case__637: case__637
-case__806: case__806
-logic__1661: logic__1661
-keep__17: keep__14
-case__1328: case__1328
-case__1439: case__1439
-muxpart__211: muxpart__211
-logic__3305: logic__3305
-reg__958: reg__958
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__10: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__8410: logic__8410
-reg__431: reg__431
-logic__8337: logic__8337
-datapath__287: datapath__287
-logic__1516: logic__1516
-cordic_angle_lut__parameterized0: cordic_angle_lut__parameterized0
-datapath__560: datapath__560
-logic__8113: logic__8113
-reg__434: reg__434
-dsp48e2__40: dsp48e2__40
-case__1287: case__1287
-reg__740: reg__740
-case__577: case__577
-logic__439: logic__439
-reg__619: reg__619
-reg__1097: reg__1097
-case__994: case__994
-logic__3483: logic__3483
-logic__6810: logic__6810
-PMPChecker_s3: PMPChecker_s3
-logic__3314: logic__3314
-logic__9222: logic__9222
-logic__3029: logic__3029
-logic__5255: logic__5255
-datapath__580: datapath__580
-datapath__777: datapath__39
-logic__1508: logic__1508
-reg__705: reg__705
-logic__4781: logic__4781
-logic__4870: logic__4870
-case__720: case__720
-reg__565: reg__565
-logic__5938: logic__5938
-logic__4877: logic__4877
-datapath__313: datapath__313
-logic__5379: logic__5379
-case__412: case__412
-logic__3847: logic__3847
-reg__1240: reg__1240
-reg__275: reg__275
-logic__3659: logic__3659
-datapath__38: datapath__38
-reg__1440: reg__1068
-logic__9309: logic__9309
-datapath__87: datapath__87
-datapath__35: datapath__35
-datapath__333: datapath__333
-muxpart__150: muxpart__150
-logic__7016: logic__7016
-reg__236: reg__236
-logic__2666: logic__2666
-reg__959: reg__959
-case__1159: case__1159
-datapath__422: datapath__422
-logic__7778: logic__7778
-logic__6639: logic__6639
-case__205: case__205
-logic__6929: logic__6929
-logic__2287: logic__2287
-reg__1049: reg__1049
-case__204: case__204
-logic__1917: logic__1917
-logic__1098: logic__1098
-reg__92: reg__92
-case__1189: case__1189
-reg__993: reg__993
-reg__686: reg__686
-reg__24: reg__24
-reg__357: reg__357
-logic__234: logic__234
-case__342: case__342
-logic__5530: logic__5530
-case__895: case__895
-reg__1477: reg__908
-reg__1341: reg__1341
-logic__1810: logic__1810
-logic__9497: logic__3600
-reg__872: reg__872
-reg__360: reg__360
-logic__7338: logic__7338
-datapath__40: datapath__40
-logic__8175: logic__8175
-logic__7073: logic__7073
-logic__9136: logic__9136
-logic__8070: logic__8070
-case__809: case__809
-case__387: case__387
-datapath__754: datapath__690
-logic__4466: logic__4466
-logic__7082: logic__7082
-datapath__60: datapath__60
-logic__3996: logic__3996
-logic__5579: logic__5579
-reg__25: reg__25
-datapath__641: datapath__641
-logic__9432: logic__9432
-datapath__107: datapath__107
-reg__123: reg__123
-case__1685: case__1685
-logic__2928: logic__2928
-logic__4521: logic__4521
-case__731: case__731
-dsp48e2__42: dsp48e2__42
-logic__4992: logic__4992
-reg__861: reg__861
-reg__1528: reg__908
-case__1087: case__1087
-logic__1248: logic__1248
-rom__6: rom__6
-logic__5055: logic__5055
-NCO_carr: NCO_carr
-muxpart__275: muxpart__275
-reg__157: reg__157
-logic__2726: logic__2726
-logic__4490: logic__4490
-reg__510: reg__510
-case: case
-TLBuffer_a32d64s2k1z4u_1: TLBuffer_a32d64s2k1z4u_1
-logic__3794: logic__3794
-case__1368: case__1368
-reg__1347: reg__1347
-reg__216: reg__216
-logic__2263: logic__2263
-case__1227: case__1227
-logic__7039: logic__7039
-case__289: case__289
-reg__902: reg__902
-case__141: case__141
-ram__10: ram__1
-reg__1295: reg__1295
-reg__1153: reg__1153
-datapath__388: datapath__388
-case__1126: case__1126
-IntToFP: IntToFP
-AsyncQueueSink_DebugInternalBundle: AsyncQueueSink_DebugInternalBundle
-reg__718: reg__718
-datapath__158: datapath__158
-logic__6899: logic__6899
-logic__2989: logic__2989
-reg__1059: reg__1059
-muxpart__174: muxpart__174
-logic__6129: logic__6129
-reg__904: reg__904
-logic__6362: logic__6362
-case__5: case__5
-logic__857: logic__857
-reg__74: reg__74
-datapath__445: datapath__445
-TLError: TLError
-reg__756: reg__756
-reg__625: reg__625
-reg__1399: reg__1399
-logic__7980: logic__7980
-logic__7423: logic__7423
-case__845: case__845
-reg__652: reg__652
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__1: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__7673: logic__7673
-logic__9585: logic__9000
-logic__6924: logic__6924
-datapath__607: datapath__607
-logic__5670: logic__5670
-counter__9: counter__9
-logic__6728: logic__6728
-case__1649: case__1649
-reg__1523: reg__907
-datapath__119: datapath__119
-reg__13: reg__13
-case__1378: case__1378
-reg__171: reg__171
-logic__9630: logic__1599
-reg__623: reg__623
-reg__977: reg__977
-case__443: case__443
-DTLB: DTLB
-logic__4318: logic__4318
-reg__283: reg__283
-logic__2678: logic__2678
-muxpart__271: muxpart__271
-logic__5436: logic__5436
-logic__7259: logic__7259
-logic__8953: logic__8953
-logic__5598: logic__5598
-logic__5314: logic__5314
-logic__5306: logic__5306
-logic__1497: logic__1497
-logic__7619: logic__7619
-logic__7252: logic__7252
-reg__1398: reg__1398
-logic__6523: logic__6523
-case__487: case__487
-reg__495: reg__495
-datapath__490: datapath__490
-reg__1095: reg__1095
-reg__365: reg__365
-case__1732: case__306
-logic__9593: logic__8795
-case__732: case__732
-reg__1324: reg__1324
-logic__2898: logic__2898
-logic__7993: logic__7993
-reg__508: reg__508
-logic__7981: logic__7981
-logic__7245: logic__7245
-logic__4351: logic__4351
-reg__580: reg__580
-reg__930: reg__930
-reg__312: reg__312
-reg__382: reg__382
-muxpart__247: muxpart__247
-reg__1075: reg__1075
-reg__1074: reg__1074
-reg__1288: reg__1288
-muxpart__352: muxpart__352
-case__728: case__728
-case__837: case__837
-case__1155: case__1155
-case__332: case__332
-reg__1060: reg__1060
-logic__7532: logic__7532
-datapath__745: datapath__141
-reg__653: reg__653
-datapath__573: datapath__573
-logic__9663: logic__920
-muxpart__262: muxpart__262
-datapath__294: datapath__294
-Repeater_TLBundleA_a29d32s2k1z3u: Repeater_TLBundleA_a29d32s2k1z3u
-logic__6560: logic__6560
-reg__82: reg__82
-logic__7845: logic__7845
-logic__2357: logic__2357
-logic__7096: logic__7096
-logic__8272: logic__8272
-datapath__693: datapath__693
-logic__6652: logic__6652
-reg__1485: reg__906
-logic__2704: logic__2704
-reg__782: reg__782
-reg__649: reg__649
-reg__32: reg__32
-datapath__190: datapath__190
-datapath__494: datapath__494
-muxpart__65: muxpart__65
-datapath__4: datapath__4
-logic__7703: logic__7703
-case__1686: case__1686
-logic__5498: logic__5498
-reg__1243: reg__1243
-logic__4963: logic__4963
-reg__742: reg__742
-logic__4785: logic__4785
-keep__24: keep__13
-datapath__706: datapath__706
-logic__102: logic__102
-logic__3107: logic__3107
-logic__6609: logic__6609
-logic__4702: logic__4702
-logic__7613: logic__7613
-logic__1888: logic__1888
-logic__6173: logic__6173
-logic__3324: logic__3324
-case__1676: case__1676
-logic__6038: logic__6038
-reg__177: reg__177
-reg__1400: reg__1400
-reg__1147: reg__1147
-muxpart__189: muxpart__189
-reg__247: reg__247
-TLFragmenter_FPGAGPS: TLFragmenter_FPGAGPS
-case__1338: case__1338
-logic__2054: logic__2054
-logic__4947: logic__4947
-datapath__625: datapath__625
-logic__1571: logic__1571
-logic__4706: logic__4706
-logic__6778: logic__6778
-case__447: case__447
-logic__6001: logic__6001
-reg__466: reg__466
-case__1154: case__1154
-logic__7134: logic__7134
-logic__6650: logic__6650
-reg__654: reg__654
-logic__2822: logic__2822
-case__513: case__513
-reg__81: reg__81
-reg__916: reg__916
-case__1598: case__1598
-reg__208: reg__208
-case__933: case__933
-muxpart__243: muxpart__243
-reg__917: reg__917
-case__391: case__391
-logic__3798: logic__3798
-logic__2123: logic__2123
-case__422: case__422
-case__877: case__877
-logic__332: logic__332
-datapath__539: datapath__539
-reg__1195: reg__1195
-logic__6524: logic__6524
-logic__5511: logic__5511
-case__1117: case__1117
-logic__1945: logic__1945
-reg__1016: reg__1016
-reg__1219: reg__1219
-logic__2103: logic__2103
-datapath__730: datapath__330
-reg__1054: reg__1054
-logic__1589: logic__1589
-reg__1050: reg__1050
-logic__9626: logic__6769
-logic__912: logic__912
-reg__1131: reg__1131
-datapath__478: datapath__478
-logic__4803: logic__4803
-logic__5595: logic__5595
-datapath__350: datapath__350
-reg__1296: reg__1296
-logic__7395: logic__7395
-ram_2x77__1: ram_2x77
-logic__843: logic__843
-reg__465: reg__465
-logic__230: logic__230
-reg__1521: reg__906
-logic__4719: logic__4719
-logic__4545: logic__4545
-muxpart__60: muxpart__60
-reg__1453: reg__908
-logic__1910: logic__1910
-case__770: case__770
-case__1031: case__1031
-logic__5496: logic__5496
-case__493: case__493
-logic__5270: logic__5270
-logic__6769: logic__6769
-case__433: case__433
-logic__1392: logic__1392
-logic__2060: logic__2060
-extram__9: extram__9
-reg__143: reg__143
-logic__8164: logic__8164
-case__1376: case__1376
-logic__5461: logic__5461
-logic__4255: logic__4255
-datapath__682: datapath__682
-case__723: case__723
-logic__7296: logic__7296
-case__547: case__547
-reg__813: reg__813
-case__1293: case__1293
-logic__5762: logic__5762
-case__1538: case__1538
-logic__5997: logic__5997
-logic__5977: logic__5977
-logic__4894: logic__4894
-reg__1018: reg__1018
-logic__1007: logic__1007
-logic__5523: logic__5523
-logic__1222: logic__1222
-logic__9331: logic__9331
-logic__4247: logic__4247
-logic__7832: logic__7832
-TLXbar_dmixbar_i1_o2_a9d32s1k1z2u: TLXbar_dmixbar_i1_o2_a9d32s1k1z2u
-logic__6744: logic__6744
-reg__830: reg__830
-reg__667: reg__667
-cordic_atan_basic__parameterized0__1: cordic_atan_basic__parameterized0
-reg__1417: reg__199
-datapath__426: datapath__426
-datapath__584: datapath__584
-rockettile_icache_data_arrays_512x32: rockettile_icache_data_arrays_512x32
-case__1648: case__1648
-case__1553: case__1553
-logic__5302: logic__5302
-logic__2084: logic__2084
-reg__602: reg__602
-reg__214: reg__214
-logic__5706: logic__5706
-logic__7894: logic__7894
-logic__6827: logic__6827
-datapath__51: datapath__51
-reg__422: reg__422
-reg__512: reg__512
-logic__4778: logic__4778
-logic__1258: logic__1258
-logic__5267: logic__5267
-reg__784: reg__784
-PMPChecker_s2: PMPChecker_s2
-logic__9612: logic__6769
-datapath__274: datapath__274
-case__594: case__594
-logic__7777: logic__7777
-logic__8275: logic__8275
-reg__770: reg__770
-case__130: case__130
-logic__5877: logic__5877
-case__1200: case__1200
-case__1095: case__1095
-logic__4398: logic__4398
-logic__4480: logic__4480
-logic__4614: logic__4614
-DCacheDataArray: DCacheDataArray
-logic__5283: logic__5283
-logic__1115: logic__1115
-case__1503: case__1503
-reg__354: reg__354
-muxpart__63: muxpart__63
-logic__183: logic__183
-logic__8127: logic__8127
-datapath__36: datapath__36
-reg__918: reg__918
-logic__835: logic__835
-case__1037: case__1037
-logic__6604: logic__6604
-reg__488: reg__488
-case__1255: case__1255
-reg__1456: reg__908
-reg__1501: reg__908
-reg__458: reg__458
-reg__1263: reg__1263
-case__1207: case__1207
-logic__2721: logic__2721
-TLFpgaSPI: TLFpgaSPI
-case__991: case__991
-datapath__289: datapath__289
-counter__13: counter__13
-case__906: case__906
-logic__6740: logic__6740
-reg__772: reg__772
-logic__7556: logic__7556
-logic__3205: logic__3205
-reg__1278: reg__1278
-reg__1355: reg__1355
-reg__1184: reg__1184
-logic__1668: logic__1668
-LF_carr: LF_carr
-logic__8198: logic__8198
-reg__1460: reg__907
-reg__301: reg__301
-reg__460: reg__460
-logic__6476: logic__6476
-reg__611: reg__611
-logic__5446: logic__5446
-logic__2817: logic__2817
-logic__2190: logic__2190
-logic__2000: logic__2000
-logic__6623: logic__6623
-logic__3318: logic__3318
-logic__7030: logic__7030
-datapath__280: datapath__280
-logic__6050: logic__6050
-case__1007: case__1007
-case__1185: case__1185
-logic__6725: logic__6725
-logic__8972: logic__8972
-muxpart__67: muxpart__67
-case__1149: case__1149
-datapath__99: datapath__99
-logic__186: logic__186
-logic__8368: logic__8368
-logic__6703: logic__6703
-logic__6557: logic__6557
-logic__4766: logic__4766
-logic__3597: logic__3597
-logic__3840: logic__3840
-logic__2237: logic__2237
-datapath__554: datapath__554
-reg__1259: reg__1259
-logic__4755: logic__4755
-logic__8742: logic__8742
-case__795: case__795
-reg__37: reg__37
-logic__5342: logic__5342
-logic__4826: logic__4826
-RoundAnyRawFNToRecFN__1: RoundAnyRawFNToRecFN
-logic__9421: logic__9421
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__7: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__7367: logic__7367
-logic__5660: logic__5660
-logic__5468: logic__5468
-logic__8954: logic__8954
-case__211: case__211
-logic__3243: logic__3243
-logic__3500: logic__3500
-logic__4409: logic__4409
-logic__1522: logic__1522
-logic__3695: logic__3695
-reg__1002: reg__1002
-datapath__163: datapath__163
-reg__63: reg__63
-reg__319: reg__319
-datapath__568: datapath__568
-reg__773: reg__773
-logic__767: logic__767
-case__1032: case__1032
-logic__7105: logic__7105
-logic__7023: logic__7023
-reg__1411: reg__119
-reg__678: reg__678
-logic__5533: logic__5533
-muxpart__251: muxpart__251
-case__1700: case__655
-logic__6054: logic__6054
-logic__3797: logic__3797
-logic__3820: logic__3820
-muxpart__23: muxpart__23
-Queue2_TLBundleD_a29d64s2k1z3u__2: Queue2_TLBundleD_a29d64s2k1z3u
-datapath__649: datapath__649
-datapath__178: datapath__178
-case__517: case__517
-case__175: case__175
-logic__7942: logic__7942
-case__1027: case__1027
-TLInterconnectCoupler_sbus_from_bus_named_fbus: TLInterconnectCoupler_sbus_from_bus_named_fbus
-logic__9236: logic__9236
-Repeater_TLBundleA_a26d64s2k1z3u: Repeater_TLBundleA_a26d64s2k1z3u
-datapath__79: datapath__79
-reg__1342: reg__1342
-reg__1408: reg__1408
-logic__3602: logic__3602
-logic__9385: logic__9385
-cacode_gen_trck: cacode_gen_trck
-reg__359: reg__359
-logic__6603: logic__6603
-reg__1077: reg__1077
-logic__941: logic__941
-PeripheryBus_pbus: PeripheryBus_pbus
-logic__8987: logic__8987
-logic__123: logic__123
-logic__7106: logic__7106
-datapath__772: datapath__44
-case__1579: case__1579
-reg__1475: reg__907
-logic__721: logic__721
-case__1073: case__1073
-datapath__675: datapath__675
-case__347: case__347
-case__550: case__550
-reg__537: reg__537
-logic__2544: logic__2544
-logic__2079: logic__2079
-case__1610: case__1610
-muxpart__186: muxpart__186
-sync__5: sync
-logic__768: logic__768
-datapath__39: datapath__39
-logic__9495: logic__3602
-TLWidthWidget8_1__1: TLWidthWidget8_1
-reg__856: reg__856
-logic__8823: logic__8823
-logic__2651: logic__2651
-muxpart__241: muxpart__241
-FPGASPIClockSinkDomain: FPGASPIClockSinkDomain
-reg__1052: reg__1052
-reg__228: reg__228
-logic__1538: logic__1538
-datapath__652: datapath__652
-logic__4231: logic__4231
-logic__4037: logic__4037
-case__1339: case__1339
-logic__8505: logic__8505
-logic__6552: logic__6552
-logic__5416: logic__5416
-case__159: case__159
-case__3: case__3
-logic__1330: logic__1330
-logic__6605: logic__6605
-logic__3034: logic__3034
-TLBusBypass: TLBusBypass
-logic__1941: logic__1941
-datapath__710: datapath__710
-logic__925: logic__925
-logic__5151: logic__5151
-case__1197: case__1197
-logic__7424: logic__7424
-logic__1477: logic__1477
-case__871: case__871
-case__946: case__946
-reg__323: reg__323
-muxpart__26: muxpart__26
-reg__800: reg__800
-reg__586: reg__586
-reg__1321: reg__1321
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__6: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6754: logic__6754
-case__1725: case__1592
-logic__437: logic__437
-reg__887: reg__887
-logic__2758: logic__2758
-case__1020: case__1020
-LevelGateway__1: LevelGateway
-logic__1596: logic__1596
-case__485: case__485
-CompareRecFN: CompareRecFN
-logic__666: logic__666
-logic__1577: logic__1577
-datapath__385: datapath__385
-datapath__725: datapath__725
-reg__293: reg__293
-case__280: case__280
-logic__5004: logic__5004
-logic__405: logic__405
-reg__764: reg__764
-logic__1777: logic__1777
-logic__1403: logic__1403
-RoundAnyRawFNToRecFN_4__1: RoundAnyRawFNToRecFN_4
-muxpart__187: muxpart__187
-logic__6865: logic__6865
-logic__4401: logic__4401
-logic__5332: logic__5332
-logic__5826: logic__5826
-logic__2145: logic__2145
-reg__59: reg__59
-logic__4024: logic__4024
-muxpart__52: muxpart__52
-logic__1827: logic__1827
-reg__1148: reg__1148
-RoundRawFNToRecFN__1: RoundRawFNToRecFN
-reg__1397: reg__1397
-logic__8055: logic__8055
-reg__164: reg__164
-logic__5623: logic__5623
-case__1736: case__302
-TLFragmenter_PLIC: TLFragmenter_PLIC
-reg__679: reg__679
-logic__5521: logic__5521
-logic__4850: logic__4850
-logic__6998: logic__6998
-reg__1019: reg__1019
-case__752: case__752
-reg__1167: reg__1167
-logic__4686: logic__4686
-logic__2605: logic__2605
-logic__5014: logic__5014
-logic__3501: logic__3501
-logic__2851: logic__2851
-case__1238: case__1238
-logic__7789: logic__7789
-logic__8326: logic__8326
-logic__3958: logic__3958
-reg__1080: reg__1080
-reg__1557: reg__856
-accum_dump: accum_dump
-reg__1394: reg__1394
-logic__869: logic__869
-case__1563: case__1563
-datapath__630: datapath__630
-muxpart__240: muxpart__240
-logic__4141: logic__4141
-reg__992: reg__992
-datapath__614: datapath__614
-logic__5925: logic__5925
-case__634: case__634
-logic__3146: logic__3146
-logic__5234: logic__5234
-reg__676: reg__676
-case__1211: case__1211
-datapath__306: datapath__306
-case__1613: case__1613
-logic__712: logic__712
-logic__8162: logic__8162
-datapath__583: datapath__583
-case__585: case__585
-logic__1281: logic__1281
-logic__7747: logic__7747
-logic__1311: logic__1311
-reg__515: reg__515
-datapath__553: datapath__553
-muxpart__91: muxpart__91
-keep__6: keep__6
-logic__4393: logic__4393
-TLAtomicAutomata_cbus: TLAtomicAutomata_cbus
-counter__6: counter__6
-case__1025: case__1025
-logic__9336: logic__9336
-reg__335: reg__335
-case__1510: case__1510
-reg__991: reg__991
-logic__4827: logic__4827
-case__1071: case__1071
-reg__684: reg__684
-logic__8959: logic__8959
-case__1418: case__1418
-datapath__638: datapath__638
-case__597: case__597
-case__297: case__297
-case__1729: case__1588
-reg__498: reg__498
-logic__5606: logic__5606
-logic__9622: logic__6769
-logic__807: logic__807
-logic__2698: logic__2698
-reg__737: reg__737
-logic__6588: logic__6588
-logic__1503: logic__1503
-reg__657: reg__657
-reg__750: reg__750
-logic__6164: logic__6164
-logic__7433: logic__7433
-logic__1243: logic__1243
-case__1731: case__1586
-reg__1512: reg__906
-logic__4818: logic__4818
-reg__915: reg__915
-logic__6984: logic__6984
-case__1101: case__1101
-reg__1245: reg__1245
-case__396: case__396
-logic__4467: logic__4467
-datapath__643: datapath__643
-reg__1540: reg__908
-case__647: case__647
-case__990: case__990
-logic__9128: logic__9128
-muxpart__378: muxpart__378
-logic__9618: logic__6769
-reg__326: reg__326
-keep__46: keep__9
-logic__4162: logic__4162
-logic__3455: logic__3455
-muxpart__78: muxpart__78
-logic__7209: logic__7209
-reg__351: reg__351
-reg__805: reg__805
-case__1299: case__1299
-reg__1562: reg__155
-case__222: case__222
-logic__7057: logic__7057
-case__446: case__446
-TLInterconnectCoupler_sbus_from_rockettile: TLInterconnectCoupler_sbus_from_rockettile
-logic__2807: logic__2807
-logic__7258: logic__7258
-logic__7625: logic__7625
-reg__600: reg__600
-datapath__689: datapath__689
-case__935: case__935
-datapath__736: datapath__388
-logic__9476: logic__3643
-logic__5219: logic__5219
-reg__1093: reg__1093
-logic__7490: logic__7490
-muxpart__225: muxpart__225
-case__1673: case__1673
-logic__2415: logic__2415
-muxpart__87: muxpart__87
-case__1005: case__1005
-logic__6615: logic__6615
-case__1237: case__1237
-logic__2488: logic__2488
-logic__3482: logic__3482
-logic__78: logic__78
-case__548: case__548
-logic__4356: logic__4356
-case__622: case__622
-logic__2532: logic__2532
-reg__292: reg__292
-logic__973: logic__973
-case__270: case__270
-keep__43: keep__12
-logic__1015: logic__1015
-fft_radix_2__parameterized0: fft_radix_2__parameterized0
-logic__2440: logic__2440
-logic__5665: logic__5665
-logic__5005: logic__5005
-reg__564: reg__564
-logic__9494: logic__3603
-case__612: case__612
-logic__6900: logic__6900
-reg__211: reg__211
-datapath__496: datapath__496
-logic__3601: logic__3601
-logic__5755: logic__5755
-datapath__152: datapath__152
-case__278: case__278
-case__833: case__833
-case__858: case__858
-case__1182: case__1182
-reg__873: reg__873
-logic__2028: logic__2028
-logic__1807: logic__1807
-logic__1500: logic__1500
-reg__1310: reg__1310
-logic__1038: logic__1038
-reg__1267: reg__1267
-datapath__248: datapath__248
-logic__6662: logic__6662
-reg__685: reg__685
-logic__3486: logic__3486
-reg__100: reg__100
-case__595: case__595
-case__323: case__323
-case__265: case__265
-datapath__328: datapath__328
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__24: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-muxpart__29: muxpart__29
-logic__9548: logic__2523
-reg__117: reg__117
-case__309: case__309
-Frontend: Frontend
-logic__7201: logic__7201
-case__356: case__356
-reg__389: reg__389
-logic__1801: logic__1801
-logic__9508: logic__4656
-case__436: case__436
-muxpart__384: muxpart__384
-case__507: case__507
-case__35: case__35
-reg__1285: reg__1285
-logic__393: logic__393
-logic__2627: logic__2627
-case__1206: case__1206
-reg__1340: reg__1340
-logic__6925: logic__6925
-datapath__587: datapath__587
-case__1108: case__1108
-logic__3510: logic__3510
-logic__7345: logic__7345
-logic__8493: logic__8493
-datapath__639: datapath__639
-case__1055: case__1055
-reg__883: reg__883
-logic__2031: logic__2031
-case__950: case__950
-logic__2092: logic__2092
-reg__1500: reg__906
-case__1506: case__1506
-case__474: case__474
-case__610: case__610
-datapath__537: datapath__537
-logic__6132: logic__6132
-logic__448: logic__448
-logic__7994: logic__7994
-logic__1867: logic__1867
-reg__242: reg__242
-logic__5271: logic__5271
-reg__895: reg__895
-datapath__460: datapath__460
-datapath__273: datapath__273
-case__325: case__325
-logic__1140: logic__1140
-reg__1262: reg__1262
-logic__2435: logic__2435
-logic__5193: logic__5193
-logic__915: logic__915
-logic__7905: logic__7905
-logic__2155: logic__2155
-datapath__430: datapath__430
-logic__4392: logic__4392
-counter__33: counter__33
-logic__3010: logic__3010
-logic__1342: logic__1342
-logic__2933: logic__2933
-logic__7339: logic__7339
-IntSyncAsyncCrossingSink_n1x1: IntSyncAsyncCrossingSink_n1x1
-logic__6335: logic__6335
-logic__2198: logic__2198
-datapath__455: datapath__455
-logic__7637: logic__7637
-reg__353: reg__353
-case__470: case__470
-case__520: case__520
-logic__2409: logic__2409
-muxpart__328: muxpart__328
-logic__7276: logic__7276
-datapath__191: datapath__191
-case__758: case__758
-logic__1894: logic__1894
-logic__1796: logic__1796
-logic__5948: logic__5948
-logic__3250: logic__3250
-logic__6995: logic__6995
-logic__7010: logic__7010
-logic__4349: logic__4349
-case__1148: case__1148
-logic__5430: logic__5430
-logic__9332: logic__9332
-case__1604: case__1604
-muxpart__188: muxpart__188
-reg__200: reg__200
-reg__1071: reg__1071
-reg__151: reg__151
-logic__7147: logic__7147
-reg__1260: reg__1260
-reg__277: reg__277
-logic__935: logic__935
-logic__5936: logic__5936
-muxpart__149: muxpart__149
-case__244: case__244
-logic__3063: logic__3063
-logic__5256: logic__5256
-OptimizationBarrier_TLBEntryData__1: OptimizationBarrier_TLBEntryData
-logic__3454: logic__3454
-logic__7405: logic__7405
-logic__2335: logic__2335
-reg__28: reg__28
-logic__8710: logic__8710
-logic__403: logic__403
-muxpart__25: muxpart__25
-logic__4935: logic__4935
-case__851: case__851
-logic__4380: logic__4380
-reg__1533: reg__906
-datapath__466: datapath__466
-reg__722: reg__722
-logic__6996: logic__6996
-datapath__164: datapath__164
-datapath__623: datapath__623
-logic__8779: logic__8779
-logic__3030: logic__3030
-logic__7881: logic__7881
-reg__952: reg__952
-reg__368: reg__368
-logic__7266: logic__7266
-logic__651: logic__651
-case__558: case__558
-case__1137: case__1137
-dsp48e2__15: dsp48e2__15
-logic__6819: logic__6819
-reg__832: reg__832
-logic__3288: logic__3288
-logic__2355: logic__2355
-case__678: case__678
-case__1223: case__1223
-reg__1008: reg__1008
-datapath__277: datapath__277
-case__150: case__150
-muxpart__40: muxpart__40
-datapath__183: datapath__183
-logic__3842: logic__3842
-reg__733: reg__733
-reg__544: reg__544
-logic__8260: logic__8260
-logic__7343: logic__7343
-logic__9538: logic__4545
-logic__8920: logic__8920
-logic__9472: logic__3666
-logic__1595: logic__1595
-datapath__123: datapath__123
-logic__8700: logic__8700
-logic__5433: logic__5433
-case__1393: case__1393
-reg__810: reg__810
-logic__1104: logic__1104
-case__1046: case__1046
-muxpart__68: muxpart__68
-logic__7293: logic__7293
-case__262: case__262
-counter__1: counter__1
-logic__4075: logic__4075
-logic__2110: logic__2110
-case__1646: case__1646
-dsp48e2__4: dsp48e2__4
-keep: keep
-case__932: case__932
-logic__1704: logic__1704
-case__1135: case__1135
-reg__1012: reg__1012
-logic__9474: logic__3660
-logic__2062: logic__2062
-logic__4899: logic__4899
-reg__570: reg__570
-case__640: case__640
-logic__7765: logic__7765
-logic__7411: logic__7411
-logic__9473: logic__3663
-case__1125: case__1125
-logic__3519: logic__3519
-reg__698: reg__698
-logic__7740: logic__7740
-logic__7527: logic__7527
-reg__1200: reg__1200
-logic__6790: logic__6790
-datapath__530: datapath__530
-logic__9529: logic__4598
-logic__443: logic__443
-logic__9511: logic__4635
-case__763: case__763
-datapath__542: datapath__542
-case__429: case__429
-reg__837: reg__837
-ram: ram
-logic__1792: logic__1792
-keep__44: keep__9
-logic__1411: logic__1411
-reg__618: reg__618
-case__248: case__248
-cordic_angle_lut: cordic_angle_lut
-logic__7506: logic__7506
-logic__1979: logic__1979
-logic__1250: logic__1250
-logic__9560: logic__2497
-logic__5851: logic__5851
-logic__4587: logic__4587
-logic__3871: logic__3871
-logic__616: logic__616
-case__1054: case__1054
-logic__3452: logic__3452
-logic__7227: logic__7227
-datapath__263: datapath__263
-logic__2997: logic__2997
-case__967: case__967
-logic__458: logic__458
-logic__1268: logic__1268
-logic__7224: logic__7224
-logic__3296: logic__3296
-logic__1101: logic__1101
-reg__852: reg__852
-reg__305: reg__305
-logic__5187: logic__5187
-datapath__532: datapath__532
-logic__7399: logic__7399
-reg__1570: reg__147
-case__1687: case__1687
-logic__9556: logic__2509
-logic__7138: logic__7138
-logic__7009: logic__7009
-logic__6366: logic__6366
-reg__1193: reg__1193
-reg__121: reg__121
-case__942: case__942
-datapath__705: datapath__705
-datapath__425: datapath__425
-logic__6029: logic__6029
-datapath__246: datapath__246
-logic__4353: logic__4353
-double_ff_syn__4: double_ff_syn
-reg__402: reg__402
-reg__1359: reg__1359
-datapath__550: datapath__550
-logic__7752: logic__7752
-logic__9430: logic__9430
-case__554: case__554
-case__1723: case__1594
-logic__5434: logic__5434
-muxpart__24: muxpart__24
-logic__4488: logic__4488
-logic__6731: logic__6731
-logic__2926: logic__2926
-muxpart__43: muxpart__43
-muxpart__38: muxpart__38
-case__431: case__431
-logic__6155: logic__6155
-TLInterconnectCoupler_cbus_to_rockettile: TLInterconnectCoupler_cbus_to_rockettile
-datapath__501: datapath__501
-case__1502: case__1502
-logic: logic
-logic__2049: logic__2049
-logic__8610: logic__8610
-reg__457: reg__457
-logic__7272: logic__7272
-logic__5547: logic__5547
-logic__4770: logic__4770
-logic__7569: logic__7569
-case__249: case__249
-reg__828: reg__828
-logic__6123: logic__6123
-case__529: case__529
-logic__2168: logic__2168
-logic__5020: logic__5020
-case__245: case__245
-case__1534: case__1534
-logic__5479: logic__5479
-datapath__173: datapath__173
-case__1516: case__1516
-Queue1_RegMapperInput_i9_m8: Queue1_RegMapperInput_i9_m8
-reg__735: reg__735
-logic__7907: logic__7907
-case__1295: case__1295
-logic__9424: logic__9424
-logic__5173: logic__5173
-reg__196: reg__196
-logic__8018: logic__8018
-logic__9340: logic__9340
-logic__659: logic__659
-reg__40: reg__40
-case__458: case__458
-logic__9638: logic__1160
-datapath__290: datapath__290
-logic__5846: logic__5846
-case__25: case__25
-logic__1619: logic__1619
-reg__210: reg__210
-datapath__746: datapath__140
-logic__6052: logic__6052
-case__1065: case__1065
-logic__5577: logic__5577
-logic__8222: logic__8222
-logic__6997: logic__6997
-logic__6920: logic__6920
-muxpart__37: muxpart__37
-logic__144: logic__144
-logic__1334: logic__1334
-logic__4531: logic__4531
-logic__3477: logic__3477
-case__510: case__510
-logic__5989: logic__5989
-reg__380: reg__380
-logic__8792: logic__8792
-logic__3217: logic__3217
-logic__2099: logic__2099
-logic__316: logic__316
-logic__3770: logic__3770
-datapath__506: datapath__506
-logic__2606: logic__2606
-case__700: case__700
-logic__1852: logic__1852
-case__586: case__586
-case__1599: case__1599
-muxpart__223: muxpart__223
-counter__11: counter__11
-case__1164: case__1164
-logic__7364: logic__7364
-case__318: case__318
-case__1176: case__1176
-logic__5793: logic__5793
-logic__8042: logic__8042
-logic__9456: logic__9456
-logic__5576: logic__5576
-reg__553: reg__553
-logic__7636: logic__7636
-datapath__536: datapath__536
-logic__1935: logic__1935
-logic__1006: logic__1006
-logic__886: logic__886
-logic__6302: logic__6302
-logic__969: logic__969
-logic__5427: logic__5427
-case__828: case__828
-reg__1360: reg__1360
-logic__2682: logic__2682
-reg__1286: reg__1286
-logic__2866: logic__2866
-case__21: case__21
-logic__5257: logic__5257
-logic__9207: logic__9207
-reg__779: reg__779
-acq_top: acq_top
-case__687: case__687
-reg__250: reg__250
-case__373: case__373
-reg__790: reg__790
-logic__4771: logic__4771
-case__54: case__54
-logic__7194: logic__7194
-gray_to_binary: gray_to_binary
-case__773: case__773
-case__993: case__993
-case__1690: case__1690
-reg__836: reg__836
-case__134: case__134
-case__292: case__292
-case__1511: case__1511
-case__988: case__988
-datapath__233: datapath__233
-case__1331: case__1331
-datapath__412: datapath__412
-logic__8145: logic__8145
-logic__7998: logic__7998
-datapath__592: datapath__592
-case__1335: case__1335
-datapath__768: datapath__122
-reg__1297: reg__1297
-case__1575: case__1575
-logic__8147: logic__8147
-logic__2732: logic__2732
-logic__4083: logic__4083
-logic__9263: logic__9263
-reg__1471: reg__908
-logic__6622: logic__6622
-TLBuffer_a32d64s2k1z3u: TLBuffer_a32d64s2k1z3u
-logic__3214: logic__3214
-case__158: case__158
-logic__3498: logic__3498
-case__76: case__76
-logic__5030: logic__5030
-reg__441: reg__441
-logic__7337: logic__7337
-logic__4662: logic__4662
-case__169: case__169
-reg__148: reg__148
-case__1256: case__1256
-logic__2846: logic__2846
-reg__724: reg__724
-logic__7550: logic__7550
-logic__1292: logic__1292
-logic__2223: logic__2223
-logic__996: logic__996
-case__830: case__830
-logic__9262: logic__9262
-AsyncValidSync__16: AsyncValidSync
-logic__5437: logic__5437
-logic__9335: logic__9335
-logic__893: logic__893
-case__330: case__330
-logic__9295: logic__9295
-logic__1422: logic__1422
-AMOALU: AMOALU
-datapath__50: datapath__50
-reg__1144: reg__1144
-logic__8497: logic__8497
-Repeater_TLBundleA_a32d64s2k1z3u: Repeater_TLBundleA_a32d64s2k1z3u
-muxpart__73: muxpart__73
-logic__8044: logic__8044
-datapath__403: datapath__403
-reg__1493: reg__907
-logic__6825: logic__6825
-logic__5947: logic__5947
-logic__1854: logic__1854
-reg__1023: reg__1023
-datapath__276: datapath__276
-logic__6053: logic__6053
-logic__9608: logic__8143
-logic__6953: logic__6953
-case__589: case__589
-reg__669: reg__669
-logic__8862: logic__8862
-case__853: case__853
-logic__328: logic__328
-logic__283: logic__283
-logic__7292: logic__7292
-datapath__677: datapath__677
-datapath__111: datapath__111
-case__1591: case__1591
-reg__825: reg__825
-reg__221: reg__221
-logic__993: logic__993
-case__1638: case__1638
-logic__9477: logic__3639
-muxpart__53: muxpart__53
-logic__7408: logic__7408
-reg__280: reg__280
-dsp48e2__27: dsp48e2__27
-reg__64: reg__64
-reg__1468: reg__908
-datapath__136: datapath__136
-case__1136: case__1136
-case__1051: case__1051
-logic__7361: logic__7361
-case__1618: case__1618
-logic__9516: logic__4624
-case__233: case__233
-logic__7077: logic__7077
-case__1041: case__1041
-logic__1600: logic__1600
-datapath__407: datapath__407
-logic__2460: logic__2460
-logic__5963: logic__5963
-reg__938: reg__938
-reg__868: reg__868
-logic__1833: logic__1833
-logic__5438: logic__5438
-logic__3476: logic__3476
-reg__926: reg__926
-reg__1209: reg__1209
-logic__8979: logic__8979
-logic__2336: logic__2336
-logic__9647: logic__1139
-case__1096: case__1096
-reg__65: reg__65
-reg__182: reg__182
-trck_top: trck_top
-muxpart__20: muxpart__20
-logic__1954: logic__1954
-logic__4067: logic__4067
-case__1593: case__1593
-datapath__186: datapath__186
-reg__695: reg__695
-ram__8: ram__8
-logic__9232: logic__9232
-TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u: TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u
-logic__2742: logic__2742
-case__1537: case__1537
-logic__7857: logic__7857
-reg__877: reg__877
-reg__118: reg__118
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__9: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__1456: logic__1456
-logic__6660: logic__6660
-reg__763: reg__763
-reg__1447: reg__1067
-logic__7508: logic__7508
-logic__7159: logic__7159
-case__411: case__411
-logic__5245: logic__5245
-logic__6749: logic__6749
-Queue1_RegMapperInput_i9_m8__1: Queue1_RegMapperInput_i9_m8
-case__460: case__460
-datapath__151: datapath__151
-logic__6554: logic__6554
-case__316: case__316
-dsp48e2__41: dsp48e2__41
-logic__5980: logic__5980
-logic__9657: logic__934
-logic__5384: logic__5384
-reg__1046: reg__1046
-logic__6670: logic__6670
-logic__3993: logic__3993
-case__674: case__674
-reg__551: reg__551
-case__783: case__783
-logic__1620: logic__1620
-logic__908: logic__908
-datapath__54: datapath__54
-logic__6160: logic__6160
-case__1178: case__1178
-logic__5924: logic__5924
-reg__167: reg__167
-logic__6726: logic__6726
-reg__827: reg__827
-logic__6127: logic__6127
-logic__18: logic__18
-case__1220: case__1220
-logic__6667: logic__6667
-bit_gen: bit_gen
-reg__940: reg__940
-logic__989: logic__989
-case__171: case__171
-logic__970: logic__970
-reg__1317: reg__1317
-logic__9518: logic__4618
-case__572: case__572
-logic__3970: logic__3970
-rf_31x64: rf_31x64
-case__552: case__552
-datapath__232: datapath__232
-logic__9479: logic__3635
-case__1216: case__1216
-reg__670: reg__670
-muxpart__206: muxpart__206
-reg__513: reg__513
-logic__2424: logic__2424
-counter__21: counter__21
-datapath__424: datapath__424
-reg__506: reg__506
-FPUFMAPipe_l3_f32: FPUFMAPipe_l3_f32
-reg__1204: reg__1204
-ram_2x77__2: ram_2x77
-reg__438: reg__438
-logic__7135: logic__7135
-case__524: case__524
-logic__1372: logic__1372
-reg__1003: reg__1003
-logic__3428: logic__3428
-reg__324: reg__324
-datapath__28: datapath__28
-logic__9582: logic__1301
-reg__880: reg__880
-logic__2035: logic__2035
-datapath__62: datapath__62
-case__642: case__642
-datapath__631: datapath__631
-case__1048: case__1048
-logic__6194: logic__6194
-logic__899: logic__899
-reg__1154: reg__1154
-logic__5085: logic__5085
-case__51: case__51
-reg__1117: reg__1117
-logic__3681: logic__3681
-logic__5860: logic__5860
-datapath__285: datapath__285
-datapath__297: datapath__297
-logic__6850: logic__6850
-logic__4945: logic__4945
-case__319: case__319
-logic__4193: logic__4193
-reg__738: reg__738
-logic__2753: logic__2753
-datapath__452: datapath__452
-reg__527: reg__527
-logic__6300: logic__6300
-logic__1681: logic__1681
-reg__1382: reg__1382
-case__842: case__842
-case__1203: case__1203
-logic__5259: logic__5259
-reg__646: reg__646
-logic__7178: logic__7178
-logic__7618: logic__7618
-logic__5819: logic__5819
-muxpart__237: muxpart__237
-logic__9275: logic__9275
-case__1668: case__1668
-logic__1114: logic__1114
-IntXbar_i3_o1: IntXbar_i3_o1
-logic__2141: logic__2141
-logic__7207: logic__7207
-logic__6797: logic__6797
-logic__918: logic__918
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__11: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__4192: logic__4192
-case__986: case__986
-case__555: case__555
-logic__5225: logic__5225
-datapath__708: datapath__708
-logic__7417: logic__7417
-logic__4362: logic__4362
-logic__5254: logic__5254
-case__1620: case__1620
-logic__732: logic__732
-logic__6856: logic__6856
-muxpart__173: muxpart__173
-case__1432: case__1432
-reg__811: reg__811
-logic__3196: logic__3196
-case__505: case__505
-case__1172: case__1172
-reg__976: reg__976
-datapath__526: datapath__526
-reg__175: reg__175
-datapath__37: datapath__37
-logic__4924: logic__4924
-case__704: case__704
-logic__9578: logic__1310
-case__1477: case__1477
-logic__6143: logic__6143
-logic__803: logic__803
-reg__1108: reg__1108
-logic__7017: logic__7017
-case__903: case__903
-logic__6834: logic__6834
-case__1337: case__1337
-reg__529: reg__529
-case__511: case__511
-logic__4333: logic__4333
-logic__6804: logic__6804
-case__1701: case__654
-datapath__767: datapath__123
-datapath__282: datapath__282
-logic__7353: logic__7353
-logic__7269: logic__7269
-case__1010: case__1010
-reg__311: reg__311
-logic__5260: logic__5260
-logic__9289: logic__9289
-logic__2312: logic__2312
-case__421: case__421
-logic__982: logic__982
-reg__2: reg__2
-reg__1135: reg__1135
-reg__142: reg__142
-logic__8739: logic__8739
-logic__4245: logic__4245
-reg__1518: reg__906
-logic__9537: logic__4546
-case__984: case__984
-logic__3028: logic__3028
-logic__9503: logic__3571
-logic__6821: logic__6821
-case__467: case__467
-logic__1166: logic__1166
-logic__3300: logic__3300
-logic__6927: logic__6927
-logic__2524: logic__2524
-logic__2463: logic__2463
-datapath__271: datapath__271
-datapath__90: datapath__90
-logic__8794: logic__8794
-datapath__356: datapath__356
-datapath__181: datapath__181
-reg__706: reg__706
-reg__1448: reg__1069
-logic__4358: logic__4358
-case__1261: case__1261
-logic__1819: logic__1819
-reg__170: reg__170
-logic__9616: logic__6769
-logic__9542: logic__4534
-logic__8795: logic__8795
-reg__1535: reg__907
-logic__7421: logic__7421
-case__971: case__971
-case__1369: case__1369
-logic__7795: logic__7795
-logic__2715: logic__2715
-datapath__321: datapath__321
-case__349: case__349
-logic__3026: logic__3026
-logic__6060: logic__6060
-datapath__602: datapath__602
-muxpart__218: muxpart__218
-case__541: case__541
-datapath__105: datapath__105
-logic__8749: logic__8749
-case__261: case__261
-logic__2091: logic__2091
-case__1243: case__1243
-case__1709: case__727
-reg__907: reg__907
-logic__6765: logic__6765
-logic__2104: logic__2104
-logic__2663: logic__2663
-logic__251: logic__251
-case__1039: case__1039
-logic__1904: logic__1904
-logic__3249: logic__3249
-logic__3326: logic__3326
-logic__3215: logic__3215
-case__1592: case__1592
-logic__3856: logic__3856
-logic__3503: logic__3503
-logic__5845: logic__5845
-logic__4369: logic__4369
-reg__1190: reg__1190
-case__345: case__345
-logic__1195: logic__1195
-datapath__252: datapath__252
-logic__5584: logic__5584
-case__1715: case__1602
-logic__7430: logic__7430
-logic__1670: logic__1670
-datapath__377: datapath__377
-datapath__249: datapath__249
-reg__105: reg__105
-RVCExpander: RVCExpander
-Rocket: Rocket
-case__902: case__902
-logic__990: logic__990
-logic__9483: logic__3623
-case__1669: case__1669
-reg__675: reg__675
-reg__613: reg__613
-logic__8226: logic__8226
-logic__38: logic__38
-case__329: case__329
-logic__2881: logic__2881
-logic__7151: logic__7151
-NonSyncResetSynchronizerPrimitiveShiftReg_d3: NonSyncResetSynchronizerPrimitiveShiftReg_d3
-muxpart__84: muxpart__84
-logic__7223: logic__7223
-reg__413: reg__413
-logic__5531: logic__5531
-logic__5745: logic__5745
-logic__8494: logic__8494
-reg__854: reg__854
-logic__1873: logic__1873
-reg__672: reg__672
-logic__3256: logic__3256
-case__1561: case__1561
-datapath__613: datapath__613
-logic__7264: logic__7264
-case__869: case__869
-reg__680: reg__680
-logic__5095: logic__5095
-logic__7833: logic__7833
-logic__2015: logic__2015
-logic__2337: logic__2337
-logic__6890: logic__6890
-logic__7526: logic__7526
-logic__2540: logic__2540
-datapath__742: datapath__43
-case__1059: case__1059
-reg__187: reg__187
-muxpart__7: muxpart__7
-logic__1536: logic__1536
-divider: divider
-datapath__94: datapath__94
-datapath__279: datapath__279
-logic__4214: logic__4214
-logic__7157: logic__7157
-logic__8034: logic__8034
-reg__162: reg__162
-logic__2674: logic__2674
-logic__2750: logic__2750
-reg__1025: reg__1025
-case__1221: case__1221
-logic__6761: logic__6761
-logic__5737: logic__5737
-logic__4751: logic__4751
-case__409: case__409
-logic__3317: logic__3317
-case__816: case__816
-logic__9249: logic__9249
-case__1100: case__1100
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__15: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__5537: logic__5537
-reg__490: reg__490
-AsyncQueueSource_DebugInternalBundle: AsyncQueueSource_DebugInternalBundle
-ShiftQueue: ShiftQueue
-logic__4386: logic__4386
-case__72: case__72
-datapath__88: datapath__88
-logic__7001: logic__7001
-case__1329: case__1329
-logic__9614: logic__6769
-reg__944: reg__944
-reg__257: reg__257
-datapath__482: datapath__482
-logic__5991: logic__5991
-datapath__507: datapath__507
-logic__6666: logic__6666
-case__454: case__454
-reg__804: reg__804
-logic__9370: logic__9370
-logic__7041: logic__7041
-reg__116: reg__116
-logic__2469: logic__2469
-logic__3493: logic__3493
-logic__5311: logic__5311
-logic__5328: logic__5328
-reg__1367: reg__1367
-case__1423: case__1423
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__315: reg__315
-logic__5907: logic__5907
-datapath__404: datapath__404
-logic__3484: logic__3484
-case__1285: case__1285
-case__1210: case__1210
-logic__6028: logic__6028
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__2: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__1371: reg__1371
-logic__4752: logic__4752
-logic__6800: logic__6800
-logic__8059: logic__8059
-logic__7746: logic__7746
-logic__7331: logic__7331
-logic__8427: logic__8427
-reg__190: reg__190
-logic__1535: logic__1535
-datapath__431: datapath__431
-logic__9531: logic__4596
-logic__6130: logic__6130
-reg__153: reg__153
-case__1665: case__1665
-muxpart__272: muxpart__272
-reg__26: reg__26
-logic__5981: logic__5981
-reg__969: reg__969
-logic__9419: logic__9419
-logic__7426: logic__7426
-case__970: case__970
-case__1670: case__1670
-case__466: case__466
-case__1324: case__1324
-reg__1116: reg__1116
-reg__193: reg__193
-case__938: case__938
-case__750: case__750
-datapath__373: datapath__373
-reg__890: reg__890
-nav_solve_timer: nav_solve_timer
-TLXbar_pbus_out_i1_o3_a29d64s2k1z3u: TLXbar_pbus_out_i1_o3_a29d64s2k1z3u
-logic__2737: logic__2737
-logic__6102: logic__6102
-logic__7698: logic__7698
-logic__9045: logic__9045
-logic__839: logic__839
-logic__4946: logic__4946
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__18: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__3462: logic__3462
-logic__4517: logic__4517
-ClockGroup__1: ClockGroup
-logic__5216: logic__5216
-logic__623: logic__623
-logic__3967: logic__3967
-logic__7181: logic__7181
-logic__1985: logic__1985
-logic__3742: logic__3742
-muxpart__209: muxpart__209
-reg__89: reg__89
-ClockGroupAggregator_cbus: ClockGroupAggregator_cbus
-reg__425: reg__425
-TLWidthWidget8_3: TLWidthWidget8_3
-logic__4913: logic__4913
-TLFragmenter_CLINT: TLFragmenter_CLINT
-datapath__369: datapath__369
-reg__483: reg__483
-logic__7251: logic__7251
-datapath__486: datapath__486
-datapath__73: datapath__73
-logic__5250: logic__5250
-case__607: case__607
-reg__224: reg__224
-case__1703: case__652
-case__304: case__304
-datapath__596: datapath__596
-logic__6782: logic__6782
-logic__2587: logic__2587
-logic__892: logic__892
-Queue1_TLBundleD_a29d32s7k1z2u: Queue1_TLBundleD_a29d32s7k1z2u
-logic__7158: logic__7158
-case__920: case__920
-logic__7200: logic__7200
-case__672: case__672
-logic__4619: logic__4619
-logic__310: logic__310
-logic__7290: logic__7290
-case__880: case__880
-datapath__261: datapath__261
-case__164: case__164
-case__1659: case__1659
-logic__9288: logic__9288
-logic__2679: logic__2679
-ram__12: ram__2
-case__849: case__849
-logic__6751: logic__6751
-case__395: case__395
-muxpart__45: muxpart__45
-reg__41: reg__41
-reg__1273: reg__1273
-MulAddRecFNToRaw_postMul: MulAddRecFNToRaw_postMul
-logic__9438: logic__9438
-logic__7217: logic__7217
-reg__876: reg__876
-logic__6131: logic__6131
-reg__398: reg__398
-datapath__427: datapath__427
-logic__8142: logic__8142
-logic__250: logic__250
-reg__590: reg__590
-reg__965: reg__965
-logic__5753: logic__5753
-case__549: case__549
-reg__1182: reg__1182
-case__538: case__538
-logic__3530: logic__3530
-datapath__46: datapath__46
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__5: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__6993: logic__6993
-logic__356: logic__356
-logic__2711: logic__2711
-reg__716: reg__716
-reg__486: reg__486
-case__476: case__476
-reg__1073: reg__1073
-logic__1135: logic__1135
-case__1042: case__1042
-logic__7054: logic__7054
-datapath__721: datapath__721
-logic__3702: logic__3702
-extram__1: extram__1
-datapath__428: datapath__428
-eth_rf_mdio_init: eth_rf_mdio_init
-logic__5613: logic__5613
-case__1341: case__1341
-logic__4961: logic__4961
-case__38: case__38
-TLROM: TLROM
-logic__175: logic__175
-datapath__125: datapath__125
-reg__528: reg__528
-logic__7270: logic__7270
-logic__7021: logic__7021
-logic__890: logic__890
-case__578: case__578
-logic__7406: logic__7406
-logic__6809: logic__6809
-logic__6759: logic__6759
-logic__2294: logic__2294
-logic__9365: logic__9365
-logic__1159: logic__1159
-logic__2604: logic__2604
-logic__2397: logic__2397
-case__742: case__742
-muxpart__244: muxpart__244
-case__317: case__317
-Repeater_TLBundleA_a29d64s2k1z3u: Repeater_TLBundleA_a29d64s2k1z3u
-logic__2509: logic__2509
-logic__5122: logic__5122
-logic__7177: logic__7177
-reg__127: reg__127
-case__553: case__553
-case__1718: case__1599
-logic__1920: logic__1920
-logic__4518: logic__4518
-logic__3164: logic__3164
-logic__6683: logic__6683
-reg__1482: reg__906
-logic__2208: logic__2208
-reg__332: reg__332
-logic__8926: logic__8926
-datapath__235: datapath__235
-case__60: case__60
-datapath__548: datapath__548
-logic__116: logic__116
-reg__962: reg__962
-reg__850: reg__850
-logic__420: logic__420
-logic__2960: logic__2960
-reg__505: reg__505
-datapath__458: datapath__458
-logic__4617: logic__4617
-datapath__85: datapath__85
-datapath__284: datapath__284
-logic__1697: logic__1697
-logic__6167: logic__6167
-logic__636: logic__636
-case__669: case__669
-logic__4355: logic__4355
-logic__8880: logic__8880
-reg__541: reg__541
-reg__279: reg__279
-datapath__3: datapath__3
-case__407: case__407
-logic__3628: logic__3628
-case__1601: case__1601
-logic__6946: logic__6946
-datapath__218: datapath__218
-logic__1555: logic__1555
-logic__1423: logic__1423
-logic__6311: logic__6311
-logic__8820: logic__8820
-logic__6928: logic__6928
-reg__745: reg__745
-case__1495: case__1495
-logic__5445: logic__5445
-reg__1265: reg__1265
-ScratchpadSlavePort: ScratchpadSlavePort
-case__691: case__691
-logic__4635: logic__4635
-logic__1100: logic__1100
-case__1508: case__1508
-reg__1387: reg__1387
-reg__1383: reg__1383
-logic__654: logic__654
-logic__921: logic__921
-logic__9659: logic__929
-logic__676: logic__676
-logic__6758: logic__6758
-reg__820: reg__820
-cdc_fifo_gray_dst: cdc_fifo_gray_dst
-case__531: case__531
-datapath__236: datapath__236
-reg__526: reg__526
-datapath__396: datapath__396
-case__641: case__641
-muxpart__216: muxpart__216
-reg__150: reg__150
-reg__1000: reg__1000
-logic__1534: logic__1534
-logic__5315: logic__5315
-datapath__384: datapath__384
-logic__5587: logic__5587
-logic__7875: logic__7875
-rom: rom
-logic__5918: logic__5918
-case__313: case__313
-logic__4180: logic__4180
-case__537: case__537
-logic__9192: logic__9192
-case__1158: case__1158
-muxpart__353: muxpart__353
-logic__7643: logic__7643
-logic__5159: logic__5159
-logic__1452: logic__1452
-case__1365: case__1365
-logic__9395: logic__9395
-case__1043: case__1043
-logic__3186: logic__3186
-counter__31: counter__31
-logic__3873: logic__3873
-case__1499: case__1499
-case__1481: case__1481
-logic__7161: logic__7161
-reg__227: reg__227
-logic__455: logic__455
-datapath__242: datapath__242
-reg__791: reg__791
-logic__6551: logic__6551
-logic__4092: logic__4092
-datapath__540: datapath__540
-reg__1547: reg__907
-logic__9522: logic__4610
-logic__1652: logic__1652
-logic__4359: logic__4359
-logic__6658: logic__6658
-datapath__538: datapath__538
-reg__922: reg__922
-logic__3315: logic__3315
-case__246: case__246
-datapath__413: datapath__413
-logic__2520: logic__2520
-reg__688: reg__688
-logic__4408: logic__4408
-logic__2813: logic__2813
-case__498: case__498
-logic__7257: logic__7257
-logic__6799: logic__6799
-logic__3532: logic__3532
-reg__1271: reg__1271
-logic__3072: logic__3072
-reg__554: reg__554
-logic__797: logic__797
-reg__1079: reg__1079
-logic__6721: logic__6721
-logic__2670: logic__2670
-reg__33: reg__33
-datapath__472: datapath__472
-logic__3488: logic__3488
-logic__9565: logic__2482
-logic__9319: logic__9319
-case__77: case__77
-logic__8214: logic__8214
-logic__8876: logic__8876
-datapath__286: datapath__286
-datapath__457: datapath__457
-logic__2119: logic__2119
-datapath__121: datapath__121
-logic__1110: logic__1110
-BreakpointUnit: BreakpointUnit
-case__1239: case__1239
-reg__913: reg__913
-logic__8931: logic__8931
-datapath__449: datapath__449
-case__1706: case__731
-logic__4720: logic__4720
-logic__6133: logic__6133
-logic__7415: logic__7415
-logic__1585: logic__1585
-case__936: case__936
-logic__7000: logic__7000
-acq_corr: acq_corr
-logic__6334: logic__6334
-case__680: case__680
-case__1023: case__1023
-case__226: case__226
-case__300: case__300
-logic__1057: logic__1057
-reg__327: reg__327
-logic__3042: logic__3042
-IntSyncCrossingSource_n1x2: IntSyncCrossingSource_n1x2
-case__382: case__382
-logic__9591: logic__8988
-DCache: DCache
-logic__769: logic__769
-logic__4373: logic__4373
-logic__9233: logic__9233
-reg__1514: reg__907
-logic__4890: logic__4890
-case__1667: case__1667
-logic__5987: logic__5987
-reg__112: reg__112
-reg__1029: reg__1029
-reg__432: reg__432
-datapath__504: datapath__504
-muxpart__22: muxpart__22
-reg__1180: reg__1180
-case__1363: case__1363
-logic__9590: logic__8991
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__16: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__57: datapath__57
-reg__556: reg__556
-datapath__185: datapath__185
-logic__4705: logic__4705
-ClockGroupAggregator_pbus: ClockGroupAggregator_pbus
-logic__5726: logic__5726
-logic__6835: logic__6835
-rockettile_icache_data_arrays_512x32__1: rockettile_icache_data_arrays_512x32
-reg__1292: reg__1292
-logic__3261: logic__3261
-logic__3407: logic__3407
-logic__4952: logic__4952
-logic__313: logic__313
-datapath__551: datapath__551
-case__1427: case__1427
-logic__7355: logic__7355
-case__314: case__314
-case__627: case__627
-Arbiter8_DCacheMetadataReq: Arbiter8_DCacheMetadataReq
-logic__7291: logic__7291
-reg__163: reg__163
-logic__2766: logic__2766
-logic__7196: logic__7196
-reg__566: reg__566
-logic__6853: logic__6853
-datapath__247: datapath__247
-reg__60: reg__60
-logic__22: logic__22
-logic__713: logic__713
-logic__4137: logic__4137
-case__2: case__2
-reg__975: reg__975
-case__266: case__266
-logic__9000: logic__9000
-Queue2_TLBundleD_a29d64s2k1z3u__1: Queue2_TLBundleD_a29d64s2k1z3u
-case__463: case__463
-case__151: case__151
-reg__1155: reg__1155
-logic__4482: logic__4482
-case__1435: case__1435
-datapath__150: datapath__150
-case__146: case__146
-case__247: case__247
-AsyncResetSynchronizerShiftReg_w1_d3_i0__8: AsyncResetSynchronizerShiftReg_w1_d3_i0
-FixedClockBroadcast_3: FixedClockBroadcast_3
-logic__122: logic__122
-logic__9390: logic__9390
-case__896: case__896
-reg__269: reg__269
-logic__1464: logic__1464
-logic__9290: logic__9290
-logic__8613: logic__8613
-ClockGroup__3: ClockGroup
-logic__4114: logic__4114
-cordic_atan_one_stage: cordic_atan_one_stage
-case__567: case__567
-logic__6805: logic__6805
-logic__5856: logic__5856
-keep__2: keep__2
-logic__355: logic__355
-case__914: case__914
-logic__2246: logic__2246
-case__1157: case__1157
-keep__10: keep__10
-logic__7110: logic__7110
-logic__7028: logic__7028
-logic__6949: logic__6949
-reg__818: reg__818
-reg__796: reg__796
-logic__6883: logic__6883
-logic__668: logic__668
-case__1212: case__1212
-case__1057: case__1057
-logic__7943: logic__7943
-logic__5861: logic__5861
-reg__297: reg__297
-logic__7160: logic__7160
-case__1006: case__1006
-datapath__108: datapath__108
-dsp48e2__17: dsp48e2__17
-logic__381: logic__381
-TLBuffer_a14d64s2k1z4u: TLBuffer_a14d64s2k1z4u
-logic__1671: logic__1671
-datapath__695: datapath__695
-dsp48e2__25: dsp48e2__25
-case__452: case__452
-datapath__655: datapath__655
-logic__2568: logic__2568
-reg__714: reg__714
-logic__5440: logic__5440
-case__371: case__371
-case__1622: case__1622
-logic__9251: logic__9251
-case__1234: case__1234
-reg__731: reg__731
-logic__916: logic__916
-logic__70: logic__70
-logic__6590: logic__6590
-reg__879: reg__879
-reg__225: reg__225
-datapath__58: datapath__58
-case__1074: case__1074
-logic__5096: logic__5096
-case__1366: case__1366
-datapath__214: datapath__214
-logic__2765: logic__2765
-logic__4256: logic__4256
-case__499: case__499
-reg__1390: reg__1390
-logic__4025: logic__4025
-muxpart__263: muxpart__263
-reg__1185: reg__1185
-case__299: case__299
-logic__2784: logic__2784
-logic__5625: logic__5625
-logic__2059: logic__2059
-logic__5571: logic__5571
-logic__5926: logic__5926
-case__580: case__580
-logic__6763: logic__6763
-case__495: case__495
-logic__4757: logic__4757
-case__1419: case__1419
-logic__3237: logic__3237
-logic__3639: logic__3639
-reg__808: reg__808
-logic__3293: logic__3293
-case__582: case__582
-case__1547: case__1547
-case__818: case__818
-case__1184: case__1184
-logic__7175: logic__7175
-cdc_fifo_gray_src: cdc_fifo_gray_src
-case__312: case__312
-logic__2697: logic__2697
-logic__7783: logic__7783
-logic__7256: logic__7256
-logic__3265: logic__3265
-reg__912: reg__912
-reg__1090: reg__1090
-logic__8973: logic__8973
-reg__102: reg__102
-logic__2295: logic__2295
-logic__1909: logic__1909
-reg__1353: reg__1353
-logic__7977: logic__7977
-logic__6069: logic__6069
-reg__149: reg__149
-logic__9304: logic__9304
-logic__4385: logic__4385
-case__629: case__629
-reg__145: reg__145
-datapath__101: datapath__101
-case__530: case__530
-AsyncValidSync__12: AsyncValidSync
-reg__1270: reg__1270
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__29: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__4791: logic__4791
-logic__5973: logic__5973
-case__451: case__451
-logic__1443: logic__1443
-datapath__367: datapath__367
-logic__2506: logic__2506
-muxpart__233: muxpart__233
-logic__896: logic__896
-logic__3453: logic__3453
-logic__5209: logic__5209
-logic__8511: logic__8511
-logic__7176: logic__7176
-case__337: case__337
-logic__4809: logic__4809
-reg__1483: reg__908
-datapath__654: datapath__654
-case__525: case__525
-case__424: case__424
-logic__6356: logic__6356
-case__948: case__948
-reg__743: reg__743
-reg__473: reg__473
-datapath__149: datapath__149
-logic__7995: logic__7995
-reg__567: reg__567
-reg__906: reg__906
-logic__3406: logic__3406
-reg__1558: reg__239
-logic__302: logic__302
-logic__4291: logic__4291
-reg__1549: reg__856
-logic__6196: logic__6196
-case__676: case__676
-logic__1980: logic__1980
-case__33: case__33
-logic__5423: logic__5423
-muxpart__152: muxpart__152
-reg__1061: reg__1061
-logic__1559: logic__1559
-reg__334: reg__334
-reg__546: reg__546
-logic__317: logic__317
-logic__206: logic__206
-logic__4814: logic__4814
-logic__5930: logic__5930
-case__1551: case__1551
-logic__6762: logic__6762
-keep__52: keep__9
-case__149: case__149
-logic__7271: logic__7271
-logic__4825: logic__4825
-logic__256: logic__256
-case__1144: case__1144
-datapath__130: datapath__130
-case__230: case__230
-reg__1318: reg__1318
-logic__7937: logic__7937
-TLWidthWidget1: TLWidthWidget1
-logic__4057: logic__4057
-logic__5489: logic__5489
-OptimizationBarrier_TLBEntryData: OptimizationBarrier_TLBEntryData
-logic__734: logic__734
-reg__1344: reg__1344
-logic__8914: logic__8914
-case__1209: case__1209
-datapath__72: datapath__72
-case__633: case__633
-logic__7036: logic__7036
-logic__3850: logic__3850
-case__859: case__859
-logic__1000: logic__1000
-logic__2106: logic__2106
-logic__1782: logic__1782
-logic__5060: logic__5060
-case__738: case__738
-logic__7976: logic__7976
-reg__951: reg__951
-logic__3298: logic__3298
-case__1134: case__1134
-logic__7357: logic__7357
-logic__5287: logic__5287
-logic__1125: logic__1125
-logic__8604: logic__8604
-reg__1305: reg__1305
-logic__3685: logic__3685
-double_ff_syn__1: double_ff_syn
-logic__236: logic__236
-case__1175: case__1175
-logic__8927: logic__8927
-logic__6829: logic__6829
-logic__4676: logic__4676
-datapath__707: datapath__707
-case__173: case__173
-reg__268: reg__268
-logic__8174: logic__8174
-case__408: case__408
-logic__714: logic__714
-counter__5: counter__5
-logic__2585: logic__2585
-logic__753: logic__753
-case__1236: case__1236
-datapath__32: datapath__32
-logic__6548: logic__6548
-reg__169: reg__169
-case__1692: case__1692
-logic__1196: logic__1196
-FPToInt: FPToInt
-ram_2x78__1: ram_2x78
-logic__4977: logic__4977
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__21: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__235: reg__235
-case__67: case__67
-case__925: case__925
-case__1121: case__1121
-logic__765: logic__765
-logic__7365: logic__7365
-logic__2412: logic__2412
-reg__179: reg__179
-TLAsyncCrossingSink_a9d32s1k1z2u: TLAsyncCrossingSink_a9d32s1k1z2u
-logic__6938: logic__6938
-SBToTL: SBToTL
-case__1684: case__1684
-case__908: case__908
-logic__1113: logic__1113
-logic__5127: logic__5127
-logic__7049: logic__7049
-logic__5056: logic__5056
-logic__7924: logic__7924
-logic__2772: logic__2772
-logic__8995: logic__8995
-case__620: case__620
-logic__5941: logic__5941
-ram_2x99: ram_2x99
-reg__137: reg__137
-logic__3502: logic__3502
-reg__894: reg__894
-logic__1003: logic__1003
-MulAddRecFNToRaw_preMul: MulAddRecFNToRaw_preMul
-datapath__302: datapath__302
-logic__1579: logic__1579
-logic__8527: logic__8527
-logic__231: logic__231
-case__811: case__811
-counter__29: counter__29
-logic__4102: logic__4102
-logic__9133: logic__9133
-logic__7242: logic__7242
-logic__8504: logic__8504
-logic__5368: logic__5368
-logic__3303: logic__3303
-logic__5026: logic__5026
-logic__7396: logic__7396
-case__1724: case__1593
-logic__5599: logic__5599
-datapath__588: datapath__588
-logic__1529: logic__1529
-logic__8264: logic__8264
-case__945: case__945
-case__624: case__624
-logic__6708: logic__6708
-case__482: case__482
-case__419: case__419
-reg__1191: reg__1191
-logic__5037: logic__5037
-logic__3015: logic__3015
-case__39: case__39
-datapath__463: datapath__463
-case__1619: case__1619
-logic__338: logic__338
-muxpart__28: muxpart__28
-case__1424: case__1424
-logic__1908: logic__1908
-logic__1892: logic__1892
-case__679: case__679
-case__377: case__377
-reg__1287: reg__1287
-muxpart__59: muxpart__59
-case__667: case__667
-datapath__93: datapath__93
-reg__1404: reg__1404
-logic__2649: logic__2649
-logic__7473: logic__7473
-reg__1141: reg__1141
-logic__9553: logic__2518
-reg__578: reg__578
-logic__4360: logic__4360
-logic__8221: logic__8221
-logic__8784: logic__8784
-logic__5160: logic__5160
-datapath__170: datapath__170
-logic__8485: logic__8485
-logic__9437: logic__9437
-logic__3232: logic__3232
-logic__733: logic__733
-case__66: case__66
-logic__243: logic__243
-logic__7347: logic__7347
-logic__6709: logic__6709
-case__1635: case__1635
-case__156: case__156
-datapath__353: datapath__353
-logic__4181: logic__4181
-case__1536: case__1536
-muxpart__148: muxpart__148
-reg__199: reg__199
-logic__2859: logic__2859
-reg__954: reg__954
-logic__8767: logic__8767
-datapath__752: datapath__692
-datapath__340: datapath__340
-TLInterconnectCoupler_cbus_to_clint: TLInterconnectCoupler_cbus_to_clint
-datapath__114: datapath__114
-logic__9238: logic__9238
-logic__5946: logic__5946
-logic__6543: logic__6543
-case__1235: case__1235
-reg__647: reg__647
-logic__3496: logic__3496
-logic__9050: logic__9050
-logic__1986: logic__1986
-logic__1898: logic__1898
-case__744: case__744
-logic__7146: logic__7146
-case__398: case__398
-logic__2539: logic__2539
-muxpart__192: muxpart__192
-case__574: case__574
-logic__8352: logic__8352
-logic__7936: logic__7936
-case__793: case__793
-logic__5735: logic__5735
-datapath__205: datapath__205
-logic__2970: logic__2970
-logic__1612: logic__1612
-logic__4368: logic__4368
-datapath__511: datapath__511
-logic__3551: logic__3551
-case__1611: case__1611
-datapath__221: datapath__221
-muxpart__190: muxpart__190
-logic__4812: logic__4812
-case__1153: case__1153
-case__1226: case__1226
-ram_2x123__1: ram_2x123
-logic__2777: logic__2777
-logic__5460: logic__5460
-logic__4485: logic__4485
-logic__272: logic__272
-keep__42: keep__13
-reg__276: reg__276
-logic__849: logic__849
-reg__775: reg__775
-reg__1522: reg__908
-case__521: case__521
-reg__1507: reg__908
-case__481: case__481
-reg__411: reg__411
-datapath__619: datapath__619
-logic__5975: logic__5975
-logic__2201: logic__2201
-dsp48e2__37: dsp48e2__37
-logic__2503: logic__2503
-reg__622: reg__622
-case__1737: case__301
-reg__91: reg__91
-logic__9580: logic__1306
-case__128: case__128
-logic__784: logic__784
-muxpart__252: muxpart__252
-reg__1222: reg__1222
-logic__4098: logic__4098
-datapath__438: datapath__438
-logic__388: logic__388
-datapath__10: datapath__10
-datapath__519: datapath__519
-datapath__67: datapath__67
-reset_synch: reset_synch
-case__1550: case__1550
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__12: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__4711: logic__4711
-case__1110: case__1110
-case__52: case__52
-reg__1467: reg__906
-logic__4880: logic__4880
-logic__5958: logic__5958
-case__775: case__775
-logic__1046: logic__1046
-logic__6975: logic__6975
-case__592: case__592
-logic__5415: logic__5415
-datapath__17: datapath__17
-logic__7986: logic__7986
-logic__7193: logic__7193
-reg__1300: reg__1300
-Queue2_TLBundleA_a29d64s2k1z3u: Queue2_TLBundleA_a29d64s2k1z3u
-logic__2907: logic__2907
-logic__9165: logic__9165
-case__890: case__890
-logic__2324: logic__2324
-case__1326: case__1326
-logic__4939: logic__4939
-reg__981: reg__981
-reg__255: reg__255
-logic__1337: logic__1337
-datapath__555: datapath__555
-case__45: case__45
-reg__1370: reg__1370
-logic__8626: logic__8626
-logic__4964: logic__4964
-logic__8801: logic__8801
-case__623: case__623
-logic__4136: logic__4136
-logic__7180: logic__7180
-logic__1279: logic__1279
-logic__9092: logic__9092
-logic__9601: logic__8795
-case__1642: case__1642
-logic__305: logic__305
-logic__7630: logic__7630
-case__1045: case__1045
-logic__7375: logic__7375
-logic__5605: logic__5605
-case__897: case__897
-logic__4080: logic__4080
-case__701: case__701
-logic__7185: logic__7185
-reg__1187: reg__1187
-datapath__298: datapath__298
-reg__370: reg__370
-logic__1027: logic__1027
-logic__5215: logic__5215
-case__201: case__201
-logic__4997: logic__4997
-logic__2210: logic__2210
-logic__5744: logic__5744
-logic__8805: logic__8805
-reg__1524: reg__906
-logic__6621: logic__6621
-reg__1379: reg__1379
-logic__9085: logic__9085
-reg__978: reg__978
-logic__9250: logic__9250
-logic__759: logic__759
-logic__3492: logic__3492
-case__686: case__686
-reg__829: reg__829
-reg__1351: reg__1351
-logic__8690: logic__8690
-logic__7870: logic__7870
-reg__594: reg__594
-reg__656: reg__656
-logic__5921: logic__5921
-logic__5047: logic__5047
-logic__2067: logic__2067
-ClockGroup: ClockGroup
-logic__745: logic__745
-logic__6647: logic__6647
-logic__112: logic__112
-reg__1565: reg__152
-datapath__260: datapath__260
-logic__7544: logic__7544
-muxpart__228: muxpart__228
-datapath__659: datapath__659
-logic__2080: logic__2080
-reg__741: reg__741
-datapath__363: datapath__363
-logic__7991: logic__7991
-logic__9422: logic__9422
-muxpart__41: muxpart__41
-regfile_32x65: regfile_32x65
-logic__7420: logic__7420
-logic__6817: logic__6817
-logic__5618: logic__5618
-MulAddRecFNPipe_l2_e11_s53: MulAddRecFNPipe_l2_e11_s53
-case__544: case__544
-logic__2050: logic__2050
-reg__1299: reg__1299
-case__1636: case__1636
-reg__640: reg__640
-Queue2_TLBundleA_a32d64s1k1z4u__1: Queue2_TLBundleA_a32d64s1k1z4u
-logic__794: logic__794
-logic__3474: logic__3474
-logic__95: logic__95
-logic__9662: logic__921
-logic__6537: logic__6537
-logic__3905: logic__3905
-datapath__349: datapath__349
-logic__7244: logic__7244
-logic__5960: logic__5960
-reg__375: reg__375
-reg__514: reg__514
-logic__5147: logic__5147
-logic__3089: logic__3089
-logic__1079: logic__1079
-logic__2161: logic__2161
-reg__893: reg__893
-logic__7680: logic__7680
-logic__9206: logic__9206
-logic__3412: logic__3412
-logic__2140: logic__2140
-logic__8857: logic__8857
-muxpart__74: muxpart__74
-logic__180: logic__180
-extram__5: extram__5
-reg__934: reg__934
-logic__6166: logic__6166
-logic__8917: logic__8917
-logic__8474: logic__8474
-muxpart__255: muxpart__255
-logic__7280: logic__7280
-reg__248: reg__248
-case__284: case__284
-logic__2317: logic__2317
-logic__4354: logic__4354
-logic__6527: logic__6527
-dsp48e2__12: dsp48e2__12
-case__1142: case__1142
-logic__682: logic__682
-case__808: case__808
-keep__22: keep__12
-muxpart__89: muxpart__89
-logic__1950: logic__1950
-logic__3550: logic__3550
-datapath__360: datapath__360
-logic__3241: logic__3241
-logic__5333: logic__5333
-logic__4476: logic__4476
-logic__1320: logic__1320
-logic__2622: logic__2622
-muxpart__49: muxpart__49
-case__1303: case__1303
-logic__637: logic__637
-datapath__146: datapath__146
-reg__1211: reg__1211
-logic__6871: logic__6871
-reg__443: reg__443
-logic__5969: logic__5969
-logic__8507: logic__8507
-case__975: case__975
-logic__392: logic__392
-logic__1414: logic__1414
-logic__1179: logic__1179
-reg__974: reg__974
-logic__6878: logic__6878
-reg__1424: reg__1322
-Queue2_TLBundleD_a32d64s1k1z4u__1: Queue2_TLBundleD_a32d64s1k1z4u
-logic__864: logic__864
-logic__3744: logic__3744
-logic__1755: logic__1755
-logic__2818: logic__2818
-logic__1530: logic__1530
-datapath__653: datapath__653
-logic__7863: logic__7863
-reg__723: reg__723
-logic__635: logic__635
-logic__6370: logic__6370
-logic__7112: logic__7112
-logic__5627: logic__5627
-datapath__571: datapath__571
-logic__3737: logic__3737
-logic__1494: logic__1494
-datapath__106: datapath__106
-case__279: case__279
-logic__134: logic__134
-muxpart__92: muxpart__92
-muxpart__71: muxpart__71
-ram__11: ram__1
-logic__1916: logic__1916
-datapath__763: datapath__165
-logic__7387: logic__7387
-logic__4197: logic__4197
-case__70: case__70
-case__381: case__381
-logic__4869: logic__4869
-logic__642: logic__642
-logic__8345: logic__8345
-reg__967: reg__967
-logic__9194: logic__9194
-logic__4397: logic__4397
-logic__4520: logic__4520
-datapath__376: datapath__376
-logic__7100: logic__7100
-logic__1860: logic__1860
-case__1428: case__1428
-logic__7189: logic__7189
-logic__9625: logic__6774
-case__1250: case__1250
-case__1652: case__1652
-case__1583: case__1583
-datapath__562: datapath__562
-counter__10: counter__10
-datapath__636: datapath__636
-case__1327: case__1327
-logic__3294: logic__3294
-logic__415: logic__415
-logic__2586: logic__2586
-datapath__61: datapath__61
-reg__1189: reg__1189
-case__819: case__819
-logic__6757: logic__6757
-case__1695: case__661
-logic__2692: logic__2692
-reg__1335: reg__1335
-datapath__505: datapath__505
-logic__6357: logic__6357
-case__506: case__506
-rockettile_icache_tag_array_64x21: rockettile_icache_tag_array_64x21
-logic__3898: logic__3898
-reg__1247: reg__1247
-logic__3605: logic__3605
-logic__2205: logic__2205
-logic__4497: logic__4497
-reg__1169: reg__1169
-datapath__203: datapath__203
-case__929: case__929
-case__664: case__664
-datapath__751: datapath__693
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__13: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-rom__4: rom__4
-logic__4185: logic__4185
-datapath__45: datapath__45
-logic__5922: logic__5922
-logic__9501: logic__3586
-datapath__168: datapath__168
-muxpart__383: muxpart__383
-case__142: case__142
-case__214: case__214
-logic__9639: logic__1159
-logic__8606: logic__8606
-logic__3855: logic__3855
-reg__1337: reg__1337
-case__562: case__562
-AsyncResetRegVec_w1_i0: AsyncResetRegVec_w1_i0
-muxpart__256: muxpart__256
-reg__430: reg__430
-logic__4429: logic__4429
-case__1650: case__1650
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__7: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__2978: logic__2978
-muxpart__220: muxpart__220
-logic__7850: logic__7850
-case__1300: case__1300
-logic__4962: logic__4962
-logic__2904: logic__2904
-datapath__391: datapath__391
-logic__8949: logic__8949
-logic__7593: logic__7593
-logic__4148: logic__4148
-logic__8152: logic__8152
-case__1196: case__1196
-case__1132: case__1132
-reg__347: reg__347
-logic__1879: logic__1879
-logic__9394: logic__9394
-logic__6047: logic__6047
-case__468: case__468
-reg__260: reg__260
-logic__1526: logic__1526
-logic__2157: logic__2157
-case__1647: case__1647
-logic__1365: logic__1365
-logic__8165: logic__8165
-logic__4741: logic__4741
-logic__6999: logic__6999
-ifft_abs_sqr: ifft_abs_sqr
-logic__4391: logic__4391
-logic__7344: logic__7344
-reg__381: reg__381
-logic__5985: logic__5985
-case__1242: case__1242
-case__997: case__997
-logic__7930: logic__7930
-logic__6944: logic__6944
-case__435: case__435
-logic__6689: logic__6689
-logic__2677: logic__2677
-logic__9294: logic__9294
-logic__235: logic__235
-datapath__264: datapath__264
-DivSqrtRawFN_small: DivSqrtRawFN_small
-reg__806: reg__806
-dsp48e2__33: dsp48e2__33
-AsyncValidSync__6: AsyncValidSync
-logic__6932: logic__6932
-logic__5251: logic__5251
-logic__770: logic__770
-case__888: case__888
-logic__9134: logic__9134
-logic__3078: logic__3078
-case__956: case__956
-case__354: case__354
-case__1195: case__1195
-logic__1368: logic__1368
-logic__1011: logic__1011
-logic__55: logic__55
-reg__1177: reg__1177
-logic__5407: logic__5407
-logic__8800: logic__8800
-reg__589: reg__589
-logic__7975: logic__7975
-reg__1206: reg__1206
-reg__638: reg__638
-logic__2624: logic__2624
-logic__7330: logic__7330
-case__1146: case__1146
-datapath__141: datapath__141
-logic__1599: logic__1599
-logic__735: logic__735
-reg__891: reg__891
-case__473: case__473
-logic__2979: logic__2979
-logic__7439: logic__7439
-reg__897: reg__897
-logic__8802: logic__8802
-datapath__485: datapath__485
-reg__1163: reg__1163
-logic__1889: logic__1889
-case__675: case__675
-logic__5075: logic__5075
-logic__8227: logic__8227
-logic__2962: logic__2962
-logic__5642: logic__5642
-logic__4176: logic__4176
-datapath__637: datapath__637
-logic__5282: logic__5282
-reg__1251: reg__1251
-datapath__83: datapath__83
-logic__3817: logic__3817
-logic__8220: logic__8220
-reg__494: reg__494
-reg__251: reg__251
-logic__2481: logic__2481
-logic__7654: logic__7654
-logic__4968: logic__4968
-case__1711: case__725
-case__15: case__15
-logic__8146: logic__8146
-logic__1868: logic__1868
-case__1671: case__1671
-datapath__18: datapath__18
-logic__6983: logic__6983
-reg__391: reg__391
-logic__9521: logic__4613
-logic__5554: logic__5554
-logic__7379: logic__7379
-reg__1237: reg__1237
-logic__8540: logic__8540
-logic__4430: logic__4430
-case__834: case__834
-logic__4038: logic__4038
-logic__2858: logic__2858
-logic__7470: logic__7470
-case__252: case__252
-logic__8944: logic__8944
-muxpart__72: muxpart__72
-AsyncResetRegVec_w2_i0: AsyncResetRegVec_w2_i0
-datapath__148: datapath__148
-logic__4395: logic__4395
-logic__6830: logic__6830
-logic__7427: logic__7427
-logic__618: logic__618
-case__1145: case__1145
-logic__9514: logic__4628
-case__784: case__784
-logic__2436: logic__2436
-case__32: case__32
-logic__3571: logic__3571
-logic__5449: logic__5449
-reg__1564: reg__153
-datapath__66: datapath__66
-reg__1106: reg__1106
-case__1044: case__1044
-reg__1119: reg__1119
-logic__2745: logic__2745
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__26: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__980: reg__980
-logic__9661: logic__925
-datapath__702: datapath__702
-logic__6764: logic__6764
-logic__1231: logic__1231
-case__303: case__303
-logic__1728: logic__1728
-reg__291: reg__291
-logic__9645: logic__1141
-logic__7369: logic__7369
-logic__2522: logic__2522
-logic__6067: logic__6067
-FPToFP: FPToFP
-logic__8950: logic__8950
-extram__6: extram__6
-logic__1528: logic__1528
-reg__1574: reg__119
-logic__9044: logic__9044
-datapath__521: datapath__521
-datapath__34: datapath__34
-logic__21: logic__21
-ITLB: ITLB
-case__618: case__618
-logic__5974: logic__5974
-case__820: case__820
-logic__9374: logic__9374
-ram__9: ram__9
-logic__1849: logic__1849
-logic__906: logic__906
-case__1422: case__1422
-reg__387: reg__387
-reg__1466: reg__907
-logic__1415: logic__1415
-case__157: case__157
-logic__7032: logic__7032
-logic__5079: logic__5079
-logic__7386: logic__7386
-logic__1617: logic__1617
-logic__3962: logic__3962
-dsp48e2__31: dsp48e2__31
-logic__4450: logic__4450
-logic__1139: logic__1139
-logic__4015: logic__4015
-datapath__206: datapath__206
-muxpart__95: muxpart__95
-reg__1516: reg__908
-datapath__339: datapath__339
-logic__4396: logic__4396
-logic__8965: logic__8965
-logic__9062: logic__9062
-logic__7624: logic__7624
-logic__8399: logic__8399
-reg__1474: reg__908
-logic__9566: logic__2481
-case__969: case__969
-logic__6863: logic__6863
-logic__9055: logic__9055
-case__573: case__573
-logic__7213: logic__7213
-case__1436: case__1436
-datapath__25: datapath__25
-case__268: case__268
-logic__5616: logic__5616
-logic__4405: logic__4405
-logic__4727: logic__4727
-case__1325: case__1325
-logic__7432: logic__7432
-case__1017: case__1017
-logic__1931: logic__1931
-logic__9493: logic__3604
-RecFNToIN_1: RecFNToIN_1
-logic__8486: logic__8486
-logic__2603: logic__2603
-reg__1358: reg__1358
-reg__1437: reg__1068
-counter__22: counter__22
-logic__8925: logic__8925
-logic__9471: logic__9471
-reg__708: reg__708
-logic__9463: logic__9463
-reg__819: reg__819
-reg__522: reg__522
-case__1486: case__1486
-logic__1560: logic__1560
-TLWidthWidget8: TLWidthWidget8
-logic__2478: logic__2478
-logic__4202: logic__4202
-logic__7277: logic__7277
-logic__5967: logic__5967
-logic__895: logic__895
-gray_to_binary__2: gray_to_binary
-logic__4840: logic__4840
-logic__750: logic__750
-logic__9631: logic__1175
-logic__5596: logic__5596
-logic__3441: logic__3441
-case__298: case__298
-case__962: case__962
-datapath__229: datapath__229
-case__385: case__385
-logic__7195: logic__7195
-logic__4634: logic__4634
-datapath__283: datapath__283
-reg__721: reg__721
-case__1286: case__1286
-logic__5551: logic__5551
-PlusArgTimeout: PlusArgTimeout
-logic__7425: logic__7425
-logic__8621: logic__8621
-datapath__525: datapath__525
-logic__2051: logic__2051
-logic__4817: logic__4817
-logic__894: logic__894
-reg__491: reg__491
-AsyncResetSynchronizerShiftReg_w1_d3_i0__6: AsyncResetSynchronizerShiftReg_w1_d3_i0
-keep__47: keep__8
-reg__226: reg__226
-case__1395: case__1395
-datapath__97: datapath__97
-datapath__324: datapath__324
-datapath__497: datapath__497
-cordic_atan_one_stage__parameterized0: cordic_atan_one_stage__parameterized0
-logic__4546: logic__4546
-sync__4: sync
-logic__1492: logic__1492
-reg__1489: reg__908
-logic__9440: logic__9440
-logic__5413: logic__5413
-logic__207: logic__207
-datapath__698: datapath__698
-logic__7605: logic__7605
-logic__6779: logic__6779
-logic__5765: logic__5765
-logic__3743: logic__3743
-logic__2869: logic__2869
-reg__984: reg__984
-reg__838: reg__838
-logic__3902: logic__3902
-case__1218: case__1218
-logic__2211: logic__2211
-case__1514: case__1514
-mult_46_15_61__2: mult_46_15_61
-logic__4489: logic__4489
-TLInterconnectCoupler_cbus_to_plic: TLInterconnectCoupler_cbus_to_plic
-logic__7363: logic__7363
-logic__7060: logic__7060
-counter__28: counter__28
-datapath__715: datapath__715
-logic__2244: logic__2244
-datapath__442: datapath__442
-counter__14: counter__14
-reg__1552: reg__856
-logic__8736: logic__8736
-logic__5953: logic__5953
-logic__1050: logic__1050
-logic__6200: logic__6200
-logic__9056: logic__9056
-reg__842: reg__842
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__14: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__1555: reg__856
-reg__1130: reg__1130
-case__504: case__504
-case__883: case__883
-logic__7382: logic__7382
-logic__2020: logic__2020
-logic__4206: logic__4206
-logic__881: logic__881
-logic__5881: logic__5881
-case__727: case__727
-reg__61: reg__61
-muxpart__1: muxpart__1
-datapath__520: datapath__520
-FPUDecoder: FPUDecoder
-logic__7374: logic__7374
-reg__165: reg__165
-logic__4406: logic__4406
-logic__815: logic__815
-reg__650: reg__650
-case__1279: case__1279
-logic__7128: logic__7128
-reg__1461: reg__906
-logic__9623: logic__6774
-PLICClockSinkDomain: PLICClockSinkDomain
-logic__1732: logic__1732
-logic__4597: logic__4597
-logic__5292: logic__5292
-datapath__102: datapath__102
-logic__868: logic__868
-logic__278: logic__278
-case__972: case__972
-logic__7539: logic__7539
-case__251: case__251
-datapath__717: datapath__717
-reg__1142: reg__1142
-logic__7237: logic__7237
-case__1740: case__298
-case__768: case__768
-reg__383: reg__383
-TLDebugModuleInnerAsync: TLDebugModuleInnerAsync
-reg__45: reg__45
-case__215: case__215
-case__320: case__320
-reg__746: reg__746
-reg__620: reg__620
-logic__7368: logic__7368
-sample_counter: sample_counter
-case__1069: case__1069
-logic__1259: logic__1259
-reg__865: reg__865
-case__891: case__891
-logic__3201: logic__3201
-case__861: case__861
-logic__8910: logic__8910
-case__1063: case__1063
-case__1026: case__1026
-datapath__491: datapath__491
-logic__8286: logic__8286
-logic__2262: logic__2262
-reg__446: reg__446
-logic__760: logic__760
-case__1181: case__1181
-logic__3095: logic__3095
-logic__9502: logic__3572
-reg__46: reg__46
-datapath__124: datapath__124
-reg__1332: reg__1332
-logic__3559: logic__3559
-logic__3819: logic__3819
-reg__999: reg__999
-reg__1216: reg__1216
-reg__576: reg__576
-logic__7229: logic__7229
-case__671: case__671
-logic__1744: logic__1744
-datapath__439: datapath__439
-datapath__26: datapath__26
-logic__140: logic__140
-logic__1274: logic__1274
-logic__7371: logic__7371
-LevelGateway: LevelGateway
-reg__429: reg__429
-datapath__1: datapath__1
-logic__1504: logic__1504
-reg__366: reg__366
-logic__5939: logic__5939
-logic__4734: logic__4734
-reg__707: reg__707
-case__129: case__129
-logic__6760: logic__6760
-logic__8019: logic__8019
-case__926: case__926
-case__781: case__781
-case__1639: case__1639
-reg__668: reg__668
-logic__3839: logic__3839
-logic__3779: logic__3779
-logic__7968: logic__7968
-logic__3901: logic__3901
-logic__3014: logic__3014
-reg__476: reg__476
-case__1554: case__1554
-logic__1191: logic__1191
-case__725: case__725
-case__1160: case__1160
-addsub__2: addsub__2
-logic__5044: logic__5044
-logic__125: logic__125
-logic__7587: logic__7587
-logic__1700: logic__1700
-logic__9260: logic__9260
-reg__1419: reg__1327
-datapath__374: datapath__374
-logic__2396: logic__2396
-case__1128: case__1128
-logic__4261: logic__4261
-reg__947: reg__947
-case__560: case__560
-reg__404: reg__404
-logic__6798: logic__6798
-case__924: case__924
-logic__9305: logic__9305
-AsyncResetSynchronizerShiftReg_w1_d3_i0__3: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__7203: logic__7203
-logic__4601: logic__4601
-logic__1301: logic__1301
-reg__909: reg__909
-reg__1354: reg__1354
-reg__631: reg__631
-datapath__405: datapath__405
-logic__725: logic__725
-logic__4078: logic__4078
-case__801: case__801
-logic__6842: logic__6842
-reg__681: reg__681
-reg__140: reg__140
-case__6: case__6
-reg__1146: reg__1146
-logic__3036: logic__3036
-LevelGateway__3: LevelGateway
-reg__1380: reg__1380
-logic__9621: logic__6774
-logic__9183: logic__9183
-reg__178: reg__178
-logic__7150: logic__7150
-case__1297: case__1297
-datapath__117: datapath__117
-case__698: case__698
-logic__7499: logic__7499
-datapath__209: datapath__209
-datapath__595: datapath__595
-reg__1527: reg__906
-logic__4796: logic__4796
-logic__74: logic__74
-logic__938: logic__938
-logic__854: logic__854
-logic__8364: logic__8364
-case__1726: case__1591
-reg__1215: reg__1215
-reg__574: reg__574
-logic__6177: logic__6177
-reg__957: reg__957
-datapath__769: datapath__121
-reg__964: reg__964
-logic__7388: logic__7388
-logic__1621: logic__1621
-reg__761: reg__761
-case__1560: case__1560
-case__1060: case__1060
-logic__9316: logic__9316
-IBuf: IBuf
-logic__5080: logic__5080
-reg__1229: reg__1229
-datapath__640: datapath__640
-logic__7562: logic__7562
-logic__6753: logic__6753
-muxpart__217: muxpart__217
-datapath__171: datapath__171
-logic__5038: logic__5038
-case__43: case__43
-logic__680: logic__680
-logic__6948: logic__6948
-logic__1347: logic__1347
-case__1370: case__1370
-datapath__160: datapath__160
-datapath__134: datapath__134
-logic__6864: logic__6864
-case__1252: case__1252
-case__785: case__785
-logic__6977: logic__6977
-logic__6803: logic__6803
-muxpart__21: muxpart__21
-reg__267: reg__267
-reg__1031: reg__1031
-logic__6566: logic__6566
-TLAtomicAutomata_pbus: TLAtomicAutomata_pbus
-logic__2738: logic__2738
-case__981: case__981
-case__614: case__614
-case__957: case__957
-logic__4296: logic__4296
-MulDiv: MulDiv
-logic__470: logic__470
-reg__286: reg__286
-case__823: case__823
-logic__8411: logic__8411
-case__180: case__180
-reg__53: reg__53
-datapath__16: datapath__16
-reg__783: reg__783
-logic__5112: logic__5112
-TLInterconnectCoupler_cbus_to_debug: TLInterconnectCoupler_cbus_to_debug
-reg__795: reg__795
-logic__1225: logic__1225
-logic__4262: logic__4262
-case__724: case__724
-logic__3870: logic__3870
-logic__7515: logic__7515
-logic__7152: logic__7152
-datapath__201: datapath__201
-logic__5608: logic__5608
-extram__3: extram__3
-reg__18: reg__18
-datapath__528: datapath__528
-logic__2757: logic__2757
-reg__1568: reg__149
-reg__409: reg__409
-reg__330: reg__330
-logic__1321: logic__1321
-logic__9058: logic__9058
-case__177: case__177
-AsyncValidSync__21: AsyncValidSync
-logic__2774: logic__2774
-reg__517: reg__517
-logic__3599: logic__3599
-logic__7116: logic__7116
-datapath__600: datapath__600
-datapath__776: datapath__40
-logic__1131: logic__1131
-datapath__513: datapath__513
-logic__4960: logic__4960
-datapath__334: datapath__334
-logic__2454: logic__2454
-logic__4066: logic__4066
-muxpart__55: muxpart__55
-reg__307: reg__307
-datapath__543: datapath__543
-logic__7301: logic__7301
-logic__5622: logic__5622
-logic__1893: logic__1893
-reg__195: reg__195
-logic__3297: logic__3297
-reg__569: reg__569
-datapath__531: datapath__531
-muxpart__215: muxpart__215
-FrontBus: FrontBus
-datapath__749: datapath__137
-logic__7820: logic__7820
-muxpart__248: muxpart__248
-logic__4425: logic__4425
-case__1584: case__1584
-datapath__644: datapath__644
-case__598: case__598
-case__681: case__681
-datapath__670: datapath__670
-logic__6697: logic__6697
-logic__6921: logic__6921
-reg__239: reg__239
-reg__427: reg__427
-logic__4330: logic__4330
-logic__7186: logic__7186
-logic__5999: logic__5999
-case__1626: case__1626
-case__741: case__741
-logic__7414: logic__7414
-case__1062: case__1062
-reg__331: reg__331
-logic__6319: logic__6319
-datapath__549: datapath__549
-logic__8614: logic__8614
-reg__533: reg__533
-logic__3238: logic__3238
-reg__1569: reg__148
-logic__7760: logic__7760
-case__599: case__599
-logic__6696: logic__6696
-logic__8886: logic__8886
-reg__99: reg__99
-muxpart__238: muxpart__238
-logic__6085: logic__6085
-logic__2005: logic__2005
-case__1562: case__1562
-logic__2993: logic__2993
-logic__9388: logic__9388
-case__803: case__803
-logic__6970: logic__6970
-case__405: case__405
-logic__7600: logic__7600
-logic__1737: logic__1737
-logic__9534: logic__4593
-case__1714: case__722
-muxpart__154: muxpart__154
-case__559: case__559
-logic__3959: logic__3959
-reg__1129: reg__1129
-logic__2216: logic__2216
-case__1680: case__1680
-muxpart__269: muxpart__269
-muxpart__62: muxpart__62
-datapath__143: datapath__143
-case__1322: case__1322
-reg__166: reg__166
-logic__5624: logic__5624
-logic__9392: logic__9392
-reg__1541: reg__907
-muxpart__88: muxpart__88
-muxpart__50: muxpart__50
-logic__6931: logic__6931
-case__1541: case__1541
-case__1566: case__1566
-logic__1419: logic__1419
-logic__6199: logic__6199
-reg__700: reg__700
-logic__7674: logic__7674
-case__1049: case__1049
-logic__2404: logic__2404
-case__1289: case__1289
-muxpart__257: muxpart__257
-logic__9310: logic__9310
-extrom__2: extrom__1
-Queue2_TLBundleD_a32d64s1k1z4u: Queue2_TLBundleD_a32d64s1k1z4u
-logic__3003: logic__3003
-reg__1004: reg__1004
-logic__1839: logic__1839
-case__1390: case__1390
-logic__7564: logic__7564
-logic__1583: logic__1583
-logic__3600: logic__3600
-case__643: case__643
-logic__1426: logic__1426
-datapath__468: datapath__468
-reg__1544: reg__907
-logic__9014: logic__9014
-datapath__156: datapath__156
-logic__5117: logic__5117
-reg__1315: reg__1315
-logic__7095: logic__7095
-case__1193: case__1193
-logic__7925: logic__7925
-case__172: case__172
-case__617: case__617
-reg__87: reg__87
-reg__246: reg__246
-case__1040: case__1040
-reg__603: reg__603
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__17: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__718: datapath__718
-logic__891: logic__891
-logic__7533: logic__7533
-logic__1164: logic__1164
-TLWidthWidget8_1: TLWidthWidget8_1
-reg__285: reg__285
-logic__8616: logic__8616
-logic__5600: logic__5600
-logic__5305: logic__5305
-reg__93: reg__93
-case__1127: case__1127
-logic__624: logic__624
-datapath__398: datapath__398
-logic__295: logic__295
-logic__7306: logic__7306
-logic__2006: logic__2006
-reg__410: reg__410
-logic__182: logic__182
-reg__134: reg__134
-muxpart__304: muxpart__304
-logic__3048: logic__3048
-logic__7410: logic__7410
-reg__1551: reg__856
-reg__1226: reg__1226
-logic__2701: logic__2701
-logic__2838: logic__2838
-logic__4887: logic__4887
-muxpart__101: muxpart__101
-case__41: case__41
-case__444: case__444
-case__870: case__870
-case__683: case__683
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__25: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__662: case__662
-datapath__300: datapath__300
-datapath__20: datapath__20
-case__1162: case__1162
-logic__5610: logic__5610
-logic__6469: logic__6469
-datapath__683: datapath__683
-logic__5043: logic__5043
-case__1675: case__1675
-case__322: case__322
-logic__3790: logic__3790
-datapath__503: datapath__503
-case__1334: case__1334
-reg__220: reg__220
-case__343: case__343
-Queue1_TLBundleA_a29d32s7k1z2u: Queue1_TLBundleA_a29d32s7k1z2u
-case__122: case__122
-case__403: case__403
-logic__2965: logic__2965
-logic__4426: logic__4426
-reg__436: reg__436
-case__690: case__690
-logic__4026: logic__4026
-logic__7378: logic__7378
-logic__3447: logic__3447
-logic__5649: logic__5649
-case__973: case__973
-case__321: case__321
-logic__8588: logic__8588
-reg__309: reg__309
-logic__942: logic__942
-case__829: case__829
-case__841: case__841
-logic__4777: logic__4777
-datapath__626: datapath__626
-logic__6538: logic__6538
-logic__514: logic__514
-logic__4514: logic__4514
-reg__1487: reg__907
-case__710: case__710
-logic__6174: logic__6174
-logic__4108: logic__4108
-case__1248: case__1248
-logic__7497: logic__7497
-logic__9177: logic__9177
-reg__863: reg__863
-logic__4384: logic__4384
-logic__4068: logic__4068
-datapath__347: datapath__347
-case__1389: case__1389
-reg__1230: reg__1230
-logic__6741: logic__6741
-datapath__489: datapath__489
-case__719: case__719
-case__827: case__827
-logic__3054: logic__3054
-logic__3515: logic__3515
-logic__9261: logic__9261
-TLBuffer_a32d64s1k1z4u: TLBuffer_a32d64s1k1z4u
-MulAddRecFNPipe_l2_e8_s24: MulAddRecFNPipe_l2_e8_s24
-case__478: case__478
-datapath__464: datapath__464
-logic__5033: logic__5033
-logic__762: logic__762
-logic__5648: logic__5648
-datapath__546: datapath__546
-logic__7710: logic__7710
-case__462: case__462
-datapath__157: datapath__157
-case__628: case__628
-logic__4596: logic__4596
-logic__7394: logic__7394
-datapath__690: datapath__690
-case__166: case__166
-reg__539: reg__539
-logic__5990: logic__5990
-logic__4724: logic__4724
-logic__4900: logic__4900
-logic__3140: logic__3140
-datapath__167: datapath__167
-logic__6533: logic__6533
-logic__1747: logic__1747
-logic__2191: logic__2191
-case__1224: case__1224
-logic__2021: logic__2021
-logic__5935: logic__5935
-logic__7498: logic__7498
-muxpart__47: muxpart__47
-muxpart__4: muxpart__4
-reg__968: reg__968
-case__1507: case__1507
-RocketTile__GCB0: RocketTile__GCB0
-logic__6841: logic__6841
-Arbiter4_DCacheDataReq: Arbiter4_DCacheDataReq
-reg__1503: reg__906
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__30: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__792: case__792
-logic__5933: logic__5933
-dual_port_bram__parameterized0: dual_port_bram__parameterized0
-reg__1217: reg__1217
-logic__2727: logic__2727
-datapath__502: datapath__502
-logic__1556: logic__1556
-logic__1180: logic__1180
-logic__9491: logic__3606
-AsyncValidSync__2: AsyncValidSync
-logic__1302: logic__1302
-logic__5518: logic__5518
-rocket_bscan_dmi_tunnel: rocket_bscan_dmi_tunnel
-logic__8780: logic__8780
-logic__8620: logic__8620
-datapath__487: datapath__487
-logic__4832: logic__4832
-reg__752: reg__752
-logic__9589: logic__8994
-reg__355: reg__355
-reg__1178: reg__1178
-reg__591: reg__591
-case__694: case__694
-case__1688: case__1688
-logic__5751: logic__5751
-reg__1076: reg__1076
-case__939: case__939
-logic__6812: logic__6812
-reg__1556: reg__856
-keep__37: keep__12
-datapath__477: datapath__477
-logic__5932: logic__5932
-logic__1981: logic__1981
-case__1426: case__1426
-logic__9211: logic__9211
-reg__520: reg__520
-logic__432: logic__432
-datapath__359: datapath__359
-case__438: case__438
-logic__6547: logic__6547
-case__980: case__980
-logic__2937: logic__2937
-case__464: case__464
-logic__8119: logic__8119
-logic__5393: logic__5393
-logic__5611: logic__5611
-logic__8017: logic__8017
-logic__8829: logic__8829
-datapath__632: datapath__632
-logic__6124: logic__6124
-logic__9629: logic__1600
-mult_46_15_61__1: mult_46_15_61
-logic__5221: logic__5221
-case__1720: case__1597
-logic__3027: logic__3027
-datapath__581: datapath__581
-logic__4175: logic__4175
-logic__5288: logic__5288
-case__905: case__905
-case__1081: case__1081
-case__1283: case__1283
-datapath__379: datapath__379
-keep__15: keep__15
-reg__1014: reg__1014
-case__1672: case__1672
-datapath__678: datapath__678
-logic__3463: logic__3463
-reg__886: reg__886
-reg__271: reg__271
-case__1522: case__1522
-logic__2097: logic__2097
-double_ff_syn__2: double_ff_syn
-datapath__257: datapath__257
-logic__5615: logic__5615
-case__515: case__515
-reg__989: reg__989
-logic__4737: logic__4737
-logic__7807: logic__7807
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__22: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__1053: reg__1053
-logic__7362: logic__7362
-reg__929: reg__929
-TLFIFOFixer: TLFIFOFixer
-case__1033: case__1033
-logic__1751: logic__1751
-logic__5871: logic__5871
-logic__152: logic__152
-logic__2809: logic__2809
-case__911: case__911
-reg__900: reg__900
-case__1689: case__1689
-muxpart__253: muxpart__253
-case__49: case__49
-logic__7373: logic__7373
-logic__1611: logic__1611
-logic__4967: logic__4967
-case__393: case__393
-dsp48e2__7: dsp48e2__7
-muxpart__214: muxpart__214
-datapath__624: datapath__624
-logic__2202: logic__2202
-logic__145: logic__145
-logic__6887: logic__6887
-logic__4189: logic__4189
-logic__4435: logic__4435
-logic__5722: logic__5722
-reg__943: reg__943
-reg__1249: reg__1249
-logic__3552: logic__3552
-logic__6736: logic__6736
-datapath__556: datapath__556
-logic__7440: logic__7440
-logic__6793: logic__6793
-logic__8921: logic__8921
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__23: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__295: case__295
-case__250: case__250
-datapath__365: datapath__365
-logic__7692: logic__7692
-logic__867: logic__867
-logic__4828: logic__4828
-case__596: case__596
-datapath__436: datapath__436
-reg__1161: reg__1161
-muxpart__194: muxpart__194
-datapath__740: datapath__45
-ram_2x77__4: ram_2x77
-datapath__671: datapath__671
-datapath__182: datapath__182
-logic__1085: logic__1085
-logic__5277: logic__5277
-logic__5998: logic__5998
-datapath__394: datapath__394
-case__894: case__894
-logic__8625: logic__8625
-reg__234: reg__234
-logic__4804: logic__4804
-reg__445: reg__445
-logic__1310: logic__1310
-logic__495: logic__495
-logic__1613: logic__1613
-reg__1563: reg__154
-logic__9428: logic__9428
-code_loop_discriminator: code_loop_discriminator
-logic__2773: logic__2773
-case__383: case__383
-keep__11: keep__11
-ram_2x115: ram_2x115
-case__1364: case__1364
-logic__2637: logic__2637
-logic__1357: logic__1357
-reg__1133: reg__1133
-TLBuffer_a32d64s2k1z4u: TLBuffer_a32d64s2k1z4u
-logic__9347: logic__9347
-case__1498: case__1498
-datapath__512: datapath__512
-logic__1272: logic__1272
-reg__1435: reg__1216
-logic__4820: logic__4820
-logic__5522: logic__5522
-reg__1339: reg__1339
-logic__4813: logic__4813
-AsyncValidSync__17: AsyncValidSync
-logic__5432: logic__5432
-logic__1949: logic__1949
-logic__3539: logic__3539
-logic__4434: logic__4434
-logic__1054: logic__1054
-logic__2078: logic__2078
-logic__7655: logic__7655
-AsyncQueueSink_TLBundleD_a9d32s1k1z2u: AsyncQueueSink_TLBundleD_a9d32s1k1z2u
-reg__213: reg__213
-datapath__98: datapath__98
-reg__1098: reg__1098
-datapath__43: datapath__43
-muxpart__246: muxpart__246
-logic__8002: logic__8002
-datapath__704: datapath__704
-logic__9539: logic__4544
-logic__5035: logic__5035
-logic__521: logic__521
-counter__7: counter__7
-logic__7513: logic__7513
-reg__924: reg__924
-case__375: case__375
-afe_top: afe_top
-logic__8793: logic__8793
-reg__1239: reg__1239
-reg__76: reg__76
-logic__1521: logic__1521
-reg__492: reg__492
-reg__1455: reg__906
-case__170: case__170
-muxpart__273: muxpart__273
-case__603: case__603
-logic__811: logic__811
-reg__734: reg__734
-logic__485: logic__485
-reg__925: reg__925
-logic__6598: logic__6598
-datapath__250: datapath__250
-case__344: case__344
-logic__3279: logic__3279
-logic__7771: logic__7771
-dsp48e2__6: dsp48e2__6
-reg__1352: reg__1352
-muxpart__235: muxpart__235
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__4: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-reg__726: reg__726
-logic__910: logic__910
-case__231: case__231
-reg__717: reg__717
-datapath__770: datapath__46
-logic__3546: logic__3546
-logic__1582: logic__1582
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__22: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__258: case__258
-case__1420: case__1420
-reg__585: reg__585
-case__887: case__887
-logic__7358: logic__7358
-logic__66: logic__66
-logic__5253: logic__5253
-reg__485: reg__485
-datapath__390: datapath__390
-logic__4424: logic__4424
-logic__3867: logic__3867
-logic__3562: logic__3562
-reg__333: reg__333
-logic__3423: logic__3423
-case__1336: case__1336
-logic__7273: logic__7273
-logic__3603: logic__3603
-case__181: case__181
-logic__6663: logic__6663
-reg__1017: reg__1017
-case__1392: case__1392
-logic__5067: logic__5067
-logic__3494: logic__3494
-logic__1246: logic__1246
-logic__5195: logic__5195
-case__697: case__697
-muxpart__278: muxpart__278
-logic__9487: logic__3617
-datapath__495: datapath__495
-logic__3226: logic__3226
-muxpart__85: muxpart__85
-datapath__234: datapath__234
-case__1152: case__1152
-logic__2135: logic__2135
-logic__4454: logic__4454
-datapath__344: datapath__344
-logic__2646: logic__2646
-case__604: case__604
-TLFragmenter_FPGAUART: TLFragmenter_FPGAUART
-logic__5668: logic__5668
-case__293: case__293
-reg__507: reg__507
-logic__9499: logic__3598
-ram_2x120: ram_2x120
-case__259: case__259
-reg__346: reg__346
-reg__1463: reg__907
-case__1473: case__1473
-logic__422: logic__422
-logic__3611: logic__3611
-reg__523: reg__523
-muxpart__250: muxpart__250
-logic__6915: logic__6915
-logic__3741: logic__3741
-logic__6747: logic__6747
-logic__7912: logic__7912
-case__1165: case__1165
-logic__7286: logic__7286
-reg__730: reg__730
-datapath__269: datapath__269
-case__126: case__126
-datapath__601: datapath__601
-logic__2369: logic__2369
-logic__6338: logic__6338
-logic__9527: logic__4600
-reg__1156: reg__1156
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__31: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-keep__50: keep__9
-logic__9306: logic__9306
-reg__94: reg__94
-logic__3558: logic__3558
-reg__1254: reg__1254
-reg__1272: reg__1272
-logic__6729: logic__6729
-reg__192: reg__192
-reg__729: reg__729
-case__875: case__875
-case__968: case__968
-logic__3975: logic__3975
-logic__6122: logic__6122
-case__20: case__20
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__15: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-datapath__411: datapath__411
-logic__6606: logic__6606
-Queue2_TLBundleA_a32d64s2k1z3u: Queue2_TLBundleA_a32d64s2k1z3u
-logic__4824: logic__4824
-case__757: case__757
-reg__299: reg__299
-logic__6619: logic__6619
-logic__2724: logic__2724
-logic__5867: logic__5867
-case__365: case__365
-logic__2107: logic__2107
-logic__5329: logic__5329
-logic__4496: logic__4496
-logic__8605: logic__8605
-logic__7393: logic__7393
-case__1735: case__303
-PTW: PTW
-datapath__565: datapath__565
-case__716: case__716
-datapath__448: datapath__448
-logic__7856: logic__7856
-reg__139: reg__139
-reg__489: reg__489
-reg__599: reg__599
-logic__7236: logic__7236
-case__1733: case__305
-logic__2821: logic__2821
-datapath__386: datapath__386
-reg__1213: reg__1213
-logic__2344: logic__2344
-logic__2061: logic__2061
-reg__1301: reg__1301
-muxpart__11: muxpart__11
-case__1099: case__1099
-case__1012: case__1012
-logic__1973: logic__1973
-extram__7: extram__7
-reg__588: reg__588
-logic__2115: logic__2115
-logic__4606: logic__4606
-datapath__351: datapath__351
-logic__4032: logic__4032
-logic__7384: logic__7384
-muxpart__33: muxpart__33
-case__621: case__621
-muxpart__177: muxpart__177
-AsyncQueueSource_TLBundleA_a9d32s1k1z2u: AsyncQueueSource_TLBundleA_a9d32s1k1z2u
-datapath__86: datapath__86
-reg__1403: reg__1403
-logic__3284: logic__3284
-muxpart__48: muxpart__48
-counter__18: counter__18
-logic__3760: logic__3760
-counter__8: counter__8
-logic__1165: logic__1165
-logic__5104: logic__5104
-logic__7202: logic__7202
-case__1565: case__1565
-reg__444: reg__444
-logic__9570: logic__2475
-logic__7496: logic__7496
-logic__5750: logic__5750
-logic__6874: logic__6874
-APBGpsBlock__GC0: APBGpsBlock__GC0
-logic__5743: logic__5743
-logic__1608: logic__1608
-datapath__145: datapath__145
-logic__6828: logic__6828
-logic__5559: logic__5559
-logic__5929: logic__5929
-case__774: case__774
-datapath__395: datapath__395
-muxpart__219: muxpart__219
-datapath__473: datapath__473
-logic__209: logic__209
-muxpart__96: muxpart__96
-reg__635: reg__635
-logic__2048: logic__2048
-logic__7697: logic__7697
-case__8: case__8
-logic__3884: logic__3884
-reg: reg
-case__665: case__665
-logic__9366: logic__9366
-logic__4063: logic__4063
-logic__13: logic__13
-logic__3133: logic__3133
-reg__273: reg__273
-logic__4998: logic__4998
-reg__754: reg__754
-case__445: case__445
-logic__3331: logic__3331
-reg__5: reg__5
-reg__921: reg__921
-case__253: case__253
-logic__7140: logic__7140
-IntSyncCrossingSource_n1x1: IntSyncCrossingSource_n1x1
-reg__1212: reg__1212
-DivSqrtRecFN_small: DivSqrtRecFN_small
-logic__4383: logic__4383
-logic__9640: logic__1156
-case__1594: case__1594
-reg__1039: reg__1039
-butterfly__parameterized1: butterfly__parameterized1
-logic__6081: logic__6081
-logic__5949: logic__5949
-case__380: case__380
-logic__1669: logic__1669
-reg__710: reg__710
-PMAChecker: PMAChecker
-logic__9450: logic__9450
-logic__1141: logic__1141
-reg__395: reg__395
-case__1655: case__1655
-reg__693: reg__693
-case__1605: case__1605
-logic__4598: logic__4598
-reg__550: reg__550
-logic__7356: logic__7356
-logic__877: logic__877
-LF_code: LF_code
-case__1240: case__1240
-logic__9234: logic__9234
-logic__8722: logic__8722
-sync__3: sync
-case__512: case__512
-keep__16: keep__16
-reg__598: reg__598
-case__958: case__958
-logic__1925: logic__1925
-ram__15: ram__1
-logic__7121: logic__7121
-logic__8176: logic__8176
-logic__7390: logic__7390
-reg__340: reg__340
-logic__3994: logic__3994
-case__1034: case__1034
-reg__435: reg__435
-logic__2811: logic__2811
-reg__78: reg__78
-reg__95: reg__95
-logic__7131: logic__7131
-logic__7208: logic__7208
-reg__801: reg__801
-logic__8184: logic__8184
-logic__7129: logic__7129
-datapath__479: datapath__479
-logic__5353: logic__5353
-case__358: case__358
-reg__423: reg__423
-reg__851: reg__851
-case__145: case__145
-reg__338: reg__338
-logic__7118: logic__7118
-logic__4079: logic__4079
-logic__3745: logic__3745
-datapath__564: datapath__564
-logic__3536: logic__3536
-reg__161: reg__161
-reg__1421: reg__1325
-reg__581: reg__581
-logic__6833: logic__6833
-logic__4895: logic__4895
-datapath__726: datapath__726
-logic__6657: logic__6657
-logic__3105: logic__3105
-case__73: case__73
-case__1202: case__1202
-case__237: case__237
-logic__3039: logic__3039
-case__1208: case__1208
-logic__1948: logic__1948
-logic__5942: logic__5942
-logic__3332: logic__3332
-logic__7381: logic__7381
-reg__35: reg__35
-logic__1260: logic__1260
-logic__8850: logic__8850
-logic__7295: logic__7295
-reg__403: reg__403
-logic__7342: logic__7342
-TLInterconnectCoupler_sbus_to_bus_named_cbus: TLInterconnectCoupler_sbus_to_bus_named_cbus
-logic__290: logic__290
-reg__36: reg__36
-datapath__74: datapath__74
-PMAChecker__1: PMAChecker
-logic__4230: logic__4230
-logic__7265: logic__7265
-logic__1019: logic__1019
-logic__9581: logic__1302
-logic__5955: logic__5955
-logic__3285: logic__3285
-case__160: case__160
-reg__1525: reg__908
-logic__9552: logic__2519
-logic__17: logic__17
-logic__3168: logic__3168
-reg__373: reg__373
-logic__2226: logic__2226
-logic__8346: logic__8346
-case__360: case__360
-dsp48e2: dsp48e2
-reg__97: reg__97
-logic__2457: logic__2457
-datapath__712: datapath__712
-logic__370: logic__370
-reg__908: reg__908
-logic__6147: logic__6147
-logic__6673: logic__6673
-datapath__437: datapath__437
-logic__344: logic__344
-Queue2_TLBundleA_a14d64s2k1z4u: Queue2_TLBundleA_a14d64s2k1z4u
-logic__4688: logic__4688
-reg__278: reg__278
-case__1694: case__662
-logic__4891: logic__4891
-case__1143: case__1143
-reg__979: reg__979
-reg__223: reg__223
-logic__5089: logic__5089
-logic__3781: logic__3781
-logic__658: logic__658
-logic__2829: logic__2829
-reg__1281: reg__1281
-case__136: case__136
-case__760: case__760
-logic__8506: logic__8506
-case__390: case__390
-logic__632: logic__632
-case__36: case__36
-logic__8774: logic__8774
-reg__1363: reg__1363
-logic__4370: logic__4370
-reg__79: reg__79
-case__668: case__668
-dual_port_bram: dual_port_bram
-logic__4516: logic__4516
-logic__5923: logic__5923
-logic__6197: logic__6197
-logic__914: logic__914
-reg__1205: reg__1205
-reg__769: reg__769
-logic__8143: logic__8143
-logic__7709: logic__7709
-logic__1861: logic__1861
-reg__1348: reg__1348
-logic__4423: logic__4423
-case__1013: case__1013
-muxpart__359: muxpart__359
-datapath__319: datapath__319
-logic__4006: logic__4006
-datapath__15: datapath__15
-logic__4274: logic__4274
-reg__1094: reg__1094
-case__733: case__733
-case__1319: case__1319
-datapath__153: datapath__153
-datapath__563: datapath__563
-case__213: case__213
-logic__3506: logic__3506
-logic__1460: logic__1460
-case__285: case__285
-reg__9: reg__9
-logic__920: logic__920
-reg__1233: reg__1233
-logic__3019: logic__3019
-case__351: case__351
-reg__337: reg__337
-logic__1533: logic__1533
-keep__20: keep__14
-reg__935: reg__935
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__23: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-AsyncResetSynchronizerShiftReg_w1_d3_i0: AsyncResetSynchronizerShiftReg_w1_d3_i0
-case__367: case__367
-datapath__577: datapath__577
-logic__4681: logic__4681
-case__653: case__653
-logic__1675: logic__1675
-reg__755: reg__755
-logic__678: logic__678
-datapath__447: datapath__447
-datapath__423: datapath__423
-datapath__262: datapath__262
-reg__194: reg__194
-logic__5394: logic__5394
-logic__3907: logic__3907
-reg__191: reg__191
-reg__1214: reg__1214
-reg__531: reg__531
-logic__1524: logic__1524
-datapath__680: datapath__680
-case__699: case__699
-case__966: case__966
-logic__132: logic__132
-logic__4297: logic__4297
-logic__2810: logic__2810
-logic__8139: logic__8139
-datapath__656: datapath__656
-case__606: case__606
-logic__1023: logic__1023
-double_ff_syn__parameterized0: double_ff_syn__parameterized0
-logic__5059: logic__5059
-logic__1398: logic__1398
-reg__1250: reg__1250
-RocketALU: RocketALU
-reg__390: reg__390
-case__127: case__127
-reg__1127: reg__1127
-datapath__608: datapath__608
-reg__516: reg__516
-case__907: case__907
-logic__4624: logic__4624
-case__878: case__878
-logic__5669: logic__5669
-logic__8687: logic__8687
-logic__4179: logic__4179
-logic__8889: logic__8889
-logic__8429: logic__8429
-logic__1701: logic__1701
-case__1480: case__1480
-keep__41: keep__14
-logic__8197: logic__8197
-logic__4694: logic__4694
-logic__2175: logic__2175
-ClockCrossingReg_w55: ClockCrossingReg_w55
-logic__1287: logic__1287
-reg__8: reg__8
-case__176: case__176
-AsyncResetSynchronizerShiftReg_w1_d3_i0__5: AsyncResetSynchronizerShiftReg_w1_d3_i0
-logic__3169: logic__3169
-case__1296: case__1296
-counter__27: counter__27
-logic__5293: logic__5293
-datapath__140: datapath__140
-datapath__606: datapath__606
-reg__125: reg__125
-logic__2264: logic__2264
-logic__809: logic__809
-logic__9568: logic__2477
-logic__8128: logic__8128
-logic__7018: logic__7018
-reg__1362: reg__1362
-datapath__734: datapath__390
-logic__409: logic__409
-reg__1496: reg__907
-case__24: case__24
-Queue2_TLBundleD_a32d8s1k1z4u: Queue2_TLBundleD_a32d8s1k1z4u
-reg__201: reg__201
-logic__5098: logic__5098
-case__817: case__817
-logic__2551: logic__2551
-muxpart__9: muxpart__9
-logic__2793: logic__2793
-case__388: case__388
-counter__32: counter__32
-muxpart__195: muxpart__195
-case__302: case__302
-logic__729: logic__729
-logic__1818: logic__1818
-case__1484: case__1484
-case__951: case__951
-logic__4522: logic__4522
-case__271: case__271
-case__1515: case__1515
-logic__6006: logic__6006
-case__762: case__762
-reg__421: reg__421
-reg__240: reg__240
-logic__1219: logic__1219
-logic__6675: logic__6675
-logic__4942: logic__4942
-case__404: case__404
-case__1330: case__1330
-logic__4799: logic__4799
-logic__442: logic__442
-logic__5011: logic__5011
-logic__4723: logic__4723
-AsyncValidSync__3: AsyncValidSync
-logic__5220: logic__5220
-reg__1313: reg__1313
-logic__7505: logic__7505
-logic__1346: logic__1346
-muxpart__270: muxpart__270
-reg__945: reg__945
-addsub: addsub
-reg__663: reg__663
-case__26: case__26
-logic__1307: logic__1307
-reg__1231: reg__1231
-logic__3877: logic__3877
-reg__114: reg__114
-reg__1343: reg__1343
-logic__4498: logic__4498
-logic__9617: logic__6774
-case__1585: case__1585
-logic__5490: logic__5490
-logic__7919: logic__7919
-logic__1215: logic__1215
-datapath__309: datapath__309
-logic__253: logic__253
-logic__6597: logic__6597
-logic__9276: logic__9276
-datapath__311: datapath__311
-reg__864: reg__864
-logic__5326: logic__5326
-logic__3812: logic__3812
-muxpart__14: muxpart__14
-datapath__567: datapath__567
-case__705: case__705
-reg__1: reg__1
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-reg__1536: reg__906
-logic__956: logic__956
-datapath__615: datapath__615
-logic__3002: logic__3002
-reg__759: reg__759
-reg__461: reg__461
-muxpart__32: muxpart__32
-datapath__174: datapath__174
-logic__4350: logic__4350
-logic__901: logic__901
-logic__1429: logic__1429
-logic__3038: logic__3038
-logic__6807: logic__6807
-logic__8788: logic__8788
-logic__5887: logic__5887
-reg__1329: reg__1329
-keep__25: keep__12
-muxpart__75: muxpart__75
-logic__9137: logic__9137
-logic__7869: logic__7869
-logic__9577: logic__1311
-case__1290: case__1290
-case__1056: case__1056
-extladd: extladd
-datapath__110: datapath__110
-reg__1063: reg__1063
-logic__7969: logic__7969
-logic__9555: logic__2512
-logic__9543: logic__2540
-logic__2712: logic__2712
-case__739: case__739
-datapath__481: datapath__481
-reg__1068: reg__1068
-case__79: case__79
-logic__674: logic__674
-logic__7352: logic__7352
-logic__2961: logic__2961
-logic__2171: logic__2171
-logic__4431: logic__4431
-case__399: case__399
-logic__3409: logic__3409
-case__1421: case__1421
-case__1483: case__1483
-case__1523: case__1523
-datapath__78: datapath__78
-logic__9549: logic__2522
-logic__4904: logic__4904
-logic__9652: logic__1125
-logic__9457: logic__9457
-logic__2180: logic__2180
-logic__2584: logic__2584
-logic__229: logic__229
-logic__5937: logic__5937
-case__200: case__200
-reg__288: reg__288
-logic__2184: logic__2184
-datapath__21: datapath__21
-logic__6745: logic__6745
-logic__3408: logic__3408
-logic__4414: logic__4414
-logic__953: logic__953
-logic__9545: logic__2536
-muxpart__64: muxpart__64
-logic__7413: logic__7413
-logic__2830: logic__2830
-logic__2045: logic__2045
-logic__4675: logic__4675
-datapath__709: datapath__709
-logic__6198: logic__6198
-case__839: case__839
-reg__1538: reg__907
-case__1674: case__1674
-case__199: case__199
-muxpart__35: muxpart__35
-case__1476: case__1476
-logic__8589: logic__8589
-reg__1423: reg__1323
-reg__1253: reg__1253
-datapath__381: datapath__381
-reg__643: reg__643
-logic__8423: logic__8423
-logic__6544: logic__6544
-case__1019: case__1019
-case__1291: case__1291
-datapath__747: datapath__139
-reg__264: reg__264
-datapath__578: datapath__578
-muxpart__232: muxpart__232
-logic__1509: logic__1509
-logic__2291: logic__2291
-reg__198: reg__198
-logic__804: logic__804
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__1: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-sync: sync
-logic__9219: logic__9219
-logic__2518: logic__2518
-logic__5741: logic__5741
-case__535: case__535
-muxpart__202: muxpart__202
-logic__2815: logic__2815
-logic__1280: logic__1280
-case__1678: case__1678
-logic__7392: logic__7392
-AsyncValidSync__18: AsyncValidSync
-logic__9504: logic__3565
-logic__917: logic__917
-case__955: case__955
-case__953: case__953
-logic__4513: logic__4513
-reg__1366: reg__1366
-logic__5962: logic__5962
-logic__1031: logic__1031
-twiddle_ram__2: twiddle_ram
-logic__6575: logic__6575
-logic__5749: logic__5749
-logic__4905: logic__4905
-logic__5355: logic__5355
-reg__1122: reg__1122
-logic__853: logic__853
-logic__9567: logic__2478
-counter__20: counter__20
-case__1107: case__1107
-logic__4628: logic__4628
-reg__80: reg__80
-logic__7982: logic__7982
-logic__5156: logic__5156
-logic__9627: logic__1605
-logic__1512: logic__1512
-reg__1443: reg__1068
-logic__5034: logic__5034
-ram_2x77: ram_2x77
-logic__4336: logic__4336
-logic__5103: logic__5103
-logic__1734: logic__1734
-logic__4138: logic__4138
-case__448: case__448
-logic__7436: logic__7436
-reg__1413: reg__203
-reg__1407: reg__1407
-case__243: case__243
-logic__5519: logic__5519
-case__14: case__14
-reg__1386: reg__1386
-datapath__731: datapath__329
-reg__845: reg__845
-case__273: case__273
-logic__3206: logic__3206
-logic__1676: logic__1676
-datapath__44: datapath__44
-reg__629: reg__629
-datapath__52: datapath__52
-reg__728: reg__728
-case__568: case__568
-case__47: case__47
-logic__52: logic__52
-logic__6857: logic__6857
-case__287: case__287
-logic__2174: logic__2174
-reg__1545: reg__906
-logic__9562: logic__2491
-case__1707: case__730
-logic__5023: logic__5023
-logic__4726: logic__4726
-reg__1559: reg__238
-logic__1440: logic__1440
-case__965: case__965
-logic__1961: logic__1961
-reg__397: reg__397
-reg__1542: reg__906
-case__1597: case__1597
-logic__2640: logic__2640
-logic__6774: logic__6774
-reg__1081: reg__1081
-logic__4105: logic__4105
-reg__543: reg__543
-logic__3813: logic__3813
-logic__9610: logic__6769
-case__1474: case__1474
-reg__306: reg__306
-logic__5497: logic__5497
-logic__5169: logic__5169
-logic__6529: logic__6529
-case__843: case__843
-reg__1325: reg__1325
-logic__8847: logic__8847
-logic__5896: logic__5896
-logic__7979: logic__7979
-logic__1964: logic__1964
-logic__1005: logic__1005
-datapath__760: datapath__684
-logic__648: logic__648
-case__1001: case__1001
-logic__6481: logic__6481
-logic__8426: logic__8426
-logic__6756: logic__6756
-logic__1743: logic__1743
-case__910: case__910
-logic__9168: logic__9168
-logic__8163: logic__8163
-reg__1132: reg__1132
-ClockGroupAggregator_aggregator: ClockGroupAggregator_aggregator
-logic__2740: logic__2740
-logic__4316: logic__4316
-logic__8430: logic__8430
-fft_radix_2__parameterized1: fft_radix_2__parameterized1
-logic__5585: logic__5585
-reg__1508: reg__907
-reg__1531: reg__908
-logic__1163: logic__1163
-case__1658: case__1658
-logic__6114: logic__6114
-logic__6966: logic__6966
-logic__9049: logic__9049
-datapath__459: datapath__459
-logic__5740: logic__5740
-logic__4120: logic__4120
-datapath__499: datapath__499
-logic__1348: logic__1348
-reg__209: reg__209
-acq_nco_carr: acq_nco_carr
-logic__5252: logic__5252
-logic__3438: logic__3438
-logic__2173: logic__2173
-logic__1532: logic__1532
-logic__9093: logic__9093
-case__1616: case__1616
-datapath__345: datapath__345
-logic__7391: logic__7391
-case__1397: case__1397
-case__154: case__154
-counter__4: counter__4
-logic__9425: logic__9425
-logic__340: logic__340
-logic__9420: logic__9420
-logic__5048: logic__5048
-logic__3069: logic__3069
-logic__1823: logic__1823
-reg__197: reg__197
-logic__819: logic__819
-logic__1293: logic__1293
-case__208: case__208
-logic__85: logic__85
-logic__7156: logic__7156
-reg__963: reg__963
-reg__66: reg__66
-logic__4837: logic__4837
-case__376: case__376
-muxpart__236: muxpart__236
-logic__9303: logic__9303
-logic__8863: logic__8863
-logic__7070: logic__7070
-logic__6737: logic__6737
-datapath__371: datapath__371
-logic__2241: logic__2241
-logic__4419: logic__4419
-reg__882: reg__882
-logic__322: logic__322
-reg__789: reg__789
-logic__79: logic__79
-logic__1470: logic__1470
-muxpart__175: muxpart__175
-logic__6093: logic__6093
-logic__252: logic__252
-reg__19: reg__19
-logic__4301: logic__4301
-logic__7612: logic__7612
-datapath__251: datapath__251
-logic__4266: logic__4266
-case__288: case__288
-reg__1266: reg__1266
-logic__8870: logic__8870
-reg__290: reg__290
-logic__1735: logic__1735
-case__341: case__341
-dsp48e2__9: dsp48e2__9
-logic__1527: logic__1527
-case__1482: case__1482
-reg__1087: reg__1087
-reg__1537: reg__908
-muxpart__46: muxpart__46
-case__389: case__389
-logic__64: logic__64
-logic__9196: logic__9196
-case__718: case__718
-logic__5546: logic__5546
-addsub__8: addsub__5
-case__940: case__940
-logic__3057: logic__3057
-reg__1376: reg__1376
-mult_53_53_106: mult_53_53_106
-logic__2602: logic__2602
-reg__1290: reg__1290
-logic__9643: logic__1145
-case__696: case__696
-logic__7521: logic__7521
-logic__7407: logic__7407
-AsyncValidSync__20: AsyncValidSync
-datapath__292: datapath__292
-logic__3495: logic__3495
-case__1187: case__1187
-logic__9446: logic__9446
-reg__987: reg__987
-logic__3682: logic__3682
-logic__5196: logic__5196
-logic__6633: logic__6633
-reg__627: reg__627
-logic__5593: logic__5593
-ram_2x10: ram_2x10
-case__165: case__165
-reg__1469: reg__907
-logic__7005: logic__7005
-case__406: case__406
-logic__5928: logic__5928
-datapath__476: datapath__476
-RecFNToIN: RecFNToIN
-logic__7802: logic__7802
-case__1131: case__1131
-case__1088: case__1088
-logic__761: logic__761
-reg__1438: reg__1067
-logic__2187: logic__2187
-logic__7931: logic__7931
-datapath__155: datapath__155
-logic__4381: logic__4381
-logic__6992: logic__6992
-case__1000: case__1000
-logic__1319: logic__1319
-reg__348: reg__348
-logic__289: logic__289
-logic__8253: logic__8253
-logic__7370: logic__7370
-dsp48e2__28: dsp48e2__28
-case__1641: case__1641
-logic__844: logic__844
-case__1362: case__1362
-case__1259: case__1259
-reg__417: reg__417
-logic__7431: logic__7431
-reg__601: reg__601
-logic__1156: logic__1156
-logic__9606: logic__8145
-logic__1997: logic__1997
-datapath__650: datapath__650
-reg__798: reg__798
-case__449: case__449
-logic__6056: logic__6056
-logic__2567: logic__2567
-case__1147: case__1147
-case__963: case__963
-logic__1783: logic__1783
-logic__8701: logic__8701
-logic__9252: logic__9252
-case__1595: case__1595
-logic__6937: logic__6937
-muxpart__226: muxpart__226
-logic__2739: logic__2739
-logic__1846: logic__1846
-datapath__315: datapath__315
-case__1217: case__1217
-datapath__392: datapath__392
-reg__321: reg__321
-logic__9500: logic__3597
-case__283: case__283
-case__123: case__123
-case__656: case__656
-reg__549: reg__549
-reg__1418: reg__1328
-logic__9576: logic__1315
-IntSyncCrossingSource_n1x1_Registered: IntSyncCrossingSource_n1x1_Registered
-logic__845: logic__845
-logic__8777: logic__8777
-logic__4186: logic__4186
-case__1742: case__296
-case__722: case__722
-case__1730: case__1587
-logic__5931: logic__5931
-case__1359: case__1359
-datapath__561: datapath__561
-logic__4479: logic__4479
-logic__5235: logic__5235
-logic__5402: logic__5402
-case__415: case__415
-logic__2209: logic__2209
-logic__3448: logic__3448
-logic__2395: logic__2395
-extram__4: extram__4
-case__1333: case__1333
-case__824: case__824
-reg__1158: reg__1158
-case__798: case__798
-reg__1306: reg__1306
-logic__2867: logic__2867
-logic__4071: logic__4071
-logic__7092: logic__7092
-reg__204: reg__204
-logic__1099: logic__1099
-reg__846: reg__846
-logic__6695: logic__6695
-datapath__492: datapath__492
-datapath__732: datapath__328
-logic__9377: logic__9377
-logic__5483: logic__5483
-reg__867: reg__867
-datapath__53: datapath__53
-reg__732: reg__732
-logic__4690: logic__4690
-case__522: case__522
-logic__2064: logic__2064
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__19: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__4115: logic__4115
-logic__8259: logic__8259
-reg__1481: reg__907
-logic__351: logic__351
-logic__7031: logic__7031
-ram_2x124: ram_2x124
-logic__8114: logic__8114
-logic__7401: logic__7401
-case__786: case__786
-logic__5179: logic__5179
-logic__1605: logic__1605
-logic__9583: logic__9010
-case__221: case__221
-logic__7906: logic__7906
-case__1683: case__1683
-logic__3771: logic__3771
-reg__245: reg__245
-datapath__59: datapath__59
-logic__1358: logic__1358
-logic__5492: logic__5492
-case__257: case__257
-reg__839: reg__839
-reg__1174: reg__1174
-logic__1138: logic__1138
-logic__2707: logic__2707
-TLError_1: TLError_1
-logic__6916: logic__6916
-case__400: case__400
-ram_2x123: ram_2x123
-logic__5891: logic__5891
-reg__1134: reg__1134
-logic__2870: logic__2870
-logic__2650: logic__2650
-muxpart__19: muxpart__19
-reg__853: reg__853
-logic__2741: logic__2741
-reg__75: reg__75
-logic__124: logic__124
-logic__1473: logic__1473
-logic__210: logic__210
-logic__255: logic__255
-logic__7997: logic__7997
-reg__217: reg__217
-logic__4884: logic__4884
-case__588: case__588
-datapath__739: datapath__46
-datapath__256: datapath__256
-logic__372: logic__372
-logic__2512: logic__2512
-case__838: case__838
-logic__8969: logic__8969
-logic__473: logic__473
-reg__1303: reg__1303
-logic__3170: logic__3170
-logic__2088: logic__2088
-reg__482: reg__482
-case__737: case__737
-case__1677: case__1677
-logic__9637: logic__1163
-logic__6036: logic__6036
-logic__4909: logic__4909
-reg__407: reg__407
-reg__1121: reg__1121
-logic__7416: logic__7416
-case__1634: case__1634
-logic__1614: logic__1614
-trck_cntrl: trck_cntrl
-logic__9469: logic__9469
-logic__634: logic__634
-logic__8144: logic__8144
-datapath__138: datapath__138
-reg__826: reg__826
-logic__2247: logic__2247
-logic__1822: logic__1822
-logic__1795: logic__1795
-logic__3228: logic__3228
-case__1607: case__1607
-logic__4121: logic__4121
-logic__5865: logic__5865
-reg__478: reg__478
-datapath__467: datapath__467
-logic__2316: logic__2316
-logic__9642: logic__1146
-reg__960: reg__960
-logic__8130: logic__8130
-logic__9632: logic__1174
-logic__984: logic__984
-reg__905: reg__905
-cordic_angle_lut__parameterized0__1: cordic_angle_lut__parameterized0
-logic__1643: logic__1643
-case__1716: case__1601
-logic__9620: logic__6769
-logic__1205: logic__1205
-case__11: case__11
-datapath__527: datapath__527
-reg__1361: reg__1361
-case__1567: case__1567
-logic__1638: logic__1638
-case__225: case__225
-reg__471: reg__471
-logic__4655: logic__4655
-reg__1067: reg__1067
-logic__5258: logic__5258
-logic__2871: logic__2871
-logic__2814: logic__2814
-logic__7154: logic__7154
-logic__4534: logic__4534
-logic__4212: logic__4212
-logic__5552: logic__5552
-muxpart__8: muxpart__8
-reg__719: reg__719
-case__1222: case__1222
-datapath__308: datapath__308
-case__1614: case__1614
-logic__4147: logic__4147
-logic__1407: logic__1407
-logic__9496: logic__3601
-case__334: case__334
-case__12: case__12
-reg__1218: reg__1218
-logic__6049: logic__6049
-reg__156: reg__156
-logic__2941: logic__2941
-logic__4051: logic__4051
-reg__1291: reg__1291
-logic__3466: logic__3466
-muxpart__172: muxpart__172
-datapath__679: datapath__679
-logic__2952: logic__2952
-reg__642: reg__642
-logic__746: logic__746
-reg__1459: reg__908
-logic__6811: logic__6811
-reg__816: reg__816
-datapath__307: datapath__307
-logic__4776: logic__4776
-logic__4972: logic__4972
-logic__9386: logic__9386
-logic__6118: logic__6118
-logic__5015: logic__5015
-logic__2063: logic__2063
-reg__799: reg__799
-counter__25: counter__25
-logic__5380: logic__5380
-reg__1433: reg__1216
-reg__1396: reg__1396
-logic__6480: logic__6480
-muxpart__44: muxpart__44
-datapath__293: datapath__293
-reg__20: reg__20
-reg__659: reg__659
-datapath__765: datapath__163
-logic__2633: logic__2633
-case__1342: case__1342
-logic__1976: logic__1976
-logic__5617: logic__5617
-reg__172: reg__172
-logic__4515: logic__4515
-case__749: case__749
-case__1556: case__1556
-reg__997: reg__997
-logic__8778: logic__8778
-logic__7262: logic__7262
-logic__744: logic__744
-logic__6814: logic__6814
-reg__1183: reg__1183
-logic__6668: logic__6668
-logic__2309: logic__2309
-logic__9526: logic__4601
-datapath__446: datapath__446
-case__459: case__459
-reg__802: reg__802
-logic__9510: logic__4639
-logic__7360: logic__7360
-logic__2550: logic__2550
-case__1653: case__1653
-reg__1517: reg__907
-reg__1307: reg__1307
-logic__8351: logic__8351
-reg__497: reg__497
-logic__3622: logic__3622
-VCU118RocketSystem__GC0: VCU118RocketSystem__GC0
-reg__106: reg__106
-logic__5673: logic__5673
-case__615: case__615
-logic__4196: logic__4196
-datapath__453: datapath__453
-logic__4413: logic__4413
-reg__128: reg__128
-reg__367: reg__367
-muxpart__36: muxpart__36
-logic__7027: logic__7027
-logic__8942: logic__8942
-logic__5636: logic__5636
-logic__4307: logic__4307
-case__1280: case__1280
-dual_port_ram: dual_port_ram
-logic__4731: logic__4731
-datapath__666: datapath__666
-logic__9603: logic__8793
-case__1343: case__1343
-logic__5428: logic__5428
-logic__7137: logic__7137
-datapath__228: datapath__228
-dsp48e2__14: dsp48e2__14
-logic__141: logic__141
-logic__1708: logic__1708
-case__616: case__616
-logic__9237: logic__9237
-case__1072: case__1072
-logic__7099: logic__7099
-keep__12: keep__12
-case__609: case__609
-muxpart__27: muxpart__27
-logic__2016: logic__2016
-logic__9195: logic__9195
-logic__9619: logic__6774
-logic__5560: logic__5560
-logic__3836: logic__3836
-reg__11: reg__11
-logic__8622: logic__8622
-reg__344: reg__344
-keep__51: keep__8
-reg__1105: reg__1105
-case__726: case__726
-reg__202: reg__202
-reg__995: reg__995
-TLBusBypassBar: TLBusBypassBar
-reg__1112: reg__1112
-logic__8961: logic__8961
-case__557: case__557
-logic__3473: logic__3473
-reg__1170: reg__1170
-logic__5961: logic__5961
-case__1663: case__1663
-logic__8187: logic__8187
-case__254: case__254
-case__735: case__735
-reg__545: reg__545
-logic__8191: logic__8191
-case__771: case__771
-case__1298: case__1298
-logic__5385: logic__5385
-ClockGroupAggregator_sbus: ClockGroupAggregator_sbus
-case__1429: case__1429
-logic__4613: logic__4613
-logic__7366: logic__7366
-logic__6752: logic__6752
-datapath__211: datapath__211
-logic__3614: logic__3614
-muxpart__245: muxpart__245
-logic__4177: logic__4177
-reg__542: reg__542
-case__27: case__27
-datapath__429: datapath__429
-logic__9267: logic__9267
-logic__5136: logic__5136
-reg__1171: reg__1171
-logic__3334: logic__3334
-logic__1991: logic__1991
-reg__385: reg__385
-reg__1202: reg__1202
-reg__38: reg__38
-logic__5097: logic__5097
-Repeater_TLBundleA_a29d64s2k1z3u__1: Repeater_TLBundleA_a29d64s2k1z3u
-logic__6836: logic__6836
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__20: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__715: logic__715
-datapath__688: datapath__688
-logic__2297: logic__2297
-logic__410: logic__410
-logic__4685: logic__4685
-dsp48e2__16: dsp48e2__16
-case__964: case__964
-logic__7844: logic__7844
-TilePRCIDomain__GC0: TilePRCIDomain__GC0
-logic__747: logic__747
-case__179: case__179
-logic__7397: logic__7397
-logic__8717: logic__8717
-logic__9179: logic__9179
-logic__5190: logic__5190
-logic__8338: logic__8338
-datapath__172: datapath__172
-logic__5464: logic__5464
-reg__1357: reg__1357
-logic__4631: logic__4631
-logic__2500: logic__2500
-IntXbar_i1_o1: IntXbar_i1_o1
-logic__8529: logic__8529
-logic__6137: logic__6137
-case__1485: case__1485
-TLBuffer_a32d64s1k1z4u_1: TLBuffer_a32d64s1k1z4u_1
-reg__744: reg__744
-sync__8: sync
-datapath__662: datapath__662
-logic__805: logic__805
-extrom__1: extrom__1
-reg__807: reg__807
-case__864: case__864
-case__143: case__143
-case__1067: case__1067
-datapath__223: datapath__223
-mult_66_66_66: mult_66_66_66
-case__931: case__931
-logic__150: logic__150
-logic__1150: logic__1150
-logic__9644: logic__1144
-reg__1302: reg__1302
-logic__9579: logic__1307
-reg__892: reg__892
-logic__7020: logic__7020
-case__378: case__378
-logic__6589: logic__6589
-logic__5995: logic__5995
-logic__3278: logic__3278
-logic__7255: logic__7255
-reg__1084: reg__1084
-case__1657: case__1657
-logic__727: logic__727
-logic__7222: logic__7222
-logic__806: logic__806
-logic__4543: logic__4543
-case__1710: case__726
-reg__592: reg__592
-case__1233: case__1233
-logic__7435: logic__7435
-logic__3666: logic__3666
-logic__1546: logic__1546
-logic__2632: logic__2632
-reg__1120: reg__1120
-datapath__441: datapath__441
-RoundAnyRawFNToRecFN_2: RoundAnyRawFNToRecFN_2
-logic__4792: logic__4792
-datapath__733: datapath__327
-logic__5612: logic__5612
-case__202: case__202
-logic__4313: logic__4313
-reg__709: reg__709
-logic__6653: logic__6653
-logic__4748: logic__4748
-logic__4985: logic__4985
-logic__7594: logic__7594
-logic__6780: logic__6780
-reg__1327: reg__1327
-logic__5586: logic__5586
-logic__5951: logic__5951
-logic__3253: logic__3253
-datapath__8: datapath__8
-logic__7238: logic__7238
-reg__521: reg__521
-reg__1145: reg__1145
-case__677: case__677
-case__1572: case__1572
-logic__9106: logic__9106
-case__1109: case__1109
-logic__4511: logic__4511
-logic__1520: logic__1520
-reg__674: reg__674
-logic__4680: logic__4680
-logic__5604: logic__5604
-reg__579: reg__579
-datapath__408: datapath__408
-dsp48e2__43: dsp48e2__43
-logic__5526: logic__5526
-reg__848: reg__848
-logic__2417: logic__2417
-muxpart__93: muxpart__93
-logic__2888: logic__2888
-muxpart__231: muxpart__231
-logic__5477: logic__5477
-logic__7808: logic__7808
-logic__1306: logic__1306
-reg__1241: reg__1241
-case__310: case__310
-logic__1200: logic__1200
-logic__4487: logic__4487
-reg__1298: reg__1298
-reg__1389: reg__1389
-logic__6125: logic__6125
-logic__5397: logic__5397
-reg__701: reg__701
-reg__173: reg__173
-reg__1196: reg__1196
-muxpart__380: muxpart__380
-case__1513: case__1513
-logic__6746: logic__6746
-logic__2901: logic__2901
-reg__1548: reg__906
-datapath__696: datapath__696
-logic__5822: logic__5822
-logic__6985: logic__6985
-reg__697: reg__697
-logic__5124: logic__5124
-logic__3866: logic__3866
-case__1247: case__1247
-reg__1032: reg__1032
-case__1717: case__1600
-reg__1113: reg__1113
-logic__1331: logic__1331
-logic__9633: logic__1169
-logic__7114: logic__7114
-logic__5539: logic__5539
-reg__683: reg__683
-reg__645: reg__645
-logic__2983: logic__2983
-logic__3916: logic__3916
-case__1090: case__1090
-case__1253: case__1253
-datapath__711: datapath__711
-logic__6732: logic__6732
-case__1433: case__1433
-extram__10: extram__3
-case__800: case__800
-TLFragmenter_FPGAUART__1: TLFragmenter_FPGAUART
-reg__973: reg__973
-reg__152: reg__152
-logic__9551: logic__2520
-HellaCacheArbiter: HellaCacheArbiter
-case__807: case__807
-reg__252: reg__252
-logic__1565: logic__1565
-logic__9164: logic__9164
-logic__6005: logic__6005
-keep__13: keep__13
-reg__17: reg__17
-datapath__7: datapath__7
-reg__637: reg__637
-logic__2029: logic__2029
-logic__1853: logic__1853
-reg__363: reg__363
-logic__3417: logic__3417
-logic__5109: logic__5109
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__8: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-logic__7563: logic__7563
-logic__2749: logic__2749
-logic__6627: logic__6627
-datapath__82: datapath__82
-logic__4679: logic__4679
-logic__1228: logic__1228
-logic__4761: logic__4761
-muxpart__356: muxpart__356
-reg__583: reg__583
-logic__4305: logic__4305
-case__1198: case__1198
-logic__4874: logic__4874
-case__1089: case__1089
-reg__884: reg__884
-logic__1430: logic__1430
-logic__7949: logic__7949
-logic__1216: logic__1216
-case__1320: case__1320
-datapath__326: datapath__326
-reg__1125: reg__1125
-logic__6195: logic__6195
-case__155: case__155
-logic__8609: logic__8609
-datapath__200: datapath__200
-reg__424: reg__424
-logic__7551: logic__7551
-reg__7: reg__7
-case__372: case__372
-reg__414: reg__414
-logic__7294: logic__7294
-reg__49: reg__49
-logic__7434: logic__7434
-reg__1172: reg__1172
-case__712: case__712
-logic__9349: logic__9349
-addsub__3: addsub__3
-logic__3111: logic__3111
-case__564: case__564
-reg__469: reg__469
-logic__8861: logic__8861
-case__362: case__362
-reg__1165: reg__1165
-case__1434: case__1434
-reg__349: reg__349
-logic__8867: logic__8867
-logic__5632: logic__5632
-reg__477: reg__477
-datapath__603: datapath__603
-case__1520: case__1520
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__8: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__2671: logic__2671
-case__1: case__1
-logic__1641: logic__1641
-reg__1244: reg__1244
-logic__9509: logic__4655
-reg__480: reg__480
-datapath: datapath
-case__350: case__350
-logic__9650: logic__1132
-logic__4936: logic__4936
-double_ff_syn: double_ff_syn
-logic__3725: logic__3725
-logic__6180: logic__6180
-logic__4441: logic__4441
-reg__205: reg__205
-datapath__118: datapath__118
-logic__9574: logic__929
-logic__9445: logic__9445
-reg__316: reg__316
-logic__7111: logic__7111
-logic__1557: logic__1557
-case__1651: case__1651
-datapath__126: datapath__126
-reg__122: reg__122
-logic__5927: logic__5927
-logic__1051: logic__1051
-datapath__509: datapath__509
-reg__563: reg__563
-logic__5950: logic__5950
-logic__3301: logic__3301
-logic__8398: logic__8398
-logic__6046: logic__6046
-logic__2716: logic__2716
-muxpart__178: muxpart__178
-logic__8799: logic__8799
-datapath__358: datapath__358
-dsp48e2__8: dsp48e2__8
-logic__2785: logic__2785
-logic__8994: logic__8994
-logic__4389: logic__4389
-logic__8282: logic__8282
-reg__1268: reg__1268
-ram__13: ram__4
-reg__1402: reg__1402
-logic__265: logic__265
-logic__1362: logic__1362
-logic__3783: logic__3783
-logic__3444: logic__3444
-logic__2352: logic__2352
-case__1544: case__1544
-logic__9223: logic__9223
-logic__6057: logic__6057
-reg__1236: reg__1236
-case__138: case__138
-logic__5481: logic__5481
-logic__633: logic__633
-logic__2786: logic__2786
-reg__1078: reg__1078
-muxpart__151: muxpart__151
-logic__3821: logic__3821
-datapath__92: datapath__92
-reg__415: reg__415
-case__791: case__791
-logic__352: logic__352
-reg__871: reg__871
-LevelGateway__4: LevelGateway
-logic__1642: logic__1642
-reg__615: reg__615
-logic__8238: logic__8238
-reg__982: reg__982
-reg__949: reg__949
-logic__8132: logic__8132
-datapath__295: datapath__295
-case__1052: case__1052
-case__340: case__340
-logic__9449: logic__9449
-logic__3554: logic__3554
-logic__7389: logic__7389
-extladd__2: extladd__2
-reg__1110: reg__1110
-case__860: case__860
-reg__776: reg__776
-datapath__753: datapath__691
-keep__19: keep__12
-logic__2281: logic__2281
-muxpart__147: muxpart__147
-counter__17: counter__17
-dsp48e2__1: dsp48e2__1
-case__1241: case__1241
-reg__1488: reg__906
-reg__1504: reg__908
-ram__2: ram__2
-case__1721: case__1596
-muxpart__81: muxpart__81
-logic__8035: logic__8035
-logic__2884: logic__2884
-case__563: case__563
-muxpart__205: muxpart__205
-datapath__27: datapath__27
-datapath__454: datapath__454
-case__1122: case__1122
-case__1014: case__1014
-TLFragmenter_bootrom: TLFragmenter_bootrom
-case__397: case__397
-datapath__663: datapath__663
-extram: extram
-case__952: case__952
-logic__4512: logic__4512
-logic__7964: logic__7964
-reg__1188: reg__1188
-logic__6007: logic__6007
-logic__5609: logic__5609
-case__1301: case__1301
-case__414: case__414
-logic__3066: logic__3066
-datapath__410: datapath__410
-logic__4352: logic__4352
-datapath__24: datapath__24
-reg__560: reg__560
-logic__5988: logic__5988
-logic__9605: logic__8798
-logic__1132: logic__1132
-case__235: case__235
-logic__7139: logic__7139
-logic__1972: logic__1972
-case__539: case__539
-reg__1223: reg__1223
-dsp48e2__36: dsp48e2__36
-muxpart__2: muxpart__2
-reg__847: reg__847
-bootromClockSinkDomain: bootromClockSinkDomain
-muxpart: muxpart
-muxpart__31: muxpart__31
-datapath__518: datapath__518
-reg__519: reg__519
-logic__4991: logic__4991
-datapath__558: datapath__558
-reg__1034: reg__1034
-logic__7422: logic__7422
-logic__330: logic__330
-TLWidthWidget8_2: TLWidthWidget8_2
-logic__2891: logic__2891
-logic__3538: logic__3538
-logic__8136: logic__8136
-logic__5485: logic__5485
-logic__9569: logic__2476
-logic__2139: logic__2139
-case__527: case__527
-logic__7376: logic__7376
-datapath__317: datapath__317
-reg__452: reg__452
-logic__968: logic__968
-datapath__744: datapath__142
-logic__4089: logic__4089
-logic__8940: logic__8940
-case__1244: case__1244
-case__569: case__569
-case__1085: case__1085
-logic__1369: logic__1369
-reg__1198: reg__1198
-case__1225: case__1225
-case__1660: case__1660
-logic__9389: logic__9389
-logic__813: logic__813
-double_ff_syn__3: double_ff_syn
-logic__2290: logic__2290
-datapath__755: datapath__689
-case__1183: case__1183
-case__1163: case__1163
-logic__7351: logic__7351
-logic__453: logic__453
-reg__824: reg__824
-logic__3694: logic__3694
-logic__2466: logic__2466
-reg__1454: reg__907
-logic__3156: logic__3156
-logic__9441: logic__9441
-logic__6669: logic__6669
-logic__1581: logic__1581
-logic__9451: logic__9451
-logic__7974: logic__7974
-reg__1373: reg__1373
-case__401: case__401
-FPUFMAPipe_l4_f64: FPUFMAPipe_l4_f64
-reg__762: reg__762
-logic__8873: logic__8873
-muxpart__239: muxpart__239
-reg__21: reg__21
-muxpart__230: muxpart__230
-logic__5878: logic__5878
-reg__634: reg__634
-logic__1327: logic__1327
-reg__113: reg__113
-case__794: case__794
-reg__110: reg__110
-AsyncQueueSource_TLBundleD_a9d32s1k1z2u: AsyncQueueSource_TLBundleD_a9d32s1k1z2u
-logic__8936: logic__8936
-case__1386: case__1386
-reg__1515: reg__906
-reg__696: reg__696
-FPU__GB0: FPU__GB0
-logic__2282: logic__2282
-logic__3051: logic__3051
-case__1543: case__1543
-reg__1021: reg__1021
-reg__1510: reg__908
-logic__6816: logic__6816
-datapath__714: datapath__714
-logic__6655: logic__6655
-datapath__692: datapath__692
-logic__3485: logic__3485
-datapath__672: datapath__672
-logic__6952: logic__6952
-datapath__281: datapath__281
-logic__9248: logic__9248
-case__1371: case__1371
-muxpart__374: muxpart__374
-rom__8: rom__8
-reg__1465: reg__908
-logic__1720: logic__1720
-datapath__750: datapath__136
-logic__4432: logic__4432
-reg__1055: reg__1055
-logic__7206: logic__7206
-reg__244: reg__244
-datapath__71: datapath__71
-logic__971: logic__971
-case__425: case__425
-case__867: case__867
-logic__9524: logic__4606
-reg__582: reg__582
-reg__1326: reg__1326
-reg__310: reg__310
-case__941: case__941
-logic__3312: logic__3312
-case__163: case__163
-reg__835: reg__835
-logic__7570: logic__7570
-logic__5431: logic__5431
-case__918: case__918
-counter__26: counter__26
-muxpart__54: muxpart__54
-logic__4438: logic__4438
-logic__7250: logic__7250
-case__1596: case__1596
-case__1558: case__1558
-reg__356: reg__356
-datapath__414: datapath__414
-TLPLIC: TLPLIC
-case__1539: case__1539
-reg__1422: reg__1324
-logic__754: logic__754
-logic__6727: logic__6727
-logic__1333: logic__1333
-case__556: case__556
-reg__1045: reg__1045
-case__1504: case__1504
-case__685: case__685
-reg__369: reg__369
-logic__8367: logic__8367
-logic__1290: logic__1290
-reg__1420: reg__1326
-logic__4772: logic__4772
-reg__62: reg__62
-case__1140: case__1140
-ClockGroup__2: ClockGroup
-case__1497: case__1497
-datapath__406: datapath__406
-muxpart__58: muxpart__58
-case__1190: case__1190
-case__1501: case__1501
-case__813: case__813
-reg__71: reg__71
-case__645: case__645
-case__364: case__364
-reg__661: reg__661
-datapath__723: datapath__723
-reg__1338: reg__1338
-datapath__620: datapath__620
-case__148: case__148
-reg__1255: reg__1255
-reg__849: reg__849
-logic__631: logic__631
-logic__5756: logic__5756
-logic__7287: logic__7287
-case__359: case__359
-logic__5594: logic__5594
-logic__1035: logic__1035
-case__985: case__985
-reg__254: reg__254
-datapath__758: datapath__686
-reg__1511: reg__907
-logic__1188: logic__1188
-case__944: case__944
-logic__3181: logic__3181
-case__708: case__708
-logic__1811: logic__1811
-reg__1388: reg__1388
-logic__8707: logic__8707
-logic__9224: logic__9224
-muxpart__180: muxpart__180
-logic__7188: logic__7188
-reg__530: reg__530
-datapath__291: datapath__291
-datapath__628: datapath__628
-logic__5844: logic__5844
-logic__1335: logic__1335
-logic__4394: logic__4394
-logic__939: logic__939
-muxpart__258: muxpart__258
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__12: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-case__759: case__759
-sync__9: sync
-reg__1261: reg__1261
-case__1102: case__1102
-datapath__547: datapath__547
-logic__1271: logic__1271
-case__1124: case__1124
-reg__203: reg__203
-case__1573: case__1573
-datapath__352: datapath__352
-reg__1137: reg__1137
-logic__3789: logic__3789
-datapath__676: datapath__676
-case__1518: case__1518
-AsyncValidSync__19: AsyncValidSync
-reg__1197: reg__1197
-case__1284: case__1284
-reg__1529: reg__907
-logic__9460: logic__9460
-datapath__338: datapath__338
-logic__5541: logic__5541
-logic__3337: logic__3337
-logic__6672: logic__6672
-reg__841: reg__841
-AsyncValidSync__7: AsyncValidSync
-case__13: case__13
-ICache: ICache
-case__1130: case__1130
-logic__5392: logic__5392
-DivSqrtRawFN_small_1: DivSqrtRawFN_small_1
-reg__1567: reg__150
-case__1186: case__1186
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__32: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-datapath__226: datapath__226
-reg__1086: reg__1086
-logic__7136: logic__7136
-muxpart__193: muxpart__193
-logic__4499: logic__4499
-datapath__703: datapath__703
-case__267: case__267
-muxpart__385: muxpart__385
-case__840: case__840
-case__601: case__601
-reg__184: reg__184
-reg__1020: reg__1020
-logic__1966: logic__1966
-reg__258: reg__258
-logic__6055: logic__6055
-logic__6794: logic__6794
-reg__1330: reg__1330
-reg__933: reg__933
-case__223: case__223
-case__734: case__734
-logic__3210: logic__3210
-logic__2761: logic__2761
-datapath__2: datapath__2
-datapath__774: datapath__42
-case__570: case__570
-logic__6002: logic__6002
-reg__1457: reg__907
-case__410: case__410
-case__534: case__534
-logic__1926: logic__1926
-case__937: case__937
-logic__7766: logic__7766
-keep__27: keep__13
-reg__1246: reg__1246
-logic__318: logic__318
-logic__9292: logic__9292
-case__917: case__917
-case__1332: case__1332
-logic__3475: logic__3475
-reg__797: reg__797
-reg__345: reg__345
-datapath__278: datapath__278
-case__766: case__766
-logic__6723: logic__6723
-case__1415: case__1415
-logic__1679: logic__1679
-logic__5372: logic__5372
-datapath__729: datapath__331
-reg__384: reg__384
-logic__3336: logic__3336
-case__928: case__928
-datapath__305: datapath__305
-logic__4374: logic__4374
-reg__1384: reg__1384
-reg__558: reg__558
-logic__4697: logic__4697
-reg__1546: reg__908
-logic__8691: logic__8691
-logic__5677: logic__5677
-TLInterconnectCoupler_pbus_to_fpga_uart__1: TLInterconnectCoupler_pbus_to_fpga_uart
-logic__3617: logic__3617
-logic__8151: logic__8151
-reg__1316: reg__1316
-logic__2329: logic__2329
-case__346: case__346
-reg__1152: reg__1152
-logic__4048: logic__4048
-logic__964: logic__964
-reg__1464: reg__906
-logic__8126: logic__8126
-case__420: case__420
-logic__5968: logic__5968
-reg__914: reg__914
-logic__3338: logic__3338
-logic__6350: logic__6350
-datapath__312: datapath__312
-logic__9280: logic__9280
-case__281: case__281
-logic__386: logic__386
-logic__51: logic__51
-logic__2219: logic__2219
-reg__233: reg__233
-logic__7214: logic__7214
-logic__1273: logic__1273
-reg__342: reg__342
-logic__2111: logic__2111
-datapath__33: datapath__33
-butterfly: butterfly
-logic__3340: logic__3340
-logic__2280: logic__2280
-reg__1030: reg__1030
-logic__5959: logic__5959
-logic__6310: logic__6310
-case__608: case__608
-logic__7734: logic__7734
-reg__1102: reg__1102
-case__1188: case__1188
-logic__2519: logic__2519
-logic__1276: logic__1276
-logic__9427: logic__9427
-case__1035: case__1035
-logic__9208: logic__9208
-reg__881: reg__881
-logic__1944: logic__1944
-logic__269: logic__269
-logic__7241: logic__7241
-datapath__664: datapath__664
-logic__7409: logic__7409
-reg__903: reg__903
-logic__810: logic__810
-logic__5548: logic__5548
-logic__6665: logic__6665
-case__593: case__593
-reg__419: reg__419
-case__264: case__264
-signinv: signinv
-reg__101: reg__101
-keep__36: keep__13
-case__492: case__492
-logic__47: logic__47
-logic__5272: logic__5272
-case__765: case__765
-logic__2895: logic__2895
-logic__5637: logic__5637
-logic__5359: logic__5359
-logic__7078: logic__7078
-reg__48: reg__48
-logic__2778: logic__2778
-logic__3456: logic__3456
-case__315: case__315
-reg__1274: reg__1274
-case__748: case__748
-reg__658: reg__658
-logic__7284: logic__7284
-reg__241: reg__241
-case__1713: case__723
-case__355: case__355
-logic__4306: logic__4306
-reg__1452: reg__1044
-Repeater_TLBundleA_a28d64s2k1z3u: Repeater_TLBundleA_a28d64s2k1z3u
-logic__9532: logic__4595
-reg__416: reg__416
-datapath__616: datapath__616
-reg__1151: reg__1151
-logic__4093: logic__4093
-logic__5197: logic__5197
-datapath__576: datapath__576
-logic__6059: logic__6059
-logic__6802: logic__6802
-logic__1733: logic__1733
-logic__2193: logic__2193
-muxpart__16: muxpart__16
-reg__1157: reg__1157
-logic__8962: logic__8962
-logic__898: logic__898
-datapath__609: datapath__609
-logic__7784: logic__7784
-logic__3537: logic__3537
-logic__2252: logic__2252
-logic__6032: logic__6032
-datapath__498: datapath__498
-logic__9636: logic__1164
-reg__1427: reg__1216
-reg__325: reg__325
-muxpart__30: muxpart__30
-reg__31: reg__31
-logic__1194: logic__1194
-logic__9517: logic__4619
-logic__2588: logic__2588
-reg__1072: reg__1072
-logic__8131: logic__8131
-reg__135: reg__135
-case__1577: case__1577
-reg__869: reg__869
-logic__5299: logic__5299
-datapath__355: datapath__355
-logic__3874: logic__3874
-ram__4: ram__4
-case__461: case__461
-datapath__115: datapath__115
-reg__970: reg__970
-datapath__56: datapath__56
-case__1624: case__1624
-logic__7263: logic__7263
-logic__6976: logic__6976
-datapath__523: datapath__523
-case__992: case__992
-logic__5984: logic__5984
-case__1360: case__1360
-logic__9482: logic__3628
-case__1509: case__1509
-logic__4925: logic__4925
-logic__5748: logic__5748
-datapath__493: datapath__493
-case__1058: case__1058
-datapath__323: datapath__323
-muxpart__199: muxpart__199
-logic__4411: logic__4411
-datapath__81: datapath__81
-logic__6003: logic__6003
-logic__1870: logic__1870
-case__802: case__802
-logic__2102: logic__2102
-case__441: case__441
-FPGAUARTClockSinkDomain: FPGAUARTClockSinkDomain
-logic__8056: logic__8056
-reg__535: reg__535
-logic__2911: logic__2911
-datapath__585: datapath__585
-case__545: case__545
-addsub__7: addsub__6
-logic__4451: logic__4451
-logic__2634: logic__2634
-case__1643: case__1643
-logic__5232: logic__5232
-sample_align: sample_align
-case__590: case__590
-case__1519: case__1519
-logic__1724: logic__1724
-logic__6099: logic__6099
-logic__3242: logic__3242
-logic__6136: logic__6136
-logic__5150: logic__5150
-case__402: case__402
-reg__1502: reg__907
-case__469: case__469
-reg__459: reg__459
-logic__8269: logic__8269
-reg__1312: reg__1312
-logic__1776: logic__1776
-case__352: case__352
-reg__840: reg__840
-case__144: case__144
-reg__266: reg__266
-case__1581: case__1581
-case__648: case__648
-reg__1414: reg__202
-case__761: case__761
-logic__4403: logic__4403
-case__1586: case__1586
-case__1702: case__653
-reg__822: reg__822
-case__927: case__927
-case__1374: case__1374
-AsyncValidSync__15: AsyncValidSync
-logic__1588: logic__1588
-reg__561: reg__561
-logic__8882: logic__8882
-logic__1399: logic__1399
-logic__9654: logic__1123
-datapath__687: datapath__687
-RoundRawFNToRecFN: RoundRawFNToRecFN
-datapath__132: datapath__132
-logic__4127: logic__4127
-logic__8325: logic__8325
-reg__1436: reg__1069
-logic__6826: logic__6826
-logic__3165: logic__3165
-logic__6035: logic__6035
-case__426: case__426
-reg__1385: reg__1385
-logic__7130: logic__7130
-case__227: case__227
-case__272: case__272
-datapath__421: datapath__421
-logic__1214: logic__1214
-logic__2908: logic__2908
-datapath__224: datapath__224
-logic__7972: logic__7972
-logic__7081: logic__7081
-logic__1315: logic__1315
-TLDebugModule: TLDebugModule
-dsp48e2__21: dsp48e2__21
-logic__7704: logic__7704
-logic__4412: logic__4412
-logic__3269: logic__3269
-datapath__299: datapath__299
-logic__7235: logic__7235
-logic__6168: logic__6168
-CLINTClockSinkDomain: CLINTClockSinkDomain
-case__413: case__413
-AsyncValidSync__8: AsyncValidSync
-logic__6926: logic__6926
-logic__1332: logic__1332
-logic__4317: logic__4317
-case__450: case__450
-logic__7348: logic__7348
-logic__1437: logic__1437
-reg__1024: reg__1024
-logic__6659: logic__6659
-case__1606: case__1606
-logic__511: logic__511
-logic__5864: logic__5864
-logic__2332: logic__2332
-logic__7091: logic__7091
-reg__889: reg__889
-binary_to_gray__1: binary_to_gray
-dsp48e2__3: dsp48e2__3
-datapath__346: datapath__346
-datapath__180: datapath__180
-case__892: case__892
-AsyncResetSynchronizerShiftReg_w1_d3_i0_1__17: AsyncResetSynchronizerShiftReg_w1_d3_i0_1
-logic__2315: logic__2315
-logic__5710: logic__5710
-keep__7: keep__7
-logic__208: logic__208
-case__660: case__660
-logic__6893: logic__6893
-LevelGateway__5: LevelGateway
-logic__5848: logic__5848
-keep__33: keep__13
-reg__1026: reg__1026
-case__366: case__366
-case__922: case__922
-datapath__9: datapath__9
-logic__9628: logic__1604
-logic__4600: logic__4600
-case__1387: case__1387
-reg__104: reg__104
-logic__2562: logic__2562
-case__1053: case__1053
-reg__287: reg__287
-logic__1824: logic__1824
-logic__1965: logic__1965
-datapath__500: datapath__500
-reg__218: reg__218
-reg__406: reg__406
-case__1029: case__1029
-rom__5: rom__5
-muxpart__66: muxpart__66
-logic__7809: logic__7809
-logic__7127: logic__7127
-logic__6750: logic__6750
-TLInterconnectCoupler_pbus_to_gps: TLInterconnectCoupler_pbus_to_gps
-extram__2: extram__2
-logic__4519: logic__4519
-reg__1401: reg__1401
-case__1373: case__1373
-dsp48e2__38: dsp48e2__38
-logic__5572: logic__5572
-logic__3073: logic__3073
-case__649: case__649
-case__490: case__490
-case__1075: case__1075
-datapath__238: datapath__238
-reg__998: reg__998
-case__743: case__743
-datapath__533: datapath__533
-keep__34: keep__12
-reg__571: reg__571
-logic__3660: logic__3660
-reg__1043: reg__1043
-logic__900: logic__900
-logic__5870: logic__5870
-case__790: case__790
-logic__1146: logic__1146
-datapath__266: datapath__266
-logic__6724: logic__6724
-reg__538: reg__538
-reg__303: reg__303
-logic__285: logic__285
-reg__955: reg__955
-logic__9006: logic__9006
-dsp48e2__23: dsp48e2__23
-reg__408: reg__408
-datapath__456: datapath__456
-reg__470: reg__470
-reg__1304: reg__1304
-logic__3878: logic__3878
-logic__14: logic__14
-logic__9433: logic__9433
-logic__8508: logic__8508
-datapath__49: datapath__49
-logic__8759: logic__8759
-reg__690: reg__690
-datapath__332: datapath__332
-reg__540: reg__540
-logic__8983: logic__8983
-logic__4232: logic__4232
-logic__5996: logic__5996
-logic__9544: logic__2539
-logic__6656: logic__6656
-reg__612: reg__612
-case__479: case__479
-logic__8223: logic__8223
-reg__1168: reg__1168
-reg__644: reg__644
-case__855: case__855
-logic__266: logic__266
-logic__1282: logic__1282
-reg__860: reg__860
-logic__3881: logic__3881
-logic__8709: logic__8709
-logic__7113: logic__7113
-reg__1550: reg__856
-logic__8212: logic__8212
-logic__1340: logic__1340
-case__1080: case__1080
-reg__803: reg__803
-logic__7419: logic__7419
-logic__1929: logic__1929
-logic__1466: logic__1466
-reg__130: reg__130
-logic__9182: logic__9182
-logic__3966: logic__3966
-logic__2939: logic__2939
-case__30: case__30
-dsp48e2__29: dsp48e2__29
-logic__3906: logic__3906
-logic__5515: logic__5515
-logic__6578: logic__6578
-logic__4915: logic__4915
-reg__1279: reg__1279
-addsub__6: addsub__6
-logic__1542: logic__1542
-muxpart__222: muxpart__222
-logic__6820: logic__6820
-logic__5992: logic__5992
-logic__8129: logic__8129
-case__579: case__579
-reg__794: reg__794
-case__442: case__442
-logic__3077: logic__3077
-case__1205: case__1205
-reg__899: reg__899
-logic__3330: logic__3330
-logic__1004: logic__1004
-logic__897: logic__897
-logic__6644: logic__6644
-reg__1238: reg__1238
-logic__5742: logic__5742
-reg__1101: reg__1101
-datapath__574: datapath__574
-logic__4410: logic__4410
-logic__5126: logic__5126
-datapath__552: datapath__552
-reg__474: reg__474
-reg__534: reg__534
-reg__748: reg__748
-case__1079: case__1079
-case__457: case__457
-case__1228: case__1228
-logic__7221: logic__7221
-reg__185: reg__185
-reg__51: reg__51
-logic__1905: logic__1905
-reg__1192: reg__1192
-logic__8686: logic__8686
-logic__139: logic__139
-logic__997: logic__997
-FPU__GB1: FPU__GB1
-case__1086: case__1086
-logic__3972: logic__3972
-logic__7996: logic__7996
-case__353: case__353
-sync__6: sync
-logic__4819: logic__4819
-reg__956: reg__956
-logic__798: logic__798
-logic__6677: logic__6677
-logic__3100: logic__3100
-case__812: case__812
-reg__1480: reg__908
-logic__6528: logic__6528
-reg__1431: reg__1216
-logic__7753: logic__7753
-logic__7069: logic__7069
-case__1021: case__1021
-datapath__691: datapath__691
-logic__3514: logic__3514
-logic__8929: logic__8929
-AsyncValidSync__9: AsyncValidSync
-case__260: case__260
-case__203: case__203
-muxpart__80: muxpart__80
-muxpart__212: muxpart__212
-logic__8943: logic__8943
-reg__270: reg__270
-case__1138: case__1138
-logic__4523: logic__4523
-case__779: case__779
-logic__8263: logic__8263
-reg__1432: reg__1216
-logic__5524: logic__5524
-logic__8122: logic__8122
-reg__1277: reg__1277
-datapath__23: datapath__23
-logic__101: logic__101
-logic__7053: logic__7053
-case__909: case__909
-logic__7759: logic__7759
-logic__1144: logic__1144
-datapath__357: datapath__357
-logic__5090: logic__5090
-reg__30: reg__30
-logic__3691: logic__3691
-logic__7117: logic__7117
-logic__2482: logic__2482
-logic__6831: logic__6831
-logic__983: logic__983
-logic__943: logic__943
-datapath__642: datapath__642
-case__930: case__930
-logic__4981: logic__4981
-logic__3696: logic__3696
-logic__9506: logic__4662
-case__1141: case__1141
-muxpart__201: muxpart__201
-signinv__2: signinv__2
-case__174: case__174
-logic__7048: logic__7048
-datapath__219: datapath__219
-reg__504: reg__504
-logic__1525: logic__1525
-muxpart__376: muxpart__376
-muxpart__210: muxpart__210
-logic__7168: logic__7168
-logic__8439: logic__8439
-case__369: case__369
-logic__5866: logic__5866
-logic__2: logic__2
-logic__7216: logic__7216
-logic__957: logic__957
-keep__5: keep__5
-logic__9655: logic__1120
-case__209: case__209
-logic__4982: logic__4982
-reg__262: reg__262
-datapath__144: datapath__144
-datapath__401: datapath__401
-case__881: case__881
-datapath__529: datapath__529
-logic__1488: logic__1488
-logic__5731: logic__5731
-AsyncResetSynchronizerPrimitiveShiftReg_d3_i0__20: AsyncResetSynchronizerPrimitiveShiftReg_d3_i0
-case__959: case__959
-logic__2894: logic__2894
-counter: counter
-logic__1754: logic__1754
-logic__3686: logic__3686
-logic__5730: logic__5730
-logic__9598: logic__8794
-case__551: case__551
-logic__7377: logic__7377
-datapath__210: datapath__210
-case__374: case__374
-logic__5471: logic__5471
-datapath__341: datapath__341
-logic__8434: logic__8434
-reg__1037: reg__1037
-logic__8531: logic__8531
-logic__2689: logic__2689
-reg__1470: reg__906
-case__1232: case__1232
-reg__219: reg__219
-datapath__759: datapath__685
-logic__7038: logic__7038
-logic__1841: logic__1841
-logic__6685: logic__6685
-logic__5198: logic__5198
-muxpart__69: muxpart__69
-logic__5658: logic__5658
-dsp48e2__10: dsp48e2__10
-case__947: case__947
-reg__641: reg__641
-logic__5318: logic__5318
-case__162: case__162
-reg__1381: reg__1381
-logic__398: logic__398
-reg__983: reg__983
-case__368: case__368
-datapath__375: datapath__375
-reg__493: reg__493
-logic__5294: logic__5294
-datapath__380: datapath__380
-reg__715: reg__715
-logic__5558: logic__5558
-dsp48e2__20: dsp48e2__20
-case__876: case__876
-logic__8180: logic__8180
-case__1708: case__728
-logic__6187: logic__6187
-rom__2: rom__2
-logic__3782: logic__3782
-logic__1840: logic__1840
-logic__785: logic__785
-reg__1242: reg__1242
-logic__9205: logic__9205
-reg__352: reg__352
-case__651: case__651
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/82910060.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/82910060.rtd
deleted file mode 100644
index da4d53a..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/82910060.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/82910260.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/82910260.rtd
deleted file mode 100644
index 9209dc5..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/82910260.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/82910E00.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/82910E00.rtd
deleted file mode 100644
index 7626917..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/82910E00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/8395DBA0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/8395DBA0.rtd
deleted file mode 100644
index 059c6f7..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/8395DBA0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/CA7D28A0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/CA7D28A0.rtd
deleted file mode 100644
index 63d7b99..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/CA7D28A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/CA7D3D00.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/CA7D3D00.rtd
deleted file mode 100644
index 27d8d36..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/CA7D3D00.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/CC7B28E0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/CC7B28E0.rtd
deleted file mode 100644
index 96b0cb6..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/CC7B28E0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE4E1080.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE4E1080.rtd
deleted file mode 100644
index 768710b..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE4E1080.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE4E10A0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE4E10A0.rtd
deleted file mode 100644
index e3a5e2b..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE4E10A0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE4E19C0.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE4E19C0.rtd
deleted file mode 100644
index 2b7b268..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE4E19C0.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE51A320.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE51A320.rtd
deleted file mode 100644
index 50f8d25..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/EE51A320.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/design.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/design.rtd
deleted file mode 100644
index ac5acb4..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/design.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/files.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/files.rtd
deleted file mode 100644
index 3f4f6d5..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/files.rtd
+++ /dev/null
@@ -1,13 +0,0 @@
-design.rtd
-straps.rtd
-82910060.rtd
-82910260.rtd
-82910E00.rtd
-EE51A320.rtd
-EE4E19C0.rtd
-EE4E10A0.rtd
-CA7D28A0.rtd
-CA7D3D00.rtd
-EE4E1080.rtd
-CC7B28E0.rtd
-8395DBA0.rtd
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/straps.rtd b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/straps.rtd
deleted file mode 100644
index 2a3ba9a..0000000
Binary files a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/t/straps.rtd and /dev/null differ
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/topModuleToGenome.map b/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/topModuleToGenome.map
deleted file mode 100644
index 421e289..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/3125184697/u/topModuleToGenome.map
+++ /dev/null
@@ -1,10 +0,0 @@
-APBGpsBlock: APBGpsBlock__GC0, tracking_wrapper,
-TLToAPB: TLToAPB,
-HierarchicalElementResetDomain: RocketTile,
-TilePRCIDomain: TilePRCIDomain__GC0, HierarchicalElementResetDomain,
-DCache: DCache,
-tracking_wrapper: tracking_wrapper,
-RocketTile: RocketTile__GCB0, FPU, DCache,
-FPGAGPSClockSinkDomain: TLToAPB, APBGpsBlock,
-VCU118RocketSystem: VCU118RocketSystem__GC0, FPGAGPSClockSinkDomain, TilePRCIDomain,
-FPU: FPU__GB2, FPU__GB1, FPU__GB0,
diff --git a/.Xil/Vivado-818686-ankalab04/incrSyn/soln.nlo b/.Xil/Vivado-818686-ankalab04/incrSyn/soln.nlo
deleted file mode 100644
index 13af484..0000000
--- a/.Xil/Vivado-818686-ankalab04/incrSyn/soln.nlo
+++ /dev/null
@@ -1 +0,0 @@
-1 -2
diff --git a/.Xil/Vivado-818686-ankalab04/wt/project.wpc b/.Xil/Vivado-818686-ankalab04/wt/project.wpc
deleted file mode 100644
index 834da22..0000000
--- a/.Xil/Vivado-818686-ankalab04/wt/project.wpc
+++ /dev/null
@@ -1,3 +0,0 @@
-version:1
-6d6f64655f636f756e7465727c42617463684d6f6465:1
-eof:
diff --git a/.Xil/Vivado-818686-ankalab04/wt/synthesis.wdf b/.Xil/Vivado-818686-ankalab04/wt/synthesis.wdf
deleted file mode 100644
index d700fa2..0000000
--- a/.Xil/Vivado-818686-ankalab04/wt/synthesis.wdf
+++ /dev/null
@@ -1,52 +0,0 @@
-version:1
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863767539702d666c6761323130342d324c2d65:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:7663753131385f726f636b65745f746f70:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d53594e544845534953:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7668646c5f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66696c65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f77:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f775f73657474696e6773:64656661756c743a3a6e6f6e65:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c75745f63617363616465:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d676c6f62616c5f726574696d696e67:64656661756c743a3a6175746f:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30323a323773:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:353136372e3139394d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3331332e3934394d42:00:00
-eof:211359638
diff --git a/.Xil/Vivado-818686-ankalab04/wt/synthesis_details.wdf b/.Xil/Vivado-818686-ankalab04/wt/synthesis_details.wdf
deleted file mode 100644
index 78f8d66..0000000
--- a/.Xil/Vivado-818686-ankalab04/wt/synthesis_details.wdf
+++ /dev/null
@@ -1,3 +0,0 @@
-version:1
-73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
-eof:2511430288
diff --git a/.Xil/Vivado-90878-onur/.lpr b/.Xil/Vivado-90878-onur/.lpr
deleted file mode 100644
index 4922431..0000000
--- a/.Xil/Vivado-90878-onur/.lpr
+++ /dev/null
@@ -1,9 +0,0 @@
-
-
-
-
-
-
-
-
-
diff --git a/.Xil/genesys2_eth_phy_smoke_propImpl.xdc b/.Xil/genesys2_eth_phy_smoke_propImpl.xdc
deleted file mode 100644
index e8b53d9..0000000
--- a/.Xil/genesys2_eth_phy_smoke_propImpl.xdc
+++ /dev/null
@@ -1,57 +0,0 @@
-set_property SRC_FILE_INFO {cfile:/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_eth_phy_smoke.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_eth_phy_smoke.xdc id:1} [current_design]
-set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AD12 [get_ports sysclk_p]
-set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AD11 [get_ports sysclk_n]
-set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN R19 [get_ports cpu_resetn]
-set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN T28 [get_ports {led[0]}]
-set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V19 [get_ports {led[1]}]
-set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U30 [get_ports {led[2]}]
-set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U29 [get_ports {led[3]}]
-set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V20 [get_ports {led[4]}]
-set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V26 [get_ports {led[5]}]
-set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W24 [get_ports {led[6]}]
-set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W23 [get_ports {led[7]}]
-set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AG10 [get_ports eth_rxck]
-set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AH11 [get_ports eth_rxctl]
-set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AJ14 [get_ports {eth_rxd[0]}]
-set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AH14 [get_ports {eth_rxd[1]}]
-set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK13 [get_ports {eth_rxd[2]}]
-set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AJ13 [get_ports {eth_rxd[3]}]
-set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AE10 [get_ports eth_txck]
-set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK14 [get_ports eth_txctl]
-set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AJ12 [get_ports {eth_txd[0]}]
-set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK11 [get_ports {eth_txd[1]}]
-set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AJ11 [get_ports {eth_txd[2]}]
-set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK10 [get_ports {eth_txd[3]}]
-set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AF12 [get_ports eth_mdc]
-set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AG12 [get_ports eth_mdio]
-set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AH24 [get_ports eth_phyrst_n]
-set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK16 [get_ports eth_int_b]
-set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK15 [get_ports eth_pme_b]
diff --git a/.Xil/genesys2_eth_reset_release_propImpl.xdc b/.Xil/genesys2_eth_reset_release_propImpl.xdc
deleted file mode 100644
index e8b53d9..0000000
--- a/.Xil/genesys2_eth_reset_release_propImpl.xdc
+++ /dev/null
@@ -1,57 +0,0 @@
-set_property SRC_FILE_INFO {cfile:/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_eth_phy_smoke.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_eth_phy_smoke.xdc id:1} [current_design]
-set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AD12 [get_ports sysclk_p]
-set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AD11 [get_ports sysclk_n]
-set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN R19 [get_ports cpu_resetn]
-set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN T28 [get_ports {led[0]}]
-set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V19 [get_ports {led[1]}]
-set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U30 [get_ports {led[2]}]
-set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U29 [get_ports {led[3]}]
-set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V20 [get_ports {led[4]}]
-set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V26 [get_ports {led[5]}]
-set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W24 [get_ports {led[6]}]
-set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W23 [get_ports {led[7]}]
-set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AG10 [get_ports eth_rxck]
-set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AH11 [get_ports eth_rxctl]
-set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AJ14 [get_ports {eth_rxd[0]}]
-set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AH14 [get_ports {eth_rxd[1]}]
-set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK13 [get_ports {eth_rxd[2]}]
-set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AJ13 [get_ports {eth_rxd[3]}]
-set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AE10 [get_ports eth_txck]
-set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK14 [get_ports eth_txctl]
-set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AJ12 [get_ports {eth_txd[0]}]
-set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK11 [get_ports {eth_txd[1]}]
-set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AJ11 [get_ports {eth_txd[2]}]
-set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK10 [get_ports {eth_txd[3]}]
-set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AF12 [get_ports eth_mdc]
-set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AG12 [get_ports eth_mdio]
-set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AH24 [get_ports eth_phyrst_n]
-set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK16 [get_ports eth_int_b]
-set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK15 [get_ports eth_pme_b]
diff --git a/.Xil/genesys2_rocket_top_propImpl.xdc b/.Xil/genesys2_rocket_top_propImpl.xdc
deleted file mode 100644
index 58d3a78..0000000
--- a/.Xil/genesys2_rocket_top_propImpl.xdc
+++ /dev/null
@@ -1,67 +0,0 @@
-set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_rocket.xdc id:1} [current_design]
-set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc id:2} [current_design]
-set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc id:3} [current_design]
-set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc id:4} [current_design]
-set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc id:5} [current_design]
-set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AD12 [get_ports sysclk_p]
-set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AD11 [get_ports sysclk_n]
-set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN R19 [get_ports cpu_resetn]
-set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN Y20 [get_ports uart_tx_in]
-set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN Y23 [get_ports uart_rx_out]
-set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN T28 [get_ports {led[0]}]
-set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V19 [get_ports {led[1]}]
-set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U30 [get_ports {led[2]}]
-set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U29 [get_ports {led[3]}]
-set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V20 [get_ports {led[4]}]
-set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V26 [get_ports {led[5]}]
-set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W24 [get_ports {led[6]}]
-set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W23 [get_ports {led[7]}]
-set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U19 [get_ports qspi_csn]
-set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN P24 [get_ports {qspi_d[0]}]
-set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN R25 [get_ports {qspi_d[1]}]
-set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN R20 [get_ports {qspi_d[2]}]
-set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN R21 [get_ports {qspi_d[3]}]
-set_property src_info {type:XDC file:2 line:13 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AC26 [get_ports pmod_spi_csn]
-set_property src_info {type:XDC file:2 line:14 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AJ27 [get_ports {pmod_spi_dq[0]}]
-set_property src_info {type:XDC file:2 line:15 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AH30 [get_ports {pmod_spi_dq[1]}]
-set_property src_info {type:XDC file:2 line:16 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK29 [get_ports pmod_spi_sck]
-set_property src_info {type:XDC file:2 line:17 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AD26 [get_ports {pmod_spi_dq[2]}]
-set_property src_info {type:XDC file:2 line:18 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AG30 [get_ports {pmod_spi_dq[3]}]
-set_property src_info {type:XDC file:3 line:6 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK30 [get_ports pmod_irq]
-set_property src_info {type:XDC file:4 line:8 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AK28 [get_ports gps_pps]
-set_property src_info {type:XDC file:5 line:4 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U27 [get_ports rf_clk_pmod]
-set_property src_info {type:XDC file:5 line:8 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U28 [get_ports {rf_data_pmod[0]}]
-set_property src_info {type:XDC file:5 line:9 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN T26 [get_ports {rf_data_pmod[1]}]
-set_property src_info {type:XDC file:5 line:10 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN T27 [get_ports {rf_data_pmod[2]}]
-set_property src_info {type:XDC file:5 line:11 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN T22 [get_ports {rf_data_pmod[3]}]
diff --git a/.Xil/gig_ethernet_pcs_pma_0_propImpl.xdc b/.Xil/gig_ethernet_pcs_pma_0_propImpl.xdc
deleted file mode 100644
index b7f5ecd..0000000
--- a/.Xil/gig_ethernet_pcs_pma_0_propImpl.xdc
+++ /dev/null
@@ -1,10 +0,0 @@
-set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/rocket/rocket-chip/.gen/sources_1/ip/gig_ethernet_pcs_pma_0/synth/gig_ethernet_pcs_pma_0.xdc rfile:../.gen/sources_1/ip/gig_ethernet_pcs_pma_0/synth/gig_ethernet_pcs_pma_0.xdc id:1 order:LATE scoped_inst:inst} [current_design]
-current_instance inst
-set_property src_info {type:SCOPED_XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]
-set_max_delay -from [get_cells -hier -filter {name =~ *rx_elastic_buffer_inst/wr_addr_*_reg[*]}] -to [get_pins -of [get_cells -hierarchical -filter {NAME =~ *reclock_wr_addrgray[*].sync_wr_addrgray/data_sync*}] -filter {REF_PIN_NAME =~ D}] 8 -datapath_only
-set_property src_info {type:SCOPED_XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
-set_max_delay -from [get_cells -hier -filter {name =~ *rx_elastic_buffer_inst/rd_addr_*_reg[*]}] -to [get_pins -of [get_cells -hierarchical -filter {NAME =~ *reclock_rd_addrgray[*].sync_rd_addrgray/data_sync*}] -filter {REF_PIN_NAME =~ D}] 8 -datapath_only
-set_property src_info {type:SCOPED_XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
-create_waiver -internal -scope -type CDC -id {CDC-1} -user "gig_ethernet_pcs_pma" -tags "11999" -desc "The CDC-1 warning is waived as this is within the LVDS_transiver module and safe to ignore" -from [get_pins -of [get_cells -hier -filter {name =~ */RAM*}] -filter {name =~ *CLK}] -to [get_pins -of [get_cells -hier -filter {name =~ */*x_elastic_buffer_inst/rd_data_reg[*]*}] -filter {name =~ *D}]
-set_property src_info {type:SCOPED_XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
-create_waiver -internal -scope -type CDC -id {CDC-10} -user "gig_ethernet_pcs_pma" -tags "11999" -desc "The CDC-10 warning is waived as this is within the LVDS_transiver module and safe to ignore" -from [get_pins -of [get_cells -hier -filter {name =~ */USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_reg*}] -filter {name =~ *C}] -to [get_pins -of [get_cells -hier -filter {name =~ */reset_sync1*}] -filter {name =~ *PRE}]
diff --git a/.Xil/vcu118_rocket_top_propImpl.xdc b/.Xil/vcu118_rocket_top_propImpl.xdc
deleted file mode 100644
index 08a936a..0000000
--- a/.Xil/vcu118_rocket_top_propImpl.xdc
+++ /dev/null
@@ -1,48 +0,0 @@
-set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/rocket/rocket-chip/hardware/fpga/vcu118/constraints/vcu118_rocket.xdc rfile:../hardware/fpga/vcu118/constraints/vcu118_rocket.xdc id:1} [current_design]
-set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/rocket/rocket-chip/hardware/fpga/vcu118/constraints/vcu118_ethernet.xdc rfile:../hardware/fpga/vcu118/constraints/vcu118_ethernet.xdc id:2} [current_design]
-set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN G31 [get_ports sysclk1_300_p]
-set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN F31 [get_ports sysclk1_300_n]
-set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN L19 [get_ports cpu_reset]
-set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN BB21 [get_ports rs232_uart_txd]
-set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AW25 [get_ports rs232_uart_rxd]
-set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AT32 [get_ports {led[0]}]
-set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AV34 [get_ports {led[1]}]
-set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AY30 [get_ports {led[2]}]
-set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN BB32 [get_ports {led[3]}]
-set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN BF32 [get_ports {led[4]}]
-set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AU37 [get_ports {led[5]}]
-set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AV36 [get_ports {led[6]}]
-set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN BA37 [get_ports {led[7]}]
-set_property src_info {type:XDC file:2 line:3 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AU24 [get_ports phy_sgmii_rx_p]
-set_property src_info {type:XDC file:2 line:4 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AV24 [get_ports phy_sgmii_rx_n]
-set_property src_info {type:XDC file:2 line:5 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AU21 [get_ports phy_sgmii_tx_p]
-set_property src_info {type:XDC file:2 line:6 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AV21 [get_ports phy_sgmii_tx_n]
-set_property src_info {type:XDC file:2 line:7 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AT22 [get_ports phy_sgmii_clk_p]
-set_property src_info {type:XDC file:2 line:8 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AU22 [get_ports phy_sgmii_clk_n]
-set_property src_info {type:XDC file:2 line:11 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN BA21 [get_ports phy_reset_n]
-set_property src_info {type:XDC file:2 line:12 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AR24 [get_ports phy_int_n]
-set_property src_info {type:XDC file:2 line:13 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AR23 [get_ports phy_mdio]
-set_property src_info {type:XDC file:2 line:14 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN AV23 [get_ports phy_mdc]
diff --git a/.gitignore b/.gitignore
index d855b3f..4e26477 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,6 +7,20 @@
# Generated build outputs.
/out/
/soc/out/
+/soc/software/*/build/
+/soc/software/gps_system/tests/test_*
+!/soc/software/gps_system/tests/test_*.c
+
+# Vivado transient work, logs, reports, and implementation checkpoints.
+.Xil/
+**/.Xil/
+vivado*.jou
+vivado*.log
+vivado_pid*.str
+clockInfo.txt
+/targets/fpga/*/out/logs/
+/targets/fpga/*/out/reports/
+/targets/fpga/*/out/build/checkpoints/
# Python runtime caches and privacy-sensitive raw board captures.
__pycache__/
diff --git a/clockInfo.txt b/clockInfo.txt
deleted file mode 100644
index 24ffbc0..0000000
--- a/clockInfo.txt
+++ /dev/null
@@ -1,10 +0,0 @@
--------------------------------------
-| Tool Version : Vivado v.2025.2
-| Date : Thu Aug 6 21:30:24 2026
-| Host : ankalab04
-| Design : design_1
-| Device : xc7k325t-ffg900-2--
--------------------------------------
-
-For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
-
diff --git a/targets/fpga/genesys2/out/build/checkpoints/.Xil/Vivado-2451337-ankalab04/.lpr b/targets/fpga/genesys2/out/build/checkpoints/.Xil/Vivado-2451337-ankalab04/.lpr
deleted file mode 100644
index 4922431..0000000
--- a/targets/fpga/genesys2/out/build/checkpoints/.Xil/Vivado-2451337-ankalab04/.lpr
+++ /dev/null
@@ -1,9 +0,0 @@
-
-
-
-
-
-
-
-
-
diff --git a/targets/fpga/genesys2/out/build/checkpoints/post_opt.dcp b/targets/fpga/genesys2/out/build/checkpoints/post_opt.dcp
deleted file mode 100644
index adef5b6..0000000
Binary files a/targets/fpga/genesys2/out/build/checkpoints/post_opt.dcp and /dev/null differ
diff --git a/targets/fpga/genesys2/out/build/checkpoints/post_phys_opt.dcp b/targets/fpga/genesys2/out/build/checkpoints/post_phys_opt.dcp
deleted file mode 100644
index f72dded..0000000
Binary files a/targets/fpga/genesys2/out/build/checkpoints/post_phys_opt.dcp and /dev/null differ
diff --git a/targets/fpga/genesys2/out/build/checkpoints/post_place.dcp b/targets/fpga/genesys2/out/build/checkpoints/post_place.dcp
deleted file mode 100644
index 26d6bd1..0000000
Binary files a/targets/fpga/genesys2/out/build/checkpoints/post_place.dcp and /dev/null differ
diff --git a/targets/fpga/genesys2/out/build/checkpoints/post_route.dcp b/targets/fpga/genesys2/out/build/checkpoints/post_route.dcp
deleted file mode 100644
index c4e11fa..0000000
Binary files a/targets/fpga/genesys2/out/build/checkpoints/post_route.dcp and /dev/null differ
diff --git a/targets/fpga/genesys2/out/build/checkpoints/post_synth.dcp b/targets/fpga/genesys2/out/build/checkpoints/post_synth.dcp
deleted file mode 100644
index db7b264..0000000
Binary files a/targets/fpga/genesys2/out/build/checkpoints/post_synth.dcp and /dev/null differ
diff --git a/targets/fpga/genesys2/out/build/checkpoints/vivado.jou b/targets/fpga/genesys2/out/build/checkpoints/vivado.jou
deleted file mode 100644
index b7b1913..0000000
--- a/targets/fpga/genesys2/out/build/checkpoints/vivado.jou
+++ /dev/null
@@ -1,31 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Mon Jul 6 19:04:30 2026
-# Process ID : 2452434
-# Current directory : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints
-# Command line : vivado
-# Log file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.log
-# Journal file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.jou
-# Running On : ankalab04
-# Platform : Ubuntu
-# Operating System : Ubuntu 24.04.4 LTS
-# Processor Detail : AMD Ryzen 9 9950X 16-Core Processor
-# CPU Frequency : 5630.841 MHz
-# CPU Physical cores : 16
-# CPU Logical cores : 32
-# Host memory : 64914 MB
-# Swap memory : 8589 MB
-# Total Virtual : 73504 MB
-# Available Virtual : 56169 MB
-#-----------------------------------------------------------
-start_gui
-open_hw_manager
-connect_hw_server -allow_non_jtag
-disconnect_hw_server localhost:3121
-connect_hw_server -allow_non_jtag
-open_hw_target
-current_hw_device [get_hw_devices xcvu9p_0]
-refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xcvu9p_0] 0]
diff --git a/targets/fpga/genesys2/out/build/checkpoints/vivado.log b/targets/fpga/genesys2/out/build/checkpoints/vivado.log
deleted file mode 100644
index 6542932..0000000
--- a/targets/fpga/genesys2/out/build/checkpoints/vivado.log
+++ /dev/null
@@ -1,73 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Mon Jul 6 19:04:30 2026
-# Process ID : 2452434
-# Current directory : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints
-# Command line : vivado
-# Log file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.log
-# Journal file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.jou
-# Running On : ankalab04
-# Platform : Ubuntu
-# Operating System : Ubuntu 24.04.4 LTS
-# Processor Detail : AMD Ryzen 9 9950X 16-Core Processor
-# CPU Frequency : 5630.841 MHz
-# CPU Physical cores : 16
-# CPU Logical cores : 32
-# Host memory : 64914 MB
-# Swap memory : 8589 MB
-# Total Virtual : 73504 MB
-# Available Virtual : 56169 MB
-#-----------------------------------------------------------
-start_gui
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vrk160:part0:1.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vrk160/1.0/board.xml as part xcvr1602-vsva2488-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vrk160:part0:1.1 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vrk160/1.1/board.xml as part xcvr1602-vsva2488-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
-open_hw_manager
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.2/data/ip'.
-connect_hw_server -allow_non_jtag
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
- Targets(s) ", jsn-JTAG-SMT2NC-210308BA5D44" may be locked by another hw_server.
-disconnect_hw_server localhost:3121
-connect_hw_server -allow_non_jtag
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308BA5D44
-current_hw_device [get_hw_devices xcvu9p_0]
-refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xcvu9p_0] 0]
-INFO: [Labtools 27-1435] Device xcvu9p (JTAG device index = 0) is not programmed (DONE status = 0).
-exit
-INFO: [Common 17-206] Exiting Vivado at Mon Jul 6 19:08:25 2026...
diff --git a/targets/fpga/genesys2/out/build/checkpoints/vivado_1994145.backup.jou b/targets/fpga/genesys2/out/build/checkpoints/vivado_1994145.backup.jou
deleted file mode 100644
index 648139d..0000000
--- a/targets/fpga/genesys2/out/build/checkpoints/vivado_1994145.backup.jou
+++ /dev/null
@@ -1,25 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Mon Jul 6 18:29:26 2026
-# Process ID : 1994145
-# Current directory : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints
-# Command line : vivado post_route.dcp
-# Log file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.log
-# Journal file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.jou
-# Running On : ankalab04
-# Platform : Ubuntu
-# Operating System : Ubuntu 24.04.4 LTS
-# Processor Detail : AMD Ryzen 9 9950X 16-Core Processor
-# CPU Frequency : 2982.259 MHz
-# CPU Physical cores : 16
-# CPU Logical cores : 32
-# Host memory : 64914 MB
-# Swap memory : 8589 MB
-# Total Virtual : 73504 MB
-# Available Virtual : 51146 MB
-#-----------------------------------------------------------
-start_gui
-open_checkpoint /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_route.dcp
diff --git a/targets/fpga/genesys2/out/build/checkpoints/vivado_1994145.backup.log b/targets/fpga/genesys2/out/build/checkpoints/vivado_1994145.backup.log
deleted file mode 100644
index f0c74a5..0000000
--- a/targets/fpga/genesys2/out/build/checkpoints/vivado_1994145.backup.log
+++ /dev/null
@@ -1,75 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Mon Jul 6 18:29:26 2026
-# Process ID : 1994145
-# Current directory : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints
-# Command line : vivado post_route.dcp
-# Log file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.log
-# Journal file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.jou
-# Running On : ankalab04
-# Platform : Ubuntu
-# Operating System : Ubuntu 24.04.4 LTS
-# Processor Detail : AMD Ryzen 9 9950X 16-Core Processor
-# CPU Frequency : 2982.259 MHz
-# CPU Physical cores : 16
-# CPU Logical cores : 32
-# Host memory : 64914 MB
-# Swap memory : 8589 MB
-# Total Virtual : 73504 MB
-# Available Virtual : 51146 MB
-#-----------------------------------------------------------
-start_gui
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vrk160:part0:1.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vrk160/1.0/board.xml as part xcvr1602-vsva2488-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vrk160:part0:1.1 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vrk160/1.1/board.xml as part xcvr1602-vsva2488-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
-open_checkpoint /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_route.dcp
-Command: open_checkpoint /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_route.dcp
-
-Starting open_checkpoint Task
-
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 9958.176 ; gain = 0.000 ; free physical = 14093 ; free virtual = 47871
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.2/data/ip'.
-INFO: [Device 21-403] Loading part xc7k325tffg900-2
-Netlist sorting complete. Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.35 . Memory (MB): peak = 10328.926 ; gain = 0.055 ; free physical = 13715 ; free virtual = 47505
-INFO: [Netlist 29-17] Analyzing 8164 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-479] Netlist was created with Vivado 2025.2
-INFO: [Project 1-570] Preparing netlist for logic optimization
-Read ShapeDB Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 10473.852 ; gain = 11.492 ; free physical = 13564 ; free virtual = 47354
-INFO: [Timing 38-478] Restoring timing data from binary archive.
-INFO: [Timing 38-479] Binary timing data restore complete.
-INFO: [Project 1-856] Restoring constraints from binary archive.
-INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are:
- general.maxThreads
-INFO: [Project 1-853] Binary constraint restore complete.
-INFO: [Designutils 20-5722] Start Reading Physical Databases.
-Reading placement.
-Read Netlist Cache: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 11228.203 ; gain = 10.000 ; free physical = 12830 ; free virtual = 46621
-Reading placer database...
-Read Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 11228.203 ; gain = 0.000 ; free physical = 12830 ; free virtual = 46621
-Read PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 11228.203 ; gain = 0.000 ; free physical = 12830 ; free virtual = 46621
-Read placeStorage: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.88 . Memory (MB): peak = 11268.602 ; gain = 40.398 ; free physical = 12796 ; free virtual = 46587
-Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 11268.602 ; gain = 0.000 ; free physical = 12796 ; free virtual = 46587
-Reading routing.
-Read RouteStorage: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.29 . Memory (MB): peak = 11324.336 ; gain = 55.734 ; free physical = 12747 ; free virtual = 46537
-Read Physdb Files: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 11324.336 ; gain = 106.133 ; free physical = 12747 ; free virtual = 46537
-Restored from archive | CPU: 1.840000 secs | Memory: 91.202095 MB |
-Finished XDEF File Restore: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 11324.336 ; gain = 106.133 ; free physical = 12747 ; free virtual = 46537
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 11382.406 ; gain = 0.000 ; free physical = 12685 ; free virtual = 46475
-INFO: [Project 1-111] Unisim Transformation Summary:
- A total of 235 instances were transformed.
- IOBUF => IOBUF (IBUF, OBUFT): 4 instances
- RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 222 instances
- RAM32X1D => RAM32X1D (RAMD32(x2)): 9 instances
-
-INFO: [Project 1-604] Checkpoint was created with Vivado v2025.2 (64-bit) build 6299465
-open_checkpoint: Time (s): cpu = 00:00:28 ; elapsed = 00:00:13 . Memory (MB): peak = 12150.938 ; gain = 2205.730 ; free physical = 12005 ; free virtual = 45805
-exit
-INFO: [Common 17-206] Exiting Vivado at Mon Jul 6 18:37:19 2026...
diff --git a/targets/fpga/genesys2/out/build/checkpoints/vivado_2451337.backup.jou b/targets/fpga/genesys2/out/build/checkpoints/vivado_2451337.backup.jou
deleted file mode 100644
index 2a21c0a..0000000
--- a/targets/fpga/genesys2/out/build/checkpoints/vivado_2451337.backup.jou
+++ /dev/null
@@ -1,25 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Mon Jul 6 19:03:31 2026
-# Process ID : 2451337
-# Current directory : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints
-# Command line : vivado
-# Log file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.log
-# Journal file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.jou
-# Running On : ankalab04
-# Platform : Ubuntu
-# Operating System : Ubuntu 24.04.4 LTS
-# Processor Detail : AMD Ryzen 9 9950X 16-Core Processor
-# CPU Frequency : 5672.241 MHz
-# CPU Physical cores : 16
-# CPU Logical cores : 32
-# Host memory : 64914 MB
-# Swap memory : 8589 MB
-# Total Virtual : 73504 MB
-# Available Virtual : 50403 MB
-#-----------------------------------------------------------
-start_gui
-open_hw_manager
diff --git a/targets/fpga/genesys2/out/build/checkpoints/vivado_2451337.backup.log b/targets/fpga/genesys2/out/build/checkpoints/vivado_2451337.backup.log
deleted file mode 100644
index bcd217b..0000000
--- a/targets/fpga/genesys2/out/build/checkpoints/vivado_2451337.backup.log
+++ /dev/null
@@ -1,33 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Mon Jul 6 19:03:31 2026
-# Process ID : 2451337
-# Current directory : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints
-# Command line : vivado
-# Log file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.log
-# Journal file : /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.jou
-# Running On : ankalab04
-# Platform : Ubuntu
-# Operating System : Ubuntu 24.04.4 LTS
-# Processor Detail : AMD Ryzen 9 9950X 16-Core Processor
-# CPU Frequency : 5672.241 MHz
-# CPU Physical cores : 16
-# CPU Logical cores : 32
-# Host memory : 64914 MB
-# Swap memory : 8589 MB
-# Total Virtual : 73504 MB
-# Available Virtual : 50403 MB
-#-----------------------------------------------------------
-start_gui
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vrk160:part0:1.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vrk160/1.0/board.xml as part xcvr1602-vsva2488-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vrk160:part0:1.1 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vrk160/1.1/board.xml as part xcvr1602-vsva2488-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/2025.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
-open_hw_manager
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.2/data/ip'.
diff --git a/targets/fpga/genesys2/out/build/checkpoints/vivado_pid2451337.str b/targets/fpga/genesys2/out/build/checkpoints/vivado_pid2451337.str
deleted file mode 100644
index c667227..0000000
--- a/targets/fpga/genesys2/out/build/checkpoints/vivado_pid2451337.str
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
-
-AMD Vivado v2025.2 (64-bit) [Major: 2025, Minor: 2]
-SW Build: 6299465 on Fri Nov 14 12:34:56 MST 2025
-IP Build: 6300035 on Fri Nov 14 10:48:45 MST 2025
-IP Build: 6300035 on Fri Nov 14 10:48:45 MST 2025
-
-Process ID (PID): 2451337
-License: Customer
-Mode: GUI Mode
-
-Current time: Mon Jul 06 19:03:39 TRT 2026
-Time zone: Turkey Time (Europe/Istanbul)
-
-OS: Ubuntu
-OS Version: 6.17.0-35-generic
-OS Architecture: amd64
-Available processors (cores): 32
-LSB Release Description: DISTRIB_ID=Ubuntu
-
-Display: 10.0
-Screen size: 3440x1440
-Local screen bounds: x = 0, y = 32, width = 3440, height = 1358
-Screen resolution (DPI): 100
-Available screens: 1
-Default font: family=Dialog,name=Dialog,style=plain,size=12
-Scale size: 12
-OS font scaling: 100%
-Anti-Alias Enabled: false
-
-Java version: 21.0.5 64-bit
-
-Java home: /tools/Xilinx/2025.2/tps/lnx64/jre21.0.5_11
-Java executable: /tools/Xilinx/2025.2/tps/lnx64/jre21.0.5_11/bin/java
-Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.uiScale.enabled=false, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, -XX:+UseStringDeduplication, -XX:MaxGCPauseMillis=200, -XX:ParallelGCThreads=4, -XX:+ParallelRefProcEnabled, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/java.awt.event=ALL-UNNAMED, --add-opens=java.desktop/sun.awt.X11=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.base/java.nio=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.table=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.desktop/sun.awt.shell=ALL-UNNAMED, --add-exports=java.base/sun.security.action=ALL-UNNAMED, --add-exports=java.desktop/sun.font=ALL-UNNAMED, --add-opens=java.desktop/sun.awt.X11=ALL-UNNAMED, -XX:NewSize=80m, -XX:MaxNewSize=80m, -Xms812m, -Xmx6144m, -Xss10m, -Xrs]
-Java initial memory (-Xms): 812 MB
-Java maximum memory (-Xmx): 6 GB
-
-User name: ankaoc
-User home directory: /home/ankaoc
-User working directory: /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints
-User country: US
-User language: en
-User locale: en_US
-
-RDI_BASEROOT: /tools/Xilinx/2025.2
-HDI_APPROOT: /tools/Xilinx/2025.2/Vivado
-RDI_DATADIR: /tools/Xilinx/2025.2/SharedData/data:/tools/Xilinx/2025.2/data
-RDI_BINDIR: /tools/Xilinx/2025.2/Vivado/bin
-
-Vivado preferences file: /home/ankaoc/.Xilinx/Vivado/2025.2/vivado.xml
-Vivado preferences directory: /home/ankaoc/.Xilinx/Vivado/2025.2/
-Vivado layouts directory: /home/ankaoc/.Xilinx/Vivado/2025.2/data/layouts
-PlanAhead jar file: /tools/Xilinx/2025.2/Vivado/lib/classes/planAhead.jar
-Vivado log file: /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.log
-Vivado journal file: /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/vivado.jou
-Engine tmp dir: ./.Xil/Vivado-2451337-ankalab04
-Non-Default Parameters: []
-
-Xilinx & AMD Environment Variables
---------------------------------------------------------------------------------------------
-GNOME_SHELL_SESSION_MODE: ubuntu
-PYENV_SHELL: bash
-RDI_APPROOT: /tools/Xilinx/2025.2/Vivado
-RDI_BASEROOT: /tools/Xilinx/2025.2
-RDI_BINROOT: /tools/Xilinx/2025.2/Vivado/bin
-RDI_BUILD: yes
-RDI_DATADIR: /tools/Xilinx/2025.2/SharedData/data:/tools/Xilinx/2025.2/data
-RDI_INSTALLROOT: /tools/Xilinx
-RDI_INSTALLVER: Vivado
-RDI_JAVA_PLATFORM:
-RDI_JAVA_VERSION: 21.0.5_11
-RDI_LIBDIR: /tools/Xilinx/2025.2/Vivado/lib/lnx64.o/Ubuntu/24:/tools/Xilinx/2025.2/Vivado/lib/lnx64.o/Ubuntu:/tools/Xilinx/2025.2/Vivado/lib/lnx64.o
-RDI_OPT_EXT: .o
-RDI_PATCHROOT:
-RDI_PLATFORM: lnx64
-RDI_PREPEND_PATH: /tools/Xilinx/2025.2/Vitis/bin:/tools/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64
-RDI_PROG: /tools/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/vivado
-RDI_SESSION_INFO: /home/ankaoc/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints:ankalab04_1783353811_2451247
-RDI_SHARED_DATA: /tools/Xilinx/2025.2/SharedData/data
-RDI_TPS_ROOT: /tools/Xilinx/2025.2/Vivado/tps/lnx64
-RDI_USE_JDK21: True
-SHELL: /bin/bash
-XILINX: /tools/Xilinx/2025.2/Vivado/ids_lite/ISE
-XILINX_DSP: /tools/Xilinx/2025.2/Vivado/ids_lite/ISE
-XILINX_HLS: /tools/Xilinx/2025.2/Vitis
-XILINX_PLANAHEAD: /tools/Xilinx/2025.2/Vivado
-XILINX_SDK: /tools/Xilinx/2025.2/Vitis
-XILINX_VITIS: /tools/Xilinx/2025.2/Vitis
-XILINX_VIVADO: /tools/Xilinx/2025.2/Vivado
-
-
-GUI allocated memory: 812 MB
-GUI max memory: 6,144 MB
-Engine allocated memory: 2,014 MB
-
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-
-*/
-
-// TclEventType: START_GUI
-// Tcl Message: start_gui
-selectMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ah (PAResourceItoN.MainMenuMgr_TOOLS, Tools)
-// HMemoryUtils.trashcanNow. Engine heap size: 2,017 MB. GUI used memory: 68 MB. Current time: 7/6/26, 7:03:40 PM TRT
-dismissMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ah (PAResourceItoN.MainMenuMgr_TOOLS, Tools)
-selectMenu(PAResourceItoN.MainMenuMgr_WINDOW, "Window"); // ah (PAResourceItoN.MainMenuMgr_WINDOW, Window)
-dismissMenu(PAResourceItoN.MainMenuMgr_WINDOW, "Window"); // ah (PAResourceItoN.MainMenuMgr_WINDOW, Window)
-selectMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ah (PAResourceItoN.MainMenuMgr_TOOLS, Tools)
-dismissMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ah (PAResourceItoN.MainMenuMgr_TOOLS, Tools)
-selectMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ah (PAResourceItoN.MainMenuMgr_FLOW, Flow)
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_OPEN_RESULTS, "Open Static Simulation..."); // ap (PAResourceCommand.PACommandNames_SIMULATION_OPEN_RESULTS, simulation_open_static_menu)
-dismissMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ah (PAResourceItoN.MainMenuMgr_FLOW, Flow)
-// Run Command: PAResourceCommand.PACommandNames_SIMULATION_OPEN_RESULTS
-dismissFileChooser();
-selectMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ah (PAResourceItoN.MainMenuMgr_FLOW, Flow)
-selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_OPEN_RESULTS, "Open Static Simulation..."); // ap (PAResourceCommand.PACommandNames_SIMULATION_OPEN_RESULTS, simulation_open_static_menu)
-dismissMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ah (PAResourceItoN.MainMenuMgr_FLOW, Flow)
-dismissFileChooser();
-selectMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ah (PAResourceItoN.MainMenuMgr_TOOLS, Tools)
-dismissMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ah (PAResourceItoN.MainMenuMgr_TOOLS, Tools)
-selectMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ah (PAResourceItoN.MainMenuMgr_FLOW, Flow)
-dismissMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ah (PAResourceItoN.MainMenuMgr_FLOW, Flow)
-selectMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ah (PAResourceItoN.MainMenuMgr_TOOLS, Tools)
-dismissMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ah (PAResourceItoN.MainMenuMgr_TOOLS, Tools)
-selectMenu(PAResourceItoN.MainMenuMgr_WINDOW, "Window"); // ah (PAResourceItoN.MainMenuMgr_WINDOW, Window)
-dismissMenu(PAResourceItoN.MainMenuMgr_WINDOW, "Window"); // ah (PAResourceItoN.MainMenuMgr_WINDOW, Window)
-selectMenu(PAResourceItoN.MainMenuMgr_HELP, "Help"); // ah (PAResourceItoN.MainMenuMgr_HELP, Help)
-dismissMenu(PAResourceItoN.MainMenuMgr_HELP, "Help"); // ah (PAResourceItoN.MainMenuMgr_HELP, Help)
-selectMenu(PAResourceItoN.MainMenuMgr_WINDOW, "Window"); // ah (PAResourceItoN.MainMenuMgr_WINDOW, Window)
-selectMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ah (PAResourceItoN.MainMenuMgr_TOOLS, Tools)
-dismissMenu(PAResourceItoN.MainMenuMgr_TOOLS, "Tools"); // ah (PAResourceItoN.MainMenuMgr_TOOLS, Tools)
-selectMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ah (PAResourceItoN.MainMenuMgr_FLOW, Flow)
-dismissMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ah (PAResourceItoN.MainMenuMgr_FLOW, Flow)
-selectMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // ah (PAResourceItoN.MainMenuMgr_FILE, File)
-dismissMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // ah (PAResourceItoN.MainMenuMgr_FILE, File)
-selectMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ah (PAResourceItoN.MainMenuMgr_FLOW, Flow)
-selectMenuItem(PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER, "Open Hardware Manager"); // ap (PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER, open_hardware_session_menu)
-dismissMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // ah (PAResourceItoN.MainMenuMgr_FLOW, Flow)
-// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
-// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes'
-// Tcl (Dont Echo) Command: 'load_features labtools'
-// TclEventType: LOAD_FEATURE
-// TclEventType: DEBUG_PROBE_SET_CHANGE
-// TclEventType: FLOW_ADDED
-// TclEventType: FILE_SET_NEW
-// TclEventType: RUN_ADD
-// TclEventType: RUN_CURRENT
-// TclEventType: PROJECT_DASHBOARD_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
-// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
-// TclEventType: PROJECT_NEW
-// [GUI Memory]: 93 MB (+94698kb) [00:00:27]
-// [Engine Memory]: 2,040 MB (+1988057kb) [00:00:27]
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// HMemoryUtils.trashcanNow. Engine heap size: 2,078 MB. GUI used memory: 74 MB. Current time: 7/6/26, 7:04:00 PM TRT
-// Tcl Message: open_hw_manager
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.2/data/ip'.
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// [GUI Memory]: 98 MB (+284kb) [00:00:28]
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// [GUI Memory]: 103 MB (+582kb) [00:00:28]
-// TclEventType: FILE_SET_OPTIONS_CHANGE
-// TclEventType: HW_SESSION_OPEN
-dismissDialog("Open Hardware Manager"); // bk (Open Hardware Manager Progress)
-// HMemoryUtils.trashcanNow. Engine heap size: 2,097 MB. GUI used memory: 73 MB. Current time: 7/6/26, 7:04:13 PM TRT
diff --git a/targets/fpga/genesys2/out/logs/.Xil/Vivado-116729-onur/.lpr b/targets/fpga/genesys2/out/logs/.Xil/Vivado-116729-onur/.lpr
deleted file mode 100644
index 4922431..0000000
--- a/targets/fpga/genesys2/out/logs/.Xil/Vivado-116729-onur/.lpr
+++ /dev/null
@@ -1,9 +0,0 @@
-
-
-
-
-
-
-
-
-
diff --git a/targets/fpga/genesys2/out/logs/.Xil/Vivado-183732-onur/.lpr b/targets/fpga/genesys2/out/logs/.Xil/Vivado-183732-onur/.lpr
deleted file mode 100644
index 4922431..0000000
--- a/targets/fpga/genesys2/out/logs/.Xil/Vivado-183732-onur/.lpr
+++ /dev/null
@@ -1,9 +0,0 @@
-
-
-
-
-
-
-
-
-
diff --git a/targets/fpga/genesys2/out/logs/.Xil/Vivado-61134-onur/.lpr b/targets/fpga/genesys2/out/logs/.Xil/Vivado-61134-onur/.lpr
deleted file mode 100644
index 4922431..0000000
--- a/targets/fpga/genesys2/out/logs/.Xil/Vivado-61134-onur/.lpr
+++ /dev/null
@@ -1,9 +0,0 @@
-
-
-
-
-
-
-
-
-
diff --git a/targets/fpga/genesys2/out/logs/.Xil/Vivado-68892-onur/.lpr b/targets/fpga/genesys2/out/logs/.Xil/Vivado-68892-onur/.lpr
deleted file mode 100644
index 4922431..0000000
--- a/targets/fpga/genesys2/out/logs/.Xil/Vivado-68892-onur/.lpr
+++ /dev/null
@@ -1,9 +0,0 @@
-
-
-
-
-
-
-
-
-
diff --git a/targets/fpga/genesys2/out/logs/.Xil/Vivado-9888-onur/.lpr b/targets/fpga/genesys2/out/logs/.Xil/Vivado-9888-onur/.lpr
deleted file mode 100644
index 4922431..0000000
--- a/targets/fpga/genesys2/out/logs/.Xil/Vivado-9888-onur/.lpr
+++ /dev/null
@@ -1,9 +0,0 @@
-
-
-
-
-
-
-
-
-
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream.jou b/targets/fpga/genesys2/out/logs/build_bitstream.jou
deleted file mode 100644
index 7641fb6..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Thu Aug 6 21:27:26 2026
-# Process ID : 3049064
-# Current directory : /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : ankalab04
-# Platform : Ubuntu
-# Operating System : Ubuntu 24.04.4 LTS
-# Processor Detail : AMD Ryzen 9 9950X 16-Core Processor
-# CPU Frequency : 3697.138 MHz
-# CPU Physical cores : 16
-# CPU Logical cores : 32
-# Host memory : 64914 MB
-# Swap memory : 8589 MB
-# Total Virtual : 73504 MB
-# Available Virtual : 44045 MB
-#-----------------------------------------------------------
-source /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream.log b/targets/fpga/genesys2/out/logs/build_bitstream.log
deleted file mode 100644
index a787127..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream.log
+++ /dev/null
@@ -1,3839 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Thu Aug 6 21:27:26 2026
-# Process ID : 3049064
-# Current directory : /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : ankalab04
-# Platform : Ubuntu
-# Operating System : Ubuntu 24.04.4 LTS
-# Processor Detail : AMD Ryzen 9 9950X 16-Core Processor
-# CPU Frequency : 3697.138 MHz
-# CPU Physical cores : 16
-# CPU Logical cores : 32
-# Host memory : 64914 MB
-# Swap memory : 8589 MB
-# Total Virtual : 73504 MB
-# Available Virtual : 44045 MB
-#-----------------------------------------------------------
-source /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../../..]]
-# set repo_dir [file normalize [file join $fpga_dir ../../..]]
-# set hardware_dir [file join $repo_dir hardware]
-# cd $repo_dir
-# set part_name "xc7k325tffg900-2"
-# set board_part "digilentinc.com:genesys2:part0:1.1"
-# set top_module "genesys2_rocket_top"
-# set out_dir [file join $fpga_dir out]
-# set generated_dir [file join $out_dir build generated]
-# set report_dir [file join $out_dir reports]
-# set bit_dir [file join $out_dir bitstream]
-# set checkpoint_dir [file join $out_dir build checkpoints]
-# file mkdir $generated_dir
-# file mkdir $report_dir
-# file mkdir $bit_dir
-# file mkdir $checkpoint_dir
-# set rocket_rtl_dir [file join $hardware_dir generated genesys2-soc-verilog]
-# set rocket_top [file join $rocket_rtl_dir VCU118RocketSystem.sv]
-# set rocket_filelist [file join $rocket_rtl_dir filelist.f]
-# set wrapper [file join $generated_dir ${top_module}.sv]
-# if {[info exists ::env(GPS_SYSTEM_DIR)] && [string trim $::env(GPS_SYSTEM_DIR)] ne ""} {
-# set gps_system_dir [file normalize $::env(GPS_SYSTEM_DIR)]
-# } else {
-# set gps_system_dir [file join $hardware_dir external gps rtl]
-# }
-# if {[info exists ::env(RF_INPUT_MODE)]} {
-# set rf_input_mode [string tolower [string trim $::env(RF_INPUT_MODE)]]
-# } else {
-# set rf_input_mode "pmod"
-# }
-# if {$rf_input_mode ni {"pmod" "generated" "ethernet"}} {
-# error "Unsupported Genesys2 RF_INPUT_MODE=$rf_input_mode. Use pmod, generated, or ethernet."
-# }
-# if {![file exists $rocket_filelist]} {
-# error "Rocket Verilog filelist not found: $rocket_filelist"
-# }
-# if {![file exists $rocket_top]} {
-# error "Rocket top Verilog not found: $rocket_top"
-# }
-# puts "Generating Genesys2 wrapper: $wrapper"
-Generating Genesys2 wrapper: /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv
-# puts "Genesys2 RF input mode: $rf_input_mode"
-Genesys2 RF input mode: pmod
-# exec python3 [file join $fpga_dir tools gen_genesys2_wrapper.py] \
-# --rocket-top $rocket_top \
-# --out $wrapper \
-# --rf-input-mode $rf_input_mode
-# set max_threads [string trim [exec nproc]]
-# puts "Using Vivado maxThreads=$max_threads"
-Using Vivado maxThreads=32
-# set_param general.maxThreads $max_threads
-# set_part $part_name
-INFO: [Coretcl 2-1500] The part has been set to 'xc7k325tffg900-2' for the current project only. Run set_part -help for more details. To evaluate different speed grades in the current design, use the set_speed_grade command, or use the open_checkpoint -part command to change the part used by an existing checkpoint design.
-# if {[llength [get_board_parts -quiet $board_part]] != 0} {
-# set_property board_part $board_part [current_project]
-# }
-# proc apply_genesys2_async_clock_groups {} {
-# set fabric_clk [get_clocks -quiet pll_fabric_clk]
-# set gps_acq_clk [get_clocks -quiet pll_gps_acq_clk]
-# set gps_trck_clk [get_clocks -quiet pll_gps_trck_clk]
-# set gps_ref_clk [get_clocks -quiet pll_gps_ref_clk]
-# set gps_rf_clk [get_clocks -quiet {pll_gps_rf_exact_clk pmod_rf_clk}]
-# set eth_clk [get_clocks -quiet genesys2_eth_rxck]
-#
-# if {[llength $fabric_clk] == 0 ||
-# [llength $gps_acq_clk] == 0 ||
-# [llength $gps_trck_clk] == 0 ||
-# [llength $gps_ref_clk] == 0 ||
-# [llength $gps_rf_clk] == 0} {
-# puts "Warning: not all Genesys2 async clock groups are available yet."
-# return
-# }
-#
-# puts "Applying Genesys2 async clock groups."
-# set args [list -asynchronous \
-# -group $fabric_clk \
-# -group $gps_acq_clk \
-# -group $gps_trck_clk \
-# -group $gps_rf_clk]
-# if {[llength $eth_clk] != 0} {
-# lappend args -group $eth_clk
-# }
-# set_clock_groups {*}$args
-# }
-# set rocket_files {}
-# set fh [open $rocket_filelist r]
-# while {[gets $fh line] >= 0} {
-# set line [string trim $line]
-# if {$line eq ""} {
-# continue
-# }
-# set line [regsub {^\./} $line ""]
-# lappend rocket_files [file normalize [file join $rocket_rtl_dir $line]]
-# }
-# close $fh
-# puts "Reading Rocket Chip RTL..."
-Reading Rocket Chip RTL...
-# read_verilog -sv $rocket_files
-# read_verilog [file join $hardware_dir upstream rocket-chip src main resources vsrc plusarg_reader.v]
-# set gps_filelist [file join $hardware_dir external gps rtl filelist.f]
-# set gps_files {}
-# set gps_fh [open $gps_filelist r]
-# while {[gets $gps_fh rel] >= 0} {
-# set rel [string trim $rel]
-# if {$rel eq "" || [string match "#*" $rel]} {
-# continue
-# }
-# lappend gps_files [file join $gps_system_dir $rel]
-# }
-# close $gps_fh
-# puts "Reading GPS APB wrapper RTL from $gps_system_dir..."
-Reading GPS APB wrapper RTL from /home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl...
-# set_property include_dirs [list [file join $gps_system_dir trck_src pulp_fifo]] [current_fileset]
-# read_verilog -sv $gps_files
-# puts "Reading Genesys2 shell RTL..."
-Reading Genesys2 shell RTL...
-# set shell_files [list \
-# [file join $hardware_dir fpga vcu118 rtl axi4_ram_64.sv] \
-# [file join $hardware_dir fpga vcu118 rtl axi4_slave_tieoff_64.sv] \
-# [file join $hardware_dir fpga genesys2 rtl rocket_bscan_dmi_tunnel.sv] \
-# ]
-# if {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet RF RTL..."
-# lappend shell_files \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_async_fifo.sv] \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_core.sv] \
-# [file join $hardware_dir fpga genesys2 rtl ethernet_rf eth_rf_genesys2.sv]
-# } else {
-# puts "Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=$rf_input_mode."
-# }
-Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=pmod.
-# read_verilog -sv $shell_files
-# read_verilog -sv $wrapper
-# puts "Reading constraints..."
-Reading constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_rocket.xdc]
-# puts "Reading Genesys2 PMOD SPI constraints..."
-Reading Genesys2 PMOD SPI constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_spi.xdc]
-# puts "Reading Genesys2 PMOD sensor IRQ constraints..."
-Reading Genesys2 PMOD sensor IRQ constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_irq.xdc]
-# puts "Reading Genesys2 PMOD PPS constraints..."
-Reading Genesys2 PMOD PPS constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_pps.xdc]
-# if {$rf_input_mode eq "pmod"} {
-# puts "Reading Genesys2 PMOD RF constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_rf.xdc]
-# } elseif {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet PHY constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_ethernet.xdc]
-# }
-Reading Genesys2 PMOD RF constraints...
-# puts "Running synthesis for $part_name..."
-Running synthesis for xc7k325tffg900-2...
-# synth_design -top $top_module -part $part_name -verilog_define SYNTHESIS
-Command: synth_design -top genesys2_rocket_top -part xc7k325tffg900-2 -verilog_define SYNTHESIS
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Device 21-403] Loading part xc7k325tffg900-2
-INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
-INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 3049384
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2349.547 ; gain = 401.484 ; free physical = 2303 ; free virtual = 40678
----------------------------------------------------------------------------------
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:8]
-WARNING: [Synth 8-11067] parameter 'CODE_LENGTH_IN_CHIPS' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:9]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:10]
-WARNING: [Synth 8-11067] parameter 'SAMPLING_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:13]
-WARNING: [Synth 8-11067] parameter 'CENTER_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:14]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:15]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:16]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:17]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:18]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:19]
-WARNING: [Synth 8-11067] parameter 'ABS_SAMPLE_CNTR_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:22]
-WARNING: [Synth 8-11067] parameter 'MS_PER_BIT' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:23]
-WARNING: [Synth 8-11067] parameter 'C_ACQ_CHN_NUM' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:26]
-WARNING: [Synth 8-11067] parameter 'ACQ_IQ_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:27]
-WARNING: [Synth 8-11067] parameter 'ACQ_CORR_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:28]
-WARNING: [Synth 8-11067] parameter 'RF_DMEM_AL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:30]
-WARNING: [Synth 8-11067] parameter 'NUM_PRN' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:31]
-WARNING: [Synth 8-11067] parameter 'PRN_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:32]
-WARNING: [Synth 8-11067] parameter 'STRECH_COUNT_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:33]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_COEF1' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:40]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:41]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:42]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:43]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:44]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:45]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_FREQ_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:46]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:47]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:48]
-WARNING: [Synth 8-11067] parameter 'NUM_TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:50]
-WARNING: [Synth 8-11067] parameter 'TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:51]
-WARNING: [Synth 8-11067] parameter 'ATAN_ANGLE_BIT_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:56]
-WARNING: [Synth 8-11067] parameter 'ATAN_TABLE_SIZE' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:57]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:60]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:61]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_IL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:62]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_SPACE_IL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:63]
-WARNING: [Synth 8-11067] parameter 'C1_CARR' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:65]
-WARNING: [Synth 8-11067] parameter 'C2_CARR' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:66]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:71]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:72]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:73]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:76]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_REAL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:77]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_INT' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:78]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_REAL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:80]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_INT' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:81]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:83]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:84]
-WARNING: [Synth 8-11067] parameter 'LOCK_WINDOW' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:85]
-WARNING: [Synth 8-11067] parameter 'LOCK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:86]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:89]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:90]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:92]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:93]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:95]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:96]
-WARNING: [Synth 8-11067] parameter 'CODE_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:99]
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:100]
-WARNING: [Synth 8-11067] parameter 'REAL_POS_FS_2' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:102]
-WARNING: [Synth 8-11067] parameter 'REAL_NEG_FS' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:103]
-WARNING: [Synth 8-11067] parameter 'FS_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:105]
-WARNING: [Synth 8-11067] parameter 'DLL_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:106]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:108]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:109]
-WARNING: [Synth 8-11067] parameter 'REM_CODE_PH_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:110]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:113]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_IL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:114]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:115]
-WARNING: [Synth 8-11067] parameter 'F_ACQ_CLK' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:118]
-WARNING: [Synth 8-11067] parameter 'ACQ_CLK_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:119]
-WARNING: [Synth 8-11067] parameter 'RF_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:120]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE_CHIP' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:121]
-WARNING: [Synth 8-11067] parameter 'ACQ_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:123]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:124]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:125]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:126]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:127]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:128]
-WARNING: [Synth 8-11067] parameter 'ACQ_CODE_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:130]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:132]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:133]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:134]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:135]
-WARNING: [Synth 8-11067] parameter 'IFFT_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:136]
-WARNING: [Synth 8-11067] parameter 'IFFT_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:137]
-WARNING: [Synth 8-11067] parameter 'IFFT_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:139]
-WARNING: [Synth 8-11067] parameter 'NFFT' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:141]
-WARNING: [Synth 8-11067] parameter 'NFFT_OVER_2' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:142]
-WARNING: [Synth 8-11067] parameter 'ZERO_PAD' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:143]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:145]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:146]
-WARNING: [Synth 8-11067] parameter 'ABS_SQR_I_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:147]
-WARNING: [Synth 8-11067] parameter 'CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:148]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_DIV_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:149]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:150]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_FL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:151]
-WARNING: [Synth 8-11067] parameter 'PEAK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:152]
-WARNING: [Synth 8-11067] parameter 'DOPP_STEP' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:154]
-WARNING: [Synth 8-11067] parameter 'NUM_FREQ_BIN' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:155]
-WARNING: [Synth 8-11067] parameter 'FREQ_BIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/definitions.sv:156]
-INFO: [Common 17-14] Message 'Synth 8-11067' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-10180] variable 'i' must explicitly be declared as automatic or static [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv:53]
-INFO: [Synth 8-6157] synthesizing module 'genesys2_rocket_top' [/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:3]
-INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
- Parameter DIFF_TERM bound to: FALSE - type: string
- Parameter IBUF_LOW_PWR bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 5.000000e+00 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 5.000000e+00 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.250000e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT1_DIVIDE bound to: 20 - type: integer
- Parameter CLKOUT1_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT1_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT2_DIVIDE bound to: 8 - type: integer
- Parameter CLKOUT2_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT2_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:75]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:75]
-WARNING: [Synth 8-7023] instance 'u_clock_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:75]
-INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6157] synthesizing module 'IBUF' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV__parameterized0' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 5.812500e+01 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 6.109500e+01 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.712500e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV__parameterized0' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_ref_mmcm' [/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:152]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_ref_mmcm' [/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:152]
-WARNING: [Synth 8-7023] instance 'u_gps_ref_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:152]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV__parameterized1' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 1.800000e+01 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 1.800000e+01 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.250000e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer
- Parameter CLKOUT1_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT1_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV__parameterized1' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_domain_mmcm' [/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:212]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_domain_mmcm' [/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:212]
-WARNING: [Synth 8-7023] instance 'u_gps_domain_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:212]
-INFO: [Synth 8-6157] synthesizing module 'BSCANE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
- Parameter DISABLE_JTAG bound to: FALSE - type: string
- Parameter JTAG_CHAIN bound to: 4 - type: integer
-INFO: [Synth 8-6155] done synthesizing module 'BSCANE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
-INFO: [Synth 8-6157] synthesizing module 'rocket_bscan_dmi_tunnel' [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'rocket_bscan_dmi_tunnel' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:390]
-INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
- Parameter PROG_USR bound to: FALSE - type: string
- Parameter SIM_CCLK_FREQ bound to: 0.000000e+00 - type: double
-INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
-INFO: [Synth 8-6157] synthesizing module 'VCU118RocketSystem' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/VCU118RocketSystem.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ClockSinkDomain' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i2_o1' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i2_o1' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'ClockSinkDomain' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_aggregator' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_aggregator' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/SystemBus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_sbus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_sbus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroup' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroup' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:11]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_1' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_1' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/SystemBus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_pbus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_pbus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_pbus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_5' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_5' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_1' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_1' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:11]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a29d64s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x120' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x120' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x77' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x77' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a29d64s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_pbus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:11]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_pbus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAUART' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAUART' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:11]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_gps' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAGPS' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAGPS' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_2' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_2' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_gps' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_pbus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'FrontBus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FrontBus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_1' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_1' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s1k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x123' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x123' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s1k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget1' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget1' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'FrontBus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FrontBus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_cbus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_cbus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_2' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_2' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:11]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x124' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x124' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x78' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x78' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:11]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLError.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLError.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s2k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x99' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x99' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s2k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u_1' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u_1' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_3' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_3' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:11]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:11]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_debug' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_Debug' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_Debug' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:11]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_debug' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_4' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_4' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:11]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TilePRCIDomain' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'HierarchicalElementResetDomain' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/HierarchicalElementResetDomain.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'RocketTile' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/RocketTile.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:11]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:11]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:2]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i3_o1' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:2]
-INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i3_o1' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'PMPChecker_s3' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/PMPChecker_s3.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'PMAChecker' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/PMAChecker.sv:2]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/DTLB.sv:162]
-INFO: [Synth 8-6155] done synthesizing module 'OptimizationBarrier_TLBEntryData' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/OptimizationBarrier_TLBEntryData.sv:2]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/DTLB.sv:196]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/DTLB.sv:230]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/DTLB.sv:264]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/DTLB.sv:298]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/DTLB.sv:332]
-INFO: [Synth 8-6155] done synthesizing module 'DTLB' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/DTLB.sv:2]
-INFO: [Synth 8-6155] done synthesizing module 'Arbiter8_DCacheMetadataReq' (0#1) [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Arbiter8_DCacheMetadataReq.sv:2]
-INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ITLB.sv:107]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ITLB.sv:141]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ITLB.sv:175]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ITLB.sv:209]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ITLB.sv:243]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/ITLB.sv:277]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:3148]
- Parameter FORMAT bound to: max_core_cycles=%d - type: string
- Parameter WIDTH bound to: 32 - type: integer
- Parameter DEFAULT bound to: 32'b00000000000000000000000000000000
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000000001
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter DATA_WIDTH bound to: 4 - type: integer
- Parameter ADDR_WIDTH bound to: 15 - type: integer
- Parameter PH_ACC_WL bound to: 32 - type: integer
- Parameter LUT_DEPTH_WL bound to: 5 - type: integer
- Parameter ACQ_SIN_IL bound to: 2 - type: integer
- Parameter ACQ_SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 25 - type: integer
- Parameter FS bound to: 16368000 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 52 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 36 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_IQ_WL bound to: 24 - type: integer
- Parameter FFT_IQ_TRUNC_WL bound to: 20 - type: integer
- Parameter FFT_CODE_WL bound to: 16 - type: integer
- Parameter FFT_CODE_TRUNC_WL bound to: 16 - type: integer
- Parameter OUT_WL bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 92 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter DWIDTH bound to: 48 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ABS_SQR_I_TRUNCATED_WL bound to: 25 - type: integer
- Parameter CORR_DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter SAMPLES_PER_CODE_CHIP bound to: 16 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv:158]
- Parameter DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ITER bound to: 9 - type: integer
- Parameter IN_W_L bound to: 36 - type: integer
- Parameter IN_F_L bound to: 0 - type: integer
- Parameter OUT_W_L bound to: 16 - type: integer
- Parameter OUT_F_L bound to: 8 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:285]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:296]
-WARNING: [Synth 8-151] case item 32'b00000000000000000000000000001100 is unreachable [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:350]
-WARNING: [Synth 8-7071] port 'clk_200mhz' of module 'afe_top' is unconnected for instance 'afe' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:130]
-WARNING: [Synth 8-7071] port 'mmcm_locked' of module 'afe_top' is unconnected for instance 'afe' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:130]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rd' of module 'afe_top' is unconnected for instance 'afe' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:130]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:130]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rxc' of module 'afe_top' is unconnected for instance 'afe' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:130]
-WARNING: [Synth 8-7071] port 'eth_rgmii_td' of module 'afe_top' is unconnected for instance 'afe' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:130]
-WARNING: [Synth 8-7071] port 'eth_rgmii_tx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:130]
-WARNING: [Synth 8-7071] port 'eth_rgmii_txc' of module 'afe_top' is unconnected for instance 'afe' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:130]
-WARNING: [Synth 8-7023] instance 'afe' of module 'afe_top' has 17 connections declared, but only 9 given [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:130]
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000100000
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter SIG_DEPTH bound to: 26 - type: integer
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000011110
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000011011
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000110010
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000000101
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000010000
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
-INFO: [Synth 8-155] case statement is not full and has no default [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:182]
- Parameter WIDTH bound to: 4 - type: integer
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter STAGES bound to: 32'b00000000000000000000000000000010
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter Bypass bound to: 1'b0
- Parameter PH_ACC_WL bound to: 24 - type: integer
- Parameter LUT_DEPTH_WL bound to: 7 - type: integer
- Parameter SIN_IL bound to: 2 - type: integer
- Parameter SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 46 - type: integer
- Parameter CODE_FREQ_I_IL bound to: 21 - type: integer
- Parameter CODE_FREQ_I_FL bound to: 20 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 10 - type: integer
- Parameter O_IL bound to: 16 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 13 - type: integer
- Parameter O_IL bound to: 8 - type: integer
- Parameter O_FL bound to: 20 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter TABLE_ADDR bound to: 4 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 33 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER1 bound to: 8 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter TABLE_ADDR bound to: 3 - type: integer
-WARNING: [Synth 8-151] case item 4'b1000 is unreachable [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:114]
-INFO: [Synth 8-226] default block is never used [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:105]
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 32 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 25 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter DIV_OUT_WL bound to: 15 - type: integer
- Parameter DIV_OUT_FL bound to: 13 - type: integer
- Parameter DIV_ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 45 - type: integer
- Parameter IN_FL bound to: 8 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:446]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:727]
- Parameter HIGH_ADDRESS bound to: 32'b00000000000000000000111111111111
- Parameter LOW_ADDRESS bound to: 32'b00000000000000000000000000000000
- Parameter DATA_BUS_WIDTH bound to: 32'b00000000000000000000000000100000
- Parameter ADDR_BUS_WIDTH bound to: 32'b00000000000000000000000000001100
- Parameter NUM_CAPTURE_CHANNELS bound to: 32'b00000000000000000000000000001001
- Parameter CLK_FREQ_HZ bound to: 32'b00000111011100110101100101000000
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:19]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:20]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_64x21.sv:18]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_64x21.sv:19]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:18]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:19]
-WARNING: [Synth 8-4767] Trying to implement RAM 'Memory_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/regfile_32x65.sv:31]
-Reason is one or more of the following :
- 1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
- 2: Invalid write to RAM.
- 3: Invalid write to RAM.
- 4: No valid clock found for write to RAM.
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2137]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2592]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2603]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2717]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2718]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2720]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2721]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2736]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2737]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2739]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2740]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2857]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2858]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2859]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2860]
-WARNING: [Synth 8-6014] Unused sequential element r_counter_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLError_1.sv:29]
-Read & Write Range Direction Mismatch
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module comp_mult has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/comp_mult.sv:106]
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module ifft_abs_sqr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:90]
-WARNING: [Synth 8-3848] Net eth_rgmii_td in module/entity afe_top does not have driver. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/afe_top.sv:38]
-WARNING: [Synth 8-3848] Net eth_rgmii_tx_ctl in module/entity afe_top does not have driver. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/afe_top.sv:39]
-WARNING: [Synth 8-3848] Net eth_rgmii_txc in module/entity afe_top does not have driver. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/afe_top.sv:40]
-WARNING: [Synth 8-3848] Net rf_data_o in module/entity afe_top does not have driver. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/common/afe_top.sv:46]
-WARNING: [Synth 8-3848] Net fifo_of_o in module/entity trck_cntrl does not have driver. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:50]
-WARNING: [Synth 8-6014] Unused sequential element g1_var_reg was removed. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:46]
-WARNING: [Synth 8-7137] Register chip_o_reg in module cacode_gen_trck has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:36]
-WARNING: [Synth 8-7129] Port loop_config[7] in module pps_core is either unconnected or has no load
-WARNING: [Synth 8-7129] Port loop_config[6] in module pps_core is either unconnected or has no load
-WARNING: [Synth 8-7129] Port loop_config[5] in module pps_core is either unconnected or has no load
-WARNING: [Synth 8-7129] Port loop_config[4] in module pps_core is either unconnected or has no load
-WARNING: [Synth 8-7129] Port loop_config[3] in module pps_core is either unconnected or has no load
-WARNING: [Synth 8-7129] Port loop_config[2] in module pps_core is either unconnected or has no load
-WARNING: [Synth 8-7129] Port loop_config[1] in module pps_core is either unconnected or has no load
-WARNING: [Synth 8-7129] Port loop_config[0] in module pps_core is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module pps_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port fifo_of_o in module trck_cntrl is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_tx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_txc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port clk_200mhz in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port mmcm_locked in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rxc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port start_acq_manuel in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_en in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_clk in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[3] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_sink in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[127] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[126] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[125] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[124] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[123] in module SBToTL is either unconnected or has no load
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2754.086 ; gain = 806.023 ; free physical = 1951 ; free virtual = 40334
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2754.086 ; gain = 806.023 ; free physical = 1956 ; free virtual = 40339
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2754.086 ; gain = 806.023 ; free physical = 1957 ; free virtual = 40339
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2754.086 ; gain = 0.000 ; free physical = 1948 ; free virtual = 40332
-INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Finished Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-INFO: [Timing 38-2] Deriving generated clocks
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3261.242 ; gain = 0.000 ; free physical = 1858 ; free virtual = 40242
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3273.164 ; gain = 0.000 ; free physical = 1841 ; free virtual = 40226
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 3273.164 ; gain = 1325.102 ; free physical = 498 ; free virtual = 38882
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7k325tffg900-2
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 3281.168 ; gain = 1333.105 ; free physical = 498 ; free virtual = 38882
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 3281.168 ; gain = 1333.105 ; free physical = 498 ; free virtual = 38882
----------------------------------------------------------------------------------
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:378]
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:416]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore2_addr_reg' and it is trimmed from '34' to '20' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/DCache.sv:395]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore1_addr_reg' and it is trimmed from '34' to '20' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/DCache.sv:395]
-WARNING: [Synth 8-3936] Found unconnected internal register 'uncachedReqs_0_addr_reg' and it is trimmed from '34' to '3' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/DCache.sv:930]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in1_reg' and it is trimmed from '65' to '33' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:29]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in3_reg' and it is trimmed from '65' to '33' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:31]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FPToInt.sv:144]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_typeTagOut_reg' and it is trimmed from '2' to '1' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FPToInt.sv:67]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_pipe_b_typeTagIn_reg' and it is trimmed from '2' to '1' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/IntToFP.sv:37]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FPU.sv:486]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FPU.sv:316]
-WARNING: [Synth 8-3936] Found unconnected internal register 'load_wb_typeTag_reg' and it is trimmed from '2' to '1' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/FPU.sv:119]
-WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2754]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2754]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Rocket.sv:2789]
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized1'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_peak_srch'
-INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'divider_fsm'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_top'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'acq_wrapper'
-INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'trck_cntrl'
-INFO: [Synth 8-802] inferred FSM for state register 'nav_solve_state_p_reg' in module 'nav_solve_timer'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'tracking_wrapper'
-INFO: [Synth 8-802] inferred FSM for state register 'commit_state_p_reg' in module 'pps_core'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'pps_wrapper'
-WARNING: [Synth 8-6841] Block RAM (Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-INFO: [Synth 8-3971] The signal "dual_port_bram:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized0:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized1:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized1'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 001 | 000
- S_CORR | 101 | 001
- S_INIT_ADDR | 100 | 010
- S_DATA_Q | 011 | 011
- S_SRCH | 010 | 100
- S_END | 000 | 101
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'sequential' in module 'acq_peak_srch'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- idle | 00 | 00
- normalization | 01 | 01
- cordic_core | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'divider_fsm'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 0000001 | 000
- S_WR_DATA | 0001000 | 001
- S_START | 0010000 | 010
- S_CTRL | 1000000 | 011
- S_FREQ | 0100000 | 100
- S_END | 0000010 | 101
- S_PULLIN | 0000100 | 110
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'one-hot' in module 'acq_top'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'acq_wrapper'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- WAIT_START | 00 | 00
- WAIT_SAMPLE_ALIGN | 01 | 01
- WAIT_CODE_PHASE | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'trck_cntrl'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- iSTATE | 00 | 00
-*
- iSTATE0 | 01 | 01
- iSTATE1 | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'nav_solve_state_p_reg' using encoding 'sequential' in module 'nav_solve_timer'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'tracking_wrapper'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- PPS_COMMIT_IDLE | 0000 | 0000
- PPS_COMMIT_FRACTION | 0001 | 0001
- PPS_COMMIT_AGE_CAPTURE | 0010 | 0010
- PPS_COMMIT_AGE_MULTIPLY | 0011 | 0011
- PPS_COMMIT_MAP | 0100 | 0100
- PPS_COMMIT_NORMALIZE | 0101 | 0101
- PPS_COMMIT_PHASE | 0110 | 0110
- PPS_COMMIT_PI_MULTIPLY | 0111 | 0111
- PPS_COMMIT_INTEGRATE | 1000 | 1000
-PPS_COMMIT_CLAMP_INTEGRATOR | 1001 | 1001
- PPS_COMMIT_APPLY | 1010 | 1010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'commit_state_p_reg' using encoding 'sequential' in module 'pps_core'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- PPS_APB_STATE_IDLE | 001 | 00
- PPS_APB_STATE_ACCESS | 100 | 01
- PPS_APB_STATE_FINISH | 010 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'pps_wrapper'
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 3281.168 ; gain = 1333.105 ; free physical = 473 ; free virtual = 36593
----------------------------------------------------------------------------------
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/tlb/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/tlb/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/tlb/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/tlb/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/tlb/entries_barrier_5'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_5'
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
----------------------------------------------------------------------------------
-Start RTL Component Statistics
----------------------------------------------------------------------------------
-Detailed RTL Component Info :
-+---Adders :
- 3 Input 128 Bit Adders := 1
- 2 Input 112 Bit Adders := 1
- 3 Input 112 Bit Adders := 1
- 2 Input 109 Bit Adders := 1
- 2 Input 107 Bit Adders := 1
- 3 Input 99 Bit Adders := 1
- 2 Input 99 Bit Adders := 1
- 2 Input 66 Bit Adders := 1
- 3 Input 65 Bit Adders := 2
- 2 Input 65 Bit Adders := 3
- 2 Input 64 Bit Adders := 15
- 3 Input 64 Bit Adders := 2
- 2 Input 62 Bit Adders := 1
- 3 Input 61 Bit Adders := 1
- 3 Input 58 Bit Adders := 1
- 2 Input 58 Bit Adders := 2
- 2 Input 55 Bit Adders := 4
- 2 Input 51 Bit Adders := 2
- 2 Input 50 Bit Adders := 9
- 2 Input 49 Bit Adders := 1
- 2 Input 46 Bit Adders := 11
- 3 Input 46 Bit Adders := 2
- 2 Input 45 Bit Adders := 18
- 3 Input 45 Bit Adders := 10
- 2 Input 42 Bit Adders := 1
- 2 Input 41 Bit Adders := 9
- 3 Input 41 Bit Adders := 1
- 2 Input 34 Bit Adders := 2
- 3 Input 33 Bit Adders := 18
- 2 Input 32 Bit Adders := 75
- 3 Input 32 Bit Adders := 67
- 2 Input 30 Bit Adders := 18
- 3 Input 30 Bit Adders := 1
- 3 Input 29 Bit Adders := 1
- 2 Input 28 Bit Adders := 18
- 2 Input 27 Bit Adders := 18
- 2 Input 26 Bit Adders := 25
- 4 Input 26 Bit Adders := 9
- 3 Input 26 Bit Adders := 2
- 2 Input 25 Bit Adders := 11
- 3 Input 25 Bit Adders := 9
- 2 Input 24 Bit Adders := 1
- 2 Input 23 Bit Adders := 54
- 2 Input 22 Bit Adders := 18
- 2 Input 18 Bit Adders := 2
- 3 Input 18 Bit Adders := 2
- 3 Input 16 Bit Adders := 1
- 2 Input 16 Bit Adders := 1
- 2 Input 15 Bit Adders := 2
- 2 Input 14 Bit Adders := 20
- 4 Input 14 Bit Adders := 1
- 3 Input 14 Bit Adders := 1
- 3 Input 13 Bit Adders := 2
- 2 Input 13 Bit Adders := 7
- 2 Input 12 Bit Adders := 13
- 3 Input 12 Bit Adders := 10
- 4 Input 11 Bit Adders := 1
- 2 Input 11 Bit Adders := 4
- 3 Input 10 Bit Adders := 2
- 2 Input 10 Bit Adders := 1
- 2 Input 9 Bit Adders := 11
- 3 Input 9 Bit Adders := 5
- 2 Input 8 Bit Adders := 7
- 2 Input 7 Bit Adders := 4
- 2 Input 6 Bit Adders := 24
- 3 Input 6 Bit Adders := 2
- 2 Input 5 Bit Adders := 59
- 2 Input 4 Bit Adders := 85
- 3 Input 4 Bit Adders := 1
- 3 Input 3 Bit Adders := 9
- 2 Input 3 Bit Adders := 43
- 2 Input 2 Bit Adders := 16
- 3 Input 2 Bit Adders := 4
- 4 Input 2 Bit Adders := 1
- 5 Input 2 Bit Adders := 1
- 3 Input 1 Bit Adders := 3
- 2 Input 1 Bit Adders := 41
-+---XORs :
- 2 Input 64 Bit XORs := 7
- 2 Input 32 Bit XORs := 8
- 2 Input 29 Bit XORs := 8
- 2 Input 17 Bit XORs := 33
- 2 Input 16 Bit XORs := 2
- 2 Input 15 Bit XORs := 4
- 2 Input 14 Bit XORs := 1
- 2 Input 12 Bit XORs := 3
- 2 Input 10 Bit XORs := 3
- 2 Input 5 Bit XORs := 38
- 2 Input 4 Bit XORs := 2
- 2 Input 3 Bit XORs := 15
- 2 Input 2 Bit XORs := 6
- 2 Input 1 Bit XORs := 487
- 3 Input 1 Bit XORs := 68
- 6 Input 1 Bit XORs := 19
- 7 Input 1 Bit XORs := 18
- 13 Input 1 Bit XORs := 90
- 11 Input 1 Bit XORs := 63
- 12 Input 1 Bit XORs := 63
- 8 Input 1 Bit XORs := 54
- 10 Input 1 Bit XORs := 72
- 4 Input 1 Bit XORs := 54
- 14 Input 1 Bit XORs := 117
- 5 Input 1 Bit XORs := 18
- 15 Input 1 Bit XORs := 9
- 9 Input 1 Bit XORs := 54
- 16 Input 1 Bit XORs := 9
-+---XORs :
- 5 Bit Wide XORs := 36
- 4 Bit Wide XORs := 36
- 3 Bit Wide XORs := 36
- 2 Bit Wide XORs := 36
-+---Registers :
- 310 Bit Registers := 9
- 130 Bit Registers := 1
- 112 Bit Registers := 5
- 107 Bit Registers := 1
- 104 Bit Registers := 1
- 99 Bit Registers := 2
- 98 Bit Registers := 1
- 92 Bit Registers := 2
- 90 Bit Registers := 3
- 88 Bit Registers := 1
- 65 Bit Registers := 45
- 64 Bit Registers := 69
- 62 Bit Registers := 2
- 58 Bit Registers := 2
- 56 Bit Registers := 1
- 55 Bit Registers := 13
- 53 Bit Registers := 1
- 52 Bit Registers := 2
- 51 Bit Registers := 8
- 50 Bit Registers := 63
- 49 Bit Registers := 2
- 48 Bit Registers := 81
- 46 Bit Registers := 18
- 45 Bit Registers := 2
- 43 Bit Registers := 1
- 41 Bit Registers := 11
- 40 Bit Registers := 9
- 36 Bit Registers := 3
- 34 Bit Registers := 25
- 33 Bit Registers := 30
- 32 Bit Registers := 274
- 31 Bit Registers := 90
- 30 Bit Registers := 73
- 29 Bit Registers := 6
- 28 Bit Registers := 20
- 27 Bit Registers := 109
- 26 Bit Registers := 121
- 24 Bit Registers := 41
- 22 Bit Registers := 136
- 21 Bit Registers := 9
- 20 Bit Registers := 2
- 18 Bit Registers := 9
- 17 Bit Registers := 3
- 16 Bit Registers := 53
- 15 Bit Registers := 53
- 14 Bit Registers := 50
- 13 Bit Registers := 9
- 12 Bit Registers := 22
- 10 Bit Registers := 29
- 9 Bit Registers := 13
- 8 Bit Registers := 117
- 7 Bit Registers := 12
- 6 Bit Registers := 83
- 5 Bit Registers := 169
- 4 Bit Registers := 218
- 3 Bit Registers := 166
- 2 Bit Registers := 223
- 1 Bit Registers := 1607
-+---Multipliers :
- 48x64 Multipliers := 2
- 53x53 Multipliers := 1
- 33x65 Multipliers := 1
- 66x66 Multipliers := 1
- 15x46 Multipliers := 4
- 27x32 Multipliers := 1
- 25x30 Multipliers := 9
-+---RAMs :
- 8192K Bit (131072 X 64 bit) RAMs := 1
- 1472K Bit (16384 X 92 bit) RAMs := 1
- 832K Bit (16384 X 52 bit) RAMs := 1
- 816K Bit (16384 X 51 bit) RAMs := 1
- 768K Bit (16384 X 48 bit) RAMs := 1
- 576K Bit (16384 X 36 bit) RAMs := 1
- 128K Bit (32768 X 4 bit) RAMs := 1
- 16K Bit (512 X 32 bit) RAMs := 2
- 1K Bit (64 X 21 bit) RAMs := 1
-+---ROMs :
- ROMs := 6
-+---Muxes :
- 2 Input 2080 Bit Muxes := 1
- 2 Input 130 Bit Muxes := 3
- 3 Input 128 Bit Muxes := 1
- 2 Input 128 Bit Muxes := 2
- 2 Input 112 Bit Muxes := 2
- 2 Input 109 Bit Muxes := 1
- 2 Input 108 Bit Muxes := 1
- 2 Input 92 Bit Muxes := 6
- 2 Input 65 Bit Muxes := 19
- 4 Input 65 Bit Muxes := 1
- 2 Input 64 Bit Muxes := 138
- 4 Input 64 Bit Muxes := 7
- 11 Input 64 Bit Muxes := 5
- 2 Input 62 Bit Muxes := 1
- 2 Input 61 Bit Muxes := 2
- 2 Input 58 Bit Muxes := 2
- 2 Input 56 Bit Muxes := 5
- 2 Input 55 Bit Muxes := 11
- 2 Input 54 Bit Muxes := 3
- 2 Input 53 Bit Muxes := 2
- 2 Input 52 Bit Muxes := 16
- 2 Input 51 Bit Muxes := 5
- 2 Input 50 Bit Muxes := 46
- 2 Input 48 Bit Muxes := 7
- 2 Input 46 Bit Muxes := 27
- 2 Input 45 Bit Muxes := 21
- 3 Input 45 Bit Muxes := 2
- 2 Input 44 Bit Muxes := 4
- 2 Input 41 Bit Muxes := 7
- 2 Input 36 Bit Muxes := 6
- 7 Input 36 Bit Muxes := 1
- 2 Input 34 Bit Muxes := 29
- 2 Input 33 Bit Muxes := 40
- 2 Input 32 Bit Muxes := 351
- 3 Input 32 Bit Muxes := 10
- 4 Input 32 Bit Muxes := 1
- 2 Input 30 Bit Muxes := 9
- 2 Input 29 Bit Muxes := 9
- 2 Input 28 Bit Muxes := 1
- 2 Input 27 Bit Muxes := 76
- 2 Input 26 Bit Muxes := 15
- 2 Input 25 Bit Muxes := 25
- 2 Input 24 Bit Muxes := 101
- 11 Input 24 Bit Muxes := 1
- 2 Input 23 Bit Muxes := 65
- 2 Input 22 Bit Muxes := 78
- 2 Input 20 Bit Muxes := 4
- 2 Input 17 Bit Muxes := 1
- 2 Input 16 Bit Muxes := 13
- 3 Input 16 Bit Muxes := 1
- 7 Input 16 Bit Muxes := 1
- 2 Input 15 Bit Muxes := 18
- 2 Input 14 Bit Muxes := 62
- 7 Input 14 Bit Muxes := 1
- 2 Input 13 Bit Muxes := 20
- 2 Input 12 Bit Muxes := 51
- 2 Input 11 Bit Muxes := 2
- 2 Input 10 Bit Muxes := 13
- 2 Input 9 Bit Muxes := 34
- 3 Input 9 Bit Muxes := 1
- 2 Input 8 Bit Muxes := 213
- 8 Input 8 Bit Muxes := 18
- 11 Input 8 Bit Muxes := 1
- 2 Input 7 Bit Muxes := 20
- 7 Input 7 Bit Muxes := 1
- 4 Input 6 Bit Muxes := 1
- 2 Input 6 Bit Muxes := 65
- 3 Input 6 Bit Muxes := 3
- 7 Input 6 Bit Muxes := 3
- 2 Input 5 Bit Muxes := 127
- 4 Input 5 Bit Muxes := 2
- 3 Input 5 Bit Muxes := 4
- 2 Input 4 Bit Muxes := 124
- 4 Input 4 Bit Muxes := 3
- 8 Input 4 Bit Muxes := 1
- 3 Input 4 Bit Muxes := 1
- 11 Input 4 Bit Muxes := 1
- 7 Input 4 Bit Muxes := 2
- 2 Input 3 Bit Muxes := 193
- 6 Input 3 Bit Muxes := 3
- 8 Input 3 Bit Muxes := 3
- 4 Input 3 Bit Muxes := 3
- 3 Input 3 Bit Muxes := 28
- 7 Input 3 Bit Muxes := 1
- 5 Input 3 Bit Muxes := 2
- 2 Input 2 Bit Muxes := 199
- 16 Input 2 Bit Muxes := 1
- 3 Input 2 Bit Muxes := 23
- 4 Input 2 Bit Muxes := 5
- 7 Input 2 Bit Muxes := 1
- 8 Input 2 Bit Muxes := 1
- 2 Input 1 Bit Muxes := 1697
- 3 Input 1 Bit Muxes := 42
- 5 Input 1 Bit Muxes := 27
- 4 Input 1 Bit Muxes := 30
- 11 Input 1 Bit Muxes := 33
- 6 Input 1 Bit Muxes := 1
- 7 Input 1 Bit Muxes := 9
----------------------------------------------------------------------------------
-Finished RTL Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 840 (col length:140)
-BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 10. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv:107]
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_typeTagIn_reg[1]' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (dfma/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\ex_reg_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\in_pipe_b_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\mem_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[1]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[2]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[2]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[3]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[3]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[4]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (ifpu/\io_out_pipe_b_exc_reg[4] )
-WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_addr_reg' and it is trimmed from '34' to '32' bits. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/DCache.sv:424]
-INFO: [Synth 8-4471] merging register 's2_tlb_resp_pf_inst_reg' into 's2_tlb_resp_cacheable_reg' [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/Frontend.sv:108]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 16. [/home/ankaoc/Desktop/tmp/gps/hardware/generated/genesys2-soc-verilog/MulDiv.sv:101]
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-WARNING: [Synth 8-6841] Block RAM (rockettile_dcache_data_arrays_0_ext/Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[60]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[60]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[61]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[61]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[62]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[62]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[57]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[57]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[58]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[58]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[59]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[59]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[54]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[54]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[55]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[55]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[56]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[56]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[51]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[51]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[52]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[52]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[53]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[53]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[48]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[48]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[49]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[49]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[50]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[50]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[45]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[45]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[46]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[46]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[47]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[47]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[42]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[42]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[43]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[43]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[44]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[44]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[39]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[39]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[40]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[40]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[41]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[41]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[36]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[36]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[37]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[37]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[38]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[38]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[33]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[33]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[34]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[34]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[35]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[35]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[30]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[30]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[31]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[31]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[32]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[32]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[27]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[27]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[28]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[28]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[29]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[29]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[24]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[24]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[25]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[25]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[26]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[26]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[21]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[21]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[22]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[22]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[23]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[23]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[18]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[18]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[19]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[19]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[20]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[20]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[15]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[15]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[16]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[16]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[17]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[17]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_reg_cause_reg[5] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/ibuf/buf_xcpt_gf_inst_reg)
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mie_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mcountinhibit_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mie_reg[63] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_sel_alu2_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/\s1_pc_reg[0] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_mem_cmd_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (dcache/s2_pma_cacheable_reg)
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/s2_tlb_resp_cacheable_reg)
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[5] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[7] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[7] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[8] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[8] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[12] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[22] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[22] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[23] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[23] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[46] )
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 4. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/NCO_carr.sv:129]
-DSP Report: Generating DSP freq_word0, operation Mode is: (A:0x6677)*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: A*(B:0x6677).
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x109).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x55).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult20, operation Mode is: A*(B:0x75).
-DSP Report: operator mult20 is absorbed into DSP mult20.
-INFO: [Synth 8-5544] ROM "cordic_angle_lut_i/angle_o" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
-INFO: [Synth 8-4471] merging register 'prompt_abs_vld_reg' into 'cos2x_i/sqr_vld_reg' [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/lock_detector.sv:111]
-DSP Report: Generating DSP cos2x_i/q_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: Generating DSP cos2x_i/i_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[15]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[14]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[13]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[12]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[11]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[10]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[9]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[8]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[7]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[6]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[5]__1) is unused and will be removed from module NCO_carr.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 8. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:357]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 4. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:346]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 12. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:424]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 12. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:423]
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (A:0x15940)*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: A*(B:0x15940).
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w0, operation Mode is: C+A*B.
-DSP Report: operator butterfly_i/x1_imag_w0 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w0, operation Mode is: C-A*B.
-DSP Report: operator butterfly_i/x1_real_w0 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP bd, operation Mode is: A*B.
-DSP Report: operator bd is absorbed into DSP bd.
-DSP Report: Generating DSP ac, operation Mode is: A*B.
-DSP Report: operator ac is absorbed into DSP ac.
-DSP Report: Generating DSP ad, operation Mode is: A*B.
-DSP Report: operator ad is absorbed into DSP ad.
-DSP Report: Generating DSP bc, operation Mode is: A*B.
-DSP Report: operator bc is absorbed into DSP bc.
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-WARNING: [Synth 8-3917] design APBGpsBlock__GCB1 has port _acq_sample_counter_clear driven by constant 0
-INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM acq/i_acq_top/dual_port_ram_i/ram_reg to conserve power
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_IQ_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_code_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /ifft_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-4652] Swapped enable and write-enable on 26 RAM instances of RAM bram_i/ram_reg to conserve power
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_12_17 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_6_11 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:54 ; elapsed = 00:00:59 . Memory (MB): peak = 3297.180 ; gain = 1349.117 ; free physical = 792 ; free virtual = 31712
----------------------------------------------------------------------------------
- Sort Area is APBGpsBlock__GCB1 p_1_out_0 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_2 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_3 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_4 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is RocketTile__GC0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_4 : 0 0 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_4 : 0 1 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_4 : 0 2 : 2812 12223 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_4 : 0 3 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_6 : 0 0 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_6 : 0 1 : 2793 11879 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_6 : 0 2 : 2812 11879 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_6 : 0 3 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_8 : 0 0 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_8 : 0 1 : 2812 11089 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_8 : 0 2 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GC0 remainder1_8 : 0 3 : 2691 11089 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 0 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 1 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 2 : 3255 9727 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 0 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 1 : 3101 9573 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 2 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 0 : 3101 9322 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 1 : 3120 9322 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 2 : 3101 9322 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 0 : 1995 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 1 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 2 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 0 : 1995 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 1 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 2 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 0 : 1313 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 1 : 2710 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 2 : 2759 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 0 : 1313 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 1 : 2710 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 2 : 2712 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 0 : 1313 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 1 : 2710 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 2 : 2712 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 0 : 1313 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 1 : 2759 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 2 : 2479 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 0 : 1995 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 1 : 2712 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 2 : 1836 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 0 : 1995 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 1 : 2712 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 2 : 1836 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 0 : 1995 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 1 : 1836 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 2 : 1495 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 0 : 1995 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 1 : 1836 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 2 : 1495 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 im_sqr0_26 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 im_sqr0_26 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 re_sqr0_23 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 re_sqr0_23 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 0 : 3446 4760 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 1 : 1314 4760 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1e : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1e : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_20 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_20 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_18 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_18 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1c : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1c : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_17 : 0 0 : 1315 3694 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_17 : 0 1 : 2379 3694 : Used 1 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 0 : 1789 3431 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 1 : 1642 3431 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_0 : 0 0 : 1313 3313 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_0 : 0 1 : 2000 3313 : Used 1 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 0 : 1785 3295 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 1 : 1510 3295 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_3 : 0 0 : 1315 3237 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_3 : 0 1 : 1922 3237 : Used 1 time 0
- Sort Area is tracking_wrapper cos2x_i/i_p_sqr0_b : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is tracking_wrapper cos2x_i/q_p_sqr0_d : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB1 ac_12 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 ad_16 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 bc_15 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 bd_14 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w0_c : 0 0 : 2196 2196 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w0_f : 0 0 : 2073 2073 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_e : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_a : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1f : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_21 : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1a : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1d : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_17 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_5 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_9 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_11 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_22 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_7 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is tracking_wrapper mult10_6 : 0 0 : 433 433 : Used 9 time 0
- Sort Area is tracking_wrapper mult10_a : 0 0 : 403 403 : Used 9 time 0
- Sort Area is tracking_wrapper mult20_8 : 0 0 : 403 403 : Used 9 time 0
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-ROM: Preliminary Mapping Report
-+----------------+----------------------+---------------+----------------+
-|Module Name | RTL Object | Depth x Width | Implemented As |
-+----------------+----------------------+---------------+----------------+
-|TLROM | _GEN | 256x64 | LUT |
-|acq_nco_carr | freq_word_arr | 64x13 | LUT |
-|acq_nco_carr | pullin_freq_word_arr | 16x11 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_ca_gen | p_0_out | 32x8 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|cacode_gen_trck | p_0_out | 32x8 | LUT |
-+----------------+----------------------+---------------+----------------+
-
-
-Block RAM: Preliminary Mapping Report (see note below)
-+-------------------------------------------------+-------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+-------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|dcache/data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GCB1 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+-------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
-
-Distributed RAM: Preliminary Mapping Report (see note below)
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
-Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
-
-DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
-+---------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+---------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|MulAddRecFNPipe_l2_e11_s53 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | (PCIN>>17)+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | (PCIN>>17)+A*B | 25 | 8 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 16 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|NCO_carr | (A:0x6677)*B | 14 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 14 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | A*(B:0x6677) | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 18 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | A*(B:0x109) | 12 | 10 | - | - | 22 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x55) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x75) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 16 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (A:0x15940)*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 16 | 11 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*(B:0x15940) | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 11 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 14 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 14 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-+---------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:14 ; elapsed = 00:01:06 . Memory (MB): peak = 3297.180 ; gain = 1349.117 ; free physical = 4092 ; free virtual = 34871
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:02:20 ; elapsed = 00:01:12 . Memory (MB): peak = 3297.180 ; gain = 1349.117 ; free physical = 3963 ; free virtual = 34747
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Block RAM: Final Mapping Report
-+-------------------------------------------------+-------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+-------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|dcache/data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GCB1 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+-------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-
-Distributed RAM: Final Mapping Report
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/rockettilei_4/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/LF_carr.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/LF_code.sv:61]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/LF_code.sv:74]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/lock_detector.sv:68]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/lock_detector.sv:68]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/trck_top.sv:157]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/trck_top.sv:157]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/trck_top.sv:157]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/trck_top.sv:157]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv:100]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/lock_detector.sv:108]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/lock_detector.sv:108]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/lock_detector.sv:108]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/lock_detector.sv:108]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/lock_detector.sv:107]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/lock_detector.sv:107]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/lock_detector.sv:107]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/trck_src/lock_detector.sv:107]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:268]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:268]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:268]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:266]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:266]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:275]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:275]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:275]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:275]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:274]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:274]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:274]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:274]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:265]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:267]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:267]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:265]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:267]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:265]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:265]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:267]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:267]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:265]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:267]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:265]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:267]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:265]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:265]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:267]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:257]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:257]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:257]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:257]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:259]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:259]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:259]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:259]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:259]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:259]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:259]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:259]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/ankaoc/Desktop/tmp/gps/hardware/external/gps/rtl/pps/pps_core.sv:272]
-INFO: [Common 17-14] Message 'Synth 8-5844' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:02:24 ; elapsed = 00:01:20 . Memory (MB): peak = 3305.184 ; gain = 1357.121 ; free physical = 2449 ; free virtual = 33237
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:02:31 ; elapsed = 00:01:27 . Memory (MB): peak = 3421.207 ; gain = 1473.145 ; free physical = 2328 ; free virtual = 33160
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:02:32 ; elapsed = 00:01:28 . Memory (MB): peak = 3421.207 ; gain = 1473.145 ; free physical = 2325 ; free virtual = 33158
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:40 ; elapsed = 00:01:37 . Memory (MB): peak = 3632.816 ; gain = 1684.754 ; free physical = 2108 ; free virtual = 32941
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:02:41 ; elapsed = 00:01:37 . Memory (MB): peak = 3632.816 ; gain = 1684.754 ; free physical = 2066 ; free virtual = 32898
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:02:42 ; elapsed = 00:01:38 . Memory (MB): peak = 3644.691 ; gain = 1696.629 ; free physical = 2065 ; free virtual = 32897
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:02:42 ; elapsed = 00:01:38 . Memory (MB): peak = 3644.691 ; gain = 1696.629 ; free physical = 2064 ; free virtual = 32897
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Static Shift Register Report:
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|VCU118RocketSystem | tile_prci_domain/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-|VCU118RocketSystem | ibus/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-DSP Final Report (the ' indicates corresponding REG is set)
-+---------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+---------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-(A*B) | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 15 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 15 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 0 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 13 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 13 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 13 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 13 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 13 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 13 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 13 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 13 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 13 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 15 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 15 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | PCIN>>17+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e11_s53 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B' | 24 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | PCIN>>17+A*B | 24 | 7 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-+---------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-
-Report BlackBoxes:
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage:
-+------+-----------+------+
-| |Cell |Count |
-+------+-----------+------+
-|1 |BSCANE2 | 1|
-|2 |BUFG | 9|
-|3 |CARRY4 | 6514|
-|4 |DSP48E1 | 208|
-|10 |LUT1 | 2938|
-|11 |LUT2 | 16979|
-|12 |LUT3 | 10731|
-|13 |LUT4 | 8858|
-|14 |LUT5 | 13248|
-|15 |LUT6 | 25074|
-|16 |MMCME2_ADV | 3|
-|17 |MUXF7 | 1956|
-|18 |MUXF8 | 244|
-|19 |RAM32M | 222|
-|20 |RAM32X1D | 9|
-|21 |RAMB18E1 | 4|
-|23 |RAMB36E1 | 415|
-|45 |SRL16E | 2|
-|46 |STARTUPE2 | 1|
-|47 |FDCE | 42235|
-|48 |FDPE | 373|
-|49 |FDRE | 10066|
-|50 |FDSE | 184|
-|51 |LDC | 9|
-|52 |IBUF | 8|
-|53 |IBUFDS | 1|
-|54 |IOBUF | 8|
-|55 |OBUF | 13|
-+------+-----------+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:02:42 ; elapsed = 00:01:39 . Memory (MB): peak = 3644.691 ; gain = 1696.629 ; free physical = 2064 ; free virtual = 32896
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 605 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:02:32 ; elapsed = 00:01:37 . Memory (MB): peak = 3648.605 ; gain = 1181.465 ; free physical = 9243 ; free virtual = 40075
-Synthesis Optimization Complete : Time (s): cpu = 00:02:42 ; elapsed = 00:01:43 . Memory (MB): peak = 3648.605 ; gain = 1700.543 ; free physical = 9258 ; free virtual = 40081
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.63 . Memory (MB): peak = 3648.605 ; gain = 0.000 ; free physical = 9292 ; free virtual = 40115
-INFO: [Netlist 29-17] Analyzing 9594 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Finished Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4010.840 ; gain = 0.000 ; free physical = 9202 ; free virtual = 40025
-INFO: [Project 1-111] Unisim Transformation Summary:
- A total of 248 instances were transformed.
- IOBUF => IOBUF (IBUF, OBUFT): 8 instances
- LDC => LDCE: 9 instances
- RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 222 instances
- RAM32X1D => RAM32X1D (RAMD32(x2)): 9 instances
-
-Synth Design complete | Checksum: 5c121bc
-INFO: [Common 17-83] Releasing license: Synthesis
-727 Infos, 387 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:02:55 ; elapsed = 00:01:56 . Memory (MB): peak = 4010.875 ; gain = 2062.812 ; free physical = 9197 ; free virtual = 40020
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 10853.477; main = 2691.980; forked = 8908.355
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 20182.770; main = 4010.844; forked = 16889.504
-# apply_genesys2_async_clock_groups
-Applying Genesys2 async clock groups.
-# write_checkpoint -force [file join $checkpoint_dir post_synth.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4042.855 ; gain = 0.000 ; free physical = 9190 ; free virtual = 40012
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4042.855 ; gain = 0.000 ; free physical = 9190 ; free virtual = 40012
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4042.855 ; gain = 0.000 ; free physical = 9190 ; free virtual = 40012
-Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4042.855 ; gain = 0.000 ; free physical = 9190 ; free virtual = 40013
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4042.855 ; gain = 0.000 ; free physical = 9190 ; free virtual = 40013
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4042.855 ; gain = 0.000 ; free physical = 9190 ; free virtual = 40013
-Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4042.855 ; gain = 0.000 ; free physical = 9190 ; free virtual = 40013
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.1 . Memory (MB): peak = 4042.855 ; gain = 0.000 ; free physical = 9175 ; free virtual = 40011
-INFO: [Common 17-1381] The checkpoint '/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/checkpoints/post_synth.dcp' has been generated.
-# report_utilization -hierarchical -file [file join $report_dir synth_utilization_hier.rpt]
-# report_utilization -file [file join $report_dir synth_utilization.rpt]
-# report_timing_summary -file [file join $report_dir synth_timing_summary.rpt]
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 32 CPUs
-# puts "Running implementation..."
-Running implementation...
-# opt_design
-Command: opt_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-Running DRC as a precondition to command opt_design
-
-Starting DRC Task
-INFO: [DRC 23-27] Running DRC with 32 threads
-INFO: [Project 1-461] DRC finished with 0 Errors
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.58 . Memory (MB): peak = 4437.574 ; gain = 385.812 ; free physical = 9127 ; free virtual = 39952
-
-Starting Cache Timing Information Task
-Ending Cache Timing Information Task | Checksum: 11e5cb814
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 9127 ; free virtual = 39952
-
-Starting Logic Optimization Task
-
-Phase 1 Initialization
-
-Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 11e5cb814
-
-Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 9028 ; free virtual = 39853
-
-Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 11e5cb814
-
-Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 9020 ; free virtual = 39845
-Phase 1 Initialization | Checksum: 11e5cb814
-
-Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 9020 ; free virtual = 39845
-
-Phase 2 Timer Update And Timing Data Collection
-
-Phase 2.1 Detect if minReqCache needed
-Phase 2.1 Detect if minReqCache needed | Checksum: 11e5cb814
-
-Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8988 ; free virtual = 39813
-
-Phase 2.2 Timer Update
-Phase 2.2 Timer Update | Checksum: 11e5cb814
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:00.88 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8985 ; free virtual = 39810
-
-Phase 2.3 Timing Data Collection
-Phase 2.3 Timing Data Collection | Checksum: 11e5cb814
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:00.94 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8985 ; free virtual = 39810
-Phase 2 Timer Update And Timing Data Collection | Checksum: 11e5cb814
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:00.95 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8985 ; free virtual = 39810
-
-Phase 3 Retarget
-INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
-INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
-INFO: [Opt 31-1566] Pulled 30 inverters resulting in an inversion of 662 pins
-INFO: [Opt 31-138] Pushed 14 inverter(s) to 130 load pin(s).
-INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: ebbf1bf5
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8985 ; free virtual = 39810
-Retarget | Checksum: ebbf1bf5
-INFO: [Opt 31-389] Phase Retarget created 678 cells and removed 721 cells
-INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 4 Constant propagation
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 17d40ef15
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8984 ; free virtual = 39809
-Constant propagation | Checksum: 17d40ef15
-INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 1 cells
-
-Phase 5 Sweep
-INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
-Done building netlist checker database: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8966 ; free virtual = 39791
-Phase 5 Sweep | Checksum: 194708eb6
-
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8961 ; free virtual = 39787
-Sweep | Checksum: 194708eb6
-INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 6 cells
-INFO: [Opt 31-1021] In phase Sweep, 360 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 6 BUFG optimization
-Phase 6 BUFG optimization | Checksum: 194708eb6
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8969 ; free virtual = 39794
-BUFG optimization | Checksum: 194708eb6
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
-
-Phase 7 Shift Register Optimization
-INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 194708eb6
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8969 ; free virtual = 39794
-Shift Register Optimization | Checksum: 194708eb6
-INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
-
-Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 194708eb6
-
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8969 ; free virtual = 39794
-Post Processing Netlist | Checksum: 194708eb6
-INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
-
-Phase 9 Finalization
-
-Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: feaf0511
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8969 ; free virtual = 39794
-
-Phase 9.2 Verifying Netlist Connectivity
-
-Starting Connectivity Check Task
-
-Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8969 ; free virtual = 39794
-Phase 9.2 Verifying Netlist Connectivity | Checksum: feaf0511
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8969 ; free virtual = 39794
-Phase 9 Finalization | Checksum: feaf0511
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8969 ; free virtual = 39794
-Opt_design Change Summary
-=========================
-
-
--------------------------------------------------------------------------------------------------------------------------
-| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
--------------------------------------------------------------------------------------------------------------------------
-| Retarget | 678 | 721 | 1 |
-| Constant propagation | 0 | 1 | 0 |
-| Sweep | 0 | 6 | 360 |
-| BUFG optimization | 0 | 0 | 0 |
-| Shift Register Optimization | 0 | 0 | 0 |
-| Post Processing Netlist | 0 | 0 | 0 |
--------------------------------------------------------------------------------------------------------------------------
-
-
-Ending Logic Optimization Task | Checksum: feaf0511
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 4437.574 ; gain = 0.000 ; free physical = 8969 ; free virtual = 39794
-
-Starting Power Optimization Task
-INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-INFO: [Power 33-23] Power model is not available for u_cfg_flash_startup
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running Vector-less Activity Propagation...
-
-Finished Running Vector-less Activity Propagation
-INFO: [Pwropt 34-9] Applying IDT optimizations ...
-INFO: [Pwropt 34-10] Applying ODC optimizations ...
-
-
-Starting PowerOpt Patch Enables Task
-INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 419 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
-INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
-Number of BRAM Ports augmented: 0 newly gated: 84 Total Ports: 838
-Ending PowerOpt Patch Enables Task | Checksum: 20e0287a5
-
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.78 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8344 ; free virtual = 39169
-Ending Power Optimization Task | Checksum: 20e0287a5
-
-Time (s): cpu = 00:00:33 ; elapsed = 00:00:15 . Memory (MB): peak = 5213.906 ; gain = 776.332 ; free physical = 8344 ; free virtual = 39169
-
-Starting Final Cleanup Task
-
-Starting Logic Optimization Task
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Logic Optimization Task | Checksum: df01f2f4
-
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:03 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8385 ; free virtual = 39210
-Ending Final Cleanup Task | Checksum: df01f2f4
-
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:04 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8390 ; free virtual = 39215
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8392 ; free virtual = 39217
-INFO: [Common 17-83] Releasing license: Implementation
-29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-opt_design completed successfully
-opt_design: Time (s): cpu = 00:01:03 ; elapsed = 00:00:27 . Memory (MB): peak = 5213.906 ; gain = 1162.145 ; free physical = 8398 ; free virtual = 39223
-# write_checkpoint -force [file join $checkpoint_dir post_opt.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8396 ; free virtual = 39222
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8396 ; free virtual = 39222
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8396 ; free virtual = 39222
-Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8396 ; free virtual = 39222
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8396 ; free virtual = 39222
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8396 ; free virtual = 39223
-Write Physdb Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8396 ; free virtual = 39223
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.1 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8384 ; free virtual = 39222
-INFO: [Common 17-1381] The checkpoint '/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/checkpoints/post_opt.dcp' has been generated.
-# place_design
-Command: place_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-83] Releasing license: Implementation
-INFO: [DRC 23-27] Running DRC with 32 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running DRC as a precondition to command place_design
-INFO: [DRC 23-27] Running DRC with 32 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 32 CPUs
-
-Starting Placer Task
-
-Phase 1 Placer Initialization
-
-Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8453 ; free virtual = 39280
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: af7c217b
-
-Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8453 ; free virtual = 39281
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8453 ; free virtual = 39281
-
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 111669c7b
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8468 ; free virtual = 39296
-
-Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 13aa6699d
-
-Time (s): cpu = 00:00:42 ; elapsed = 00:00:12 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8349 ; free virtual = 39177
-
-Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 13aa6699d
-
-Time (s): cpu = 00:00:42 ; elapsed = 00:00:12 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8350 ; free virtual = 39178
-Phase 1 Placer Initialization | Checksum: 13aa6699d
-
-Time (s): cpu = 00:00:42 ; elapsed = 00:00:12 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8349 ; free virtual = 39177
-
-Phase 2 Global Placement
-
-Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 131a5db3c
-
-Time (s): cpu = 00:00:58 ; elapsed = 00:00:15 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8399 ; free virtual = 39226
-
-Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1eb372648
-
-Time (s): cpu = 00:01:16 ; elapsed = 00:00:17 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8395 ; free virtual = 39221
-
-Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 1eb372648
-
-Time (s): cpu = 00:01:16 ; elapsed = 00:00:17 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8394 ; free virtual = 39221
-
-Phase 2.4 Global Place Phase1
-Phase 2.4 Global Place Phase1 | Checksum: 2006efade
-
-Time (s): cpu = 00:02:21 ; elapsed = 00:00:38 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8386 ; free virtual = 39213
-
-Phase 2.5 Global Place Phase2
-
-Phase 2.5.1 UpdateTiming Before Physical Synthesis
-Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 1627b51b5
-
-Time (s): cpu = 00:02:40 ; elapsed = 00:00:40 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8399 ; free virtual = 39226
-
-Phase 2.5.2 Physical Synthesis In Placer
-INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 4144 LUT instances to create LUTNM shape
-INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
-INFO: [Physopt 32-1138] End 1 Pass. Optimized 1058 nets or LUTs. Breaked 0 LUT, combined 1058 existing LUTs and moved 0 existing LUT
-INFO: [Physopt 32-65] No nets found for high-fanout optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
-INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
-INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
-INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8435 ; free virtual = 39263
-
-Summary of Physical Synthesis Optimizations
-============================================
-
-
------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
------------------------------------------------------------------------------------------------------------------------------------------------------------
-| LUT Combining | 0 | 1058 | 1058 | 0 | 1 | 00:00:01 |
-| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Total | 0 | 1058 | 1058 | 0 | 9 | 00:00:02 |
------------------------------------------------------------------------------------------------------------------------------------------------------------
-
-
-Phase 2.5.2 Physical Synthesis In Placer | Checksum: 2a14ef70f
-
-Time (s): cpu = 00:02:58 ; elapsed = 00:00:45 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8454 ; free virtual = 39281
-Phase 2.5 Global Place Phase2 | Checksum: 1f54a697e
-
-Time (s): cpu = 00:03:01 ; elapsed = 00:00:47 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8461 ; free virtual = 39288
-Phase 2 Global Placement | Checksum: 1f54a697e
-
-Time (s): cpu = 00:03:01 ; elapsed = 00:00:47 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8461 ; free virtual = 39288
-
-Phase 3 Detail Placement
-
-Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 2ab90ea2b
-
-Time (s): cpu = 00:03:17 ; elapsed = 00:00:49 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8462 ; free virtual = 39289
-
-Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 185fbbc74
-
-Time (s): cpu = 00:03:48 ; elapsed = 00:00:55 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8468 ; free virtual = 39295
-
-Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 18bb5967a
-
-Time (s): cpu = 00:03:49 ; elapsed = 00:00:56 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8470 ; free virtual = 39296
-
-Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 20240e8ff
-
-Time (s): cpu = 00:03:49 ; elapsed = 00:00:56 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8469 ; free virtual = 39296
-
-Phase 3.5 Fast Optimization
-Phase 3.5 Fast Optimization | Checksum: 1b3efd78c
-
-Time (s): cpu = 00:04:36 ; elapsed = 00:01:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8465 ; free virtual = 39292
-
-Phase 3.6 Small Shape Detail Placement
-Phase 3.6 Small Shape Detail Placement | Checksum: 1b786527c
-
-Time (s): cpu = 00:04:49 ; elapsed = 00:01:12 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8458 ; free virtual = 39285
-
-Phase 3.7 Re-assign LUT pins
-Phase 3.7 Re-assign LUT pins | Checksum: 1d2088456
-
-Time (s): cpu = 00:04:52 ; elapsed = 00:01:15 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8462 ; free virtual = 39289
-
-Phase 3.8 Pipeline Register Optimization
-Phase 3.8 Pipeline Register Optimization | Checksum: 255798617
-
-Time (s): cpu = 00:04:52 ; elapsed = 00:01:15 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8462 ; free virtual = 39289
-
-Phase 3.9 Fast Optimization
-Phase 3.9 Fast Optimization | Checksum: 1624c859d
-
-Time (s): cpu = 00:06:54 ; elapsed = 00:01:22 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8421 ; free virtual = 39248
-Phase 3 Detail Placement | Checksum: 1624c859d
-
-Time (s): cpu = 00:06:54 ; elapsed = 00:01:22 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8425 ; free virtual = 39252
-
-Phase 4 Post Placement Optimization and Clean-Up
-
-Phase 4.1 Post Commit Optimization
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-
-Phase 4.1.1 Post Placement Optimization
-Post Placement Optimization Initialization | Checksum: 19748e948
-
-Phase 4.1.1.1 BUFG Insertion
-
-Starting Physical Synthesis Task
-
-Phase 1 Physical Synthesis Initialization
-INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 32 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.521 | TNS=-1.889 |
-Phase 1 Physical Synthesis Initialization | Checksum: 152ca3a28
-
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.51 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8394 ; free virtual = 39221
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/sync_0_reg, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/trckReset_gps_trck_reset/io_sync_reset_chain/output_chain/sync_0_reg_1, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_1, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-56] BUFG insertion identified 11 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 11, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
-Ending Physical Synthesis Task | Checksum: 1450732e8
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8398 ; free virtual = 39226
-Phase 4.1.1.1 BUFG Insertion | Checksum: 19748e948
-
-Time (s): cpu = 00:08:34 ; elapsed = 00:01:31 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8394 ; free virtual = 39222
-
-Phase 4.1.1.2 Post Placement Timing Optimization
-INFO: [Place 30-746] Post Placement Timing Summary WNS=0.084. For the most accurate timing information please run report_timing.
-Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1d8cdaaad
-
-Time (s): cpu = 00:11:36 ; elapsed = 00:01:47 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8432 ; free virtual = 39260
-
-Time (s): cpu = 00:11:36 ; elapsed = 00:01:47 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8432 ; free virtual = 39260
-Phase 4.1 Post Commit Optimization | Checksum: 1d8cdaaad
-
-Time (s): cpu = 00:11:36 ; elapsed = 00:01:47 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8429 ; free virtual = 39257
-
-Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 1d8cdaaad
-
-Time (s): cpu = 00:11:37 ; elapsed = 00:01:47 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8431 ; free virtual = 39258
-
-Phase 4.3 Placer Reporting
-
-Phase 4.3.1 Print Estimated Congestion
-INFO: [Place 30-612] Post-Placement Estimated Congestion
- ____________________________________________________
-| | Global Congestion | Short Congestion |
-| Direction | Region Size | Region Size |
-|___________|___________________|___________________|
-| North| 2x2| 2x2|
-|___________|___________________|___________________|
-| South| 1x1| 4x4|
-|___________|___________________|___________________|
-| East| 1x1| 2x2|
-|___________|___________________|___________________|
-| West| 1x1| 2x2|
-|___________|___________________|___________________|
-
-Phase 4.3.1 Print Estimated Congestion | Checksum: 1d8cdaaad
-
-Time (s): cpu = 00:11:37 ; elapsed = 00:01:48 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8432 ; free virtual = 39259
-Phase 4.3 Placer Reporting | Checksum: 1d8cdaaad
-
-Time (s): cpu = 00:11:38 ; elapsed = 00:01:48 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8432 ; free virtual = 39259
-
-Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8431 ; free virtual = 39259
-
-Time (s): cpu = 00:11:38 ; elapsed = 00:01:48 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8431 ; free virtual = 39259
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1aaefcd94
-
-Time (s): cpu = 00:11:38 ; elapsed = 00:01:48 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8429 ; free virtual = 39256
-Ending Placer Task | Checksum: 137bd36fe
-
-Time (s): cpu = 00:11:39 ; elapsed = 00:01:48 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8428 ; free virtual = 39256
-48 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-place_design completed successfully
-place_design: Time (s): cpu = 00:11:53 ; elapsed = 00:01:51 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8428 ; free virtual = 39256
-# write_checkpoint -force [file join $checkpoint_dir post_place.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8428 ; free virtual = 39256
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8428 ; free virtual = 39256
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8428 ; free virtual = 39256
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.13 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8404 ; free virtual = 39254
-Wrote PlaceStorage: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8301 ; free virtual = 39250
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8291 ; free virtual = 39251
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8291 ; free virtual = 39252
-Write Physdb Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8290 ; free virtual = 39251
-INFO: [Common 17-1381] The checkpoint '/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/checkpoints/post_place.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8348 ; free virtual = 39180
-# phys_opt_design -directive Explore
-Command: phys_opt_design -directive Explore
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
-
-Starting Initial Update Timing Task
-
-Time (s): cpu = 00:01:31 ; elapsed = 00:00:05 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8401 ; free virtual = 39233
-INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 0.084 | TNS= 0.000 |
-INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
-INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
-INFO: [Common 17-83] Releasing license: Implementation
-6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-phys_opt_design completed successfully
-phys_opt_design: Time (s): cpu = 00:01:32 ; elapsed = 00:00:06 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8401 ; free virtual = 39232
-# write_checkpoint -force [file join $checkpoint_dir post_phys_opt.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8401 ; free virtual = 39233
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8401 ; free virtual = 39233
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8403 ; free virtual = 39235
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.12 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8382 ; free virtual = 39235
-Wrote PlaceStorage: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8287 ; free virtual = 39241
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8276 ; free virtual = 39240
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8276 ; free virtual = 39241
-Write Physdb Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8275 ; free virtual = 39240
-INFO: [Common 17-1381] The checkpoint '/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/checkpoints/post_phys_opt.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8427 ; free virtual = 39263
-# route_design
-Command: route_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-
-
-Starting Routing Task
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 32 CPUs
-
-Phase 1 Build RT Design
-Checksum: PlaceDB: 9ba2b8f1 ConstDB: 0 ShapeSum: 739f03bd RouteDB: 287b7a50
-Post Restoration Checksum: NetGraph: d9c67fbd | NumContArr: 1128fd2a | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 270417221
-
-Time (s): cpu = 00:02:27 ; elapsed = 00:00:16 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8442 ; free virtual = 39274
-
-Phase 2 Router Initialization
-
-Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 270417221
-
-Time (s): cpu = 00:02:28 ; elapsed = 00:00:16 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8442 ; free virtual = 39274
-
-Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 270417221
-
-Time (s): cpu = 00:02:28 ; elapsed = 00:00:16 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8442 ; free virtual = 39274
- Number of Nodes with overlaps = 0
-
-Phase 2.3 Update Timing
-Phase 2.3 Update Timing | Checksum: 1e61ed447
-
-Time (s): cpu = 00:04:56 ; elapsed = 00:00:27 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8343 ; free virtual = 39183
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.126 | TNS=0.000 | WHS=-0.371 | THS=-2663.155|
-
-
-Phase 2.4 Soft Constraint Pins - Fast Budgeting
-Phase 2.4 Soft Constraint Pins - Fast Budgeting | Checksum: 1c35cd151
-
-Time (s): cpu = 00:05:12 ; elapsed = 00:00:29 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8344 ; free virtual = 39184
-
-Router Utilization Summary
- Global Vertical Routing Utilization = 0.00187274 %
- Global Horizontal Routing Utilization = 0.00159796 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 116850
- (Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 116831
- Number of Partially Routed Nets = 19
- Number of Node Overlaps = 2
-
-Phase 2 Router Initialization | Checksum: 1b8c92979
-
-Time (s): cpu = 00:05:14 ; elapsed = 00:00:29 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8298 ; free virtual = 39138
-
-Phase 3 Global Routing
-Phase 3 Global Routing | Checksum: 1b8c92979
-
-Time (s): cpu = 00:05:14 ; elapsed = 00:00:29 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8298 ; free virtual = 39138
-
-Phase 4 Initial Routing
-
-Phase 4.1 Initial Net Routing Pass
-Phase 4.1 Initial Net Routing Pass | Checksum: 1777ade1a
-
-Time (s): cpu = 00:05:43 ; elapsed = 00:00:36 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8315 ; free virtual = 39155
-Phase 4 Initial Routing | Checksum: 1777ade1a
-
-Time (s): cpu = 00:05:44 ; elapsed = 00:00:36 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 8315 ; free virtual = 39155
-
-Phase 5 Rip-up And Reroute
-
-Phase 5.1 Global Iteration 0
- Number of Nodes with overlaps = 9683
- Number of Nodes with overlaps = 119
- Number of Nodes with overlaps = 4
- Number of Nodes with overlaps = 2
- Number of Nodes with overlaps = 0
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.080 | TNS=0.000 | WHS=N/A | THS=N/A |
-
-Phase 5.1 Global Iteration 0 | Checksum: 29ec52a51
-
-Time (s): cpu = 00:06:43 ; elapsed = 00:00:56 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7871 ; free virtual = 39065
-Phase 5 Rip-up And Reroute | Checksum: 29ec52a51
-
-Time (s): cpu = 00:06:43 ; elapsed = 00:00:56 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7878 ; free virtual = 39072
-
-Phase 6 Delay and Skew Optimization
-
-Phase 6.1 Delay CleanUp
-Phase 6.1 Delay CleanUp | Checksum: 29ec52a51
-
-Time (s): cpu = 00:06:43 ; elapsed = 00:00:56 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7877 ; free virtual = 39072
-
-Phase 6.2 Clock Skew Optimization
-Phase 6.2 Clock Skew Optimization | Checksum: 29ec52a51
-
-Time (s): cpu = 00:06:43 ; elapsed = 00:00:56 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7877 ; free virtual = 39072
-Phase 6 Delay and Skew Optimization | Checksum: 29ec52a51
-
-Time (s): cpu = 00:06:44 ; elapsed = 00:00:56 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7878 ; free virtual = 39072
-
-Phase 7 Post Hold Fix
-
-Phase 7.1 Hold Fix Iter
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.080 | TNS=0.000 | WHS=0.056 | THS=0.000 |
-
-Phase 7.1 Hold Fix Iter | Checksum: 26176c50f
-
-Time (s): cpu = 00:06:52 ; elapsed = 00:00:57 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7881 ; free virtual = 39076
-Phase 7 Post Hold Fix | Checksum: 26176c50f
-
-Time (s): cpu = 00:06:52 ; elapsed = 00:00:57 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7881 ; free virtual = 39076
-
-Phase 8 Route finalize
-
-Router Utilization Summary
- Global Vertical Routing Utilization = 10.2628 %
- Global Horizontal Routing Utilization = 11.3066 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 0
- (Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 0
- Number of Partially Routed Nets = 0
- Number of Node Overlaps = 0
-
-Phase 8 Route finalize | Checksum: 26176c50f
-
-Time (s): cpu = 00:06:53 ; elapsed = 00:00:57 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7881 ; free virtual = 39075
-
-Phase 9 Verifying routed nets
-
- Verification completed successfully
-Phase 9 Verifying routed nets | Checksum: 26176c50f
-
-Time (s): cpu = 00:06:53 ; elapsed = 00:00:57 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7882 ; free virtual = 39076
-
-Phase 10 Depositing Routes
-Phase 10 Depositing Routes | Checksum: 1a70b7d29
-
-Time (s): cpu = 00:07:00 ; elapsed = 00:01:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7842 ; free virtual = 39039
-
-Phase 11 Post Process Routing
-Phase 11 Post Process Routing | Checksum: 1a70b7d29
-
-Time (s): cpu = 00:07:00 ; elapsed = 00:01:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7842 ; free virtual = 39039
-
-Phase 12 Post Router Timing
-INFO: [Route 35-57] Estimated Timing Summary | WNS=0.080 | TNS=0.000 | WHS=0.056 | THS=0.000 |
-
-INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
-Phase 12 Post Router Timing | Checksum: 1a70b7d29
-
-Time (s): cpu = 00:07:01 ; elapsed = 00:01:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7841 ; free virtual = 39038
-Total Elapsed time in route_design: 60.37 secs
-
-Phase 13 Post-Route Event Processing
-Phase 13 Post-Route Event Processing | Checksum: 1f95de3e9
-
-Time (s): cpu = 00:07:01 ; elapsed = 00:01:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7841 ; free virtual = 39038
-INFO: [Route 35-16] Router Completed Successfully
-Ending Routing Task | Checksum: 1f95de3e9
-
-Time (s): cpu = 00:07:02 ; elapsed = 00:01:01 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7841 ; free virtual = 39038
-
-Routing Is Done.
-INFO: [Common 17-83] Releasing license: Implementation
-9 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-route_design completed successfully
-route_design: Time (s): cpu = 00:07:02 ; elapsed = 00:01:01 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7841 ; free virtual = 39038
-# write_checkpoint -force [file join $checkpoint_dir post_route.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7844 ; free virtual = 39041
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7844 ; free virtual = 39041
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.14 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7835 ; free virtual = 39050
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.5 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7801 ; free virtual = 39063
-Wrote PlaceStorage: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7659 ; free virtual = 39002
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7652 ; free virtual = 39004
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7652 ; free virtual = 39005
-Write Physdb Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7652 ; free virtual = 39005
-INFO: [Common 17-1381] The checkpoint '/home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/build/checkpoints/post_route.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7828 ; free virtual = 39031
-# report_utilization -file [file join $report_dir route_utilization.rpt]
-# report_timing_summary -file [file join $report_dir route_timing_summary.rpt]
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 32 CPUs
-report_timing_summary: Time (s): cpu = 00:02:18 ; elapsed = 00:00:08 . Memory (MB): peak = 5213.906 ; gain = 0.000 ; free physical = 7815 ; free virtual = 39017
-# report_drc -file [file join $report_dir route_drc.rpt]
-Command: report_drc -file /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/reports/route_drc.rpt
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.2/data/ip'.
-INFO: [DRC 23-27] Running DRC with 32 threads
-INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/reports/route_drc.rpt.
-report_drc completed successfully
-# report_power -file [file join $report_dir route_power.rpt]
-Command: report_power -file /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/reports/route_power.rpt
-INFO: [Power 33-23] Power model is not available for u_cfg_flash_startup
-Running Vector-less Activity Propagation...
-
-Finished Running Vector-less Activity Propagation
-WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
-Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
-1 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
-report_power completed successfully
-report_power: Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 5322.441 ; gain = 108.535 ; free physical = 7744 ; free virtual = 38950
-# set bit_file [file join $bit_dir genesys2_rocket.bit]
-# puts "Writing bitstream: $bit_file"
-Writing bitstream: /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-# write_bitstream -force $bit_file
-Command: write_bitstream -force /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-Running DRC as a precondition to command write_bitstream
-INFO: [IP_Flow 19-1839] IP Catalog is up to date.
-INFO: [DRC 23-27] Running DRC with 32 threads
-INFO: [Vivado 12-3199] DRC finished with 0 Errors
-INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
-Integrating Hard IP ELF/MEM with the PDI.
-INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
-Loading data files...
-Loading site data...
-Loading route data...
-Processing options...
-Creating bitmap...
-Creating bitstream...
-Writing bitstream /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit...
-INFO: [Vivado 12-1842] Bitgen Completed Successfully.
-INFO: [Common 17-83] Releasing license: Implementation
-8 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:01:41 ; elapsed = 00:00:32 . Memory (MB): peak = 5369.695 ; gain = 47.254 ; free physical = 7360 ; free virtual = 38632
-# puts "Genesys2 non-project flow complete."
-Genesys2 non-project flow complete.
-INFO: [Common 17-206] Exiting Vivado at Thu Aug 6 21:34:17 2026...
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream_116693.backup.jou b/targets/fpga/genesys2/out/logs/build_bitstream_116693.backup.jou
deleted file mode 100644
index ee8103f..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream_116693.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 17:40:26 2026
-# Process ID : 116693
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21743 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream_116693.backup.log b/targets/fpga/genesys2/out/logs/build_bitstream_116693.backup.log
deleted file mode 100644
index c85ed3c..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream_116693.backup.log
+++ /dev/null
@@ -1,3820 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 17:40:26 2026
-# Process ID : 116693
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21743 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../../..]]
-# set repo_dir [file normalize [file join $fpga_dir ../../..]]
-# set hardware_dir [file join $repo_dir hardware]
-# cd $repo_dir
-# set part_name "xc7k325tffg900-2"
-# set board_part "digilentinc.com:genesys2:part0:1.1"
-# set top_module "genesys2_rocket_top"
-# set out_dir [file join $fpga_dir out]
-# set generated_dir [file join $out_dir build generated]
-# set report_dir [file join $out_dir reports]
-# set bit_dir [file join $out_dir bitstream]
-# set checkpoint_dir [file join $out_dir build checkpoints]
-# file mkdir $generated_dir
-# file mkdir $report_dir
-# file mkdir $bit_dir
-# file mkdir $checkpoint_dir
-# set rocket_rtl_dir [file join $hardware_dir generated genesys2-soc-verilog]
-# set rocket_top [file join $rocket_rtl_dir VCU118RocketSystem.sv]
-# set rocket_filelist [file join $rocket_rtl_dir filelist.f]
-# set wrapper [file join $generated_dir ${top_module}.sv]
-# if {[info exists ::env(GPS_SYSTEM_DIR)] && [string trim $::env(GPS_SYSTEM_DIR)] ne ""} {
-# set gps_system_dir [file normalize $::env(GPS_SYSTEM_DIR)]
-# } else {
-# set gps_system_dir [file join $hardware_dir external gps rtl]
-# }
-# if {[info exists ::env(RF_INPUT_MODE)]} {
-# set rf_input_mode [string tolower [string trim $::env(RF_INPUT_MODE)]]
-# } else {
-# set rf_input_mode "pmod"
-# }
-# if {$rf_input_mode ni {"pmod" "generated" "ethernet"}} {
-# error "Unsupported Genesys2 RF_INPUT_MODE=$rf_input_mode. Use pmod, generated, or ethernet."
-# }
-# if {![file exists $rocket_filelist]} {
-# error "Rocket Verilog filelist not found: $rocket_filelist"
-# }
-# if {![file exists $rocket_top]} {
-# error "Rocket top Verilog not found: $rocket_top"
-# }
-# puts "Generating Genesys2 wrapper: $wrapper"
-Generating Genesys2 wrapper: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv
-# puts "Genesys2 RF input mode: $rf_input_mode"
-Genesys2 RF input mode: pmod
-# exec python3 [file join $fpga_dir tools gen_genesys2_wrapper.py] \
-# --rocket-top $rocket_top \
-# --out $wrapper \
-# --rf-input-mode $rf_input_mode
-# set max_threads [string trim [exec nproc]]
-# puts "Using Vivado maxThreads=$max_threads"
-Using Vivado maxThreads=12
-# set_param general.maxThreads $max_threads
-# set_part $part_name
-INFO: [Coretcl 2-1500] The part has been set to 'xc7k325tffg900-2' for the current project only. Run set_part -help for more details. To evaluate different speed grades in the current design, use the set_speed_grade command, or use the open_checkpoint -part command to change the part used by an existing checkpoint design.
-# if {[llength [get_board_parts -quiet $board_part]] != 0} {
-# set_property board_part $board_part [current_project]
-# }
-# proc apply_genesys2_async_clock_groups {} {
-# set fabric_clk [get_clocks -quiet pll_fabric_clk]
-# set gps_acq_clk [get_clocks -quiet pll_gps_acq_clk]
-# set gps_trck_clk [get_clocks -quiet pll_gps_trck_clk]
-# set gps_rf_clk [get_clocks -quiet {pll_gps_rf_exact_clk pmod_rf_clk}]
-# set eth_clk [get_clocks -quiet genesys2_eth_rxck]
-#
-# if {[llength $fabric_clk] == 0 ||
-# [llength $gps_acq_clk] == 0 ||
-# [llength $gps_trck_clk] == 0 ||
-# [llength $gps_rf_clk] == 0} {
-# puts "Warning: not all Genesys2 async clock groups are available yet."
-# return
-# }
-#
-# puts "Applying Genesys2 async clock groups."
-# set args [list -asynchronous \
-# -group $fabric_clk \
-# -group $gps_acq_clk \
-# -group $gps_trck_clk \
-# -group $gps_rf_clk]
-# if {[llength $eth_clk] != 0} {
-# lappend args -group $eth_clk
-# }
-# set_clock_groups {*}$args
-# }
-# set rocket_files {}
-# set fh [open $rocket_filelist r]
-# while {[gets $fh line] >= 0} {
-# set line [string trim $line]
-# if {$line eq ""} {
-# continue
-# }
-# set line [regsub {^\./} $line ""]
-# lappend rocket_files [file normalize [file join $rocket_rtl_dir $line]]
-# }
-# close $fh
-# puts "Reading Rocket Chip RTL..."
-Reading Rocket Chip RTL...
-# read_verilog -sv $rocket_files
-# read_verilog [file join $hardware_dir upstream rocket-chip src main resources vsrc plusarg_reader.v]
-# set gps_filelist [file join $hardware_dir external gps rtl filelist.f]
-# set gps_files {}
-# set gps_fh [open $gps_filelist r]
-# while {[gets $gps_fh rel] >= 0} {
-# set rel [string trim $rel]
-# if {$rel eq "" || [string match "#*" $rel]} {
-# continue
-# }
-# lappend gps_files [file join $gps_system_dir $rel]
-# }
-# close $gps_fh
-# puts "Reading GPS APB wrapper RTL from $gps_system_dir..."
-Reading GPS APB wrapper RTL from /home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl...
-# set_property include_dirs [list [file join $gps_system_dir trck_src pulp_fifo]] [current_fileset]
-# read_verilog -sv $gps_files
-# puts "Reading Genesys2 shell RTL..."
-Reading Genesys2 shell RTL...
-# set shell_files [list \
-# [file join $hardware_dir fpga vcu118 rtl axi4_ram_64.sv] \
-# [file join $hardware_dir fpga vcu118 rtl axi4_slave_tieoff_64.sv] \
-# [file join $hardware_dir fpga genesys2 rtl rocket_bscan_dmi_tunnel.sv] \
-# ]
-# if {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet RF RTL..."
-# lappend shell_files \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_async_fifo.sv] \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_core.sv] \
-# [file join $hardware_dir fpga genesys2 rtl ethernet_rf eth_rf_genesys2.sv]
-# } else {
-# puts "Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=$rf_input_mode."
-# }
-Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=pmod.
-# read_verilog -sv $shell_files
-# read_verilog -sv $wrapper
-# puts "Reading constraints..."
-Reading constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_rocket.xdc]
-# puts "Reading Genesys2 PMOD SPI constraints..."
-Reading Genesys2 PMOD SPI constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_spi.xdc]
-# puts "Reading Genesys2 PMOD sensor IRQ constraints..."
-Reading Genesys2 PMOD sensor IRQ constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_irq.xdc]
-# puts "Reading Genesys2 PMOD PPS constraints..."
-Reading Genesys2 PMOD PPS constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_pps.xdc]
-# if {$rf_input_mode eq "pmod"} {
-# puts "Reading Genesys2 PMOD RF constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_rf.xdc]
-# } elseif {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet PHY constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_ethernet.xdc]
-# }
-Reading Genesys2 PMOD RF constraints...
-# puts "Running synthesis for $part_name..."
-Running synthesis for xc7k325tffg900-2...
-# synth_design -top $top_module -part $part_name -verilog_define SYNTHESIS
-Command: synth_design -top genesys2_rocket_top -part xc7k325tffg900-2 -verilog_define SYNTHESIS
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Device 21-403] Loading part xc7k325tffg900-2
-INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
-INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 116721
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2305.109 ; gain = 484.875 ; free physical = 8124 ; free virtual = 19291
----------------------------------------------------------------------------------
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:8]
-WARNING: [Synth 8-11067] parameter 'CODE_LENGTH_IN_CHIPS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:9]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:10]
-WARNING: [Synth 8-11067] parameter 'SAMPLING_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:13]
-WARNING: [Synth 8-11067] parameter 'CENTER_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:14]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:15]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:16]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:17]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:18]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:19]
-WARNING: [Synth 8-11067] parameter 'ABS_SAMPLE_CNTR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:22]
-WARNING: [Synth 8-11067] parameter 'MS_PER_BIT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:23]
-WARNING: [Synth 8-11067] parameter 'C_ACQ_CHN_NUM' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:26]
-WARNING: [Synth 8-11067] parameter 'ACQ_IQ_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:27]
-WARNING: [Synth 8-11067] parameter 'ACQ_CORR_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:28]
-WARNING: [Synth 8-11067] parameter 'RF_DMEM_AL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:30]
-WARNING: [Synth 8-11067] parameter 'NUM_PRN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:31]
-WARNING: [Synth 8-11067] parameter 'PRN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:32]
-WARNING: [Synth 8-11067] parameter 'STRECH_COUNT_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:33]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_COEF1' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:40]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:41]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:42]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:43]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:44]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:45]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_FREQ_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:46]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:47]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:48]
-WARNING: [Synth 8-11067] parameter 'NUM_TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:50]
-WARNING: [Synth 8-11067] parameter 'TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:51]
-WARNING: [Synth 8-11067] parameter 'ATAN_ANGLE_BIT_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:56]
-WARNING: [Synth 8-11067] parameter 'ATAN_TABLE_SIZE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:57]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:60]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:61]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:62]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_SPACE_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:63]
-WARNING: [Synth 8-11067] parameter 'C1_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:65]
-WARNING: [Synth 8-11067] parameter 'C2_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:66]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:71]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:72]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:73]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:76]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:77]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:78]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:80]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:81]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:83]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:84]
-WARNING: [Synth 8-11067] parameter 'LOCK_WINDOW' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:85]
-WARNING: [Synth 8-11067] parameter 'LOCK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:86]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:89]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:90]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:92]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:93]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:95]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:96]
-WARNING: [Synth 8-11067] parameter 'CODE_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:99]
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:100]
-WARNING: [Synth 8-11067] parameter 'REAL_POS_FS_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:102]
-WARNING: [Synth 8-11067] parameter 'REAL_NEG_FS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:103]
-WARNING: [Synth 8-11067] parameter 'FS_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:105]
-WARNING: [Synth 8-11067] parameter 'DLL_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:106]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:108]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:109]
-WARNING: [Synth 8-11067] parameter 'REM_CODE_PH_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:110]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:113]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:114]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:115]
-WARNING: [Synth 8-11067] parameter 'F_ACQ_CLK' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:118]
-WARNING: [Synth 8-11067] parameter 'ACQ_CLK_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:119]
-WARNING: [Synth 8-11067] parameter 'RF_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:120]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE_CHIP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:121]
-WARNING: [Synth 8-11067] parameter 'ACQ_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:123]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:124]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:125]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:126]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:127]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:128]
-WARNING: [Synth 8-11067] parameter 'ACQ_CODE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:130]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:132]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:133]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:134]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:135]
-WARNING: [Synth 8-11067] parameter 'IFFT_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:136]
-WARNING: [Synth 8-11067] parameter 'IFFT_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:137]
-WARNING: [Synth 8-11067] parameter 'IFFT_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:139]
-WARNING: [Synth 8-11067] parameter 'NFFT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:141]
-WARNING: [Synth 8-11067] parameter 'NFFT_OVER_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:142]
-WARNING: [Synth 8-11067] parameter 'ZERO_PAD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:143]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:145]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:146]
-WARNING: [Synth 8-11067] parameter 'ABS_SQR_I_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:147]
-WARNING: [Synth 8-11067] parameter 'CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:148]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_DIV_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:149]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:150]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:151]
-WARNING: [Synth 8-11067] parameter 'PEAK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:152]
-WARNING: [Synth 8-11067] parameter 'DOPP_STEP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:154]
-WARNING: [Synth 8-11067] parameter 'NUM_FREQ_BIN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:155]
-WARNING: [Synth 8-11067] parameter 'FREQ_BIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:156]
-INFO: [Common 17-14] Message 'Synth 8-11067' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-10180] variable 'i' must explicitly be declared as automatic or static [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv:53]
-INFO: [Synth 8-6157] synthesizing module 'genesys2_rocket_top' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:3]
-INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
- Parameter DIFF_TERM bound to: FALSE - type: string
- Parameter IBUF_LOW_PWR bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 5.000000e+00 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 5.000000e+00 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.250000e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT1_DIVIDE bound to: 20 - type: integer
- Parameter CLKOUT1_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT1_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT2_DIVIDE bound to: 8 - type: integer
- Parameter CLKOUT2_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT2_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:66]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:66]
-WARNING: [Synth 8-7023] instance 'u_clock_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:66]
-INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6157] synthesizing module 'IBUF' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6157] synthesizing module 'BSCANE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
- Parameter DISABLE_JTAG bound to: FALSE - type: string
- Parameter JTAG_CHAIN bound to: 4 - type: integer
-INFO: [Synth 8-6155] done synthesizing module 'BSCANE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
-INFO: [Synth 8-6157] synthesizing module 'rocket_bscan_dmi_tunnel' [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'rocket_bscan_dmi_tunnel' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:264]
-INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
- Parameter PROG_USR bound to: FALSE - type: string
- Parameter SIM_CCLK_FREQ bound to: 0.000000e+00 - type: double
-INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
-INFO: [Synth 8-6157] synthesizing module 'VCU118RocketSystem' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/VCU118RocketSystem.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockSinkDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i2_o1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i2_o1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockSinkDomain' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_aggregator' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_aggregator' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_sbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_sbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroup' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroup' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_5' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_5' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x120' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x120' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x77' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x77' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAUART' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAUART' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_gps' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAGPS' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAGPS' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_2' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_2' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_gps' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FrontBus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x123' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x123' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FrontBus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_2' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_2' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x124' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x124' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x78' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x78' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x99' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x99' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_debug' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_Debug' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_Debug' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_debug' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_4' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_4' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TilePRCIDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'HierarchicalElementResetDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/HierarchicalElementResetDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'RocketTile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/RocketTile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i3_o1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i3_o1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'DCache' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'DTLB' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:31]
-INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-6155] done synthesizing module 'PMPChecker_s3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PMPChecker_s3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PMAChecker' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PMAChecker.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:194]
-INFO: [Synth 8-6155] done synthesizing module 'OptimizationBarrier_TLBEntryData' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/OptimizationBarrier_TLBEntryData.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:228]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:262]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:296]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:330]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:364]
-INFO: [Synth 8-6155] done synthesizing module 'DTLB' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:1121]
-INFO: [Synth 8-6155] done synthesizing module 'Arbiter8_DCacheMetadataReq' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Arbiter8_DCacheMetadataReq.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'rockettile_dcache_data_arrays_0_131072x64' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'DCacheDataArray' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCacheDataArray.sv:31]
-INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:139]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:173]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:207]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:241]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:275]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:309]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PTW.sv:188]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:3191]
- Parameter FORMAT bound to: max_core_cycles=%d - type: string
- Parameter WIDTH bound to: 32 - type: integer
- Parameter DEFAULT bound to: 32'b00000000000000000000000000000000
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:400]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:406]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:412]
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000000001
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter DATA_WIDTH bound to: 4 - type: integer
- Parameter ADDR_WIDTH bound to: 15 - type: integer
- Parameter PH_ACC_WL bound to: 32 - type: integer
- Parameter LUT_DEPTH_WL bound to: 5 - type: integer
- Parameter ACQ_SIN_IL bound to: 2 - type: integer
- Parameter ACQ_SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 25 - type: integer
- Parameter FS bound to: 16368000 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 52 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 36 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_IQ_WL bound to: 24 - type: integer
- Parameter FFT_IQ_TRUNC_WL bound to: 20 - type: integer
- Parameter FFT_CODE_WL bound to: 16 - type: integer
- Parameter FFT_CODE_TRUNC_WL bound to: 16 - type: integer
- Parameter OUT_WL bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 92 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter DWIDTH bound to: 48 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ABS_SQR_I_TRUNCATED_WL bound to: 25 - type: integer
- Parameter CORR_DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter SAMPLES_PER_CODE_CHIP bound to: 16 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv:158]
- Parameter DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ITER bound to: 9 - type: integer
- Parameter IN_W_L bound to: 36 - type: integer
- Parameter IN_F_L bound to: 0 - type: integer
- Parameter OUT_W_L bound to: 16 - type: integer
- Parameter OUT_F_L bound to: 8 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:285]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:296]
-WARNING: [Synth 8-151] case item 32'b00000000000000000000000000001100 is unreachable [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:350]
-WARNING: [Synth 8-7071] port 'clk_200mhz' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'mmcm_locked' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rd' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rxc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_td' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_tx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_txc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7023] instance 'afe' of module 'afe_top' has 17 connections declared, but only 9 given [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000100000
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter SIG_DEPTH bound to: 26 - type: integer
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:182]
- Parameter WIDTH bound to: 4 - type: integer
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter STAGES bound to: 32'b00000000000000000000000000000010
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter Bypass bound to: 1'b0
- Parameter PH_ACC_WL bound to: 24 - type: integer
- Parameter LUT_DEPTH_WL bound to: 7 - type: integer
- Parameter SIN_IL bound to: 2 - type: integer
- Parameter SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 46 - type: integer
- Parameter CODE_FREQ_I_IL bound to: 21 - type: integer
- Parameter CODE_FREQ_I_FL bound to: 20 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 10 - type: integer
- Parameter O_IL bound to: 16 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 13 - type: integer
- Parameter O_IL bound to: 8 - type: integer
- Parameter O_FL bound to: 20 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter TABLE_ADDR bound to: 4 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 33 - type: integer
-WARNING: [Synth 8-7071] port 'vec_len_o' of module 'cordic_atan_basic' is unconnected for instance 'Disc_PLL_i' [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:218]
-WARNING: [Synth 8-7023] instance 'Disc_PLL_i' of module 'cordic_atan_basic' has 8 connections declared, but only 7 given [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:218]
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER1 bound to: 8 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter TABLE_ADDR bound to: 3 - type: integer
-WARNING: [Synth 8-151] case item 4'b1000 is unreachable [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:114]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:105]
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 32 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 25 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter DIV_OUT_WL bound to: 15 - type: integer
- Parameter DIV_OUT_FL bound to: 13 - type: integer
- Parameter DIV_ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 45 - type: integer
- Parameter IN_FL bound to: 8 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:288]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:546]
- Parameter HIGH_ADDRESS bound to: 32'b00000000000000000000111111111111
- Parameter LOW_ADDRESS bound to: 32'b00000000000000000000000000000000
- Parameter DATA_BUS_WIDTH bound to: 32'b00000000000000000000000000100000
- Parameter ADDR_BUS_WIDTH bound to: 32'b00000000000000000000000000001100
- Parameter NUM_CAPTURE_CHANNELS bound to: 32'b00000000000000000000000000001001
- Parameter CLK_FREQ_HZ bound to: 32'b00000111011100110101100101000000
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:48]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:49]
-WARNING: [Synth 8-6014] Unused sequential element s2_vaddr_r_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:989]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:47]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:48]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:47]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:48]
-WARNING: [Synth 8-4767] Trying to implement RAM 'Memory_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/regfile_32x65.sv:60]
-Reason is one or more of the following :
- 1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
- 2: Invalid write to RAM.
- 3: Invalid write to RAM.
- 4: No valid clock found for write to RAM.
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2183]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2626]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2637]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2754]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2755]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2757]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2758]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2769]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2770]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2772]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2773]
-WARNING: [Synth 8-6014] Unused sequential element rocc_blocked_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2894]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2895]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2896]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2897]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2898]
-WARNING: [Synth 8-6014] Unused sequential element r_counter_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError_1.sv:69]
-Read & Write Range Direction Mismatch
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module comp_mult has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/comp_mult.sv:106]
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module ifft_abs_sqr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:90]
-WARNING: [Synth 8-3848] Net eth_rgmii_td in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:38]
-WARNING: [Synth 8-3848] Net eth_rgmii_tx_ctl in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:39]
-WARNING: [Synth 8-3848] Net eth_rgmii_txc in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:40]
-WARNING: [Synth 8-3848] Net rf_data_o in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:46]
-WARNING: [Synth 8-3848] Net fifo_of_o in module/entity trck_cntrl does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:50]
-WARNING: [Synth 8-6014] Unused sequential element g1_var_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:46]
-WARNING: [Synth 8-7137] Register chip_o_reg in module cacode_gen_trck has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:36]
-WARNING: [Synth 8-7129] Port PENABLE in module pps_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port fifo_of_o in module trck_cntrl is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port trck_resetn in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port afe_resetn in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_tx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_txc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port clk_200mhz in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port mmcm_locked in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rxc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port start_acq_manuel in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_en in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_clk in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[3] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_sink in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[127] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[126] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[125] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[124] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[123] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[122] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[121] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[120] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[119] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[118] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[117] in module SBToTL is either unconnected or has no load
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2706.398 ; gain = 886.164 ; free physical = 7710 ; free virtual = 18884
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2706.398 ; gain = 886.164 ; free physical = 7720 ; free virtual = 18894
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2706.398 ; gain = 886.164 ; free physical = 7720 ; free virtual = 18894
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.62 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2706.398 ; gain = 0.000 ; free physical = 7739 ; free virtual = 18913
-INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-INFO: [Timing 38-2] Deriving generated clocks
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2994.570 ; gain = 0.000 ; free physical = 7663 ; free virtual = 18837
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3006.492 ; gain = 0.008 ; free physical = 7657 ; free virtual = 18830
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 3006.492 ; gain = 1186.258 ; free physical = 6491 ; free virtual = 17665
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7k325tffg900-2
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 3014.496 ; gain = 1194.262 ; free physical = 6491 ; free virtual = 17665
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 3014.496 ; gain = 1194.262 ; free physical = 6467 ; free virtual = 17641
----------------------------------------------------------------------------------
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:405]
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:443]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '99' to '12' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:57]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore2_addr_reg' and it is trimmed from '34' to '20' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:383]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore1_addr_reg' and it is trimmed from '34' to '20' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:383]
-WARNING: [Synth 8-3936] Found unconnected internal register 'uncachedReqs_0_addr_reg' and it is trimmed from '34' to '3' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:958]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in1_reg' and it is trimmed from '65' to '33' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:58]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in3_reg' and it is trimmed from '65' to '33' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:60]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPToInt.sv:173]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_typeTagOut_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPToInt.sv:95]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_pipe_b_typeTagIn_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntToFP.sv:66]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:524]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:333]
-WARNING: [Synth 8-3936] Found unconnected internal register 'load_wb_typeTag_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:142]
-WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2787]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2787]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2822]
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized1'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_peak_srch'
-INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'divider_fsm'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_top'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'acq_wrapper'
-INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'trck_cntrl'
-INFO: [Synth 8-802] inferred FSM for state register 'nav_solve_state_p_reg' in module 'nav_solve_timer'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'tracking_wrapper'
-INFO: [Synth 8-802] inferred FSM for state register 'commit_state_p_reg' in module 'pps_core'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'pps_wrapper'
-WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '88' to '87' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a29d32s7k1z2u.sv:66]
-WARNING: [Synth 8-6841] Block RAM (Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-INFO: [Synth 8-3971] The signal "dual_port_bram:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized0:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized1:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized1'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 001 | 000
- S_CORR | 101 | 001
- S_INIT_ADDR | 100 | 010
- S_DATA_Q | 011 | 011
- S_SRCH | 010 | 100
- S_END | 000 | 101
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'sequential' in module 'acq_peak_srch'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- idle | 00 | 00
- normalization | 01 | 01
- cordic_core | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'divider_fsm'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 0000001 | 000
- S_WR_DATA | 0001000 | 001
- S_START | 0010000 | 010
- S_CTRL | 1000000 | 011
- S_FREQ | 0100000 | 100
- S_END | 0000010 | 101
- S_PULLIN | 0000100 | 110
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'one-hot' in module 'acq_top'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'acq_wrapper'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- WAIT_START | 00 | 00
- WAIT_SAMPLE_ALIGN | 01 | 01
- WAIT_CODE_PHASE | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'trck_cntrl'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- iSTATE0 | 0 | 00000000000000000000000000000000
-*
- iSTATE | 1 | 00000000000000000000000000000001
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'nav_solve_state_p_reg' using encoding 'sequential' in module 'nav_solve_timer'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'tracking_wrapper'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- PPS_COMMIT_IDLE | 0000 | 0000
- PPS_COMMIT_FRACTION | 0001 | 0001
- PPS_COMMIT_AGE_CAPTURE | 0010 | 0010
- PPS_COMMIT_AGE_MULTIPLY | 0011 | 0011
- PPS_COMMIT_MAP | 0100 | 0100
- PPS_COMMIT_NORMALIZE | 0101 | 0101
- PPS_COMMIT_PHASE | 0110 | 0110
- PPS_COMMIT_PI_MULTIPLY | 0111 | 0111
- PPS_COMMIT_INTEGRATE | 1000 | 1000
-PPS_COMMIT_CLAMP_INTEGRATOR | 1001 | 1001
- PPS_COMMIT_APPLY | 1010 | 1010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'commit_state_p_reg' using encoding 'sequential' in module 'pps_core'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- PPS_APB_STATE_IDLE | 001 | 00
- PPS_APB_STATE_ACCESS | 100 | 01
- PPS_APB_STATE_FINISH | 010 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'pps_wrapper'
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 3014.496 ; gain = 1194.262 ; free physical = 3982 ; free virtual = 15165
----------------------------------------------------------------------------------
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_5'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_5'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'u_rocket/tile_prci_domain/intsource_2'
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
----------------------------------------------------------------------------------
-Start RTL Component Statistics
----------------------------------------------------------------------------------
-Detailed RTL Component Info :
-+---Adders :
- 3 Input 128 Bit Adders := 1
- 2 Input 112 Bit Adders := 1
- 3 Input 112 Bit Adders := 1
- 2 Input 109 Bit Adders := 1
- 2 Input 107 Bit Adders := 1
- 3 Input 99 Bit Adders := 1
- 2 Input 99 Bit Adders := 1
- 2 Input 66 Bit Adders := 1
- 3 Input 65 Bit Adders := 2
- 2 Input 65 Bit Adders := 3
- 2 Input 64 Bit Adders := 14
- 3 Input 64 Bit Adders := 2
- 2 Input 62 Bit Adders := 1
- 3 Input 61 Bit Adders := 1
- 3 Input 58 Bit Adders := 1
- 2 Input 58 Bit Adders := 2
- 2 Input 55 Bit Adders := 4
- 2 Input 51 Bit Adders := 2
- 2 Input 49 Bit Adders := 1
- 2 Input 46 Bit Adders := 11
- 3 Input 46 Bit Adders := 2
- 2 Input 45 Bit Adders := 18
- 3 Input 45 Bit Adders := 10
- 2 Input 42 Bit Adders := 1
- 2 Input 41 Bit Adders := 9
- 3 Input 41 Bit Adders := 1
- 2 Input 34 Bit Adders := 3
- 3 Input 33 Bit Adders := 18
- 2 Input 32 Bit Adders := 75
- 3 Input 32 Bit Adders := 58
- 2 Input 30 Bit Adders := 18
- 3 Input 30 Bit Adders := 1
- 3 Input 29 Bit Adders := 1
- 2 Input 28 Bit Adders := 18
- 2 Input 26 Bit Adders := 25
- 3 Input 26 Bit Adders := 2
- 2 Input 25 Bit Adders := 11
- 3 Input 25 Bit Adders := 9
- 2 Input 23 Bit Adders := 54
- 2 Input 22 Bit Adders := 18
- 2 Input 18 Bit Adders := 2
- 3 Input 18 Bit Adders := 2
- 3 Input 16 Bit Adders := 1
- 2 Input 16 Bit Adders := 1
- 2 Input 15 Bit Adders := 2
- 2 Input 14 Bit Adders := 20
- 4 Input 14 Bit Adders := 1
- 3 Input 14 Bit Adders := 1
- 3 Input 13 Bit Adders := 2
- 2 Input 13 Bit Adders := 7
- 2 Input 12 Bit Adders := 13
- 3 Input 12 Bit Adders := 10
- 4 Input 11 Bit Adders := 1
- 2 Input 11 Bit Adders := 4
- 3 Input 10 Bit Adders := 2
- 2 Input 10 Bit Adders := 1
- 2 Input 9 Bit Adders := 11
- 3 Input 9 Bit Adders := 5
- 2 Input 8 Bit Adders := 5
- 2 Input 7 Bit Adders := 4
- 2 Input 6 Bit Adders := 24
- 3 Input 6 Bit Adders := 2
- 2 Input 5 Bit Adders := 41
- 2 Input 4 Bit Adders := 86
- 3 Input 4 Bit Adders := 1
- 3 Input 3 Bit Adders := 9
- 2 Input 3 Bit Adders := 34
- 2 Input 2 Bit Adders := 6
- 3 Input 2 Bit Adders := 4
- 4 Input 2 Bit Adders := 1
- 5 Input 2 Bit Adders := 1
- 3 Input 1 Bit Adders := 3
- 2 Input 1 Bit Adders := 41
-+---XORs :
- 2 Input 65 Bit XORs := 1
- 2 Input 64 Bit XORs := 7
- 2 Input 33 Bit XORs := 1
- 2 Input 32 Bit XORs := 8
- 2 Input 29 Bit XORs := 16
- 2 Input 17 Bit XORs := 48
- 2 Input 16 Bit XORs := 2
- 2 Input 15 Bit XORs := 5
- 2 Input 14 Bit XORs := 1
- 2 Input 12 Bit XORs := 4
- 2 Input 10 Bit XORs := 4
- 2 Input 5 Bit XORs := 38
- 2 Input 4 Bit XORs := 2
- 2 Input 3 Bit XORs := 23
- 2 Input 2 Bit XORs := 7
- 2 Input 1 Bit XORs := 485
- 3 Input 1 Bit XORs := 68
- 6 Input 1 Bit XORs := 19
- 7 Input 1 Bit XORs := 18
- 13 Input 1 Bit XORs := 90
- 11 Input 1 Bit XORs := 63
- 12 Input 1 Bit XORs := 63
- 8 Input 1 Bit XORs := 54
- 10 Input 1 Bit XORs := 72
- 4 Input 1 Bit XORs := 54
- 14 Input 1 Bit XORs := 117
- 5 Input 1 Bit XORs := 18
- 15 Input 1 Bit XORs := 9
- 9 Input 1 Bit XORs := 54
- 16 Input 1 Bit XORs := 9
-+---XORs :
- 5 Bit Wide XORs := 36
- 4 Bit Wide XORs := 36
- 3 Bit Wide XORs := 36
- 2 Bit Wide XORs := 36
-+---Registers :
- 310 Bit Registers := 9
- 130 Bit Registers := 1
- 112 Bit Registers := 5
- 107 Bit Registers := 1
- 104 Bit Registers := 1
- 99 Bit Registers := 1
- 98 Bit Registers := 1
- 92 Bit Registers := 2
- 90 Bit Registers := 3
- 87 Bit Registers := 1
- 65 Bit Registers := 45
- 64 Bit Registers := 68
- 62 Bit Registers := 2
- 58 Bit Registers := 2
- 56 Bit Registers := 1
- 55 Bit Registers := 13
- 53 Bit Registers := 1
- 52 Bit Registers := 2
- 51 Bit Registers := 8
- 50 Bit Registers := 9
- 49 Bit Registers := 2
- 48 Bit Registers := 81
- 46 Bit Registers := 18
- 45 Bit Registers := 2
- 43 Bit Registers := 1
- 41 Bit Registers := 11
- 40 Bit Registers := 9
- 36 Bit Registers := 3
- 34 Bit Registers := 25
- 33 Bit Registers := 30
- 32 Bit Registers := 219
- 31 Bit Registers := 90
- 30 Bit Registers := 28
- 29 Bit Registers := 6
- 28 Bit Registers := 20
- 27 Bit Registers := 1
- 26 Bit Registers := 67
- 24 Bit Registers := 40
- 22 Bit Registers := 136
- 21 Bit Registers := 9
- 20 Bit Registers := 2
- 18 Bit Registers := 9
- 17 Bit Registers := 3
- 16 Bit Registers := 18
- 15 Bit Registers := 53
- 14 Bit Registers := 50
- 13 Bit Registers := 9
- 12 Bit Registers := 21
- 10 Bit Registers := 30
- 9 Bit Registers := 15
- 8 Bit Registers := 113
- 7 Bit Registers := 12
- 6 Bit Registers := 83
- 5 Bit Registers := 106
- 4 Bit Registers := 218
- 3 Bit Registers := 156
- 2 Bit Registers := 215
- 1 Bit Registers := 1446
-+---Multipliers :
- 48x64 Multipliers := 2
- 53x53 Multipliers := 1
- 33x65 Multipliers := 1
- 66x66 Multipliers := 1
- 15x46 Multipliers := 4
- 27x32 Multipliers := 1
- 25x30 Multipliers := 9
-+---RAMs :
- 8192K Bit (131072 X 64 bit) RAMs := 1
- 1472K Bit (16384 X 92 bit) RAMs := 1
- 832K Bit (16384 X 52 bit) RAMs := 1
- 816K Bit (16384 X 51 bit) RAMs := 1
- 768K Bit (16384 X 48 bit) RAMs := 1
- 576K Bit (16384 X 36 bit) RAMs := 1
- 128K Bit (32768 X 4 bit) RAMs := 1
- 16K Bit (512 X 32 bit) RAMs := 2
- 1K Bit (64 X 21 bit) RAMs := 1
-+---ROMs :
- ROMs := 6
-+---Muxes :
- 2 Input 2080 Bit Muxes := 1
- 2 Input 130 Bit Muxes := 3
- 3 Input 128 Bit Muxes := 1
- 2 Input 128 Bit Muxes := 2
- 2 Input 112 Bit Muxes := 2
- 2 Input 109 Bit Muxes := 1
- 2 Input 108 Bit Muxes := 1
- 2 Input 92 Bit Muxes := 6
- 2 Input 65 Bit Muxes := 19
- 4 Input 65 Bit Muxes := 1
- 2 Input 64 Bit Muxes := 136
- 4 Input 64 Bit Muxes := 7
- 11 Input 64 Bit Muxes := 5
- 2 Input 62 Bit Muxes := 1
- 2 Input 61 Bit Muxes := 2
- 2 Input 58 Bit Muxes := 2
- 2 Input 56 Bit Muxes := 5
- 2 Input 55 Bit Muxes := 11
- 2 Input 54 Bit Muxes := 3
- 2 Input 53 Bit Muxes := 2
- 2 Input 52 Bit Muxes := 16
- 2 Input 51 Bit Muxes := 5
- 2 Input 50 Bit Muxes := 10
- 2 Input 48 Bit Muxes := 7
- 2 Input 46 Bit Muxes := 27
- 2 Input 45 Bit Muxes := 21
- 3 Input 45 Bit Muxes := 2
- 2 Input 44 Bit Muxes := 4
- 2 Input 41 Bit Muxes := 7
- 2 Input 36 Bit Muxes := 6
- 7 Input 36 Bit Muxes := 1
- 2 Input 34 Bit Muxes := 30
- 2 Input 33 Bit Muxes := 39
- 2 Input 32 Bit Muxes := 325
- 3 Input 32 Bit Muxes := 1
- 4 Input 32 Bit Muxes := 1
- 2 Input 30 Bit Muxes := 9
- 2 Input 29 Bit Muxes := 9
- 2 Input 28 Bit Muxes := 1
- 2 Input 27 Bit Muxes := 4
- 2 Input 26 Bit Muxes := 15
- 2 Input 25 Bit Muxes := 25
- 2 Input 24 Bit Muxes := 97
- 2 Input 23 Bit Muxes := 65
- 2 Input 22 Bit Muxes := 78
- 2 Input 20 Bit Muxes := 4
- 2 Input 17 Bit Muxes := 1
- 2 Input 16 Bit Muxes := 14
- 3 Input 16 Bit Muxes := 1
- 7 Input 16 Bit Muxes := 1
- 2 Input 15 Bit Muxes := 18
- 2 Input 14 Bit Muxes := 62
- 7 Input 14 Bit Muxes := 1
- 2 Input 13 Bit Muxes := 20
- 2 Input 12 Bit Muxes := 51
- 2 Input 11 Bit Muxes := 2
- 2 Input 10 Bit Muxes := 13
- 2 Input 9 Bit Muxes := 34
- 3 Input 9 Bit Muxes := 1
- 2 Input 8 Bit Muxes := 210
- 8 Input 8 Bit Muxes := 18
- 2 Input 7 Bit Muxes := 20
- 7 Input 7 Bit Muxes := 1
- 4 Input 6 Bit Muxes := 1
- 2 Input 6 Bit Muxes := 65
- 3 Input 6 Bit Muxes := 3
- 7 Input 6 Bit Muxes := 3
- 2 Input 5 Bit Muxes := 58
- 4 Input 5 Bit Muxes := 1
- 5 Input 5 Bit Muxes := 3
- 3 Input 5 Bit Muxes := 2
- 2 Input 4 Bit Muxes := 124
- 4 Input 4 Bit Muxes := 3
- 8 Input 4 Bit Muxes := 1
- 3 Input 4 Bit Muxes := 1
- 11 Input 4 Bit Muxes := 1
- 7 Input 4 Bit Muxes := 2
- 2 Input 3 Bit Muxes := 176
- 6 Input 3 Bit Muxes := 3
- 8 Input 3 Bit Muxes := 3
- 4 Input 3 Bit Muxes := 3
- 3 Input 3 Bit Muxes := 28
- 7 Input 3 Bit Muxes := 1
- 5 Input 3 Bit Muxes := 2
- 2 Input 2 Bit Muxes := 157
- 16 Input 2 Bit Muxes := 1
- 3 Input 2 Bit Muxes := 13
- 4 Input 2 Bit Muxes := 5
- 7 Input 2 Bit Muxes := 1
- 8 Input 2 Bit Muxes := 1
- 2 Input 1 Bit Muxes := 1386
- 3 Input 1 Bit Muxes := 42
- 5 Input 1 Bit Muxes := 27
- 11 Input 1 Bit Muxes := 29
- 4 Input 1 Bit Muxes := 21
- 6 Input 1 Bit Muxes := 1
- 7 Input 1 Bit Muxes := 9
----------------------------------------------------------------------------------
-Finished RTL Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 840 (col length:140)
-BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 10. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv:136]
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (dfma/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_vec_reg' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3886] merging instance 'mem_ctrl_vec_reg' (FDE) to 'mem_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_typeTagIn_reg[1]' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\ex_reg_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\in_pipe_b_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\mem_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[1]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[2]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[2]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[3]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[3]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[4]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (ifpu/\io_out_pipe_b_exc_reg[4] )
-INFO: [Synth 8-4471] merging register 's2_tlb_resp_pf_inst_reg' into 's2_tlb_resp_cacheable_reg' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Frontend.sv:127]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 16. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/MulDiv.sv:131]
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[60]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[60]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[61]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[61]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[62]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[62]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[57]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[57]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[58]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[58]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[59]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[59]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[54]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[54]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[55]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[55]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[56]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[56]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[51]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[51]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[52]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[52]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[53]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[53]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[48]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[48]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[49]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[49]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[50]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[50]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[45]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[45]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[46]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[46]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[47]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[47]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[42]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[42]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[43]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[43]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[44]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[44]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[39]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[39]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[40]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[40]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[41]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[41]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[36]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[36]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[37]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[37]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[38]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[38]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[33]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[33]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[34]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[34]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[35]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[35]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[30]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[30]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[31]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[31]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[32]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[32]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[27]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[27]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[28]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[28]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[29]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[29]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[24]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[24]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[25]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[25]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[26]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[26]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[21]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[21]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[22]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[22]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[23]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[23]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[18]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[18]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[19]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[19]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[20]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[20]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[15]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[15]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[16]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[16]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_reg_cause_reg[5] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_mstatus_mpp_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mcountinhibit_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mie_reg[0] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/\s1_pc_reg[0] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_mem_cmd_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_sel_alu2_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/s2_tlb_resp_cacheable_reg)
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[5] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[7] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[7] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[8] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[8] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[12] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[22] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[22] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[23] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[23] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[46] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[46] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[47] )
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_addr_reg' and it is trimmed from '34' to '32' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:408]
-WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[3] driven by constant 0
-WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[2] driven by constant 0
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-WARNING: [Synth 8-6841] Block RAM (rockettile_dcache_data_arrays_0_ext/Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 4. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:129]
-DSP Report: Generating DSP freq_word0, operation Mode is: (A:0x6677)*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: A*(B:0x6677).
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x109).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x55).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult20, operation Mode is: A*(B:0x75).
-DSP Report: operator mult20 is absorbed into DSP mult20.
-INFO: [Synth 8-5544] ROM "cordic_angle_lut_i/angle_o" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
-INFO: [Synth 8-4471] merging register 'prompt_abs_vld_reg' into 'cos2x_i/sqr_vld_reg' [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:107]
-DSP Report: Generating DSP cos2x_i/q_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: Generating DSP cos2x_i/i_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[15]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[14]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[13]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[12]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[11]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[10]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[9]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[8]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[7]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[6]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[5]__1) is unused and will be removed from module NCO_carr.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 8. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:311]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 4. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:300]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 12. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:375]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 12. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:374]
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (A:0x15940)*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: A*(B:0x15940).
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w0, operation Mode is: C+A*B.
-DSP Report: operator butterfly_i/x1_imag_w0 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w0, operation Mode is: C-A*B.
-DSP Report: operator butterfly_i/x1_real_w0 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP bd, operation Mode is: A*B.
-DSP Report: operator bd is absorbed into DSP bd.
-DSP Report: Generating DSP ac, operation Mode is: A*B.
-DSP Report: operator ac is absorbed into DSP ac.
-DSP Report: Generating DSP ad, operation Mode is: A*B.
-DSP Report: operator ad is absorbed into DSP ad.
-DSP Report: Generating DSP bc, operation Mode is: A*B.
-DSP Report: operator bc is absorbed into DSP bc.
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-WARNING: [Synth 8-3917] design APBGpsBlock__GCB1 has port _acq_sample_counter_clear driven by constant 0
-INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM acq/i_acq_top/dual_port_ram_i/ram_reg to conserve power
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_IQ_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_code_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /ifft_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-4652] Swapped enable and write-enable on 26 RAM instances of RAM bram_i/ram_reg to conserve power
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:16 ; elapsed = 00:01:29 . Memory (MB): peak = 3030.508 ; gain = 1210.273 ; free physical = 271 ; free virtual = 11306
----------------------------------------------------------------------------------
- Sort Area is APBGpsBlock__GCB1 p_1_out_0 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_2 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_3 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_4 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 0 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 1 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 2 : 2812 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 3 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 0 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 1 : 2793 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 2 : 2812 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 3 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 0 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 1 : 2812 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 2 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 3 : 2691 11089 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 0 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 1 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 2 : 3255 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 0 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 1 : 3101 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 2 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 0 : 3101 9322 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 1 : 3120 9322 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 2 : 3101 9322 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 0 : 1995 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 1 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 2 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 0 : 1995 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 1 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 2 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 0 : 1313 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 1 : 2710 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 2 : 2759 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 0 : 1313 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 1 : 2710 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 2 : 2712 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 0 : 1313 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 1 : 2710 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 2 : 2712 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 0 : 1313 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 1 : 2759 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 2 : 2479 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 0 : 1995 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 1 : 2712 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 2 : 1836 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 0 : 1995 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 1 : 2712 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 2 : 1836 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 0 : 1995 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 1 : 1836 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 2 : 1495 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 0 : 1995 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 1 : 1836 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 2 : 1495 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 im_sqr0_26 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 im_sqr0_26 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 re_sqr0_23 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 re_sqr0_23 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 0 : 3446 4760 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 1 : 1314 4760 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1e : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1e : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_20 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_20 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_18 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_18 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1c : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1c : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_17 : 0 0 : 1315 3694 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_17 : 0 1 : 2379 3694 : Used 1 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 0 : 1789 3431 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 1 : 1642 3431 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_0 : 0 0 : 1313 3313 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_0 : 0 1 : 2000 3313 : Used 1 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 0 : 1785 3295 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 1 : 1510 3295 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_3 : 0 0 : 1315 3237 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_3 : 0 1 : 1922 3237 : Used 1 time 0
- Sort Area is tracking_wrapper cos2x_i/i_p_sqr0_b : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is tracking_wrapper cos2x_i/q_p_sqr0_d : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB1 ac_12 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 ad_16 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 bc_15 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 bd_14 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w0_c : 0 0 : 2196 2196 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w0_f : 0 0 : 2073 2073 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_e : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_a : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1f : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_21 : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1a : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1d : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_17 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_5 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_9 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_11 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_22 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_7 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is tracking_wrapper mult10_6 : 0 0 : 433 433 : Used 9 time 0
- Sort Area is tracking_wrapper mult10_a : 0 0 : 403 403 : Used 9 time 0
- Sort Area is tracking_wrapper mult20_8 : 0 0 : 403 403 : Used 9 time 0
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-ROM: Preliminary Mapping Report
-+----------------+----------------------+---------------+----------------+
-|Module Name | RTL Object | Depth x Width | Implemented As |
-+----------------+----------------------+---------------+----------------+
-|TLROM | _GEN | 256x64 | LUT |
-|acq_nco_carr | freq_word_arr | 64x13 | LUT |
-|acq_nco_carr | pullin_freq_word_arr | 16x11 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_ca_gen | p_0_out | 32x8 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|cacode_gen_trck | p_0_out | 32x8 | LUT |
-+----------------+----------------------+---------------+----------------+
-
-
-Block RAM: Preliminary Mapping Report (see note below)
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GCB1 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
-
-Distributed RAM: Preliminary Mapping Report (see note below)
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
-Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
-
-DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | (PCIN>>17)+A*B | 25 | 8 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 16 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|NCO_carr | (A:0x6677)*B | 14 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 14 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | A*(B:0x6677) | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 18 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | A*(B:0x109) | 12 | 10 | - | - | 22 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x55) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x75) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 16 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (A:0x15940)*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 16 | 11 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*(B:0x15940) | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 11 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 14 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 14 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:20 ; elapsed = 00:01:37 . Memory (MB): peak = 3030.508 ; gain = 1210.273 ; free physical = 2609 ; free virtual = 13696
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:03:29 ; elapsed = 00:01:47 . Memory (MB): peak = 3034.594 ; gain = 1214.359 ; free physical = 2476 ; free virtual = 13565
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Block RAM: Final Mapping Report
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GCB1 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-
-Distributed RAM: Final Mapping Report
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:61]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:74]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:66]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:66]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv:100]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:234]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:234]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:234]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:232]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:232]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:241]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:241]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:241]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:241]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:240]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:240]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:240]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:240]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:231]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:233]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:233]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:231]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:233]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:231]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:231]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:233]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:233]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:231]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:233]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:231]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:233]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:231]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:231]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:233]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:226]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:226]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:226]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:226]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:229]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:228]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:228]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:228]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:228]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:228]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:228]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:228]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:228]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:238]
-INFO: [Common 17-14] Message 'Synth 8-5844' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:03:36 ; elapsed = 00:01:58 . Memory (MB): peak = 3054.527 ; gain = 1234.293 ; free physical = 987 ; free virtual = 12081
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:03:44 ; elapsed = 00:02:07 . Memory (MB): peak = 3196.270 ; gain = 1376.035 ; free physical = 761 ; free virtual = 11899
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:03:44 ; elapsed = 00:02:07 . Memory (MB): peak = 3196.270 ; gain = 1376.035 ; free physical = 762 ; free virtual = 11899
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:03:55 ; elapsed = 00:02:18 . Memory (MB): peak = 3382.449 ; gain = 1562.215 ; free physical = 606 ; free virtual = 11744
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:03:55 ; elapsed = 00:02:19 . Memory (MB): peak = 3382.449 ; gain = 1562.215 ; free physical = 607 ; free virtual = 11745
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:03:57 ; elapsed = 00:02:20 . Memory (MB): peak = 3394.324 ; gain = 1574.090 ; free physical = 610 ; free virtual = 11748
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:03:57 ; elapsed = 00:02:20 . Memory (MB): peak = 3394.324 ; gain = 1574.090 ; free physical = 609 ; free virtual = 11747
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Static Shift Register Report:
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|VCU118RocketSystem | tile_prci_domain/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-|VCU118RocketSystem | ibus/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-DSP Final Report (the ' indicates corresponding REG is set)
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-(A*B) | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 15 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 15 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 0 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 15 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 15 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN>>17+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B' | 24 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | PCIN>>17+A*B | 24 | 7 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-
-Report BlackBoxes:
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage:
-+------+-----------+------+
-| |Cell |Count |
-+------+-----------+------+
-|1 |BSCANE2 | 1|
-|2 |BUFG | 6|
-|3 |CARRY4 | 6016|
-|4 |DSP48E1 | 208|
-|10 |LUT1 | 2815|
-|11 |LUT2 | 15087|
-|12 |LUT3 | 10704|
-|13 |LUT4 | 7956|
-|14 |LUT5 | 12038|
-|15 |LUT6 | 24664|
-|16 |MMCME2_ADV | 1|
-|17 |MUXF7 | 1797|
-|18 |MUXF8 | 142|
-|19 |RAM32M | 225|
-|20 |RAM32X1D | 5|
-|21 |RAMB18E1 | 4|
-|23 |RAMB36E1 | 415|
-|45 |SRL16E | 2|
-|46 |STARTUPE2 | 1|
-|47 |FDCE | 30794|
-|48 |FDPE | 360|
-|49 |FDRE | 10101|
-|50 |FDSE | 130|
-|51 |LDC | 9|
-|52 |IBUF | 8|
-|53 |IBUFDS | 1|
-|54 |IOBUF | 8|
-|55 |OBUF | 13|
-+------+-----------+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:03:57 ; elapsed = 00:02:21 . Memory (MB): peak = 3394.324 ; gain = 1574.090 ; free physical = 610 ; free virtual = 11748
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 644 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:03:47 ; elapsed = 00:02:17 . Memory (MB): peak = 3398.238 ; gain = 1277.910 ; free physical = 7504 ; free virtual = 18642
-Synthesis Optimization Complete : Time (s): cpu = 00:03:57 ; elapsed = 00:02:25 . Memory (MB): peak = 3398.238 ; gain = 1578.004 ; free physical = 7522 ; free virtual = 18650
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.8 . Memory (MB): peak = 3398.238 ; gain = 0.000 ; free physical = 7531 ; free virtual = 18659
-INFO: [Netlist 29-17] Analyzing 8832 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3578.582 ; gain = 0.000 ; free physical = 7432 ; free virtual = 18560
-INFO: [Project 1-111] Unisim Transformation Summary:
- A total of 247 instances were transformed.
- IOBUF => IOBUF (IBUF, OBUFT): 8 instances
- LDC => LDCE: 9 instances
- RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 225 instances
- RAM32X1D => RAM32X1D (RAMD32(x2)): 5 instances
-
-Synth Design complete | Checksum: 19a5cb86
-INFO: [Common 17-83] Releasing license: Synthesis
-727 Infos, 394 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:04:15 ; elapsed = 00:02:43 . Memory (MB): peak = 3578.617 ; gain = 1965.367 ; free physical = 7433 ; free virtual = 18560
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 10055.206; main = 2851.233; forked = 8208.029
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19233.250; main = 3578.586; forked = 16206.656
-# apply_genesys2_async_clock_groups
-Applying Genesys2 async clock groups.
-# write_checkpoint -force [file join $checkpoint_dir post_synth.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.598 ; gain = 0.000 ; free physical = 7433 ; free virtual = 18561
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.598 ; gain = 0.000 ; free physical = 7433 ; free virtual = 18561
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3610.598 ; gain = 0.000 ; free physical = 7433 ; free virtual = 18561
-Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.598 ; gain = 0.000 ; free physical = 7433 ; free virtual = 18561
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.598 ; gain = 0.000 ; free physical = 7433 ; free virtual = 18561
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.598 ; gain = 0.000 ; free physical = 7433 ; free virtual = 18562
-Write Physdb Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3610.598 ; gain = 0.000 ; free physical = 7432 ; free virtual = 18561
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3610.598 ; gain = 0.000 ; free physical = 7405 ; free virtual = 18546
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_synth.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 3610.598 ; gain = 31.980 ; free physical = 7352 ; free virtual = 18480
-# report_utilization -hierarchical -file [file join $report_dir synth_utilization_hier.rpt]
-# report_utilization -file [file join $report_dir synth_utilization.rpt]
-# report_timing_summary -file [file join $report_dir synth_timing_summary.rpt]
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs
-report_timing_summary: Time (s): cpu = 00:00:38 ; elapsed = 00:00:09 . Memory (MB): peak = 3610.598 ; gain = 0.000 ; free physical = 7399 ; free virtual = 18526
-# puts "Running implementation..."
-Running implementation...
-# opt_design
-Command: opt_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-Running DRC as a precondition to command opt_design
-
-Starting DRC Task
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Project 1-461] DRC finished with 0 Errors
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.54 . Memory (MB): peak = 3682.910 ; gain = 72.312 ; free physical = 7398 ; free virtual = 18526
-
-Starting Cache Timing Information Task
-Ending Cache Timing Information Task | Checksum: c35b053c
-
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3682.910 ; gain = 0.000 ; free physical = 7398 ; free virtual = 18526
-
-Starting Logic Optimization Task
-
-Phase 1 Initialization
-
-Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: c35b053c
-
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3691.816 ; gain = 0.000 ; free physical = 7346 ; free virtual = 18473
-
-Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: c35b053c
-
-Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3691.816 ; gain = 0.000 ; free physical = 7346 ; free virtual = 18473
-Phase 1 Initialization | Checksum: c35b053c
-
-Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3691.816 ; gain = 0.000 ; free physical = 7346 ; free virtual = 18473
-
-Phase 2 Timer Update And Timing Data Collection
-
-Phase 2.1 Detect if minReqCache needed
-Phase 2.1 Detect if minReqCache needed | Checksum: c35b053c
-
-Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.21 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7322 ; free virtual = 18450
-
-Phase 2.2 Timer Update
-Phase 2.2 Timer Update | Checksum: c35b053c
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7323 ; free virtual = 18450
-
-Phase 2.3 Timing Data Collection
-Phase 2.3 Timing Data Collection | Checksum: c35b053c
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7323 ; free virtual = 18450
-Phase 2 Timer Update And Timing Data Collection | Checksum: c35b053c
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7323 ; free virtual = 18450
-
-Phase 3 Retarget
-INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
-INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
-INFO: [Opt 31-1566] Pulled 28 inverters resulting in an inversion of 507 pins
-INFO: [Opt 31-138] Pushed 14 inverter(s) to 129 load pin(s).
-INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 1e05457d6
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7326 ; free virtual = 18453
-Retarget | Checksum: 1e05457d6
-INFO: [Opt 31-389] Phase Retarget created 713 cells and removed 754 cells
-INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 4 Constant propagation
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 24443e568
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7327 ; free virtual = 18455
-Constant propagation | Checksum: 24443e568
-INFO: [Opt 31-389] Phase Constant propagation created 1 cells and removed 1 cells
-
-Phase 5 Sweep
-INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
-Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3710.785 ; gain = 0.000 ; free physical = 7327 ; free virtual = 18454
-Phase 5 Sweep | Checksum: 20f9f73d2
-
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7329 ; free virtual = 18456
-Sweep | Checksum: 20f9f73d2
-INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 5 cells
-INFO: [Opt 31-1021] In phase Sweep, 360 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 6 BUFG optimization
-Phase 6 BUFG optimization | Checksum: 20f9f73d2
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7329 ; free virtual = 18456
-BUFG optimization | Checksum: 20f9f73d2
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
-
-Phase 7 Shift Register Optimization
-INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 20f9f73d2
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7329 ; free virtual = 18456
-Shift Register Optimization | Checksum: 20f9f73d2
-INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
-
-Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 20f9f73d2
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7329 ; free virtual = 18456
-Post Processing Netlist | Checksum: 20f9f73d2
-INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
-
-Phase 9 Finalization
-
-Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 18a04d138
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7331 ; free virtual = 18459
-
-Phase 9.2 Verifying Netlist Connectivity
-
-Starting Connectivity Check Task
-
-Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3710.785 ; gain = 0.000 ; free physical = 7331 ; free virtual = 18459
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 18a04d138
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7331 ; free virtual = 18459
-Phase 9 Finalization | Checksum: 18a04d138
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7331 ; free virtual = 18459
-Opt_design Change Summary
-=========================
-
-
--------------------------------------------------------------------------------------------------------------------------
-| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
--------------------------------------------------------------------------------------------------------------------------
-| Retarget | 713 | 754 | 1 |
-| Constant propagation | 1 | 1 | 0 |
-| Sweep | 0 | 5 | 360 |
-| BUFG optimization | 0 | 0 | 0 |
-| Shift Register Optimization | 0 | 0 | 0 |
-| Post Processing Netlist | 0 | 0 | 0 |
--------------------------------------------------------------------------------------------------------------------------
-
-
-Ending Logic Optimization Task | Checksum: 18a04d138
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 3710.785 ; gain = 18.969 ; free physical = 7331 ; free virtual = 18459
-
-Starting Power Optimization Task
-INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-INFO: [Power 33-23] Power model is not available for u_cfg_flash_startup
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running Vector-less Activity Propagation...
-
-Finished Running Vector-less Activity Propagation
-INFO: [Pwropt 34-9] Applying IDT optimizations ...
-INFO: [Pwropt 34-10] Applying ODC optimizations ...
-
-
-Starting PowerOpt Patch Enables Task
-INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 419 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
-INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
-Number of BRAM Ports augmented: 0 newly gated: 84 Total Ports: 838
-Ending PowerOpt Patch Enables Task | Checksum: 12ef72a94
-
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6896 ; free virtual = 18023
-Ending Power Optimization Task | Checksum: 12ef72a94
-
-Time (s): cpu = 00:00:38 ; elapsed = 00:00:22 . Memory (MB): peak = 4327.207 ; gain = 616.422 ; free physical = 6896 ; free virtual = 18023
-
-Starting Final Cleanup Task
-
-Starting Logic Optimization Task
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Logic Optimization Task | Checksum: 199b57293
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:04 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6885 ; free virtual = 18013
-Ending Final Cleanup Task | Checksum: 199b57293
-
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6885 ; free virtual = 18013
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6885 ; free virtual = 18013
-INFO: [Common 17-83] Releasing license: Implementation
-29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-opt_design completed successfully
-opt_design: Time (s): cpu = 00:01:06 ; elapsed = 00:00:37 . Memory (MB): peak = 4327.207 ; gain = 716.609 ; free physical = 6885 ; free virtual = 18013
-# write_checkpoint -force [file join $checkpoint_dir post_opt.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6885 ; free virtual = 18013
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6885 ; free virtual = 18013
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6884 ; free virtual = 18012
-Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6884 ; free virtual = 18013
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6884 ; free virtual = 18013
-Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6884 ; free virtual = 18012
-Write Physdb Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6884 ; free virtual = 18012
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.13 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6865 ; free virtual = 18006
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_opt.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6803 ; free virtual = 17930
-# place_design
-Command: place_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-83] Releasing license: Implementation
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running DRC as a precondition to command place_design
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 12 CPUs
-
-Starting Placer Task
-
-Phase 1 Placer Initialization
-
-Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6853 ; free virtual = 17981
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b93e1e49
-
-Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6853 ; free virtual = 17981
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6853 ; free virtual = 17981
-
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1797dab6a
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6866 ; free virtual = 17993
-
-Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 1ddd8aaa3
-
-Time (s): cpu = 00:00:50 ; elapsed = 00:00:17 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6879 ; free virtual = 18007
-
-Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 1ddd8aaa3
-
-Time (s): cpu = 00:00:50 ; elapsed = 00:00:17 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6879 ; free virtual = 18007
-Phase 1 Placer Initialization | Checksum: 1ddd8aaa3
-
-Time (s): cpu = 00:00:50 ; elapsed = 00:00:17 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6879 ; free virtual = 18007
-
-Phase 2 Global Placement
-
-Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 1820bbd06
-
-Time (s): cpu = 00:01:18 ; elapsed = 00:00:24 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6911 ; free virtual = 18038
-
-Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1943f57b1
-
-Time (s): cpu = 00:01:47 ; elapsed = 00:00:30 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6909 ; free virtual = 18036
-
-Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 1943f57b1
-
-Time (s): cpu = 00:01:48 ; elapsed = 00:00:31 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6909 ; free virtual = 18036
-
-Phase 2.4 Global Place Phase1
-Phase 2.4 Global Place Phase1 | Checksum: 2697f582e
-
-Time (s): cpu = 00:03:27 ; elapsed = 00:01:07 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6910 ; free virtual = 18037
-
-Phase 2.5 Global Place Phase2
-
-Phase 2.5.1 UpdateTiming Before Physical Synthesis
-Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 20fe44a48
-
-Time (s): cpu = 00:03:59 ; elapsed = 00:01:13 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6891 ; free virtual = 18014
-
-Phase 2.5.2 Physical Synthesis In Placer
-INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 4056 LUT instances to create LUTNM shape
-INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
-INFO: [Physopt 32-1138] End 1 Pass. Optimized 1109 nets or LUTs. Breaked 0 LUT, combined 1109 existing LUTs and moved 0 existing LUT
-INFO: [Physopt 32-65] No nets found for high-fanout optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
-INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
-INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
-INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6892 ; free virtual = 18016
-
-Summary of Physical Synthesis Optimizations
-============================================
-
-
------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
------------------------------------------------------------------------------------------------------------------------------------------------------------
-| LUT Combining | 0 | 1109 | 1109 | 0 | 1 | 00:00:02 |
-| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Total | 0 | 1109 | 1109 | 0 | 9 | 00:00:02 |
------------------------------------------------------------------------------------------------------------------------------------------------------------
-
-
-Phase 2.5.2 Physical Synthesis In Placer | Checksum: 2ae0ffcc0
-
-Time (s): cpu = 00:04:33 ; elapsed = 00:01:24 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6899 ; free virtual = 18023
-Phase 2.5 Global Place Phase2 | Checksum: 201b98f6a
-
-Time (s): cpu = 00:04:37 ; elapsed = 00:01:27 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6899 ; free virtual = 18023
-Phase 2 Global Placement | Checksum: 201b98f6a
-
-Time (s): cpu = 00:04:38 ; elapsed = 00:01:27 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6899 ; free virtual = 18023
-
-Phase 3 Detail Placement
-
-Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 24277196b
-
-Time (s): cpu = 00:05:07 ; elapsed = 00:01:33 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6898 ; free virtual = 18023
-
-Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1e366fc1a
-
-Time (s): cpu = 00:06:00 ; elapsed = 00:01:47 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6891 ; free virtual = 18016
-
-Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 270261f7a
-
-Time (s): cpu = 00:06:01 ; elapsed = 00:01:48 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6891 ; free virtual = 18016
-
-Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 1d93f1b5d
-
-Time (s): cpu = 00:06:01 ; elapsed = 00:01:48 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6891 ; free virtual = 18016
-
-Phase 3.5 Fast Optimization
-Phase 3.5 Fast Optimization | Checksum: 292695cb5
-
-Time (s): cpu = 00:06:55 ; elapsed = 00:02:00 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6915 ; free virtual = 18041
-
-Phase 3.6 Small Shape Detail Placement
-Phase 3.6 Small Shape Detail Placement | Checksum: 24f73d3f4
-
-Time (s): cpu = 00:07:28 ; elapsed = 00:02:43 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6909 ; free virtual = 18035
-
-Phase 3.7 Re-assign LUT pins
-Phase 3.7 Re-assign LUT pins | Checksum: 1a0d4f18f
-
-Time (s): cpu = 00:07:32 ; elapsed = 00:02:47 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6909 ; free virtual = 18035
-
-Phase 3.8 Pipeline Register Optimization
-Phase 3.8 Pipeline Register Optimization | Checksum: 1c1e7f57f
-
-Time (s): cpu = 00:07:33 ; elapsed = 00:02:47 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6909 ; free virtual = 18035
-
-Phase 3.9 Fast Optimization
-Phase 3.9 Fast Optimization | Checksum: 1b4db73ed
-
-Time (s): cpu = 00:08:40 ; elapsed = 00:03:02 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6876 ; free virtual = 18003
-Phase 3 Detail Placement | Checksum: 1b4db73ed
-
-Time (s): cpu = 00:08:40 ; elapsed = 00:03:02 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6876 ; free virtual = 18003
-
-Phase 4 Post Placement Optimization and Clean-Up
-
-Phase 4.1 Post Commit Optimization
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-
-Phase 4.1.1 Post Placement Optimization
-Post Placement Optimization Initialization | Checksum: 10402c622
-
-Phase 4.1.1.1 BUFG Insertion
-
-Starting Physical Synthesis Task
-
-Phase 1 Physical Synthesis Initialization
-INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 12 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.221 | TNS=-1.166 |
-Phase 1 Physical Synthesis Initialization | Checksum: 14064eccb
-
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.69 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/apbReset_gps_apb_reset/io_sync_reset_chain/output_chain/sync_0_reg_1, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/pps/sync_0_reg, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_1, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-56] BUFG insertion identified 11 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 11, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
-Ending Physical Synthesis Task | Checksum: 1931fa2e7
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-Phase 4.1.1.1 BUFG Insertion | Checksum: 10402c622
-
-Time (s): cpu = 00:09:33 ; elapsed = 00:03:15 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-
-Phase 4.1.1.2 Post Placement Timing Optimization
-INFO: [Place 30-746] Post Placement Timing Summary WNS=0.074. For the most accurate timing information please run report_timing.
-Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: e9bcd183
-
-Time (s): cpu = 00:10:36 ; elapsed = 00:03:36 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-
-Time (s): cpu = 00:10:36 ; elapsed = 00:03:36 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-Phase 4.1 Post Commit Optimization | Checksum: e9bcd183
-
-Time (s): cpu = 00:10:36 ; elapsed = 00:03:36 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-
-Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: e9bcd183
-
-Time (s): cpu = 00:10:37 ; elapsed = 00:03:36 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-
-Phase 4.3 Placer Reporting
-
-Phase 4.3.1 Print Estimated Congestion
-INFO: [Place 30-612] Post-Placement Estimated Congestion
- ____________________________________________________
-| | Global Congestion | Short Congestion |
-| Direction | Region Size | Region Size |
-|___________|___________________|___________________|
-| North| 1x1| 4x4|
-|___________|___________________|___________________|
-| South| 1x1| 4x4|
-|___________|___________________|___________________|
-| East| 1x1| 2x2|
-|___________|___________________|___________________|
-| West| 1x1| 1x1|
-|___________|___________________|___________________|
-
-Phase 4.3.1 Print Estimated Congestion | Checksum: e9bcd183
-
-Time (s): cpu = 00:10:38 ; elapsed = 00:03:37 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-Phase 4.3 Placer Reporting | Checksum: e9bcd183
-
-Time (s): cpu = 00:10:38 ; elapsed = 00:03:37 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-
-Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-
-Time (s): cpu = 00:10:38 ; elapsed = 00:03:37 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 11a0295f2
-
-Time (s): cpu = 00:10:38 ; elapsed = 00:03:37 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-Ending Placer Task | Checksum: d0040437
-
-Time (s): cpu = 00:10:39 ; elapsed = 00:03:37 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-48 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-place_design completed successfully
-place_design: Time (s): cpu = 00:10:50 ; elapsed = 00:03:41 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6870 ; free virtual = 17997
-# write_checkpoint -force [file join $checkpoint_dir post_place.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6869 ; free virtual = 17997
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6869 ; free virtual = 17997
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6869 ; free virtual = 17997
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.15 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6843 ; free virtual = 17990
-Wrote PlaceStorage: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6713 ; free virtual = 17951
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6705 ; free virtual = 17953
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6705 ; free virtual = 17953
-Write Physdb Complete: Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6705 ; free virtual = 17953
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_place.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6813 ; free virtual = 17941
-# phys_opt_design -directive Explore
-Command: phys_opt_design -directive Explore
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
-
-Starting Initial Update Timing Task
-
-Time (s): cpu = 00:00:41 ; elapsed = 00:00:09 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6842 ; free virtual = 17969
-INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 0.074 | TNS= 0.000 |
-INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
-INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
-INFO: [Common 17-83] Releasing license: Implementation
-6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-phys_opt_design completed successfully
-phys_opt_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:09 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6842 ; free virtual = 17969
-# write_checkpoint -force [file join $checkpoint_dir post_phys_opt.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6842 ; free virtual = 17969
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6842 ; free virtual = 17969
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6842 ; free virtual = 17970
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.15 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6819 ; free virtual = 17966
-Wrote PlaceStorage: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6711 ; free virtual = 17950
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6704 ; free virtual = 17951
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6704 ; free virtual = 17952
-Write Physdb Complete: Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6704 ; free virtual = 17952
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_phys_opt.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6697 ; free virtual = 17892
-# route_design
-Command: route_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-
-
-Starting Routing Task
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 12 CPUs
-
-Phase 1 Build RT Design
-Checksum: PlaceDB: 68afa47c ConstDB: 0 ShapeSum: 3ed8e56b RouteDB: 287b7a50
-Post Restoration Checksum: NetGraph: 55bac3a5 | NumContArr: f696f831 | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 2d1a3b110
-
-Time (s): cpu = 00:00:59 ; elapsed = 00:00:20 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6753 ; free virtual = 17949
-
-Phase 2 Router Initialization
-
-Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 2d1a3b110
-
-Time (s): cpu = 00:01:00 ; elapsed = 00:00:20 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6754 ; free virtual = 17950
-
-Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 2d1a3b110
-
-Time (s): cpu = 00:01:00 ; elapsed = 00:00:20 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6754 ; free virtual = 17950
- Number of Nodes with overlaps = 0
-
-Phase 2.3 Update Timing
-Phase 2.3 Update Timing | Checksum: 1e1945268
-
-Time (s): cpu = 00:01:56 ; elapsed = 00:00:35 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6736 ; free virtual = 17933
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.121 | TNS=0.000 | WHS=-0.362 | THS=-2045.289|
-
-
-Phase 2.4 Soft Constraint Pins - Fast Budgeting
-Phase 2.4 Soft Constraint Pins - Fast Budgeting | Checksum: 1d3f44bf0
-
-Time (s): cpu = 00:02:10 ; elapsed = 00:00:38 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6736 ; free virtual = 17933
-
-Router Utilization Summary
- Global Vertical Routing Utilization = 0.00238349 %
- Global Horizontal Routing Utilization = 0.0012969 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 103032
- (Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 103014
- Number of Partially Routed Nets = 18
- Number of Node Overlaps = 1
-
-Phase 2 Router Initialization | Checksum: 12e0a82ba
-
-Time (s): cpu = 00:02:12 ; elapsed = 00:00:38 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6697 ; free virtual = 17894
-
-Phase 3 Global Routing
-Phase 3 Global Routing | Checksum: 12e0a82ba
-
-Time (s): cpu = 00:02:12 ; elapsed = 00:00:38 . Memory (MB): peak = 4327.207 ; gain = 0.000 ; free physical = 6697 ; free virtual = 17894
-
-Phase 4 Initial Routing
-
-Phase 4.1 Initial Net Routing Pass
-Phase 4.1 Initial Net Routing Pass | Checksum: 183c2fd57
-
-Time (s): cpu = 00:02:59 ; elapsed = 00:00:49 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6588 ; free virtual = 17785
-Phase 4 Initial Routing | Checksum: 183c2fd57
-
-Time (s): cpu = 00:02:59 ; elapsed = 00:00:49 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6588 ; free virtual = 17785
-INFO: [Route 35-580] Design has 1 pins with tight setup and hold constraints.
-
-The top 5 pins with tight setup and hold constraints:
-
-+====================+===================+=========================================================================================================+
-| Launch Setup Clock | Launch Hold Clock | Pin |
-+====================+===================+=========================================================================================================+
-| pll_gps_acq_clk | pll_gps_acq_clk | u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_42/DIBDI[1] |
-+--------------------+-------------------+---------------------------------------------------------------------------------------------------------+
-
-File with complete list of pins: tight_setup_hold_pins.txt
-
-
-Phase 5 Rip-up And Reroute
-
-Phase 5.1 Global Iteration 0
- Number of Nodes with overlaps = 9623
- Number of Nodes with overlaps = 187
- Number of Nodes with overlaps = 12
- Number of Nodes with overlaps = 2
- Number of Nodes with overlaps = 0
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.218 | TNS=0.000 | WHS=N/A | THS=N/A |
-
-Phase 5.1 Global Iteration 0 | Checksum: 266dd5aa5
-
-Time (s): cpu = 00:04:09 ; elapsed = 00:01:19 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6596 ; free virtual = 17793
-Phase 5 Rip-up And Reroute | Checksum: 266dd5aa5
-
-Time (s): cpu = 00:04:10 ; elapsed = 00:01:19 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6596 ; free virtual = 17793
-
-Phase 6 Delay and Skew Optimization
-
-Phase 6.1 Delay CleanUp
-Phase 6.1 Delay CleanUp | Checksum: 266dd5aa5
-
-Time (s): cpu = 00:04:10 ; elapsed = 00:01:19 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6596 ; free virtual = 17793
-
-Phase 6.2 Clock Skew Optimization
-Phase 6.2 Clock Skew Optimization | Checksum: 266dd5aa5
-
-Time (s): cpu = 00:04:10 ; elapsed = 00:01:19 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17791
-Phase 6 Delay and Skew Optimization | Checksum: 266dd5aa5
-
-Time (s): cpu = 00:04:10 ; elapsed = 00:01:19 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17791
-
-Phase 7 Post Hold Fix
-
-Phase 7.1 Hold Fix Iter
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.218 | TNS=0.000 | WHS=0.060 | THS=0.000 |
-
-Phase 7.1 Hold Fix Iter | Checksum: 2ec337fa5
-
-Time (s): cpu = 00:04:18 ; elapsed = 00:01:21 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17792
-Phase 7 Post Hold Fix | Checksum: 2ec337fa5
-
-Time (s): cpu = 00:04:18 ; elapsed = 00:01:21 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17792
-
-Phase 8 Route finalize
-
-Router Utilization Summary
- Global Vertical Routing Utilization = 10.0875 %
- Global Horizontal Routing Utilization = 10.7798 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 0
- (Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 0
- Number of Partially Routed Nets = 0
- Number of Node Overlaps = 0
-
-Phase 8 Route finalize | Checksum: 2ec337fa5
-
-Time (s): cpu = 00:04:19 ; elapsed = 00:01:21 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17792
-
-Phase 9 Verifying routed nets
-
- Verification completed successfully
-Phase 9 Verifying routed nets | Checksum: 2ec337fa5
-
-Time (s): cpu = 00:04:19 ; elapsed = 00:01:21 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17792
-
-Phase 10 Depositing Routes
-Phase 10 Depositing Routes | Checksum: 304d0f3a1
-
-Time (s): cpu = 00:04:29 ; elapsed = 00:01:27 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17791
-
-Phase 11 Post Process Routing
-Phase 11 Post Process Routing | Checksum: 304d0f3a1
-
-Time (s): cpu = 00:04:30 ; elapsed = 00:01:27 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17791
-
-Phase 12 Post Router Timing
-INFO: [Route 35-57] Estimated Timing Summary | WNS=0.218 | TNS=0.000 | WHS=0.060 | THS=0.000 |
-
-INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
-Phase 12 Post Router Timing | Checksum: 304d0f3a1
-
-Time (s): cpu = 00:04:30 ; elapsed = 00:01:27 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17791
-Total Elapsed time in route_design: 86.9 secs
-
-Phase 13 Post-Route Event Processing
-Phase 13 Post-Route Event Processing | Checksum: 16e0d61ad
-
-Time (s): cpu = 00:04:31 ; elapsed = 00:01:27 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17791
-INFO: [Route 35-16] Router Completed Successfully
-Ending Routing Task | Checksum: 16e0d61ad
-
-Time (s): cpu = 00:04:31 ; elapsed = 00:01:27 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17791
-
-Routing Is Done.
-INFO: [Common 17-83] Releasing license: Implementation
-10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-route_design completed successfully
-route_design: Time (s): cpu = 00:04:32 ; elapsed = 00:01:28 . Memory (MB): peak = 4355.180 ; gain = 27.973 ; free physical = 6594 ; free virtual = 17791
-# write_checkpoint -force [file join $checkpoint_dir post_route.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4355.180 ; gain = 0.000 ; free physical = 6594 ; free virtual = 17791
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4355.180 ; gain = 0.000 ; free physical = 6594 ; free virtual = 17791
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.17 . Memory (MB): peak = 4355.180 ; gain = 0.000 ; free physical = 6571 ; free virtual = 17784
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:07 ; elapsed = 00:00:01 . Memory (MB): peak = 4355.180 ; gain = 0.000 ; free physical = 6524 ; free virtual = 17786
-Wrote PlaceStorage: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 4355.180 ; gain = 0.000 ; free physical = 6437 ; free virtual = 17766
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4355.180 ; gain = 0.000 ; free physical = 6429 ; free virtual = 17768
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4355.180 ; gain = 0.000 ; free physical = 6429 ; free virtual = 17768
-Write Physdb Complete: Time (s): cpu = 00:00:11 ; elapsed = 00:00:04 . Memory (MB): peak = 4355.180 ; gain = 0.000 ; free physical = 6429 ; free virtual = 17768
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_route.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 4355.180 ; gain = 0.000 ; free physical = 6438 ; free virtual = 17711
-# report_utilization -file [file join $report_dir route_utilization.rpt]
-# report_timing_summary -file [file join $report_dir route_timing_summary.rpt]
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs
-report_timing_summary: Time (s): cpu = 00:00:45 ; elapsed = 00:00:09 . Memory (MB): peak = 4355.180 ; gain = 0.000 ; free physical = 6469 ; free virtual = 17742
-# report_drc -file [file join $report_dir route_drc.rpt]
-Command: report_drc -file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/route_drc.rpt
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.2/data/ip'.
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/route_drc.rpt.
-report_drc completed successfully
-# report_power -file [file join $report_dir route_power.rpt]
-Command: report_power -file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/route_power.rpt
-INFO: [Power 33-23] Power model is not available for u_cfg_flash_startup
-Running Vector-less Activity Propagation...
-
-Finished Running Vector-less Activity Propagation
-WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
-Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
-1 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
-report_power completed successfully
-report_power: Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 4459.230 ; gain = 104.051 ; free physical = 6475 ; free virtual = 17749
-# set bit_file [file join $bit_dir genesys2_rocket.bit]
-# puts "Writing bitstream: $bit_file"
-Writing bitstream: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-# write_bitstream -force $bit_file
-Command: write_bitstream -force /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-Running DRC as a precondition to command write_bitstream
-INFO: [IP_Flow 19-1839] IP Catalog is up to date.
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado 12-3199] DRC finished with 0 Errors
-INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
-Integrating Hard IP ELF/MEM with the PDI.
-INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
-Loading data files...
-Loading site data...
-Loading route data...
-Processing options...
-Creating bitmap...
-Creating bitstream...
-Writing bitstream /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit...
-INFO: [Vivado 12-1842] Bitgen Completed Successfully.
-INFO: [Common 17-83] Releasing license: Implementation
-8 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:01:53 ; elapsed = 00:00:24 . Memory (MB): peak = 4816.023 ; gain = 356.793 ; free physical = 6072 ; free virtual = 17350
-# puts "Genesys2 non-project flow complete."
-Genesys2 non-project flow complete.
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 17:50:54 2026...
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream_176305.backup.jou b/targets/fpga/genesys2/out/logs/build_bitstream_176305.backup.jou
deleted file mode 100644
index 09d1fe7..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream_176305.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 19:21:37 2026
-# Process ID : 176305
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21572 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream_176305.backup.log b/targets/fpga/genesys2/out/logs/build_bitstream_176305.backup.log
deleted file mode 100644
index 799554f..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream_176305.backup.log
+++ /dev/null
@@ -1,5547 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 19:21:37 2026
-# Process ID : 176305
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21572 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../../..]]
-# set repo_dir [file normalize [file join $fpga_dir ../../..]]
-# set hardware_dir [file join $repo_dir hardware]
-# cd $repo_dir
-# set part_name "xc7k325tffg900-2"
-# set board_part "digilentinc.com:genesys2:part0:1.1"
-# set top_module "genesys2_rocket_top"
-# set out_dir [file join $fpga_dir out]
-# set generated_dir [file join $out_dir build generated]
-# set report_dir [file join $out_dir reports]
-# set bit_dir [file join $out_dir bitstream]
-# set checkpoint_dir [file join $out_dir build checkpoints]
-# file mkdir $generated_dir
-# file mkdir $report_dir
-# file mkdir $bit_dir
-# file mkdir $checkpoint_dir
-# set rocket_rtl_dir [file join $hardware_dir generated genesys2-soc-verilog]
-# set rocket_top [file join $rocket_rtl_dir VCU118RocketSystem.sv]
-# set rocket_filelist [file join $rocket_rtl_dir filelist.f]
-# set wrapper [file join $generated_dir ${top_module}.sv]
-# if {[info exists ::env(GPS_SYSTEM_DIR)] && [string trim $::env(GPS_SYSTEM_DIR)] ne ""} {
-# set gps_system_dir [file normalize $::env(GPS_SYSTEM_DIR)]
-# } else {
-# set gps_system_dir [file join $hardware_dir external gps rtl]
-# }
-# if {[info exists ::env(RF_INPUT_MODE)]} {
-# set rf_input_mode [string tolower [string trim $::env(RF_INPUT_MODE)]]
-# } else {
-# set rf_input_mode "pmod"
-# }
-# if {$rf_input_mode ni {"pmod" "generated" "ethernet"}} {
-# error "Unsupported Genesys2 RF_INPUT_MODE=$rf_input_mode. Use pmod, generated, or ethernet."
-# }
-# if {![file exists $rocket_filelist]} {
-# error "Rocket Verilog filelist not found: $rocket_filelist"
-# }
-# if {![file exists $rocket_top]} {
-# error "Rocket top Verilog not found: $rocket_top"
-# }
-# puts "Generating Genesys2 wrapper: $wrapper"
-Generating Genesys2 wrapper: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv
-# puts "Genesys2 RF input mode: $rf_input_mode"
-Genesys2 RF input mode: pmod
-# exec python3 [file join $fpga_dir tools gen_genesys2_wrapper.py] \
-# --rocket-top $rocket_top \
-# --out $wrapper \
-# --rf-input-mode $rf_input_mode
-# set max_threads [string trim [exec nproc]]
-# puts "Using Vivado maxThreads=$max_threads"
-Using Vivado maxThreads=12
-# set_param general.maxThreads $max_threads
-# set_part $part_name
-INFO: [Coretcl 2-1500] The part has been set to 'xc7k325tffg900-2' for the current project only. Run set_part -help for more details. To evaluate different speed grades in the current design, use the set_speed_grade command, or use the open_checkpoint -part command to change the part used by an existing checkpoint design.
-# if {[llength [get_board_parts -quiet $board_part]] != 0} {
-# set_property board_part $board_part [current_project]
-# }
-# proc apply_genesys2_async_clock_groups {} {
-# set fabric_clk [get_clocks -quiet pll_fabric_clk]
-# set gps_acq_clk [get_clocks -quiet pll_gps_acq_clk]
-# set gps_trck_clk [get_clocks -quiet pll_gps_trck_clk]
-# set gps_ref_clk [get_clocks -quiet pll_gps_ref_clk]
-# set gps_clocks [get_clocks -quiet {
-# pll_gps_rf_exact_clk
-# pmod_rf_clk
-# pll_gps_ref_clk
-# pll_gps_acq_clk
-# pll_gps_trck_clk
-# }]
-# set eth_clk [get_clocks -quiet genesys2_eth_rxck]
-#
-# if {[llength $fabric_clk] == 0 ||
-# [llength $gps_acq_clk] == 0 ||
-# [llength $gps_trck_clk] == 0 ||
-# [llength $gps_ref_clk] == 0 ||
-# [llength $gps_clocks] == 0} {
-# puts "Warning: not all Genesys2 async clock groups are available yet."
-# return
-# }
-#
-# puts "Applying Genesys2 async clock groups."
-# set args [list -asynchronous \
-# -group $fabric_clk \
-# -group $gps_clocks]
-# if {[llength $eth_clk] != 0} {
-# lappend args -group $eth_clk
-# }
-# set_clock_groups {*}$args
-# }
-# set rocket_files {}
-# set fh [open $rocket_filelist r]
-# while {[gets $fh line] >= 0} {
-# set line [string trim $line]
-# if {$line eq ""} {
-# continue
-# }
-# set line [regsub {^\./} $line ""]
-# lappend rocket_files [file normalize [file join $rocket_rtl_dir $line]]
-# }
-# close $fh
-# puts "Reading Rocket Chip RTL..."
-Reading Rocket Chip RTL...
-# read_verilog -sv $rocket_files
-# read_verilog [file join $hardware_dir upstream rocket-chip src main resources vsrc plusarg_reader.v]
-# set gps_filelist [file join $hardware_dir external gps rtl filelist.f]
-# set gps_files {}
-# set gps_fh [open $gps_filelist r]
-# while {[gets $gps_fh rel] >= 0} {
-# set rel [string trim $rel]
-# if {$rel eq "" || [string match "#*" $rel]} {
-# continue
-# }
-# lappend gps_files [file join $gps_system_dir $rel]
-# }
-# close $gps_fh
-# puts "Reading GPS APB wrapper RTL from $gps_system_dir..."
-Reading GPS APB wrapper RTL from /home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl...
-# set_property include_dirs [list [file join $gps_system_dir trck_src pulp_fifo]] [current_fileset]
-# read_verilog -sv $gps_files
-# puts "Reading Genesys2 shell RTL..."
-Reading Genesys2 shell RTL...
-# set shell_files [list \
-# [file join $hardware_dir fpga vcu118 rtl axi4_ram_64.sv] \
-# [file join $hardware_dir fpga vcu118 rtl axi4_slave_tieoff_64.sv] \
-# [file join $hardware_dir fpga genesys2 rtl rocket_bscan_dmi_tunnel.sv] \
-# ]
-# if {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet RF RTL..."
-# lappend shell_files \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_async_fifo.sv] \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_core.sv] \
-# [file join $hardware_dir fpga genesys2 rtl ethernet_rf eth_rf_genesys2.sv]
-# } else {
-# puts "Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=$rf_input_mode."
-# }
-Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=pmod.
-# read_verilog -sv $shell_files
-# read_verilog -sv $wrapper
-# puts "Reading constraints..."
-Reading constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_rocket.xdc]
-# puts "Reading Genesys2 PMOD SPI constraints..."
-Reading Genesys2 PMOD SPI constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_spi.xdc]
-# puts "Reading Genesys2 PMOD sensor IRQ constraints..."
-Reading Genesys2 PMOD sensor IRQ constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_irq.xdc]
-# puts "Reading Genesys2 PMOD PPS constraints..."
-Reading Genesys2 PMOD PPS constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_pps.xdc]
-# if {$rf_input_mode eq "pmod"} {
-# puts "Reading Genesys2 PMOD RF constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_rf.xdc]
-# } elseif {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet PHY constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_ethernet.xdc]
-# }
-Reading Genesys2 PMOD RF constraints...
-# puts "Running synthesis for $part_name..."
-Running synthesis for xc7k325tffg900-2...
-# synth_design -top $top_module -part $part_name -verilog_define SYNTHESIS
-Command: synth_design -top genesys2_rocket_top -part xc7k325tffg900-2 -verilog_define SYNTHESIS
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Device 21-403] Loading part xc7k325tffg900-2
-INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
-INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 176332
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2305.227 ; gain = 483.875 ; free physical = 7440 ; free virtual = 19107
----------------------------------------------------------------------------------
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:8]
-WARNING: [Synth 8-11067] parameter 'CODE_LENGTH_IN_CHIPS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:9]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:10]
-WARNING: [Synth 8-11067] parameter 'SAMPLING_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:13]
-WARNING: [Synth 8-11067] parameter 'CENTER_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:14]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:15]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:16]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:17]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:18]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:19]
-WARNING: [Synth 8-11067] parameter 'ABS_SAMPLE_CNTR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:22]
-WARNING: [Synth 8-11067] parameter 'MS_PER_BIT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:23]
-WARNING: [Synth 8-11067] parameter 'C_ACQ_CHN_NUM' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:26]
-WARNING: [Synth 8-11067] parameter 'ACQ_IQ_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:27]
-WARNING: [Synth 8-11067] parameter 'ACQ_CORR_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:28]
-WARNING: [Synth 8-11067] parameter 'RF_DMEM_AL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:30]
-WARNING: [Synth 8-11067] parameter 'NUM_PRN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:31]
-WARNING: [Synth 8-11067] parameter 'PRN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:32]
-WARNING: [Synth 8-11067] parameter 'STRECH_COUNT_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:33]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_COEF1' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:40]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:41]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:42]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:43]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:44]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:45]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_FREQ_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:46]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:47]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:48]
-WARNING: [Synth 8-11067] parameter 'NUM_TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:50]
-WARNING: [Synth 8-11067] parameter 'TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:51]
-WARNING: [Synth 8-11067] parameter 'ATAN_ANGLE_BIT_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:56]
-WARNING: [Synth 8-11067] parameter 'ATAN_TABLE_SIZE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:57]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:60]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:61]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:62]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_SPACE_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:63]
-WARNING: [Synth 8-11067] parameter 'C1_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:65]
-WARNING: [Synth 8-11067] parameter 'C2_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:66]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:71]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:72]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:73]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:76]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:77]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:78]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:80]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:81]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:83]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:84]
-WARNING: [Synth 8-11067] parameter 'LOCK_WINDOW' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:85]
-WARNING: [Synth 8-11067] parameter 'LOCK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:86]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:89]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:90]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:92]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:93]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:95]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:96]
-WARNING: [Synth 8-11067] parameter 'CODE_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:99]
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:100]
-WARNING: [Synth 8-11067] parameter 'REAL_POS_FS_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:102]
-WARNING: [Synth 8-11067] parameter 'REAL_NEG_FS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:103]
-WARNING: [Synth 8-11067] parameter 'FS_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:105]
-WARNING: [Synth 8-11067] parameter 'DLL_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:106]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:108]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:109]
-WARNING: [Synth 8-11067] parameter 'REM_CODE_PH_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:110]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:113]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:114]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:115]
-WARNING: [Synth 8-11067] parameter 'F_ACQ_CLK' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:118]
-WARNING: [Synth 8-11067] parameter 'ACQ_CLK_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:119]
-WARNING: [Synth 8-11067] parameter 'RF_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:120]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE_CHIP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:121]
-WARNING: [Synth 8-11067] parameter 'ACQ_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:123]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:124]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:125]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:126]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:127]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:128]
-WARNING: [Synth 8-11067] parameter 'ACQ_CODE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:130]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:132]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:133]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:134]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:135]
-WARNING: [Synth 8-11067] parameter 'IFFT_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:136]
-WARNING: [Synth 8-11067] parameter 'IFFT_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:137]
-WARNING: [Synth 8-11067] parameter 'IFFT_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:139]
-WARNING: [Synth 8-11067] parameter 'NFFT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:141]
-WARNING: [Synth 8-11067] parameter 'NFFT_OVER_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:142]
-WARNING: [Synth 8-11067] parameter 'ZERO_PAD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:143]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:145]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:146]
-WARNING: [Synth 8-11067] parameter 'ABS_SQR_I_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:147]
-WARNING: [Synth 8-11067] parameter 'CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:148]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_DIV_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:149]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:150]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:151]
-WARNING: [Synth 8-11067] parameter 'PEAK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:152]
-WARNING: [Synth 8-11067] parameter 'DOPP_STEP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:154]
-WARNING: [Synth 8-11067] parameter 'NUM_FREQ_BIN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:155]
-WARNING: [Synth 8-11067] parameter 'FREQ_BIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:156]
-INFO: [Common 17-14] Message 'Synth 8-11067' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-10180] variable 'i' must explicitly be declared as automatic or static [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv:53]
-INFO: [Synth 8-6157] synthesizing module 'genesys2_rocket_top' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:3]
-INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
- Parameter DIFF_TERM bound to: FALSE - type: string
- Parameter IBUF_LOW_PWR bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 5.000000e+00 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 5.000000e+00 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.250000e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT1_DIVIDE bound to: 20 - type: integer
- Parameter CLKOUT1_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT1_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT2_DIVIDE bound to: 8 - type: integer
- Parameter CLKOUT2_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT2_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:75]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:75]
-WARNING: [Synth 8-7023] instance 'u_clock_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:75]
-INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6157] synthesizing module 'IBUF' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV__parameterized0' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 5.812500e+01 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 6.109500e+01 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.712500e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV__parameterized0' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_ref_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:152]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_ref_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:152]
-WARNING: [Synth 8-7023] instance 'u_gps_ref_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:152]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV__parameterized1' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 1.800000e+01 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 1.800000e+01 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.250000e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer
- Parameter CLKOUT1_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT1_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV__parameterized1' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_domain_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:212]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_domain_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:212]
-WARNING: [Synth 8-7023] instance 'u_gps_domain_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:212]
-INFO: [Synth 8-6157] synthesizing module 'BSCANE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
- Parameter DISABLE_JTAG bound to: FALSE - type: string
- Parameter JTAG_CHAIN bound to: 4 - type: integer
-INFO: [Synth 8-6155] done synthesizing module 'BSCANE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
-INFO: [Synth 8-6157] synthesizing module 'rocket_bscan_dmi_tunnel' [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'rocket_bscan_dmi_tunnel' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:388]
-INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
- Parameter PROG_USR bound to: FALSE - type: string
- Parameter SIM_CCLK_FREQ bound to: 0.000000e+00 - type: double
-INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
-INFO: [Synth 8-6157] synthesizing module 'VCU118RocketSystem' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/VCU118RocketSystem.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockSinkDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i2_o1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i2_o1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockSinkDomain' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_aggregator' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_aggregator' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_sbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_sbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroup' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroup' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_5' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_5' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x120' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x120' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x77' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x77' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAUART' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAUART' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_gps' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAGPS' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAGPS' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_2' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_2' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_gps' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FrontBus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x123' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x123' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FrontBus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_2' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_2' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x124' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x124' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x78' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x78' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x99' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x99' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_debug' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_Debug' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_Debug' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_debug' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_4' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_4' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TilePRCIDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'HierarchicalElementResetDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/HierarchicalElementResetDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'RocketTile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/RocketTile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i3_o1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
-INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i3_o1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PMPChecker_s3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PMPChecker_s3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PMAChecker' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PMAChecker.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:194]
-INFO: [Synth 8-6155] done synthesizing module 'OptimizationBarrier_TLBEntryData' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/OptimizationBarrier_TLBEntryData.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:228]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:262]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:296]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:330]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:364]
-INFO: [Synth 8-6155] done synthesizing module 'DTLB' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:1121]
-INFO: [Synth 8-6155] done synthesizing module 'Arbiter8_DCacheMetadataReq' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Arbiter8_DCacheMetadataReq.sv:31]
-INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:139]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:173]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:207]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:241]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:275]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:309]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PTW.sv:188]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:3191]
- Parameter FORMAT bound to: max_core_cycles=%d - type: string
- Parameter WIDTH bound to: 32 - type: integer
- Parameter DEFAULT bound to: 32'b00000000000000000000000000000000
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:400]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:406]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:412]
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000000001
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter DATA_WIDTH bound to: 4 - type: integer
- Parameter ADDR_WIDTH bound to: 15 - type: integer
- Parameter PH_ACC_WL bound to: 32 - type: integer
- Parameter LUT_DEPTH_WL bound to: 5 - type: integer
- Parameter ACQ_SIN_IL bound to: 2 - type: integer
- Parameter ACQ_SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 25 - type: integer
- Parameter FS bound to: 16368000 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 52 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 36 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_IQ_WL bound to: 24 - type: integer
- Parameter FFT_IQ_TRUNC_WL bound to: 20 - type: integer
- Parameter FFT_CODE_WL bound to: 16 - type: integer
- Parameter FFT_CODE_TRUNC_WL bound to: 16 - type: integer
- Parameter OUT_WL bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 92 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter DWIDTH bound to: 48 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ABS_SQR_I_TRUNCATED_WL bound to: 25 - type: integer
- Parameter CORR_DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter SAMPLES_PER_CODE_CHIP bound to: 16 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv:158]
- Parameter DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ITER bound to: 9 - type: integer
- Parameter IN_W_L bound to: 36 - type: integer
- Parameter IN_F_L bound to: 0 - type: integer
- Parameter OUT_W_L bound to: 16 - type: integer
- Parameter OUT_F_L bound to: 8 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:285]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:296]
-WARNING: [Synth 8-151] case item 32'b00000000000000000000000000001100 is unreachable [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:350]
-WARNING: [Synth 8-7071] port 'clk_200mhz' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'mmcm_locked' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rd' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rxc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_td' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_tx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_txc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7023] instance 'afe' of module 'afe_top' has 17 connections declared, but only 9 given [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000100000
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter SIG_DEPTH bound to: 26 - type: integer
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:182]
- Parameter WIDTH bound to: 4 - type: integer
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter STAGES bound to: 32'b00000000000000000000000000000010
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter Bypass bound to: 1'b0
- Parameter PH_ACC_WL bound to: 24 - type: integer
- Parameter LUT_DEPTH_WL bound to: 7 - type: integer
- Parameter SIN_IL bound to: 2 - type: integer
- Parameter SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 46 - type: integer
- Parameter CODE_FREQ_I_IL bound to: 21 - type: integer
- Parameter CODE_FREQ_I_FL bound to: 20 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 10 - type: integer
- Parameter O_IL bound to: 16 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 13 - type: integer
- Parameter O_IL bound to: 8 - type: integer
- Parameter O_FL bound to: 20 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter TABLE_ADDR bound to: 4 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 33 - type: integer
-WARNING: [Synth 8-7071] port 'vec_len_o' of module 'cordic_atan_basic' is unconnected for instance 'Disc_PLL_i' [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:218]
-WARNING: [Synth 8-7023] instance 'Disc_PLL_i' of module 'cordic_atan_basic' has 8 connections declared, but only 7 given [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:218]
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER1 bound to: 8 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter TABLE_ADDR bound to: 3 - type: integer
-WARNING: [Synth 8-151] case item 4'b1000 is unreachable [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:114]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:105]
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 32 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 25 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter DIV_OUT_WL bound to: 15 - type: integer
- Parameter DIV_OUT_FL bound to: 13 - type: integer
- Parameter DIV_ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 45 - type: integer
- Parameter IN_FL bound to: 8 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:288]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:546]
- Parameter HIGH_ADDRESS bound to: 32'b00000000000000000000111111111111
- Parameter LOW_ADDRESS bound to: 32'b00000000000000000000000000000000
- Parameter DATA_BUS_WIDTH bound to: 32'b00000000000000000000000000100000
- Parameter ADDR_BUS_WIDTH bound to: 32'b00000000000000000000000000001100
- Parameter NUM_CAPTURE_CHANNELS bound to: 32'b00000000000000000000000000001001
- Parameter CLK_FREQ_HZ bound to: 32'b00000111011100110101100101000000
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:48]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:49]
-WARNING: [Synth 8-6014] Unused sequential element s2_vaddr_r_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:989]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:47]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:48]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:47]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:48]
-WARNING: [Synth 8-4767] Trying to implement RAM 'Memory_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/regfile_32x65.sv:60]
-Reason is one or more of the following :
- 1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
- 2: Invalid write to RAM.
- 3: Invalid write to RAM.
- 4: No valid clock found for write to RAM.
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2183]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2626]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2637]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2754]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2755]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2757]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2758]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2769]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2770]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2772]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2773]
-WARNING: [Synth 8-6014] Unused sequential element rocc_blocked_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2894]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2895]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2896]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2897]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2898]
-WARNING: [Synth 8-6014] Unused sequential element r_counter_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError_1.sv:69]
-Read & Write Range Direction Mismatch
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module comp_mult has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/comp_mult.sv:106]
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module ifft_abs_sqr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:90]
-WARNING: [Synth 8-3848] Net eth_rgmii_td in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:38]
-WARNING: [Synth 8-3848] Net eth_rgmii_tx_ctl in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:39]
-WARNING: [Synth 8-3848] Net eth_rgmii_txc in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:40]
-WARNING: [Synth 8-3848] Net rf_data_o in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:46]
-WARNING: [Synth 8-3848] Net fifo_of_o in module/entity trck_cntrl does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:50]
-WARNING: [Synth 8-6014] Unused sequential element g1_var_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:46]
-WARNING: [Synth 8-7137] Register chip_o_reg in module cacode_gen_trck has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:36]
-WARNING: [Synth 8-7129] Port PENABLE in module pps_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port fifo_of_o in module trck_cntrl is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port trck_resetn in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port afe_resetn in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_tx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_txc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port clk_200mhz in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port mmcm_locked in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rxc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port start_acq_manuel in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_en in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_clk in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[3] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_sink in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[127] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[126] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[125] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[124] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[123] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[122] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[121] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[120] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[119] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[118] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[117] in module SBToTL is either unconnected or has no load
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 2705.516 ; gain = 884.164 ; free physical = 7112 ; free virtual = 18786
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 2705.516 ; gain = 884.164 ; free physical = 7136 ; free virtual = 18810
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 2705.516 ; gain = 884.164 ; free physical = 7136 ; free virtual = 18810
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.65 . Memory (MB): peak = 2708.484 ; gain = 0.000 ; free physical = 7160 ; free virtual = 18834
-INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-INFO: [Timing 38-2] Deriving generated clocks
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2998.961 ; gain = 0.000 ; free physical = 7044 ; free virtual = 18718
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3010.883 ; gain = 0.000 ; free physical = 7045 ; free virtual = 18719
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:29 . Memory (MB): peak = 3010.883 ; gain = 1189.531 ; free physical = 5878 ; free virtual = 17553
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7k325tffg900-2
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:29 . Memory (MB): peak = 3018.887 ; gain = 1197.535 ; free physical = 5878 ; free virtual = 17553
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:29 . Memory (MB): peak = 3018.887 ; gain = 1197.535 ; free physical = 5886 ; free virtual = 17560
----------------------------------------------------------------------------------
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:405]
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:443]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '99' to '12' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:57]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore2_addr_reg' and it is trimmed from '34' to '20' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:383]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore1_addr_reg' and it is trimmed from '34' to '20' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:383]
-WARNING: [Synth 8-3936] Found unconnected internal register 'uncachedReqs_0_addr_reg' and it is trimmed from '34' to '3' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:958]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in1_reg' and it is trimmed from '65' to '33' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:58]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in3_reg' and it is trimmed from '65' to '33' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:60]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPToInt.sv:173]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_typeTagOut_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPToInt.sv:95]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_pipe_b_typeTagIn_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntToFP.sv:66]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:524]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:333]
-WARNING: [Synth 8-3936] Found unconnected internal register 'load_wb_typeTag_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:142]
-WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2787]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2787]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2822]
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized1'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_peak_srch'
-INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'divider_fsm'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_top'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'acq_wrapper'
-INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'trck_cntrl'
-INFO: [Synth 8-802] inferred FSM for state register 'nav_solve_state_p_reg' in module 'nav_solve_timer'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'tracking_wrapper'
-INFO: [Synth 8-802] inferred FSM for state register 'commit_state_p_reg' in module 'pps_core'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'pps_wrapper'
-WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '88' to '87' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a29d32s7k1z2u.sv:66]
-WARNING: [Synth 8-6841] Block RAM (Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-INFO: [Synth 8-3971] The signal "dual_port_bram:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized0:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized1:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized1'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 001 | 000
- S_CORR | 101 | 001
- S_INIT_ADDR | 100 | 010
- S_DATA_Q | 011 | 011
- S_SRCH | 010 | 100
- S_END | 000 | 101
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'sequential' in module 'acq_peak_srch'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- idle | 00 | 00
- normalization | 01 | 01
- cordic_core | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'divider_fsm'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 0000001 | 000
- S_WR_DATA | 0001000 | 001
- S_START | 0010000 | 010
- S_CTRL | 1000000 | 011
- S_FREQ | 0100000 | 100
- S_END | 0000010 | 101
- S_PULLIN | 0000100 | 110
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'one-hot' in module 'acq_top'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'acq_wrapper'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- WAIT_START | 00 | 00
- WAIT_SAMPLE_ALIGN | 01 | 01
- WAIT_CODE_PHASE | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'trck_cntrl'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- iSTATE0 | 0 | 00000000000000000000000000000000
-*
- iSTATE | 1 | 00000000000000000000000000000001
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'nav_solve_state_p_reg' using encoding 'sequential' in module 'nav_solve_timer'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'tracking_wrapper'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- PPS_COMMIT_IDLE | 0000 | 0000
- PPS_COMMIT_FRACTION | 0001 | 0001
- PPS_COMMIT_AGE_CAPTURE | 0010 | 0010
- PPS_COMMIT_AGE_MULTIPLY | 0011 | 0011
- PPS_COMMIT_MAP | 0100 | 0100
- PPS_COMMIT_NORMALIZE | 0101 | 0101
- PPS_COMMIT_PHASE | 0110 | 0110
- PPS_COMMIT_PI_MULTIPLY | 0111 | 0111
- PPS_COMMIT_INTEGRATE | 1000 | 1000
-PPS_COMMIT_CLAMP_INTEGRATOR | 1001 | 1001
- PPS_COMMIT_APPLY | 1010 | 1010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'commit_state_p_reg' using encoding 'sequential' in module 'pps_core'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- PPS_APB_STATE_IDLE | 001 | 00
- PPS_APB_STATE_ACCESS | 100 | 01
- PPS_APB_STATE_FINISH | 010 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'pps_wrapper'
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 3018.887 ; gain = 1197.535 ; free physical = 2555 ; free virtual = 14239
----------------------------------------------------------------------------------
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_5'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_5'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'u_rocket/tile_prci_domain/intsource_2'
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
----------------------------------------------------------------------------------
-Start RTL Component Statistics
----------------------------------------------------------------------------------
-Detailed RTL Component Info :
-+---Adders :
- 3 Input 128 Bit Adders := 1
- 2 Input 112 Bit Adders := 1
- 3 Input 112 Bit Adders := 1
- 2 Input 109 Bit Adders := 1
- 2 Input 107 Bit Adders := 1
- 3 Input 99 Bit Adders := 1
- 2 Input 99 Bit Adders := 1
- 2 Input 66 Bit Adders := 1
- 3 Input 65 Bit Adders := 2
- 2 Input 65 Bit Adders := 3
- 2 Input 64 Bit Adders := 15
- 3 Input 64 Bit Adders := 2
- 2 Input 62 Bit Adders := 1
- 3 Input 61 Bit Adders := 1
- 3 Input 58 Bit Adders := 1
- 2 Input 58 Bit Adders := 2
- 2 Input 55 Bit Adders := 4
- 2 Input 51 Bit Adders := 2
- 2 Input 49 Bit Adders := 1
- 2 Input 46 Bit Adders := 11
- 3 Input 46 Bit Adders := 2
- 2 Input 45 Bit Adders := 18
- 3 Input 45 Bit Adders := 10
- 2 Input 42 Bit Adders := 1
- 2 Input 41 Bit Adders := 9
- 3 Input 41 Bit Adders := 1
- 2 Input 34 Bit Adders := 3
- 3 Input 33 Bit Adders := 18
- 2 Input 32 Bit Adders := 75
- 3 Input 32 Bit Adders := 58
- 2 Input 30 Bit Adders := 18
- 3 Input 30 Bit Adders := 1
- 3 Input 29 Bit Adders := 1
- 2 Input 28 Bit Adders := 18
- 2 Input 26 Bit Adders := 25
- 3 Input 26 Bit Adders := 2
- 2 Input 25 Bit Adders := 11
- 3 Input 25 Bit Adders := 9
- 2 Input 24 Bit Adders := 1
- 2 Input 23 Bit Adders := 54
- 2 Input 22 Bit Adders := 18
- 2 Input 18 Bit Adders := 2
- 3 Input 18 Bit Adders := 2
- 3 Input 16 Bit Adders := 1
- 2 Input 16 Bit Adders := 1
- 2 Input 15 Bit Adders := 2
- 2 Input 14 Bit Adders := 20
- 4 Input 14 Bit Adders := 1
- 3 Input 14 Bit Adders := 1
- 3 Input 13 Bit Adders := 2
- 2 Input 13 Bit Adders := 7
- 2 Input 12 Bit Adders := 13
- 3 Input 12 Bit Adders := 10
- 4 Input 11 Bit Adders := 1
- 2 Input 11 Bit Adders := 4
- 3 Input 10 Bit Adders := 2
- 2 Input 10 Bit Adders := 1
- 2 Input 9 Bit Adders := 11
- 3 Input 9 Bit Adders := 5
- 2 Input 8 Bit Adders := 5
- 2 Input 7 Bit Adders := 4
- 2 Input 6 Bit Adders := 24
- 3 Input 6 Bit Adders := 2
- 2 Input 5 Bit Adders := 41
- 2 Input 4 Bit Adders := 86
- 3 Input 4 Bit Adders := 1
- 3 Input 3 Bit Adders := 9
- 2 Input 3 Bit Adders := 35
- 2 Input 2 Bit Adders := 6
- 3 Input 2 Bit Adders := 4
- 4 Input 2 Bit Adders := 1
- 5 Input 2 Bit Adders := 1
- 3 Input 1 Bit Adders := 3
- 2 Input 1 Bit Adders := 41
-+---XORs :
- 2 Input 65 Bit XORs := 1
- 2 Input 64 Bit XORs := 7
- 2 Input 33 Bit XORs := 1
- 2 Input 32 Bit XORs := 8
- 2 Input 29 Bit XORs := 16
- 2 Input 17 Bit XORs := 48
- 2 Input 16 Bit XORs := 2
- 2 Input 15 Bit XORs := 5
- 2 Input 14 Bit XORs := 1
- 2 Input 12 Bit XORs := 4
- 2 Input 10 Bit XORs := 4
- 2 Input 5 Bit XORs := 38
- 2 Input 4 Bit XORs := 2
- 2 Input 3 Bit XORs := 23
- 2 Input 2 Bit XORs := 7
- 2 Input 1 Bit XORs := 485
- 3 Input 1 Bit XORs := 68
- 6 Input 1 Bit XORs := 19
- 7 Input 1 Bit XORs := 18
- 13 Input 1 Bit XORs := 90
- 11 Input 1 Bit XORs := 63
- 12 Input 1 Bit XORs := 63
- 8 Input 1 Bit XORs := 54
- 10 Input 1 Bit XORs := 72
- 4 Input 1 Bit XORs := 54
- 14 Input 1 Bit XORs := 117
- 5 Input 1 Bit XORs := 18
- 15 Input 1 Bit XORs := 9
- 9 Input 1 Bit XORs := 54
- 16 Input 1 Bit XORs := 9
-+---XORs :
- 5 Bit Wide XORs := 36
- 4 Bit Wide XORs := 36
- 3 Bit Wide XORs := 36
- 2 Bit Wide XORs := 36
-+---Registers :
- 310 Bit Registers := 9
- 130 Bit Registers := 1
- 112 Bit Registers := 5
- 107 Bit Registers := 1
- 104 Bit Registers := 1
- 99 Bit Registers := 1
- 98 Bit Registers := 1
- 92 Bit Registers := 2
- 90 Bit Registers := 3
- 87 Bit Registers := 1
- 65 Bit Registers := 45
- 64 Bit Registers := 68
- 62 Bit Registers := 2
- 58 Bit Registers := 2
- 56 Bit Registers := 1
- 55 Bit Registers := 13
- 53 Bit Registers := 1
- 52 Bit Registers := 2
- 51 Bit Registers := 8
- 50 Bit Registers := 9
- 49 Bit Registers := 2
- 48 Bit Registers := 81
- 46 Bit Registers := 18
- 45 Bit Registers := 2
- 43 Bit Registers := 1
- 41 Bit Registers := 11
- 40 Bit Registers := 9
- 36 Bit Registers := 3
- 34 Bit Registers := 25
- 33 Bit Registers := 30
- 32 Bit Registers := 219
- 31 Bit Registers := 90
- 30 Bit Registers := 28
- 29 Bit Registers := 6
- 28 Bit Registers := 20
- 27 Bit Registers := 1
- 26 Bit Registers := 67
- 24 Bit Registers := 41
- 22 Bit Registers := 136
- 21 Bit Registers := 9
- 20 Bit Registers := 2
- 18 Bit Registers := 9
- 17 Bit Registers := 3
- 16 Bit Registers := 18
- 15 Bit Registers := 53
- 14 Bit Registers := 50
- 13 Bit Registers := 9
- 12 Bit Registers := 23
- 10 Bit Registers := 30
- 9 Bit Registers := 13
- 8 Bit Registers := 113
- 7 Bit Registers := 12
- 6 Bit Registers := 83
- 5 Bit Registers := 106
- 4 Bit Registers := 218
- 3 Bit Registers := 157
- 2 Bit Registers := 215
- 1 Bit Registers := 1447
-+---Multipliers :
- 48x64 Multipliers := 2
- 53x53 Multipliers := 1
- 33x65 Multipliers := 1
- 66x66 Multipliers := 1
- 15x46 Multipliers := 4
- 27x32 Multipliers := 1
- 25x30 Multipliers := 9
-+---RAMs :
- 8192K Bit (131072 X 64 bit) RAMs := 1
- 1472K Bit (16384 X 92 bit) RAMs := 1
- 832K Bit (16384 X 52 bit) RAMs := 1
- 816K Bit (16384 X 51 bit) RAMs := 1
- 768K Bit (16384 X 48 bit) RAMs := 1
- 576K Bit (16384 X 36 bit) RAMs := 1
- 128K Bit (32768 X 4 bit) RAMs := 1
- 16K Bit (512 X 32 bit) RAMs := 2
- 1K Bit (64 X 21 bit) RAMs := 1
-+---ROMs :
- ROMs := 6
-+---Muxes :
- 2 Input 2080 Bit Muxes := 1
- 2 Input 130 Bit Muxes := 3
- 3 Input 128 Bit Muxes := 1
- 2 Input 128 Bit Muxes := 2
- 2 Input 112 Bit Muxes := 2
- 2 Input 109 Bit Muxes := 1
- 2 Input 108 Bit Muxes := 1
- 2 Input 92 Bit Muxes := 6
- 2 Input 65 Bit Muxes := 19
- 4 Input 65 Bit Muxes := 1
- 2 Input 64 Bit Muxes := 137
- 4 Input 64 Bit Muxes := 7
- 11 Input 64 Bit Muxes := 5
- 2 Input 62 Bit Muxes := 1
- 2 Input 61 Bit Muxes := 2
- 2 Input 58 Bit Muxes := 2
- 2 Input 56 Bit Muxes := 5
- 2 Input 55 Bit Muxes := 11
- 2 Input 54 Bit Muxes := 3
- 2 Input 53 Bit Muxes := 2
- 2 Input 52 Bit Muxes := 16
- 2 Input 51 Bit Muxes := 5
- 2 Input 50 Bit Muxes := 10
- 2 Input 48 Bit Muxes := 7
- 2 Input 46 Bit Muxes := 27
- 2 Input 45 Bit Muxes := 21
- 3 Input 45 Bit Muxes := 2
- 2 Input 44 Bit Muxes := 4
- 2 Input 41 Bit Muxes := 7
- 2 Input 36 Bit Muxes := 6
- 7 Input 36 Bit Muxes := 1
- 2 Input 34 Bit Muxes := 30
- 2 Input 33 Bit Muxes := 39
- 2 Input 32 Bit Muxes := 325
- 3 Input 32 Bit Muxes := 1
- 4 Input 32 Bit Muxes := 1
- 2 Input 30 Bit Muxes := 9
- 2 Input 29 Bit Muxes := 9
- 2 Input 28 Bit Muxes := 1
- 2 Input 27 Bit Muxes := 4
- 2 Input 26 Bit Muxes := 15
- 2 Input 25 Bit Muxes := 25
- 2 Input 24 Bit Muxes := 101
- 11 Input 24 Bit Muxes := 1
- 2 Input 23 Bit Muxes := 65
- 2 Input 22 Bit Muxes := 78
- 2 Input 20 Bit Muxes := 4
- 2 Input 17 Bit Muxes := 1
- 2 Input 16 Bit Muxes := 14
- 3 Input 16 Bit Muxes := 1
- 7 Input 16 Bit Muxes := 1
- 2 Input 15 Bit Muxes := 18
- 2 Input 14 Bit Muxes := 62
- 7 Input 14 Bit Muxes := 1
- 2 Input 13 Bit Muxes := 20
- 2 Input 12 Bit Muxes := 51
- 2 Input 11 Bit Muxes := 2
- 2 Input 10 Bit Muxes := 13
- 2 Input 9 Bit Muxes := 34
- 3 Input 9 Bit Muxes := 1
- 2 Input 8 Bit Muxes := 210
- 8 Input 8 Bit Muxes := 18
- 2 Input 7 Bit Muxes := 20
- 7 Input 7 Bit Muxes := 1
- 4 Input 6 Bit Muxes := 1
- 2 Input 6 Bit Muxes := 65
- 3 Input 6 Bit Muxes := 3
- 7 Input 6 Bit Muxes := 3
- 2 Input 5 Bit Muxes := 58
- 4 Input 5 Bit Muxes := 1
- 5 Input 5 Bit Muxes := 3
- 3 Input 5 Bit Muxes := 2
- 2 Input 4 Bit Muxes := 124
- 4 Input 4 Bit Muxes := 3
- 8 Input 4 Bit Muxes := 1
- 3 Input 4 Bit Muxes := 1
- 11 Input 4 Bit Muxes := 1
- 7 Input 4 Bit Muxes := 2
- 2 Input 3 Bit Muxes := 179
- 6 Input 3 Bit Muxes := 3
- 8 Input 3 Bit Muxes := 3
- 4 Input 3 Bit Muxes := 3
- 3 Input 3 Bit Muxes := 28
- 11 Input 3 Bit Muxes := 1
- 7 Input 3 Bit Muxes := 1
- 5 Input 3 Bit Muxes := 2
- 2 Input 2 Bit Muxes := 157
- 16 Input 2 Bit Muxes := 1
- 3 Input 2 Bit Muxes := 13
- 4 Input 2 Bit Muxes := 5
- 7 Input 2 Bit Muxes := 1
- 8 Input 2 Bit Muxes := 1
- 2 Input 1 Bit Muxes := 1396
- 3 Input 1 Bit Muxes := 42
- 5 Input 1 Bit Muxes := 27
- 11 Input 1 Bit Muxes := 33
- 4 Input 1 Bit Muxes := 21
- 6 Input 1 Bit Muxes := 1
- 7 Input 1 Bit Muxes := 9
----------------------------------------------------------------------------------
-Finished RTL Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 840 (col length:140)
-BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 10. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv:136]
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (dfma/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_vec_reg' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3886] merging instance 'mem_ctrl_vec_reg' (FDE) to 'mem_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_typeTagIn_reg[1]' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\ex_reg_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\in_pipe_b_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\mem_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[1]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[2]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[2]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[3]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[3]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[4]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (ifpu/\io_out_pipe_b_exc_reg[4] )
-INFO: [Synth 8-4471] merging register 's2_tlb_resp_pf_inst_reg' into 's2_tlb_resp_cacheable_reg' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Frontend.sv:127]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 16. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/MulDiv.sv:131]
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[60]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[60]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[61]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[61]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[62]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[62]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[57]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[57]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[58]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[58]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[59]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[59]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[54]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[54]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[55]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[55]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[56]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[56]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[51]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[51]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[52]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[52]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[53]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[53]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[48]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[48]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[49]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[49]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[50]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[50]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[45]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[45]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[46]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[46]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[47]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[47]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[42]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[42]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[43]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[43]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[44]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[44]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[39]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[39]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[40]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[40]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[41]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[41]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[36]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[36]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[37]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[37]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[38]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[38]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[33]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[33]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[34]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[34]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[35]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[35]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[30]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[30]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[31]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[31]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[32]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[32]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[27]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[27]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[28]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[28]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[29]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[29]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[24]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[24]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[25]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[25]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[26]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[26]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[21]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[21]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[22]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[22]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[23]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[23]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[18]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[18]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[19]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[19]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[20]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[20]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[15]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[15]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[16]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[16]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_reg_cause_reg[5] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_mstatus_mpp_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mcountinhibit_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mie_reg[0] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/\s1_pc_reg[0] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_mem_cmd_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_sel_alu2_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/s2_tlb_resp_cacheable_reg)
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[5] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[7] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[7] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[8] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[8] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[12] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[22] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[22] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[23] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[23] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[46] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[46] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[47] )
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_addr_reg' and it is trimmed from '34' to '32' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:408]
-WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[3] driven by constant 0
-WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[2] driven by constant 0
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-WARNING: [Synth 8-6841] Block RAM (rockettile_dcache_data_arrays_0_ext/Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 4. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:129]
-DSP Report: Generating DSP freq_word0, operation Mode is: (A:0x6677)*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: A*(B:0x6677).
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x109).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x55).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult20, operation Mode is: A*(B:0x75).
-DSP Report: operator mult20 is absorbed into DSP mult20.
-INFO: [Synth 8-5544] ROM "cordic_angle_lut_i/angle_o" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
-INFO: [Synth 8-4471] merging register 'prompt_abs_vld_reg' into 'cos2x_i/sqr_vld_reg' [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:107]
-DSP Report: Generating DSP cos2x_i/q_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: Generating DSP cos2x_i/i_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[15]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[14]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[13]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[12]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[11]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[10]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[9]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[8]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[7]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[6]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[5]__1) is unused and will be removed from module NCO_carr.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 8. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:342]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 4. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:331]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 12. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:409]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 12. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:408]
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (A:0x15940)*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: A*(B:0x15940).
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w0, operation Mode is: C+A*B.
-DSP Report: operator butterfly_i/x1_imag_w0 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w0, operation Mode is: C-A*B.
-DSP Report: operator butterfly_i/x1_real_w0 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP bd, operation Mode is: A*B.
-DSP Report: operator bd is absorbed into DSP bd.
-DSP Report: Generating DSP ac, operation Mode is: A*B.
-DSP Report: operator ac is absorbed into DSP ac.
-DSP Report: Generating DSP ad, operation Mode is: A*B.
-DSP Report: operator ad is absorbed into DSP ad.
-DSP Report: Generating DSP bc, operation Mode is: A*B.
-DSP Report: operator bc is absorbed into DSP bc.
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-WARNING: [Synth 8-3917] design APBGpsBlock__GCB1 has port _acq_sample_counter_clear driven by constant 0
-INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM acq/i_acq_top/dual_port_ram_i/ram_reg to conserve power
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_IQ_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_code_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /ifft_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-4652] Swapped enable and write-enable on 26 RAM instances of RAM bram_i/ram_reg to conserve power
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:37 ; elapsed = 00:01:55 . Memory (MB): peak = 3034.898 ; gain = 1213.547 ; free physical = 262 ; free virtual = 11149
----------------------------------------------------------------------------------
- Sort Area is APBGpsBlock__GCB1 p_1_out_0 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_2 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_3 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_4 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 0 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 1 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 2 : 2812 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 3 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 0 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 1 : 2793 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 2 : 2812 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 3 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 0 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 1 : 2812 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 2 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 3 : 2691 11089 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 0 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 1 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 2 : 3255 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 0 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 1 : 3101 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 2 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 0 : 3101 9322 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 1 : 3120 9322 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 2 : 3101 9322 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 0 : 1995 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 1 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 2 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 0 : 1995 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 1 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 2 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 0 : 1313 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 1 : 2710 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 2 : 2759 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 0 : 1313 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 1 : 2710 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 2 : 2712 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 0 : 1313 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 1 : 2710 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 2 : 2712 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 0 : 1313 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 1 : 2759 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 2 : 2479 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 0 : 1995 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 1 : 2712 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 2 : 1836 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 0 : 1995 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 1 : 2712 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 2 : 1836 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 0 : 1995 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 1 : 1836 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 2 : 1495 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 0 : 1995 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 1 : 1836 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 2 : 1495 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 im_sqr0_26 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 im_sqr0_26 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 re_sqr0_23 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 re_sqr0_23 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 0 : 3446 4760 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 1 : 1314 4760 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1e : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1e : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_20 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_20 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_18 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_18 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1c : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1c : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_17 : 0 0 : 1315 3694 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_17 : 0 1 : 2379 3694 : Used 1 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 0 : 1789 3431 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 1 : 1642 3431 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_0 : 0 0 : 1313 3313 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_0 : 0 1 : 2000 3313 : Used 1 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 0 : 1785 3295 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 1 : 1510 3295 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_3 : 0 0 : 1315 3237 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_3 : 0 1 : 1922 3237 : Used 1 time 0
- Sort Area is tracking_wrapper cos2x_i/i_p_sqr0_b : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is tracking_wrapper cos2x_i/q_p_sqr0_d : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB1 ac_12 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 ad_16 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 bc_15 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 bd_14 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w0_c : 0 0 : 2196 2196 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w0_f : 0 0 : 2073 2073 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_e : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_a : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1f : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_21 : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1a : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1d : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_17 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_5 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_9 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_11 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_22 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_7 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is tracking_wrapper mult10_6 : 0 0 : 433 433 : Used 9 time 0
- Sort Area is tracking_wrapper mult10_a : 0 0 : 403 403 : Used 9 time 0
- Sort Area is tracking_wrapper mult20_8 : 0 0 : 403 403 : Used 9 time 0
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-ROM: Preliminary Mapping Report
-+----------------+----------------------+---------------+----------------+
-|Module Name | RTL Object | Depth x Width | Implemented As |
-+----------------+----------------------+---------------+----------------+
-|TLROM | _GEN | 256x64 | LUT |
-|acq_nco_carr | freq_word_arr | 64x13 | LUT |
-|acq_nco_carr | pullin_freq_word_arr | 16x11 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_ca_gen | p_0_out | 32x8 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|cacode_gen_trck | p_0_out | 32x8 | LUT |
-+----------------+----------------------+---------------+----------------+
-
-
-Block RAM: Preliminary Mapping Report (see note below)
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GCB1 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
-
-Distributed RAM: Preliminary Mapping Report (see note below)
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
-Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
-
-DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | (PCIN>>17)+A*B | 25 | 8 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 16 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|NCO_carr | (A:0x6677)*B | 14 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 14 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | A*(B:0x6677) | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 18 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | A*(B:0x109) | 12 | 10 | - | - | 22 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x55) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x75) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 16 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (A:0x15940)*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 16 | 11 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*(B:0x15940) | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 11 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 14 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 14 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:27 ; elapsed = 00:02:05 . Memory (MB): peak = 3034.898 ; gain = 1213.547 ; free physical = 2624 ; free virtual = 13563
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:03:39 ; elapsed = 00:02:19 . Memory (MB): peak = 3034.898 ; gain = 1213.547 ; free physical = 2421 ; free virtual = 13363
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Block RAM: Final Mapping Report
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GCB1 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-
-Distributed RAM: Final Mapping Report
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:61]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:74]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:66]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:66]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv:100]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:256]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:256]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:256]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:254]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:254]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:263]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:263]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:263]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:263]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:262]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:262]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:262]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:262]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:248]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:248]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:248]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:248]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Common 17-14] Message 'Synth 8-5844' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:03:49 ; elapsed = 00:02:35 . Memory (MB): peak = 3051.918 ; gain = 1230.566 ; free physical = 969 ; free virtual = 11914
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:04:00 ; elapsed = 00:02:46 . Memory (MB): peak = 3200.254 ; gain = 1378.902 ; free physical = 774 ; free virtual = 11764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:04:00 ; elapsed = 00:02:47 . Memory (MB): peak = 3200.254 ; gain = 1378.902 ; free physical = 774 ; free virtual = 11764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:04:14 ; elapsed = 00:03:01 . Memory (MB): peak = 3384.434 ; gain = 1563.082 ; free physical = 582 ; free virtual = 11572
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:04:14 ; elapsed = 00:03:02 . Memory (MB): peak = 3384.434 ; gain = 1563.082 ; free physical = 584 ; free virtual = 11574
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:04:16 ; elapsed = 00:03:04 . Memory (MB): peak = 3399.277 ; gain = 1577.926 ; free physical = 589 ; free virtual = 11579
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:04:16 ; elapsed = 00:03:04 . Memory (MB): peak = 3399.277 ; gain = 1577.926 ; free physical = 589 ; free virtual = 11579
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Static Shift Register Report:
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|VCU118RocketSystem | tile_prci_domain/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-|VCU118RocketSystem | ibus/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-DSP Final Report (the ' indicates corresponding REG is set)
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-(A*B) | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 15 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 15 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 0 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 15 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 15 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN>>17+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B' | 24 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | PCIN>>17+A*B | 24 | 7 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-
-Report BlackBoxes:
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage:
-+------+-----------+------+
-| |Cell |Count |
-+------+-----------+------+
-|1 |BSCANE2 | 1|
-|2 |BUFG | 9|
-|3 |CARRY4 | 6055|
-|4 |DSP48E1 | 208|
-|10 |LUT1 | 2902|
-|11 |LUT2 | 15079|
-|12 |LUT3 | 10674|
-|13 |LUT4 | 8028|
-|14 |LUT5 | 12173|
-|15 |LUT6 | 24589|
-|16 |MMCME2_ADV | 3|
-|17 |MUXF7 | 1796|
-|18 |MUXF8 | 142|
-|19 |RAM32M | 225|
-|20 |RAM32X1D | 5|
-|21 |RAMB18E1 | 4|
-|23 |RAMB36E1 | 415|
-|45 |SRL16E | 2|
-|46 |STARTUPE2 | 1|
-|47 |FDCE | 30828|
-|48 |FDPE | 360|
-|49 |FDRE | 10101|
-|50 |FDSE | 130|
-|51 |LDC | 9|
-|52 |IBUF | 8|
-|53 |IBUFDS | 1|
-|54 |IOBUF | 8|
-|55 |OBUF | 13|
-+------+-----------+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:04:16 ; elapsed = 00:03:04 . Memory (MB): peak = 3399.277 ; gain = 1577.926 ; free physical = 588 ; free virtual = 11578
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 644 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:04:05 ; elapsed = 00:02:59 . Memory (MB): peak = 3403.191 ; gain = 1276.473 ; free physical = 7502 ; free virtual = 18493
-Synthesis Optimization Complete : Time (s): cpu = 00:04:16 ; elapsed = 00:03:07 . Memory (MB): peak = 3403.191 ; gain = 1581.840 ; free physical = 7509 ; free virtual = 18489
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.78 . Memory (MB): peak = 3403.191 ; gain = 0.000 ; free physical = 7521 ; free virtual = 18502
-INFO: [Netlist 29-17] Analyzing 8872 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3578.535 ; gain = 0.000 ; free physical = 7418 ; free virtual = 18398
-INFO: [Project 1-111] Unisim Transformation Summary:
- A total of 247 instances were transformed.
- IOBUF => IOBUF (IBUF, OBUFT): 8 instances
- LDC => LDCE: 9 instances
- RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 225 instances
- RAM32X1D => RAM32X1D (RAMD32(x2)): 5 instances
-
-Synth Design complete | Checksum: 419840f0
-INFO: [Common 17-83] Releasing license: Synthesis
-727 Infos, 400 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:04:38 ; elapsed = 00:03:30 . Memory (MB): peak = 3578.570 ; gain = 1933.234 ; free physical = 7420 ; free virtual = 18400
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 10074.977; main = 2844.857; forked = 8228.690
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19248.113; main = 3578.539; forked = 16217.129
-# apply_genesys2_async_clock_groups
-Applying Genesys2 async clock groups.
-# write_checkpoint -force [file join $checkpoint_dir post_synth.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.551 ; gain = 0.000 ; free physical = 7410 ; free virtual = 18390
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.551 ; gain = 0.000 ; free physical = 7410 ; free virtual = 18390
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3610.551 ; gain = 0.000 ; free physical = 7409 ; free virtual = 18390
-Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.551 ; gain = 0.000 ; free physical = 7409 ; free virtual = 18390
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.551 ; gain = 0.000 ; free physical = 7409 ; free virtual = 18390
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.551 ; gain = 0.000 ; free physical = 7409 ; free virtual = 18390
-Write Physdb Complete: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3610.551 ; gain = 0.000 ; free physical = 7409 ; free virtual = 18390
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3610.551 ; gain = 0.000 ; free physical = 7393 ; free virtual = 18387
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_synth.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 3610.551 ; gain = 31.980 ; free physical = 7381 ; free virtual = 18361
-# report_utilization -hierarchical -file [file join $report_dir synth_utilization_hier.rpt]
-# report_utilization -file [file join $report_dir synth_utilization.rpt]
-# report_timing_summary -file [file join $report_dir synth_timing_summary.rpt]
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs
-report_timing_summary: Time (s): cpu = 00:00:46 ; elapsed = 00:00:10 . Memory (MB): peak = 3610.551 ; gain = 0.000 ; free physical = 7388 ; free virtual = 18368
-# puts "Running implementation..."
-Running implementation...
-# opt_design
-Command: opt_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-Running DRC as a precondition to command opt_design
-
-Starting DRC Task
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Project 1-461] DRC finished with 0 Errors
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.56 . Memory (MB): peak = 3692.074 ; gain = 81.523 ; free physical = 7385 ; free virtual = 18366
-
-Starting Cache Timing Information Task
-Ending Cache Timing Information Task | Checksum: d78ae65d
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3692.074 ; gain = 0.000 ; free physical = 7385 ; free virtual = 18366
-
-Starting Logic Optimization Task
-
-Phase 1 Initialization
-
-Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: d78ae65d
-
-Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3695.043 ; gain = 0.000 ; free physical = 7323 ; free virtual = 18304
-
-Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: d78ae65d
-
-Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3695.043 ; gain = 0.000 ; free physical = 7323 ; free virtual = 18304
-Phase 1 Initialization | Checksum: d78ae65d
-
-Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3695.043 ; gain = 0.000 ; free physical = 7323 ; free virtual = 18304
-
-Phase 2 Timer Update And Timing Data Collection
-
-Phase 2.1 Detect if minReqCache needed
-Phase 2.1 Detect if minReqCache needed | Checksum: d78ae65d
-
-Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7300 ; free virtual = 18280
-
-Phase 2.2 Timer Update
-Phase 2.2 Timer Update | Checksum: d78ae65d
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7301 ; free virtual = 18281
-
-Phase 2.3 Timing Data Collection
-Phase 2.3 Timing Data Collection | Checksum: d78ae65d
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7301 ; free virtual = 18281
-Phase 2 Timer Update And Timing Data Collection | Checksum: d78ae65d
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7301 ; free virtual = 18281
-
-Phase 3 Retarget
-INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
-INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
-INFO: [Opt 31-1566] Pulled 28 inverters resulting in an inversion of 507 pins
-INFO: [Opt 31-138] Pushed 14 inverter(s) to 130 load pin(s).
-INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 1eb0d752e
-
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7302 ; free virtual = 18282
-Retarget | Checksum: 1eb0d752e
-INFO: [Opt 31-389] Phase Retarget created 683 cells and removed 724 cells
-INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 4 Constant propagation
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 16d251146
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7302 ; free virtual = 18282
-Constant propagation | Checksum: 16d251146
-INFO: [Opt 31-389] Phase Constant propagation created 1 cells and removed 1 cells
-
-Phase 5 Sweep
-INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
-Done building netlist checker database: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3711.043 ; gain = 0.000 ; free physical = 7302 ; free virtual = 18282
-Phase 5 Sweep | Checksum: 200d5cbf0
-
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7302 ; free virtual = 18282
-Sweep | Checksum: 200d5cbf0
-INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 9 cells
-INFO: [Opt 31-1021] In phase Sweep, 360 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 6 BUFG optimization
-Phase 6 BUFG optimization | Checksum: 200d5cbf0
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7302 ; free virtual = 18283
-BUFG optimization | Checksum: 200d5cbf0
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
-
-Phase 7 Shift Register Optimization
-INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 200d5cbf0
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7302 ; free virtual = 18283
-Shift Register Optimization | Checksum: 200d5cbf0
-INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
-
-Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 200d5cbf0
-
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7302 ; free virtual = 18283
-Post Processing Netlist | Checksum: 200d5cbf0
-INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
-
-Phase 9 Finalization
-
-Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1b9f6045a
-
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7302 ; free virtual = 18283
-
-Phase 9.2 Verifying Netlist Connectivity
-
-Starting Connectivity Check Task
-
-Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3711.043 ; gain = 0.000 ; free physical = 7302 ; free virtual = 18283
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 1b9f6045a
-
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7302 ; free virtual = 18283
-Phase 9 Finalization | Checksum: 1b9f6045a
-
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7302 ; free virtual = 18283
-Opt_design Change Summary
-=========================
-
-
--------------------------------------------------------------------------------------------------------------------------
-| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
--------------------------------------------------------------------------------------------------------------------------
-| Retarget | 683 | 724 | 1 |
-| Constant propagation | 1 | 1 | 0 |
-| Sweep | 0 | 9 | 360 |
-| BUFG optimization | 0 | 0 | 0 |
-| Shift Register Optimization | 0 | 0 | 0 |
-| Post Processing Netlist | 0 | 0 | 0 |
--------------------------------------------------------------------------------------------------------------------------
-
-
-Ending Logic Optimization Task | Checksum: 1b9f6045a
-
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3711.043 ; gain = 16.000 ; free physical = 7302 ; free virtual = 18283
-
-Starting Power Optimization Task
-INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-INFO: [Power 33-23] Power model is not available for u_cfg_flash_startup
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running Vector-less Activity Propagation...
-
-Finished Running Vector-less Activity Propagation
-INFO: [Pwropt 34-9] Applying IDT optimizations ...
-INFO: [Pwropt 34-10] Applying ODC optimizations ...
-
-
-Starting PowerOpt Patch Enables Task
-INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 419 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
-INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
-Number of BRAM Ports augmented: 0 newly gated: 84 Total Ports: 838
-Ending PowerOpt Patch Enables Task | Checksum: dcf6d7b2
-
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6793 ; free virtual = 17773
-Ending Power Optimization Task | Checksum: dcf6d7b2
-
-Time (s): cpu = 00:00:47 ; elapsed = 00:00:26 . Memory (MB): peak = 4337.910 ; gain = 626.867 ; free physical = 6793 ; free virtual = 17774
-
-Starting Final Cleanup Task
-
-Starting Logic Optimization Task
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Logic Optimization Task | Checksum: a91c588a
-
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:05 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6800 ; free virtual = 17780
-Ending Final Cleanup Task | Checksum: a91c588a
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:07 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6800 ; free virtual = 17780
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6800 ; free virtual = 17780
-INFO: [Common 17-83] Releasing license: Implementation
-29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-opt_design completed successfully
-opt_design: Time (s): cpu = 00:01:22 ; elapsed = 00:00:45 . Memory (MB): peak = 4337.910 ; gain = 727.359 ; free physical = 6800 ; free virtual = 17780
-# write_checkpoint -force [file join $checkpoint_dir post_opt.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6800 ; free virtual = 17780
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6800 ; free virtual = 17780
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6800 ; free virtual = 17781
-Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6800 ; free virtual = 17781
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6800 ; free virtual = 17781
-Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6799 ; free virtual = 17780
-Write Physdb Complete: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6799 ; free virtual = 17781
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.16 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6781 ; free virtual = 17773
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_opt.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6759 ; free virtual = 17740
-# place_design
-Command: place_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-83] Releasing license: Implementation
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running DRC as a precondition to command place_design
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 12 CPUs
-
-Starting Placer Task
-
-Phase 1 Placer Initialization
-
-Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6808 ; free virtual = 17789
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 748b7c80
-
-Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6809 ; free virtual = 17789
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6809 ; free virtual = 17789
-
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f588d2fb
-
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6813 ; free virtual = 17794
-
-Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 113cb2f0d
-
-Time (s): cpu = 00:01:05 ; elapsed = 00:00:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6808 ; free virtual = 17789
-
-Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 113cb2f0d
-
-Time (s): cpu = 00:01:05 ; elapsed = 00:00:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6808 ; free virtual = 17789
-Phase 1 Placer Initialization | Checksum: 113cb2f0d
-
-Time (s): cpu = 00:01:05 ; elapsed = 00:00:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6808 ; free virtual = 17788
-
-Phase 2 Global Placement
-
-Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 13eeb9087
-
-Time (s): cpu = 00:01:37 ; elapsed = 00:00:31 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6855 ; free virtual = 17835
-
-Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1c1323097
-
-Time (s): cpu = 00:02:14 ; elapsed = 00:00:39 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7208 ; free virtual = 18189
-
-Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 1c1323097
-
-Time (s): cpu = 00:02:15 ; elapsed = 00:00:40 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7208 ; free virtual = 18189
-
-Phase 2.4 Global Place Phase1
-Phase 2.4 Global Place Phase1 | Checksum: 9a1c9e78
-
-Time (s): cpu = 00:04:24 ; elapsed = 00:01:26 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7156 ; free virtual = 18136
-
-Phase 2.5 Global Place Phase2
-
-Phase 2.5.1 UpdateTiming Before Physical Synthesis
-Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 10a1ff244
-
-Time (s): cpu = 00:05:00 ; elapsed = 00:01:33 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7124 ; free virtual = 18105
-
-Phase 2.5.2 Physical Synthesis In Placer
-INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 3905 LUT instances to create LUTNM shape
-INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
-INFO: [Physopt 32-1138] End 1 Pass. Optimized 1045 nets or LUTs. Breaked 0 LUT, combined 1045 existing LUTs and moved 0 existing LUT
-INFO: [Physopt 32-65] No nets found for high-fanout optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
-INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
-INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
-INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7108 ; free virtual = 18089
-
-Summary of Physical Synthesis Optimizations
-============================================
-
-
------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
------------------------------------------------------------------------------------------------------------------------------------------------------------
-| LUT Combining | 0 | 1045 | 1045 | 0 | 1 | 00:00:02 |
-| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Total | 0 | 1045 | 1045 | 0 | 9 | 00:00:03 |
------------------------------------------------------------------------------------------------------------------------------------------------------------
-
-
-Phase 2.5.2 Physical Synthesis In Placer | Checksum: 1a7fe1a0b
-
-Time (s): cpu = 00:05:38 ; elapsed = 00:01:46 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7097 ; free virtual = 18078
-Phase 2.5 Global Place Phase2 | Checksum: 17ae00875
-
-Time (s): cpu = 00:05:44 ; elapsed = 00:01:49 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7100 ; free virtual = 18081
-Phase 2 Global Placement | Checksum: 17ae00875
-
-Time (s): cpu = 00:05:44 ; elapsed = 00:01:49 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7100 ; free virtual = 18081
-
-Phase 3 Detail Placement
-
-Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 194277fa5
-
-Time (s): cpu = 00:06:22 ; elapsed = 00:01:57 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7090 ; free virtual = 18071
-
-Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1a09fb91a
-
-Time (s): cpu = 00:07:28 ; elapsed = 00:02:16 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7087 ; free virtual = 18067
-
-Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 1cc3df838
-
-Time (s): cpu = 00:07:29 ; elapsed = 00:02:16 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7087 ; free virtual = 18067
-
-Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 1acac4056
-
-Time (s): cpu = 00:07:29 ; elapsed = 00:02:17 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7087 ; free virtual = 18067
-
-Phase 3.5 Fast Optimization
-Phase 3.5 Fast Optimization | Checksum: 171d676b1
-
-Time (s): cpu = 00:08:33 ; elapsed = 00:02:32 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7116 ; free virtual = 18096
-
-Phase 3.6 Small Shape Detail Placement
-Phase 3.6 Small Shape Detail Placement | Checksum: 143550b7e
-
-Time (s): cpu = 00:09:11 ; elapsed = 00:03:22 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7064 ; free virtual = 18045
-
-Phase 3.7 Re-assign LUT pins
-Phase 3.7 Re-assign LUT pins | Checksum: 18f7cc75e
-
-Time (s): cpu = 00:09:16 ; elapsed = 00:03:26 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7064 ; free virtual = 18045
-
-Phase 3.8 Pipeline Register Optimization
-Phase 3.8 Pipeline Register Optimization | Checksum: 1e3e51f1a
-
-Time (s): cpu = 00:09:17 ; elapsed = 00:03:27 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 7064 ; free virtual = 18045
-
-Phase 3.9 Fast Optimization
-Phase 3.9 Fast Optimization | Checksum: 25635f18d
-
-Time (s): cpu = 00:10:44 ; elapsed = 00:03:48 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6975 ; free virtual = 17956
-Phase 3 Detail Placement | Checksum: 25635f18d
-
-Time (s): cpu = 00:10:44 ; elapsed = 00:03:48 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6975 ; free virtual = 17956
-
-Phase 4 Post Placement Optimization and Clean-Up
-
-Phase 4.1 Post Commit Optimization
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-
-Phase 4.1.1 Post Placement Optimization
-Post Placement Optimization Initialization | Checksum: 1fea3c330
-
-Phase 4.1.1.1 BUFG Insertion
-
-Starting Physical Synthesis Task
-
-Phase 1 Physical Synthesis Initialization
-INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 12 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.999 | TNS=-521.029 |
-Phase 1 Physical Synthesis Initialization | Checksum: 134847dad
-
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.92 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6909 ; free virtual = 17889
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/apbReset_gps_apb_reset/io_sync_reset_chain/output_chain/sync_0_reg_1, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/pps/sync_0_reg, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_1, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-56] BUFG insertion identified 11 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 11, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
-Ending Physical Synthesis Task | Checksum: 1668226fb
-
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6908 ; free virtual = 17889
-Phase 4.1.1.1 BUFG Insertion | Checksum: 1fea3c330
-
-Time (s): cpu = 00:11:48 ; elapsed = 00:04:04 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6908 ; free virtual = 17889
-
-Phase 4.1.1.2 Post Placement Timing Optimization
-INFO: [Place 30-746] Post Placement Timing Summary WNS=-2.954. For the most accurate timing information please run report_timing.
-Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 16ab0e43e
-
-Time (s): cpu = 00:13:26 ; elapsed = 00:04:53 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-
-Time (s): cpu = 00:13:26 ; elapsed = 00:04:53 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-Phase 4.1 Post Commit Optimization | Checksum: 16ab0e43e
-
-Time (s): cpu = 00:13:27 ; elapsed = 00:04:53 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-
-Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 16ab0e43e
-
-Time (s): cpu = 00:13:28 ; elapsed = 00:04:54 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-
-Phase 4.3 Placer Reporting
-
-Phase 4.3.1 Print Estimated Congestion
-INFO: [Place 30-612] Post-Placement Estimated Congestion
- ____________________________________________________
-| | Global Congestion | Short Congestion |
-| Direction | Region Size | Region Size |
-|___________|___________________|___________________|
-| North| 1x1| 4x4|
-|___________|___________________|___________________|
-| South| 1x1| 4x4|
-|___________|___________________|___________________|
-| East| 1x1| 4x4|
-|___________|___________________|___________________|
-| West| 1x1| 2x2|
-|___________|___________________|___________________|
-
-Phase 4.3.1 Print Estimated Congestion | Checksum: 16ab0e43e
-
-Time (s): cpu = 00:13:28 ; elapsed = 00:04:54 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-Phase 4.3 Placer Reporting | Checksum: 16ab0e43e
-
-Time (s): cpu = 00:13:29 ; elapsed = 00:04:54 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-
-Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-
-Time (s): cpu = 00:13:29 ; elapsed = 00:04:54 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1bec5c626
-
-Time (s): cpu = 00:13:29 ; elapsed = 00:04:54 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-Ending Placer Task | Checksum: 124ccb841
-
-Time (s): cpu = 00:13:30 ; elapsed = 00:04:54 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-48 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-place_design completed successfully
-place_design: Time (s): cpu = 00:13:42 ; elapsed = 00:04:59 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-# write_checkpoint -force [file join $checkpoint_dir post_place.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17879
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17879
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6899 ; free virtual = 17880
-Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.2 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6860 ; free virtual = 17860
-Wrote PlaceStorage: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6755 ; free virtual = 17845
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.11 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6747 ; free virtual = 17847
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6747 ; free virtual = 17847
-Write Physdb Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6747 ; free virtual = 17847
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_place.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6858 ; free virtual = 17839
-# phys_opt_design -directive Explore
-Command: phys_opt_design -directive Explore
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
-
-Starting Initial Update Timing Task
-
-Time (s): cpu = 00:00:51 ; elapsed = 00:00:11 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6877 ; free virtual = 17858
-INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 55.53s | WALL: 11.57s
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6877 ; free virtual = 17858
-
-Starting Physical Synthesis Task
-
-Phase 1 Physical Synthesis Initialization
-INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 12 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.954 | TNS=-504.702 |
-Phase 1 Physical Synthesis Initialization | Checksum: 181f91480
-
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6863 ; free virtual = 17844
-
-Phase 2 SLR Crossing Optimization
-Phase 2 SLR Crossing Optimization | Checksum: 181f91480
-
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6863 ; free virtual = 17844
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.954 | TNS=-504.702 |
-
-Phase 3 Fanout Optimization
-INFO: [Physopt 32-64] No nets found for fanout-optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 3 Fanout Optimization | Checksum: 181f91480
-
-Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6864 ; free virtual = 17844
-
-Phase 4 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__3
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_9__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_9__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__4
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[9]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__4_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_8__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_8__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_19__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_19__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_16__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_16__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_20__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_20__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_27_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_27
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_14__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_14__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_13_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__3
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[13]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_9_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-661] Optimized 7 nets. Re-placed 7 instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 7 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 7 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-503.611 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6866 ; free virtual = 17846
-Phase 4 Single Cell Placement Optimization | Checksum: 1202bff0c
-
-Time (s): cpu = 00:01:15 ; elapsed = 00:00:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6866 ; free virtual = 17846
-
-Phase 5 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[9]/Q
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[13]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[13]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[8]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[11]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__1/O
-INFO: [Physopt 32-661] Optimized 1 net. Re-placed 2 instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 0 new cell, deleted 0 existing cell and moved 2 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-503.611 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6866 ; free virtual = 17847
-Phase 5 Multi Cell Placement Optimization | Checksum: 1bbbbad0f
-
-Time (s): cpu = 00:01:34 ; elapsed = 00:00:28 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6866 ; free virtual = 17847
-
-Phase 6 Rewire
-INFO: [Physopt 32-246] Starting Signal Push optimization...
-INFO: [Physopt 32-241] No nets found for rewiring () optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6866 ; free virtual = 17847
-Phase 6 Rewire | Checksum: 1bbbbad0f
-
-Time (s): cpu = 00:01:35 ; elapsed = 00:00:28 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6866 ; free virtual = 17847
-
-Phase 7 Critical Cell Optimization
-INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[1] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[4] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[3] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[0] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[9] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[6] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[8] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[10] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[13] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[11] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[7] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[2] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[0] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[12] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[1] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[2] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[2] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[2] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[4] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[3] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[3] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[1] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[6] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[4] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[5] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[7] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6863 ; free virtual = 17844
-Phase 7 Critical Cell Optimization | Checksum: 13b5501c6
-
-Time (s): cpu = 00:01:48 ; elapsed = 00:00:34 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6863 ; free virtual = 17844
-
-Phase 8 Fanout Optimization
-INFO: [Physopt 32-64] No nets found for fanout-optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 8 Fanout Optimization | Checksum: 13b5501c6
-
-Time (s): cpu = 00:01:49 ; elapsed = 00:00:35 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6863 ; free virtual = 17844
-
-Phase 9 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_9__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_9__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_19__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_19__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_8__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_8__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_16__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_16__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_20__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_20__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_14__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_14__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_27_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_27
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_13_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__3_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-661] Optimized 1 net. Re-placed 1 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 0 new cell, deleted 0 existing cell and moved 1 existing cell
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-503.611 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6861 ; free virtual = 17842
-Phase 9 Single Cell Placement Optimization | Checksum: 15cd90cc1
-
-Time (s): cpu = 00:02:46 ; elapsed = 00:00:48 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6861 ; free virtual = 17842
-
-Phase 10 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[9]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[8]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[13]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[11]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__1/O
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6860 ; free virtual = 17841
-Phase 10 Multi Cell Placement Optimization | Checksum: 183f81873
-
-Time (s): cpu = 00:03:03 ; elapsed = 00:00:53 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6860 ; free virtual = 17841
-
-Phase 11 Rewire
-INFO: [Physopt 32-246] Starting Signal Push optimization...
-INFO: [Physopt 32-241] No nets found for rewiring () optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6860 ; free virtual = 17841
-Phase 11 Rewire | Checksum: 183f81873
-
-Time (s): cpu = 00:03:03 ; elapsed = 00:00:53 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6860 ; free virtual = 17841
-
-Phase 12 Critical Cell Optimization
-INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[10] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[5] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg[2] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[6] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[6] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[5] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[12] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[5] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[0] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[3] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[3] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[0] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[4] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg[4] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/code_phase_reg[2] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg[5] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Net driver u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2] was replaced.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[11] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[4] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[0] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Replicated 1 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[9] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[1] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[1] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Net driver u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5] was replaced.
-INFO: [Physopt 32-232] Optimized 3 nets. Created 1 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 3 nets or cells. Created 1 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-503.596 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6857 ; free virtual = 17838
-Phase 12 Critical Cell Optimization | Checksum: 224a86daa
-
-Time (s): cpu = 00:03:17 ; elapsed = 00:01:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6857 ; free virtual = 17838
-
-Phase 13 SLR Crossing Optimization
-Phase 13 SLR Crossing Optimization | Checksum: 224a86daa
-
-Time (s): cpu = 00:03:17 ; elapsed = 00:01:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6857 ; free virtual = 17838
-
-Phase 14 Fanout Optimization
-INFO: [Physopt 32-64] No nets found for fanout-optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 14 Fanout Optimization | Checksum: 224a86daa
-
-Time (s): cpu = 00:03:17 ; elapsed = 00:01:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6857 ; free virtual = 17838
-
-Phase 15 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_9__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_9__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_19__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_19__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_8__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_8__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_16__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_16__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_20__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_20__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_14__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_14__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_27_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_27
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_13_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__6
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6858 ; free virtual = 17839
-Phase 15 Single Cell Placement Optimization | Checksum: 2799945ef
-
-Time (s): cpu = 00:04:11 ; elapsed = 00:01:13 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6858 ; free virtual = 17839
-
-Phase 16 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[9]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[8]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[13]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[11]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__1/O
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6857 ; free virtual = 17838
-Phase 16 Multi Cell Placement Optimization | Checksum: 230f6b7d0
-
-Time (s): cpu = 00:04:27 ; elapsed = 00:01:17 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6857 ; free virtual = 17838
-
-Phase 17 Rewire
-INFO: [Physopt 32-246] Starting Signal Push optimization...
-INFO: [Physopt 32-241] No nets found for rewiring () optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6857 ; free virtual = 17838
-Phase 17 Rewire | Checksum: 230f6b7d0
-
-Time (s): cpu = 00:04:27 ; elapsed = 00:01:17 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6857 ; free virtual = 17838
-
-Phase 18 Critical Cell Optimization
-INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[3] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[4] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg[6] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Net driver u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3] was replaced.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[13] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg[8]. Net driver u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg_reg[8] was replaced.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[3] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Net driver u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7] was replaced.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[5] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Net driver u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0] was replaced.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[1] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Net driver u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12] was replaced.
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[8]. Net driver u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[8] was replaced.
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Net driver u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10] was replaced.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[8] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Net driver u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4] was replaced.
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Net driver u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4] was replaced.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg[0] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/code_phase_reg[5] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Net driver u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3] was replaced.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[7] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-601] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[9]. Net driver u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg_reg[9] was replaced.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[8] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[4] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-232] Optimized 11 nets. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 11 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-503.596 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6856 ; free virtual = 17837
-Phase 18 Critical Cell Optimization | Checksum: 26b38feea
-
-Time (s): cpu = 00:04:40 ; elapsed = 00:01:22 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6856 ; free virtual = 17837
-
-Phase 19 DSP Register Optimization
-INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 19 DSP Register Optimization | Checksum: 26b38feea
-
-Time (s): cpu = 00:04:40 ; elapsed = 00:01:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6856 ; free virtual = 17837
-
-Phase 20 BRAM Register Optimization
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_10' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_11' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_12' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_13' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_14' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_15' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_16' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_17' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_18' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_19' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_20' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_21' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_22' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_23' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_8' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_9' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Common 17-14] Message 'Physopt 32-614' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 20 BRAM Register Optimization | Checksum: 26b38feea
-
-Time (s): cpu = 00:04:40 ; elapsed = 00:01:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6856 ; free virtual = 17837
-
-Phase 21 URAM Register Optimization
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 21 URAM Register Optimization | Checksum: 26b38feea
-
-Time (s): cpu = 00:04:40 ; elapsed = 00:01:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6856 ; free virtual = 17837
-
-Phase 22 Shift Register Optimization
-INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
-INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 22 Shift Register Optimization | Checksum: 26b38feea
-
-Time (s): cpu = 00:04:40 ; elapsed = 00:01:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6856 ; free virtual = 17837
-
-Phase 23 DSP Register Optimization
-INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 23 DSP Register Optimization | Checksum: 26b38feea
-
-Time (s): cpu = 00:04:40 ; elapsed = 00:01:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6856 ; free virtual = 17837
-
-Phase 24 BRAM Register Optimization
-INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 24 BRAM Register Optimization | Checksum: 26b38feea
-
-Time (s): cpu = 00:04:40 ; elapsed = 00:01:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6856 ; free virtual = 17837
-
-Phase 25 URAM Register Optimization
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 25 URAM Register Optimization | Checksum: 26b38feea
-
-Time (s): cpu = 00:04:40 ; elapsed = 00:01:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6856 ; free virtual = 17837
-
-Phase 26 Shift Register Optimization
-INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
-INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 26 Shift Register Optimization | Checksum: 26b38feea
-
-Time (s): cpu = 00:04:40 ; elapsed = 00:01:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6856 ; free virtual = 17837
-
-Phase 27 Critical Pin Optimization
-INFO: [Physopt 32-606] Identified 76 candidate nets for critical-pin optimization.
-INFO: [Physopt 32-608] Optimized 9 nets. Swapped 162 pins.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 9 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 162 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.987 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6855 ; free virtual = 17837
-Phase 27 Critical Pin Optimization | Checksum: 26b38feea
-
-Time (s): cpu = 00:04:41 ; elapsed = 00:01:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6855 ; free virtual = 17837
-
-Phase 28 Very High Fanout Optimization
-INFO: [Physopt 32-65] No nets found for high-fanout optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 28 Very High Fanout Optimization | Checksum: 26b38feea
-
-Time (s): cpu = 00:04:41 ; elapsed = 00:01:23 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6855 ; free virtual = 17837
-
-Phase 29 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_9__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_9__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_19__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_19__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_8__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_8__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_16__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_16__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_20__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_20__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_14__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_14__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_27_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_27
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_26__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6__5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_24__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_11__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter__0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[9]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_23
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_12__4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[4]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter__0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/code_phase_counter_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_10__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter__0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter__0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_21__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[8]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_reg_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/fifo_wr_en_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[0]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter__0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_counter_reg[1]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17__1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_17__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_22__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter__0[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__0
-INFO: [Physopt 32-661] Optimized 2 nets. Re-placed 2 instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 2 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.987 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6855 ; free virtual = 17837
-Phase 29 Single Cell Placement Optimization | Checksum: 21ada4001
-
-Time (s): cpu = 00:05:36 ; elapsed = 00:01:36 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6855 ; free virtual = 17837
-
-Phase 30 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[13]_i_2__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[4]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[6]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/fifo_wr_en_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[5]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[9]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[6]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[8]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[10]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[13]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[11]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[7]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/p_2_in[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter[7]_i_1__4/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg_reg[12]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[1]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[4]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[9]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/code_phase_reg_reg[3]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_reg_reg[2]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[0]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[5]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[8]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[8]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__3/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[1]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[10]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[3]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[12]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[11]_i_1__2/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/p_2_in[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/code_phase_counter[2]_i_1__2/O
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6854 ; free virtual = 17835
-Phase 30 Multi Cell Placement Optimization | Checksum: 217f91dee
-
-Time (s): cpu = 00:05:51 ; elapsed = 00:01:41 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6854 ; free virtual = 17835
-
-Phase 31 SLR Crossing Optimization
-Phase 31 SLR Crossing Optimization | Checksum: 217f91dee
-
-Time (s): cpu = 00:05:51 ; elapsed = 00:01:41 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6854 ; free virtual = 17835
-
-Phase 32 Critical Path Optimization
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.987 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net pll_gps_trck_clk. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_2__3_n_1. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_3__4_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_4__4_n_2. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_7__3_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_13__3_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_18__3_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_dst/i_spill_register/spill_register_flushable_i/gen_spill_reg.a_data_q[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[13].data_q_reg[13]_165[0]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[13].data_q_reg[13][0]
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[13].data_q_reg[13]_165[0]. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.907 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[13].data_q_reg[13]_165[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/rptr_q_reg[2]_6. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_spill_reg.a_data_q[0]_i_4__3_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-608] Optimized 1 net. Swapped 20 pins.
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_dst/i_spill_register/spill_register_flushable_i/async_data_i[0]. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.853 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_dst/i_spill_register/spill_register_flushable_i/gen_spill_reg.a_data_q[3]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[13].data_q_reg[13]_101[3]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[13].data_q_reg[13][3]
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[13].data_q_reg[13]_101[3]. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.852 |
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[11].data_q_reg[11]_103[3]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[11].data_q_reg[11][3]
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[11].data_q_reg[11]_103[3]. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.826 |
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[10].data_q_reg[10]_104[3]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[10].data_q_reg[10][3]
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[10].data_q_reg[10]_104[3]. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.800 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_dst/i_spill_register/spill_register_flushable_i/gen_spill_reg.a_data_q[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[5].data_q_reg[5]_221[0]. Re-placed instance u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[5].data_q_reg[5][0]
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[5].data_q_reg[5]_221[0]. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.740 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_dst/i_spill_register/spill_register_flushable_i/async_data_i[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net rf_clk_pmod_ibuf. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_end_r1. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_end. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net pll_gps_trck_clk. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_2__3_n_1. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_4__4_n_2. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_dst/i_spill_register/spill_register_flushable_i/gen_spill_reg.a_data_q[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[13].data_q_reg[13]_165[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/rptr_q_reg[2]_6. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_spill_reg.a_data_q[0]_i_4__3_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_dst/i_spill_register/spill_register_flushable_i/async_data_i[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net rf_clk_pmod_ibuf. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_end_r1. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_end. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.707 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6862 ; free virtual = 17843
-Phase 32 Critical Path Optimization | Checksum: 217f91dee
-
-Time (s): cpu = 00:06:07 ; elapsed = 00:01:45 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6862 ; free virtual = 17843
-
-Phase 33 Critical Path Optimization
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.707 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net pll_gps_trck_clk. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_2__3_n_1. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_3__4_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_4__4_n_2. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_7__3_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_13__3_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_18__3_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_dst/i_spill_register/spill_register_flushable_i/gen_spill_reg.a_data_q[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[13].data_q_reg[13]_165[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/rptr_q_reg[2]_6. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_spill_reg.a_data_q[0]_i_4__3_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_dst/i_spill_register/spill_register_flushable_i/async_data_i[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net rf_clk_pmod_ibuf. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_end_r1. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_end. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net pll_gps_trck_clk. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_2__3_n_1. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]_i_4__4_n_2. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state[1]_i_1__4_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_reg[2]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_dst/i_spill_register/spill_register_flushable_i/gen_spill_reg.a_data_q[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_word[13].data_q_reg[13]_165[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/rptr_q_reg[2]_6. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_spill_reg.a_data_q[0]_i_4__3_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_dst/i_spill_register/spill_register_flushable_i/async_data_i[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net rf_clk_pmod_ibuf. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_end_r1. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_end. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.953 | TNS=-502.707 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6867 ; free virtual = 17848
-Phase 33 Critical Path Optimization | Checksum: 217f91dee
-
-Time (s): cpu = 00:06:20 ; elapsed = 00:01:49 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6867 ; free virtual = 17848
-
-Phase 34 BRAM Enable Optimization
-Phase 34 BRAM Enable Optimization | Checksum: 217f91dee
-
-Time (s): cpu = 00:06:20 ; elapsed = 00:01:49 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6867 ; free virtual = 17848
-INFO: [Physopt 32-960] Skip hold-fix as initial WHS does not violate hold threshold 250 ps
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6867 ; free virtual = 17848
-INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-2.953 | TNS=-502.707 |
-
-Summary of Physical Synthesis Optimizations
-============================================
-
-
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Fanout | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:01 |
-| Single Cell Placement | 0.001 | 1.090 | 0 | 0 | 10 | 0 | 4 | 00:00:52 |
-| Multi Cell Placement | 0.000 | 0.000 | 0 | 0 | 1 | 0 | 4 | 00:00:18 |
-| Rewire | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:01 |
-| Critical Cell | 0.000 | 0.016 | 1 | 0 | 14 | 0 | 3 | 00:00:18 |
-| SLR Crossing | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:00 |
-| DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
-| BRAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
-| URAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
-| Shift Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
-| Critical Pin | 0.000 | 0.608 | 0 | 0 | 9 | 0 | 1 | 00:00:00 |
-| Very High Fanout | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| BRAM Enable | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Critical Path | 0.000 | 0.280 | 0 | 0 | 7 | 0 | 2 | 00:00:08 |
-| Total | 0.001 | 1.994 | 1 | 0 | 41 | 0 | 33 | 00:01:38 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
-
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6866 ; free virtual = 17848
-Ending Physical Synthesis Task | Checksum: 22a100a40
-
-Time (s): cpu = 00:06:21 ; elapsed = 00:01:49 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6866 ; free virtual = 17848
-INFO: [Common 17-83] Releasing license: Implementation
-1546 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-phys_opt_design completed successfully
-phys_opt_design: Time (s): cpu = 00:07:13 ; elapsed = 00:02:01 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6867 ; free virtual = 17848
-# write_checkpoint -force [file join $checkpoint_dir post_phys_opt.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6867 ; free virtual = 17848
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6867 ; free virtual = 17848
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6866 ; free virtual = 17848
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.12 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6840 ; free virtual = 17833
-Wrote PlaceStorage: Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6712 ; free virtual = 17798
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6704 ; free virtual = 17800
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6704 ; free virtual = 17801
-Write Physdb Complete: Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6704 ; free virtual = 17801
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_phys_opt.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6808 ; free virtual = 17789
-# route_design
-Command: route_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-
-
-Starting Routing Task
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 12 CPUs
-
-Phase 1 Build RT Design
-Checksum: PlaceDB: 82aa7fb4 ConstDB: 0 ShapeSum: cc446156 RouteDB: 287b7a50
-Post Restoration Checksum: NetGraph: af2740dd | NumContArr: 1fb8af1d | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 25431e534
-
-Time (s): cpu = 00:01:06 ; elapsed = 00:00:22 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6877 ; free virtual = 17857
-
-Phase 2 Router Initialization
-
-Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 25431e534
-
-Time (s): cpu = 00:01:07 ; elapsed = 00:00:22 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6877 ; free virtual = 17857
-
-Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 25431e534
-
-Time (s): cpu = 00:01:07 ; elapsed = 00:00:22 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6877 ; free virtual = 17857
- Number of Nodes with overlaps = 0
-
-Phase 2.3 Update Timing
-Phase 2.3 Update Timing | Checksum: 1df3bf628
-
-Time (s): cpu = 00:02:16 ; elapsed = 00:00:38 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6822 ; free virtual = 17802
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.881 | TNS=-487.028| WHS=-0.729 | THS=-2159.605|
-
-
-Phase 2.4 Soft Constraint Pins - Fast Budgeting
-Phase 2.4 Soft Constraint Pins - Fast Budgeting | Checksum: 1a47c9797
-
-Time (s): cpu = 00:02:34 ; elapsed = 00:00:42 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6824 ; free virtual = 17804
-
-Router Utilization Summary
- Global Vertical Routing Utilization = 0.00209974 %
- Global Horizontal Routing Utilization = 0.00176007 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 103177
- (Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 103159
- Number of Partially Routed Nets = 18
- Number of Node Overlaps = 4
-
-Phase 2 Router Initialization | Checksum: 26067f41e
-
-Time (s): cpu = 00:02:36 ; elapsed = 00:00:42 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6786 ; free virtual = 17766
-
-Phase 3 Global Routing
-Phase 3 Global Routing | Checksum: 26067f41e
-
-Time (s): cpu = 00:02:36 ; elapsed = 00:00:42 . Memory (MB): peak = 4337.910 ; gain = 0.000 ; free physical = 6786 ; free virtual = 17766
-
-Phase 4 Initial Routing
-
-Phase 4.1 Initial Net Routing Pass
-Phase 4.1 Initial Net Routing Pass | Checksum: 1c9f02ee3
-
-Time (s): cpu = 00:03:43 ; elapsed = 00:00:56 . Memory (MB): peak = 4475.398 ; gain = 137.488 ; free physical = 6562 ; free virtual = 17542
-Phase 4 Initial Routing | Checksum: 1c9f02ee3
-
-Time (s): cpu = 00:03:44 ; elapsed = 00:00:56 . Memory (MB): peak = 4475.398 ; gain = 137.488 ; free physical = 6562 ; free virtual = 17542
-INFO: [Route 35-580] Design has 277 pins with tight setup and hold constraints.
-
-The top 5 pins with tight setup and hold constraints:
-
-+====================+===================+=======================================================================================================+
-| Launch Setup Clock | Launch Hold Clock | Pin |
-+====================+===================+=======================================================================================================+
-| pll_gps_trck_clk | pmod_rf_clk | u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[13]/D |
-| pll_gps_trck_clk | pmod_rf_clk | u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[9]/D |
-| pll_gps_trck_clk | pmod_rf_clk | u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/FSM_sequential_current_state_reg[1]/D |
-| pll_gps_trck_clk | pmod_rf_clk | u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[11]/D |
-| pll_gps_trck_clk | pmod_rf_clk | u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/code_phase_counter_reg[0]/D |
-+--------------------+-------------------+-------------------------------------------------------------------------------------------------------+
-
-File with complete list of pins: tight_setup_hold_pins.txt
-
-
-Phase 5 Rip-up And Reroute
-
-Phase 5.1 Global Iteration 0
- Number of Nodes with overlaps = 10093
- Number of Nodes with overlaps = 184
- Number of Nodes with overlaps = 9
- Number of Nodes with overlaps = 1
- Number of Nodes with overlaps = 0
-INFO: [Common 17-41] Interrupt caught. Command should exit soon.
-Phase 5.1 Global Iteration 0 | Checksum: 251686085
-
-Time (s): cpu = 00:05:19 ; elapsed = 00:01:40 . Memory (MB): peak = 4475.398 ; gain = 137.488 ; free physical = 6576 ; free virtual = 17558
-Phase 5 Rip-up And Reroute | Checksum: 251686085
-
-Time (s): cpu = 00:05:19 ; elapsed = 00:01:40 . Memory (MB): peak = 4475.398 ; gain = 137.488 ; free physical = 6576 ; free virtual = 17558
-Total Elapsed time in route_design: 99.91 secs
-Ending Routing Task | Checksum: 16e9f6162
-
-Time (s): cpu = 00:05:20 ; elapsed = 00:01:40 . Memory (MB): peak = 4475.398 ; gain = 137.488 ; free physical = 6574 ; free virtual = 17557
-INFO: [Common 17-83] Releasing license: Implementation
-9 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors encountered.
-route_design failed
-INFO: [Common 17-344] 'route_design' was cancelled
-INFO: [Common 17-344] 'source' was cancelled
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 19:35:27 2026...
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream_303406.backup.jou b/targets/fpga/genesys2/out/logs/build_bitstream_303406.backup.jou
deleted file mode 100644
index c1950e7..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream_303406.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 19:45:58 2026
-# Process ID : 303406
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21506 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream_303406.backup.log b/targets/fpga/genesys2/out/logs/build_bitstream_303406.backup.log
deleted file mode 100644
index 8ddb1b1..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream_303406.backup.log
+++ /dev/null
@@ -1,3343 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 19:45:58 2026
-# Process ID : 303406
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21506 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../../..]]
-# set repo_dir [file normalize [file join $fpga_dir ../../..]]
-# set hardware_dir [file join $repo_dir hardware]
-# cd $repo_dir
-# set part_name "xc7k325tffg900-2"
-# set board_part "digilentinc.com:genesys2:part0:1.1"
-# set top_module "genesys2_rocket_top"
-# set out_dir [file join $fpga_dir out]
-# set generated_dir [file join $out_dir build generated]
-# set report_dir [file join $out_dir reports]
-# set bit_dir [file join $out_dir bitstream]
-# set checkpoint_dir [file join $out_dir build checkpoints]
-# file mkdir $generated_dir
-# file mkdir $report_dir
-# file mkdir $bit_dir
-# file mkdir $checkpoint_dir
-# set rocket_rtl_dir [file join $hardware_dir generated genesys2-soc-verilog]
-# set rocket_top [file join $rocket_rtl_dir VCU118RocketSystem.sv]
-# set rocket_filelist [file join $rocket_rtl_dir filelist.f]
-# set wrapper [file join $generated_dir ${top_module}.sv]
-# if {[info exists ::env(GPS_SYSTEM_DIR)] && [string trim $::env(GPS_SYSTEM_DIR)] ne ""} {
-# set gps_system_dir [file normalize $::env(GPS_SYSTEM_DIR)]
-# } else {
-# set gps_system_dir [file join $hardware_dir external gps rtl]
-# }
-# if {[info exists ::env(RF_INPUT_MODE)]} {
-# set rf_input_mode [string tolower [string trim $::env(RF_INPUT_MODE)]]
-# } else {
-# set rf_input_mode "pmod"
-# }
-# if {$rf_input_mode ni {"pmod" "generated" "ethernet"}} {
-# error "Unsupported Genesys2 RF_INPUT_MODE=$rf_input_mode. Use pmod, generated, or ethernet."
-# }
-# if {![file exists $rocket_filelist]} {
-# error "Rocket Verilog filelist not found: $rocket_filelist"
-# }
-# if {![file exists $rocket_top]} {
-# error "Rocket top Verilog not found: $rocket_top"
-# }
-# puts "Generating Genesys2 wrapper: $wrapper"
-Generating Genesys2 wrapper: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv
-# puts "Genesys2 RF input mode: $rf_input_mode"
-Genesys2 RF input mode: pmod
-# exec python3 [file join $fpga_dir tools gen_genesys2_wrapper.py] \
-# --rocket-top $rocket_top \
-# --out $wrapper \
-# --rf-input-mode $rf_input_mode
-# set max_threads [string trim [exec nproc]]
-# puts "Using Vivado maxThreads=$max_threads"
-Using Vivado maxThreads=12
-# set_param general.maxThreads $max_threads
-# set_part $part_name
-INFO: [Coretcl 2-1500] The part has been set to 'xc7k325tffg900-2' for the current project only. Run set_part -help for more details. To evaluate different speed grades in the current design, use the set_speed_grade command, or use the open_checkpoint -part command to change the part used by an existing checkpoint design.
-# if {[llength [get_board_parts -quiet $board_part]] != 0} {
-# set_property board_part $board_part [current_project]
-# }
-# proc apply_genesys2_async_clock_groups {} {
-# set fabric_clk [get_clocks -quiet pll_fabric_clk]
-# set gps_acq_clk [get_clocks -quiet pll_gps_acq_clk]
-# set gps_trck_clk [get_clocks -quiet pll_gps_trck_clk]
-# set gps_ref_clk [get_clocks -quiet pll_gps_ref_clk]
-# set gps_rf_clk [get_clocks -quiet {pll_gps_rf_exact_clk pmod_rf_clk}]
-# set eth_clk [get_clocks -quiet genesys2_eth_rxck]
-#
-# if {[llength $fabric_clk] == 0 ||
-# [llength $gps_acq_clk] == 0 ||
-# [llength $gps_trck_clk] == 0 ||
-# [llength $gps_ref_clk] == 0 ||
-# [llength $gps_rf_clk] == 0} {
-# puts "Warning: not all Genesys2 async clock groups are available yet."
-# return
-# }
-#
-# puts "Applying Genesys2 async clock groups."
-# set args [list -asynchronous \
-# -group $fabric_clk \
-# -group $gps_acq_clk \
-# -group $gps_trck_clk \
-# -group $gps_rf_clk]
-# if {[llength $eth_clk] != 0} {
-# lappend args -group $eth_clk
-# }
-# set_clock_groups {*}$args
-# }
-# set rocket_files {}
-# set fh [open $rocket_filelist r]
-# while {[gets $fh line] >= 0} {
-# set line [string trim $line]
-# if {$line eq ""} {
-# continue
-# }
-# set line [regsub {^\./} $line ""]
-# lappend rocket_files [file normalize [file join $rocket_rtl_dir $line]]
-# }
-# close $fh
-# puts "Reading Rocket Chip RTL..."
-Reading Rocket Chip RTL...
-# read_verilog -sv $rocket_files
-# read_verilog [file join $hardware_dir upstream rocket-chip src main resources vsrc plusarg_reader.v]
-# set gps_filelist [file join $hardware_dir external gps rtl filelist.f]
-# set gps_files {}
-# set gps_fh [open $gps_filelist r]
-# while {[gets $gps_fh rel] >= 0} {
-# set rel [string trim $rel]
-# if {$rel eq "" || [string match "#*" $rel]} {
-# continue
-# }
-# lappend gps_files [file join $gps_system_dir $rel]
-# }
-# close $gps_fh
-# puts "Reading GPS APB wrapper RTL from $gps_system_dir..."
-Reading GPS APB wrapper RTL from /home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl...
-# set_property include_dirs [list [file join $gps_system_dir trck_src pulp_fifo]] [current_fileset]
-# read_verilog -sv $gps_files
-# puts "Reading Genesys2 shell RTL..."
-Reading Genesys2 shell RTL...
-# set shell_files [list \
-# [file join $hardware_dir fpga vcu118 rtl axi4_ram_64.sv] \
-# [file join $hardware_dir fpga vcu118 rtl axi4_slave_tieoff_64.sv] \
-# [file join $hardware_dir fpga genesys2 rtl rocket_bscan_dmi_tunnel.sv] \
-# ]
-# if {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet RF RTL..."
-# lappend shell_files \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_async_fifo.sv] \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_core.sv] \
-# [file join $hardware_dir fpga genesys2 rtl ethernet_rf eth_rf_genesys2.sv]
-# } else {
-# puts "Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=$rf_input_mode."
-# }
-Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=pmod.
-# read_verilog -sv $shell_files
-# read_verilog -sv $wrapper
-# puts "Reading constraints..."
-Reading constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_rocket.xdc]
-# puts "Reading Genesys2 PMOD SPI constraints..."
-Reading Genesys2 PMOD SPI constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_spi.xdc]
-# puts "Reading Genesys2 PMOD sensor IRQ constraints..."
-Reading Genesys2 PMOD sensor IRQ constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_irq.xdc]
-# puts "Reading Genesys2 PMOD PPS constraints..."
-Reading Genesys2 PMOD PPS constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_pps.xdc]
-# if {$rf_input_mode eq "pmod"} {
-# puts "Reading Genesys2 PMOD RF constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_rf.xdc]
-# } elseif {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet PHY constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_ethernet.xdc]
-# }
-Reading Genesys2 PMOD RF constraints...
-# puts "Running synthesis for $part_name..."
-Running synthesis for xc7k325tffg900-2...
-# synth_design -top $top_module -part $part_name -verilog_define SYNTHESIS
-Command: synth_design -top genesys2_rocket_top -part xc7k325tffg900-2 -verilog_define SYNTHESIS
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Device 21-403] Loading part xc7k325tffg900-2
-INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
-INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 303430
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2305.137 ; gain = 482.844 ; free physical = 8286 ; free virtual = 19062
----------------------------------------------------------------------------------
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:8]
-WARNING: [Synth 8-11067] parameter 'CODE_LENGTH_IN_CHIPS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:9]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:10]
-WARNING: [Synth 8-11067] parameter 'SAMPLING_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:13]
-WARNING: [Synth 8-11067] parameter 'CENTER_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:14]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:15]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:16]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:17]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:18]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:19]
-WARNING: [Synth 8-11067] parameter 'ABS_SAMPLE_CNTR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:22]
-WARNING: [Synth 8-11067] parameter 'MS_PER_BIT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:23]
-WARNING: [Synth 8-11067] parameter 'C_ACQ_CHN_NUM' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:26]
-WARNING: [Synth 8-11067] parameter 'ACQ_IQ_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:27]
-WARNING: [Synth 8-11067] parameter 'ACQ_CORR_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:28]
-WARNING: [Synth 8-11067] parameter 'RF_DMEM_AL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:30]
-WARNING: [Synth 8-11067] parameter 'NUM_PRN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:31]
-WARNING: [Synth 8-11067] parameter 'PRN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:32]
-WARNING: [Synth 8-11067] parameter 'STRECH_COUNT_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:33]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_COEF1' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:40]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:41]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:42]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:43]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:44]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:45]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_FREQ_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:46]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:47]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:48]
-WARNING: [Synth 8-11067] parameter 'NUM_TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:50]
-WARNING: [Synth 8-11067] parameter 'TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:51]
-WARNING: [Synth 8-11067] parameter 'ATAN_ANGLE_BIT_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:56]
-WARNING: [Synth 8-11067] parameter 'ATAN_TABLE_SIZE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:57]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:60]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:61]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:62]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_SPACE_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:63]
-WARNING: [Synth 8-11067] parameter 'C1_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:65]
-WARNING: [Synth 8-11067] parameter 'C2_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:66]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:71]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:72]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:73]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:76]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:77]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:78]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:80]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:81]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:83]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:84]
-WARNING: [Synth 8-11067] parameter 'LOCK_WINDOW' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:85]
-WARNING: [Synth 8-11067] parameter 'LOCK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:86]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:89]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:90]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:92]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:93]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:95]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:96]
-WARNING: [Synth 8-11067] parameter 'CODE_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:99]
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:100]
-WARNING: [Synth 8-11067] parameter 'REAL_POS_FS_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:102]
-WARNING: [Synth 8-11067] parameter 'REAL_NEG_FS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:103]
-WARNING: [Synth 8-11067] parameter 'FS_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:105]
-WARNING: [Synth 8-11067] parameter 'DLL_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:106]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:108]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:109]
-WARNING: [Synth 8-11067] parameter 'REM_CODE_PH_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:110]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:113]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:114]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:115]
-WARNING: [Synth 8-11067] parameter 'F_ACQ_CLK' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:118]
-WARNING: [Synth 8-11067] parameter 'ACQ_CLK_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:119]
-WARNING: [Synth 8-11067] parameter 'RF_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:120]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE_CHIP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:121]
-WARNING: [Synth 8-11067] parameter 'ACQ_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:123]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:124]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:125]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:126]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:127]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:128]
-WARNING: [Synth 8-11067] parameter 'ACQ_CODE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:130]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:132]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:133]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:134]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:135]
-WARNING: [Synth 8-11067] parameter 'IFFT_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:136]
-WARNING: [Synth 8-11067] parameter 'IFFT_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:137]
-WARNING: [Synth 8-11067] parameter 'IFFT_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:139]
-WARNING: [Synth 8-11067] parameter 'NFFT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:141]
-WARNING: [Synth 8-11067] parameter 'NFFT_OVER_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:142]
-WARNING: [Synth 8-11067] parameter 'ZERO_PAD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:143]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:145]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:146]
-WARNING: [Synth 8-11067] parameter 'ABS_SQR_I_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:147]
-WARNING: [Synth 8-11067] parameter 'CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:148]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_DIV_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:149]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:150]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:151]
-WARNING: [Synth 8-11067] parameter 'PEAK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:152]
-WARNING: [Synth 8-11067] parameter 'DOPP_STEP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:154]
-WARNING: [Synth 8-11067] parameter 'NUM_FREQ_BIN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:155]
-WARNING: [Synth 8-11067] parameter 'FREQ_BIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:156]
-INFO: [Common 17-14] Message 'Synth 8-11067' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-10180] variable 'i' must explicitly be declared as automatic or static [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv:53]
-INFO: [Synth 8-6157] synthesizing module 'genesys2_rocket_top' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:3]
-INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
- Parameter DIFF_TERM bound to: FALSE - type: string
- Parameter IBUF_LOW_PWR bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 5.000000e+00 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 5.000000e+00 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.250000e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT1_DIVIDE bound to: 20 - type: integer
- Parameter CLKOUT1_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT1_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT2_DIVIDE bound to: 8 - type: integer
- Parameter CLKOUT2_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT2_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:75]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:75]
-WARNING: [Synth 8-7023] instance 'u_clock_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:75]
-INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6157] synthesizing module 'IBUF' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV__parameterized0' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 5.812500e+01 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 6.109500e+01 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.712500e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV__parameterized0' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_ref_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:152]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_ref_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:152]
-WARNING: [Synth 8-7023] instance 'u_gps_ref_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:152]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV__parameterized1' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 1.800000e+01 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 1.800000e+01 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.250000e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer
- Parameter CLKOUT1_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT1_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV__parameterized1' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_domain_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:212]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_gps_domain_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:212]
-WARNING: [Synth 8-7023] instance 'u_gps_domain_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:212]
-INFO: [Synth 8-6157] synthesizing module 'BSCANE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
- Parameter DISABLE_JTAG bound to: FALSE - type: string
- Parameter JTAG_CHAIN bound to: 4 - type: integer
-INFO: [Synth 8-6155] done synthesizing module 'BSCANE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
-INFO: [Synth 8-6157] synthesizing module 'rocket_bscan_dmi_tunnel' [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'rocket_bscan_dmi_tunnel' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:388]
-INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
- Parameter PROG_USR bound to: FALSE - type: string
- Parameter SIM_CCLK_FREQ bound to: 0.000000e+00 - type: double
-INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
-INFO: [Synth 8-6157] synthesizing module 'VCU118RocketSystem' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/VCU118RocketSystem.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockSinkDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i2_o1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i2_o1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockSinkDomain' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_aggregator' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_aggregator' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_sbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_sbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroup' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroup' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_5' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_5' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x120' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x120' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x77' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x77' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAUART' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAUART' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_gps' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAGPS' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAGPS' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_2' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_2' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_gps' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FrontBus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x123' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x123' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FrontBus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_2' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_2' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x124' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x124' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x78' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x78' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x99' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x99' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_debug' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_Debug' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_Debug' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_debug' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_4' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_4' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TilePRCIDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'HierarchicalElementResetDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/HierarchicalElementResetDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'RocketTile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/RocketTile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i3_o1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
-INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i3_o1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PMPChecker_s3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PMPChecker_s3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PMAChecker' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PMAChecker.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:194]
-INFO: [Synth 8-6155] done synthesizing module 'OptimizationBarrier_TLBEntryData' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/OptimizationBarrier_TLBEntryData.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:228]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:262]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:296]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:330]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:364]
-INFO: [Synth 8-6155] done synthesizing module 'DTLB' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:1121]
-INFO: [Synth 8-6155] done synthesizing module 'Arbiter8_DCacheMetadataReq' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Arbiter8_DCacheMetadataReq.sv:31]
-INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:139]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:173]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:207]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:241]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:275]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:309]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PTW.sv:188]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:3191]
- Parameter FORMAT bound to: max_core_cycles=%d - type: string
- Parameter WIDTH bound to: 32 - type: integer
- Parameter DEFAULT bound to: 32'b00000000000000000000000000000000
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:400]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:406]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:412]
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000000001
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter DATA_WIDTH bound to: 4 - type: integer
- Parameter ADDR_WIDTH bound to: 15 - type: integer
- Parameter PH_ACC_WL bound to: 32 - type: integer
- Parameter LUT_DEPTH_WL bound to: 5 - type: integer
- Parameter ACQ_SIN_IL bound to: 2 - type: integer
- Parameter ACQ_SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 25 - type: integer
- Parameter FS bound to: 16368000 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 52 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 36 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_IQ_WL bound to: 24 - type: integer
- Parameter FFT_IQ_TRUNC_WL bound to: 20 - type: integer
- Parameter FFT_CODE_WL bound to: 16 - type: integer
- Parameter FFT_CODE_TRUNC_WL bound to: 16 - type: integer
- Parameter OUT_WL bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 92 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter DWIDTH bound to: 48 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ABS_SQR_I_TRUNCATED_WL bound to: 25 - type: integer
- Parameter CORR_DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter SAMPLES_PER_CODE_CHIP bound to: 16 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv:158]
- Parameter DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ITER bound to: 9 - type: integer
- Parameter IN_W_L bound to: 36 - type: integer
- Parameter IN_F_L bound to: 0 - type: integer
- Parameter OUT_W_L bound to: 16 - type: integer
- Parameter OUT_F_L bound to: 8 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:285]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:296]
-WARNING: [Synth 8-151] case item 32'b00000000000000000000000000001100 is unreachable [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:350]
-WARNING: [Synth 8-7071] port 'clk_200mhz' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'mmcm_locked' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rd' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rxc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_td' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_tx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_txc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7023] instance 'afe' of module 'afe_top' has 17 connections declared, but only 9 given [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000100000
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter SIG_DEPTH bound to: 26 - type: integer
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:182]
- Parameter WIDTH bound to: 4 - type: integer
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter STAGES bound to: 32'b00000000000000000000000000000010
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter Bypass bound to: 1'b0
- Parameter PH_ACC_WL bound to: 24 - type: integer
- Parameter LUT_DEPTH_WL bound to: 7 - type: integer
- Parameter SIN_IL bound to: 2 - type: integer
- Parameter SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 46 - type: integer
- Parameter CODE_FREQ_I_IL bound to: 21 - type: integer
- Parameter CODE_FREQ_I_FL bound to: 20 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 10 - type: integer
- Parameter O_IL bound to: 16 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 13 - type: integer
- Parameter O_IL bound to: 8 - type: integer
- Parameter O_FL bound to: 20 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter TABLE_ADDR bound to: 4 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 33 - type: integer
-WARNING: [Synth 8-7071] port 'vec_len_o' of module 'cordic_atan_basic' is unconnected for instance 'Disc_PLL_i' [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:218]
-WARNING: [Synth 8-7023] instance 'Disc_PLL_i' of module 'cordic_atan_basic' has 8 connections declared, but only 7 given [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:218]
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER1 bound to: 8 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter TABLE_ADDR bound to: 3 - type: integer
-WARNING: [Synth 8-151] case item 4'b1000 is unreachable [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:114]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:105]
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 32 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 25 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter DIV_OUT_WL bound to: 15 - type: integer
- Parameter DIV_OUT_FL bound to: 13 - type: integer
- Parameter DIV_ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 45 - type: integer
- Parameter IN_FL bound to: 8 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:288]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:546]
- Parameter HIGH_ADDRESS bound to: 32'b00000000000000000000111111111111
- Parameter LOW_ADDRESS bound to: 32'b00000000000000000000000000000000
- Parameter DATA_BUS_WIDTH bound to: 32'b00000000000000000000000000100000
- Parameter ADDR_BUS_WIDTH bound to: 32'b00000000000000000000000000001100
- Parameter NUM_CAPTURE_CHANNELS bound to: 32'b00000000000000000000000000001001
- Parameter CLK_FREQ_HZ bound to: 32'b00000111011100110101100101000000
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:48]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:49]
-WARNING: [Synth 8-6014] Unused sequential element s2_vaddr_r_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:989]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:47]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:48]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:47]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:48]
-WARNING: [Synth 8-4767] Trying to implement RAM 'Memory_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/regfile_32x65.sv:60]
-Reason is one or more of the following :
- 1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
- 2: Invalid write to RAM.
- 3: Invalid write to RAM.
- 4: No valid clock found for write to RAM.
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2183]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2626]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2637]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2754]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2755]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2757]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2758]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2769]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2770]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2772]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2773]
-WARNING: [Synth 8-6014] Unused sequential element rocc_blocked_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2894]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2895]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2896]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2897]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2898]
-WARNING: [Synth 8-6014] Unused sequential element r_counter_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError_1.sv:69]
-Read & Write Range Direction Mismatch
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module comp_mult has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/comp_mult.sv:106]
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module ifft_abs_sqr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:90]
-WARNING: [Synth 8-3848] Net eth_rgmii_td in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:38]
-WARNING: [Synth 8-3848] Net eth_rgmii_tx_ctl in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:39]
-WARNING: [Synth 8-3848] Net eth_rgmii_txc in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:40]
-WARNING: [Synth 8-3848] Net rf_data_o in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:46]
-WARNING: [Synth 8-3848] Net fifo_of_o in module/entity trck_cntrl does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:50]
-WARNING: [Synth 8-6014] Unused sequential element g1_var_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:46]
-WARNING: [Synth 8-7137] Register chip_o_reg in module cacode_gen_trck has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:36]
-WARNING: [Synth 8-7129] Port PENABLE in module pps_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port fifo_of_o in module trck_cntrl is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port trck_resetn in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port afe_resetn in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_tx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_txc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port clk_200mhz in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port mmcm_locked in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rxc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port start_acq_manuel in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_en in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_clk in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[3] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_sink in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[127] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[126] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[125] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[124] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[123] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[122] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[121] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[120] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[119] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[118] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[117] in module SBToTL is either unconnected or has no load
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2705.426 ; gain = 883.133 ; free physical = 7834 ; free virtual = 18617
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2705.426 ; gain = 883.133 ; free physical = 7835 ; free virtual = 18618
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2705.426 ; gain = 883.133 ; free physical = 7835 ; free virtual = 18618
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2705.426 ; gain = 0.000 ; free physical = 7864 ; free virtual = 18647
-INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-INFO: [Timing 38-2] Deriving generated clocks
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2997.566 ; gain = 0.000 ; free physical = 7837 ; free virtual = 18615
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3009.488 ; gain = 0.000 ; free physical = 7817 ; free virtual = 18596
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 3009.488 ; gain = 1187.195 ; free physical = 6415 ; free virtual = 17194
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7k325tffg900-2
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 3017.492 ; gain = 1195.199 ; free physical = 6423 ; free virtual = 17202
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:24 . Memory (MB): peak = 3017.492 ; gain = 1195.199 ; free physical = 6415 ; free virtual = 17194
----------------------------------------------------------------------------------
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:405]
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:443]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '99' to '12' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:57]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore2_addr_reg' and it is trimmed from '34' to '20' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:383]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore1_addr_reg' and it is trimmed from '34' to '20' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:383]
-WARNING: [Synth 8-3936] Found unconnected internal register 'uncachedReqs_0_addr_reg' and it is trimmed from '34' to '3' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:958]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in1_reg' and it is trimmed from '65' to '33' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:58]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in3_reg' and it is trimmed from '65' to '33' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:60]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPToInt.sv:173]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_typeTagOut_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPToInt.sv:95]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_pipe_b_typeTagIn_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntToFP.sv:66]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:524]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:333]
-WARNING: [Synth 8-3936] Found unconnected internal register 'load_wb_typeTag_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:142]
-WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2787]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2787]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2822]
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized1'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_peak_srch'
-INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'divider_fsm'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_top'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'acq_wrapper'
-INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'trck_cntrl'
-INFO: [Synth 8-802] inferred FSM for state register 'nav_solve_state_p_reg' in module 'nav_solve_timer'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'tracking_wrapper'
-INFO: [Synth 8-802] inferred FSM for state register 'commit_state_p_reg' in module 'pps_core'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'pps_wrapper'
-WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '88' to '87' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a29d32s7k1z2u.sv:66]
-WARNING: [Synth 8-6841] Block RAM (Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-INFO: [Synth 8-3971] The signal "dual_port_bram:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized0:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized1:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized1'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 001 | 000
- S_CORR | 101 | 001
- S_INIT_ADDR | 100 | 010
- S_DATA_Q | 011 | 011
- S_SRCH | 010 | 100
- S_END | 000 | 101
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'sequential' in module 'acq_peak_srch'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- idle | 00 | 00
- normalization | 01 | 01
- cordic_core | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'divider_fsm'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 0000001 | 000
- S_WR_DATA | 0001000 | 001
- S_START | 0010000 | 010
- S_CTRL | 1000000 | 011
- S_FREQ | 0100000 | 100
- S_END | 0000010 | 101
- S_PULLIN | 0000100 | 110
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'one-hot' in module 'acq_top'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'acq_wrapper'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- WAIT_START | 00 | 00
- WAIT_SAMPLE_ALIGN | 01 | 01
- WAIT_CODE_PHASE | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'trck_cntrl'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- iSTATE0 | 0 | 00000000000000000000000000000000
-*
- iSTATE | 1 | 00000000000000000000000000000001
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'nav_solve_state_p_reg' using encoding 'sequential' in module 'nav_solve_timer'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'tracking_wrapper'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- PPS_COMMIT_IDLE | 0000 | 0000
- PPS_COMMIT_FRACTION | 0001 | 0001
- PPS_COMMIT_AGE_CAPTURE | 0010 | 0010
- PPS_COMMIT_AGE_MULTIPLY | 0011 | 0011
- PPS_COMMIT_MAP | 0100 | 0100
- PPS_COMMIT_NORMALIZE | 0101 | 0101
- PPS_COMMIT_PHASE | 0110 | 0110
- PPS_COMMIT_PI_MULTIPLY | 0111 | 0111
- PPS_COMMIT_INTEGRATE | 1000 | 1000
-PPS_COMMIT_CLAMP_INTEGRATOR | 1001 | 1001
- PPS_COMMIT_APPLY | 1010 | 1010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'commit_state_p_reg' using encoding 'sequential' in module 'pps_core'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- PPS_APB_STATE_IDLE | 001 | 00
- PPS_APB_STATE_ACCESS | 100 | 01
- PPS_APB_STATE_FINISH | 010 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'pps_wrapper'
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:32 . Memory (MB): peak = 3017.492 ; gain = 1195.199 ; free physical = 3402 ; free virtual = 14191
----------------------------------------------------------------------------------
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_5'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_5'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'u_rocket/tile_prci_domain/intsource_2'
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
----------------------------------------------------------------------------------
-Start RTL Component Statistics
----------------------------------------------------------------------------------
-Detailed RTL Component Info :
-+---Adders :
- 3 Input 128 Bit Adders := 1
- 2 Input 112 Bit Adders := 1
- 3 Input 112 Bit Adders := 1
- 2 Input 109 Bit Adders := 1
- 2 Input 107 Bit Adders := 1
- 3 Input 99 Bit Adders := 1
- 2 Input 99 Bit Adders := 1
- 2 Input 66 Bit Adders := 1
- 3 Input 65 Bit Adders := 2
- 2 Input 65 Bit Adders := 3
- 2 Input 64 Bit Adders := 15
- 3 Input 64 Bit Adders := 2
- 2 Input 62 Bit Adders := 1
- 3 Input 61 Bit Adders := 1
- 3 Input 58 Bit Adders := 1
- 2 Input 58 Bit Adders := 2
- 2 Input 55 Bit Adders := 4
- 2 Input 51 Bit Adders := 2
- 2 Input 49 Bit Adders := 1
- 2 Input 46 Bit Adders := 11
- 3 Input 46 Bit Adders := 2
- 2 Input 45 Bit Adders := 18
- 3 Input 45 Bit Adders := 10
- 2 Input 42 Bit Adders := 1
- 2 Input 41 Bit Adders := 9
- 3 Input 41 Bit Adders := 1
- 2 Input 34 Bit Adders := 3
- 3 Input 33 Bit Adders := 18
- 2 Input 32 Bit Adders := 75
- 3 Input 32 Bit Adders := 58
- 2 Input 30 Bit Adders := 18
- 3 Input 30 Bit Adders := 1
- 3 Input 29 Bit Adders := 1
- 2 Input 28 Bit Adders := 18
- 2 Input 26 Bit Adders := 25
- 3 Input 26 Bit Adders := 2
- 2 Input 25 Bit Adders := 11
- 3 Input 25 Bit Adders := 9
- 2 Input 24 Bit Adders := 1
- 2 Input 23 Bit Adders := 54
- 2 Input 22 Bit Adders := 18
- 2 Input 18 Bit Adders := 2
- 3 Input 18 Bit Adders := 2
- 3 Input 16 Bit Adders := 1
- 2 Input 16 Bit Adders := 1
- 2 Input 15 Bit Adders := 2
- 2 Input 14 Bit Adders := 20
- 4 Input 14 Bit Adders := 1
- 3 Input 14 Bit Adders := 1
- 3 Input 13 Bit Adders := 2
- 2 Input 13 Bit Adders := 7
- 2 Input 12 Bit Adders := 13
- 3 Input 12 Bit Adders := 10
- 4 Input 11 Bit Adders := 1
- 2 Input 11 Bit Adders := 4
- 3 Input 10 Bit Adders := 2
- 2 Input 10 Bit Adders := 1
- 2 Input 9 Bit Adders := 11
- 3 Input 9 Bit Adders := 5
- 2 Input 8 Bit Adders := 5
- 2 Input 7 Bit Adders := 4
- 2 Input 6 Bit Adders := 24
- 3 Input 6 Bit Adders := 2
- 2 Input 5 Bit Adders := 41
- 2 Input 4 Bit Adders := 86
- 3 Input 4 Bit Adders := 1
- 3 Input 3 Bit Adders := 9
- 2 Input 3 Bit Adders := 35
- 2 Input 2 Bit Adders := 6
- 3 Input 2 Bit Adders := 4
- 4 Input 2 Bit Adders := 1
- 5 Input 2 Bit Adders := 1
- 3 Input 1 Bit Adders := 3
- 2 Input 1 Bit Adders := 41
-+---XORs :
- 2 Input 65 Bit XORs := 1
- 2 Input 64 Bit XORs := 7
- 2 Input 33 Bit XORs := 1
- 2 Input 32 Bit XORs := 8
- 2 Input 29 Bit XORs := 16
- 2 Input 17 Bit XORs := 48
- 2 Input 16 Bit XORs := 2
- 2 Input 15 Bit XORs := 5
- 2 Input 14 Bit XORs := 1
- 2 Input 12 Bit XORs := 4
- 2 Input 10 Bit XORs := 4
- 2 Input 5 Bit XORs := 38
- 2 Input 4 Bit XORs := 2
- 2 Input 3 Bit XORs := 23
- 2 Input 2 Bit XORs := 7
- 2 Input 1 Bit XORs := 485
- 3 Input 1 Bit XORs := 68
- 6 Input 1 Bit XORs := 19
- 7 Input 1 Bit XORs := 18
- 13 Input 1 Bit XORs := 90
- 11 Input 1 Bit XORs := 63
- 12 Input 1 Bit XORs := 63
- 8 Input 1 Bit XORs := 54
- 10 Input 1 Bit XORs := 72
- 4 Input 1 Bit XORs := 54
- 14 Input 1 Bit XORs := 117
- 5 Input 1 Bit XORs := 18
- 15 Input 1 Bit XORs := 9
- 9 Input 1 Bit XORs := 54
- 16 Input 1 Bit XORs := 9
-+---XORs :
- 5 Bit Wide XORs := 36
- 4 Bit Wide XORs := 36
- 3 Bit Wide XORs := 36
- 2 Bit Wide XORs := 36
-+---Registers :
- 310 Bit Registers := 9
- 130 Bit Registers := 1
- 112 Bit Registers := 5
- 107 Bit Registers := 1
- 104 Bit Registers := 1
- 99 Bit Registers := 1
- 98 Bit Registers := 1
- 92 Bit Registers := 2
- 90 Bit Registers := 3
- 87 Bit Registers := 1
- 65 Bit Registers := 45
- 64 Bit Registers := 68
- 62 Bit Registers := 2
- 58 Bit Registers := 2
- 56 Bit Registers := 1
- 55 Bit Registers := 13
- 53 Bit Registers := 1
- 52 Bit Registers := 2
- 51 Bit Registers := 8
- 50 Bit Registers := 9
- 49 Bit Registers := 2
- 48 Bit Registers := 81
- 46 Bit Registers := 18
- 45 Bit Registers := 2
- 43 Bit Registers := 1
- 41 Bit Registers := 11
- 40 Bit Registers := 9
- 36 Bit Registers := 3
- 34 Bit Registers := 25
- 33 Bit Registers := 30
- 32 Bit Registers := 219
- 31 Bit Registers := 90
- 30 Bit Registers := 28
- 29 Bit Registers := 6
- 28 Bit Registers := 20
- 27 Bit Registers := 1
- 26 Bit Registers := 67
- 24 Bit Registers := 41
- 22 Bit Registers := 136
- 21 Bit Registers := 9
- 20 Bit Registers := 2
- 18 Bit Registers := 9
- 17 Bit Registers := 3
- 16 Bit Registers := 18
- 15 Bit Registers := 53
- 14 Bit Registers := 50
- 13 Bit Registers := 9
- 12 Bit Registers := 23
- 10 Bit Registers := 30
- 9 Bit Registers := 13
- 8 Bit Registers := 113
- 7 Bit Registers := 12
- 6 Bit Registers := 83
- 5 Bit Registers := 106
- 4 Bit Registers := 218
- 3 Bit Registers := 157
- 2 Bit Registers := 215
- 1 Bit Registers := 1447
-+---Multipliers :
- 48x64 Multipliers := 2
- 53x53 Multipliers := 1
- 33x65 Multipliers := 1
- 66x66 Multipliers := 1
- 15x46 Multipliers := 4
- 27x32 Multipliers := 1
- 25x30 Multipliers := 9
-+---RAMs :
- 8192K Bit (131072 X 64 bit) RAMs := 1
- 1472K Bit (16384 X 92 bit) RAMs := 1
- 832K Bit (16384 X 52 bit) RAMs := 1
- 816K Bit (16384 X 51 bit) RAMs := 1
- 768K Bit (16384 X 48 bit) RAMs := 1
- 576K Bit (16384 X 36 bit) RAMs := 1
- 128K Bit (32768 X 4 bit) RAMs := 1
- 16K Bit (512 X 32 bit) RAMs := 2
- 1K Bit (64 X 21 bit) RAMs := 1
-+---ROMs :
- ROMs := 6
-+---Muxes :
- 2 Input 2080 Bit Muxes := 1
- 2 Input 130 Bit Muxes := 3
- 3 Input 128 Bit Muxes := 1
- 2 Input 128 Bit Muxes := 2
- 2 Input 112 Bit Muxes := 2
- 2 Input 109 Bit Muxes := 1
- 2 Input 108 Bit Muxes := 1
- 2 Input 92 Bit Muxes := 6
- 2 Input 65 Bit Muxes := 19
- 4 Input 65 Bit Muxes := 1
- 2 Input 64 Bit Muxes := 137
- 4 Input 64 Bit Muxes := 7
- 11 Input 64 Bit Muxes := 5
- 2 Input 62 Bit Muxes := 1
- 2 Input 61 Bit Muxes := 2
- 2 Input 58 Bit Muxes := 2
- 2 Input 56 Bit Muxes := 5
- 2 Input 55 Bit Muxes := 11
- 2 Input 54 Bit Muxes := 3
- 2 Input 53 Bit Muxes := 2
- 2 Input 52 Bit Muxes := 16
- 2 Input 51 Bit Muxes := 5
- 2 Input 50 Bit Muxes := 10
- 2 Input 48 Bit Muxes := 7
- 2 Input 46 Bit Muxes := 27
- 2 Input 45 Bit Muxes := 21
- 3 Input 45 Bit Muxes := 2
- 2 Input 44 Bit Muxes := 4
- 2 Input 41 Bit Muxes := 7
- 2 Input 36 Bit Muxes := 6
- 7 Input 36 Bit Muxes := 1
- 2 Input 34 Bit Muxes := 30
- 2 Input 33 Bit Muxes := 39
- 2 Input 32 Bit Muxes := 325
- 3 Input 32 Bit Muxes := 1
- 4 Input 32 Bit Muxes := 1
- 2 Input 30 Bit Muxes := 9
- 2 Input 29 Bit Muxes := 9
- 2 Input 28 Bit Muxes := 1
- 2 Input 27 Bit Muxes := 4
- 2 Input 26 Bit Muxes := 15
- 2 Input 25 Bit Muxes := 25
- 2 Input 24 Bit Muxes := 101
- 11 Input 24 Bit Muxes := 1
- 2 Input 23 Bit Muxes := 65
- 2 Input 22 Bit Muxes := 78
- 2 Input 20 Bit Muxes := 4
- 2 Input 17 Bit Muxes := 1
- 2 Input 16 Bit Muxes := 14
- 3 Input 16 Bit Muxes := 1
- 7 Input 16 Bit Muxes := 1
- 2 Input 15 Bit Muxes := 18
- 2 Input 14 Bit Muxes := 62
- 7 Input 14 Bit Muxes := 1
- 2 Input 13 Bit Muxes := 20
- 2 Input 12 Bit Muxes := 51
- 2 Input 11 Bit Muxes := 2
- 2 Input 10 Bit Muxes := 13
- 2 Input 9 Bit Muxes := 34
- 3 Input 9 Bit Muxes := 1
- 2 Input 8 Bit Muxes := 210
- 8 Input 8 Bit Muxes := 18
- 2 Input 7 Bit Muxes := 20
- 7 Input 7 Bit Muxes := 1
- 4 Input 6 Bit Muxes := 1
- 2 Input 6 Bit Muxes := 65
- 3 Input 6 Bit Muxes := 3
- 7 Input 6 Bit Muxes := 3
- 2 Input 5 Bit Muxes := 58
- 4 Input 5 Bit Muxes := 1
- 5 Input 5 Bit Muxes := 3
- 3 Input 5 Bit Muxes := 2
- 2 Input 4 Bit Muxes := 124
- 4 Input 4 Bit Muxes := 3
- 8 Input 4 Bit Muxes := 1
- 3 Input 4 Bit Muxes := 1
- 11 Input 4 Bit Muxes := 1
- 7 Input 4 Bit Muxes := 2
- 2 Input 3 Bit Muxes := 179
- 6 Input 3 Bit Muxes := 3
- 8 Input 3 Bit Muxes := 3
- 4 Input 3 Bit Muxes := 3
- 3 Input 3 Bit Muxes := 28
- 11 Input 3 Bit Muxes := 1
- 7 Input 3 Bit Muxes := 1
- 5 Input 3 Bit Muxes := 2
- 2 Input 2 Bit Muxes := 157
- 16 Input 2 Bit Muxes := 1
- 3 Input 2 Bit Muxes := 13
- 4 Input 2 Bit Muxes := 5
- 7 Input 2 Bit Muxes := 1
- 8 Input 2 Bit Muxes := 1
- 2 Input 1 Bit Muxes := 1396
- 3 Input 1 Bit Muxes := 42
- 5 Input 1 Bit Muxes := 27
- 11 Input 1 Bit Muxes := 33
- 4 Input 1 Bit Muxes := 21
- 6 Input 1 Bit Muxes := 1
- 7 Input 1 Bit Muxes := 9
----------------------------------------------------------------------------------
-Finished RTL Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 840 (col length:140)
-BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 10. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv:136]
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (dfma/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_vec_reg' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3886] merging instance 'mem_ctrl_vec_reg' (FDE) to 'mem_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_typeTagIn_reg[1]' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\ex_reg_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\in_pipe_b_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\mem_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[1]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[2]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[2]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[3]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[3]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[4]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (ifpu/\io_out_pipe_b_exc_reg[4] )
-INFO: [Synth 8-4471] merging register 's2_tlb_resp_pf_inst_reg' into 's2_tlb_resp_cacheable_reg' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Frontend.sv:127]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 16. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/MulDiv.sv:131]
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[60]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[60]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[61]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[61]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[62]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[62]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[57]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[57]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[58]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[58]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[59]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[59]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[54]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[54]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[55]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[55]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[56]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[56]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[51]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[51]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[52]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[52]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[53]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[53]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[48]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[48]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[49]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[49]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[50]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[50]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[45]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[45]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[46]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[46]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[47]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[47]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[42]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[42]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[43]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[43]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[44]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[44]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[39]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[39]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[40]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[40]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[41]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[41]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[36]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[36]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[37]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[37]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[38]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[38]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[33]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[33]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[34]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[34]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[35]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[35]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[30]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[30]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[31]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[31]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[32]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[32]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[27]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[27]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[28]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[28]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[29]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[29]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[24]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[24]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[25]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[25]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[26]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[26]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[21]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[21]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[22]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[22]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[23]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[23]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[18]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[18]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[19]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[19]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[20]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[20]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[15]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[15]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[16]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[16]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_reg_cause_reg[5] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_mstatus_mpp_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mcountinhibit_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mie_reg[0] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/\s1_pc_reg[0] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_mem_cmd_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_sel_alu2_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/s2_tlb_resp_cacheable_reg)
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[5] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[7] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[7] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[8] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[8] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[12] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[22] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[22] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[23] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[23] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[46] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[46] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[47] )
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_addr_reg' and it is trimmed from '34' to '32' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:408]
-WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[3] driven by constant 0
-WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[2] driven by constant 0
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-WARNING: [Synth 8-6841] Block RAM (rockettile_dcache_data_arrays_0_ext/Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 4. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:129]
-DSP Report: Generating DSP freq_word0, operation Mode is: (A:0x6677)*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: A*(B:0x6677).
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x109).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x55).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult20, operation Mode is: A*(B:0x75).
-DSP Report: operator mult20 is absorbed into DSP mult20.
-INFO: [Synth 8-5544] ROM "cordic_angle_lut_i/angle_o" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
-INFO: [Synth 8-4471] merging register 'prompt_abs_vld_reg' into 'cos2x_i/sqr_vld_reg' [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:107]
-DSP Report: Generating DSP cos2x_i/q_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: Generating DSP cos2x_i/i_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[15]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[14]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[13]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[12]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[11]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[10]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[9]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[8]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[7]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[6]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[5]__1) is unused and will be removed from module NCO_carr.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 8. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:342]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 4. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:331]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 12. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:409]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 12. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:408]
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP reference_age_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: operator reference_age_work0 is absorbed into DSP reference_age_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (A:0x15940)*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: A*(B:0x15940).
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP fraction_ticks_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: operator fraction_ticks_work0 is absorbed into DSP fraction_ticks_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP ki_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: operator ki_product_work0 is absorbed into DSP ki_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: Generating DSP kp_product_work0, operation Mode is: PCIN+A*B.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-DSP Report: operator kp_product_work0 is absorbed into DSP kp_product_work0.
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w0, operation Mode is: C+A*B.
-DSP Report: operator butterfly_i/x1_imag_w0 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w0, operation Mode is: C-A*B.
-DSP Report: operator butterfly_i/x1_real_w0 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP bd, operation Mode is: A*B.
-DSP Report: operator bd is absorbed into DSP bd.
-DSP Report: Generating DSP ac, operation Mode is: A*B.
-DSP Report: operator ac is absorbed into DSP ac.
-DSP Report: Generating DSP ad, operation Mode is: A*B.
-DSP Report: operator ad is absorbed into DSP ad.
-DSP Report: Generating DSP bc, operation Mode is: A*B.
-DSP Report: operator bc is absorbed into DSP bc.
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-WARNING: [Synth 8-3917] design APBGpsBlock__GCB1 has port _acq_sample_counter_clear driven by constant 0
-INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM acq/i_acq_top/dual_port_ram_i/ram_reg to conserve power
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_IQ_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_code_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /ifft_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-4652] Swapped enable and write-enable on 26 RAM instances of RAM bram_i/ram_reg to conserve power
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:21 ; elapsed = 00:01:29 . Memory (MB): peak = 3033.504 ; gain = 1211.211 ; free physical = 182 ; free virtual = 11042
----------------------------------------------------------------------------------
- Sort Area is APBGpsBlock__GCB1 p_1_out_0 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_2 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_3 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_4 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 0 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 1 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 2 : 2812 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 3 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 0 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 1 : 2793 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 2 : 2812 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 3 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 0 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 1 : 2812 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 2 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 3 : 2691 11089 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 0 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 1 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 2 : 3255 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 0 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 1 : 3101 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 2 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 0 : 3101 9322 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 1 : 3120 9322 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 2 : 3101 9322 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 0 : 1995 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 1 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_9 : 0 2 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 0 : 1995 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 1 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_10 : 0 2 : 2712 7419 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 0 : 1313 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 1 : 2710 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_13 : 0 2 : 2759 6782 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 0 : 1313 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 1 : 2710 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_6 : 0 2 : 2712 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 0 : 1313 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 1 : 2710 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_f : 0 2 : 2712 6735 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 0 : 1313 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 1 : 2759 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_15 : 0 2 : 2479 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 0 : 1995 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 1 : 2712 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_b : 0 2 : 1836 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 0 : 1995 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 1 : 2712 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_11 : 0 2 : 1836 6543 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 0 : 1995 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 1 : 1836 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 ki_product_work0_d : 0 2 : 1495 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 0 : 1995 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 1 : 1836 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 kp_product_work0_12 : 0 2 : 1495 5326 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 im_sqr0_26 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 im_sqr0_26 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 re_sqr0_23 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 re_sqr0_23 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 0 : 3446 4760 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 1 : 1314 4760 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1e : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1e : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_20 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_20 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_18 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_18 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1c : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1c : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_17 : 0 0 : 1315 3694 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_age_work0_17 : 0 1 : 2379 3694 : Used 1 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 0 : 1789 3431 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 1 : 1642 3431 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_0 : 0 0 : 1313 3313 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_0 : 0 1 : 2000 3313 : Used 1 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 0 : 1785 3295 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 1 : 1510 3295 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_3 : 0 0 : 1315 3237 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 fraction_ticks_work0_3 : 0 1 : 1922 3237 : Used 1 time 0
- Sort Area is tracking_wrapper cos2x_i/i_p_sqr0_b : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is tracking_wrapper cos2x_i/q_p_sqr0_d : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB1 ac_12 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 ad_16 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 bc_15 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 bd_14 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w0_c : 0 0 : 2196 2196 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w0_f : 0 0 : 2073 2073 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_e : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_a : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1f : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_21 : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1a : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1d : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_17 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_5 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_9 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_11 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_22 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_7 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is tracking_wrapper mult10_6 : 0 0 : 433 433 : Used 9 time 0
- Sort Area is tracking_wrapper mult10_a : 0 0 : 403 403 : Used 9 time 0
- Sort Area is tracking_wrapper mult20_8 : 0 0 : 403 403 : Used 9 time 0
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-ROM: Preliminary Mapping Report
-+----------------+----------------------+---------------+----------------+
-|Module Name | RTL Object | Depth x Width | Implemented As |
-+----------------+----------------------+---------------+----------------+
-|TLROM | _GEN | 256x64 | LUT |
-|acq_nco_carr | freq_word_arr | 64x13 | LUT |
-|acq_nco_carr | pullin_freq_word_arr | 16x11 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_ca_gen | p_0_out | 32x8 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|cacode_gen_trck | p_0_out | 32x8 | LUT |
-+----------------+----------------------+---------------+----------------+
-
-
-Block RAM: Preliminary Mapping Report (see note below)
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GCB1 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
-
-Distributed RAM: Preliminary Mapping Report (see note below)
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
-Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
-
-DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | (PCIN>>17)+A*B | 25 | 8 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 16 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|NCO_carr | (A:0x6677)*B | 14 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 14 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | A*(B:0x6677) | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 18 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | A*(B:0x109) | 12 | 10 | - | - | 22 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x55) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x75) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 16 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (A:0x15940)*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 16 | 11 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*(B:0x15940) | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 11 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 14 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 14 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:36 ; elapsed = 00:01:37 . Memory (MB): peak = 3033.504 ; gain = 1211.211 ; free physical = 2424 ; free virtual = 13337
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:03:46 ; elapsed = 00:01:48 . Memory (MB): peak = 3037.590 ; gain = 1215.297 ; free physical = 2383 ; free virtual = 13298
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Block RAM: Final Mapping Report
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GCB1 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-
-Distributed RAM: Final Mapping Report
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:61]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:74]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:66]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:66]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv:100]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:256]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:256]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:256]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:254]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:254]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:263]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:263]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:263]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:263]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:262]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:262]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:262]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:262]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:253]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:255]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:248]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:248]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:248]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:248]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:251]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:250]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:260]
-INFO: [Common 17-14] Message 'Synth 8-5844' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:03:53 ; elapsed = 00:02:00 . Memory (MB): peak = 3057.523 ; gain = 1235.230 ; free physical = 916 ; free virtual = 11834
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:04:02 ; elapsed = 00:02:10 . Memory (MB): peak = 3199.891 ; gain = 1377.598 ; free physical = 721 ; free virtual = 11684
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:04:02 ; elapsed = 00:02:10 . Memory (MB): peak = 3199.891 ; gain = 1377.598 ; free physical = 721 ; free virtual = 11684
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:04:14 ; elapsed = 00:02:22 . Memory (MB): peak = 3384.641 ; gain = 1562.348 ; free physical = 517 ; free virtual = 11480
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:04:14 ; elapsed = 00:02:22 . Memory (MB): peak = 3384.641 ; gain = 1562.348 ; free physical = 517 ; free virtual = 11480
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:04:15 ; elapsed = 00:02:24 . Memory (MB): peak = 3395.547 ; gain = 1573.254 ; free physical = 519 ; free virtual = 11482
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:04:15 ; elapsed = 00:02:24 . Memory (MB): peak = 3395.547 ; gain = 1573.254 ; free physical = 519 ; free virtual = 11482
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Static Shift Register Report:
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|VCU118RocketSystem | tile_prci_domain/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-|VCU118RocketSystem | ibus/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-DSP Final Report (the ' indicates corresponding REG is set)
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-(A*B) | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 15 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 15 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 0 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN+A*B)' | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 15 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 15 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN>>17+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B' | 24 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | PCIN>>17+A*B | 24 | 7 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-
-Report BlackBoxes:
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage:
-+------+-----------+------+
-| |Cell |Count |
-+------+-----------+------+
-|1 |BSCANE2 | 1|
-|2 |BUFG | 9|
-|3 |CARRY4 | 6055|
-|4 |DSP48E1 | 208|
-|10 |LUT1 | 2902|
-|11 |LUT2 | 15080|
-|12 |LUT3 | 10675|
-|13 |LUT4 | 8029|
-|14 |LUT5 | 12169|
-|15 |LUT6 | 24589|
-|16 |MMCME2_ADV | 3|
-|17 |MUXF7 | 1796|
-|18 |MUXF8 | 142|
-|19 |RAM32M | 225|
-|20 |RAM32X1D | 5|
-|21 |RAMB18E1 | 4|
-|23 |RAMB36E1 | 415|
-|45 |SRL16E | 2|
-|46 |STARTUPE2 | 1|
-|47 |FDCE | 30828|
-|48 |FDPE | 360|
-|49 |FDRE | 10101|
-|50 |FDSE | 130|
-|51 |LDC | 9|
-|52 |IBUF | 8|
-|53 |IBUFDS | 1|
-|54 |IOBUF | 8|
-|55 |OBUF | 13|
-+------+-----------+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:04:16 ; elapsed = 00:02:24 . Memory (MB): peak = 3395.547 ; gain = 1573.254 ; free physical = 519 ; free virtual = 11482
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 644 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:04:04 ; elapsed = 00:02:19 . Memory (MB): peak = 3399.461 ; gain = 1273.105 ; free physical = 7448 ; free virtual = 18411
-Synthesis Optimization Complete : Time (s): cpu = 00:04:16 ; elapsed = 00:02:27 . Memory (MB): peak = 3399.461 ; gain = 1577.168 ; free physical = 7457 ; free virtual = 18410
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.78 . Memory (MB): peak = 3399.461 ; gain = 0.000 ; free physical = 7471 ; free virtual = 18424
-INFO: [Netlist 29-17] Analyzing 8872 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3583.805 ; gain = 0.000 ; free physical = 7384 ; free virtual = 18337
-INFO: [Project 1-111] Unisim Transformation Summary:
- A total of 247 instances were transformed.
- IOBUF => IOBUF (IBUF, OBUFT): 8 instances
- LDC => LDCE: 9 instances
- RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 225 instances
- RAM32X1D => RAM32X1D (RAMD32(x2)): 5 instances
-
-Synth Design complete | Checksum: c2316b55
-INFO: [Common 17-83] Releasing license: Synthesis
-727 Infos, 400 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:04:34 ; elapsed = 00:02:45 . Memory (MB): peak = 3583.840 ; gain = 1927.656 ; free physical = 7361 ; free virtual = 18314
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 10079.181; main = 2857.954; forked = 8220.542
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19235.441; main = 3583.809; forked = 16205.852
-# apply_genesys2_async_clock_groups
-Applying Genesys2 async clock groups.
-# write_checkpoint -force [file join $checkpoint_dir post_synth.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3631.820 ; gain = 0.000 ; free physical = 7358 ; free virtual = 18311
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3631.820 ; gain = 0.000 ; free physical = 7358 ; free virtual = 18311
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3631.820 ; gain = 0.000 ; free physical = 7358 ; free virtual = 18312
-Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3631.820 ; gain = 0.000 ; free physical = 7358 ; free virtual = 18312
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3631.820 ; gain = 0.000 ; free physical = 7358 ; free virtual = 18312
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3631.820 ; gain = 0.000 ; free physical = 7358 ; free virtual = 18312
-Write Physdb Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3631.820 ; gain = 0.000 ; free physical = 7358 ; free virtual = 18312
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3631.820 ; gain = 0.000 ; free physical = 7334 ; free virtual = 18301
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_synth.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 3631.820 ; gain = 32.016 ; free physical = 7340 ; free virtual = 18293
-# report_utilization -hierarchical -file [file join $report_dir synth_utilization_hier.rpt]
-# report_utilization -file [file join $report_dir synth_utilization.rpt]
-# report_timing_summary -file [file join $report_dir synth_timing_summary.rpt]
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs
-report_timing_summary: Time (s): cpu = 00:00:44 ; elapsed = 00:00:09 . Memory (MB): peak = 3631.820 ; gain = 0.000 ; free physical = 7325 ; free virtual = 18278
-# puts "Running implementation..."
-Running implementation...
-# opt_design
-Command: opt_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-Running DRC as a precondition to command opt_design
-
-Starting DRC Task
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Project 1-461] DRC finished with 0 Errors
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.53 . Memory (MB): peak = 3682.008 ; gain = 50.188 ; free physical = 7325 ; free virtual = 18278
-
-Starting Cache Timing Information Task
-Ending Cache Timing Information Task | Checksum: 18d214bef
-
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3682.008 ; gain = 0.000 ; free physical = 7325 ; free virtual = 18278
-
-Starting Logic Optimization Task
-
-Phase 1 Initialization
-
-Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 18d214bef
-
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3692.914 ; gain = 0.000 ; free physical = 7286 ; free virtual = 18239
-
-Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 18d214bef
-
-Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3692.914 ; gain = 0.000 ; free physical = 7286 ; free virtual = 18239
-Phase 1 Initialization | Checksum: 18d214bef
-
-Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3692.914 ; gain = 0.000 ; free physical = 7286 ; free virtual = 18239
-
-Phase 2 Timer Update And Timing Data Collection
-
-Phase 2.1 Detect if minReqCache needed
-Phase 2.1 Detect if minReqCache needed | Checksum: 18d214bef
-
-Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7255 ; free virtual = 18208
-
-Phase 2.2 Timer Update
-Phase 2.2 Timer Update | Checksum: 18d214bef
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7256 ; free virtual = 18209
-
-Phase 2.3 Timing Data Collection
-Phase 2.3 Timing Data Collection | Checksum: 18d214bef
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7255 ; free virtual = 18208
-Phase 2 Timer Update And Timing Data Collection | Checksum: 18d214bef
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7255 ; free virtual = 18208
-
-Phase 3 Retarget
-INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
-INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
-INFO: [Opt 31-1566] Pulled 28 inverters resulting in an inversion of 507 pins
-INFO: [Opt 31-138] Pushed 14 inverter(s) to 130 load pin(s).
-INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 1e908047d
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7258 ; free virtual = 18211
-Retarget | Checksum: 1e908047d
-INFO: [Opt 31-389] Phase Retarget created 683 cells and removed 724 cells
-INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 4 Constant propagation
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 1af415512
-
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7258 ; free virtual = 18211
-Constant propagation | Checksum: 1af415512
-INFO: [Opt 31-389] Phase Constant propagation created 1 cells and removed 1 cells
-
-Phase 5 Sweep
-INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
-Done building netlist checker database: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3711.883 ; gain = 0.000 ; free physical = 7258 ; free virtual = 18211
-Phase 5 Sweep | Checksum: 13df81a3b
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7259 ; free virtual = 18212
-Sweep | Checksum: 13df81a3b
-INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 9 cells
-INFO: [Opt 31-1021] In phase Sweep, 360 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 6 BUFG optimization
-Phase 6 BUFG optimization | Checksum: 13df81a3b
-
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7261 ; free virtual = 18214
-BUFG optimization | Checksum: 13df81a3b
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
-
-Phase 7 Shift Register Optimization
-INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 13df81a3b
-
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7261 ; free virtual = 18214
-Shift Register Optimization | Checksum: 13df81a3b
-INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
-
-Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 13df81a3b
-
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7261 ; free virtual = 18214
-Post Processing Netlist | Checksum: 13df81a3b
-INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
-
-Phase 9 Finalization
-
-Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1c929d98e
-
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7265 ; free virtual = 18218
-
-Phase 9.2 Verifying Netlist Connectivity
-
-Starting Connectivity Check Task
-
-Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3711.883 ; gain = 0.000 ; free physical = 7264 ; free virtual = 18217
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 1c929d98e
-
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7264 ; free virtual = 18217
-Phase 9 Finalization | Checksum: 1c929d98e
-
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7264 ; free virtual = 18217
-Opt_design Change Summary
-=========================
-
-
--------------------------------------------------------------------------------------------------------------------------
-| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
--------------------------------------------------------------------------------------------------------------------------
-| Retarget | 683 | 724 | 1 |
-| Constant propagation | 1 | 1 | 0 |
-| Sweep | 0 | 9 | 360 |
-| BUFG optimization | 0 | 0 | 0 |
-| Shift Register Optimization | 0 | 0 | 0 |
-| Post Processing Netlist | 0 | 0 | 0 |
--------------------------------------------------------------------------------------------------------------------------
-
-
-Ending Logic Optimization Task | Checksum: 1c929d98e
-
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 3711.883 ; gain = 18.969 ; free physical = 7264 ; free virtual = 18217
-
-Starting Power Optimization Task
-INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-INFO: [Power 33-23] Power model is not available for u_cfg_flash_startup
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running Vector-less Activity Propagation...
-
-Finished Running Vector-less Activity Propagation
-INFO: [Pwropt 34-9] Applying IDT optimizations ...
-INFO: [Pwropt 34-10] Applying ODC optimizations ...
-
-
-Starting PowerOpt Patch Enables Task
-INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 419 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
-INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
-Number of BRAM Ports augmented: 0 newly gated: 84 Total Ports: 838
-Ending PowerOpt Patch Enables Task | Checksum: 1bae12972
-
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6804 ; free virtual = 17757
-Ending Power Optimization Task | Checksum: 1bae12972
-
-Time (s): cpu = 00:00:42 ; elapsed = 00:00:23 . Memory (MB): peak = 4339.789 ; gain = 627.906 ; free physical = 6804 ; free virtual = 17757
-
-Starting Final Cleanup Task
-
-Starting Logic Optimization Task
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Logic Optimization Task | Checksum: 17d9bbac3
-
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:04 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6815 ; free virtual = 17768
-Ending Final Cleanup Task | Checksum: 17d9bbac3
-
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6814 ; free virtual = 17767
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6814 ; free virtual = 17767
-INFO: [Common 17-83] Releasing license: Implementation
-29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-opt_design completed successfully
-opt_design: Time (s): cpu = 00:01:12 ; elapsed = 00:00:39 . Memory (MB): peak = 4339.789 ; gain = 707.969 ; free physical = 6814 ; free virtual = 17767
-# write_checkpoint -force [file join $checkpoint_dir post_opt.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6814 ; free virtual = 17767
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6814 ; free virtual = 17767
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6814 ; free virtual = 17767
-Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6814 ; free virtual = 17767
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6814 ; free virtual = 17767
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6814 ; free virtual = 17768
-Write Physdb Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6814 ; free virtual = 17768
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.13 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6793 ; free virtual = 17759
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_opt.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6745 ; free virtual = 17698
-# place_design
-Command: place_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-83] Releasing license: Implementation
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running DRC as a precondition to command place_design
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 12 CPUs
-
-Starting Placer Task
-
-Phase 1 Placer Initialization
-
-Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6748 ; free virtual = 17701
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 963dd95e
-
-Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6748 ; free virtual = 17701
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6748 ; free virtual = 17701
-
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fb77f731
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6781 ; free virtual = 17734
-
-Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 1d6ae0c21
-
-Time (s): cpu = 00:00:58 ; elapsed = 00:00:20 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6802 ; free virtual = 17755
-
-Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 1d6ae0c21
-
-Time (s): cpu = 00:00:58 ; elapsed = 00:00:20 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6802 ; free virtual = 17755
-Phase 1 Placer Initialization | Checksum: 1d6ae0c21
-
-Time (s): cpu = 00:00:58 ; elapsed = 00:00:20 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6802 ; free virtual = 17755
-
-Phase 2 Global Placement
-
-Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 1c9bbd2fa
-
-Time (s): cpu = 00:01:32 ; elapsed = 00:00:27 . Memory (MB): peak = 4339.789 ; gain = 0.000 ; free physical = 6853 ; free virtual = 17806
-
-Phase 2.2 Update Timing before SLR Path Opt
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream_310847.backup.jou b/targets/fpga/genesys2/out/logs/build_bitstream_310847.backup.jou
deleted file mode 100644
index b7a03f1..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream_310847.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 19:52:11 2026
-# Process ID : 310847
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21498 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream_39651.backup.log b/targets/fpga/genesys2/out/logs/build_bitstream_39651.backup.log
deleted file mode 100644
index 228e0d7..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream_39651.backup.log
+++ /dev/null
@@ -1,5253 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 17:17:03 2026
-# Process ID : 39651
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21714 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../../..]]
-# set repo_dir [file normalize [file join $fpga_dir ../../..]]
-# set hardware_dir [file join $repo_dir hardware]
-# cd $repo_dir
-# set part_name "xc7k325tffg900-2"
-# set board_part "digilentinc.com:genesys2:part0:1.1"
-# set top_module "genesys2_rocket_top"
-# set out_dir [file join $fpga_dir out]
-# set generated_dir [file join $out_dir build generated]
-# set report_dir [file join $out_dir reports]
-# set bit_dir [file join $out_dir bitstream]
-# set checkpoint_dir [file join $out_dir build checkpoints]
-# file mkdir $generated_dir
-# file mkdir $report_dir
-# file mkdir $bit_dir
-# file mkdir $checkpoint_dir
-# set rocket_rtl_dir [file join $hardware_dir generated genesys2-soc-verilog]
-# set rocket_top [file join $rocket_rtl_dir VCU118RocketSystem.sv]
-# set rocket_filelist [file join $rocket_rtl_dir filelist.f]
-# set wrapper [file join $generated_dir ${top_module}.sv]
-# if {[info exists ::env(GPS_SYSTEM_DIR)] && [string trim $::env(GPS_SYSTEM_DIR)] ne ""} {
-# set gps_system_dir [file normalize $::env(GPS_SYSTEM_DIR)]
-# } else {
-# set gps_system_dir [file join $hardware_dir external gps rtl]
-# }
-# if {[info exists ::env(RF_INPUT_MODE)]} {
-# set rf_input_mode [string tolower [string trim $::env(RF_INPUT_MODE)]]
-# } else {
-# set rf_input_mode "pmod"
-# }
-# if {$rf_input_mode ni {"pmod" "generated" "ethernet"}} {
-# error "Unsupported Genesys2 RF_INPUT_MODE=$rf_input_mode. Use pmod, generated, or ethernet."
-# }
-# if {![file exists $rocket_filelist]} {
-# error "Rocket Verilog filelist not found: $rocket_filelist"
-# }
-# if {![file exists $rocket_top]} {
-# error "Rocket top Verilog not found: $rocket_top"
-# }
-# puts "Generating Genesys2 wrapper: $wrapper"
-Generating Genesys2 wrapper: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv
-# puts "Genesys2 RF input mode: $rf_input_mode"
-Genesys2 RF input mode: pmod
-# exec python3 [file join $fpga_dir tools gen_genesys2_wrapper.py] \
-# --rocket-top $rocket_top \
-# --out $wrapper \
-# --rf-input-mode $rf_input_mode
-# set max_threads [string trim [exec nproc]]
-# puts "Using Vivado maxThreads=$max_threads"
-Using Vivado maxThreads=12
-# set_param general.maxThreads $max_threads
-# set_part $part_name
-INFO: [Coretcl 2-1500] The part has been set to 'xc7k325tffg900-2' for the current project only. Run set_part -help for more details. To evaluate different speed grades in the current design, use the set_speed_grade command, or use the open_checkpoint -part command to change the part used by an existing checkpoint design.
-# if {[llength [get_board_parts -quiet $board_part]] != 0} {
-# set_property board_part $board_part [current_project]
-# }
-# proc apply_genesys2_async_clock_groups {} {
-# set fabric_clk [get_clocks -quiet pll_fabric_clk]
-# set gps_acq_clk [get_clocks -quiet pll_gps_acq_clk]
-# set gps_trck_clk [get_clocks -quiet pll_gps_trck_clk]
-# set gps_rf_clk [get_clocks -quiet {pll_gps_rf_exact_clk pmod_rf_clk}]
-# set eth_clk [get_clocks -quiet genesys2_eth_rxck]
-#
-# if {[llength $fabric_clk] == 0 ||
-# [llength $gps_acq_clk] == 0 ||
-# [llength $gps_trck_clk] == 0 ||
-# [llength $gps_rf_clk] == 0} {
-# puts "Warning: not all Genesys2 async clock groups are available yet."
-# return
-# }
-#
-# puts "Applying Genesys2 async clock groups."
-# set args [list -asynchronous \
-# -group $fabric_clk \
-# -group $gps_acq_clk \
-# -group $gps_trck_clk \
-# -group $gps_rf_clk]
-# if {[llength $eth_clk] != 0} {
-# lappend args -group $eth_clk
-# }
-# set_clock_groups {*}$args
-# }
-# set rocket_files {}
-# set fh [open $rocket_filelist r]
-# while {[gets $fh line] >= 0} {
-# set line [string trim $line]
-# if {$line eq ""} {
-# continue
-# }
-# set line [regsub {^\./} $line ""]
-# lappend rocket_files [file normalize [file join $rocket_rtl_dir $line]]
-# }
-# close $fh
-# puts "Reading Rocket Chip RTL..."
-Reading Rocket Chip RTL...
-# read_verilog -sv $rocket_files
-# read_verilog [file join $hardware_dir upstream rocket-chip src main resources vsrc plusarg_reader.v]
-# set gps_filelist [file join $hardware_dir external gps rtl filelist.f]
-# set gps_files {}
-# set gps_fh [open $gps_filelist r]
-# while {[gets $gps_fh rel] >= 0} {
-# set rel [string trim $rel]
-# if {$rel eq "" || [string match "#*" $rel]} {
-# continue
-# }
-# lappend gps_files [file join $gps_system_dir $rel]
-# }
-# close $gps_fh
-# puts "Reading GPS APB wrapper RTL from $gps_system_dir..."
-Reading GPS APB wrapper RTL from /home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl...
-# set_property include_dirs [list [file join $gps_system_dir trck_src pulp_fifo]] [current_fileset]
-# read_verilog -sv $gps_files
-# puts "Reading Genesys2 shell RTL..."
-Reading Genesys2 shell RTL...
-# set shell_files [list \
-# [file join $hardware_dir fpga vcu118 rtl axi4_ram_64.sv] \
-# [file join $hardware_dir fpga vcu118 rtl axi4_slave_tieoff_64.sv] \
-# [file join $hardware_dir fpga genesys2 rtl rocket_bscan_dmi_tunnel.sv] \
-# ]
-# if {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet RF RTL..."
-# lappend shell_files \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_async_fifo.sv] \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_core.sv] \
-# [file join $hardware_dir fpga genesys2 rtl ethernet_rf eth_rf_genesys2.sv]
-# } else {
-# puts "Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=$rf_input_mode."
-# }
-Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=pmod.
-# read_verilog -sv $shell_files
-# read_verilog -sv $wrapper
-# puts "Reading constraints..."
-Reading constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_rocket.xdc]
-# puts "Reading Genesys2 PMOD SPI constraints..."
-Reading Genesys2 PMOD SPI constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_spi.xdc]
-# puts "Reading Genesys2 PMOD sensor IRQ constraints..."
-Reading Genesys2 PMOD sensor IRQ constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_irq.xdc]
-# puts "Reading Genesys2 PMOD PPS constraints..."
-Reading Genesys2 PMOD PPS constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_pps.xdc]
-# if {$rf_input_mode eq "pmod"} {
-# puts "Reading Genesys2 PMOD RF constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_rf.xdc]
-# } elseif {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet PHY constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_ethernet.xdc]
-# }
-Reading Genesys2 PMOD RF constraints...
-# puts "Running synthesis for $part_name..."
-Running synthesis for xc7k325tffg900-2...
-# synth_design -top $top_module -part $part_name -verilog_define SYNTHESIS
-Command: synth_design -top genesys2_rocket_top -part xc7k325tffg900-2 -verilog_define SYNTHESIS
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Device 21-403] Loading part xc7k325tffg900-2
-INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
-INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 39676
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2304.605 ; gain = 484.875 ; free physical = 6438 ; free virtual = 19279
----------------------------------------------------------------------------------
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:8]
-WARNING: [Synth 8-11067] parameter 'CODE_LENGTH_IN_CHIPS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:9]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:10]
-WARNING: [Synth 8-11067] parameter 'SAMPLING_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:13]
-WARNING: [Synth 8-11067] parameter 'CENTER_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:14]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:15]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:16]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:17]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:18]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:19]
-WARNING: [Synth 8-11067] parameter 'ABS_SAMPLE_CNTR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:22]
-WARNING: [Synth 8-11067] parameter 'MS_PER_BIT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:23]
-WARNING: [Synth 8-11067] parameter 'C_ACQ_CHN_NUM' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:26]
-WARNING: [Synth 8-11067] parameter 'ACQ_IQ_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:27]
-WARNING: [Synth 8-11067] parameter 'ACQ_CORR_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:28]
-WARNING: [Synth 8-11067] parameter 'RF_DMEM_AL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:30]
-WARNING: [Synth 8-11067] parameter 'NUM_PRN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:31]
-WARNING: [Synth 8-11067] parameter 'PRN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:32]
-WARNING: [Synth 8-11067] parameter 'STRECH_COUNT_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:33]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_COEF1' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:40]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:41]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:42]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:43]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:44]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:45]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_FREQ_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:46]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:47]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:48]
-WARNING: [Synth 8-11067] parameter 'NUM_TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:50]
-WARNING: [Synth 8-11067] parameter 'TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:51]
-WARNING: [Synth 8-11067] parameter 'ATAN_ANGLE_BIT_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:56]
-WARNING: [Synth 8-11067] parameter 'ATAN_TABLE_SIZE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:57]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:60]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:61]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:62]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_SPACE_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:63]
-WARNING: [Synth 8-11067] parameter 'C1_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:65]
-WARNING: [Synth 8-11067] parameter 'C2_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:66]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:71]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:72]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:73]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:76]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:77]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:78]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:80]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:81]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:83]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:84]
-WARNING: [Synth 8-11067] parameter 'LOCK_WINDOW' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:85]
-WARNING: [Synth 8-11067] parameter 'LOCK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:86]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:89]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:90]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:92]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:93]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:95]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:96]
-WARNING: [Synth 8-11067] parameter 'CODE_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:99]
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:100]
-WARNING: [Synth 8-11067] parameter 'REAL_POS_FS_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:102]
-WARNING: [Synth 8-11067] parameter 'REAL_NEG_FS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:103]
-WARNING: [Synth 8-11067] parameter 'FS_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:105]
-WARNING: [Synth 8-11067] parameter 'DLL_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:106]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:108]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:109]
-WARNING: [Synth 8-11067] parameter 'REM_CODE_PH_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:110]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:113]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:114]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:115]
-WARNING: [Synth 8-11067] parameter 'F_ACQ_CLK' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:118]
-WARNING: [Synth 8-11067] parameter 'ACQ_CLK_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:119]
-WARNING: [Synth 8-11067] parameter 'RF_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:120]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE_CHIP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:121]
-WARNING: [Synth 8-11067] parameter 'ACQ_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:123]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:124]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:125]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:126]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:127]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:128]
-WARNING: [Synth 8-11067] parameter 'ACQ_CODE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:130]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:132]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:133]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:134]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:135]
-WARNING: [Synth 8-11067] parameter 'IFFT_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:136]
-WARNING: [Synth 8-11067] parameter 'IFFT_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:137]
-WARNING: [Synth 8-11067] parameter 'IFFT_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:139]
-WARNING: [Synth 8-11067] parameter 'NFFT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:141]
-WARNING: [Synth 8-11067] parameter 'NFFT_OVER_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:142]
-WARNING: [Synth 8-11067] parameter 'ZERO_PAD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:143]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:145]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:146]
-WARNING: [Synth 8-11067] parameter 'ABS_SQR_I_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:147]
-WARNING: [Synth 8-11067] parameter 'CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:148]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_DIV_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:149]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:150]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:151]
-WARNING: [Synth 8-11067] parameter 'PEAK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:152]
-WARNING: [Synth 8-11067] parameter 'DOPP_STEP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:154]
-WARNING: [Synth 8-11067] parameter 'NUM_FREQ_BIN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:155]
-WARNING: [Synth 8-11067] parameter 'FREQ_BIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:156]
-INFO: [Common 17-14] Message 'Synth 8-11067' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-10180] variable 'i' must explicitly be declared as automatic or static [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv:53]
-INFO: [Synth 8-6157] synthesizing module 'genesys2_rocket_top' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:3]
-INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
- Parameter DIFF_TERM bound to: FALSE - type: string
- Parameter IBUF_LOW_PWR bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 5.000000e+00 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 5.000000e+00 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.250000e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT1_DIVIDE bound to: 20 - type: integer
- Parameter CLKOUT1_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT1_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT2_DIVIDE bound to: 8 - type: integer
- Parameter CLKOUT2_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT2_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:66]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:66]
-WARNING: [Synth 8-7023] instance 'u_clock_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:66]
-INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6157] synthesizing module 'IBUF' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6157] synthesizing module 'BSCANE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
- Parameter DISABLE_JTAG bound to: FALSE - type: string
- Parameter JTAG_CHAIN bound to: 4 - type: integer
-INFO: [Synth 8-6155] done synthesizing module 'BSCANE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
-INFO: [Synth 8-6157] synthesizing module 'rocket_bscan_dmi_tunnel' [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'rocket_bscan_dmi_tunnel' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:264]
-INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
- Parameter PROG_USR bound to: FALSE - type: string
- Parameter SIM_CCLK_FREQ bound to: 0.000000e+00 - type: double
-INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
-INFO: [Synth 8-6157] synthesizing module 'VCU118RocketSystem' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/VCU118RocketSystem.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockSinkDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i2_o1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i2_o1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockSinkDomain' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_aggregator' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_aggregator' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_sbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_sbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroup' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroup' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_5' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_5' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x120' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x120' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x77' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x77' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAUART' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAUART' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_gps' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAGPS' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAGPS' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_2' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_2' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_gps' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FrontBus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x123' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x123' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FrontBus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_2' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_2' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x124' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x124' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x78' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x78' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x99' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x99' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_debug' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_Debug' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_Debug' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_debug' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_4' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_4' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TilePRCIDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'HierarchicalElementResetDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/HierarchicalElementResetDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'RocketTile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/RocketTile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i3_o1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i3_o1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'DCache' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'DTLB' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:31]
-INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-6155] done synthesizing module 'PMPChecker_s3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PMPChecker_s3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PMAChecker' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PMAChecker.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:194]
-INFO: [Synth 8-6155] done synthesizing module 'OptimizationBarrier_TLBEntryData' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/OptimizationBarrier_TLBEntryData.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:228]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:262]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:296]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:330]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:364]
-INFO: [Synth 8-6155] done synthesizing module 'DTLB' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:1121]
-INFO: [Synth 8-6155] done synthesizing module 'Arbiter8_DCacheMetadataReq' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Arbiter8_DCacheMetadataReq.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'rockettile_dcache_data_arrays_0_131072x64' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'DCacheDataArray' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCacheDataArray.sv:31]
-INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:139]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:173]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:207]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:241]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:275]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:309]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PTW.sv:188]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:3191]
- Parameter FORMAT bound to: max_core_cycles=%d - type: string
- Parameter WIDTH bound to: 32 - type: integer
- Parameter DEFAULT bound to: 32'b00000000000000000000000000000000
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:400]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:406]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:412]
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000000001
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter DATA_WIDTH bound to: 4 - type: integer
- Parameter ADDR_WIDTH bound to: 15 - type: integer
- Parameter PH_ACC_WL bound to: 32 - type: integer
- Parameter LUT_DEPTH_WL bound to: 5 - type: integer
- Parameter ACQ_SIN_IL bound to: 2 - type: integer
- Parameter ACQ_SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 25 - type: integer
- Parameter FS bound to: 16368000 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 52 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 36 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_IQ_WL bound to: 24 - type: integer
- Parameter FFT_IQ_TRUNC_WL bound to: 20 - type: integer
- Parameter FFT_CODE_WL bound to: 16 - type: integer
- Parameter FFT_CODE_TRUNC_WL bound to: 16 - type: integer
- Parameter OUT_WL bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 92 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter DWIDTH bound to: 48 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ABS_SQR_I_TRUNCATED_WL bound to: 25 - type: integer
- Parameter CORR_DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter SAMPLES_PER_CODE_CHIP bound to: 16 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv:158]
- Parameter DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ITER bound to: 9 - type: integer
- Parameter IN_W_L bound to: 36 - type: integer
- Parameter IN_F_L bound to: 0 - type: integer
- Parameter OUT_W_L bound to: 16 - type: integer
- Parameter OUT_F_L bound to: 8 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:285]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:296]
-WARNING: [Synth 8-151] case item 32'b00000000000000000000000000001100 is unreachable [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:350]
-WARNING: [Synth 8-7071] port 'clk_200mhz' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'mmcm_locked' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rd' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rxc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_td' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_tx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7071] port 'eth_rgmii_txc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
-WARNING: [Synth 8-7023] instance 'afe' of module 'afe_top' has 17 connections declared, but only 9 given [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:159]
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000100000
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter SIG_DEPTH bound to: 26 - type: integer
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:182]
- Parameter WIDTH bound to: 4 - type: integer
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter STAGES bound to: 32'b00000000000000000000000000000010
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter Bypass bound to: 1'b0
- Parameter PH_ACC_WL bound to: 24 - type: integer
- Parameter LUT_DEPTH_WL bound to: 7 - type: integer
- Parameter SIN_IL bound to: 2 - type: integer
- Parameter SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 46 - type: integer
- Parameter CODE_FREQ_I_IL bound to: 21 - type: integer
- Parameter CODE_FREQ_I_FL bound to: 20 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 10 - type: integer
- Parameter O_IL bound to: 16 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 13 - type: integer
- Parameter O_IL bound to: 8 - type: integer
- Parameter O_FL bound to: 20 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter TABLE_ADDR bound to: 4 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 33 - type: integer
-WARNING: [Synth 8-7071] port 'vec_len_o' of module 'cordic_atan_basic' is unconnected for instance 'Disc_PLL_i' [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:218]
-WARNING: [Synth 8-7023] instance 'Disc_PLL_i' of module 'cordic_atan_basic' has 8 connections declared, but only 7 given [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:218]
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER1 bound to: 8 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter TABLE_ADDR bound to: 3 - type: integer
-WARNING: [Synth 8-151] case item 4'b1000 is unreachable [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:114]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:105]
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 32 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 25 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter DIV_OUT_WL bound to: 15 - type: integer
- Parameter DIV_OUT_FL bound to: 13 - type: integer
- Parameter DIV_ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 45 - type: integer
- Parameter IN_FL bound to: 8 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:288]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:546]
- Parameter HIGH_ADDRESS bound to: 32'b00000000000000000000111111111111
- Parameter LOW_ADDRESS bound to: 32'b00000000000000000000000000000000
- Parameter DATA_BUS_WIDTH bound to: 32'b00000000000000000000000000100000
- Parameter ADDR_BUS_WIDTH bound to: 32'b00000000000000000000000000001100
- Parameter NUM_CAPTURE_CHANNELS bound to: 32'b00000000000000000000000000001001
- Parameter CLK_FREQ_HZ bound to: 32'b00000111011100110101100101000000
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:48]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:49]
-WARNING: [Synth 8-6014] Unused sequential element s2_vaddr_r_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:989]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:47]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:48]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:47]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:48]
-WARNING: [Synth 8-4767] Trying to implement RAM 'Memory_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/regfile_32x65.sv:60]
-Reason is one or more of the following :
- 1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
- 2: Invalid write to RAM.
- 3: Invalid write to RAM.
- 4: No valid clock found for write to RAM.
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2183]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2626]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2637]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2754]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2755]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2757]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2758]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2769]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2770]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2772]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2773]
-WARNING: [Synth 8-6014] Unused sequential element rocc_blocked_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2894]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2895]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2896]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2897]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2898]
-WARNING: [Synth 8-6014] Unused sequential element r_counter_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError_1.sv:69]
-Read & Write Range Direction Mismatch
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module comp_mult has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/comp_mult.sv:106]
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module ifft_abs_sqr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:90]
-WARNING: [Synth 8-3848] Net eth_rgmii_td in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:38]
-WARNING: [Synth 8-3848] Net eth_rgmii_tx_ctl in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:39]
-WARNING: [Synth 8-3848] Net eth_rgmii_txc in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:40]
-WARNING: [Synth 8-3848] Net rf_data_o in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:46]
-WARNING: [Synth 8-3848] Net fifo_of_o in module/entity trck_cntrl does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:50]
-WARNING: [Synth 8-6014] Unused sequential element g1_var_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:46]
-WARNING: [Synth 8-7137] Register chip_o_reg in module cacode_gen_trck has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:36]
-WARNING: [Synth 8-7129] Port PENABLE in module pps_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port fifo_of_o in module trck_cntrl is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port trck_resetn in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port afe_resetn in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_tx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_txc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port clk_200mhz in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port mmcm_locked in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rxc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port start_acq_manuel in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_en in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_clk in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[3] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_sink in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[127] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[126] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[125] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[124] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[123] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[122] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[121] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[120] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[119] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[118] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[117] in module SBToTL is either unconnected or has no load
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2702.895 ; gain = 883.164 ; free physical = 6019 ; free virtual = 18867
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2702.895 ; gain = 883.164 ; free physical = 6026 ; free virtual = 18874
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2702.895 ; gain = 883.164 ; free physical = 6026 ; free virtual = 18874
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2702.895 ; gain = 0.000 ; free physical = 6043 ; free virtual = 18891
-INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-INFO: [Timing 38-2] Deriving generated clocks
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2988.035 ; gain = 0.000 ; free physical = 5984 ; free virtual = 18833
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2999.957 ; gain = 0.000 ; free physical = 5976 ; free virtual = 18826
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2999.957 ; gain = 1180.227 ; free physical = 5132 ; free virtual = 17982
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7k325tffg900-2
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 3007.961 ; gain = 1188.230 ; free physical = 5113 ; free virtual = 17963
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 3007.961 ; gain = 1188.230 ; free physical = 5080 ; free virtual = 17930
----------------------------------------------------------------------------------
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:405]
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:443]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '99' to '12' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:57]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore2_addr_reg' and it is trimmed from '34' to '20' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:383]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore1_addr_reg' and it is trimmed from '34' to '20' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:383]
-WARNING: [Synth 8-3936] Found unconnected internal register 'uncachedReqs_0_addr_reg' and it is trimmed from '34' to '3' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:958]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in1_reg' and it is trimmed from '65' to '33' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:58]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in3_reg' and it is trimmed from '65' to '33' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:60]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPToInt.sv:173]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_typeTagOut_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPToInt.sv:95]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_pipe_b_typeTagIn_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntToFP.sv:66]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:524]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:333]
-WARNING: [Synth 8-3936] Found unconnected internal register 'load_wb_typeTag_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:142]
-WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2787]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2787]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2822]
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized1'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_peak_srch'
-INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'divider_fsm'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_top'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'acq_wrapper'
-INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'trck_cntrl'
-INFO: [Synth 8-802] inferred FSM for state register 'nav_solve_state_p_reg' in module 'nav_solve_timer'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'tracking_wrapper'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'pps_wrapper'
-WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '88' to '87' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a29d32s7k1z2u.sv:66]
-WARNING: [Synth 8-6841] Block RAM (Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-INFO: [Synth 8-3971] The signal "dual_port_bram:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized0:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized1:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized1'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 001 | 000
- S_CORR | 101 | 001
- S_INIT_ADDR | 100 | 010
- S_DATA_Q | 011 | 011
- S_SRCH | 010 | 100
- S_END | 000 | 101
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'sequential' in module 'acq_peak_srch'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- idle | 00 | 00
- normalization | 01 | 01
- cordic_core | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'divider_fsm'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 0000001 | 000
- S_WR_DATA | 0001000 | 001
- S_START | 0010000 | 010
- S_CTRL | 1000000 | 011
- S_FREQ | 0100000 | 100
- S_END | 0000010 | 101
- S_PULLIN | 0000100 | 110
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'one-hot' in module 'acq_top'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'acq_wrapper'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- WAIT_START | 00 | 00
- WAIT_SAMPLE_ALIGN | 01 | 01
- WAIT_CODE_PHASE | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'trck_cntrl'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- iSTATE0 | 0 | 00000000000000000000000000000000
-*
- iSTATE | 1 | 00000000000000000000000000000001
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'nav_solve_state_p_reg' using encoding 'sequential' in module 'nav_solve_timer'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'tracking_wrapper'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- PPS_APB_STATE_IDLE | 001 | 00
- PPS_APB_STATE_ACCESS | 100 | 01
- PPS_APB_STATE_FINISH | 010 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'pps_wrapper'
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 3007.961 ; gain = 1188.230 ; free physical = 2244 ; free virtual = 15103
----------------------------------------------------------------------------------
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_5'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_5'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'u_rocket/tile_prci_domain/intsource_2'
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
----------------------------------------------------------------------------------
-Start RTL Component Statistics
----------------------------------------------------------------------------------
-Detailed RTL Component Info :
-+---Adders :
- 4 Input 128 Bit Adders := 1
- 2 Input 112 Bit Adders := 3
- 2 Input 109 Bit Adders := 1
- 2 Input 107 Bit Adders := 1
- 2 Input 99 Bit Adders := 1
- 2 Input 66 Bit Adders := 1
- 3 Input 65 Bit Adders := 2
- 2 Input 65 Bit Adders := 2
- 2 Input 64 Bit Adders := 12
- 3 Input 64 Bit Adders := 2
- 2 Input 62 Bit Adders := 1
- 3 Input 61 Bit Adders := 1
- 3 Input 58 Bit Adders := 1
- 2 Input 58 Bit Adders := 2
- 2 Input 55 Bit Adders := 4
- 2 Input 51 Bit Adders := 2
- 2 Input 49 Bit Adders := 1
- 2 Input 46 Bit Adders := 11
- 3 Input 46 Bit Adders := 2
- 2 Input 45 Bit Adders := 18
- 3 Input 45 Bit Adders := 10
- 2 Input 42 Bit Adders := 1
- 2 Input 41 Bit Adders := 9
- 3 Input 41 Bit Adders := 1
- 2 Input 34 Bit Adders := 3
- 3 Input 33 Bit Adders := 18
- 2 Input 32 Bit Adders := 75
- 3 Input 32 Bit Adders := 58
- 2 Input 30 Bit Adders := 18
- 3 Input 30 Bit Adders := 1
- 3 Input 29 Bit Adders := 1
- 2 Input 28 Bit Adders := 18
- 2 Input 26 Bit Adders := 25
- 3 Input 26 Bit Adders := 2
- 2 Input 25 Bit Adders := 11
- 3 Input 25 Bit Adders := 9
- 2 Input 23 Bit Adders := 54
- 2 Input 22 Bit Adders := 18
- 2 Input 18 Bit Adders := 2
- 3 Input 18 Bit Adders := 2
- 3 Input 16 Bit Adders := 1
- 2 Input 16 Bit Adders := 1
- 2 Input 15 Bit Adders := 2
- 2 Input 14 Bit Adders := 20
- 4 Input 14 Bit Adders := 1
- 3 Input 14 Bit Adders := 1
- 3 Input 13 Bit Adders := 2
- 2 Input 13 Bit Adders := 7
- 2 Input 12 Bit Adders := 13
- 3 Input 12 Bit Adders := 10
- 4 Input 11 Bit Adders := 1
- 2 Input 11 Bit Adders := 4
- 3 Input 10 Bit Adders := 2
- 2 Input 10 Bit Adders := 1
- 2 Input 9 Bit Adders := 11
- 3 Input 9 Bit Adders := 5
- 2 Input 8 Bit Adders := 5
- 2 Input 7 Bit Adders := 4
- 2 Input 6 Bit Adders := 24
- 3 Input 6 Bit Adders := 2
- 2 Input 5 Bit Adders := 41
- 2 Input 4 Bit Adders := 86
- 3 Input 4 Bit Adders := 1
- 3 Input 3 Bit Adders := 9
- 2 Input 3 Bit Adders := 34
- 2 Input 2 Bit Adders := 6
- 3 Input 2 Bit Adders := 4
- 4 Input 2 Bit Adders := 1
- 5 Input 2 Bit Adders := 1
- 3 Input 1 Bit Adders := 3
- 2 Input 1 Bit Adders := 41
-+---XORs :
- 2 Input 65 Bit XORs := 1
- 2 Input 64 Bit XORs := 7
- 2 Input 33 Bit XORs := 1
- 2 Input 32 Bit XORs := 8
- 2 Input 29 Bit XORs := 16
- 2 Input 17 Bit XORs := 48
- 2 Input 16 Bit XORs := 2
- 2 Input 15 Bit XORs := 5
- 2 Input 14 Bit XORs := 1
- 2 Input 12 Bit XORs := 4
- 2 Input 10 Bit XORs := 4
- 2 Input 5 Bit XORs := 38
- 2 Input 4 Bit XORs := 2
- 2 Input 3 Bit XORs := 23
- 2 Input 2 Bit XORs := 7
- 2 Input 1 Bit XORs := 487
- 3 Input 1 Bit XORs := 68
- 6 Input 1 Bit XORs := 19
- 7 Input 1 Bit XORs := 18
- 13 Input 1 Bit XORs := 90
- 11 Input 1 Bit XORs := 63
- 12 Input 1 Bit XORs := 63
- 8 Input 1 Bit XORs := 54
- 10 Input 1 Bit XORs := 72
- 4 Input 1 Bit XORs := 54
- 14 Input 1 Bit XORs := 117
- 5 Input 1 Bit XORs := 18
- 15 Input 1 Bit XORs := 9
- 9 Input 1 Bit XORs := 54
- 16 Input 1 Bit XORs := 9
-+---XORs :
- 5 Bit Wide XORs := 36
- 4 Bit Wide XORs := 36
- 3 Bit Wide XORs := 36
- 2 Bit Wide XORs := 36
-+---Registers :
- 310 Bit Registers := 9
- 130 Bit Registers := 1
- 107 Bit Registers := 1
- 104 Bit Registers := 1
- 92 Bit Registers := 2
- 90 Bit Registers := 3
- 87 Bit Registers := 1
- 65 Bit Registers := 44
- 64 Bit Registers := 60
- 62 Bit Registers := 2
- 58 Bit Registers := 2
- 56 Bit Registers := 1
- 55 Bit Registers := 13
- 53 Bit Registers := 1
- 52 Bit Registers := 2
- 51 Bit Registers := 8
- 50 Bit Registers := 9
- 49 Bit Registers := 2
- 48 Bit Registers := 79
- 46 Bit Registers := 18
- 45 Bit Registers := 2
- 43 Bit Registers := 1
- 41 Bit Registers := 11
- 40 Bit Registers := 9
- 36 Bit Registers := 3
- 34 Bit Registers := 25
- 33 Bit Registers := 30
- 32 Bit Registers := 216
- 31 Bit Registers := 90
- 30 Bit Registers := 28
- 29 Bit Registers := 6
- 28 Bit Registers := 20
- 27 Bit Registers := 1
- 26 Bit Registers := 67
- 24 Bit Registers := 40
- 22 Bit Registers := 136
- 21 Bit Registers := 9
- 20 Bit Registers := 2
- 18 Bit Registers := 9
- 17 Bit Registers := 3
- 16 Bit Registers := 18
- 15 Bit Registers := 53
- 14 Bit Registers := 50
- 13 Bit Registers := 9
- 12 Bit Registers := 21
- 10 Bit Registers := 30
- 9 Bit Registers := 15
- 8 Bit Registers := 113
- 7 Bit Registers := 12
- 6 Bit Registers := 83
- 5 Bit Registers := 106
- 4 Bit Registers := 218
- 3 Bit Registers := 156
- 2 Bit Registers := 215
- 1 Bit Registers := 1444
-+---Multipliers :
- 60x65 Multipliers := 1
- 48x64 Multipliers := 2
- 53x53 Multipliers := 1
- 33x65 Multipliers := 1
- 66x66 Multipliers := 1
- 15x46 Multipliers := 4
- 27x32 Multipliers := 1
- 25x30 Multipliers := 9
-+---RAMs :
- 8192K Bit (131072 X 64 bit) RAMs := 1
- 1472K Bit (16384 X 92 bit) RAMs := 1
- 832K Bit (16384 X 52 bit) RAMs := 1
- 816K Bit (16384 X 51 bit) RAMs := 1
- 768K Bit (16384 X 48 bit) RAMs := 1
- 576K Bit (16384 X 36 bit) RAMs := 1
- 128K Bit (32768 X 4 bit) RAMs := 1
- 16K Bit (512 X 32 bit) RAMs := 2
- 1K Bit (64 X 21 bit) RAMs := 1
-+---ROMs :
- ROMs := 6
-+---Muxes :
- 2 Input 2080 Bit Muxes := 1
- 2 Input 130 Bit Muxes := 3
- 2 Input 128 Bit Muxes := 2
- 2 Input 112 Bit Muxes := 2
- 2 Input 109 Bit Muxes := 1
- 2 Input 108 Bit Muxes := 1
- 2 Input 92 Bit Muxes := 6
- 2 Input 65 Bit Muxes := 19
- 4 Input 65 Bit Muxes := 1
- 2 Input 64 Bit Muxes := 146
- 4 Input 64 Bit Muxes := 7
- 2 Input 62 Bit Muxes := 1
- 2 Input 61 Bit Muxes := 2
- 2 Input 58 Bit Muxes := 2
- 2 Input 56 Bit Muxes := 5
- 2 Input 55 Bit Muxes := 11
- 2 Input 54 Bit Muxes := 3
- 2 Input 53 Bit Muxes := 2
- 2 Input 52 Bit Muxes := 16
- 2 Input 51 Bit Muxes := 5
- 2 Input 50 Bit Muxes := 10
- 2 Input 48 Bit Muxes := 7
- 2 Input 46 Bit Muxes := 27
- 2 Input 45 Bit Muxes := 21
- 3 Input 45 Bit Muxes := 2
- 2 Input 44 Bit Muxes := 4
- 2 Input 41 Bit Muxes := 7
- 2 Input 36 Bit Muxes := 6
- 7 Input 36 Bit Muxes := 1
- 2 Input 34 Bit Muxes := 30
- 2 Input 33 Bit Muxes := 39
- 2 Input 32 Bit Muxes := 325
- 3 Input 32 Bit Muxes := 1
- 4 Input 32 Bit Muxes := 1
- 2 Input 30 Bit Muxes := 9
- 2 Input 29 Bit Muxes := 9
- 2 Input 28 Bit Muxes := 1
- 2 Input 27 Bit Muxes := 4
- 2 Input 26 Bit Muxes := 15
- 2 Input 25 Bit Muxes := 25
- 2 Input 24 Bit Muxes := 97
- 2 Input 23 Bit Muxes := 65
- 2 Input 22 Bit Muxes := 78
- 2 Input 20 Bit Muxes := 4
- 2 Input 17 Bit Muxes := 1
- 2 Input 16 Bit Muxes := 14
- 3 Input 16 Bit Muxes := 1
- 7 Input 16 Bit Muxes := 1
- 2 Input 15 Bit Muxes := 18
- 2 Input 14 Bit Muxes := 62
- 7 Input 14 Bit Muxes := 1
- 2 Input 13 Bit Muxes := 20
- 2 Input 12 Bit Muxes := 51
- 2 Input 11 Bit Muxes := 2
- 2 Input 10 Bit Muxes := 13
- 2 Input 9 Bit Muxes := 34
- 3 Input 9 Bit Muxes := 1
- 2 Input 8 Bit Muxes := 210
- 8 Input 8 Bit Muxes := 18
- 2 Input 7 Bit Muxes := 20
- 7 Input 7 Bit Muxes := 1
- 4 Input 6 Bit Muxes := 1
- 2 Input 6 Bit Muxes := 65
- 3 Input 6 Bit Muxes := 3
- 7 Input 6 Bit Muxes := 3
- 2 Input 5 Bit Muxes := 58
- 4 Input 5 Bit Muxes := 1
- 5 Input 5 Bit Muxes := 3
- 3 Input 5 Bit Muxes := 2
- 2 Input 4 Bit Muxes := 121
- 4 Input 4 Bit Muxes := 3
- 8 Input 4 Bit Muxes := 1
- 3 Input 4 Bit Muxes := 1
- 7 Input 4 Bit Muxes := 2
- 2 Input 3 Bit Muxes := 176
- 6 Input 3 Bit Muxes := 3
- 8 Input 3 Bit Muxes := 3
- 4 Input 3 Bit Muxes := 3
- 3 Input 3 Bit Muxes := 28
- 7 Input 3 Bit Muxes := 1
- 5 Input 3 Bit Muxes := 2
- 2 Input 2 Bit Muxes := 157
- 16 Input 2 Bit Muxes := 1
- 3 Input 2 Bit Muxes := 13
- 4 Input 2 Bit Muxes := 5
- 7 Input 2 Bit Muxes := 1
- 8 Input 2 Bit Muxes := 1
- 2 Input 1 Bit Muxes := 1395
- 3 Input 1 Bit Muxes := 42
- 5 Input 1 Bit Muxes := 28
- 4 Input 1 Bit Muxes := 21
- 6 Input 1 Bit Muxes := 1
- 7 Input 1 Bit Muxes := 9
----------------------------------------------------------------------------------
-Finished RTL Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 840 (col length:140)
-BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 10. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv:136]
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (dfma/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_vec_reg' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3886] merging instance 'mem_ctrl_vec_reg' (FDE) to 'mem_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_typeTagIn_reg[1]' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\ex_reg_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\in_pipe_b_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\mem_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[1]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[2]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[2]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[3]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[3]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[4]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (ifpu/\io_out_pipe_b_exc_reg[4] )
-INFO: [Synth 8-4471] merging register 's2_tlb_resp_pf_inst_reg' into 's2_tlb_resp_cacheable_reg' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Frontend.sv:127]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 16. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/MulDiv.sv:131]
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[60]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[60]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[61]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[61]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[62]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[62]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[57]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[57]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[58]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[58]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[59]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[59]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[54]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[54]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[55]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[55]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[56]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[56]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[51]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[51]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[52]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[52]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[53]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[53]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[48]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[48]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[49]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[49]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[50]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[50]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[45]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[45]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[46]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[46]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[47]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[47]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[42]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[42]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[43]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[43]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[44]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[44]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[39]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[39]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[40]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[40]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[41]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[41]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[36]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[36]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[37]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[37]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[38]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[38]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[33]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[33]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[34]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[34]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[35]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[35]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[30]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[30]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[31]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[31]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[32]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[32]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[27]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[27]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[28]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[28]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[29]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[29]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[24]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[24]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[25]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[25]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[26]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[26]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[21]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[21]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[22]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[22]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[23]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[23]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[18]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[18]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[19]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[19]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[20]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[20]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[15]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[15]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[16]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[16]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_reg_cause_reg[5] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_mstatus_mpp_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mcountinhibit_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mie_reg[0] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/\s1_pc_reg[0] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_mem_cmd_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_sel_alu2_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/s2_tlb_resp_cacheable_reg)
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[5] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[7] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[7] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[8] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[8] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[12] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[22] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[22] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[23] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[23] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[46] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[46] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[47] )
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_addr_reg' and it is trimmed from '34' to '32' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:408]
-WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[3] driven by constant 0
-WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[2] driven by constant 0
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-WARNING: [Synth 8-6841] Block RAM (rockettile_dcache_data_arrays_0_ext/Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 4. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:129]
-DSP Report: Generating DSP freq_word0, operation Mode is: (A:0x6677)*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: A*(B:0x6677).
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x109).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x55).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult20, operation Mode is: A*(B:0x75).
-DSP Report: operator mult20 is absorbed into DSP mult20.
-INFO: [Synth 8-5544] ROM "cordic_angle_lut_i/angle_o" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
-INFO: [Synth 8-4471] merging register 'prompt_abs_vld_reg' into 'cos2x_i/sqr_vld_reg' [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:107]
-DSP Report: Generating DSP cos2x_i/q_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: Generating DSP cos2x_i/i_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[15]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[14]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[13]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[12]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[11]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[10]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[9]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[8]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[7]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[6]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[5]__1) is unused and will be removed from module NCO_carr.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 16. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:202]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 12. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:212]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 12. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:213]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 8. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:160]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 4. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_core.sv:153]
-DSP Report: Generating DSP phase_wide2, operation Mode is: A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: PCIN+A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: PCIN+A*(B:0x0).
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: PCIN+A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: PCIN+A*(B:0x0).
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: PCIN+A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: A*(B:0x0).
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: PCIN+A*(B:0x0).
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP phase_wide2, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: operator phase_wide2 is absorbed into DSP phase_wide2.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP rate_word_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: operator rate_word_q32_n4 is absorbed into DSP rate_word_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP integrator_q32_n4, operation Mode is: PCIN+A*B.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: operator integrator_q32_n4 is absorbed into DSP integrator_q32_n4.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: A*B.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: A*B.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: PCIN+A*B.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: A*B.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: PCIN+A*B.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: (A:0x15940)*B.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: A*(B:0x15940).
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: Generating DSP reference_seconds3, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-DSP Report: operator reference_seconds3 is absorbed into DSP reference_seconds3.
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w0, operation Mode is: C+A*B.
-DSP Report: operator butterfly_i/x1_imag_w0 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w0, operation Mode is: C-A*B.
-DSP Report: operator butterfly_i/x1_real_w0 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP bd, operation Mode is: A*B.
-DSP Report: operator bd is absorbed into DSP bd.
-DSP Report: Generating DSP ac, operation Mode is: A*B.
-DSP Report: operator ac is absorbed into DSP ac.
-DSP Report: Generating DSP ad, operation Mode is: A*B.
-DSP Report: operator ad is absorbed into DSP ad.
-DSP Report: Generating DSP bc, operation Mode is: A*B.
-DSP Report: operator bc is absorbed into DSP bc.
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-WARNING: [Synth 8-3917] design APBGpsBlock__GCB1 has port _acq_sample_counter_clear driven by constant 0
-INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM acq/i_acq_top/dual_port_ram_i/ram_reg to conserve power
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_IQ_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_code_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /ifft_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-4652] Swapped enable and write-enable on 26 RAM instances of RAM bram_i/ram_reg to conserve power
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:21 ; elapsed = 00:01:43 . Memory (MB): peak = 3023.973 ; gain = 1204.242 ; free physical = 250 ; free virtual = 11311
----------------------------------------------------------------------------------
- Sort Area is APBGpsBlock__GCB1 p_1_out_0 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_2 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_3 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GCB1 p_1_out_4 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 0 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 1 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 2 : 2812 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 3 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 0 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 1 : 2793 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 2 : 2812 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 3 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 0 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 1 : 2812 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 2 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 3 : 2691 11089 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 0 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 1 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 2 : 3255 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 0 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 1 : 3101 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 2 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 0 : 3101 9322 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 1 : 3120 9322 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 2 : 3101 9322 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_14 : 0 0 : 2460 8662 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_14 : 0 1 : 3101 8662 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_14 : 0 2 : 3101 8662 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_1a : 0 0 : 2460 8662 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_1a : 0 1 : 3101 8662 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_1a : 0 2 : 3101 8662 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_f : 0 0 : 2460 8072 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_f : 0 1 : 1642 8072 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_f : 0 2 : 2460 8072 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_f : 0 3 : 1510 8072 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_13 : 0 0 : 1313 7534 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_13 : 0 1 : 3120 7534 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_13 : 0 2 : 3101 7534 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_19 : 0 0 : 1313 7534 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_19 : 0 1 : 3120 7534 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_19 : 0 2 : 3101 7534 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_15 : 0 0 : 2460 7397 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_15 : 0 1 : 3101 7397 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_15 : 0 2 : 1836 7397 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_1b : 0 0 : 2460 7397 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_1b : 0 1 : 3101 7397 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_1b : 0 2 : 1836 7397 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_1d : 0 0 : 1313 7192 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_1d : 0 1 : 3120 7192 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_1d : 0 2 : 2759 7192 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_1f : 0 0 : 1313 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_1f : 0 1 : 2759 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_1f : 0 2 : 2479 6551 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_6 : 0 0 : 0 6383 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_6 : 0 1 : 3120 6383 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_6 : 0 2 : 143 6383 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_6 : 0 3 : 3120 6383 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_a : 0 0 : 1313 6199 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_a : 0 1 : 143 6199 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_a : 0 2 : 1642 6199 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_a : 0 3 : 3101 6199 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_d : 0 0 : 1313 6199 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_d : 0 1 : 143 6199 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_d : 0 2 : 1642 6199 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 phase_wide2_d : 0 3 : 3101 6199 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_17 : 0 0 : 2460 5791 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_17 : 0 1 : 1836 5791 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 integrator_q32_n4_17 : 0 2 : 1495 5791 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_1c : 0 0 : 2460 5791 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_1c : 0 1 : 1836 5791 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 rate_word_q32_n4_1c : 0 2 : 1495 5791 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 im_sqr0_26 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 im_sqr0_26 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 re_sqr0_23 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 re_sqr0_23 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 0 : 3446 4760 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 1 : 1314 4760 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1e : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1e : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_20 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_20 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_18 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_18 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1c : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1c : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_21 : 0 0 : 1315 3694 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_21 : 0 1 : 2379 3694 : Used 1 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 0 : 1789 3431 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 1 : 1642 3431 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_0 : 0 0 : 1313 3313 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_0 : 0 1 : 2000 3313 : Used 1 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 0 : 1785 3295 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 1 : 1510 3295 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_3 : 0 0 : 1315 3237 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB0 reference_seconds3_3 : 0 1 : 1922 3237 : Used 1 time 0
- Sort Area is tracking_wrapper cos2x_i/i_p_sqr0_b : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is tracking_wrapper cos2x_i/q_p_sqr0_d : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is APBGpsBlock__GCB1 ac_12 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 ad_16 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 bc_15 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 bd_14 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w0_c : 0 0 : 2196 2196 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w0_f : 0 0 : 2073 2073 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_e : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_a : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_1f : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_imag_w1_21 : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1a : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 butterfly_i/x1_real_w1_1d : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_17 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_5 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 port1_addr0_9 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_11 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_22 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GCB1 k0_7 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is tracking_wrapper mult10_6 : 0 0 : 433 433 : Used 9 time 0
- Sort Area is tracking_wrapper mult10_a : 0 0 : 403 403 : Used 9 time 0
- Sort Area is tracking_wrapper mult20_8 : 0 0 : 403 403 : Used 9 time 0
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-ROM: Preliminary Mapping Report
-+----------------+----------------------+---------------+----------------+
-|Module Name | RTL Object | Depth x Width | Implemented As |
-+----------------+----------------------+---------------+----------------+
-|TLROM | _GEN | 256x64 | LUT |
-|acq_nco_carr | freq_word_arr | 64x13 | LUT |
-|acq_nco_carr | pullin_freq_word_arr | 16x11 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_ca_gen | p_0_out | 32x8 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|cacode_gen_trck | p_0_out | 32x8 | LUT |
-+----------------+----------------------+---------------+----------------+
-
-
-Block RAM: Preliminary Mapping Report (see note below)
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GCB1 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
-
-Distributed RAM: Preliminary Mapping Report (see note below)
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
-Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
-
-DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | (PCIN>>17)+A*B | 25 | 8 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 16 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|NCO_carr | (A:0x6677)*B | 14 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 14 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | A*(B:0x6677) | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 18 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | A*(B:0x109) | 12 | 10 | - | - | 22 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x55) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x75) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 14 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*(B:0x0) | 14 | 2 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*(B:0x0) | 18 | 2 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*(B:0x0) | 18 | 2 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*(B:0x0) | 18 | 2 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 14 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 14 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 16 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (A:0x15940)*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 16 | 11 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*(B:0x15940) | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | (PCIN>>17)+A*B | 18 | 11 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:34 ; elapsed = 00:01:53 . Memory (MB): peak = 3023.973 ; gain = 1204.242 ; free physical = 2456 ; free virtual = 13568
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:03:47 ; elapsed = 00:02:07 . Memory (MB): peak = 3138.809 ; gain = 1319.078 ; free physical = 2314 ; free virtual = 13429
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Block RAM: Final Mapping Report
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GCB1 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-
-Distributed RAM: Final Mapping Report
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:61]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:74]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:66]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:66]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv:100]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:147]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:148]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:145]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:145]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:145]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/pps/pps_wrapper.sv:145]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:78]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:79]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:301]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:301]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:301]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:03:55 ; elapsed = 00:02:19 . Memory (MB): peak = 3150.734 ; gain = 1331.004 ; free physical = 813 ; free virtual = 11931
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:04:04 ; elapsed = 00:02:30 . Memory (MB): peak = 3208.984 ; gain = 1389.254 ; free physical = 716 ; free virtual = 11886
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:04:05 ; elapsed = 00:02:30 . Memory (MB): peak = 3208.984 ; gain = 1389.254 ; free physical = 717 ; free virtual = 11886
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:04:16 ; elapsed = 00:02:42 . Memory (MB): peak = 3395.492 ; gain = 1575.762 ; free physical = 526 ; free virtual = 11695
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:04:17 ; elapsed = 00:02:42 . Memory (MB): peak = 3395.492 ; gain = 1575.762 ; free physical = 525 ; free virtual = 11694
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:04:18 ; elapsed = 00:02:44 . Memory (MB): peak = 3406.398 ; gain = 1586.668 ; free physical = 524 ; free virtual = 11693
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:04:18 ; elapsed = 00:02:44 . Memory (MB): peak = 3406.398 ; gain = 1586.668 ; free physical = 525 ; free virtual = 11694
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Static Shift Register Report:
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|VCU118RocketSystem | tile_prci_domain/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-|VCU118RocketSystem | ibus/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-DSP Final Report (the ' indicates corresponding REG is set)
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-(A*B) | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 0 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 16 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 30 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 0 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 30 | 0 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 0 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 0 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 0 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 0 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 0 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 15 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN+A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 15 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|pps_core | PCIN>>17+A*B | 17 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 15 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 15 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN>>17+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B' | 24 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | PCIN>>17+A*B | 24 | 7 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-
-Report BlackBoxes:
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage:
-+------+-----------+------+
-| |Cell |Count |
-+------+-----------+------+
-|1 |BSCANE2 | 1|
-|2 |BUFG | 6|
-|3 |CARRY4 | 5957|
-|4 |DSP48E1 | 224|
-|11 |LUT1 | 2821|
-|12 |LUT2 | 14747|
-|13 |LUT3 | 10448|
-|14 |LUT4 | 7894|
-|15 |LUT5 | 12308|
-|16 |LUT6 | 24652|
-|17 |MMCME2_ADV | 1|
-|18 |MUXF7 | 1797|
-|19 |MUXF8 | 142|
-|20 |RAM32M | 225|
-|21 |RAM32X1D | 5|
-|22 |RAMB18E1 | 4|
-|24 |RAMB36E1 | 415|
-|46 |SRL16E | 2|
-|47 |STARTUPE2 | 1|
-|48 |FDCE | 29614|
-|49 |FDPE | 360|
-|50 |FDRE | 10101|
-|51 |FDSE | 130|
-|52 |LDC | 9|
-|53 |IBUF | 8|
-|54 |IBUFDS | 1|
-|55 |IOBUF | 8|
-|56 |OBUF | 13|
-+------+-----------+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:04:18 ; elapsed = 00:02:44 . Memory (MB): peak = 3406.398 ; gain = 1586.668 ; free physical = 524 ; free virtual = 11694
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 544 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:04:08 ; elapsed = 00:02:39 . Memory (MB): peak = 3410.312 ; gain = 1293.520 ; free physical = 7450 ; free virtual = 18620
-Synthesis Optimization Complete : Time (s): cpu = 00:04:19 ; elapsed = 00:02:47 . Memory (MB): peak = 3410.312 ; gain = 1590.582 ; free physical = 7468 ; free virtual = 18627
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.79 . Memory (MB): peak = 3410.312 ; gain = 0.000 ; free physical = 7485 ; free virtual = 18645
-INFO: [Netlist 29-17] Analyzing 8789 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3591.688 ; gain = 0.000 ; free physical = 7382 ; free virtual = 18541
-INFO: [Project 1-111] Unisim Transformation Summary:
- A total of 247 instances were transformed.
- IOBUF => IOBUF (IBUF, OBUFT): 8 instances
- LDC => LDCE: 9 instances
- RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 225 instances
- RAM32X1D => RAM32X1D (RAMD32(x2)): 5 instances
-
-Synth Design complete | Checksum: 9720915c
-INFO: [Common 17-83] Releasing license: Synthesis
-688 Infos, 394 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:04:38 ; elapsed = 00:03:07 . Memory (MB): peak = 3591.723 ; gain = 1975.594 ; free physical = 7386 ; free virtual = 18545
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 10066.001; main = 2859.157; forked = 8215.155
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19259.895; main = 3591.691; forked = 16239.836
-# apply_genesys2_async_clock_groups
-Applying Genesys2 async clock groups.
-# write_checkpoint -force [file join $checkpoint_dir post_synth.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3623.703 ; gain = 0.000 ; free physical = 7401 ; free virtual = 18559
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3623.703 ; gain = 0.000 ; free physical = 7401 ; free virtual = 18559
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3623.703 ; gain = 0.000 ; free physical = 7399 ; free virtual = 18558
-Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3623.703 ; gain = 0.000 ; free physical = 7399 ; free virtual = 18558
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3623.703 ; gain = 0.000 ; free physical = 7399 ; free virtual = 18558
-Wrote Device Cache: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3623.703 ; gain = 0.000 ; free physical = 7399 ; free virtual = 18559
-Write Physdb Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3623.703 ; gain = 0.000 ; free physical = 7399 ; free virtual = 18559
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.25 . Memory (MB): peak = 3623.703 ; gain = 0.000 ; free physical = 7378 ; free virtual = 18558
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_synth.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 3623.703 ; gain = 31.980 ; free physical = 7255 ; free virtual = 18469
-# report_utilization -hierarchical -file [file join $report_dir synth_utilization_hier.rpt]
-# report_utilization -file [file join $report_dir synth_utilization.rpt]
-# report_timing_summary -file [file join $report_dir synth_timing_summary.rpt]
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs
-report_timing_summary: Time (s): cpu = 00:00:39 ; elapsed = 00:00:09 . Memory (MB): peak = 3623.703 ; gain = 0.000 ; free physical = 7313 ; free virtual = 18527
-# puts "Running implementation..."
-Running implementation...
-# opt_design
-Command: opt_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-Running DRC as a precondition to command opt_design
-
-Starting DRC Task
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Project 1-461] DRC finished with 0 Errors
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.65 . Memory (MB): peak = 3710.336 ; gain = 86.633 ; free physical = 7313 ; free virtual = 18527
-
-Starting Cache Timing Information Task
-Ending Cache Timing Information Task | Checksum: 179df0050
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7313 ; free virtual = 18527
-
-Starting Logic Optimization Task
-
-Phase 1 Initialization
-
-Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 179df0050
-
-Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7283 ; free virtual = 18498
-
-Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 179df0050
-
-Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7283 ; free virtual = 18498
-Phase 1 Initialization | Checksum: 179df0050
-
-Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7283 ; free virtual = 18498
-
-Phase 2 Timer Update And Timing Data Collection
-
-Phase 2.1 Detect if minReqCache needed
-Phase 2.1 Detect if minReqCache needed | Checksum: 179df0050
-
-Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7259 ; free virtual = 18474
-
-Phase 2.2 Timer Update
-Phase 2.2 Timer Update | Checksum: 179df0050
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7259 ; free virtual = 18474
-
-Phase 2.3 Timing Data Collection
-Phase 2.3 Timing Data Collection | Checksum: 179df0050
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7259 ; free virtual = 18474
-Phase 2 Timer Update And Timing Data Collection | Checksum: 179df0050
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7259 ; free virtual = 18474
-
-Phase 3 Retarget
-INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
-INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
-INFO: [Opt 31-1566] Pulled 28 inverters resulting in an inversion of 507 pins
-INFO: [Opt 31-138] Pushed 14 inverter(s) to 129 load pin(s).
-INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 148655b65
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7260 ; free virtual = 18475
-Retarget | Checksum: 148655b65
-INFO: [Opt 31-389] Phase Retarget created 474 cells and removed 517 cells
-INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 4 Constant propagation
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 1249be888
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7261 ; free virtual = 18476
-Constant propagation | Checksum: 1249be888
-INFO: [Opt 31-389] Phase Constant propagation created 1 cells and removed 1 cells
-
-Phase 5 Sweep
-INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
-Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7262 ; free virtual = 18477
-Phase 5 Sweep | Checksum: 16bb147ce
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7262 ; free virtual = 18477
-Sweep | Checksum: 16bb147ce
-INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 5 cells
-INFO: [Opt 31-1021] In phase Sweep, 360 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 6 BUFG optimization
-Phase 6 BUFG optimization | Checksum: 16bb147ce
-
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7271 ; free virtual = 18486
-BUFG optimization | Checksum: 16bb147ce
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
-
-Phase 7 Shift Register Optimization
-INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 16bb147ce
-
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7271 ; free virtual = 18486
-Shift Register Optimization | Checksum: 16bb147ce
-INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
-
-Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 16bb147ce
-
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7271 ; free virtual = 18486
-Post Processing Netlist | Checksum: 16bb147ce
-INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
-
-Phase 9 Finalization
-
-Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 17b359fac
-
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7271 ; free virtual = 18486
-
-Phase 9.2 Verifying Netlist Connectivity
-
-Starting Connectivity Check Task
-
-Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7271 ; free virtual = 18486
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 17b359fac
-
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7271 ; free virtual = 18486
-Phase 9 Finalization | Checksum: 17b359fac
-
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7271 ; free virtual = 18486
-Opt_design Change Summary
-=========================
-
-
--------------------------------------------------------------------------------------------------------------------------
-| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
--------------------------------------------------------------------------------------------------------------------------
-| Retarget | 474 | 517 | 1 |
-| Constant propagation | 1 | 1 | 0 |
-| Sweep | 0 | 5 | 360 |
-| BUFG optimization | 0 | 0 | 0 |
-| Shift Register Optimization | 0 | 0 | 0 |
-| Post Processing Netlist | 0 | 0 | 0 |
--------------------------------------------------------------------------------------------------------------------------
-
-
-Ending Logic Optimization Task | Checksum: 17b359fac
-
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 3710.336 ; gain = 0.000 ; free physical = 7271 ; free virtual = 18486
-
-Starting Power Optimization Task
-INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-INFO: [Power 33-23] Power model is not available for u_cfg_flash_startup
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running Vector-less Activity Propagation...
-
-Finished Running Vector-less Activity Propagation
-INFO: [Pwropt 34-9] Applying IDT optimizations ...
-INFO: [Pwropt 34-10] Applying ODC optimizations ...
-
-
-Starting PowerOpt Patch Enables Task
-INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 419 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
-INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
-Number of BRAM Ports augmented: 0 newly gated: 84 Total Ports: 838
-Ending PowerOpt Patch Enables Task | Checksum: 149fb999b
-
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6778 ; free virtual = 17997
-Ending Power Optimization Task | Checksum: 149fb999b
-
-Time (s): cpu = 00:00:38 ; elapsed = 00:00:22 . Memory (MB): peak = 4349.227 ; gain = 638.891 ; free physical = 6778 ; free virtual = 17997
-
-Starting Final Cleanup Task
-
-Starting Logic Optimization Task
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Logic Optimization Task | Checksum: 152661ca0
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:04 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6769 ; free virtual = 17988
-Ending Final Cleanup Task | Checksum: 152661ca0
-
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:06 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6769 ; free virtual = 17988
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6769 ; free virtual = 17988
-INFO: [Common 17-83] Releasing license: Implementation
-29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-opt_design completed successfully
-opt_design: Time (s): cpu = 00:01:07 ; elapsed = 00:00:38 . Memory (MB): peak = 4349.227 ; gain = 725.523 ; free physical = 6769 ; free virtual = 17988
-# write_checkpoint -force [file join $checkpoint_dir post_opt.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6769 ; free virtual = 17988
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6769 ; free virtual = 17988
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6769 ; free virtual = 17988
-Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6769 ; free virtual = 17988
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6769 ; free virtual = 17988
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6769 ; free virtual = 17989
-Write Physdb Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6769 ; free virtual = 17989
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.12 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6749 ; free virtual = 17981
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_opt.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6653 ; free virtual = 17920
-# place_design
-Command: place_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-83] Releasing license: Implementation
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running DRC as a precondition to command place_design
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 12 CPUs
-
-Starting Placer Task
-
-Phase 1 Placer Initialization
-
-Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6687 ; free virtual = 17954
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14f95da54
-
-Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6687 ; free virtual = 17954
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6687 ; free virtual = 17954
-
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 18fa6d7d0
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6697 ; free virtual = 17969
-
-Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 28b94529c
-
-Time (s): cpu = 00:00:51 ; elapsed = 00:00:18 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6731 ; free virtual = 18002
-
-Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 28b94529c
-
-Time (s): cpu = 00:00:51 ; elapsed = 00:00:18 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6731 ; free virtual = 18002
-Phase 1 Placer Initialization | Checksum: 28b94529c
-
-Time (s): cpu = 00:00:51 ; elapsed = 00:00:18 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6731 ; free virtual = 18003
-
-Phase 2 Global Placement
-
-Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 27b6f0b5f
-
-Time (s): cpu = 00:01:22 ; elapsed = 00:00:27 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6765 ; free virtual = 18038
-
-Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 25498f93e
-
-Time (s): cpu = 00:01:50 ; elapsed = 00:00:34 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6762 ; free virtual = 18035
-
-Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 1f68fae57
-
-Time (s): cpu = 00:01:50 ; elapsed = 00:00:34 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6762 ; free virtual = 18035
-
-Phase 2.4 Global Place Phase1
-Phase 2.4 Global Place Phase1 | Checksum: 1f190a9b9
-
-Time (s): cpu = 00:03:38 ; elapsed = 00:01:14 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 7123 ; free virtual = 18396
-
-Phase 2.5 Global Place Phase2
-
-Phase 2.5.1 UpdateTiming Before Physical Synthesis
-Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 28c53ca0c
-
-Time (s): cpu = 00:04:09 ; elapsed = 00:01:21 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 7028 ; free virtual = 18302
-
-Phase 2.5.2 Physical Synthesis In Placer
-INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 3866 LUT instances to create LUTNM shape
-INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
-INFO: [Physopt 32-1138] End 1 Pass. Optimized 1026 nets or LUTs. Breaked 0 LUT, combined 1026 existing LUTs and moved 0 existing LUT
-INFO: [Physopt 32-65] No nets found for high-fanout optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
-INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
-INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
-INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 7002 ; free virtual = 18277
-
-Summary of Physical Synthesis Optimizations
-============================================
-
-
------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
------------------------------------------------------------------------------------------------------------------------------------------------------------
-| LUT Combining | 0 | 1026 | 1026 | 0 | 1 | 00:00:02 |
-| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Total | 0 | 1026 | 1026 | 0 | 9 | 00:00:02 |
------------------------------------------------------------------------------------------------------------------------------------------------------------
-
-
-Phase 2.5.2 Physical Synthesis In Placer | Checksum: 1641a8b70
-
-Time (s): cpu = 00:04:40 ; elapsed = 00:01:32 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 7017 ; free virtual = 18293
-Phase 2.5 Global Place Phase2 | Checksum: 12473b1fc
-
-Time (s): cpu = 00:04:45 ; elapsed = 00:01:35 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 7017 ; free virtual = 18292
-Phase 2 Global Placement | Checksum: 12473b1fc
-
-Time (s): cpu = 00:04:45 ; elapsed = 00:01:35 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 7017 ; free virtual = 18292
-
-Phase 3 Detail Placement
-
-Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 14c050255
-
-Time (s): cpu = 00:05:13 ; elapsed = 00:01:42 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 7018 ; free virtual = 18293
-
-Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: de286b2e
-
-Time (s): cpu = 00:06:04 ; elapsed = 00:01:56 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 7016 ; free virtual = 18292
-
-Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 13859bc09
-
-Time (s): cpu = 00:06:05 ; elapsed = 00:01:56 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 7016 ; free virtual = 18293
-
-Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: affcac99
-
-Time (s): cpu = 00:06:05 ; elapsed = 00:01:57 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 7016 ; free virtual = 18293
-
-Phase 3.5 Fast Optimization
-Phase 3.5 Fast Optimization | Checksum: 11d1b3189
-
-Time (s): cpu = 00:07:02 ; elapsed = 00:02:14 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 7021 ; free virtual = 18297
-
-Phase 3.6 Small Shape Detail Placement
-Phase 3.6 Small Shape Detail Placement | Checksum: fe814ede
-
-Time (s): cpu = 00:07:27 ; elapsed = 00:02:45 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6989 ; free virtual = 18265
-
-Phase 3.7 Re-assign LUT pins
-Phase 3.7 Re-assign LUT pins | Checksum: 1256d5963
-
-Time (s): cpu = 00:07:31 ; elapsed = 00:02:48 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6989 ; free virtual = 18265
-
-Phase 3.8 Pipeline Register Optimization
-Phase 3.8 Pipeline Register Optimization | Checksum: cd9f0661
-
-Time (s): cpu = 00:07:32 ; elapsed = 00:02:49 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6989 ; free virtual = 18265
-
-Phase 3.9 Fast Optimization
-Phase 3.9 Fast Optimization | Checksum: 1a3666af5
-
-Time (s): cpu = 00:08:42 ; elapsed = 00:03:08 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6884 ; free virtual = 18161
-Phase 3 Detail Placement | Checksum: 1a3666af5
-
-Time (s): cpu = 00:08:42 ; elapsed = 00:03:08 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6885 ; free virtual = 18161
-
-Phase 4 Post Placement Optimization and Clean-Up
-
-Phase 4.1 Post Commit Optimization
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-
-Phase 4.1.1 Post Placement Optimization
-Post Placement Optimization Initialization | Checksum: 22c674c7f
-
-Phase 4.1.1.1 BUFG Insertion
-
-Starting Physical Synthesis Task
-
-Phase 1 Physical Synthesis Initialization
-INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 12 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.849 | TNS=-5820.906 |
-Phase 1 Physical Synthesis Initialization | Checksum: 1781cd5b1
-
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.77 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6847 ; free virtual = 18123
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/apbReset_gps_apb_reset/io_sync_reset_chain/output_chain/sync_0_reg_1, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_1, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-56] BUFG insertion identified 10 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 10, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
-Ending Physical Synthesis Task | Checksum: 17c7019b5
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6847 ; free virtual = 18123
-Phase 4.1.1.1 BUFG Insertion | Checksum: 22c674c7f
-
-Time (s): cpu = 00:09:35 ; elapsed = 00:03:21 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6848 ; free virtual = 18124
-
-Phase 4.1.1.2 Post Placement Timing Optimization
-INFO: [Place 30-746] Post Placement Timing Summary WNS=-33.428. For the most accurate timing information please run report_timing.
-Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1e592d8f3
-
-Time (s): cpu = 00:11:11 ; elapsed = 00:04:08 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-
-Time (s): cpu = 00:11:11 ; elapsed = 00:04:08 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-Phase 4.1 Post Commit Optimization | Checksum: 1e592d8f3
-
-Time (s): cpu = 00:11:12 ; elapsed = 00:04:08 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-
-Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 1e592d8f3
-
-Time (s): cpu = 00:11:13 ; elapsed = 00:04:08 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-
-Phase 4.3 Placer Reporting
-
-Phase 4.3.1 Print Estimated Congestion
-INFO: [Place 30-612] Post-Placement Estimated Congestion
- ____________________________________________________
-| | Global Congestion | Short Congestion |
-| Direction | Region Size | Region Size |
-|___________|___________________|___________________|
-| North| 2x2| 2x2|
-|___________|___________________|___________________|
-| South| 1x1| 8x8|
-|___________|___________________|___________________|
-| East| 1x1| 2x2|
-|___________|___________________|___________________|
-| West| 2x2| 4x4|
-|___________|___________________|___________________|
-
-Phase 4.3.1 Print Estimated Congestion | Checksum: 1e592d8f3
-
-Time (s): cpu = 00:11:13 ; elapsed = 00:04:08 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-Phase 4.3 Placer Reporting | Checksum: 1e592d8f3
-
-Time (s): cpu = 00:11:14 ; elapsed = 00:04:08 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-
-Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-
-Time (s): cpu = 00:11:14 ; elapsed = 00:04:09 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c9d751ae
-
-Time (s): cpu = 00:11:14 ; elapsed = 00:04:09 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-Ending Placer Task | Checksum: 15e841f6d
-
-Time (s): cpu = 00:11:14 ; elapsed = 00:04:09 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-47 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-place_design completed successfully
-place_design: Time (s): cpu = 00:11:25 ; elapsed = 00:04:13 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-# write_checkpoint -force [file join $checkpoint_dir post_place.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18119
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6843 ; free virtual = 18120
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.16 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18116
-Wrote PlaceStorage: Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6723 ; free virtual = 18112
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6707 ; free virtual = 18105
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6707 ; free virtual = 18106
-Write Physdb Complete: Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6707 ; free virtual = 18106
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_place.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6637 ; free virtual = 17981
-# phys_opt_design -directive Explore
-Command: phys_opt_design -directive Explore
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
-
-Starting Initial Update Timing Task
-
-Time (s): cpu = 00:00:41 ; elapsed = 00:00:09 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6742 ; free virtual = 18086
-INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 45.60s | WALL: 9.31s
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6742 ; free virtual = 18086
-
-Starting Physical Synthesis Task
-
-Phase 1 Physical Synthesis Initialization
-INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 12 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.428 | TNS=-5734.079 |
-Phase 1 Physical Synthesis Initialization | Checksum: 1396ef9a5
-
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6750 ; free virtual = 18094
-
-Phase 2 SLR Crossing Optimization
-Phase 2 SLR Crossing Optimization | Checksum: 1396ef9a5
-
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6750 ; free virtual = 18094
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.428 | TNS=-5734.079 |
-
-Phase 3 Fanout Optimization
-INFO: [Physopt 32-76] Pass 1. Identified 3 candidate nets for fanout optimization.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__15[64]. Replicated 1 times.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/aligned_p_reg_rep_n_0. Replicated 9 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[63] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-232] Optimized 2 nets. Created 10 new instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 10 new cells, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.421 | TNS=-5732.722 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6746 ; free virtual = 18090
-Phase 3 Fanout Optimization | Checksum: 121a9deff
-
-Time (s): cpu = 00:00:55 ; elapsed = 00:00:20 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6746 ; free virtual = 18090
-
-Phase 4 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__15[64]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2_i_1_replica
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[6]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[32]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[32]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_320_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_320
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[48]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[31]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[31]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_20_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_20
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_7_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_45_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_45
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_35_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_35
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_243_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_243
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_324_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_324
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_83_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_83
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_8_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_115_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_115
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_100_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_100
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_107_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_107
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_59_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_59
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[37]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[37]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[37]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[37]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[35]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[36]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[36]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_116_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_116
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_36_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_36
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[5]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_24_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_24
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_21_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_21
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_limited_wide[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_113_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_113
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_193_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_193
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_240_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_240
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_245_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_245
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_105_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_105
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_96_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_96
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_112_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_112
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[34]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_32_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_32
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_112_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_112
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_19_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_19
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_106_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_106
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_79_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_79
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[14]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[14]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[14]_i_1_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[14]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[39]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[39]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[12]_i_1_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[12]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[40]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[8]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_102_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_102
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[38]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[38]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_111_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_111
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_16
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_80_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_80
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_111_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_111
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_31_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_31
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_125_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_125
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[44]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_79_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_79
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[11]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_122_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_122
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_195_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_195
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_242_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_242
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_247_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_247
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_130_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_130
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_113_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_113
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_17
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_20_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_20
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_46_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_46
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_121_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_121
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[49]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_248_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_248
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[15]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[47]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_81_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_81
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[13]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_23
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_saturated_n4_out. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_saturated_p_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_saturated_p_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_saturated_p_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/D[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_saturated_p_reg
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_22_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_22
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_132_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_132
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_107_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_107
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_118_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_118
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[50]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[46]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[9]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[9]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[15]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[15]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_137_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_137
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[15]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[15]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_109_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_109
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_124_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_124
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_194_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_194
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_241_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_241
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_246_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_246
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[13]_i_1_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[13]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_103_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_103
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[10]_i_1_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[10]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_312_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_312
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_316_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_316
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[33]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[33]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[43]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[43]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_126_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_126
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_188_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_188
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[43]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[43]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_102_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_102
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[16]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_98_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_98
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[49]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[49]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[49]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[49]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_19_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_19
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[50]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[50]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[50]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[50]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_27_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_27
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_18_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_18
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_77_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_77
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[39]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[39]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_44_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_44
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_58_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_58
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_100_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_100
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_143_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_143
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[16]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[16]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_28_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_28
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[16]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[16]_i_1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_166_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_166
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_9_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_77_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_77
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[5]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[40]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_196_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_196
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[5]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[5]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_92_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_92
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_134_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_134
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_140_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_140
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_139_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_139
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[41]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[41]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_34_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_34
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_128_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_128
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_190_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_190
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[41]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[41]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_11_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[42]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[42]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[42]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[42]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[44]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[44]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_45_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_45
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[44]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[44]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_78_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_78
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[14]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_3
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_54_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_54
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_24_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_24
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_33_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_33
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_120_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_120
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_110_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_110
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_119_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_119
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_109_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_109
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_373_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_373
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_105_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_105
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_93_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_93
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[43]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_96_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_96
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_104_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_104
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_180_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_180
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_130_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_130
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_13_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_136_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_136
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[20]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_14
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_10_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_19_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_19
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[46]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[46]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_23
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[46]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[46]_i_1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_11_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_89_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_89
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_300_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_300
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[37]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_18
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_5
-INFO: [Physopt 32-661] Optimized 18 nets. Re-placed 18 instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 18 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 18 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.379 | TNS=-5723.197 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6695 ; free virtual = 18041
-Phase 4 Single Cell Placement Optimization | Checksum: 143b666cc
-
-Time (s): cpu = 00:04:59 ; elapsed = 00:01:12 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6695 ; free virtual = 18041
-
-Phase 5 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1/O
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[37]_i_1_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[37]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1/O
-INFO: [Physopt 32-661] Optimized 1 net. Re-placed 2 instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 0 new cell, deleted 0 existing cell and moved 2 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.379 | TNS=-5723.147 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6693 ; free virtual = 18038
-Phase 5 Multi Cell Placement Optimization | Checksum: 1d1bf15ad
-
-Time (s): cpu = 00:05:22 ; elapsed = 00:01:17 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6693 ; free virtual = 18038
-
-Phase 6 Rewire
-INFO: [Physopt 32-246] Starting Signal Push optimization...
-INFO: [Physopt 32-77] Pass 1. Identified 1 candidate net for rewire optimization.
-INFO: [Physopt 32-134] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_610_n_0. Rewiring did not optimize the net.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6670 ; free virtual = 18015
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6670 ; free virtual = 18015
-Phase 6 Rewire | Checksum: 131755aaa
-
-Time (s): cpu = 00:05:23 ; elapsed = 00:01:18 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6679 ; free virtual = 18024
-
-Phase 7 Critical Cell Optimization
-INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__15[64]_repN. Replicated 1 times.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[6]. Replicated 2 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[32] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-571] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_320_n_0 was not replicated.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[48]. Replicated 1 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[31] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[5]. Replicated 4 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[35] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[36] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[1]. Replicated 2 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[34] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[11]. Replicated 4 times.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[8]. Replicated 1 times.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[2]. Replicated 4 times.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[0]. Replicated 2 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[39] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[40] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[15]. Replicated 4 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[38] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[10]. Replicated 2 times.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[4]. Replicated 4 times.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[12]. Replicated 2 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[44] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[49] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[9] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[47]. Replicated 1 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[16] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[12] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[14] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[37] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-232] Optimized 14 nets. Created 34 new instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 14 nets or cells. Created 34 new cells, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.330 | TNS=-5716.007 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6699 ; free virtual = 18044
-Phase 7 Critical Cell Optimization | Checksum: e7e2c321
-
-Time (s): cpu = 00:09:32 ; elapsed = 00:02:38 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6699 ; free virtual = 18044
-
-Phase 8 Fanout Optimization
-INFO: [Physopt 32-76] Pass 1. Identified 1 candidate net for fanout optimization.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[63] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6699 ; free virtual = 18044
-Phase 8 Fanout Optimization | Checksum: 1050c02d7
-
-Time (s): cpu = 00:09:33 ; elapsed = 00:02:38 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6699 ; free virtual = 18044
-
-Phase 9 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization.
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__15[64]_repN_1. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2_i_1_replica_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[32]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[32]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_320_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_320
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[31]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[31]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_20_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_20
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_45_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_45
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[8]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_9_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_35_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_35
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_243_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_243
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_324_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_324
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_83_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_83
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_8_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_115_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_115
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[48]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[6]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_11_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_102_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_102
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_17
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_79_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_79
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_100_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_100
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_107_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_107
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_59_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_59
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[35]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[36]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[36]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[15]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_2_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_116_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_116
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_36_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_36
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_24_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_24
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[16]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_21_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_21
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_limited_wide[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_80_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_80
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_113_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_113
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_193_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_193
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_240_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_240
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_245_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_245
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_105_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_105
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_96_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_96
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_112_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_112
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[34]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_32_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_32
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_112_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_112
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[2]_repN. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_15_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_19_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_19
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_106_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_106
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[0]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_17_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[39]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[39]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[40]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[38]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[38]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_111_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_111
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_111_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_111
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[11]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_6_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_31_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_31
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_125_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_125
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_79_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_79
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[44]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_98_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_98
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[14]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_122_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_122
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_195_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_195
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_242_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_242
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_247_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_247
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[5]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_12_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_130_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_130
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[1]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_16_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_113_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_113
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[49]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_20_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_20
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_23
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_22_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_22
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_46_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_46
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_121_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_121
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_100_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_100
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_137_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_137
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_248_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_248
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[47]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_81_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_81
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[50]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[12]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[12]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[14]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[14]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[46]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[37]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[37]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_44_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_44
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_132_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_132
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[14]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[14]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[37]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[37]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_107_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_107
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_118_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_118
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[2]_repN_1. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_15_replica_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[9]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[9]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[15]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[15]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[15]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[15]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_109_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_109
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_124_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_124
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_77_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_77
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_194_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_194
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_241_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_241
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_246_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_246
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_103_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_103
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_312_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_312
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_316_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_316
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[33]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[33]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[43]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[43]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_19_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_19
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_126_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_126
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_188_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_188
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[43]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[43]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_102_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_102
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[10]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[10]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[13]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[13]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_18_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_18
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[49]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[49]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_45_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_45
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[49]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[49]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_78_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_78
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_96_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_96
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[50]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[50]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[50]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[50]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_27_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_27
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_77_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_77
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[39]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[39]_i_1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[23]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_11
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_11_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_11
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_10_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_11_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_166_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_166
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_15
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_10_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_180_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_180
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_58_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_58
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_143_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_143
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[16]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[16]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[11]_repN_1. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_6_replica_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_28_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_28
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[16]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[16]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_9_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[20]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[7]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[5]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[5]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_23
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_196_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_196
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[5]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[5]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_92_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_92
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_134_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_134
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_140_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_140
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_139_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_139
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[27]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[41]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[41]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_34_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_34
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_128_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_128
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_190_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_190
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[41]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[41]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[42]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[42]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[42]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[42]_i_1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_8_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[44]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[44]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_41_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_41
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[44]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[44]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_24_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_24
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_33_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_33
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_120_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_120
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_110_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_110
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_119_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_119
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[43]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_109_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_109
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_373_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_373
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_29_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_29
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_5
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/raw_counter[2]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/raw_counter_p_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[39]_i_16_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[39]_i_16
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[51]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[51]_i_7
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_167_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_167
-INFO: [Physopt 32-661] Optimized 13 nets. Re-placed 13 instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 13 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 13 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.304 | TNS=-5709.944 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6692 ; free virtual = 18038
-Phase 9 Single Cell Placement Optimization | Checksum: b12a9ea9
-
-Time (s): cpu = 00:13:45 ; elapsed = 00:03:29 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6692 ; free virtual = 18038
-
-Phase 10 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1/O
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1/O
-INFO: [Physopt 32-661] Optimized 1 net. Re-placed 2 instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 0 new cell, deleted 0 existing cell and moved 2 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.302 | TNS=-5703.084 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6692 ; free virtual = 18037
-Phase 10 Multi Cell Placement Optimization | Checksum: 150c363ea
-
-Time (s): cpu = 00:14:07 ; elapsed = 00:03:35 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6692 ; free virtual = 18037
-
-Phase 11 Rewire
-INFO: [Physopt 32-246] Starting Signal Push optimization...
-INFO: [Physopt 32-77] Pass 1. Identified 1 candidate net for rewire optimization.
-INFO: [Physopt 32-134] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_610_n_0. Rewiring did not optimize the net.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6692 ; free virtual = 18037
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6692 ; free virtual = 18037
-Phase 11 Rewire | Checksum: 114e164b0
-
-Time (s): cpu = 00:14:07 ; elapsed = 00:03:35 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6692 ; free virtual = 18037
-
-Phase 12 Critical Cell Optimization
-INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__15[64]_repN_1 was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[32] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-571] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_320_n_0 was not replicated.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[31] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[0] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[9] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[10] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[16] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[12] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[35] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[39] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[0]_repN was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[36] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[44] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[14] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[13] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[49] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[7] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[50]. Replicated 1 times.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[46]. Replicated 1 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[33] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[3] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-571] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_312_n_0 was not replicated.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8_n_0 was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[11]_repN_1 was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[40] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[20] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_11_n_0 was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[34] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[40]. Replicated 1 times.
-INFO: [Physopt 32-232] Optimized 3 nets. Created 3 new instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 3 nets or cells. Created 3 new cells, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.302 | TNS=-5703.084 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6682 ; free virtual = 18028
-Phase 12 Critical Cell Optimization | Checksum: 14a4c2e42
-
-Time (s): cpu = 00:17:25 ; elapsed = 00:04:38 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6682 ; free virtual = 18028
-
-Phase 13 SLR Crossing Optimization
-Phase 13 SLR Crossing Optimization | Checksum: 14a4c2e42
-
-Time (s): cpu = 00:17:25 ; elapsed = 00:04:38 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6682 ; free virtual = 18028
-
-Phase 14 Fanout Optimization
-INFO: [Physopt 32-76] Pass 1. Identified 1 candidate net for fanout optimization.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[63] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6682 ; free virtual = 18028
-Phase 14 Fanout Optimization | Checksum: 13205cee4
-
-Time (s): cpu = 00:17:27 ; elapsed = 00:04:39 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6682 ; free virtual = 18028
-
-Phase 15 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__15[64]_repN_1. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2_i_1_replica_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[32]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[32]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_320_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_320
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[31]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[31]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_20_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_20
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_45_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_45
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[8]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_9_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_35_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_35
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_243_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_243
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_324_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_324
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_83_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_83
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_8_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_107_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_107
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[48]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_59_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_59
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[6]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_11_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_102_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_102
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_17
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_79_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_79
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[15]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_2_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_36_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_36
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_24_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_24
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[16]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_21_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_21
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_limited_wide[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_105_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_105
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_80_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_80
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_113_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_113
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_193_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_193
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_240_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_240
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_245_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_245
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[35]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_32_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_32
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_112_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_112
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[39]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[39]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_19_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_19
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_106_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_106
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[0]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_17_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[2]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_15_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_125_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_125
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[36]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[36]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_122_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_122
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_111_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_111
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[11]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_6_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_31_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_31
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_79_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_79
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[44]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_98_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_98
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[14]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_195_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_195
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_242_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_242
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_247_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_247
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[5]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_12_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_130_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_130
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_121_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_121
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[1]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_16_replica
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[49]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_20_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_20
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_23
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_22_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_22
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_46_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_46
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_100_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_100
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_137_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_137
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_248_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_248
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_118_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_118
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[47]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_81_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_81
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_44_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_44
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_132_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_132
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_107_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_107
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_124_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_124
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[50]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[46]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[33]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[33]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_77_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_77
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_194_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_194
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_241_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_241
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_246_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_246
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_103_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_103
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_312_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_312
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_316_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_316
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_19_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_19
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_126_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_126
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_188_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_188
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_102_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_102
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_18_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_18
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_115_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_115
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_45_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_45
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_78_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_78
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_96_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_96
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_27_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_27
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_100_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_100
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_77_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_77
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_143_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_143
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_116_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_116
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_166_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_166
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_180_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_180
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[11]_repN_1. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_6_replica_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[59]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_28_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_28
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_9_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[40]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_96_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_96
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_140_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_140
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_139_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_139
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[20]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_11_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_112_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_112
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[34]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_23
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_196_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_196
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_92_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_92
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_120_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_120
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_34_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_34
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_128_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_128
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_190_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_190
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_41_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_41
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_24_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_24
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_33_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_33
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_110_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_110
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_119_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_119
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[43]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_109_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_109
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_373_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_373
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_105_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_105
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_93_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_93
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_136_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_136
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[38]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[38]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_104_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_104
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[19]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_111_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_111
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[7]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[44]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[44]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_75_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_75
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_13_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_54_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_54
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_19_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_19
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_23
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[21]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[45]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_89_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_89
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_300_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_300
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[37]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[37]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_113_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_113
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[29]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_11_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_11
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[35]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_20
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_42_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_42
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_189_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_189
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[22]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_256_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_256
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_30_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_30
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_260_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_260
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[42]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_29_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_29
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[1]_repN_1. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_16_replica_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_131_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_131
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[48]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[48]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_128_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_128
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_76_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_76
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_154_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_154
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_115_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_115
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_60_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_60
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_84_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_84
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_142_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_142
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[12]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[12]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[14]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[14]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_43_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_43
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_377_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_377
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[14]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[14]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[37]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[37]_i_1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_10_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[2]_repN_1. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_15_replica_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_101_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_101
-INFO: [Physopt 32-661] Optimized 9 nets. Re-placed 9 instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 9 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 9 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.279 | TNS=-5696.529 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6686 ; free virtual = 18032
-Phase 15 Single Cell Placement Optimization | Checksum: 184895d63
-
-Time (s): cpu = 00:21:38 ; elapsed = 00:05:32 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6686 ; free virtual = 18032
-
-Phase 16 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[32]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[32]/Q
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1/O
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6686 ; free virtual = 18032
-Phase 16 Multi Cell Placement Optimization | Checksum: bd803523
-
-Time (s): cpu = 00:21:45 ; elapsed = 00:05:34 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6686 ; free virtual = 18032
-
-Phase 17 Rewire
-INFO: [Physopt 32-246] Starting Signal Push optimization...
-INFO: [Physopt 32-77] Pass 1. Identified 1 candidate net for rewire optimization.
-INFO: [Physopt 32-134] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_610_n_0. Rewiring did not optimize the net.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6686 ; free virtual = 18032
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6686 ; free virtual = 18032
-Phase 17 Rewire | Checksum: 158751853
-
-Time (s): cpu = 00:21:46 ; elapsed = 00:05:34 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6686 ; free virtual = 18032
-
-Phase 18 Critical Cell Optimization
-INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__15[64]_repN_1 was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[32] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-571] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_320_n_0 was not replicated.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[31] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[0] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[9] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[10] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[16] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[12] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[35] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[44] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[39] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[0]_repN was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[36] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[49] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[14] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[13] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[7] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[33] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[3] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-571] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_312_n_0 was not replicated.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8_n_0 was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[43] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[11]_repN_1 was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[40] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[20] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_11_n_0 was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[45]. Replicated 1 times.
-INFO: [Physopt 32-572] Net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[34] was not replicated.
-Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets .
-INFO: [Physopt 32-232] Optimized 1 net. Created 1 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 1 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-33.279 | TNS=-5696.529 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18036
-Phase 18 Critical Cell Optimization | Checksum: 239da8618
-
-Time (s): cpu = 00:24:59 ; elapsed = 00:06:35 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18036
-
-Phase 19 DSP Register Optimization
-INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 19 DSP Register Optimization | Checksum: 239da8618
-
-Time (s): cpu = 00:24:59 ; elapsed = 00:06:35 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18036
-
-Phase 20 BRAM Register Optimization
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_10' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_11' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_12' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_13' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_14' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_15' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_16' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_17' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_18' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_19' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_20' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_21' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_22' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_23' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_8' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_9' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Common 17-14] Message 'Physopt 32-614' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 20 BRAM Register Optimization | Checksum: 239da8618
-
-Time (s): cpu = 00:24:59 ; elapsed = 00:06:36 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18036
-
-Phase 21 URAM Register Optimization
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 21 URAM Register Optimization | Checksum: 239da8618
-
-Time (s): cpu = 00:24:59 ; elapsed = 00:06:36 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18036
-
-Phase 22 Shift Register Optimization
-INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
-INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 22 Shift Register Optimization | Checksum: 239da8618
-
-Time (s): cpu = 00:24:59 ; elapsed = 00:06:36 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18036
-
-Phase 23 DSP Register Optimization
-INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 23 DSP Register Optimization | Checksum: 239da8618
-
-Time (s): cpu = 00:24:59 ; elapsed = 00:06:36 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18036
-
-Phase 24 BRAM Register Optimization
-INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 24 BRAM Register Optimization | Checksum: 239da8618
-
-Time (s): cpu = 00:24:59 ; elapsed = 00:06:36 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18036
-
-Phase 25 URAM Register Optimization
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 25 URAM Register Optimization | Checksum: 239da8618
-
-Time (s): cpu = 00:24:59 ; elapsed = 00:06:36 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18036
-
-Phase 26 Shift Register Optimization
-INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
-INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 26 Shift Register Optimization | Checksum: 239da8618
-
-Time (s): cpu = 00:24:59 ; elapsed = 00:06:36 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18036
-
-Phase 27 Critical Pin Optimization
-INFO: [Physopt 32-606] Identified 100 candidate nets for critical-pin optimization.
-INFO: [Physopt 32-608] Optimized 33 nets. Swapped 563 pins.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 33 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 563 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.979 | TNS=-5647.512 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18035
-Phase 27 Critical Pin Optimization | Checksum: 239da8618
-
-Time (s): cpu = 00:25:10 ; elapsed = 00:06:40 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18035
-
-Phase 28 Very High Fanout Optimization
-INFO: [Physopt 32-65] No nets found for high-fanout optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 28 Very High Fanout Optimization | Checksum: 239da8618
-
-Time (s): cpu = 00:25:10 ; elapsed = 00:06:40 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18035
-
-Phase 29 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization.
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[20]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__15[64]_repN_1. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2_i_1_replica_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[32]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[32]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_11_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_320_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_320
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[31]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[31]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_44_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_44
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_113_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_113
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_35_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_35
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_188_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_188
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_324_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_324
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_81_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_81
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_8_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_115_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_115
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[48]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[39]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[39]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_100_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_100
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[55]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_77_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_77
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[59]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[35]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[36]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[36]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_107_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_107
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_116_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_116
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_36_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_36
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_79_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_79
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_24_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_24
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_21_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_21
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_limited_wide[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_112_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_112
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_195_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_195
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_242_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_242
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_247_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_247
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_83_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_83
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[7]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[16]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_243_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_243
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[14]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_45_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_45
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[44]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_78_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_78
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_96_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_96
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_132_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_132
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_105_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_105
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_112_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_112
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[34]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_80_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_80
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_77_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_77
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_166_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_166
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_32_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_32
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_180_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_180
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_11_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_190_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_190
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[47]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_23
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[40]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_193_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_193
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_240_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_240
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_245_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_245
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_22_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_22
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_194_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_194
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_241_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_241
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_246_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_246
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[38]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[38]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_46_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_46
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[50]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_111_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_111
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[49]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_31_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_31
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[46]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_154_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_154
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_41_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_41
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_100_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_100
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[30]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_107_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_107
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_7
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/raw_counter[3]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/raw_counter_p_reg[3]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_9_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[39]_i_16_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[39]_i_16
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[51]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[51]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_13_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_113_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_113
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3__1_i_31_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3__1_i_31
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_17
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[26]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_8
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[43]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[43]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_20_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_20
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/raw_counter[6]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/raw_counter_p_reg[6]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[39]_i_7_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[39]_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3__1_i_25_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3__1_i_25
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_19_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_19
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[6]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_11_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_189_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_189
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_79_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_79
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_103_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_103
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_45_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_45
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_312_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_312
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_18_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_18
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_316_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_316
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_75_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_75
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[12]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[12]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[12]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[12]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[14]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[14]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[37]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[37]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[43]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[43]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[14]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[14]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[37]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[37]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[22]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[39]_i_6_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[39]_i_6
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_23_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_23
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_128_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_128
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_10_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_137_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_137
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[18]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_16
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[19]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[21]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[1]_repN_1. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_16_replica_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_42_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_42
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[9]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[9]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_196_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_196
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[9]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[9]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[15]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[15]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_106_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_106
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[15]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[15]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[31]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_109_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_109
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_59_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_59
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[3]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[23]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_76_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_76
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_124_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_124
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[6]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[43]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[43]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_13_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_96_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_96
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[43]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[43]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[10]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[10]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[10]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[10]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[13]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[13]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[13]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[13]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_12_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_102_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_102
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[27]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_7
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[2]_repN_1. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_15_replica_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_43_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_43
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3__1_i_21_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3__1_i_21
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[5]_repN_1. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_12_replica_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[49]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[49]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_9_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[49]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[49]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_111_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_111
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[7]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_248_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_248
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[29]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[50]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[50]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[50]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[50]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/raw_counter[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/raw_counter_p_reg[2]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_29_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_29
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_14_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_14
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_27_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_27
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3__1_i_32_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3__1_i_32
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_20_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[55]_i_20
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_152_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_152
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_9_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_13_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_13
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[39]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[39]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_increment_q32[43]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3_i_12
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_150_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_150
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_191_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_191
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_11_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_11
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[8]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_9_replica
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_179_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/active_subsec_q32_p[63]_i_179
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[4]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_13_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[16]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[16]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[35]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_28_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_wide2__9_i_28
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[16]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[16]_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_373_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_373
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[44]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[44]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[39]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_300_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4_i_300
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_143_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_143
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[43]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_125_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_125
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[8]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/raw_counter[4]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/raw_counter_p_reg[4]
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_9_n_0. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_9
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[48]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[48]
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[47]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_119_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_119
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3__1_i_27_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds3__1_i_27
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[33]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[10]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_7_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_10_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[15]_i_10
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_15_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[31]_i_15
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_5_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[51]_i_5
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[15]_repN. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_2_replica
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[24]. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__2_i_10
-INFO: [Physopt 32-661] Optimized 14 nets. Re-placed 14 instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 14 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 14 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.966 | TNS=-5645.716 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6720 ; free virtual = 18065
-Phase 29 Single Cell Placement Optimization | Checksum: 1814af8c5
-
-Time (s): cpu = 00:29:46 ; elapsed = 00:07:38 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6720 ; free virtual = 18065
-
-Phase 30 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[35]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[36]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[34]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[40]_i_1/O
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[38]_i_1/O
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6721 ; free virtual = 18067
-Phase 30 Multi Cell Placement Optimization | Checksum: 22c137776
-
-Time (s): cpu = 00:30:04 ; elapsed = 00:07:43 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6721 ; free virtual = 18067
-
-Phase 31 SLR Crossing Optimization
-Phase 31 SLR Crossing Optimization | Checksum: 22c137776
-
-Time (s): cpu = 00:30:04 ; elapsed = 00:07:43 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6721 ; free virtual = 18067
-
-Phase 32 Critical Path Optimization
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.966 | TNS=-5645.716 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_0[32]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net pll_gps_trck_clk. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_i_3_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_i_11_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_i_32_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_i_50_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_i_64_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_i_78_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_i_92_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins.
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_115_n_0. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.961 | TNS=-5645.605 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[63]_i_100_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_i_24_n_7. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[63]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[59]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[55]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[51]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[47]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[43]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[39]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[35]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[31]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[27]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[23]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[19]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[15]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[11]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[7]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p_reg[3]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[3]_i_8_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[63]_i_5_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[63]_i_23_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[63]_i_40_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[63]_i_66_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[63]_i_80_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[63]_i_94_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[63]_i_113_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[63]_i_27_n_7. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[63]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[59]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[55]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[51]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[47]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[43]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[39]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[35]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[31]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[27]_i_2_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[27]_i_6_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[27]_i_7_n_6. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[23]_i_7_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[19]_i_7_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins.
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[19]_i_15_n_0. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.960 | TNS=-5645.475 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[15]_i_7_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[11]_i_7_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[7]_i_7_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[3]_i_7_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[3]_i_8_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[3]_i_13_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p_reg[3]_i_18_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[3]_i_25_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_p[32]_i_1_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_n4__10_n_88. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_n4__9_n_106. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[16]. Re-placed instance u_rocket/fpga_gps_domain/dev/pps/i_pps_core/rate_word_q32_n4__5_i_1
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[16]. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.947 | TNS=-5643.798 |
-INFO: [Physopt 32-608] Optimized 1 net. Swapped 16 pins.
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8_n_0. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.946 | TNS=-5643.670 |
-INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins.
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_14_n_0. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.946 | TNS=-5643.670 |
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[16]. Replicated 2 times.
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[16]. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.945 | TNS=-5643.606 |
-INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins.
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[11]_i_15_n_0. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.929 | TNS=-5641.542 |
-INFO: [Physopt 32-608] Optimized 1 net. Swapped 16 pins.
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_p[23]_i_8_n_0. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.929 | TNS=-5641.542 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_n4__7_n_105. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/integrator_q32_n4__6_n_106. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-81] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[7]. Replicated 4 times.
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_for_pi[7]. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-32.926 | TNS=-5641.154 |
-INFO: [Common 17-41] Interrupt caught. Command should exit soon.
-Phase 32 Critical Path Optimization | Checksum: 22c137776
-
-Time (s): cpu = 00:30:44 ; elapsed = 00:07:56 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6726 ; free virtual = 18072
-Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6726 ; free virtual = 18072
-Ending Physical Synthesis Task | Checksum: 24256c9d9
-
-Time (s): cpu = 00:30:45 ; elapsed = 00:07:56 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6726 ; free virtual = 18072
-INFO: [Vivado_Tcl 4-60] Physopt has been cancelled by the user.
-INFO: [Common 17-83] Releasing license: Implementation
-1415 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-phys_opt_design failed
-phys_opt_design: Time (s): cpu = 00:31:26 ; elapsed = 00:08:05 . Memory (MB): peak = 4349.227 ; gain = 0.000 ; free physical = 6726 ; free virtual = 18072
-INFO: [Common 17-344] 'phys_opt_design' was cancelled
-INFO: [Common 17-344] 'source' was cancelled
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 17:33:47 2026...
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream_6431.backup.jou b/targets/fpga/genesys2/out/logs/build_bitstream_6431.backup.jou
deleted file mode 100644
index 77a89e6..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream_6431.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Fri Jul 10 16:40:44 2026
-# Process ID : 6431
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21751 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
diff --git a/targets/fpga/genesys2/out/logs/build_bitstream_6431.backup.log b/targets/fpga/genesys2/out/logs/build_bitstream_6431.backup.log
deleted file mode 100644
index f5f9e78..0000000
--- a/targets/fpga/genesys2/out/logs/build_bitstream_6431.backup.log
+++ /dev/null
@@ -1,4460 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Fri Jul 10 16:40:44 2026
-# Process ID : 6431
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21751 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../../..]]
-# set repo_dir [file normalize [file join $fpga_dir ../../..]]
-# set hardware_dir [file join $repo_dir hardware]
-# cd $repo_dir
-# set part_name "xc7k325tffg900-2"
-# set board_part "digilentinc.com:genesys2:part0:1.1"
-# set top_module "genesys2_rocket_top"
-# set out_dir [file join $fpga_dir out]
-# set generated_dir [file join $out_dir build generated]
-# set report_dir [file join $out_dir reports]
-# set bit_dir [file join $out_dir bitstream]
-# set checkpoint_dir [file join $out_dir build checkpoints]
-# file mkdir $generated_dir
-# file mkdir $report_dir
-# file mkdir $bit_dir
-# file mkdir $checkpoint_dir
-# set rocket_rtl_dir [file join $hardware_dir generated genesys2-soc-verilog]
-# set rocket_top [file join $rocket_rtl_dir VCU118RocketSystem.sv]
-# set rocket_filelist [file join $rocket_rtl_dir filelist.f]
-# set wrapper [file join $generated_dir ${top_module}.sv]
-# if {[info exists ::env(GPS_SYSTEM_DIR)] && [string trim $::env(GPS_SYSTEM_DIR)] ne ""} {
-# set gps_system_dir [file normalize $::env(GPS_SYSTEM_DIR)]
-# } else {
-# set gps_system_dir [file join $hardware_dir external gps rtl]
-# }
-# if {[info exists ::env(RF_INPUT_MODE)]} {
-# set rf_input_mode [string tolower [string trim $::env(RF_INPUT_MODE)]]
-# } else {
-# set rf_input_mode "pmod"
-# }
-# if {$rf_input_mode ni {"pmod" "generated" "ethernet"}} {
-# error "Unsupported Genesys2 RF_INPUT_MODE=$rf_input_mode. Use pmod, generated, or ethernet."
-# }
-# if {![file exists $rocket_filelist]} {
-# error "Rocket Verilog filelist not found: $rocket_filelist"
-# }
-# if {![file exists $rocket_top]} {
-# error "Rocket top Verilog not found: $rocket_top"
-# }
-# puts "Generating Genesys2 wrapper: $wrapper"
-Generating Genesys2 wrapper: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv
-# puts "Genesys2 RF input mode: $rf_input_mode"
-Genesys2 RF input mode: pmod
-# exec python3 [file join $fpga_dir tools gen_genesys2_wrapper.py] \
-# --rocket-top $rocket_top \
-# --out $wrapper \
-# --rf-input-mode $rf_input_mode
-# set max_threads [string trim [exec nproc]]
-# puts "Using Vivado maxThreads=$max_threads"
-Using Vivado maxThreads=12
-# set_param general.maxThreads $max_threads
-# set_part $part_name
-INFO: [Coretcl 2-1500] The part has been set to 'xc7k325tffg900-2' for the current project only. Run set_part -help for more details. To evaluate different speed grades in the current design, use the set_speed_grade command, or use the open_checkpoint -part command to change the part used by an existing checkpoint design.
-# if {[llength [get_board_parts -quiet $board_part]] != 0} {
-# set_property board_part $board_part [current_project]
-# }
-# proc apply_genesys2_async_clock_groups {} {
-# set fabric_clk [get_clocks -quiet pll_fabric_clk]
-# set gps_acq_clk [get_clocks -quiet pll_gps_acq_clk]
-# set gps_trck_clk [get_clocks -quiet pll_gps_trck_clk]
-# set gps_rf_clk [get_clocks -quiet {pll_gps_rf_exact_clk pmod_rf_clk}]
-# set eth_clk [get_clocks -quiet genesys2_eth_rxck]
-#
-# if {[llength $fabric_clk] == 0 ||
-# [llength $gps_acq_clk] == 0 ||
-# [llength $gps_trck_clk] == 0 ||
-# [llength $gps_rf_clk] == 0} {
-# puts "Warning: not all Genesys2 async clock groups are available yet."
-# return
-# }
-#
-# puts "Applying Genesys2 async clock groups."
-# set args [list -asynchronous \
-# -group $fabric_clk \
-# -group $gps_acq_clk \
-# -group $gps_trck_clk \
-# -group $gps_rf_clk]
-# if {[llength $eth_clk] != 0} {
-# lappend args -group $eth_clk
-# }
-# set_clock_groups {*}$args
-# }
-# set rocket_files {}
-# set fh [open $rocket_filelist r]
-# while {[gets $fh line] >= 0} {
-# set line [string trim $line]
-# if {$line eq ""} {
-# continue
-# }
-# set line [regsub {^\./} $line ""]
-# lappend rocket_files [file normalize [file join $rocket_rtl_dir $line]]
-# }
-# close $fh
-# puts "Reading Rocket Chip RTL..."
-Reading Rocket Chip RTL...
-# read_verilog -sv $rocket_files
-# read_verilog [file join $hardware_dir upstream rocket-chip src main resources vsrc plusarg_reader.v]
-# set gps_filelist [file join $hardware_dir external gps rtl filelist.f]
-# set gps_files {}
-# set gps_fh [open $gps_filelist r]
-# while {[gets $gps_fh rel] >= 0} {
-# set rel [string trim $rel]
-# if {$rel eq "" || [string match "#*" $rel]} {
-# continue
-# }
-# lappend gps_files [file join $gps_system_dir $rel]
-# }
-# close $gps_fh
-# puts "Reading GPS APB wrapper RTL from $gps_system_dir..."
-Reading GPS APB wrapper RTL from /home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl...
-# set_property include_dirs [list [file join $gps_system_dir trck_src pulp_fifo]] [current_fileset]
-# read_verilog -sv $gps_files
-# puts "Reading Genesys2 shell RTL..."
-Reading Genesys2 shell RTL...
-# set shell_files [list \
-# [file join $hardware_dir fpga vcu118 rtl axi4_ram_64.sv] \
-# [file join $hardware_dir fpga vcu118 rtl axi4_slave_tieoff_64.sv] \
-# [file join $hardware_dir fpga genesys2 rtl rocket_bscan_dmi_tunnel.sv] \
-# ]
-# if {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet RF RTL..."
-# lappend shell_files \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_async_fifo.sv] \
-# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_core.sv] \
-# [file join $hardware_dir fpga genesys2 rtl ethernet_rf eth_rf_genesys2.sv]
-# } else {
-# puts "Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=$rf_input_mode."
-# }
-Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=pmod.
-# read_verilog -sv $shell_files
-# read_verilog -sv $wrapper
-# puts "Reading constraints..."
-Reading constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_rocket.xdc]
-# puts "Reading Genesys2 PMOD SPI constraints..."
-Reading Genesys2 PMOD SPI constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_spi.xdc]
-# puts "Reading Genesys2 PMOD sensor IRQ constraints..."
-Reading Genesys2 PMOD sensor IRQ constraints...
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_irq.xdc]
-# if {$rf_input_mode eq "pmod"} {
-# puts "Reading Genesys2 PMOD RF constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_rf.xdc]
-# } elseif {$rf_input_mode eq "ethernet"} {
-# puts "Reading Genesys2 Ethernet PHY constraints..."
-# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_ethernet.xdc]
-# }
-Reading Genesys2 PMOD RF constraints...
-# puts "Running synthesis for $part_name..."
-Running synthesis for xc7k325tffg900-2...
-# synth_design -top $top_module -part $part_name -verilog_define SYNTHESIS
-Command: synth_design -top genesys2_rocket_top -part xc7k325tffg900-2 -verilog_define SYNTHESIS
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
-INFO: [Device 21-403] Loading part xc7k325tffg900-2
-INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
-INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 6459
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2344.473 ; gain = 483.562 ; free physical = 2940 ; free virtual = 19506
----------------------------------------------------------------------------------
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:8]
-WARNING: [Synth 8-11067] parameter 'CODE_LENGTH_IN_CHIPS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:9]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:10]
-WARNING: [Synth 8-11067] parameter 'SAMPLING_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:13]
-WARNING: [Synth 8-11067] parameter 'CENTER_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:14]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:15]
-WARNING: [Synth 8-11067] parameter 'RF_DATA_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:16]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:17]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:18]
-WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:19]
-WARNING: [Synth 8-11067] parameter 'ABS_SAMPLE_CNTR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:22]
-WARNING: [Synth 8-11067] parameter 'MS_PER_BIT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:23]
-WARNING: [Synth 8-11067] parameter 'C_ACQ_CHN_NUM' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:26]
-WARNING: [Synth 8-11067] parameter 'ACQ_IQ_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:27]
-WARNING: [Synth 8-11067] parameter 'ACQ_CORR_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:28]
-WARNING: [Synth 8-11067] parameter 'RF_DMEM_AL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:30]
-WARNING: [Synth 8-11067] parameter 'NUM_PRN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:31]
-WARNING: [Synth 8-11067] parameter 'PRN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:32]
-WARNING: [Synth 8-11067] parameter 'STRECH_COUNT_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:33]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_COEF1' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:40]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:41]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:42]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:43]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:44]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:45]
-WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_FREQ_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:46]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:47]
-WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:48]
-WARNING: [Synth 8-11067] parameter 'NUM_TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:50]
-WARNING: [Synth 8-11067] parameter 'TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:51]
-WARNING: [Synth 8-11067] parameter 'ATAN_ANGLE_BIT_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:56]
-WARNING: [Synth 8-11067] parameter 'ATAN_TABLE_SIZE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:57]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:60]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:61]
-WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:62]
-WARNING: [Synth 8-11067] parameter 'DOPPLER_SPACE_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:63]
-WARNING: [Synth 8-11067] parameter 'C1_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:65]
-WARNING: [Synth 8-11067] parameter 'C2_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:66]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:71]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:72]
-WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:73]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:76]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:77]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:78]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:80]
-WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:81]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:83]
-WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:84]
-WARNING: [Synth 8-11067] parameter 'LOCK_WINDOW' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:85]
-WARNING: [Synth 8-11067] parameter 'LOCK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:86]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:89]
-WARNING: [Synth 8-11067] parameter 'DLL_LF_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:90]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:92]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:93]
-WARNING: [Synth 8-11067] parameter 'C1_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:95]
-WARNING: [Synth 8-11067] parameter 'C2_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:96]
-WARNING: [Synth 8-11067] parameter 'CODE_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:99]
-WARNING: [Synth 8-11067] parameter 'CODE_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:100]
-WARNING: [Synth 8-11067] parameter 'REAL_POS_FS_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:102]
-WARNING: [Synth 8-11067] parameter 'REAL_NEG_FS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:103]
-WARNING: [Synth 8-11067] parameter 'FS_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:105]
-WARNING: [Synth 8-11067] parameter 'DLL_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:106]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:108]
-WARNING: [Synth 8-11067] parameter 'DLL_SPACING_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:109]
-WARNING: [Synth 8-11067] parameter 'REM_CODE_PH_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:110]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:113]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:114]
-WARNING: [Synth 8-11067] parameter 'TRCK_CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:115]
-WARNING: [Synth 8-11067] parameter 'F_ACQ_CLK' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:118]
-WARNING: [Synth 8-11067] parameter 'ACQ_CLK_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:119]
-WARNING: [Synth 8-11067] parameter 'RF_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:120]
-WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE_CHIP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:121]
-WARNING: [Synth 8-11067] parameter 'ACQ_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:123]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:124]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:125]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:126]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:127]
-WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:128]
-WARNING: [Synth 8-11067] parameter 'ACQ_CODE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:130]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:132]
-WARNING: [Synth 8-11067] parameter 'FFT_IQ_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:133]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:134]
-WARNING: [Synth 8-11067] parameter 'FFT_CODE_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:135]
-WARNING: [Synth 8-11067] parameter 'IFFT_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:136]
-WARNING: [Synth 8-11067] parameter 'IFFT_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:137]
-WARNING: [Synth 8-11067] parameter 'IFFT_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:139]
-WARNING: [Synth 8-11067] parameter 'NFFT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:141]
-WARNING: [Synth 8-11067] parameter 'NFFT_OVER_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:142]
-WARNING: [Synth 8-11067] parameter 'ZERO_PAD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:143]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:145]
-WARNING: [Synth 8-11067] parameter 'IFFT_O_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:146]
-WARNING: [Synth 8-11067] parameter 'ABS_SQR_I_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:147]
-WARNING: [Synth 8-11067] parameter 'CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:148]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_DIV_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:149]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:150]
-WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:151]
-WARNING: [Synth 8-11067] parameter 'PEAK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:152]
-WARNING: [Synth 8-11067] parameter 'DOPP_STEP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:154]
-WARNING: [Synth 8-11067] parameter 'NUM_FREQ_BIN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:155]
-WARNING: [Synth 8-11067] parameter 'FREQ_BIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:156]
-INFO: [Common 17-14] Message 'Synth 8-11067' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-10180] variable 'i' must explicitly be declared as automatic or static [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv:53]
-INFO: [Synth 8-6157] synthesizing module 'genesys2_rocket_top' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:3]
-INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
- Parameter DIFF_TERM bound to: FALSE - type: string
- Parameter IBUF_LOW_PWR bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
-INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
- Parameter BANDWIDTH bound to: OPTIMIZED - type: string
- Parameter CLKFBOUT_MULT_F bound to: 5.000000e+00 - type: double
- Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKIN1_PERIOD bound to: 5.000000e+00 - type: double
- Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
- Parameter CLKOUT0_DIVIDE_F bound to: 1.250000e+01 - type: double
- Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT1_DIVIDE bound to: 20 - type: integer
- Parameter CLKOUT1_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT1_PHASE bound to: 0.000000e+00 - type: double
- Parameter CLKOUT2_DIVIDE bound to: 8 - type: integer
- Parameter CLKOUT2_DUTY_CYCLE bound to: 5.000000e-01 - type: double
- Parameter CLKOUT2_PHASE bound to: 0.000000e+00 - type: double
- Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
- Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
- Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
- Parameter STARTUP_WAIT bound to: FALSE - type: string
-INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
-WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:65]
-WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:65]
-WARNING: [Synth 8-7023] instance 'u_clock_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:65]
-INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
-INFO: [Synth 8-6157] synthesizing module 'IBUF' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
-INFO: [Synth 8-6157] synthesizing module 'BSCANE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
- Parameter DISABLE_JTAG bound to: FALSE - type: string
- Parameter JTAG_CHAIN bound to: 4 - type: integer
-INFO: [Synth 8-6155] done synthesizing module 'BSCANE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
-INFO: [Synth 8-6157] synthesizing module 'rocket_bscan_dmi_tunnel' [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-INFO: [Synth 8-6155] done synthesizing module 'rocket_bscan_dmi_tunnel' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:263]
-INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
- Parameter PROG_USR bound to: FALSE - type: string
- Parameter SIM_CCLK_FREQ bound to: 0.000000e+00 - type: double
-INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
-INFO: [Synth 8-6157] synthesizing module 'VCU118RocketSystem' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/VCU118RocketSystem.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockSinkDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i2_o1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i2_o1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SynchronizerShiftReg_w1_d3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockSinkDomain' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_aggregator' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_aggregator' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_sbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_sbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroup' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroup' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_5' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_5' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_out_i1_o4_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o4_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x120' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x120' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x77' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x77' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAUART' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAUART' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_gps' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAGPS' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAGPS' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_2' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_2' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_gps' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FrontBus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x123' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x123' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'FrontBus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_2' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_2' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x124' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x124' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x78' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x78' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'ram_2x99' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'ram_2x99' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u_1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u_1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_3' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_debug' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_Debug' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_Debug' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_debug' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_4' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_4' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TilePRCIDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'HierarchicalElementResetDomain' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/HierarchicalElementResetDomain.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'RocketTile' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/RocketTile.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'IntXbar_i3_o1' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i3_o1' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'DCache' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:31]
-INFO: [Synth 8-6157] synthesizing module 'DTLB' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:31]
-INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-6155] done synthesizing module 'PMPChecker_s3' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PMPChecker_s3.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'PMAChecker' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PMAChecker.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:194]
-INFO: [Synth 8-6155] done synthesizing module 'OptimizationBarrier_TLBEntryData' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/OptimizationBarrier_TLBEntryData.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:228]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:262]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:296]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:330]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:364]
-INFO: [Synth 8-6155] done synthesizing module 'DTLB' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:31]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:1121]
-INFO: [Synth 8-6155] done synthesizing module 'Arbiter8_DCacheMetadataReq' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Arbiter8_DCacheMetadataReq.sv:31]
-INFO: [Synth 8-6155] done synthesizing module 'rockettile_dcache_data_arrays_0_131072x64' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:32]
-INFO: [Synth 8-6155] done synthesizing module 'DCacheDataArray' (0#1) [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCacheDataArray.sv:31]
-INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:139]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:173]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:207]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:241]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:275]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:309]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/PTW.sv:188]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:3191]
- Parameter FORMAT bound to: max_core_cycles=%d - type: string
- Parameter WIDTH bound to: 32 - type: integer
- Parameter DEFAULT bound to: 32'b00000000000000000000000000000000
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:400]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:406]
-WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:412]
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000000001
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter DATA_WIDTH bound to: 4 - type: integer
- Parameter ADDR_WIDTH bound to: 15 - type: integer
- Parameter PH_ACC_WL bound to: 32 - type: integer
- Parameter LUT_DEPTH_WL bound to: 5 - type: integer
- Parameter ACQ_SIN_IL bound to: 2 - type: integer
- Parameter ACQ_SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 25 - type: integer
- Parameter FS bound to: 16368000 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 10 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 52 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 2 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 36 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter FFT_IQ_WL bound to: 24 - type: integer
- Parameter FFT_IQ_TRUNC_WL bound to: 20 - type: integer
- Parameter FFT_CODE_WL bound to: 16 - type: integer
- Parameter FFT_CODE_TRUNC_WL bound to: 16 - type: integer
- Parameter OUT_WL bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 30 - type: integer
- Parameter FFT_POWER bound to: 14 - type: integer
- Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
- Parameter FRAC_BITS bound to: 2 - type: integer
- Parameter DATA_WIDTH bound to: 92 - type: integer
- Parameter ADDR_WIDTH bound to: 14 - type: integer
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
- Parameter DWIDTH bound to: 48 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ABS_SQR_I_TRUNCATED_WL bound to: 25 - type: integer
- Parameter CORR_DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter SAMPLES_PER_CODE_CHIP bound to: 16 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv:158]
- Parameter DWIDTH bound to: 51 - type: integer
- Parameter AWIDTH bound to: 14 - type: integer
- Parameter ITER bound to: 9 - type: integer
- Parameter IN_W_L bound to: 36 - type: integer
- Parameter IN_F_L bound to: 0 - type: integer
- Parameter OUT_W_L bound to: 16 - type: integer
- Parameter OUT_F_L bound to: 8 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:285]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:296]
-WARNING: [Synth 8-151] case item 32'b00000000000000000000000000001100 is unreachable [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:350]
-WARNING: [Synth 8-7071] port 'clk_200mhz' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
-WARNING: [Synth 8-7071] port 'mmcm_locked' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rd' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
-WARNING: [Synth 8-7071] port 'eth_rgmii_rxc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
-WARNING: [Synth 8-7071] port 'eth_rgmii_td' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
-WARNING: [Synth 8-7071] port 'eth_rgmii_tx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
-WARNING: [Synth 8-7071] port 'eth_rgmii_txc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
-WARNING: [Synth 8-7023] instance 'afe' of module 'afe_top' has 17 connections declared, but only 9 given [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
- Parameter HIGH_ADDRESS bound to: 4095 - type: integer
- Parameter LOW_ADDRESS bound to: 0 - type: integer
- Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
- Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
- Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000100000
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
- Parameter SIG_DEPTH bound to: 26 - type: integer
- Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:182]
- Parameter WIDTH bound to: 4 - type: integer
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter STAGES bound to: 32'b00000000000000000000000000000010
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter N bound to: 32'sb00000000000000000000000000000101
- Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
- Parameter Bypass bound to: 1'b0
- Parameter PH_ACC_WL bound to: 24 - type: integer
- Parameter LUT_DEPTH_WL bound to: 7 - type: integer
- Parameter SIN_IL bound to: 2 - type: integer
- Parameter SIN_FL bound to: 4 - type: integer
- Parameter PH_ACC_WL bound to: 46 - type: integer
- Parameter CODE_FREQ_I_IL bound to: 21 - type: integer
- Parameter CODE_FREQ_I_FL bound to: 20 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 10 - type: integer
- Parameter O_IL bound to: 16 - type: integer
- Parameter ERROR_I_IL bound to: 2 - type: integer
- Parameter ERROR_I_FL bound to: 13 - type: integer
- Parameter O_IL bound to: 8 - type: integer
- Parameter O_FL bound to: 20 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter TABLE_ADDR bound to: 4 - type: integer
- Parameter TABLE_SIZE bound to: 9 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 33 - type: integer
-WARNING: [Synth 8-7071] port 'vec_len_o' of module 'cordic_atan_basic' is unconnected for instance 'Disc_PLL_i' [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:218]
-WARNING: [Synth 8-7023] instance 'Disc_PLL_i' of module 'cordic_atan_basic' has 8 connections declared, but only 7 given [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:218]
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER1 bound to: 8 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter TABLE_ADDR bound to: 3 - type: integer
-WARNING: [Synth 8-151] case item 4'b1000 is unreachable [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:114]
-INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:105]
- Parameter TABLE_SIZE bound to: 8 - type: integer
- Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
- Parameter COORD_BIT_WIDTH bound to: 32 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 25 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter DIV_OUT_WL bound to: 15 - type: integer
- Parameter DIV_OUT_FL bound to: 13 - type: integer
- Parameter DIV_ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 22 - type: integer
- Parameter IN_FL bound to: 4 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
- Parameter ITER2 bound to: 14 - type: integer
- Parameter ITER bound to: 14 - type: integer
- Parameter IN_WL bound to: 45 - type: integer
- Parameter IN_FL bound to: 8 - type: integer
- Parameter OUT_WL bound to: 15 - type: integer
- Parameter OUT_FL bound to: 13 - type: integer
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:283]
-INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:541]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:48]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:49]
-WARNING: [Synth 8-6014] Unused sequential element s2_vaddr_r_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:989]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:47]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:48]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:47]
-WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:48]
-WARNING: [Synth 8-4767] Trying to implement RAM 'Memory_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/regfile_32x65.sv:60]
-Reason is one or more of the following :
- 1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
- 2: Invalid write to RAM.
- 3: Invalid write to RAM.
- 4: No valid clock found for write to RAM.
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2183]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2626]
-WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2637]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2754]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2755]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2757]
-WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2758]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2769]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2770]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2772]
-WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2773]
-WARNING: [Synth 8-6014] Unused sequential element rocc_blocked_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2894]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2895]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2896]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2897]
-WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2898]
-WARNING: [Synth 8-6014] Unused sequential element r_counter_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError_1.sv:69]
-Read & Write Range Direction Mismatch
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module comp_mult has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/comp_mult.sv:106]
-Read & Write Range Direction Mismatch
-WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module ifft_abs_sqr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:90]
-WARNING: [Synth 8-3848] Net eth_rgmii_td in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:38]
-WARNING: [Synth 8-3848] Net eth_rgmii_tx_ctl in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:39]
-WARNING: [Synth 8-3848] Net eth_rgmii_txc in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:40]
-WARNING: [Synth 8-3848] Net rf_data_o in module/entity afe_top does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:46]
-WARNING: [Synth 8-3848] Net fifo_of_o in module/entity trck_cntrl does not have driver. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:50]
-WARNING: [Synth 8-6014] Unused sequential element g1_var_reg was removed. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:46]
-WARNING: [Synth 8-7137] Register chip_o_reg in module cacode_gen_trck has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:36]
-WARNING: [Synth 8-7129] Port fifo_of_o in module trck_cntrl is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port trck_resetn in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port afe_resetn in module tracking_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_td[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_tx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_txc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port rf_data_o[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port clk_200mhz in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port mmcm_locked in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[3] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[2] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[1] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rd[0] in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rx_ctl in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port eth_rgmii_rxc in module afe_top is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port a_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[3] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[2] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[1] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port bi_i[0] in module comp_mult is either unconnected or has no load
-WARNING: [Synth 8-7129] Port PENABLE in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port start_acq_manuel in module acq_wrapper is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaSPI is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaUART is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLROM is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_en in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port R0_clk in module ram_2x10 is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_opcode[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_param[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[3] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_size[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_enq_bits_sink in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[127] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[126] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[125] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[124] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[123] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[122] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[121] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[120] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[119] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[118] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[117] in module SBToTL is either unconnected or has no load
-WARNING: [Synth 8-7129] Port io_dataIn[116] in module SBToTL is either unconnected or has no load
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2732.012 ; gain = 871.102 ; free physical = 2525 ; free virtual = 19099
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 2732.012 ; gain = 871.102 ; free physical = 2536 ; free virtual = 19111
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 2732.012 ; gain = 871.102 ; free physical = 2536 ; free virtual = 19111
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2732.012 ; gain = 0.000 ; free physical = 2542 ; free virtual = 19117
-INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-INFO: [Timing 38-2] Deriving generated clocks
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3001.152 ; gain = 0.000 ; free physical = 2402 ; free virtual = 18993
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3013.074 ; gain = 0.008 ; free physical = 2408 ; free virtual = 18999
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 3013.074 ; gain = 1152.164 ; free physical = 1790 ; free virtual = 18381
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7k325tffg900-2
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 3021.078 ; gain = 1160.168 ; free physical = 1797 ; free virtual = 18389
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 3021.078 ; gain = 1160.168 ; free physical = 1777 ; free virtual = 18368
----------------------------------------------------------------------------------
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:405]
-WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:444]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '99' to '12' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:57]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore2_addr_reg' and it is trimmed from '34' to '20' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:383]
-WARNING: [Synth 8-3936] Found unconnected internal register 'pstore1_addr_reg' and it is trimmed from '34' to '20' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:383]
-WARNING: [Synth 8-3936] Found unconnected internal register 'uncachedReqs_0_addr_reg' and it is trimmed from '34' to '3' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:958]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in1_reg' and it is trimmed from '65' to '33' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:58]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_in3_reg' and it is trimmed from '65' to '33' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv:60]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPToInt.sv:173]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_typeTagOut_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPToInt.sv:95]
-WARNING: [Synth 8-3936] Found unconnected internal register 'in_pipe_b_typeTagIn_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/IntToFP.sv:66]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:524]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:333]
-WARNING: [Synth 8-3936] Found unconnected internal register 'load_wb_typeTag_reg' and it is trimmed from '2' to '1' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/FPU.sv:142]
-WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2787]
-WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2787]
-WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2822]
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-802] inferred FSM for state register 'FsmState_SP_reg' in module 'fft_radix_2__parameterized1'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_peak_srch'
-INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'divider_fsm'
-INFO: [Synth 8-802] inferred FSM for state register 'STATE_reg' in module 'acq_top'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'acq_wrapper'
-INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'trck_cntrl'
-INFO: [Synth 8-802] inferred FSM for state register 'nav_solve_state_p_reg' in module 'nav_solve_timer'
-INFO: [Synth 8-802] inferred FSM for state register 'apb_bus_ps_reg' in module 'tracking_wrapper'
-WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '88' to '87' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a29d32s7k1z2u.sv:66]
-WARNING: [Synth 8-6841] Block RAM (Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-INFO: [Synth 8-3971] The signal "dual_port_bram:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized0:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized0'
-INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized1:/ram_reg" was recognized as a true dual port RAM template.
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- FSM_IDLE | 00 | 00
- FSM_SAVE_DATA | 01 | 01
- FSM_CALC_FFT | 10 | 10
- FSM_RELEASE_DATA | 11 | 11
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized1'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 001 | 000
- S_CORR | 101 | 001
- S_INIT_ADDR | 100 | 010
- S_DATA_Q | 011 | 011
- S_SRCH | 010 | 100
- S_END | 000 | 101
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'sequential' in module 'acq_peak_srch'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- idle | 00 | 00
- normalization | 01 | 01
- cordic_core | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'divider_fsm'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- S_IDLE | 0000001 | 000
- S_WR_DATA | 0001000 | 001
- S_START | 0010000 | 010
- S_CTRL | 1000000 | 011
- S_FREQ | 0100000 | 100
- S_END | 0000010 | 101
- S_PULLIN | 0000100 | 110
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'one-hot' in module 'acq_top'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'acq_wrapper'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- WAIT_START | 00 | 00
- WAIT_SAMPLE_ALIGN | 01 | 01
- WAIT_CODE_PHASE | 10 | 10
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'trck_cntrl'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- iSTATE0 | 0 | 00000000000000000000000000000000
-*
- iSTATE | 1 | 00000000000000000000000000000001
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'nav_solve_state_p_reg' using encoding 'sequential' in module 'nav_solve_timer'
----------------------------------------------------------------------------------------------------
- State | New Encoding | Previous Encoding
----------------------------------------------------------------------------------------------------
- APB_STATE_IDLE | 001 | 00000000000000000000000000000000
- APB_STATE_SEL | 010 | 00000000000000000000000000000001
- APB_STATE_WR | 100 | 00000000000000000000000000000010
----------------------------------------------------------------------------------------------------
-INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'tracking_wrapper'
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 3021.078 ; gain = 1160.168 ; free physical = 193 ; free virtual = 14994
----------------------------------------------------------------------------------
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_5'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_1'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_2'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_3'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_4'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_5'
-INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'u_rocket/tile_prci_domain/intsource_2'
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
----------------------------------------------------------------------------------
-Start RTL Component Statistics
----------------------------------------------------------------------------------
-Detailed RTL Component Info :
-+---Adders :
- 2 Input 109 Bit Adders := 1
- 2 Input 107 Bit Adders := 1
- 2 Input 66 Bit Adders := 1
- 3 Input 65 Bit Adders := 1
- 2 Input 64 Bit Adders := 7
- 3 Input 64 Bit Adders := 1
- 2 Input 62 Bit Adders := 1
- 3 Input 61 Bit Adders := 1
- 3 Input 58 Bit Adders := 1
- 2 Input 58 Bit Adders := 2
- 2 Input 55 Bit Adders := 4
- 2 Input 51 Bit Adders := 2
- 2 Input 49 Bit Adders := 1
- 2 Input 46 Bit Adders := 11
- 3 Input 46 Bit Adders := 2
- 2 Input 45 Bit Adders := 18
- 3 Input 45 Bit Adders := 10
- 2 Input 42 Bit Adders := 1
- 2 Input 41 Bit Adders := 9
- 3 Input 41 Bit Adders := 1
- 2 Input 34 Bit Adders := 3
- 3 Input 33 Bit Adders := 18
- 2 Input 32 Bit Adders := 75
- 3 Input 32 Bit Adders := 57
- 2 Input 30 Bit Adders := 18
- 3 Input 30 Bit Adders := 1
- 3 Input 29 Bit Adders := 1
- 2 Input 28 Bit Adders := 18
- 2 Input 26 Bit Adders := 25
- 3 Input 26 Bit Adders := 2
- 2 Input 25 Bit Adders := 11
- 3 Input 25 Bit Adders := 9
- 2 Input 23 Bit Adders := 54
- 2 Input 22 Bit Adders := 18
- 2 Input 18 Bit Adders := 2
- 3 Input 18 Bit Adders := 2
- 3 Input 16 Bit Adders := 1
- 2 Input 16 Bit Adders := 1
- 2 Input 15 Bit Adders := 2
- 2 Input 14 Bit Adders := 20
- 4 Input 14 Bit Adders := 1
- 3 Input 14 Bit Adders := 1
- 3 Input 13 Bit Adders := 2
- 2 Input 13 Bit Adders := 7
- 2 Input 12 Bit Adders := 13
- 3 Input 12 Bit Adders := 10
- 4 Input 11 Bit Adders := 1
- 2 Input 11 Bit Adders := 4
- 3 Input 10 Bit Adders := 2
- 2 Input 10 Bit Adders := 1
- 2 Input 9 Bit Adders := 11
- 3 Input 9 Bit Adders := 5
- 2 Input 8 Bit Adders := 5
- 2 Input 7 Bit Adders := 4
- 2 Input 6 Bit Adders := 24
- 3 Input 6 Bit Adders := 2
- 2 Input 5 Bit Adders := 41
- 2 Input 4 Bit Adders := 86
- 3 Input 4 Bit Adders := 1
- 3 Input 3 Bit Adders := 9
- 2 Input 3 Bit Adders := 34
- 2 Input 2 Bit Adders := 6
- 3 Input 2 Bit Adders := 4
- 4 Input 2 Bit Adders := 1
- 5 Input 2 Bit Adders := 1
- 3 Input 1 Bit Adders := 3
- 2 Input 1 Bit Adders := 41
-+---XORs :
- 2 Input 65 Bit XORs := 1
- 2 Input 64 Bit XORs := 6
- 2 Input 33 Bit XORs := 1
- 2 Input 32 Bit XORs := 8
- 2 Input 29 Bit XORs := 16
- 2 Input 17 Bit XORs := 44
- 2 Input 16 Bit XORs := 2
- 2 Input 15 Bit XORs := 2
- 2 Input 14 Bit XORs := 5
- 2 Input 12 Bit XORs := 4
- 2 Input 10 Bit XORs := 4
- 2 Input 5 Bit XORs := 38
- 2 Input 4 Bit XORs := 2
- 2 Input 3 Bit XORs := 24
- 2 Input 2 Bit XORs := 6
- 2 Input 1 Bit XORs := 420
- 3 Input 1 Bit XORs := 68
- 6 Input 1 Bit XORs := 19
- 7 Input 1 Bit XORs := 18
- 13 Input 1 Bit XORs := 90
- 11 Input 1 Bit XORs := 63
- 12 Input 1 Bit XORs := 63
- 8 Input 1 Bit XORs := 54
- 10 Input 1 Bit XORs := 72
- 4 Input 1 Bit XORs := 54
- 14 Input 1 Bit XORs := 117
- 5 Input 1 Bit XORs := 18
- 15 Input 1 Bit XORs := 9
- 9 Input 1 Bit XORs := 54
- 16 Input 1 Bit XORs := 9
-+---XORs :
- 5 Bit Wide XORs := 36
- 4 Bit Wide XORs := 36
- 3 Bit Wide XORs := 36
- 2 Bit Wide XORs := 36
-+---Registers :
- 310 Bit Registers := 9
- 130 Bit Registers := 1
- 107 Bit Registers := 1
- 104 Bit Registers := 1
- 92 Bit Registers := 2
- 90 Bit Registers := 3
- 87 Bit Registers := 1
- 65 Bit Registers := 44
- 64 Bit Registers := 26
- 62 Bit Registers := 2
- 58 Bit Registers := 2
- 56 Bit Registers := 1
- 55 Bit Registers := 13
- 53 Bit Registers := 1
- 52 Bit Registers := 2
- 51 Bit Registers := 8
- 50 Bit Registers := 9
- 49 Bit Registers := 2
- 48 Bit Registers := 77
- 46 Bit Registers := 18
- 45 Bit Registers := 2
- 43 Bit Registers := 1
- 41 Bit Registers := 11
- 40 Bit Registers := 9
- 36 Bit Registers := 3
- 34 Bit Registers := 25
- 33 Bit Registers := 30
- 32 Bit Registers := 206
- 31 Bit Registers := 90
- 30 Bit Registers := 28
- 29 Bit Registers := 6
- 28 Bit Registers := 20
- 27 Bit Registers := 1
- 26 Bit Registers := 67
- 24 Bit Registers := 40
- 22 Bit Registers := 136
- 21 Bit Registers := 9
- 20 Bit Registers := 2
- 18 Bit Registers := 9
- 17 Bit Registers := 3
- 16 Bit Registers := 18
- 15 Bit Registers := 53
- 14 Bit Registers := 50
- 13 Bit Registers := 9
- 12 Bit Registers := 21
- 10 Bit Registers := 30
- 9 Bit Registers := 13
- 8 Bit Registers := 113
- 7 Bit Registers := 12
- 6 Bit Registers := 83
- 5 Bit Registers := 106
- 4 Bit Registers := 217
- 3 Bit Registers := 153
- 2 Bit Registers := 215
- 1 Bit Registers := 1420
-+---Multipliers :
- 53x53 Multipliers := 1
- 66x66 Multipliers := 1
- 15x46 Multipliers := 4
- 25x30 Multipliers := 9
-+---RAMs :
- 8192K Bit (131072 X 64 bit) RAMs := 1
- 1472K Bit (16384 X 92 bit) RAMs := 1
- 832K Bit (16384 X 52 bit) RAMs := 1
- 816K Bit (16384 X 51 bit) RAMs := 1
- 768K Bit (16384 X 48 bit) RAMs := 1
- 576K Bit (16384 X 36 bit) RAMs := 1
- 128K Bit (32768 X 4 bit) RAMs := 1
- 16K Bit (512 X 32 bit) RAMs := 2
- 1K Bit (64 X 21 bit) RAMs := 1
-+---ROMs :
- ROMs := 6
-+---Muxes :
- 2 Input 2080 Bit Muxes := 1
- 2 Input 130 Bit Muxes := 3
- 2 Input 109 Bit Muxes := 1
- 2 Input 108 Bit Muxes := 1
- 2 Input 92 Bit Muxes := 6
- 2 Input 65 Bit Muxes := 18
- 4 Input 65 Bit Muxes := 1
- 2 Input 64 Bit Muxes := 121
- 4 Input 64 Bit Muxes := 7
- 2 Input 62 Bit Muxes := 1
- 2 Input 61 Bit Muxes := 2
- 2 Input 58 Bit Muxes := 2
- 2 Input 56 Bit Muxes := 5
- 2 Input 55 Bit Muxes := 11
- 2 Input 54 Bit Muxes := 3
- 2 Input 53 Bit Muxes := 2
- 2 Input 52 Bit Muxes := 16
- 2 Input 51 Bit Muxes := 5
- 2 Input 50 Bit Muxes := 10
- 2 Input 48 Bit Muxes := 3
- 2 Input 46 Bit Muxes := 27
- 2 Input 45 Bit Muxes := 21
- 3 Input 45 Bit Muxes := 2
- 2 Input 44 Bit Muxes := 4
- 2 Input 41 Bit Muxes := 7
- 2 Input 36 Bit Muxes := 6
- 7 Input 36 Bit Muxes := 1
- 2 Input 34 Bit Muxes := 30
- 2 Input 33 Bit Muxes := 39
- 2 Input 32 Bit Muxes := 321
- 3 Input 32 Bit Muxes := 1
- 4 Input 32 Bit Muxes := 1
- 2 Input 30 Bit Muxes := 9
- 2 Input 29 Bit Muxes := 9
- 2 Input 28 Bit Muxes := 1
- 2 Input 27 Bit Muxes := 4
- 2 Input 26 Bit Muxes := 15
- 2 Input 25 Bit Muxes := 25
- 2 Input 24 Bit Muxes := 97
- 2 Input 23 Bit Muxes := 65
- 2 Input 22 Bit Muxes := 78
- 2 Input 20 Bit Muxes := 4
- 2 Input 17 Bit Muxes := 1
- 2 Input 16 Bit Muxes := 13
- 3 Input 16 Bit Muxes := 1
- 7 Input 16 Bit Muxes := 1
- 2 Input 15 Bit Muxes := 18
- 2 Input 14 Bit Muxes := 62
- 7 Input 14 Bit Muxes := 1
- 2 Input 13 Bit Muxes := 20
- 2 Input 12 Bit Muxes := 51
- 2 Input 11 Bit Muxes := 2
- 2 Input 10 Bit Muxes := 13
- 2 Input 9 Bit Muxes := 34
- 3 Input 9 Bit Muxes := 1
- 2 Input 8 Bit Muxes := 210
- 8 Input 8 Bit Muxes := 18
- 2 Input 7 Bit Muxes := 20
- 7 Input 7 Bit Muxes := 1
- 4 Input 6 Bit Muxes := 1
- 2 Input 6 Bit Muxes := 65
- 3 Input 6 Bit Muxes := 3
- 7 Input 6 Bit Muxes := 3
- 2 Input 5 Bit Muxes := 58
- 4 Input 5 Bit Muxes := 1
- 5 Input 5 Bit Muxes := 3
- 3 Input 5 Bit Muxes := 2
- 2 Input 4 Bit Muxes := 121
- 4 Input 4 Bit Muxes := 3
- 8 Input 4 Bit Muxes := 1
- 3 Input 4 Bit Muxes := 1
- 7 Input 4 Bit Muxes := 2
- 2 Input 3 Bit Muxes := 176
- 6 Input 3 Bit Muxes := 3
- 8 Input 3 Bit Muxes := 3
- 4 Input 3 Bit Muxes := 3
- 3 Input 3 Bit Muxes := 28
- 7 Input 3 Bit Muxes := 1
- 5 Input 3 Bit Muxes := 2
- 2 Input 2 Bit Muxes := 157
- 16 Input 2 Bit Muxes := 1
- 3 Input 2 Bit Muxes := 13
- 4 Input 2 Bit Muxes := 5
- 7 Input 2 Bit Muxes := 1
- 8 Input 2 Bit Muxes := 1
- 2 Input 1 Bit Muxes := 1362
- 3 Input 1 Bit Muxes := 41
- 5 Input 1 Bit Muxes := 27
- 4 Input 1 Bit Muxes := 21
- 6 Input 1 Bit Muxes := 1
- 7 Input 1 Bit Muxes := 9
----------------------------------------------------------------------------------
-Finished RTL Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 840 (col length:140)
-BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 10. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv:136]
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (dfma/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_vec_reg' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3886] merging instance 'mem_ctrl_vec_reg' (FDE) to 'mem_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] )
-INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_typeTagIn_reg[1]' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\ex_reg_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\in_pipe_b_typeTagOut_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (\mem_ctrl_typeTagOut_reg[1] )
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[1]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[2]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[2]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[3]'
-INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[3]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[4]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (ifpu/\io_out_pipe_b_exc_reg[4] )
-INFO: [Synth 8-4471] merging register 's2_tlb_resp_pf_inst_reg' into 's2_tlb_resp_cacheable_reg' [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/Frontend.sv:127]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 16. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/MulDiv.sv:131]
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: register remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-DSP Report: operator remainder1 is absorbed into DSP remainder1.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[60]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[60]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[61]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[61]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[62]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[62]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[57]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[57]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[58]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[58]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[59]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[59]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[54]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[54]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[55]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[55]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[56]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[56]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[51]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[51]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[52]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[52]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[53]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[53]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[48]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[48]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[49]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[49]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[50]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[50]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[45]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[45]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[46]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[46]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[47]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[47]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[42]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[42]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[43]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[43]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[44]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[44]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[39]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[39]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[40]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[40]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[41]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[41]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[36]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[36]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[37]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[37]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[38]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[38]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[33]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[33]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[34]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[34]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[35]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[35]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[30]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[30]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[31]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[31]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[32]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[32]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[27]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[27]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[28]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[28]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[29]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[29]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[24]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[24]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[25]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[25]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[26]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[26]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[21]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[21]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[22]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[22]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[23]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[23]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[18]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[18]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[19]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[19]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[20]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[20]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[15]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[15]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[16]' (FDE) to 'core/ex_reg_cause_reg[5]'
-INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[16]' (FDE) to 'core/mem_reg_cause_reg[5]'
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_reg_cause_reg[5] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_mstatus_mpp_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mcountinhibit_reg[1] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mie_reg[0] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/\s1_pc_reg[0] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_mem_cmd_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_sel_alu2_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/s2_tlb_resp_cacheable_reg)
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[32] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[2] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[4] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[5] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[6] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[7] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[7] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[8] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[8] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[9] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[10] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[11] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[12] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[13] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[14] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[15] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[16] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[17] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[18] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[19] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[20] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[21] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[22] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[22] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[23] )
-INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[23] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[24] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[25] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[26] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[27] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[28] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[29] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[30] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[31] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[33] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[34] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[35] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[36] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[37] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[38] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[39] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[40] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[41] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[42] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[43] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[44] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[45] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[46] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[46] )
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[47] )
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_addr_reg' and it is trimmed from '34' to '32' bits. [/home/onur/Desktop/rocket/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:408]
-WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[3] driven by constant 0
-WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[2] driven by constant 0
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-WARNING: [Synth 8-6841] Block RAM (rockettile_dcache_data_arrays_0_ext/Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
-(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
-RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 4. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:129]
-DSP Report: Generating DSP freq_word0, operation Mode is: (A:0x6677)*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: A*(B:0x6677).
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x109).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x55).
-DSP Report: operator mult10 is absorbed into DSP mult10.
-DSP Report: Generating DSP mult20, operation Mode is: A*(B:0x75).
-DSP Report: operator mult20 is absorbed into DSP mult20.
-INFO: [Synth 8-5544] ROM "cordic_angle_lut_i/angle_o" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
-INFO: [Synth 8-4471] merging register 'prompt_abs_vld_reg' into 'cos2x_i/sqr_vld_reg' [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:107]
-DSP Report: Generating DSP cos2x_i/q_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
-DSP Report: Generating DSP cos2x_i/i_p_sqr0, operation Mode is: A*B.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__0) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[15]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[14]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[13]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[12]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[11]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[10]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[9]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[8]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[7]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[6]__1) is unused and will be removed from module NCO_carr.
-WARNING: [Synth 8-3332] Sequential element (freq_word_reg[5]__1) is unused and will be removed from module NCO_carr.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w0, operation Mode is: C+A*B.
-DSP Report: operator butterfly_i/x1_imag_w0 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w0.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w0, operation Mode is: C-A*B.
-DSP Report: operator butterfly_i/x1_real_w0 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w0.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP bd, operation Mode is: A*B.
-DSP Report: operator bd is absorbed into DSP bd.
-DSP Report: Generating DSP ac, operation Mode is: A*B.
-DSP Report: operator ac is absorbed into DSP ac.
-DSP Report: Generating DSP ad, operation Mode is: A*B.
-DSP Report: operator ad is absorbed into DSP ad.
-DSP Report: Generating DSP bc, operation Mode is: A*B.
-DSP Report: operator bc is absorbed into DSP bc.
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
-DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
-DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
-DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
-DSP Report: Generating DSP k0, operation Mode is: A*B.
-DSP Report: operator k0 is absorbed into DSP k0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP im_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: Generating DSP re_sqr0, operation Mode is: (PCIN>>17)+A*B.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
-INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM acq/i_acq_top/dual_port_ram_i/ram_reg to conserve power
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_IQ_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_code_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /ifft_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
-INFO: [Synth 8-4652] Swapped enable and write-enable on 26 RAM instances of RAM bram_i/ram_reg to conserve power
-INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
-INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:10 ; elapsed = 00:01:22 . Memory (MB): peak = 3037.090 ; gain = 1176.180 ; free physical = 211 ; free virtual = 11563
----------------------------------------------------------------------------------
- Sort Area is APBGpsBlock__GC0 p_1_out_0 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GC0 p_1_out_2 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GC0 p_1_out_3 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is APBGpsBlock__GC0 p_1_out_4 : 0 0 : 2790 2790 : Used 1 time 100
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 0 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 1 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 2 : 2812 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_4 : 0 3 : 3137 12223 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 0 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 1 : 2793 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 2 : 2812 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_6 : 0 3 : 3137 11879 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 0 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 1 : 2812 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 2 : 2793 11089 : Used 1 time 0
- Sort Area is RocketTile__GCB0 remainder1_8 : 0 3 : 2691 11089 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 0 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 1 : 3236 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 2 : 3255 9727 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 0 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 1 : 3101 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 2 : 3236 9573 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 0 : 3101 9322 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 1 : 3120 9322 : Used 1 time 0
- Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 2 : 3101 9322 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 im_sqr0_26 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 im_sqr0_26 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 re_sqr0_23 : 0 0 : 3406 4775 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 re_sqr0_23 : 0 1 : 1369 4775 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 0 : 3446 4760 : Used 1 time 0
- Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 1 : 1314 4760 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_1e : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_1e : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_20 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_20 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_18 : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_18 : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_1c : 0 0 : 1981 4634 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_1c : 0 1 : 2653 4634 : Used 1 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 0 : 3234 4210 : Used 9 time 0
- Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 1 : 976 4210 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 0 : 1789 3431 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_0 : 0 1 : 1642 3431 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 0 : 1785 3295 : Used 9 time 0
- Sort Area is tracking_wrapper freq_word0_3 : 0 1 : 1510 3295 : Used 9 time 0
- Sort Area is tracking_wrapper cos2x_i/i_p_sqr0_b : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is tracking_wrapper cos2x_i/q_p_sqr0_d : 0 0 : 3088 3088 : Used 9 time 0
- Sort Area is APBGpsBlock__GC0 ac_12 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 ad_16 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 bc_15 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 bd_14 : 0 0 : 2310 2310 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w0_c : 0 0 : 2196 2196 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w0_f : 0 0 : 2073 2073 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_e : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_a : 0 0 : 1981 1981 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_1f : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_21 : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_1a : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_1d : 0 0 : 1954 1954 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 port1_addr0_17 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 port1_addr0_5 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 port1_addr0_9 : 0 0 : 1357 1357 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 k0_11 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 k0_22 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is APBGpsBlock__GC0 k0_7 : 0 0 : 1238 1238 : Used 1 time 0
- Sort Area is tracking_wrapper mult10_6 : 0 0 : 433 433 : Used 9 time 0
- Sort Area is tracking_wrapper mult10_a : 0 0 : 403 403 : Used 9 time 0
- Sort Area is tracking_wrapper mult20_8 : 0 0 : 403 403 : Used 9 time 0
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-ROM: Preliminary Mapping Report
-+----------------+----------------------+---------------+----------------+
-|Module Name | RTL Object | Depth x Width | Implemented As |
-+----------------+----------------------+---------------+----------------+
-|TLROM | _GEN | 256x64 | LUT |
-|acq_nco_carr | freq_word_arr | 64x13 | LUT |
-|acq_nco_carr | pullin_freq_word_arr | 16x11 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_nco_carr | sinwav_lut | 32x6 | LUT |
-|acq_ca_gen | p_0_out | 32x8 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|NCO_carr | sinwav_lut | 128x6 | LUT |
-|cacode_gen_trck | p_0_out | 32x8 | LUT |
-+----------------+----------------------+---------------+----------------+
-
-
-Block RAM: Preliminary Mapping Report (see note below)
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GC0 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
-
-Distributed RAM: Preliminary Mapping Report (see note below)
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
-Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
-
-DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | (PCIN>>17)+A*B | 25 | 8 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 16 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|NCO_carr | (A:0x6677)*B | 14 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 14 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | A*(B:0x6677) | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17)+A*B | 18 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | A*(B:0x109) | 12 | 10 | - | - | 22 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x55) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_code | A*(B:0x75) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:37 ; elapsed = 00:01:29 . Memory (MB): peak = 3037.090 ; gain = 1176.180 ; free physical = 2639 ; free virtual = 14051
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:02:45 ; elapsed = 00:01:37 . Memory (MB): peak = 3049.184 ; gain = 1188.273 ; free physical = 2396 ; free virtual = 13809
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Block RAM: Final Mapping Report
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
-|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
-|APBGpsBlock__GC0 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
-|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
-|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
-|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
-|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
-|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
-+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
-
-
-Distributed RAM: Final Mapping Report
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
-|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
-|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
-|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
-|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
-|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
-|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
-|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
-|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
-+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:61]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:74]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:66]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:66]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:134]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv:100]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:78]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:79]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:301]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:301]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:301]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
-INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:02:50 ; elapsed = 00:01:47 . Memory (MB): peak = 3069.117 ; gain = 1208.207 ; free physical = 810 ; free virtual = 12227
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:02:57 ; elapsed = 00:01:54 . Memory (MB): peak = 3218.617 ; gain = 1357.707 ; free physical = 653 ; free virtual = 12109
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:02:57 ; elapsed = 00:01:54 . Memory (MB): peak = 3218.617 ; gain = 1357.707 ; free physical = 653 ; free virtual = 12109
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:03:06 ; elapsed = 00:02:03 . Memory (MB): peak = 3392.125 ; gain = 1531.215 ; free physical = 478 ; free virtual = 11935
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:03:07 ; elapsed = 00:02:04 . Memory (MB): peak = 3392.125 ; gain = 1531.215 ; free physical = 478 ; free virtual = 11935
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:03:08 ; elapsed = 00:02:05 . Memory (MB): peak = 3404.000 ; gain = 1543.090 ; free physical = 478 ; free virtual = 11934
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:03:08 ; elapsed = 00:02:05 . Memory (MB): peak = 3404.000 ; gain = 1543.090 ; free physical = 481 ; free virtual = 11937
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
-
-Static Shift Register Report:
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-|VCU118RocketSystem | tile_prci_domain/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-|VCU118RocketSystem | ibus/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
-+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
-
----------------------------------------------------------------------------------
-Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-DSP Final Report (the ' indicates corresponding REG is set)
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C+A*B | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
-|butterfly | C-(A*B) | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 15 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 15 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN>>17+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | A*B' | 24 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
-|MulAddRecFNPipe_l2_e8_s24 | PCIN>>17+A*B | 24 | 7 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
-+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
-
-
-Report BlackBoxes:
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage:
-+------+-----------+------+
-| |Cell |Count |
-+------+-----------+------+
-|1 |BSCANE2 | 1|
-|2 |BUFG | 6|
-|3 |CARRY4 | 5424|
-|4 |DSP48E1 | 172|
-|10 |LUT1 | 2664|
-|11 |LUT2 | 13495|
-|12 |LUT3 | 10208|
-|13 |LUT4 | 7488|
-|14 |LUT5 | 11661|
-|15 |LUT6 | 23530|
-|16 |MMCME2_ADV | 1|
-|17 |MUXF7 | 1706|
-|18 |MUXF8 | 140|
-|19 |RAM32M | 225|
-|20 |RAM32X1D | 5|
-|21 |RAMB18E1 | 4|
-|23 |RAMB36E1 | 415|
-|45 |SRL16E | 2|
-|46 |STARTUPE2 | 1|
-|47 |FDCE | 26617|
-|48 |FDPE | 349|
-|49 |FDRE | 10100|
-|50 |FDSE | 130|
-|51 |LDC | 9|
-|52 |IBUF | 8|
-|53 |IBUFDS | 1|
-|54 |IOBUF | 8|
-|55 |OBUF | 12|
-+------+-----------+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:03:08 ; elapsed = 00:02:05 . Memory (MB): peak = 3404.000 ; gain = 1543.090 ; free physical = 481 ; free virtual = 11937
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 589 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:02:59 ; elapsed = 00:02:01 . Memory (MB): peak = 3407.914 ; gain = 1265.941 ; free physical = 7365 ; free virtual = 18822
-Synthesis Optimization Complete : Time (s): cpu = 00:03:08 ; elapsed = 00:02:09 . Memory (MB): peak = 3407.914 ; gain = 1547.004 ; free physical = 7371 ; free virtual = 18818
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.69 . Memory (MB): peak = 3407.914 ; gain = 0.000 ; free physical = 7400 ; free virtual = 18847
-INFO: [Netlist 29-17] Analyzing 8111 Unisim elements for replacement
-INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-570] Preparing netlist for logic optimization
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc]
-Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-Finished Parsing XDC File [/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3578.383 ; gain = 0.000 ; free physical = 7352 ; free virtual = 18800
-INFO: [Project 1-111] Unisim Transformation Summary:
- A total of 247 instances were transformed.
- IOBUF => IOBUF (IBUF, OBUFT): 8 instances
- LDC => LDCE: 9 instances
- RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 225 instances
- RAM32X1D => RAM32X1D (RAMD32(x2)): 5 instances
-
-Synth Design complete | Checksum: 6197de4
-INFO: [Common 17-83] Releasing license: Synthesis
-650 Infos, 393 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:03:23 ; elapsed = 00:02:25 . Memory (MB): peak = 3578.418 ; gain = 1918.461 ; free physical = 7356 ; free virtual = 18804
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 10055.043; main = 2799.705; forked = 8217.472
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19247.062; main = 3578.387; forked = 16213.887
-# apply_genesys2_async_clock_groups
-Applying Genesys2 async clock groups.
-# write_checkpoint -force [file join $checkpoint_dir post_synth.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3610.398 ; gain = 0.000 ; free physical = 7337 ; free virtual = 18801
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.398 ; gain = 0.000 ; free physical = 7337 ; free virtual = 18801
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.398 ; gain = 0.000 ; free physical = 7337 ; free virtual = 18801
-Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.398 ; gain = 0.000 ; free physical = 7337 ; free virtual = 18801
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.398 ; gain = 0.000 ; free physical = 7337 ; free virtual = 18801
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3610.398 ; gain = 0.000 ; free physical = 7337 ; free virtual = 18802
-Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3610.398 ; gain = 0.000 ; free physical = 7337 ; free virtual = 18802
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3610.398 ; gain = 0.000 ; free physical = 7321 ; free virtual = 18797
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_synth.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 3610.398 ; gain = 31.980 ; free physical = 7205 ; free virtual = 18722
-# report_utilization -hierarchical -file [file join $report_dir synth_utilization_hier.rpt]
-# report_utilization -file [file join $report_dir synth_utilization.rpt]
-# report_timing_summary -file [file join $report_dir synth_timing_summary.rpt]
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs
-report_timing_summary: Time (s): cpu = 00:00:34 ; elapsed = 00:00:07 . Memory (MB): peak = 3610.398 ; gain = 0.000 ; free physical = 7257 ; free virtual = 18774
-# puts "Running implementation..."
-Running implementation...
-# opt_design
-Command: opt_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-Running DRC as a precondition to command opt_design
-
-Starting DRC Task
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Project 1-461] DRC finished with 0 Errors
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.44 . Memory (MB): peak = 3656.961 ; gain = 46.562 ; free physical = 7255 ; free virtual = 18773
-
-Starting Cache Timing Information Task
-Ending Cache Timing Information Task | Checksum: 187aa4b3e
-
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3656.961 ; gain = 0.000 ; free physical = 7255 ; free virtual = 18773
-
-Starting Logic Optimization Task
-
-Phase 1 Initialization
-
-Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 187aa4b3e
-
-Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3690.773 ; gain = 0.000 ; free physical = 7209 ; free virtual = 18726
-
-Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 187aa4b3e
-
-Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3690.773 ; gain = 0.000 ; free physical = 7209 ; free virtual = 18726
-Phase 1 Initialization | Checksum: 187aa4b3e
-
-Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3690.773 ; gain = 0.000 ; free physical = 7209 ; free virtual = 18726
-
-Phase 2 Timer Update And Timing Data Collection
-
-Phase 2.1 Detect if minReqCache needed
-Phase 2.1 Detect if minReqCache needed | Checksum: 187aa4b3e
-
-Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7185 ; free virtual = 18703
-
-Phase 2.2 Timer Update
-Phase 2.2 Timer Update | Checksum: 187aa4b3e
-
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7188 ; free virtual = 18705
-
-Phase 2.3 Timing Data Collection
-Phase 2.3 Timing Data Collection | Checksum: 187aa4b3e
-
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7188 ; free virtual = 18705
-Phase 2 Timer Update And Timing Data Collection | Checksum: 187aa4b3e
-
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7188 ; free virtual = 18705
-
-Phase 3 Retarget
-INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
-INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
-INFO: [Opt 31-1566] Pulled 26 inverters resulting in an inversion of 491 pins
-INFO: [Opt 31-138] Pushed 14 inverter(s) to 129 load pin(s).
-INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 15923115e
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7192 ; free virtual = 18709
-Retarget | Checksum: 15923115e
-INFO: [Opt 31-389] Phase Retarget created 474 cells and removed 513 cells
-INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 4 Constant propagation
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 1603ad24b
-
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7196 ; free virtual = 18713
-Constant propagation | Checksum: 1603ad24b
-INFO: [Opt 31-389] Phase Constant propagation created 1 cells and removed 1 cells
-
-Phase 5 Sweep
-INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
-Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3706.773 ; gain = 0.000 ; free physical = 7196 ; free virtual = 18713
-Phase 5 Sweep | Checksum: 13cbdf333
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7196 ; free virtual = 18713
-Sweep | Checksum: 13cbdf333
-INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 3 cells
-INFO: [Opt 31-1021] In phase Sweep, 360 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
-
-Phase 6 BUFG optimization
-Phase 6 BUFG optimization | Checksum: 13cbdf333
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7200 ; free virtual = 18718
-BUFG optimization | Checksum: 13cbdf333
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
-
-Phase 7 Shift Register Optimization
-INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 13cbdf333
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7200 ; free virtual = 18717
-Shift Register Optimization | Checksum: 13cbdf333
-INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
-
-Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 13cbdf333
-
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7200 ; free virtual = 18717
-Post Processing Netlist | Checksum: 13cbdf333
-INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
-
-Phase 9 Finalization
-
-Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1cebe5e59
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7205 ; free virtual = 18723
-
-Phase 9.2 Verifying Netlist Connectivity
-
-Starting Connectivity Check Task
-
-Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3706.773 ; gain = 0.000 ; free physical = 7207 ; free virtual = 18724
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 1cebe5e59
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7207 ; free virtual = 18724
-Phase 9 Finalization | Checksum: 1cebe5e59
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7207 ; free virtual = 18724
-Opt_design Change Summary
-=========================
-
-
--------------------------------------------------------------------------------------------------------------------------
-| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
--------------------------------------------------------------------------------------------------------------------------
-| Retarget | 474 | 513 | 1 |
-| Constant propagation | 1 | 1 | 0 |
-| Sweep | 0 | 3 | 360 |
-| BUFG optimization | 0 | 0 | 0 |
-| Shift Register Optimization | 0 | 0 | 0 |
-| Post Processing Netlist | 0 | 0 | 0 |
--------------------------------------------------------------------------------------------------------------------------
-
-
-Ending Logic Optimization Task | Checksum: 1cebe5e59
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 3706.773 ; gain = 16.000 ; free physical = 7207 ; free virtual = 18724
-
-Starting Power Optimization Task
-INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-INFO: [Power 33-23] Power model is not available for u_cfg_flash_startup
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running Vector-less Activity Propagation...
-
-Finished Running Vector-less Activity Propagation
-INFO: [Pwropt 34-9] Applying IDT optimizations ...
-INFO: [Pwropt 34-10] Applying ODC optimizations ...
-
-
-Starting PowerOpt Patch Enables Task
-INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 419 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
-INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
-Number of BRAM Ports augmented: 0 newly gated: 84 Total Ports: 838
-Ending PowerOpt Patch Enables Task | Checksum: 275274135
-
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.95 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6779 ; free virtual = 18301
-Ending Power Optimization Task | Checksum: 275274135
-
-Time (s): cpu = 00:00:34 ; elapsed = 00:00:20 . Memory (MB): peak = 4322.688 ; gain = 615.914 ; free physical = 6779 ; free virtual = 18301
-
-Starting Final Cleanup Task
-
-Starting Logic Optimization Task
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Logic Optimization Task | Checksum: 1a7e25b41
-
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18274
-Ending Final Cleanup Task | Checksum: 1a7e25b41
-
-Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18274
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18274
-INFO: [Common 17-83] Releasing license: Implementation
-29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-opt_design completed successfully
-opt_design: Time (s): cpu = 00:00:58 ; elapsed = 00:00:33 . Memory (MB): peak = 4322.688 ; gain = 712.289 ; free physical = 6753 ; free virtual = 18274
-# write_checkpoint -force [file join $checkpoint_dir post_opt.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18274
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18274
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18274
-Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18274
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18274
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18275
-Write Physdb Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18275
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.1 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6747 ; free virtual = 18280
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_opt.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6634 ; free virtual = 18200
-# place_design
-Command: place_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-83] Releasing license: Implementation
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running DRC as a precondition to command place_design
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 12 CPUs
-
-Starting Placer Task
-
-Phase 1 Placer Initialization
-
-Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6655 ; free virtual = 18222
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12534bfb4
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6655 ; free virtual = 18222
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6655 ; free virtual = 18222
-
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1198e6a86
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6676 ; free virtual = 18247
-
-Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 18b1e680c
-
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:15 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6706 ; free virtual = 18278
-
-Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 18b1e680c
-
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:15 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6706 ; free virtual = 18278
-Phase 1 Placer Initialization | Checksum: 18b1e680c
-
-Time (s): cpu = 00:00:44 ; elapsed = 00:00:15 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6706 ; free virtual = 18278
-
-Phase 2 Global Placement
-
-Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 1f85b603a
-
-Time (s): cpu = 00:01:10 ; elapsed = 00:00:21 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6746 ; free virtual = 18318
-
-Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18fd79fc3
-
-Time (s): cpu = 00:01:36 ; elapsed = 00:00:26 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6739 ; free virtual = 18312
-
-Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 18fd79fc3
-
-Time (s): cpu = 00:01:37 ; elapsed = 00:00:26 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6739 ; free virtual = 18311
-
-Phase 2.4 Global Place Phase1
-Phase 2.4 Global Place Phase1 | Checksum: 17daeba8b
-
-Time (s): cpu = 00:03:06 ; elapsed = 00:00:58 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6750 ; free virtual = 18323
-
-Phase 2.5 Global Place Phase2
-
-Phase 2.5.1 UpdateTiming Before Physical Synthesis
-Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 13a562b47
-
-Time (s): cpu = 00:03:34 ; elapsed = 00:01:04 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6749 ; free virtual = 18322
-
-Phase 2.5.2 Physical Synthesis In Placer
-INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 3974 LUT instances to create LUTNM shape
-INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
-INFO: [Physopt 32-1138] End 1 Pass. Optimized 1037 nets or LUTs. Breaked 0 LUT, combined 1037 existing LUTs and moved 0 existing LUT
-INFO: [Physopt 32-65] No nets found for high-fanout optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
-INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
-INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
-INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6747 ; free virtual = 18322
-
-Summary of Physical Synthesis Optimizations
-============================================
-
-
------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
------------------------------------------------------------------------------------------------------------------------------------------------------------
-| LUT Combining | 0 | 1037 | 1037 | 0 | 1 | 00:00:02 |
-| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Total | 0 | 1037 | 1037 | 0 | 9 | 00:00:02 |
------------------------------------------------------------------------------------------------------------------------------------------------------------
-
-
-Phase 2.5.2 Physical Synthesis In Placer | Checksum: 225f84e8d
-
-Time (s): cpu = 00:04:03 ; elapsed = 00:01:13 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6746 ; free virtual = 18321
-Phase 2.5 Global Place Phase2 | Checksum: 195623102
-
-Time (s): cpu = 00:04:08 ; elapsed = 00:01:16 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6746 ; free virtual = 18321
-Phase 2 Global Placement | Checksum: 195623102
-
-Time (s): cpu = 00:04:08 ; elapsed = 00:01:16 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6746 ; free virtual = 18321
-
-Phase 3 Detail Placement
-
-Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 1654936c9
-
-Time (s): cpu = 00:04:36 ; elapsed = 00:01:21 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6744 ; free virtual = 18319
-
-Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1f7d8b624
-
-Time (s): cpu = 00:05:24 ; elapsed = 00:01:34 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6765 ; free virtual = 18340
-
-Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 2472bbc8a
-
-Time (s): cpu = 00:05:25 ; elapsed = 00:01:34 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6765 ; free virtual = 18340
-
-Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 22798a5c4
-
-Time (s): cpu = 00:05:25 ; elapsed = 00:01:34 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6765 ; free virtual = 18340
-
-Phase 3.5 Fast Optimization
-Phase 3.5 Fast Optimization | Checksum: 2950c2c70
-
-Time (s): cpu = 00:06:15 ; elapsed = 00:01:45 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6780 ; free virtual = 18355
-
-Phase 3.6 Small Shape Detail Placement
-Phase 3.6 Small Shape Detail Placement | Checksum: 20d8e4ae8
-
-Time (s): cpu = 00:06:38 ; elapsed = 00:02:20 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6775 ; free virtual = 18350
-
-Phase 3.7 Re-assign LUT pins
-Phase 3.7 Re-assign LUT pins | Checksum: 2a02c100e
-
-Time (s): cpu = 00:06:42 ; elapsed = 00:02:23 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6775 ; free virtual = 18350
-
-Phase 3.8 Pipeline Register Optimization
-Phase 3.8 Pipeline Register Optimization | Checksum: 16bcb8537
-
-Time (s): cpu = 00:06:42 ; elapsed = 00:02:23 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6775 ; free virtual = 18350
-
-Phase 3.9 Fast Optimization
-Phase 3.9 Fast Optimization | Checksum: 18a947596
-
-Time (s): cpu = 00:07:45 ; elapsed = 00:02:36 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6911 ; free virtual = 18486
-Phase 3 Detail Placement | Checksum: 18a947596
-
-Time (s): cpu = 00:07:45 ; elapsed = 00:02:36 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6911 ; free virtual = 18486
-
-Phase 4 Post Placement Optimization and Clean-Up
-
-Phase 4.1 Post Commit Optimization
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-
-Phase 4.1.1 Post Placement Optimization
-Post Placement Optimization Initialization | Checksum: 1db4023f7
-
-Phase 4.1.1.1 BUFG Insertion
-
-Starting Physical Synthesis Task
-
-Phase 1 Physical Synthesis Initialization
-INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 12 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.203 | TNS=-1.675 |
-Phase 1 Physical Synthesis Initialization | Checksum: 1c69f3946
-
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.6 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6848 ; free virtual = 18424
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/apbReset_gps_apb_reset/io_sync_reset_chain/output_chain/sync_0_reg_1, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_1, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
-INFO: [Place 46-56] BUFG insertion identified 10 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 10, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
-Ending Physical Synthesis Task | Checksum: 1b4f0b8af
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6847 ; free virtual = 18423
-Phase 4.1.1.1 BUFG Insertion | Checksum: 1db4023f7
-
-Time (s): cpu = 00:08:32 ; elapsed = 00:02:47 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6847 ; free virtual = 18423
-
-Phase 4.1.1.2 Post Placement Timing Optimization
-INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.115. For the most accurate timing information please run report_timing.
-Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 21dfd6790
-
-Time (s): cpu = 00:09:32 ; elapsed = 00:03:06 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18397
-
-Time (s): cpu = 00:09:32 ; elapsed = 00:03:06 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18397
-Phase 4.1 Post Commit Optimization | Checksum: 21dfd6790
-
-Time (s): cpu = 00:09:33 ; elapsed = 00:03:07 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-
-Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 21dfd6790
-
-Time (s): cpu = 00:09:33 ; elapsed = 00:03:07 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-
-Phase 4.3 Placer Reporting
-
-Phase 4.3.1 Print Estimated Congestion
-INFO: [Place 30-612] Post-Placement Estimated Congestion
- ____________________________________________________
-| | Global Congestion | Short Congestion |
-| Direction | Region Size | Region Size |
-|___________|___________________|___________________|
-| North| 1x1| 4x4|
-|___________|___________________|___________________|
-| South| 1x1| 4x4|
-|___________|___________________|___________________|
-| East| 4x4| 4x4|
-|___________|___________________|___________________|
-| West| 1x1| 2x2|
-|___________|___________________|___________________|
-
-Phase 4.3.1 Print Estimated Congestion | Checksum: 21dfd6790
-
-Time (s): cpu = 00:09:34 ; elapsed = 00:03:07 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-Phase 4.3 Placer Reporting | Checksum: 21dfd6790
-
-Time (s): cpu = 00:09:34 ; elapsed = 00:03:07 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-
-Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-
-Time (s): cpu = 00:09:34 ; elapsed = 00:03:07 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 22880d014
-
-Time (s): cpu = 00:09:35 ; elapsed = 00:03:07 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-Ending Placer Task | Checksum: 1793fa97e
-
-Time (s): cpu = 00:09:35 ; elapsed = 00:03:08 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-47 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-place_design completed successfully
-place_design: Time (s): cpu = 00:09:44 ; elapsed = 00:03:11 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-# write_checkpoint -force [file join $checkpoint_dir post_place.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6820 ; free virtual = 18396
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.13 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6800 ; free virtual = 18395
-Wrote PlaceStorage: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6690 ; free virtual = 18370
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6682 ; free virtual = 18370
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6682 ; free virtual = 18371
-Write Physdb Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6682 ; free virtual = 18371
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_place.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6673 ; free virtual = 18313
-# phys_opt_design -directive Explore
-Command: phys_opt_design -directive Explore
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
-
-Starting Initial Update Timing Task
-
-Time (s): cpu = 00:00:37 ; elapsed = 00:00:07 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6721 ; free virtual = 18360
-INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 39.46s | WALL: 7.86s
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6721 ; free virtual = 18360
-
-Starting Physical Synthesis Task
-
-Phase 1 Physical Synthesis Initialization
-INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 12 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.115 | TNS=-0.813 |
-Phase 1 Physical Synthesis Initialization | Checksum: 1a4f6b5ee
-
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6725 ; free virtual = 18365
-
-Phase 2 SLR Crossing Optimization
-Phase 2 SLR Crossing Optimization | Checksum: 1a4f6b5ee
-
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6725 ; free virtual = 18365
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.115 | TNS=-0.813 |
-
-Phase 3 Fanout Optimization
-INFO: [Physopt 32-64] No nets found for fanout-optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 3 Fanout Optimization | Checksum: 1a4f6b5ee
-
-Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6727 ; free virtual = 18367
-
-Phase 4 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 183 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[32]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_4
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[36]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_4__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_4
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[37]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[37]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_2__2
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[32]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[33]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_2__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_2__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[33]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_1__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_1__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_2__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_2__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_3__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_3__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_4__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_4__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_1__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_1__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[41]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[36]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_4__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__8_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_2
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[40]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[41]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_2__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_2__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_3__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_3__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[73]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_37_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__5_i_1__0
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[11]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_5_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_5_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__1_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_4__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_4__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_4
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[16]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_8_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[75]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_37_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_7_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__2_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_5_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__1_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_3_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__0_i_3__1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[17]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_8_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_1__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_1__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_5_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__1_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_7_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__2_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_5_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__1_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__4_i_1__0
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[43]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_21_i_3__0
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[43]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_21_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__4_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__4_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_21_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__9_i_4
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[78]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_39_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__9_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__9_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__4_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_38_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__6_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[39]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_19_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__8_i_1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[16]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_8_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_7_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__2_i_4__1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[28]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_14_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_4
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[39]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_19_i_1__1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[79]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_39_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_4
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[29]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_14_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__8_i_2
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[89]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_45_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__10_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__10_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__11_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__11_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_40_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__7_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_42_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__8_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_44_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__9_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__12_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__12_i_2
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/port2_wr_data[90]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_45_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_40_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__7_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_40_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__7_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_42_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_42_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__8_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_44_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__9_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_44_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__9_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[42]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_21_i_4__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_40_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__7_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_42_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__8_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_44_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__9_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[19]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_9_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_3_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__0_i_3__1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[66]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_34_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__7_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__7_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_34_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__4_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[31]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_15_i_3__1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[18]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_9_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__4_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_3_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__0_i_1__1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[82]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_42_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__7_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__7_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__5_i_3
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[81]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_41_i_3
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[80]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_40_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_38_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__6_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_40_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__7_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_42_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__8_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_44_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__9_i_1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[4]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_2_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__1_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__1_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_3_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__0_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__4_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_40_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__7_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_42_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__8_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_44_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__9_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_7_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__2_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_40_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__7_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_42_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_44_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__9_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_21_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__9_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__10_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__10_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__11_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__11_i_4
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[30]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_15_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__12_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__12_i_4
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[25]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_12_i_3__2
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[31]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_15_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_34_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__4_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__7_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__7_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[84]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_43_i_4
-INFO: [Physopt 32-661] Optimized 27 nets. Re-placed 27 instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 27 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 27 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.115 | TNS=-0.707 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6730 ; free virtual = 18370
-Phase 4 Single Cell Placement Optimization | Checksum: 157911829
-
-Time (s): cpu = 00:00:52 ; elapsed = 00:00:15 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6730 ; free virtual = 18370
-
-Phase 5 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 5 Multi Cell Placement Optimization | Checksum: 157911829
-
-Time (s): cpu = 00:00:53 ; elapsed = 00:00:15 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6730 ; free virtual = 18370
-
-Phase 6 Rewire
-INFO: [Physopt 32-246] Starting Signal Push optimization...
-INFO: [Physopt 32-241] No nets found for rewiring () optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6731 ; free virtual = 18371
-Phase 6 Rewire | Checksum: 157911829
-
-Time (s): cpu = 00:00:53 ; elapsed = 00:00:15 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6731 ; free virtual = 18371
-
-Phase 7 Critical Cell Optimization
-INFO: [Physopt 32-68] No nets found for critical-cell optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 7 Critical Cell Optimization | Checksum: 157911829
-
-Time (s): cpu = 00:00:53 ; elapsed = 00:00:15 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6731 ; free virtual = 18371
-
-Phase 8 Fanout Optimization
-INFO: [Physopt 32-64] No nets found for fanout-optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 8 Fanout Optimization | Checksum: 157911829
-
-Time (s): cpu = 00:00:53 ; elapsed = 00:00:15 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6731 ; free virtual = 18371
-
-Phase 9 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 119 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[32]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[37]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[36]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_4__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[33]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_3__1
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[32]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_2__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_2__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[33]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_1__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_1__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_2__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_2__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_3__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_3__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[37]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_4__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_4__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_1__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_1__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[36]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_4__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[41]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_2__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_2__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_3__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_3__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[73]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_37_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_4__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_4__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[75]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_37_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_3__0
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[41]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_1__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_1__62
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[40]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__4_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__4_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[39]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_19_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__8_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[39]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_19_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[42]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_21_i_4__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[19]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_9_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_7_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__2_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_5_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__1_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[31]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_15_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[43]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_21_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__4_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__7_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__7_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__4_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__1_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__1_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_21_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__9_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_34_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__4_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[84]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_43_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__10_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__10_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__9_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__9_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_40_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__7_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_42_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__8_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_7_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__2_i_3__1
-INFO: [Physopt 32-661] Optimized 3 nets. Re-placed 3 instances.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 3 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 3 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.115 | TNS=-0.704 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6732 ; free virtual = 18371
-Phase 9 Single Cell Placement Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:23 ; elapsed = 00:00:22 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6732 ; free virtual = 18371
-
-Phase 10 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 10 Multi Cell Placement Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:23 ; elapsed = 00:00:22 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6732 ; free virtual = 18371
-
-Phase 11 Rewire
-INFO: [Physopt 32-246] Starting Signal Push optimization...
-INFO: [Physopt 32-241] No nets found for rewiring () optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6732 ; free virtual = 18371
-Phase 11 Rewire | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:23 ; elapsed = 00:00:22 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6732 ; free virtual = 18371
-
-Phase 12 Critical Cell Optimization
-INFO: [Physopt 32-68] No nets found for critical-cell optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 12 Critical Cell Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:23 ; elapsed = 00:00:22 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6732 ; free virtual = 18371
-
-Phase 13 SLR Crossing Optimization
-Phase 13 SLR Crossing Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:23 ; elapsed = 00:00:22 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6732 ; free virtual = 18371
-
-Phase 14 Fanout Optimization
-INFO: [Physopt 32-64] No nets found for fanout-optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 14 Fanout Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:24 ; elapsed = 00:00:23 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6732 ; free virtual = 18371
-
-Phase 15 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 119 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[32]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[37]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[36]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_4__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[33]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[32]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_2__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_2__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[33]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_1__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_1__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_2__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_2__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_3__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_3__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[37]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_4__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_4__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_1__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_1__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[36]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_4__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[41]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_2__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_2__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_3__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_3__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[73]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_37_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_4__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_4__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[75]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_37_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[41]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_1__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_1__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__4_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__4_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[39]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_19_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__8_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[39]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_19_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[42]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_21_i_4__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[19]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_9_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_7_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__2_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_5_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__1_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[31]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_15_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[43]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_21_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__4_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__7_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__7_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__4_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__1_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__1_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_21_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__9_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_34_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__4_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[84]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_43_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__10_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__10_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__9_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__9_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_40_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__7_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_42_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__8_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_7_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__2_i_3__1
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6740 ; free virtual = 18380
-Phase 15 Single Cell Placement Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:55 ; elapsed = 00:00:29 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6740 ; free virtual = 18380
-
-Phase 16 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 16 Multi Cell Placement Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:55 ; elapsed = 00:00:29 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6740 ; free virtual = 18380
-
-Phase 17 Rewire
-INFO: [Physopt 32-246] Starting Signal Push optimization...
-INFO: [Physopt 32-241] No nets found for rewiring () optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6740 ; free virtual = 18380
-Phase 17 Rewire | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:56 ; elapsed = 00:00:30 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6740 ; free virtual = 18380
-
-Phase 18 Critical Cell Optimization
-INFO: [Physopt 32-68] No nets found for critical-cell optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 18 Critical Cell Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:56 ; elapsed = 00:00:30 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6740 ; free virtual = 18380
-
-Phase 19 DSP Register Optimization
-INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 19 DSP Register Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:56 ; elapsed = 00:00:30 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6740 ; free virtual = 18380
-
-Phase 20 BRAM Register Optimization
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_10' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_11' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_12' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_13' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_14' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_15' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_16' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_17' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_18' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_19' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_20' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_21' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_22' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_23' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_8' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/coh_ram_inst/ram_reg_9' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_imag_reg_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/twiddle_ram_i/tw_real_reg_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_2_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_0_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_2_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_4' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_5' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_6' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_7' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_0' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_1' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_2' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Physopt 32-614] Property 'READ_WIDTH_B' on BRAM cell 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_0_3' Port 'B' is 0. Skip BRAM Register Optimization on the port
-INFO: [Common 17-14] Message 'Physopt 32-614' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 20 BRAM Register Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:56 ; elapsed = 00:00:30 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6740 ; free virtual = 18380
-
-Phase 21 URAM Register Optimization
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 21 URAM Register Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:56 ; elapsed = 00:00:30 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6739 ; free virtual = 18379
-
-Phase 22 Shift Register Optimization
-INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
-INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 22 Shift Register Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:56 ; elapsed = 00:00:30 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6739 ; free virtual = 18379
-
-Phase 23 DSP Register Optimization
-INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 23 DSP Register Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:56 ; elapsed = 00:00:30 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6739 ; free virtual = 18379
-
-Phase 24 BRAM Register Optimization
-INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 24 BRAM Register Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:56 ; elapsed = 00:00:30 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6739 ; free virtual = 18379
-
-Phase 25 URAM Register Optimization
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 25 URAM Register Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:56 ; elapsed = 00:00:30 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6739 ; free virtual = 18379
-
-Phase 26 Shift Register Optimization
-INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
-INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 26 Shift Register Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:56 ; elapsed = 00:00:30 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6739 ; free virtual = 18379
-
-Phase 27 Critical Pin Optimization
-INFO: [Physopt 32-606] Identified 100 candidate nets for critical-pin optimization.
-INFO: [Physopt 32-608] Optimized 20 nets. Swapped 187 pins.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 20 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 187 existing cells
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.066 | TNS=-0.211 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6739 ; free virtual = 18380
-Phase 27 Critical Pin Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:57 ; elapsed = 00:00:31 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6739 ; free virtual = 18380
-
-Phase 28 Very High Fanout Optimization
-INFO: [Physopt 32-65] No nets found for high-fanout optimization.
-INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 28 Very High Fanout Optimization | Checksum: 145353a0b
-
-Time (s): cpu = 00:01:57 ; elapsed = 00:00:31 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6739 ; free virtual = 18380
-
-Phase 29 Single Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 101 candidate nets for placement-based optimization.
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[35]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_1__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[32]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[37]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_3__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_3__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[34]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[33]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[32]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_2__2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_1__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_1__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[33]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_16_i_1__3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_2__63_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_2__63
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_1__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_1__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_2__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_2__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_4__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__0_i_4__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[36]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_4__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[37]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__9_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[36]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_18_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__6_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_3__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_3__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__6_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_4__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[41]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__7_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_1[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__7_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_13_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__5_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_1__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_1__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_2__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_2__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_4__62_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry__1_i_4__62
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[73]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_37_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_2__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_2__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_real_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__8_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[75]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_37_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_36_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_real_carry__5_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_2_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[41]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[2]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_2
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_17_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__7_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_0[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[19]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_9_i_3__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_3__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__3_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_1[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__4_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_7_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__2_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_5_1[0]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__1_i_4__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[40]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_20_i_2__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_0[3]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__4_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__4_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_1__0_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_1__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1_carry__0_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_1_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_11_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__4_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__1_i_3_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__1_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[39]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_19_i_3__0
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_19_0[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__8_i_3
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[39]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_19_i_1__1
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_4_n_0. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w0_carry__8_i_4
-INFO: [Physopt 32-662] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_7_1[1]. Did not re-place instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y0_imag_carry__2_i_3__1
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6737 ; free virtual = 18377
-Phase 29 Single Cell Placement Optimization | Checksum: 1c94e1d3d
-
-Time (s): cpu = 00:02:22 ; elapsed = 00:00:37 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6737 ; free virtual = 18377
-
-Phase 30 Multi Cell Placement Optimization
-INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
-INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance.
-INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Phase 30 Multi Cell Placement Optimization | Checksum: 1c94e1d3d
-
-Time (s): cpu = 00:02:22 ; elapsed = 00:00:37 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6737 ; free virtual = 18377
-
-Phase 31 SLR Crossing Optimization
-Phase 31 SLR Crossing Optimization | Checksum: 1c94e1d3d
-
-Time (s): cpu = 00:02:22 ; elapsed = 00:00:37 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6737 ; free virtual = 18377
-
-Phase 32 Critical Path Optimization
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.066 | TNS=-0.211 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/port1_rd_data[34]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net pll_gps_acq_clk. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/y0_imag[35]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/y0_imag_carry__6_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w[28]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_inferred__0/i__carry__0_n_7. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_inferred__0/i__carry_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[35]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4_n_88. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3_n_106. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/port2_rd_data[5]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/port1_rd_data[34]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net pll_gps_acq_clk. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/y0_imag[35]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w[28]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_inferred__0/i__carry__0_n_7. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[35]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_3__1
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[35]. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.057 | TNS=-0.192 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/y1_imag[35]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_0[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-663] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[35]. Re-placed instance u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_17_i_1__2
-INFO: [Physopt 32-735] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_wr_data_i[35]. Optimization improves timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.047 | TNS=-0.150 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[35]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4_n_88. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/port2_rd_data[5]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.047 | TNS=-0.150 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6738 ; free virtual = 18378
-Phase 32 Critical Path Optimization | Checksum: 146300f4c
-
-Time (s): cpu = 00:02:34 ; elapsed = 00:00:41 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6738 ; free virtual = 18378
-
-Phase 33 Critical Path Optimization
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.047 | TNS=-0.150 |
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/port1_rd_data[34]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net pll_gps_acq_clk. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/y0_imag[35]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/y0_imag_carry__6_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w[28]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_inferred__0/i__carry__0_n_7. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_inferred__0/i__carry_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[35]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4_n_88. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3_n_106. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/port2_rd_data[5]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/port1_rd_data[34]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net pll_gps_acq_clk. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/y0_imag[35]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_15_1[0]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w[28]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__8_i_3__0_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_inferred__0/i__carry__0_n_7. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/i__carry_i_3__63_n_0. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port1_wr_data_i[35]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4_n_88. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-702] Processed net u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/port2_rd_data[5]. Optimizations did not improve timing on the net.
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.047 | TNS=-0.150 |
-Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6736 ; free virtual = 18377
-Phase 33 Critical Path Optimization | Checksum: 146300f4c
-
-Time (s): cpu = 00:02:45 ; elapsed = 00:00:44 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6736 ; free virtual = 18377
-
-Phase 34 BRAM Enable Optimization
-Phase 34 BRAM Enable Optimization | Checksum: 146300f4c
-
-Time (s): cpu = 00:02:45 ; elapsed = 00:00:44 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6736 ; free virtual = 18377
-INFO: [Physopt 32-960] Skip hold-fix as initial WHS does not violate hold threshold 250 ps
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6736 ; free virtual = 18377
-INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.047 | TNS=-0.150 |
-
-Summary of Physical Synthesis Optimizations
-============================================
-
-
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Fanout | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:00 |
-| Single Cell Placement | 0.000 | 0.115 | 0 | 0 | 30 | 0 | 4 | 00:00:28 |
-| Multi Cell Placement | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 4 | 00:00:01 |
-| Rewire | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:00 |
-| Critical Cell | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:00 |
-| SLR Crossing | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:00 |
-| DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
-| BRAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
-| URAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
-| Shift Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 |
-| Critical Pin | 0.049 | 0.493 | 0 | 0 | 20 | 0 | 1 | 00:00:01 |
-| Very High Fanout | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| BRAM Enable | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
-| Critical Path | 0.019 | 0.061 | 0 | 0 | 2 | 0 | 2 | 00:00:06 |
-| Total | 0.068 | 0.669 | 0 | 0 | 52 | 0 | 33 | 00:00:37 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
-
-Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6736 ; free virtual = 18377
-Ending Physical Synthesis Task | Checksum: fc6d85d8
-
-Time (s): cpu = 00:02:45 ; elapsed = 00:00:44 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6736 ; free virtual = 18377
-INFO: [Common 17-83] Releasing license: Implementation
-781 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-phys_opt_design completed successfully
-phys_opt_design: Time (s): cpu = 00:03:23 ; elapsed = 00:00:52 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6736 ; free virtual = 18377
-# write_checkpoint -force [file join $checkpoint_dir post_phys_opt.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6736 ; free virtual = 18377
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6736 ; free virtual = 18377
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6736 ; free virtual = 18377
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6725 ; free virtual = 18376
-Wrote PlaceStorage: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6612 ; free virtual = 18350
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6604 ; free virtual = 18351
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6604 ; free virtual = 18352
-Write Physdb Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6604 ; free virtual = 18352
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_phys_opt.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6598 ; free virtual = 18301
-# route_design
-Command: route_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-
-
-Starting Routing Task
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 12 CPUs
-
-Phase 1 Build RT Design
-Checksum: PlaceDB: b824f3b ConstDB: 0 ShapeSum: 45c220c0 RouteDB: 287b7a50
-Post Restoration Checksum: NetGraph: c8cd44d2 | NumContArr: cde02344 | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 31bff5d50
-
-Time (s): cpu = 00:00:55 ; elapsed = 00:00:19 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6644 ; free virtual = 18348
-
-Phase 2 Router Initialization
-
-Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 31bff5d50
-
-Time (s): cpu = 00:00:55 ; elapsed = 00:00:19 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6644 ; free virtual = 18349
-
-Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 31bff5d50
-
-Time (s): cpu = 00:00:56 ; elapsed = 00:00:20 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6644 ; free virtual = 18349
- Number of Nodes with overlaps = 0
-
-Phase 2.3 Update Timing
-Phase 2.3 Update Timing | Checksum: 1d135d404
-
-Time (s): cpu = 00:01:49 ; elapsed = 00:00:31 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6512 ; free virtual = 18216
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.010 | TNS=-0.016 | WHS=-0.268 | THS=-2190.678|
-
-
-Phase 2.4 Soft Constraint Pins - Fast Budgeting
-Phase 2.4 Soft Constraint Pins - Fast Budgeting | Checksum: 2188a2af1
-
-Time (s): cpu = 00:02:01 ; elapsed = 00:00:34 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6513 ; free virtual = 18218
-
-Router Utilization Summary
- Global Vertical Routing Utilization = 0.0016883 %
- Global Horizontal Routing Utilization = 0.00150533 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 94383
- (Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 94365
- Number of Partially Routed Nets = 18
- Number of Node Overlaps = 3
-
-Phase 2 Router Initialization | Checksum: 22b0382d2
-
-Time (s): cpu = 00:02:03 ; elapsed = 00:00:34 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6513 ; free virtual = 18218
-
-Phase 3 Global Routing
-Phase 3 Global Routing | Checksum: 22b0382d2
-
-Time (s): cpu = 00:02:03 ; elapsed = 00:00:34 . Memory (MB): peak = 4322.688 ; gain = 0.000 ; free physical = 6513 ; free virtual = 18218
-
-Phase 4 Initial Routing
-
-Phase 4.1 Initial Net Routing Pass
-Phase 4.1 Initial Net Routing Pass | Checksum: 233338121
-
-Time (s): cpu = 00:02:51 ; elapsed = 00:00:47 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6373 ; free virtual = 18078
-Phase 4 Initial Routing | Checksum: 233338121
-
-Time (s): cpu = 00:02:51 ; elapsed = 00:00:47 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6373 ; free virtual = 18078
-INFO: [Route 35-580] Design has 1 pins with tight setup and hold constraints.
-
-The top 5 pins with tight setup and hold constraints:
-
-+====================+===================+=========================================================================================================+
-| Launch Setup Clock | Launch Hold Clock | Pin |
-+====================+===================+=========================================================================================================+
-| pll_gps_acq_clk | pll_gps_acq_clk | u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_20/DIADI[0] |
-+--------------------+-------------------+---------------------------------------------------------------------------------------------------------+
-
-File with complete list of pins: tight_setup_hold_pins.txt
-
-
-Phase 5 Rip-up And Reroute
-
-Phase 5.1 Global Iteration 0
- Number of Nodes with overlaps = 8665
- Number of Nodes with overlaps = 89
- Number of Nodes with overlaps = 8
- Number of Nodes with overlaps = 1
- Number of Nodes with overlaps = 0
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.205 | TNS=0.000 | WHS=N/A | THS=N/A |
-
-Phase 5.1 Global Iteration 0 | Checksum: 3212799f2
-
-Time (s): cpu = 00:03:51 ; elapsed = 00:01:11 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6383 ; free virtual = 18088
-Phase 5 Rip-up And Reroute | Checksum: 3212799f2
-
-Time (s): cpu = 00:03:52 ; elapsed = 00:01:11 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6383 ; free virtual = 18088
-
-Phase 6 Delay and Skew Optimization
-
-Phase 6.1 Delay CleanUp
-Phase 6.1 Delay CleanUp | Checksum: 3212799f2
-
-Time (s): cpu = 00:03:52 ; elapsed = 00:01:11 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6383 ; free virtual = 18088
-
-Phase 6.2 Clock Skew Optimization
-Phase 6.2 Clock Skew Optimization | Checksum: 3212799f2
-
-Time (s): cpu = 00:03:52 ; elapsed = 00:01:11 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6383 ; free virtual = 18088
-Phase 6 Delay and Skew Optimization | Checksum: 3212799f2
-
-Time (s): cpu = 00:03:52 ; elapsed = 00:01:11 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6383 ; free virtual = 18088
-
-Phase 7 Post Hold Fix
-
-Phase 7.1 Hold Fix Iter
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.205 | TNS=0.000 | WHS=0.057 | THS=0.000 |
-
-Phase 7.1 Hold Fix Iter | Checksum: 31892488d
-
-Time (s): cpu = 00:03:59 ; elapsed = 00:01:12 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6386 ; free virtual = 18092
-Phase 7 Post Hold Fix | Checksum: 31892488d
-
-Time (s): cpu = 00:03:59 ; elapsed = 00:01:12 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6386 ; free virtual = 18092
-
-Phase 8 Route finalize
-
-Router Utilization Summary
- Global Vertical Routing Utilization = 8.6766 %
- Global Horizontal Routing Utilization = 9.27418 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 0
- (Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 0
- Number of Partially Routed Nets = 0
- Number of Node Overlaps = 0
-
-Phase 8 Route finalize | Checksum: 31892488d
-
-Time (s): cpu = 00:04:00 ; elapsed = 00:01:12 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6386 ; free virtual = 18092
-
-Phase 9 Verifying routed nets
-
- Verification completed successfully
-Phase 9 Verifying routed nets | Checksum: 31892488d
-
-Time (s): cpu = 00:04:00 ; elapsed = 00:01:12 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6386 ; free virtual = 18091
-
-Phase 10 Depositing Routes
-Phase 10 Depositing Routes | Checksum: 27b1f6231
-
-Time (s): cpu = 00:04:09 ; elapsed = 00:01:17 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6385 ; free virtual = 18090
-
-Phase 11 Post Process Routing
-Phase 11 Post Process Routing | Checksum: 27b1f6231
-
-Time (s): cpu = 00:04:09 ; elapsed = 00:01:17 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6385 ; free virtual = 18090
-
-Phase 12 Post Router Timing
-INFO: [Route 35-57] Estimated Timing Summary | WNS=0.205 | TNS=0.000 | WHS=0.057 | THS=0.000 |
-
-INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
-Phase 12 Post Router Timing | Checksum: 27b1f6231
-
-Time (s): cpu = 00:04:09 ; elapsed = 00:01:17 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6385 ; free virtual = 18090
-Total Elapsed time in route_design: 77.49 secs
-
-Phase 13 Post-Route Event Processing
-Phase 13 Post-Route Event Processing | Checksum: 101093cae
-
-Time (s): cpu = 00:04:10 ; elapsed = 00:01:18 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6385 ; free virtual = 18090
-INFO: [Route 35-16] Router Completed Successfully
-Ending Routing Task | Checksum: 101093cae
-
-Time (s): cpu = 00:04:10 ; elapsed = 00:01:18 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6385 ; free virtual = 18090
-
-Routing Is Done.
-INFO: [Common 17-83] Releasing license: Implementation
-10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-route_design completed successfully
-route_design: Time (s): cpu = 00:04:11 ; elapsed = 00:01:18 . Memory (MB): peak = 4369.676 ; gain = 46.988 ; free physical = 6385 ; free virtual = 18090
-# write_checkpoint -force [file join $checkpoint_dir post_route.dcp]
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4369.676 ; gain = 0.000 ; free physical = 6385 ; free virtual = 18090
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4369.676 ; gain = 0.000 ; free physical = 6385 ; free virtual = 18090
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4369.676 ; gain = 0.000 ; free physical = 6377 ; free virtual = 18090
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:07 ; elapsed = 00:00:01 . Memory (MB): peak = 4369.676 ; gain = 0.000 ; free physical = 6322 ; free virtual = 18082
-Wrote PlaceStorage: Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 4369.676 ; gain = 0.000 ; free physical = 6264 ; free virtual = 18087
-Wrote Netlist Cache: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4369.676 ; gain = 0.000 ; free physical = 6256 ; free virtual = 18088
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4369.676 ; gain = 0.000 ; free physical = 6248 ; free virtual = 18081
-Write Physdb Complete: Time (s): cpu = 00:00:10 ; elapsed = 00:00:03 . Memory (MB): peak = 4369.676 ; gain = 0.000 ; free physical = 6248 ; free virtual = 18081
-INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_route.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:14 ; elapsed = 00:00:08 . Memory (MB): peak = 4369.676 ; gain = 0.000 ; free physical = 6235 ; free virtual = 18010
-# report_utilization -file [file join $report_dir route_utilization.rpt]
-# report_timing_summary -file [file join $report_dir route_timing_summary.rpt]
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs
-report_timing_summary: Time (s): cpu = 00:00:39 ; elapsed = 00:00:07 . Memory (MB): peak = 4369.676 ; gain = 0.000 ; free physical = 6267 ; free virtual = 18042
-# report_drc -file [file join $report_dir route_drc.rpt]
-Command: report_drc -file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/route_drc.rpt
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.2/data/ip'.
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/route_drc.rpt.
-report_drc completed successfully
-# report_power -file [file join $report_dir route_power.rpt]
-Command: report_power -file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/route_power.rpt
-INFO: [Power 33-23] Power model is not available for u_cfg_flash_startup
-Running Vector-less Activity Propagation...
-
-Finished Running Vector-less Activity Propagation
-WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
-Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
-1 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
-report_power completed successfully
-report_power: Time (s): cpu = 00:00:20 ; elapsed = 00:00:09 . Memory (MB): peak = 4441.711 ; gain = 72.035 ; free physical = 6283 ; free virtual = 18060
-# set bit_file [file join $bit_dir genesys2_rocket.bit]
-# puts "Writing bitstream: $bit_file"
-Writing bitstream: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-# write_bitstream -force $bit_file
-Command: write_bitstream -force /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
-Running DRC as a precondition to command write_bitstream
-INFO: [IP_Flow 19-1839] IP Catalog is up to date.
-INFO: [DRC 23-27] Running DRC with 12 threads
-INFO: [Vivado 12-3199] DRC finished with 0 Errors
-INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
-Integrating Hard IP ELF/MEM with the PDI.
-INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
-Loading data files...
-Loading site data...
-Loading route data...
-Processing options...
-Creating bitmap...
-Creating bitstream...
-Writing bitstream /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit...
-INFO: [Vivado 12-1842] Bitgen Completed Successfully.
-INFO: [Common 17-83] Releasing license: Implementation
-8 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:01:43 ; elapsed = 00:00:22 . Memory (MB): peak = 4796.402 ; gain = 354.691 ; free physical = 5859 ; free virtual = 17650
-# puts "Genesys2 non-project flow complete."
-Genesys2 non-project flow complete.
-INFO: [Common 17-206] Exiting Vivado at Fri Jul 10 16:50:39 2026...
diff --git a/targets/fpga/genesys2/out/logs/hs_err_pid171985.log b/targets/fpga/genesys2/out/logs/hs_err_pid171985.log
deleted file mode 100644
index 7e043e0..0000000
--- a/targets/fpga/genesys2/out/logs/hs_err_pid171985.log
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# An unexpected error has occurred (11) Segmentation fault
-#
-Stack:
-/lib/x86_64-linux-gnu/libc.so.6(+0x42520) [0x7b8032a42520]
-[0x26189400]
diff --git a/targets/fpga/genesys2/out/logs/hs_err_pid30058.log b/targets/fpga/genesys2/out/logs/hs_err_pid30058.log
deleted file mode 100644
index 6ffbf11..0000000
--- a/targets/fpga/genesys2/out/logs/hs_err_pid30058.log
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# An unexpected error has occurred (11) Segmentation fault
-#
-Stack:
-/lib/x86_64-linux-gnu/libc.so.6(+0x42520) [0x723add242520]
-/tools/Xilinx/2025.2/Vivado/lib/lnx64.o/libboost_regex.so.1.72.0(boost::detail::sp_counted_impl_p > > >::dispose()+0x47) [0x723ae61b86a7]
-/tools/Xilinx/2025.2/Vivado/lib/lnx64.o/libboost_regex.so.1.72.0(boost::detail::sp_counted_impl_p > > >::dispose()+0x72) [0x723ae61b8752]
-/tools/Xilinx/2025.2/Vivado/lib/lnx64.o/libxv_xicom_hw.so(XHWPropertyManager::findParent(std::__cxx11::basic_string, std::allocator >)+0x3e9) [0x723aae411699]
-/tools/Xilinx/2025.2/Vivado/lib/lnx64.o/libxv_xicom_hw.so(XHWPropertyManager::addList(XHWName, XHWName)+0x141) [0x723aae411921]
-/tools/Xilinx/2025.2/Vivado/lib/lnx64.o/libxv_xicom_hw.so(XicomHWXicomNodeEvents::addNodeEvent(Channel*, void*)+0x458) [0x723aae616b08]
-/tools/Xilinx/2025.2/Vivado/lib/lnx64.o/libxv_xicom_hw.so(handle_protocol_message(Channel*)+0x1083) [0x723aae697463]
-/tools/Xilinx/2025.2/Vivado/lib/lnx64.o/libxv_xicom_hw.so(+0x49e6f5) [0x723aae69e6f5]
-/tools/Xilinx/2025.2/Vivado/lib/lnx64.o/libxv_xicom_hw.so(run_event_loop()+0xcc) [0x723aae69a65c]
-/tools/Xilinx/2025.2/Vivado/lib/lnx64.o/libxv_xicom_hw.so(+0x49c403) [0x723aae69c403]
-/lib/x86_64-linux-gnu/libc.so.6(+0x94ac3) [0x723add294ac3]
-/lib/x86_64-linux-gnu/libc.so.6(+0x1268d0) [0x723add3268d0]
diff --git a/targets/fpga/genesys2/out/logs/program_flash.jou b/targets/fpga/genesys2/out/logs/program_flash.jou
deleted file mode 100644
index 95e9917..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 00:16:17 2026
-# Process ID : 90546
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20462 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_flash.log b/targets/fpga/genesys2/out/logs/program_flash.log
deleted file mode 100644
index dd7ba95..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash.log
+++ /dev/null
@@ -1,114 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 00:16:17 2026
-# Process ID : 90546
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20462 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set cfgmem_part [getenv_default CFGMEM_PART s25fl256sxxxxxx0-spi-x1_x2_x4]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# set flash_verify [getenv_default FLASH_VERIFY 0]
-# set flash_erase [getenv_default FLASH_ERASE 1]
-# set flash_region_names [split [getenv_default FLASH_REGION_NAMES "combined"] ";"]
-# set flash_region_files_env [getenv_default FLASH_REGION_FILES ""]
-# if {$flash_region_files_env eq ""} {
-# set flash_region_files [list $mcs_file]
-# } else {
-# set flash_region_files [split $flash_region_files_env ";"]
-# }
-# if {[llength $flash_region_names] != [llength $flash_region_files]} {
-# error "FLASH_REGION_NAMES and FLASH_REGION_FILES length mismatch"
-# }
-# foreach region_file $flash_region_files {
-# if {![file exists $region_file]} {
-# error "MCS file not found: $region_file"
-# }
-# }
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
-# set cfg_parts [get_cfgmem_parts $cfgmem_part]
-# if {[llength $cfg_parts] == 0} {
-# error "Configuration memory part not found: $cfgmem_part"
-# }
-# create_hw_cfgmem -hw_device $dev [lindex $cfg_parts 0]
-# set cfgmem [current_hw_cfgmem]
-# set_property PROGRAM.ADDRESS_RANGE {use_file} $cfgmem
-# set_property PROGRAM.BLANK_CHECK 0 $cfgmem
-# set_property PROGRAM.ERASE $flash_erase $cfgmem
-# set_property PROGRAM.CFG_PROGRAM 1 $cfgmem
-# set_property PROGRAM.VERIFY $flash_verify $cfgmem
-# set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $cfgmem
-# create_hw_bitstream -hw_device $dev [get_property PROGRAM.HW_CFGMEM_BITFILE $dev]
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-# refresh_hw_device $dev
-INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
-# for {set i 0} {$i < [llength $flash_region_files]} {incr i} {
-# set region_name [lindex $flash_region_names $i]
-# set region_file [lindex $flash_region_files $i]
-# puts "Programming flash region '$region_name' from $region_file"
-# set_property PROGRAM.FILES [list $region_file] $cfgmem
-# program_hw_cfgmem $cfgmem
-# }
-Programming flash region 'app' from /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-Mfg ID : 1 Memory Type : 2 Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
-Performing Erase Operation...
-Erase Operation successful.
-Performing Program Operation...
-Program Operation successful.
-INFO: [Labtoolstcl 44-377] Flash programming completed successfully
-# puts "Programmed flash $cfgmem_part"
-Programmed flash s25fl256sxxxxxx0-spi-x1_x2_x4
-# close_hw_manager
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 00:16:29 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_flash_5207.backup.jou b/targets/fpga/genesys2/out/logs/program_flash_5207.backup.jou
deleted file mode 100644
index a695e1a..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_5207.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Wed Jul 8 01:07:57 2026
-# Process ID : 5207
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22413 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_flash_5207.backup.log b/targets/fpga/genesys2/out/logs/program_flash_5207.backup.log
deleted file mode 100644
index 12fd3dd..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_5207.backup.log
+++ /dev/null
@@ -1,123 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Wed Jul 8 01:07:57 2026
-# Process ID : 5207
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22413 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set cfgmem_part [getenv_default CFGMEM_PART s25fl256sxxxxxx0-spi-x1_x2_x4]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# set flash_verify [getenv_default FLASH_VERIFY 0]
-# set flash_erase [getenv_default FLASH_ERASE 1]
-# set flash_region_names [split [getenv_default FLASH_REGION_NAMES "combined"] ";"]
-# set flash_region_files_env [getenv_default FLASH_REGION_FILES ""]
-# if {$flash_region_files_env eq ""} {
-# set flash_region_files [list $mcs_file]
-# } else {
-# set flash_region_files [split $flash_region_files_env ";"]
-# }
-# if {[llength $flash_region_names] != [llength $flash_region_files]} {
-# error "FLASH_REGION_NAMES and FLASH_REGION_FILES length mismatch"
-# }
-# foreach region_file $flash_region_files {
-# if {![file exists $region_file]} {
-# error "MCS file not found: $region_file"
-# }
-# }
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# set cfg_parts [get_cfgmem_parts $cfgmem_part]
-# if {[llength $cfg_parts] == 0} {
-# error "Configuration memory part not found: $cfgmem_part"
-# }
-# create_hw_cfgmem -hw_device $dev [lindex $cfg_parts 0]
-# set cfgmem [current_hw_cfgmem]
-# set_property PROGRAM.ADDRESS_RANGE {use_file} $cfgmem
-# set_property PROGRAM.BLANK_CHECK 0 $cfgmem
-# set_property PROGRAM.ERASE $flash_erase $cfgmem
-# set_property PROGRAM.CFG_PROGRAM 1 $cfgmem
-# set_property PROGRAM.VERIFY $flash_verify $cfgmem
-# set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $cfgmem
-# create_hw_bitstream -hw_device $dev [get_property PROGRAM.HW_CFGMEM_BITFILE $dev]
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-# refresh_hw_device $dev
-INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
-# for {set i 0} {$i < [llength $flash_region_files]} {incr i} {
-# set region_name [lindex $flash_region_names $i]
-# set region_file [lindex $flash_region_files $i]
-# puts "Programming flash region '$region_name' from $region_file"
-# set_property PROGRAM.FILES [list $region_file] $cfgmem
-# program_hw_cfgmem $cfgmem
-# }
-Programming flash region 'bitstream' from /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/bitstream.mcs
-Mfg ID : 1 Memory Type : 2 Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
-Performing Erase Operation...
-Erase Operation successful.
-Performing Program Operation...
-Program Operation successful.
-INFO: [Labtoolstcl 44-377] Flash programming completed successfully
-program_hw_cfgmem: Time (s): cpu = 00:00:00.89 ; elapsed = 00:07:39 . Memory (MB): peak = 1700.477 ; gain = 32.000 ; free physical = 11623 ; free virtual = 20754
-# puts "Programmed flash $cfgmem_part"
-Programmed flash s25fl256sxxxxxx0-spi-x1_x2_x4
-# close_hw_manager
-INFO: [Common 17-206] Exiting Vivado at Wed Jul 8 01:15:48 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_flash_62330.backup.jou b/targets/fpga/genesys2/out/logs/program_flash_62330.backup.jou
deleted file mode 100644
index fbc55dd..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_62330.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Thu Jul 9 20:19:50 2026
-# Process ID : 62330
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21964 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_flash_62330.backup.log b/targets/fpga/genesys2/out/logs/program_flash_62330.backup.log
deleted file mode 100644
index c6457c5..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_62330.backup.log
+++ /dev/null
@@ -1,122 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Thu Jul 9 20:19:50 2026
-# Process ID : 62330
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21964 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set cfgmem_part [getenv_default CFGMEM_PART s25fl256sxxxxxx0-spi-x1_x2_x4]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# set flash_verify [getenv_default FLASH_VERIFY 0]
-# set flash_erase [getenv_default FLASH_ERASE 1]
-# set flash_region_names [split [getenv_default FLASH_REGION_NAMES "combined"] ";"]
-# set flash_region_files_env [getenv_default FLASH_REGION_FILES ""]
-# if {$flash_region_files_env eq ""} {
-# set flash_region_files [list $mcs_file]
-# } else {
-# set flash_region_files [split $flash_region_files_env ";"]
-# }
-# if {[llength $flash_region_names] != [llength $flash_region_files]} {
-# error "FLASH_REGION_NAMES and FLASH_REGION_FILES length mismatch"
-# }
-# foreach region_file $flash_region_files {
-# if {![file exists $region_file]} {
-# error "MCS file not found: $region_file"
-# }
-# }
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# set cfg_parts [get_cfgmem_parts $cfgmem_part]
-# if {[llength $cfg_parts] == 0} {
-# error "Configuration memory part not found: $cfgmem_part"
-# }
-# create_hw_cfgmem -hw_device $dev [lindex $cfg_parts 0]
-# set cfgmem [current_hw_cfgmem]
-# set_property PROGRAM.ADDRESS_RANGE {use_file} $cfgmem
-# set_property PROGRAM.BLANK_CHECK 0 $cfgmem
-# set_property PROGRAM.ERASE $flash_erase $cfgmem
-# set_property PROGRAM.CFG_PROGRAM 1 $cfgmem
-# set_property PROGRAM.VERIFY $flash_verify $cfgmem
-# set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $cfgmem
-# create_hw_bitstream -hw_device $dev [get_property PROGRAM.HW_CFGMEM_BITFILE $dev]
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-# refresh_hw_device $dev
-INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
-# for {set i 0} {$i < [llength $flash_region_files]} {incr i} {
-# set region_name [lindex $flash_region_names $i]
-# set region_file [lindex $flash_region_files $i]
-# puts "Programming flash region '$region_name' from $region_file"
-# set_property PROGRAM.FILES [list $region_file] $cfgmem
-# program_hw_cfgmem $cfgmem
-# }
-Programming flash region 'app' from /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-Mfg ID : 1 Memory Type : 2 Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
-Performing Erase Operation...
-Erase Operation successful.
-Performing Program Operation...
-Program Operation successful.
-INFO: [Labtoolstcl 44-377] Flash programming completed successfully
-# puts "Programmed flash $cfgmem_part"
-Programmed flash s25fl256sxxxxxx0-spi-x1_x2_x4
-# close_hw_manager
-INFO: [Common 17-206] Exiting Vivado at Thu Jul 9 20:20:02 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_flash_62408.backup.jou b/targets/fpga/genesys2/out/logs/program_flash_62408.backup.jou
deleted file mode 100644
index 98f31e9..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_62408.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Tue Jul 7 18:24:36 2026
-# Process ID : 62408
-# Current directory : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log -journal /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou -source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log
-# Journal file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22180 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_flash_62408.backup.log b/targets/fpga/genesys2/out/logs/program_flash_62408.backup.log
deleted file mode 100644
index 426f56b..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_62408.backup.log
+++ /dev/null
@@ -1,130 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Tue Jul 7 18:24:36 2026
-# Process ID : 62408
-# Current directory : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log -journal /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou -source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.log
-# Journal file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22180 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set cfgmem_part [getenv_default CFGMEM_PART s25fl256sxxxxxx0-spi-x1_x2_x4]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# set flash_verify [getenv_default FLASH_VERIFY 0]
-# set flash_erase [getenv_default FLASH_ERASE 1]
-# set flash_region_names [split [getenv_default FLASH_REGION_NAMES "combined"] ";"]
-# set flash_region_files_env [getenv_default FLASH_REGION_FILES ""]
-# if {$flash_region_files_env eq ""} {
-# set flash_region_files [list $mcs_file]
-# } else {
-# set flash_region_files [split $flash_region_files_env ";"]
-# }
-# if {[llength $flash_region_names] != [llength $flash_region_files]} {
-# error "FLASH_REGION_NAMES and FLASH_REGION_FILES length mismatch"
-# }
-# foreach region_file $flash_region_files {
-# if {![file exists $region_file]} {
-# error "MCS file not found: $region_file"
-# }
-# }
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# set cfg_parts [get_cfgmem_parts $cfgmem_part]
-# if {[llength $cfg_parts] == 0} {
-# error "Configuration memory part not found: $cfgmem_part"
-# }
-# create_hw_cfgmem -hw_device $dev [lindex $cfg_parts 0]
-# set cfgmem [current_hw_cfgmem]
-# set_property PROGRAM.ADDRESS_RANGE {use_file} $cfgmem
-# set_property PROGRAM.BLANK_CHECK 0 $cfgmem
-# set_property PROGRAM.ERASE $flash_erase $cfgmem
-# set_property PROGRAM.CFG_PROGRAM 1 $cfgmem
-# set_property PROGRAM.VERIFY $flash_verify $cfgmem
-# set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $cfgmem
-# create_hw_bitstream -hw_device $dev [get_property PROGRAM.HW_CFGMEM_BITFILE $dev]
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-# refresh_hw_device $dev
-INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
-# for {set i 0} {$i < [llength $flash_region_files]} {incr i} {
-# set region_name [lindex $flash_region_names $i]
-# set region_file [lindex $flash_region_files $i]
-# puts "Programming flash region '$region_name' from $region_file"
-# set_property PROGRAM.FILES [list $region_file] $cfgmem
-# program_hw_cfgmem $cfgmem
-# }
-Programming flash region 'bitstream' from /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/regions/bitstream.mcs
-Mfg ID : 1 Memory Type : 2 Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
-Performing Erase Operation...
-Erase Operation successful.
-Performing Program Operation...
-Program Operation successful.
-INFO: [Labtoolstcl 44-377] Flash programming completed successfully
-program_hw_cfgmem: Time (s): cpu = 00:00:00.87 ; elapsed = 00:08:10 . Memory (MB): peak = 1700.188 ; gain = 32.000 ; free physical = 9904 ; free virtual = 20646
-Programming flash region 'app' from /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-Mfg ID : 1 Memory Type : 2 Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
-Performing Erase Operation...
-Erase Operation successful.
-Performing Program Operation...
-Program Operation successful.
-INFO: [Labtoolstcl 44-377] Flash programming completed successfully
-# puts "Programmed flash $cfgmem_part"
-Programmed flash s25fl256sxxxxxx0-spi-x1_x2_x4
-# close_hw_manager
-INFO: [Common 17-206] Exiting Vivado at Tue Jul 7 18:33:01 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_flash_combined.jou b/targets/fpga/genesys2/out/logs/program_flash_combined.jou
deleted file mode 100644
index 80ac848..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_combined.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Thu Jul 9 21:25:39 2026
-# Process ID : 69900
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21719 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_flash_combined.log b/targets/fpga/genesys2/out/logs/program_flash_combined.log
deleted file mode 100644
index 8e45c9d..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_combined.log
+++ /dev/null
@@ -1,123 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Thu Jul 9 21:25:39 2026
-# Process ID : 69900
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21719 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set cfgmem_part [getenv_default CFGMEM_PART s25fl256sxxxxxx0-spi-x1_x2_x4]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# set flash_verify [getenv_default FLASH_VERIFY 0]
-# set flash_erase [getenv_default FLASH_ERASE 1]
-# set flash_region_names [split [getenv_default FLASH_REGION_NAMES "combined"] ";"]
-# set flash_region_files_env [getenv_default FLASH_REGION_FILES ""]
-# if {$flash_region_files_env eq ""} {
-# set flash_region_files [list $mcs_file]
-# } else {
-# set flash_region_files [split $flash_region_files_env ";"]
-# }
-# if {[llength $flash_region_names] != [llength $flash_region_files]} {
-# error "FLASH_REGION_NAMES and FLASH_REGION_FILES length mismatch"
-# }
-# foreach region_file $flash_region_files {
-# if {![file exists $region_file]} {
-# error "MCS file not found: $region_file"
-# }
-# }
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# set cfg_parts [get_cfgmem_parts $cfgmem_part]
-# if {[llength $cfg_parts] == 0} {
-# error "Configuration memory part not found: $cfgmem_part"
-# }
-# create_hw_cfgmem -hw_device $dev [lindex $cfg_parts 0]
-# set cfgmem [current_hw_cfgmem]
-# set_property PROGRAM.ADDRESS_RANGE {use_file} $cfgmem
-# set_property PROGRAM.BLANK_CHECK 0 $cfgmem
-# set_property PROGRAM.ERASE $flash_erase $cfgmem
-# set_property PROGRAM.CFG_PROGRAM 1 $cfgmem
-# set_property PROGRAM.VERIFY $flash_verify $cfgmem
-# set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $cfgmem
-# create_hw_bitstream -hw_device $dev [get_property PROGRAM.HW_CFGMEM_BITFILE $dev]
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-# refresh_hw_device $dev
-INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
-# for {set i 0} {$i < [llength $flash_region_files]} {incr i} {
-# set region_name [lindex $flash_region_names $i]
-# set region_file [lindex $flash_region_files $i]
-# puts "Programming flash region '$region_name' from $region_file"
-# set_property PROGRAM.FILES [list $region_file] $cfgmem
-# program_hw_cfgmem $cfgmem
-# }
-Programming flash region 'combined' from /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Mfg ID : 1 Memory Type : 2 Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
-Performing Erase Operation...
-Erase Operation successful.
-Performing Program Operation...
-Program Operation successful.
-INFO: [Labtoolstcl 44-377] Flash programming completed successfully
-program_hw_cfgmem: Time (s): cpu = 00:00:00.66 ; elapsed = 00:04:03 . Memory (MB): peak = 1732.098 ; gain = 63.000 ; free physical = 8719 ; free virtual = 20152
-# puts "Programmed flash $cfgmem_part"
-Programmed flash s25fl256sxxxxxx0-spi-x1_x2_x4
-# close_hw_manager
-INFO: [Common 17-206] Exiting Vivado at Thu Jul 9 21:29:51 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_flash_combined_116729.backup.jou b/targets/fpga/genesys2/out/logs/program_flash_combined_116729.backup.jou
deleted file mode 100644
index 1e50488..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_combined_116729.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Tue Jul 7 18:52:12 2026
-# Process ID : 116729
-# Current directory : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log -journal /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou -source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log
-# Journal file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22059 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_flash_combined_116729.backup.log b/targets/fpga/genesys2/out/logs/program_flash_combined_116729.backup.log
deleted file mode 100644
index 872ba8a..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_combined_116729.backup.log
+++ /dev/null
@@ -1,121 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Tue Jul 7 18:52:12 2026
-# Process ID : 116729
-# Current directory : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log -journal /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou -source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log
-# Journal file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22059 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set cfgmem_part [getenv_default CFGMEM_PART s25fl256sxxxxxx0-spi-x1_x2_x4]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# set flash_verify [getenv_default FLASH_VERIFY 0]
-# set flash_erase [getenv_default FLASH_ERASE 1]
-# set flash_region_names [split [getenv_default FLASH_REGION_NAMES "combined"] ";"]
-# set flash_region_files_env [getenv_default FLASH_REGION_FILES ""]
-# if {$flash_region_files_env eq ""} {
-# set flash_region_files [list $mcs_file]
-# } else {
-# set flash_region_files [split $flash_region_files_env ";"]
-# }
-# if {[llength $flash_region_names] != [llength $flash_region_files]} {
-# error "FLASH_REGION_NAMES and FLASH_REGION_FILES length mismatch"
-# }
-# foreach region_file $flash_region_files {
-# if {![file exists $region_file]} {
-# error "MCS file not found: $region_file"
-# }
-# }
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# set cfg_parts [get_cfgmem_parts $cfgmem_part]
-# if {[llength $cfg_parts] == 0} {
-# error "Configuration memory part not found: $cfgmem_part"
-# }
-# create_hw_cfgmem -hw_device $dev [lindex $cfg_parts 0]
-# set cfgmem [current_hw_cfgmem]
-# set_property PROGRAM.ADDRESS_RANGE {use_file} $cfgmem
-# set_property PROGRAM.BLANK_CHECK 0 $cfgmem
-# set_property PROGRAM.ERASE $flash_erase $cfgmem
-# set_property PROGRAM.CFG_PROGRAM 1 $cfgmem
-# set_property PROGRAM.VERIFY $flash_verify $cfgmem
-# set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $cfgmem
-# create_hw_bitstream -hw_device $dev [get_property PROGRAM.HW_CFGMEM_BITFILE $dev]
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-# refresh_hw_device $dev
-INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
-# for {set i 0} {$i < [llength $flash_region_files]} {incr i} {
-# set region_name [lindex $flash_region_names $i]
-# set region_file [lindex $flash_region_files $i]
-# puts "Programming flash region '$region_name' from $region_file"
-# set_property PROGRAM.FILES [list $region_file] $cfgmem
-# program_hw_cfgmem $cfgmem
-# }
-Programming flash region 'combined' from /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Mfg ID : 1 Memory Type : 2 Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
-Performing Erase Operation...
-Erase Operation successful.
-Performing Program Operation...
-INFO: [Common 17-41] Interrupt caught. Command should exit soon.
-INFO: [Common 17-41] Interrupt caught. Command should exit soon.
-INFO: [Common 17-41] Interrupt caught. Command should exit soon.
-INFO: [Common 17-41] Interrupt caught. Command should exit soon.
-INFO: [Common 17-41] Interrupt caught. Command should exit soon.
diff --git a/targets/fpga/genesys2/out/logs/program_flash_combined_117250.backup.jou b/targets/fpga/genesys2/out/logs/program_flash_combined_117250.backup.jou
deleted file mode 100644
index 05d00a5..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_combined_117250.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Tue Jul 7 18:55:41 2026
-# Process ID : 117250
-# Current directory : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log -journal /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou -source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log
-# Journal file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21972 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_flash_combined_117250.backup.log b/targets/fpga/genesys2/out/logs/program_flash_combined_117250.backup.log
deleted file mode 100644
index e89ea9a..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_combined_117250.backup.log
+++ /dev/null
@@ -1,123 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Tue Jul 7 18:55:41 2026
-# Process ID : 117250
-# Current directory : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log -journal /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou -source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log
-# Journal file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21972 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set cfgmem_part [getenv_default CFGMEM_PART s25fl256sxxxxxx0-spi-x1_x2_x4]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# set flash_verify [getenv_default FLASH_VERIFY 0]
-# set flash_erase [getenv_default FLASH_ERASE 1]
-# set flash_region_names [split [getenv_default FLASH_REGION_NAMES "combined"] ";"]
-# set flash_region_files_env [getenv_default FLASH_REGION_FILES ""]
-# if {$flash_region_files_env eq ""} {
-# set flash_region_files [list $mcs_file]
-# } else {
-# set flash_region_files [split $flash_region_files_env ";"]
-# }
-# if {[llength $flash_region_names] != [llength $flash_region_files]} {
-# error "FLASH_REGION_NAMES and FLASH_REGION_FILES length mismatch"
-# }
-# foreach region_file $flash_region_files {
-# if {![file exists $region_file]} {
-# error "MCS file not found: $region_file"
-# }
-# }
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
-# set cfg_parts [get_cfgmem_parts $cfgmem_part]
-# if {[llength $cfg_parts] == 0} {
-# error "Configuration memory part not found: $cfgmem_part"
-# }
-# create_hw_cfgmem -hw_device $dev [lindex $cfg_parts 0]
-# set cfgmem [current_hw_cfgmem]
-# set_property PROGRAM.ADDRESS_RANGE {use_file} $cfgmem
-# set_property PROGRAM.BLANK_CHECK 0 $cfgmem
-# set_property PROGRAM.ERASE $flash_erase $cfgmem
-# set_property PROGRAM.CFG_PROGRAM 1 $cfgmem
-# set_property PROGRAM.VERIFY $flash_verify $cfgmem
-# set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $cfgmem
-# create_hw_bitstream -hw_device $dev [get_property PROGRAM.HW_CFGMEM_BITFILE $dev]
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-# refresh_hw_device $dev
-INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
-# for {set i 0} {$i < [llength $flash_region_files]} {incr i} {
-# set region_name [lindex $flash_region_names $i]
-# set region_file [lindex $flash_region_files $i]
-# puts "Programming flash region '$region_name' from $region_file"
-# set_property PROGRAM.FILES [list $region_file] $cfgmem
-# program_hw_cfgmem $cfgmem
-# }
-Programming flash region 'combined' from /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Mfg ID : 1 Memory Type : 2 Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
-Performing Erase Operation...
-Erase Operation successful.
-Performing Program Operation...
-Program Operation successful.
-INFO: [Labtoolstcl 44-377] Flash programming completed successfully
-program_hw_cfgmem: Time (s): cpu = 00:00:00.91 ; elapsed = 00:07:01 . Memory (MB): peak = 1732.645 ; gain = 64.000 ; free physical = 9669 ; free virtual = 20480
-# puts "Programmed flash $cfgmem_part"
-Programmed flash s25fl256sxxxxxx0-spi-x1_x2_x4
-# close_hw_manager
-INFO: [Common 17-206] Exiting Vivado at Tue Jul 7 19:02:54 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_flash_combined_57310.backup.jou b/targets/fpga/genesys2/out/logs/program_flash_combined_57310.backup.jou
deleted file mode 100644
index 2694f1b..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_combined_57310.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Tue Jul 7 17:51:06 2026
-# Process ID : 57310
-# Current directory : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log -journal /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou -source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log
-# Journal file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22287 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_flash_combined_57310.backup.log b/targets/fpga/genesys2/out/logs/program_flash_combined_57310.backup.log
deleted file mode 100644
index 10f13a7..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_combined_57310.backup.log
+++ /dev/null
@@ -1,123 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Tue Jul 7 17:51:06 2026
-# Process ID : 57310
-# Current directory : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log -journal /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou -source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log
-# Journal file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22287 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set cfgmem_part [getenv_default CFGMEM_PART s25fl256sxxxxxx0-spi-x1_x2_x4]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# set flash_verify [getenv_default FLASH_VERIFY 0]
-# set flash_erase [getenv_default FLASH_ERASE 1]
-# set flash_region_names [split [getenv_default FLASH_REGION_NAMES "combined"] ";"]
-# set flash_region_files_env [getenv_default FLASH_REGION_FILES ""]
-# if {$flash_region_files_env eq ""} {
-# set flash_region_files [list $mcs_file]
-# } else {
-# set flash_region_files [split $flash_region_files_env ";"]
-# }
-# if {[llength $flash_region_names] != [llength $flash_region_files]} {
-# error "FLASH_REGION_NAMES and FLASH_REGION_FILES length mismatch"
-# }
-# foreach region_file $flash_region_files {
-# if {![file exists $region_file]} {
-# error "MCS file not found: $region_file"
-# }
-# }
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# set cfg_parts [get_cfgmem_parts $cfgmem_part]
-# if {[llength $cfg_parts] == 0} {
-# error "Configuration memory part not found: $cfgmem_part"
-# }
-# create_hw_cfgmem -hw_device $dev [lindex $cfg_parts 0]
-# set cfgmem [current_hw_cfgmem]
-# set_property PROGRAM.ADDRESS_RANGE {use_file} $cfgmem
-# set_property PROGRAM.BLANK_CHECK 0 $cfgmem
-# set_property PROGRAM.ERASE $flash_erase $cfgmem
-# set_property PROGRAM.CFG_PROGRAM 1 $cfgmem
-# set_property PROGRAM.VERIFY $flash_verify $cfgmem
-# set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $cfgmem
-# create_hw_bitstream -hw_device $dev [get_property PROGRAM.HW_CFGMEM_BITFILE $dev]
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-# refresh_hw_device $dev
-INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
-# for {set i 0} {$i < [llength $flash_region_files]} {incr i} {
-# set region_name [lindex $flash_region_names $i]
-# set region_file [lindex $flash_region_files $i]
-# puts "Programming flash region '$region_name' from $region_file"
-# set_property PROGRAM.FILES [list $region_file] $cfgmem
-# program_hw_cfgmem $cfgmem
-# }
-Programming flash region 'combined' from /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Mfg ID : 1 Memory Type : 2 Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
-Performing Erase Operation...
-Erase Operation successful.
-Performing Program Operation...
-Program Operation successful.
-INFO: [Labtoolstcl 44-377] Flash programming completed successfully
-program_hw_cfgmem: Time (s): cpu = 00:00:00.88 ; elapsed = 00:08:13 . Memory (MB): peak = 1732.160 ; gain = 63.000 ; free physical = 10313 ; free virtual = 20694
-# puts "Programmed flash $cfgmem_part"
-Programmed flash s25fl256sxxxxxx0-spi-x1_x2_x4
-# close_hw_manager
-INFO: [Common 17-206] Exiting Vivado at Tue Jul 7 17:59:32 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_flash_combined_65566.backup.jou b/targets/fpga/genesys2/out/logs/program_flash_combined_65566.backup.jou
deleted file mode 100644
index e56643d..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_combined_65566.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Thu Jul 9 20:42:41 2026
-# Process ID : 65566
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21795 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_flash_combined_65566.backup.log b/targets/fpga/genesys2/out/logs/program_flash_combined_65566.backup.log
deleted file mode 100644
index 9ba65f0..0000000
--- a/targets/fpga/genesys2/out/logs/program_flash_combined_65566.backup.log
+++ /dev/null
@@ -1,123 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Thu Jul 9 20:42:41 2026
-# Process ID : 65566
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_flash_combined.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21795 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set cfgmem_part [getenv_default CFGMEM_PART s25fl256sxxxxxx0-spi-x1_x2_x4]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# set flash_verify [getenv_default FLASH_VERIFY 0]
-# set flash_erase [getenv_default FLASH_ERASE 1]
-# set flash_region_names [split [getenv_default FLASH_REGION_NAMES "combined"] ";"]
-# set flash_region_files_env [getenv_default FLASH_REGION_FILES ""]
-# if {$flash_region_files_env eq ""} {
-# set flash_region_files [list $mcs_file]
-# } else {
-# set flash_region_files [split $flash_region_files_env ";"]
-# }
-# if {[llength $flash_region_names] != [llength $flash_region_files]} {
-# error "FLASH_REGION_NAMES and FLASH_REGION_FILES length mismatch"
-# }
-# foreach region_file $flash_region_files {
-# if {![file exists $region_file]} {
-# error "MCS file not found: $region_file"
-# }
-# }
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# set cfg_parts [get_cfgmem_parts $cfgmem_part]
-# if {[llength $cfg_parts] == 0} {
-# error "Configuration memory part not found: $cfgmem_part"
-# }
-# create_hw_cfgmem -hw_device $dev [lindex $cfg_parts 0]
-# set cfgmem [current_hw_cfgmem]
-# set_property PROGRAM.ADDRESS_RANGE {use_file} $cfgmem
-# set_property PROGRAM.BLANK_CHECK 0 $cfgmem
-# set_property PROGRAM.ERASE $flash_erase $cfgmem
-# set_property PROGRAM.CFG_PROGRAM 1 $cfgmem
-# set_property PROGRAM.VERIFY $flash_verify $cfgmem
-# set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $cfgmem
-# create_hw_bitstream -hw_device $dev [get_property PROGRAM.HW_CFGMEM_BITFILE $dev]
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-# refresh_hw_device $dev
-INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
-# for {set i 0} {$i < [llength $flash_region_files]} {incr i} {
-# set region_name [lindex $flash_region_names $i]
-# set region_file [lindex $flash_region_files $i]
-# puts "Programming flash region '$region_name' from $region_file"
-# set_property PROGRAM.FILES [list $region_file] $cfgmem
-# program_hw_cfgmem $cfgmem
-# }
-Programming flash region 'combined' from /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Mfg ID : 1 Memory Type : 2 Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
-Performing Erase Operation...
-Erase Operation successful.
-Performing Program Operation...
-Program Operation successful.
-INFO: [Labtoolstcl 44-377] Flash programming completed successfully
-program_hw_cfgmem: Time (s): cpu = 00:00:00.64 ; elapsed = 00:04:04 . Memory (MB): peak = 1732.164 ; gain = 63.000 ; free physical = 9048 ; free virtual = 20268
-# puts "Programmed flash $cfgmem_part"
-Programmed flash s25fl256sxxxxxx0-spi-x1_x2_x4
-# close_hw_manager
-INFO: [Common 17-206] Exiting Vivado at Thu Jul 9 20:46:54 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_fpga.jou b/targets/fpga/genesys2/out/logs/program_fpga.jou
deleted file mode 100644
index 55bf129..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 20:07:29 2026
-# Process ID : 365586
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21531 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_fpga.log b/targets/fpga/genesys2/out/logs/program_fpga.log
deleted file mode 100644
index 899b9a3..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga.log
+++ /dev/null
@@ -1,78 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 20:07:29 2026
-# Process ID : 365586
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21531 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# set_property PROGRAM.FILE $bit_file $dev
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-program_hw_devices: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1669.160 ; gain = 1.000 ; free physical = 9122 ; free virtual = 20028
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# puts "Programmed FPGA with $bit_file"
-Programmed FPGA with /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 20:07:44 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_fpga_170923.backup.jou b/targets/fpga/genesys2/out/logs/program_fpga_170923.backup.jou
deleted file mode 100644
index 09864ae..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga_170923.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 18:03:01 2026
-# Process ID : 170923
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21685 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_fpga_170923.backup.log b/targets/fpga/genesys2/out/logs/program_fpga_170923.backup.log
deleted file mode 100644
index e6547b8..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga_170923.backup.log
+++ /dev/null
@@ -1,78 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 18:03:01 2026
-# Process ID : 170923
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21685 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# set_property PROGRAM.FILE $bit_file $dev
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-program_hw_devices: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1667.648 ; gain = 0.000 ; free physical = 8928 ; free virtual = 20094
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# puts "Programmed FPGA with $bit_file"
-Programmed FPGA with /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 18:03:16 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_fpga_171536.backup.jou b/targets/fpga/genesys2/out/logs/program_fpga_171536.backup.jou
deleted file mode 100644
index 704db88..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga_171536.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 18:11:00 2026
-# Process ID : 171536
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21698 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_fpga_171536.backup.log b/targets/fpga/genesys2/out/logs/program_fpga_171536.backup.log
deleted file mode 100644
index 435a8b6..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga_171536.backup.log
+++ /dev/null
@@ -1,78 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 18:11:00 2026
-# Process ID : 171536
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21698 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
-# set dev [lindex [get_hw_devices $device_pattern] 0]
-# if {$dev eq ""} {
-# error "No hardware device found matching $device_pattern"
-# }
-# current_hw_device $dev
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# set_property PROGRAM.FILE $bit_file $dev
-# program_hw_devices $dev
-INFO: [Labtools 27-3164] End of startup status: HIGH
-program_hw_devices: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1668.078 ; gain = 0.000 ; free physical = 8918 ; free virtual = 20122
-# refresh_hw_device $dev
-INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
-# puts "Programmed FPGA with $bit_file"
-Programmed FPGA with /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 18:11:16 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_fpga_171985.backup.jou b/targets/fpga/genesys2/out/logs/program_fpga_171985.backup.jou
deleted file mode 100644
index 827d156..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga_171985.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 18:13:50 2026
-# Process ID : 171985
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21676 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_fpga_171985.backup.log b/targets/fpga/genesys2/out/logs/program_fpga_171985.backup.log
deleted file mode 100644
index 69c9227..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga_171985.backup.log
+++ /dev/null
@@ -1,71 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 18:13:50 2026
-# Process ID : 171985
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21676 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80
-ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/200300BB2D80.
-Check cable connectivity and that the target board is powered up then
-use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
-ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors.
-
- while executing
-"open_hw_target"
- (file "/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl" line 16)
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 18:13:58 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_fpga_172221.backup.jou b/targets/fpga/genesys2/out/logs/program_fpga_172221.backup.jou
deleted file mode 100644
index f48c846..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga_172221.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 18:14:08 2026
-# Process ID : 172221
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21655 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_fpga_172221.backup.log b/targets/fpga/genesys2/out/logs/program_fpga_172221.backup.log
deleted file mode 100644
index 71d9b70..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga_172221.backup.log
+++ /dev/null
@@ -1,71 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 18:14:08 2026
-# Process ID : 172221
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21655 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80
-ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/200300BB2D80.
-Check cable connectivity and that the target board is powered up then
-use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
-ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors.
-
- while executing
-"open_hw_target"
- (file "/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl" line 16)
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 18:14:16 2026...
diff --git a/targets/fpga/genesys2/out/logs/program_fpga_172480.backup.jou b/targets/fpga/genesys2/out/logs/program_fpga_172480.backup.jou
deleted file mode 100644
index 5c965d1..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga_172480.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 18:14:44 2026
-# Process ID : 172480
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21694 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
diff --git a/targets/fpga/genesys2/out/logs/program_fpga_172480.backup.log b/targets/fpga/genesys2/out/logs/program_fpga_172480.backup.log
deleted file mode 100644
index 4eed430..0000000
--- a/targets/fpga/genesys2/out/logs/program_fpga_172480.backup.log
+++ /dev/null
@@ -1,71 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 18:14:44 2026
-# Process ID : 172480
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21694 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
-# open_hw_manager
-# connect_hw_server
-INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
-INFO: [Labtools 27-2222] Launching hw_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-****** Xilinx hw_server v2025.2
- **** Build date : Oct 28 2025 at 16:07:00
- ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-
-
-INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
-INFO: [Labtools 27-3417] Launching cs_server...
-INFO: [Labtools 27-2221] Launch Output:
-
-
-******** Xilinx cs_server v2025.2.0
- ****** Build date : Nov 14 2025-02:16:52
- **** Build number : 2025.2.1763075812
- ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
- ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-
-# open_hw_target
-INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80
-ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/200300BB2D80.
-Check cable connectivity and that the target board is powered up then
-use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
-ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors.
-
- while executing
-"open_hw_target"
- (file "/home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl" line 16)
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 18:14:52 2026...
diff --git a/targets/fpga/genesys2/out/logs/write_flash.jou b/targets/fpga/genesys2/out/logs/write_flash.jou
deleted file mode 100644
index 1db8163..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 11:10:57 2026
-# Process ID : 4999
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21129 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/write_flash.log b/targets/fpga/genesys2/out/logs/write_flash.log
deleted file mode 100644
index 25331ed..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash.log
+++ /dev/null
@@ -1,137 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 11:10:57 2026
-# Process ID : 4999
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21129 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# proc region_end {offset file} {
-# return [expr {$offset + [file size $file]}]
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set bin_file [file normalize [getenv_default FLASH_BIN [file join $fpga_dir out flash genesys2_rocket.bin]]]
-# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
-# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
-# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
-# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
-# file mkdir [file dirname $mcs_file]
-# file mkdir [file dirname $bin_file]
-# if {![file exists $bit_file]} {
-# error "Bitstream not found: $bit_file"
-# }
-# if {![file exists $app_image]} {
-# error "Application flash image not found: $app_image"
-# }
-# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
-# set bitstream_end [region_end $bitstream_offset $bit_file]
-# set app_end [region_end $app_flash_offset $app_image]
-# if {$bitstream_end > $flash_size_bytes} {
-# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
-# }
-# if {$app_end > $flash_size_bytes} {
-# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
-# }
-# if {$bitstream_offset < $app_end && $app_flash_offset < $bitstream_end} {
-# error [format "Bitstream/app flash regions overlap: bit=[0x%08x,0x%08x) app=[0x%08x,0x%08x)" \
-# $bitstream_offset $bitstream_end $app_flash_offset $app_end]
-# }
-# puts "Generating flash MCS:"
-Generating flash MCS:
-# puts " bitstream: $bit_file @ $bitstream_offset"
- bitstream: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit @ 0x00000000
-# puts " app image: $app_image @ $app_flash_offset"
- app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin @ 0x01800000
-# puts " size/interface: ${flash_size_mb}MiB $flash_interface"
- size/interface: 32MiB SPIx4
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
- flash size: 0x02000000 bytes
-# puts [format " bitstream end: 0x%08x" $bitstream_end]
- bitstream end: 0x00ae9e20
-# puts [format " app end: 0x%08x" $app_end]
- app end: 0x018134a0
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $mcs_file
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181349F Jul 11 11:10:56 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# write_cfgmem -force -format BIN -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $bin_file
-Command: write_cfgmem -force -format BIN -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format BIN
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181349F Jul 11 11:10:56 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# puts "Wrote $mcs_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-# puts "Wrote $bin_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 11:11:02 2026...
diff --git a/targets/fpga/genesys2/out/logs/write_flash_127934.backup.jou b/targets/fpga/genesys2/out/logs/write_flash_127934.backup.jou
deleted file mode 100644
index c0b3b8a..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_127934.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 03:43:53 2026
-# Process ID : 127934
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20257 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/write_flash_127934.backup.log b/targets/fpga/genesys2/out/logs/write_flash_127934.backup.log
deleted file mode 100644
index ffe6f3f..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_127934.backup.log
+++ /dev/null
@@ -1,137 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 03:43:53 2026
-# Process ID : 127934
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20257 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# proc region_end {offset file} {
-# return [expr {$offset + [file size $file]}]
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set bin_file [file normalize [getenv_default FLASH_BIN [file join $fpga_dir out flash genesys2_rocket.bin]]]
-# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
-# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
-# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
-# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
-# file mkdir [file dirname $mcs_file]
-# file mkdir [file dirname $bin_file]
-# if {![file exists $bit_file]} {
-# error "Bitstream not found: $bit_file"
-# }
-# if {![file exists $app_image]} {
-# error "Application flash image not found: $app_image"
-# }
-# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
-# set bitstream_end [region_end $bitstream_offset $bit_file]
-# set app_end [region_end $app_flash_offset $app_image]
-# if {$bitstream_end > $flash_size_bytes} {
-# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
-# }
-# if {$app_end > $flash_size_bytes} {
-# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
-# }
-# if {$bitstream_offset < $app_end && $app_flash_offset < $bitstream_end} {
-# error [format "Bitstream/app flash regions overlap: bit=[0x%08x,0x%08x) app=[0x%08x,0x%08x)" \
-# $bitstream_offset $bitstream_end $app_flash_offset $app_end]
-# }
-# puts "Generating flash MCS:"
-Generating flash MCS:
-# puts " bitstream: $bit_file @ $bitstream_offset"
- bitstream: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit @ 0x00000000
-# puts " app image: $app_image @ $app_flash_offset"
- app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin @ 0x01800000
-# puts " size/interface: ${flash_size_mb}MiB $flash_interface"
- size/interface: 32MiB SPIx4
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
- flash size: 0x02000000 bytes
-# puts [format " bitstream end: 0x%08x" $bitstream_end]
- bitstream end: 0x00ae9e20
-# puts [format " app end: 0x%08x" $app_end]
- app end: 0x01814850
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $mcs_file
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181484F Jul 11 03:43:52 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# write_cfgmem -force -format BIN -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $bin_file
-Command: write_cfgmem -force -format BIN -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format BIN
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181484F Jul 11 03:43:52 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# puts "Wrote $mcs_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-# puts "Wrote $bin_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 03:43:56 2026...
diff --git a/targets/fpga/genesys2/out/logs/write_flash_128044.backup.jou b/targets/fpga/genesys2/out/logs/write_flash_128044.backup.jou
deleted file mode 100644
index 978712c..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_128044.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 03:44:03 2026
-# Process ID : 128044
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20213 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/write_flash_128044.backup.log b/targets/fpga/genesys2/out/logs/write_flash_128044.backup.log
deleted file mode 100644
index 9423578..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_128044.backup.log
+++ /dev/null
@@ -1,137 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 03:44:03 2026
-# Process ID : 128044
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20213 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# proc region_end {offset file} {
-# return [expr {$offset + [file size $file]}]
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set bin_file [file normalize [getenv_default FLASH_BIN [file join $fpga_dir out flash genesys2_rocket.bin]]]
-# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
-# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
-# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
-# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
-# file mkdir [file dirname $mcs_file]
-# file mkdir [file dirname $bin_file]
-# if {![file exists $bit_file]} {
-# error "Bitstream not found: $bit_file"
-# }
-# if {![file exists $app_image]} {
-# error "Application flash image not found: $app_image"
-# }
-# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
-# set bitstream_end [region_end $bitstream_offset $bit_file]
-# set app_end [region_end $app_flash_offset $app_image]
-# if {$bitstream_end > $flash_size_bytes} {
-# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
-# }
-# if {$app_end > $flash_size_bytes} {
-# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
-# }
-# if {$bitstream_offset < $app_end && $app_flash_offset < $bitstream_end} {
-# error [format "Bitstream/app flash regions overlap: bit=[0x%08x,0x%08x) app=[0x%08x,0x%08x)" \
-# $bitstream_offset $bitstream_end $app_flash_offset $app_end]
-# }
-# puts "Generating flash MCS:"
-Generating flash MCS:
-# puts " bitstream: $bit_file @ $bitstream_offset"
- bitstream: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit @ 0x00000000
-# puts " app image: $app_image @ $app_flash_offset"
- app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin @ 0x01800000
-# puts " size/interface: ${flash_size_mb}MiB $flash_interface"
- size/interface: 32MiB SPIx4
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
- flash size: 0x02000000 bytes
-# puts [format " bitstream end: 0x%08x" $bitstream_end]
- bitstream end: 0x00ae9e20
-# puts [format " app end: 0x%08x" $app_end]
- app end: 0x01814850
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $mcs_file
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181484F Jul 11 03:44:02 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# write_cfgmem -force -format BIN -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $bin_file
-Command: write_cfgmem -force -format BIN -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format BIN
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181484F Jul 11 03:44:02 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# puts "Wrote $mcs_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-# puts "Wrote $bin_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 03:44:07 2026...
diff --git a/targets/fpga/genesys2/out/logs/write_flash_129573.backup.jou b/targets/fpga/genesys2/out/logs/write_flash_129573.backup.jou
deleted file mode 100644
index 724d396..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_129573.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 03:57:01 2026
-# Process ID : 129573
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20249 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/write_flash_129573.backup.log b/targets/fpga/genesys2/out/logs/write_flash_129573.backup.log
deleted file mode 100644
index 6c091ef..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_129573.backup.log
+++ /dev/null
@@ -1,137 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 03:57:01 2026
-# Process ID : 129573
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20249 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# proc region_end {offset file} {
-# return [expr {$offset + [file size $file]}]
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set bin_file [file normalize [getenv_default FLASH_BIN [file join $fpga_dir out flash genesys2_rocket.bin]]]
-# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
-# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
-# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
-# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
-# file mkdir [file dirname $mcs_file]
-# file mkdir [file dirname $bin_file]
-# if {![file exists $bit_file]} {
-# error "Bitstream not found: $bit_file"
-# }
-# if {![file exists $app_image]} {
-# error "Application flash image not found: $app_image"
-# }
-# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
-# set bitstream_end [region_end $bitstream_offset $bit_file]
-# set app_end [region_end $app_flash_offset $app_image]
-# if {$bitstream_end > $flash_size_bytes} {
-# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
-# }
-# if {$app_end > $flash_size_bytes} {
-# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
-# }
-# if {$bitstream_offset < $app_end && $app_flash_offset < $bitstream_end} {
-# error [format "Bitstream/app flash regions overlap: bit=[0x%08x,0x%08x) app=[0x%08x,0x%08x)" \
-# $bitstream_offset $bitstream_end $app_flash_offset $app_end]
-# }
-# puts "Generating flash MCS:"
-Generating flash MCS:
-# puts " bitstream: $bit_file @ $bitstream_offset"
- bitstream: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit @ 0x00000000
-# puts " app image: $app_image @ $app_flash_offset"
- app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin @ 0x01800000
-# puts " size/interface: ${flash_size_mb}MiB $flash_interface"
- size/interface: 32MiB SPIx4
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
- flash size: 0x02000000 bytes
-# puts [format " bitstream end: 0x%08x" $bitstream_end]
- bitstream end: 0x00ae9e20
-# puts [format " app end: 0x%08x" $app_end]
- app end: 0x01814850
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $mcs_file
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181484F Jul 11 03:57:00 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# write_cfgmem -force -format BIN -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $bin_file
-Command: write_cfgmem -force -format BIN -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format BIN
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181484F Jul 11 03:57:00 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# puts "Wrote $mcs_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-# puts "Wrote $bin_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 03:57:05 2026...
diff --git a/targets/fpga/genesys2/out/logs/write_flash_3720.backup.jou b/targets/fpga/genesys2/out/logs/write_flash_3720.backup.jou
deleted file mode 100644
index fe8b5e7..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_3720.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 11:02:51 2026
-# Process ID : 3720
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22483 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/write_flash_3720.backup.log b/targets/fpga/genesys2/out/logs/write_flash_3720.backup.log
deleted file mode 100644
index adbbb6f..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_3720.backup.log
+++ /dev/null
@@ -1,137 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 11:02:51 2026
-# Process ID : 3720
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22483 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# proc region_end {offset file} {
-# return [expr {$offset + [file size $file]}]
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set bin_file [file normalize [getenv_default FLASH_BIN [file join $fpga_dir out flash genesys2_rocket.bin]]]
-# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
-# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
-# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
-# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
-# file mkdir [file dirname $mcs_file]
-# file mkdir [file dirname $bin_file]
-# if {![file exists $bit_file]} {
-# error "Bitstream not found: $bit_file"
-# }
-# if {![file exists $app_image]} {
-# error "Application flash image not found: $app_image"
-# }
-# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
-# set bitstream_end [region_end $bitstream_offset $bit_file]
-# set app_end [region_end $app_flash_offset $app_image]
-# if {$bitstream_end > $flash_size_bytes} {
-# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
-# }
-# if {$app_end > $flash_size_bytes} {
-# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
-# }
-# if {$bitstream_offset < $app_end && $app_flash_offset < $bitstream_end} {
-# error [format "Bitstream/app flash regions overlap: bit=[0x%08x,0x%08x) app=[0x%08x,0x%08x)" \
-# $bitstream_offset $bitstream_end $app_flash_offset $app_end]
-# }
-# puts "Generating flash MCS:"
-Generating flash MCS:
-# puts " bitstream: $bit_file @ $bitstream_offset"
- bitstream: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit @ 0x00000000
-# puts " app image: $app_image @ $app_flash_offset"
- app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin @ 0x01800000
-# puts " size/interface: ${flash_size_mb}MiB $flash_interface"
- size/interface: 32MiB SPIx4
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
- flash size: 0x02000000 bytes
-# puts [format " bitstream end: 0x%08x" $bitstream_end]
- bitstream end: 0x00ae9e20
-# puts [format " app end: 0x%08x" $app_end]
- app end: 0x018134a0
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $mcs_file
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181349F Jul 11 11:02:49 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# write_cfgmem -force -format BIN -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $bin_file
-Command: write_cfgmem -force -format BIN -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format BIN
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181349F Jul 11 11:02:49 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# puts "Wrote $mcs_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-# puts "Wrote $bin_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 11:03:03 2026...
diff --git a/targets/fpga/genesys2/out/logs/write_flash_4308.backup.jou b/targets/fpga/genesys2/out/logs/write_flash_4308.backup.jou
deleted file mode 100644
index f010d7c..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_4308.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 11:04:38 2026
-# Process ID : 4308
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21217 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
diff --git a/targets/fpga/genesys2/out/logs/write_flash_4308.backup.log b/targets/fpga/genesys2/out/logs/write_flash_4308.backup.log
deleted file mode 100644
index 166a3c4..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_4308.backup.log
+++ /dev/null
@@ -1,137 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 11:04:38 2026
-# Process ID : 4308
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.924 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21217 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# proc region_end {offset file} {
-# return [expr {$offset + [file size $file]}]
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
-# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
-# set bin_file [file normalize [getenv_default FLASH_BIN [file join $fpga_dir out flash genesys2_rocket.bin]]]
-# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
-# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
-# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
-# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
-# file mkdir [file dirname $mcs_file]
-# file mkdir [file dirname $bin_file]
-# if {![file exists $bit_file]} {
-# error "Bitstream not found: $bit_file"
-# }
-# if {![file exists $app_image]} {
-# error "Application flash image not found: $app_image"
-# }
-# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
-# set bitstream_end [region_end $bitstream_offset $bit_file]
-# set app_end [region_end $app_flash_offset $app_image]
-# if {$bitstream_end > $flash_size_bytes} {
-# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
-# }
-# if {$app_end > $flash_size_bytes} {
-# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
-# }
-# if {$bitstream_offset < $app_end && $app_flash_offset < $bitstream_end} {
-# error [format "Bitstream/app flash regions overlap: bit=[0x%08x,0x%08x) app=[0x%08x,0x%08x)" \
-# $bitstream_offset $bitstream_end $app_flash_offset $app_end]
-# }
-# puts "Generating flash MCS:"
-Generating flash MCS:
-# puts " bitstream: $bit_file @ $bitstream_offset"
- bitstream: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit @ 0x00000000
-# puts " app image: $app_image @ $app_flash_offset"
- app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin @ 0x01800000
-# puts " size/interface: ${flash_size_mb}MiB $flash_interface"
- size/interface: 32MiB SPIx4
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
- flash size: 0x02000000 bytes
-# puts [format " bitstream end: 0x%08x" $bitstream_end]
- bitstream end: 0x00ae9e20
-# puts [format " app end: 0x%08x" $app_end]
- app end: 0x018134a0
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $mcs_file
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181349F Jul 11 11:04:37 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# write_cfgmem -force -format BIN -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# -loaddata "up $app_flash_offset $app_image" \
-# $bin_file
-Command: write_cfgmem -force -format BIN -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
-===================================
-Configuration Memory information
-===================================
-File Format BIN
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0x01800000 0x0181349F Jul 11 11:04:37 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-# puts "Wrote $mcs_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
-# puts "Wrote $bin_file"
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 11:04:44 2026...
diff --git a/targets/fpga/genesys2/out/logs/write_flash_regions.jou b/targets/fpga/genesys2/out/logs/write_flash_regions.jou
deleted file mode 100644
index 2ac919c..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_regions.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 00:16:14 2026
-# Process ID : 90489
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20488 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
diff --git a/targets/fpga/genesys2/out/logs/write_flash_regions.log b/targets/fpga/genesys2/out/logs/write_flash_regions.log
deleted file mode 100644
index d2bc218..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_regions.log
+++ /dev/null
@@ -1,117 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 00:16:14 2026
-# Process ID : 90489
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20488 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# proc region_end {offset file} {
-# return [expr {$offset + [file size $file]}]
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
-# set bitstream_mcs [file normalize [getenv_default BITSTREAM_MCS [file join $fpga_dir out flash regions bitstream.mcs]]]
-# set app_mcs [file normalize [getenv_default APP_MCS [file join $fpga_dir out flash regions app.mcs]]]
-# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
-# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
-# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
-# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
-# set region_names [split [getenv_default FLASH_REGION_NAMES "bitstream;app"] ";"]
-# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
-# foreach region $region_names {
-# if {$region eq ""} {
-# continue
-# } elseif {$region eq "bitstream"} {
-# if {![file exists $bit_file]} {
-# error "Bitstream not found: $bit_file"
-# }
-# set bitstream_end [region_end $bitstream_offset $bit_file]
-# if {$bitstream_end > $flash_size_bytes} {
-# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
-# }
-# if {$bitstream_end > $app_flash_offset} {
-# error [format "Bitstream region crosses APP_FLASH_OFFSET: bit_end=0x%08x app_offset=0x%08x" \
-# $bitstream_end $app_flash_offset]
-# }
-# file mkdir [file dirname $bitstream_mcs]
-# puts "Generating bitstream region MCS:"
-# puts " bitstream: $bit_file @ $bitstream_offset"
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
-# puts [format " bitstream end: 0x%08x" $bitstream_end]
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# $bitstream_mcs
-# puts "Wrote $bitstream_mcs"
-# } elseif {$region eq "app"} {
-# if {![file exists $app_image]} {
-# error "Application flash image not found: $app_image"
-# }
-# set app_end [region_end $app_flash_offset $app_image]
-# if {$app_end > $flash_size_bytes} {
-# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
-# }
-# file mkdir [file dirname $app_mcs]
-# puts "Generating app region MCS:"
-# puts " app image: $app_image @ $app_flash_offset"
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
-# puts [format " app end: 0x%08x" $app_end]
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loaddata "up $app_flash_offset $app_image" \
-# $app_mcs
-# puts "Wrote $app_mcs"
-# } else {
-# error "Unknown flash region: $region"
-# }
-# }
-Generating app region MCS:
- app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin @ 0x01800000
- flash size: 0x02000000 bytes
- app end: 0x01814648
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x01800000 0x01814647 Jul 11 00:16:13 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 00:16:16 2026...
diff --git a/targets/fpga/genesys2/out/logs/write_flash_regions_5150.backup.jou b/targets/fpga/genesys2/out/logs/write_flash_regions_5150.backup.jou
deleted file mode 100644
index 4ece4b6..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_regions_5150.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Wed Jul 8 01:07:52 2026
-# Process ID : 5150
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22418 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
diff --git a/targets/fpga/genesys2/out/logs/write_flash_regions_5150.backup.log b/targets/fpga/genesys2/out/logs/write_flash_regions_5150.backup.log
deleted file mode 100644
index 7c48a37..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_regions_5150.backup.log
+++ /dev/null
@@ -1,117 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Wed Jul 8 01:07:52 2026
-# Process ID : 5150
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22418 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# proc region_end {offset file} {
-# return [expr {$offset + [file size $file]}]
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
-# set bitstream_mcs [file normalize [getenv_default BITSTREAM_MCS [file join $fpga_dir out flash regions bitstream.mcs]]]
-# set app_mcs [file normalize [getenv_default APP_MCS [file join $fpga_dir out flash regions app.mcs]]]
-# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
-# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
-# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
-# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
-# set region_names [split [getenv_default FLASH_REGION_NAMES "bitstream;app"] ";"]
-# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
-# foreach region $region_names {
-# if {$region eq ""} {
-# continue
-# } elseif {$region eq "bitstream"} {
-# if {![file exists $bit_file]} {
-# error "Bitstream not found: $bit_file"
-# }
-# set bitstream_end [region_end $bitstream_offset $bit_file]
-# if {$bitstream_end > $flash_size_bytes} {
-# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
-# }
-# if {$bitstream_end > $app_flash_offset} {
-# error [format "Bitstream region crosses APP_FLASH_OFFSET: bit_end=0x%08x app_offset=0x%08x" \
-# $bitstream_end $app_flash_offset]
-# }
-# file mkdir [file dirname $bitstream_mcs]
-# puts "Generating bitstream region MCS:"
-# puts " bitstream: $bit_file @ $bitstream_offset"
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
-# puts [format " bitstream end: 0x%08x" $bitstream_end]
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# $bitstream_mcs
-# puts "Wrote $bitstream_mcs"
-# } elseif {$region eq "app"} {
-# if {![file exists $app_image]} {
-# error "Application flash image not found: $app_image"
-# }
-# set app_end [region_end $app_flash_offset $app_image]
-# if {$app_end > $flash_size_bytes} {
-# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
-# }
-# file mkdir [file dirname $app_mcs]
-# puts "Generating app region MCS:"
-# puts " app image: $app_image @ $app_flash_offset"
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
-# puts [format " app end: 0x%08x" $app_end]
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loaddata "up $app_flash_offset $app_image" \
-# $app_mcs
-# puts "Wrote $app_mcs"
-# } else {
-# error "Unknown flash region: $region"
-# }
-# }
-Generating bitstream region MCS:
- bitstream: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit @ 0x00000000
- flash size: 0x02000000 bytes
- bitstream end: 0x00ae9e20
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/bitstream.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/bitstream.mcs
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/bitstream.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 8 00:49:43 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/bitstream.mcs
-INFO: [Common 17-206] Exiting Vivado at Wed Jul 8 01:07:56 2026...
diff --git a/targets/fpga/genesys2/out/logs/write_flash_regions_62276.backup.jou b/targets/fpga/genesys2/out/logs/write_flash_regions_62276.backup.jou
deleted file mode 100644
index 2f8b766..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_regions_62276.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Thu Jul 9 20:19:47 2026
-# Process ID : 62276
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21986 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
diff --git a/targets/fpga/genesys2/out/logs/write_flash_regions_62276.backup.log b/targets/fpga/genesys2/out/logs/write_flash_regions_62276.backup.log
deleted file mode 100644
index 7aab9b8..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_regions_62276.backup.log
+++ /dev/null
@@ -1,117 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Thu Jul 9 20:19:47 2026
-# Process ID : 62276
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 21986 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# proc region_end {offset file} {
-# return [expr {$offset + [file size $file]}]
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
-# set bitstream_mcs [file normalize [getenv_default BITSTREAM_MCS [file join $fpga_dir out flash regions bitstream.mcs]]]
-# set app_mcs [file normalize [getenv_default APP_MCS [file join $fpga_dir out flash regions app.mcs]]]
-# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
-# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
-# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
-# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
-# set region_names [split [getenv_default FLASH_REGION_NAMES "bitstream;app"] ";"]
-# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
-# foreach region $region_names {
-# if {$region eq ""} {
-# continue
-# } elseif {$region eq "bitstream"} {
-# if {![file exists $bit_file]} {
-# error "Bitstream not found: $bit_file"
-# }
-# set bitstream_end [region_end $bitstream_offset $bit_file]
-# if {$bitstream_end > $flash_size_bytes} {
-# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
-# }
-# if {$bitstream_end > $app_flash_offset} {
-# error [format "Bitstream region crosses APP_FLASH_OFFSET: bit_end=0x%08x app_offset=0x%08x" \
-# $bitstream_end $app_flash_offset]
-# }
-# file mkdir [file dirname $bitstream_mcs]
-# puts "Generating bitstream region MCS:"
-# puts " bitstream: $bit_file @ $bitstream_offset"
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
-# puts [format " bitstream end: 0x%08x" $bitstream_end]
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# $bitstream_mcs
-# puts "Wrote $bitstream_mcs"
-# } elseif {$region eq "app"} {
-# if {![file exists $app_image]} {
-# error "Application flash image not found: $app_image"
-# }
-# set app_end [region_end $app_flash_offset $app_image]
-# if {$app_end > $flash_size_bytes} {
-# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
-# }
-# file mkdir [file dirname $app_mcs]
-# puts "Generating app region MCS:"
-# puts " app image: $app_image @ $app_flash_offset"
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
-# puts [format " app end: 0x%08x" $app_end]
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loaddata "up $app_flash_offset $app_image" \
-# $app_mcs
-# puts "Wrote $app_mcs"
-# } else {
-# error "Unknown flash region: $region"
-# }
-# }
-Generating app region MCS:
- app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin @ 0x01800000
- flash size: 0x02000000 bytes
- app end: 0x01814748
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x01800000 0x01814747 Jul 9 20:19:46 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-INFO: [Common 17-206] Exiting Vivado at Thu Jul 9 20:19:49 2026...
diff --git a/targets/fpga/genesys2/out/logs/write_flash_regions_62352.backup.jou b/targets/fpga/genesys2/out/logs/write_flash_regions_62352.backup.jou
deleted file mode 100644
index 88b9740..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_regions_62352.backup.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Tue Jul 7 18:24:32 2026
-# Process ID : 62352
-# Current directory : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log -journal /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou -source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# Log file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log
-# Journal file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22195 MB
-#-----------------------------------------------------------
-source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
diff --git a/targets/fpga/genesys2/out/logs/write_flash_regions_62352.backup.log b/targets/fpga/genesys2/out/logs/write_flash_regions_62352.backup.log
deleted file mode 100644
index faff96a..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_regions_62352.backup.log
+++ /dev/null
@@ -1,141 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Tue Jul 7 18:24:32 2026
-# Process ID : 62352
-# Current directory : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log -journal /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou -source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# Log file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log
-# Journal file : /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.918 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 22195 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# proc region_end {offset file} {
-# return [expr {$offset + [file size $file]}]
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
-# set bitstream_mcs [file normalize [getenv_default BITSTREAM_MCS [file join $fpga_dir out flash regions bitstream.mcs]]]
-# set app_mcs [file normalize [getenv_default APP_MCS [file join $fpga_dir out flash regions app.mcs]]]
-# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
-# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
-# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
-# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
-# set region_names [split [getenv_default FLASH_REGION_NAMES "bitstream;app"] ";"]
-# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
-# foreach region $region_names {
-# if {$region eq ""} {
-# continue
-# } elseif {$region eq "bitstream"} {
-# if {![file exists $bit_file]} {
-# error "Bitstream not found: $bit_file"
-# }
-# set bitstream_end [region_end $bitstream_offset $bit_file]
-# if {$bitstream_end > $flash_size_bytes} {
-# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
-# }
-# if {$bitstream_end > $app_flash_offset} {
-# error [format "Bitstream region crosses APP_FLASH_OFFSET: bit_end=0x%08x app_offset=0x%08x" \
-# $bitstream_end $app_flash_offset]
-# }
-# file mkdir [file dirname $bitstream_mcs]
-# puts "Generating bitstream region MCS:"
-# puts " bitstream: $bit_file @ $bitstream_offset"
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
-# puts [format " bitstream end: 0x%08x" $bitstream_end]
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# $bitstream_mcs
-# puts "Wrote $bitstream_mcs"
-# } elseif {$region eq "app"} {
-# if {![file exists $app_image]} {
-# error "Application flash image not found: $app_image"
-# }
-# set app_end [region_end $app_flash_offset $app_image]
-# if {$app_end > $flash_size_bytes} {
-# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
-# }
-# file mkdir [file dirname $app_mcs]
-# puts "Generating app region MCS:"
-# puts " app image: $app_image @ $app_flash_offset"
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
-# puts [format " app end: 0x%08x" $app_end]
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loaddata "up $app_flash_offset $app_image" \
-# $app_mcs
-# puts "Wrote $app_mcs"
-# } else {
-# error "Unknown flash region: $region"
-# }
-# }
-Generating bitstream region MCS:
- bitstream: /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit @ 0x00000000
- flash size: 0x02000000 bytes
- bitstream end: 0x00ae9e20
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/regions/bitstream.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x00000000
-Loading bitfile /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-Writing file /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/regions/bitstream.mcs
-Writing log file /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/regions/bitstream.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x00000000 0x00AE9D9B Jul 7 17:42:59 2026 /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-Wrote /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/regions/bitstream.mcs
-Generating app region MCS:
- app image: /home/onur/Desktop/tmp/rocket-chip/soc/out/flash/hello_uart.flash.bin @ 0x01800000
- flash size: 0x02000000 bytes
- app end: 0x01809ff0
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loaddata {up 0x01800000 /home/onur/Desktop/tmp/rocket-chip/soc/out/flash/hello_uart.flash.bin} /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/tmp/rocket-chip/soc/out/flash/hello_uart.flash.bin
-Writing file /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-Writing log file /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x01800000 0x01809FEF Jul 7 18:24:31 2026 /home/onur/Desktop/tmp/rocket-chip/soc/out/flash/hello_uart.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-Wrote /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-INFO: [Common 17-206] Exiting Vivado at Tue Jul 7 18:24:35 2026...
diff --git a/targets/fpga/genesys2/out/logs/write_flash_regions_offline_check.jou b/targets/fpga/genesys2/out/logs/write_flash_regions_offline_check.jou
deleted file mode 100644
index 6364acd..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_regions_offline_check.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 00:13:03 2026
-# Process ID : 89816
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log write_flash_regions_offline_check.log -journal write_flash_regions_offline_check.jou -source ../../flow/vivado/scripts/write_flash_regions.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions_offline_check.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions_offline_check.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20344 MB
-#-----------------------------------------------------------
-source ../../flow/vivado/scripts/write_flash_regions.tcl
diff --git a/targets/fpga/genesys2/out/logs/write_flash_regions_offline_check.log b/targets/fpga/genesys2/out/logs/write_flash_regions_offline_check.log
deleted file mode 100644
index 9f8c9e5..0000000
--- a/targets/fpga/genesys2/out/logs/write_flash_regions_offline_check.log
+++ /dev/null
@@ -1,117 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2025.2 (64-bit)
-# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
-# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
-# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
-# Start of session at: Sat Jul 11 00:13:03 2026
-# Process ID : 89816
-# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
-# Command line : vivado -mode batch -log write_flash_regions_offline_check.log -journal write_flash_regions_offline_check.jou -source ../../flow/vivado/scripts/write_flash_regions.tcl
-# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions_offline_check.log
-# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions_offline_check.jou
-# Running On : onur
-# Platform : Ubuntu
-# Operating System : Ubuntu 22.04.5 LTS
-# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
-# CPU Frequency : 4199.910 MHz
-# CPU Physical cores : 12
-# CPU Logical cores : 12
-# Host memory : 22112 MB
-# Swap memory : 2147 MB
-# Total Virtual : 24260 MB
-# Available Virtual : 20344 MB
-#-----------------------------------------------------------
-Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
-Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
-source ../../flow/vivado/scripts/write_flash_regions.tcl
-# set script_dir [file dirname [file normalize [info script]]]
-# set fpga_dir [file normalize [file join $script_dir ../..]]
-# proc getenv_default {name default} {
-# if {[info exists ::env($name)] && $::env($name) ne ""} {
-# return $::env($name)
-# }
-# return $default
-# }
-# proc region_end {offset file} {
-# return [expr {$offset + [file size $file]}]
-# }
-# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
-# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
-# set bitstream_mcs [file normalize [getenv_default BITSTREAM_MCS [file join $fpga_dir out flash regions bitstream.mcs]]]
-# set app_mcs [file normalize [getenv_default APP_MCS [file join $fpga_dir out flash regions app.mcs]]]
-# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
-# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
-# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
-# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
-# set region_names [split [getenv_default FLASH_REGION_NAMES "bitstream;app"] ";"]
-# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
-# foreach region $region_names {
-# if {$region eq ""} {
-# continue
-# } elseif {$region eq "bitstream"} {
-# if {![file exists $bit_file]} {
-# error "Bitstream not found: $bit_file"
-# }
-# set bitstream_end [region_end $bitstream_offset $bit_file]
-# if {$bitstream_end > $flash_size_bytes} {
-# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
-# }
-# if {$bitstream_end > $app_flash_offset} {
-# error [format "Bitstream region crosses APP_FLASH_OFFSET: bit_end=0x%08x app_offset=0x%08x" \
-# $bitstream_end $app_flash_offset]
-# }
-# file mkdir [file dirname $bitstream_mcs]
-# puts "Generating bitstream region MCS:"
-# puts " bitstream: $bit_file @ $bitstream_offset"
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
-# puts [format " bitstream end: 0x%08x" $bitstream_end]
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loadbit "up $bitstream_offset $bit_file" \
-# $bitstream_mcs
-# puts "Wrote $bitstream_mcs"
-# } elseif {$region eq "app"} {
-# if {![file exists $app_image]} {
-# error "Application flash image not found: $app_image"
-# }
-# set app_end [region_end $app_flash_offset $app_image]
-# if {$app_end > $flash_size_bytes} {
-# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
-# }
-# file mkdir [file dirname $app_mcs]
-# puts "Generating app region MCS:"
-# puts " app image: $app_image @ $app_flash_offset"
-# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
-# puts [format " app end: 0x%08x" $app_end]
-# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
-# -loaddata "up $app_flash_offset $app_image" \
-# $app_mcs
-# puts "Wrote $app_mcs"
-# } else {
-# error "Unknown flash region: $region"
-# }
-# }
-Generating app region MCS:
- app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/hello_uart.flash.bin @ 0x01800000
- flash size: 0x02000000 bytes
- app end: 0x01809ff0
-Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/hello_uart.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-Creating config memory files...
-Creating bitstream load up from address 0x01800000
-Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/hello_uart.flash.bin
-Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.prm
-===================================
-Configuration Memory information
-===================================
-File Format MCS
-Interface SPIX4
-Size 32M
-Start Address 0x00000000
-End Address 0x01FFFFFF
-
-Addr1 Addr2 Date File(s)
-0x01800000 0x01809FEF Jul 11 00:12:52 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/hello_uart.flash.bin
-0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_cfgmem completed successfully
-Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 00:13:04 2026...
diff --git a/targets/fpga/genesys2/out/reports/route_drc.rpt b/targets/fpga/genesys2/out/reports/route_drc.rpt
deleted file mode 100644
index 83d4f68..0000000
--- a/targets/fpga/genesys2/out/reports/route_drc.rpt
+++ /dev/null
@@ -1,8019 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
-| Date : Thu Aug 6 21:33:36 2026
-| Host : ankalab04 running 64-bit Ubuntu 24.04.4 LTS
-| Command : report_drc -file /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/reports/route_drc.rpt
-| Design : genesys2_rocket_top
-| Device : xc7k325tffg900-2
-| Speed File : -2
-| Design State : Fully Routed
----------------------------------------------------------------------------------------------------------------------------------------------
-
-Report DRC
-
-Table of Contents
------------------
-1. REPORT SUMMARY
-2. REPORT DETAILS
-
-1. REPORT SUMMARY
------------------
- Netlist: genesys2_rocket_top
- Floorplan: design_1
- Design limits:
- Ruledeck: default
- Max checks:
- Checks found: 1595
-+-----------+----------+-----------------------------+--------+
-| Rule | Severity | Description | Checks |
-+-----------+----------+-----------------------------+--------+
-| CHECK-3 | Warning | Report rule limit reached | 2 |
-| DPIP-1 | Warning | Input pipelining | 323 |
-| DPOP-1 | Warning | PREG Output pipelining | 106 |
-| DPOP-2 | Warning | MREG Output pipelining | 184 |
-| DPOR-1 | Warning | Asynchronous load check | 927 |
-| DPREG-4 | Warning | DSP48E1_PregDynOpmodeZmuxP: | 4 |
-| PDRC-153 | Warning | Gated clock check | 9 |
-| REQP-1839 | Warning | RAMB36 async control check | 20 |
-| REQP-1840 | Warning | RAMB18 async control check | 20 |
-+-----------+----------+-----------------------------+--------+
-
-2. REPORT DETAILS
------------------
-CHECK-3#1 Warning
-Report rule limit reached
-REQP-1839 rule limit reached: 20 violations have been found.
-Related violations:
-
-CHECK-3#2 Warning
-Report rule limit reached
-REQP-1840 rule limit reached: 20 violations have been found.
-Related violations:
-
-DPIP-1#1 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#2 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#3 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#4 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#5 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#6 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#7 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#8 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#9 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#10 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#11 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#12 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#13 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#14 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#15 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#16 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#17 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#18 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#19 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#20 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#21 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#22 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#23 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#24 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#25 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#26 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#27 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#28 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#29 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#30 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#31 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#32 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#33 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#34 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#35 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#36 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#37 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#38 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#39 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#40 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#41 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#42 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#43 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#44 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#45 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#46 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#47 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#48 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#49 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#50 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#51 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#52 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#53 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#54 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#55 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#56 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#57 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#58 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#59 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#60 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#61 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#62 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#63 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#64 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#65 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#66 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#67 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#68 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#69 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#70 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#71 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#72 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#73 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#74 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#75 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#76 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#77 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#78 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#79 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#80 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#81 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#82 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#83 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#84 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#85 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#86 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#87 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__10 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#88 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__10 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__10/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#89 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__2 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#90 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__2 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#91 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__3 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#92 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__3 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#93 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__4 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#94 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__4 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#95 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__5 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__5/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#96 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__5 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__5/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#97 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__6 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__6/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#98 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__6 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__6/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#99 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__7 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#100 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__7 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__7/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#101 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__8 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__8/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#102 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__8 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__8/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#103 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__9 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__9/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#104 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__9 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__9/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#105 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#106 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#107 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#108 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#109 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#110 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#111 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__10 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#112 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__10 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__10/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#113 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__2 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#114 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__2 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations:
-
-DPIP-1#115 Warning
-Input pipelining
-DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__3 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
-Related violations: