From dc5796e2fc03153c703f43de34310cae5974001e Mon Sep 17 00:00:00 2001 From: onur Date: Fri, 31 Jul 2026 23:57:16 +0300 Subject: [PATCH] docs: add Ti375C529 Efinity pin and flow details --- README.md | 136 ++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 128 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index 64fd25a..ad1f49b 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,7 @@ # Rocket Project -Bu agac VCU118/Genesys2 FPGA ve ASIC-style Rocket akislari icin sade proje duzenidir. +Bu agac VCU118, Genesys2 ve Ti375C529 FPGA akislari ile ASIC-style Rocket +akisi icin sade proje duzenidir. Upstream Rocket-Chip kaynaklari daginik kok klasorlerde tutulmaz; gerekli upstream kaynaklar `hardware/upstream/rocket-chip/` altindadir. @@ -22,6 +23,7 @@ hardware/ soc/software/ Bootloader, BSP, uygulamalar, flash image tool targets/fpga/vcu118/ VCU118 build/programlama akisi targets/fpga/genesys2/ Genesys2 build/programlama akisi +targets/fpga/ti375c529/ Ti375C529 Efinity build/programlama akisi targets/asic/rocket/ ASIC wrapper/filelist/sim akisi setup_tools.sh /tools/soc-tools host araci kurulum betigi ``` @@ -209,6 +211,7 @@ make -C hardware/fpga/vcu118/rtl help make -C hardware/sim/fpga/vcu118 help make -C targets/fpga/vcu118 help make -C targets/fpga/genesys2 help +make -C targets/fpga/ti375c529 help make -C targets/asic/rocket help ``` @@ -219,6 +222,7 @@ FPGA karti kok Makefile'dan `FPGA_BOARD` ile secilir: ```sh make FPGA_BOARD=vcu118 fpga-config make FPGA_BOARD=genesys2 fpga-config +make FPGA_BOARD=ti375c529 fpga-config ``` Top-level `BOARD=...` alias'i da desteklenir. Orneklerde Genesys2 kullanilir: @@ -232,7 +236,7 @@ Yanlislikla underscore kullanilmasi durumunda yaygin FPGA hedefleri icin alias'lar da vardir (`fpga_program`, `fpga_debug_openocd` gibi). `fpga-config` secilen kartin clock, flash, UART, DTIM ve RF ayarlarini -gosterir. RF kaynagi `RF_INPUT_MODE` ile secilir: +gosterir. Genesys2 ve VCU118'de RF kaynagi `RF_INPUT_MODE` ile secilir: ```text RF_INPUT_MODE=pmod Varsayilan. Harici 4-bit RF data + RF clock PMOD'dan gelir. @@ -240,10 +244,14 @@ RF_INPUT_MODE=generated Dahili RF clock uretilir, RF data sifira baglanir. RF_INPUT_MODE=ethernet Kart bazli raw-Ethernet RF streamer path'i. ``` +Ti375C529 Efinity wrapper'i su anda yalniz harici PMOD RF girisini kullanir; +bu kartta `RF_INPUT_MODE=pmod` birakilmalidir. `generated` ve `ethernet` +yollari Ti375C529 wrapper'ina henuz uygulanmamistir. + Top-level FPGA wrapper'lar elle yazilmaz; `targets/fpga/*/tools/gen_*_wrapper.py` -scriptleri tarafindan uretilir. Bu yuzden RF secimi RTL `ifdef` ile degil, -generator parametresi ile yapilir. `make rtl` ve Vivado `build.tcl` ayni -`RF_INPUT_MODE` degerini wrapper generator'a gecirir. +scriptleri tarafindan uretilir. Genesys2 ve VCU118'de RF secimi RTL `ifdef` +ile degil, generator parametresi ile yapilir. `make rtl` ve Vivado `build.tcl` +ayni `RF_INPUT_MODE` degerini wrapper generator'a gecirir. Varsayilan `pmod` modunda Ethernet RF IP/RTL okunmaz ve top'ta Ethernet PHY portlari olusmaz. Ethernet RF akisi gerektiginde: @@ -275,11 +283,23 @@ uzerinden 1.8 V bank/LVCMOS18: rf_data_pmod[1] AW15 PMOD0_2 J52.5 LVCMOS18 3.3 V rf_data_pmod[2] AV15 PMOD0_3 J52.7 LVCMOS18 3.3 V rf_data_pmod[3] AV16 PMOD0_4 J52.2 LVCMOS18 3.3 V + +Ti375C529 PMOD0/J13, connector ve FPGA tarafi 3.3 V: + port FPGA pin PMOD pin FPGA resource FPGA I/O + rf_clk A12 J13.10 GPIOR_95_CLK12 3.3_V_LVCMOS + rf_data[0] G16 J13.2 GPIOR_89 3.3_V_LVCMOS + rf_data[1] F16 J13.3 GPIOR_90 3.3_V_LVCMOS + rf_data[2] F17 J13.4 GPIOR_91 3.3_V_LVCMOS + rf_data[3] G17 J13.7 GPIOR_92 3.3_V_LVCMOS ``` VCU118'de disaridan PMOD header'a 3.3 V seviye verilir. FPGA U1 package pinlerine dogrudan 3.3 V uygulanmaz; o tarafta XDC `LVCMOS18` kullanir. +Ti375C529'de AX2771 `rf_clk` hatti mutlaka J13 pin 10'a baglanmalidir. Bu pin +global-clock girisidir. J13 pin 1 / G15 (`GPIOR_88_PLLIN1`) PLL girisi olsa da +dedicated fabric GCLK degildir ve bu akis RF saati icin onu kullanmaz. + PMOD SPI portu her RF modunda aktiftir ve ayri MMIO register block olarak `0x10015000` adresindedir. Kart uzerindeki konfig flash SPI'si `0x10014000` adresinde kalir. Yazilim driver'i single/quad calisma modunu `ctrl.bit2` @@ -305,6 +325,15 @@ uzerinden 1.2 V bank/LVCMOS12: pmod_spi_sck P30 PMOD1_3 J53.7 SCK LVCMOS12 3.3 V pmod_spi_dq[2] P29 PMOD1_4 J53.2 LVCMOS12 3.3 V pmod_spi_dq[3] L31 PMOD1_5 J53.4 LVCMOS12 3.3 V + +Ti375C529 PMOD1/J14, connector ve FPGA tarafi 3.3 V: + port FPGA pin PMOD pin FPGA resource FPGA I/O + pmod_spi_csn B12 J14.1 GPIOR_96_CLK13 3.3_V_LVCMOS + pmod_spi_dq[0] C14 J14.2 MOSI GPIOR_97 3.3_V_LVCMOS + pmod_spi_dq[1] C13 J14.3 MISO GPIOR_98 3.3_V_LVCMOS + pmod_spi_sck C12 J14.4 SCK GPIOR_99 3.3_V_LVCMOS + pmod_spi_dq[2] D12 J14.7 GPIOR_100 3.3_V_LVCMOS + pmod_spi_dq[3] F12 J14.8 GPIOR_101_PLLIN1 3.3_V_LVCMOS ``` Sensorden gelen external interrupt hatti SPI'dan bagimsizdir. `pmod_irq` @@ -319,8 +348,16 @@ Genesys2: VCU118: port FPGA pin PMOD pin FPGA I/O PMOD header level pmod_irq M31 PMOD1_6 J53.6 LVCMOS12 3.3 V + +Ti375C529: + port FPGA pin PMOD pin FPGA resource FPGA I/O + pmod_irq D13 J14.9 GPIOR_102 3.3_V_LVCMOS + gps_pps E13 J14.10 GPIOR_103 3.3_V_LVCMOS ``` +Ti375C529'de `gps_pps` J14.10 uzerinden cikan 3.3 V PPS sinyalidir; +`pmod_irq` ise J14.9 uzerinden FPGA'ya girer. + Bu pinler mod bazli companion XDC dosyalarinda tutulur: `hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc`, `hardware/fpga/vcu118/constraints/vcu118_pmod_rf.xdc`, @@ -329,13 +366,45 @@ Bu pinler mod bazli companion XDC dosyalarinda tutulur: `hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc`, `hardware/fpga/vcu118/constraints/vcu118_pmod_irq.xdc`, `hardware/fpga/genesys2/constraints/genesys2_ethernet.xdc` ve -`hardware/fpga/vcu118/constraints/vcu118_ethernet.xdc`. +`hardware/fpga/vcu118/constraints/vcu118_ethernet.xdc`. Ti375C529 pinleri, +I/O standartlari, PLL'ler ve hard-JTAG baglantisi tek Efinity interface +scriptinde tutulur: +`hardware/fpga/ti375c529/constraints/ti375c529_rocket.isf`. + +### Ti375C529 kart uzeri baglantilar + +Ti375C529 development kit'te Rocket sistem saati kart uzerindeki 100 MHz +osilatorden, GPS isleme saatleri ise AX2771'in J13.10 uzerindeki +16.367981 MHz RF saatinden uretilir. SW3 active-low Rocket resetidir. FTDI +UART varsayilan olarak 460800 baud ve mevcut Linux enumeration'inda +`/dev/ttyUSB2` kullanir. Birden fazla kart veya farkli enumeration icin +`UART_PORT=...` ve `FTDI_URL=...` ile override edilebilir. + +Lower 512-Mbit konfig flash'i kart icinde su pinlere baglidir; PMOD'a kablo +cekilmez: + +```text +port FPGA pin FPGA resource +flash_csn A7 GPIOB_N_38 / SSL_N +flash_sck G6 GPIOB_P_39 / CCK +flash_dq[0] H4 GPIOB_N_40 / CDI0 +flash_dq[1] H5 GPIOB_P_40 / CDI1 +flash_dq[2] G5 GPIOB_N_39 / CDI2 +flash_dq[3] B7 GPIOB_P_38 / CDI3 +``` + +Efinity `JTAG_USER1`, mevcut Rocket DMI tunnel protokolunu kullanir. Host +OpenOCD build'inde `riscv set_bscan_tunnel_ir` destegi bulunmalidir; Efinity +ile gelen OpenOCD yerine uyumlu host OpenOCD kullanilir. Ayrintili Efinity, +clock, JTAG ve dogrulama notlari icin +`targets/fpga/ti375c529/README.md` dosyasina bakin. ## FPGA Flash ve MCS Akislari Bu hedefler kok Makefile'dan secilen karta yonlenir. Genesys2 icin -`BOARD=genesys2`, VCU118 icin `BOARD=vcu118` kullanilir. `APP` verilmezse -varsayilan uygulama `hello_uart` olur. +`BOARD=genesys2`, VCU118 icin `BOARD=vcu118`, Ti375C529 icin +`BOARD=ti375c529` kullanilir. `APP` verilmezse varsayilan uygulama +`hello_uart` olur. Sadece ELF'i derleyip bootloader'in okuyacagi flash-format app imajina cevirmek: @@ -432,6 +501,57 @@ flash size: 32 MiB interface: SPIx4 ``` +### Ti375C529 Efinity build ve flash + +Efinity varsayilan olarak `/tools/efinix/efinity` altinda aranir. Farkli bir +kurulum `EFINITY_HOME=/path/to/efinity` ile secilebilir. Build, SRAM'e gecici +programlama ve kart tespiti kokten su sekilde yapilir: + +```sh +make FPGA_BOARD=ti375c529 fpga-config +make FPGA_BOARD=ti375c529 fpga-bitstream +make -C targets/fpga/ti375c529 detect +make FPGA_BOARD=ti375c529 fpga-program +``` + +Ti375C529'de repository genelindeki `fpga-mcs` hedef adi korunur fakat cikti +Xilinx MCS/BIN degil, Efinity raw HEX'tir. Lower 512-Mbit flash yerlesimi: + +```text +configuration offset: 0x00000000 +app offset: 0x00800000 +flash size: 64 MiB +interface: active-x1 configuration / user-mode quad SPI +``` + +Konfig ve uygulama imajlarini uretmek ve programlamak icin: + +```sh +make FPGA_BOARD=ti375c529 APP=hello_uart fpga-mcs +make FPGA_BOARD=ti375c529 APP=hello_uart fpga-flash-app +make FPGA_BOARD=ti375c529 fpga-flash-bitstream +make FPGA_BOARD=ti375c529 APP=hello_uart fpga-flash-mcs +``` + +Ciktilar: + +```text +targets/fpga/ti375c529/out/bitstream/ti375c529_rocket.bit +targets/fpga/ti375c529/out/bitstream/ti375c529_rocket.hex +targets/fpga/ti375c529/out/flash/ti375c529_rocket.hex +targets/fpga/ti375c529/out/flash/ti375c529_rocket.json +``` + +Flash programlama Efinity'nin Ti375'e uygun JTAG-to-SPI bridge'ini gecici +olarak yukler. Gercek persistent boot testi icin programlamadan sonra karta +power-cycle uygulanmalidir. GDB ile DTIM'e yukleme ve UART dinleme: + +```sh +make FPGA_BOARD=ti375c529 fpga-debug-openocd +make FPGA_BOARD=ti375c529 APP=hello_uart fpga-debug-load +make FPGA_BOARD=ti375c529 fpga-uart +``` + ## GPS Reset Davranisi OpenOCD/GDB `monitor reset` yolu Rocket debug module `ndmreset` sinyalini