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Add STEVAL-MKI217V1 SPI logger and replay

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This commit is contained in:
onur
2026-07-13 22:16:51 +03:00
parent f16ac8aa80
commit df563aa207
12 changed files with 629 additions and 13 deletions
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soc/software/bsp/drivers/pmod_spi.c
+44 -1
View File
@@ -11,6 +11,11 @@
#define PMOD_SPI_CTRL_BUSY 0x1u
#define PMOD_SPI_CTRL_CSN 0x2u
#define PMOD_SPI_CTRL_QUAD 0x4u
#define PMOD_SPI_CTRL_CPOL 0x8u
#define PMOD_SPI_CTRL_CPHA 0x10u
#define PMOD_SPI_CTRL_WRITABLE \
(PMOD_SPI_CTRL_CSN | PMOD_SPI_CTRL_QUAD | \
PMOD_SPI_CTRL_CPOL | PMOD_SPI_CTRL_CPHA)
static uint32_t pmod_spi_ctrl_shadow = PMOD_SPI_CTRL_CSN;
static uint32_t pmod_spi_cs_setup_us;
@@ -42,7 +47,7 @@ static void pmod_spi_wait_ready(void)
static void pmod_spi_write_ctrl(uint32_t ctrl)
{
pmod_spi_wait_ready();
pmod_spi_ctrl_shadow = ctrl & (PMOD_SPI_CTRL_CSN | PMOD_SPI_CTRL_QUAD);
pmod_spi_ctrl_shadow = ctrl & PMOD_SPI_CTRL_WRITABLE;
bsp_write32(PMOD_SPI_CTRL, pmod_spi_ctrl_shadow);
}
@@ -72,6 +77,44 @@ void bsp_pmod_spi_set_quad(int enabled)
bsp_pmod_spi_set_mode(enabled ? BSP_PMOD_SPI_MODE_QUAD : BSP_PMOD_SPI_MODE_SINGLE);
}
void bsp_pmod_spi_set_clock_mode(bsp_pmod_spi_clock_mode_t mode)
{
uint32_t ctrl =
pmod_spi_ctrl_shadow & ~(PMOD_SPI_CTRL_CPOL | PMOD_SPI_CTRL_CPHA);
switch (mode) {
case BSP_PMOD_SPI_CLOCK_MODE1:
ctrl |= PMOD_SPI_CTRL_CPHA;
break;
case BSP_PMOD_SPI_CLOCK_MODE2:
ctrl |= PMOD_SPI_CTRL_CPOL;
break;
case BSP_PMOD_SPI_CLOCK_MODE3:
ctrl |= PMOD_SPI_CTRL_CPOL | PMOD_SPI_CTRL_CPHA;
break;
case BSP_PMOD_SPI_CLOCK_MODE0:
default:
break;
}
pmod_spi_write_ctrl(ctrl);
}
bsp_pmod_spi_clock_mode_t bsp_pmod_spi_clock_mode(void)
{
const uint32_t bits =
pmod_spi_ctrl_shadow & (PMOD_SPI_CTRL_CPOL | PMOD_SPI_CTRL_CPHA);
if (bits == (PMOD_SPI_CTRL_CPOL | PMOD_SPI_CTRL_CPHA)) {
return BSP_PMOD_SPI_CLOCK_MODE3;
}
if (bits == PMOD_SPI_CTRL_CPOL) {
return BSP_PMOD_SPI_CLOCK_MODE2;
}
if (bits == PMOD_SPI_CTRL_CPHA) {
return BSP_PMOD_SPI_CLOCK_MODE1;
}
return BSP_PMOD_SPI_CLOCK_MODE0;
}
void bsp_pmod_spi_set_timing(uint32_t cs_setup_us,
uint32_t inter_byte_us,
uint32_t cs_hold_us,
soc/software/bsp/include/bsp/pmod_spi.h
+14
View File
@@ -9,11 +9,25 @@ typedef enum {
BSP_PMOD_SPI_MODE_QUAD = 1
} bsp_pmod_spi_mode_t;
typedef enum {
BSP_PMOD_SPI_CLOCK_MODE0 = 0,
BSP_PMOD_SPI_CLOCK_MODE1 = 1,
BSP_PMOD_SPI_CLOCK_MODE2 = 2,
BSP_PMOD_SPI_CLOCK_MODE3 = 3
} bsp_pmod_spi_clock_mode_t;
void bsp_pmod_spi_init(void);
void bsp_pmod_spi_set_mode(bsp_pmod_spi_mode_t mode);
bsp_pmod_spi_mode_t bsp_pmod_spi_mode(void);
void bsp_pmod_spi_set_quad(int enabled);
/*
* Select the standard CPOL/CPHA SPI clock mode independently of data width.
* Mode 0 is hardware-validated; modes 1-3 require target/device validation.
*/
void bsp_pmod_spi_set_clock_mode(bsp_pmod_spi_clock_mode_t mode);
bsp_pmod_spi_clock_mode_t bsp_pmod_spi_clock_mode(void);
/*
* Configure delays used by the chip-select-managed transaction helpers.
* All values are in microseconds. Zero disables the corresponding delay.