/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* AttrDef Declarations                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_ATTRDEF_CLASSES
#undef GET_ATTRDEF_CLASSES


namespace mlir {
class AsmParser;
class AsmPrinter;
} // namespace mlir
namespace mlir::amdgpu {

/// AMDGPU-specific address spaces
/// AMDGPU-specific memory spaces that may not have exact analogues on other
/// GPU targets or backends.
/// 
/// - `fat_raw_buffer` is the memory space used when a memref is stored as
/// as a "buffer fat pointer" - that is, a buffer resource (that is set up to
/// use raw byte-level indexing) along with its offset. The AMDGPU backend
/// implements `ptr addrspace(7)` to represent these fat pointers so that
/// buffer resources (which allow advanced features like bounds checking or
/// cache swizzling) can be used like ordinary LLVM pointers or memrefs.
/// See also the `fat_raw_buffer_cast` operation
/// - `buffer_rsrc` is the memory space for `ptr addrspace(8)`, representing a
/// buffer resource. It should not be used for memrefs, since it does not support
/// indexing
/// - `fat_structured_buffer` represents `ptr addrspace(9)`, a buffer resource
/// that carries both an index and offset field, which are used for complex
/// structured indexing that is primarily seen in graphics applications. This
/// is also incompatible with the simple indexing model supported by memref.
class AddressSpaceAttr;
/// The possible permutations for a DPP operation
/// Enum cases:
/// * quad_perm (`quad_perm`)
/// * row_shl (`row_shl`)
/// * row_shr (`row_shr`)
/// * row_ror (`row_ror`)
/// * wave_shl (`wave_shl`)
/// * wave_shr (`wave_shr`)
/// * wave_ror (`wave_ror`)
/// * wave_rol (`wave_rol`)
/// * row_mirror (`row_mirror`)
/// * row_half_mirror (`row_half_mirror`)
/// * row_bcast_15 (`row_bcast_15`)
/// * row_bcast_31 (`row_bcast_31`)
class DPPPermAttr;
/// AMDGPU-specific prefetch temporal hints for load instructions. RT - regular temporal for both near and far caches; NT - non-temporal for both near and far caches; HT - high-priority temporal for both near and far caches; LU - last-use; NT_RT - non-temporal for near cache(s) and regular for far caches; RT_NT - regular for near cache(s) and non-temporal for far caches; NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches
/// Enum cases:
/// * RT (`RT`)
/// * NT (`NT`)
/// * HT (`HT`)
/// * LU (`LU`)
/// * NT_RT (`NT_RT`)
/// * RT_NT (`RT_NT`)
/// * NT_HT (`NT_HT`)
class LoadTemporalHintAttr;
/// AMDGPU-specific cache scopes. WGP - workgroup processor (CUs); SE - shader engine (GL2); DEV - device; SYS - system
/// Enum cases:
/// * WGP (`WGP`)
/// * SE (`SE`)
/// * DEV (`DEV`)
/// * SYS (`SYS`)
class ScopeAttr;
namespace detail {

struct AddressSpaceAttrStorage;

} // namespace detail
class AddressSpaceAttr : public ::mlir::Attribute::AttrBase<AddressSpaceAttr, ::mlir::Attribute, detail::AddressSpaceAttrStorage> {
public:
  using Base::Base;
  static constexpr ::llvm::StringLiteral name = "amdgpu.address_space";
  static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
  static AddressSpaceAttr get(::mlir::MLIRContext *context, ::mlir::amdgpu::AddressSpace value);
  static constexpr ::llvm::StringLiteral getMnemonic() {
    return {"address_space"};
  }

  static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
  void print(::mlir::AsmPrinter &odsPrinter) const;
  ::mlir::amdgpu::AddressSpace getValue() const;
};
namespace detail {

struct DPPPermAttrStorage;

} // namespace detail
class DPPPermAttr : public ::mlir::Attribute::AttrBase<DPPPermAttr, ::mlir::Attribute, detail::DPPPermAttrStorage> {
public:
  using Base::Base;
  static constexpr ::llvm::StringLiteral name = "amdgpu.dpp_perm";
  static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
  static DPPPermAttr get(::mlir::MLIRContext *context, ::mlir::amdgpu::DPPPerm value);
  static constexpr ::llvm::StringLiteral getMnemonic() {
    return {"dpp_perm"};
  }

  static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
  void print(::mlir::AsmPrinter &odsPrinter) const;
  ::mlir::amdgpu::DPPPerm getValue() const;
};
namespace detail {

struct LoadTemporalHintAttrStorage;

} // namespace detail
class LoadTemporalHintAttr : public ::mlir::Attribute::AttrBase<LoadTemporalHintAttr, ::mlir::Attribute, detail::LoadTemporalHintAttrStorage> {
public:
  using Base::Base;
  static constexpr ::llvm::StringLiteral name = "amdgpu.load_temporal_hint";
  static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
  static LoadTemporalHintAttr get(::mlir::MLIRContext *context, ::mlir::amdgpu::LoadTemporalHint value);
  static constexpr ::llvm::StringLiteral getMnemonic() {
    return {"load_temporal_hint"};
  }

  static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
  void print(::mlir::AsmPrinter &odsPrinter) const;
  ::mlir::amdgpu::LoadTemporalHint getValue() const;
};
namespace detail {

struct ScopeAttrStorage;

} // namespace detail
class ScopeAttr : public ::mlir::Attribute::AttrBase<ScopeAttr, ::mlir::Attribute, detail::ScopeAttrStorage> {
public:
  using Base::Base;
  static constexpr ::llvm::StringLiteral name = "amdgpu.cache_scope";
  static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
  static ScopeAttr get(::mlir::MLIRContext *context, ::mlir::amdgpu::Scope value);
  static constexpr ::llvm::StringLiteral getMnemonic() {
    return {"cache_scope"};
  }

  static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
  void print(::mlir::AsmPrinter &odsPrinter) const;
  ::mlir::amdgpu::Scope getValue() const;
};

} // namespace mlir::amdgpu
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::AddressSpaceAttr)
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::DPPPermAttr)
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::LoadTemporalHintAttr)
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::ScopeAttr)

#endif // GET_ATTRDEF_CLASSES