/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Enum Utility Declarations                                                  *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|* From: AMDGPUEnums.td                                                       *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

namespace mlir::amdgpu {

// AMDGPU-specific address spaces
enum class AddressSpace : uint32_t {
  FatRawBuffer = 0,
  BufferRsrc = 1,
  FatStructuredBuffer = 2,
};

::std::optional<AddressSpace> symbolizeAddressSpace(uint32_t);
::llvm::StringRef stringifyAddressSpace(AddressSpace);
::std::optional<AddressSpace> symbolizeAddressSpace(::llvm::StringRef);
inline constexpr unsigned getMaxEnumValForAddressSpace() {
  return 2;
}


inline ::llvm::StringRef stringifyEnum(AddressSpace enumValue) {
  return stringifyAddressSpace(enumValue);
}

template <typename EnumType>
::std::optional<EnumType> symbolizeEnum(::llvm::StringRef);

template <>
inline ::std::optional<AddressSpace> symbolizeEnum<AddressSpace>(::llvm::StringRef str) {
  return symbolizeAddressSpace(str);
}

} // namespace mlir::amdgpu

namespace mlir {
template <typename T, typename>
struct FieldParser;

template<>
struct FieldParser<::mlir::amdgpu::AddressSpace, ::mlir::amdgpu::AddressSpace> {
  template <typename ParserT>
  static FailureOr<::mlir::amdgpu::AddressSpace> parse(ParserT &parser) {
    // Parse the keyword/string containing the enum.
    std::string enumKeyword;
    auto loc = parser.getCurrentLocation();
    if (failed(parser.parseOptionalKeywordOrString(&enumKeyword)))
      return parser.emitError(loc, "expected keyword for AMDGPU-specific address spaces");

    // Symbolize the keyword.
    if (::std::optional<::mlir::amdgpu::AddressSpace> attr = ::mlir::amdgpu::symbolizeEnum<::mlir::amdgpu::AddressSpace>(enumKeyword))
      return *attr;
    return parser.emitError(loc, "expected one of [fat_raw_buffer, buffer_rsrc, fat_structured_buffer] for AMDGPU-specific address spaces, got: ") << enumKeyword;
  }
};

/// Support for std::optional, useful in attribute/type definition where the enum is
/// used as:
///
///    let parameters = (ins OptionalParameter<"std::optional<TheEnumName>">:$value);
template<>
struct FieldParser<std::optional<::mlir::amdgpu::AddressSpace>, std::optional<::mlir::amdgpu::AddressSpace>> {
  template <typename ParserT>
  static FailureOr<std::optional<::mlir::amdgpu::AddressSpace>> parse(ParserT &parser) {
    // Parse the keyword/string containing the enum.
    std::string enumKeyword;
    auto loc = parser.getCurrentLocation();
    if (failed(parser.parseOptionalKeywordOrString(&enumKeyword, {"fat_raw_buffer", "buffer_rsrc", "fat_structured_buffer"})))
      return std::optional<::mlir::amdgpu::AddressSpace>{};

    // Symbolize the keyword.
    if (::std::optional<::mlir::amdgpu::AddressSpace> attr = ::mlir::amdgpu::symbolizeEnum<::mlir::amdgpu::AddressSpace>(enumKeyword))
      return attr;
    return parser.emitError(loc, "expected one of [fat_raw_buffer, buffer_rsrc, fat_structured_buffer] for AMDGPU-specific address spaces, got: ") << enumKeyword;
  }
};
} // namespace mlir

namespace llvm {
inline ::llvm::raw_ostream &operator<<(::llvm::raw_ostream &p, ::mlir::amdgpu::AddressSpace value) {
  auto valueStr = stringifyEnum(value);
  return p << valueStr;
}
} // namespace llvm

namespace llvm {
template<> struct DenseMapInfo<::mlir::amdgpu::AddressSpace> {
  using StorageInfo = ::llvm::DenseMapInfo<uint32_t>;

  static unsigned getHashValue(const ::mlir::amdgpu::AddressSpace &val) {
    return StorageInfo::getHashValue(static_cast<uint32_t>(val));
  }

  static bool isEqual(const ::mlir::amdgpu::AddressSpace &lhs, const ::mlir::amdgpu::AddressSpace &rhs) {
    return lhs == rhs;
  }
};
}

namespace mlir::amdgpu {

// AMDGPU-specific cache scopes. WGP - workgroup processor (CUs); SE - shader engine (GL2); DEV - device; SYS - system
enum class Scope : uint32_t {
  WGP = 0,
  SE = 1,
  DEV = 2,
  SYS = 3,
};

::std::optional<Scope> symbolizeScope(uint32_t);
::llvm::StringRef stringifyScope(Scope);
::std::optional<Scope> symbolizeScope(::llvm::StringRef);
inline constexpr unsigned getMaxEnumValForScope() {
  return 3;
}


inline ::llvm::StringRef stringifyEnum(Scope enumValue) {
  return stringifyScope(enumValue);
}

template <typename EnumType>
::std::optional<EnumType> symbolizeEnum(::llvm::StringRef);

template <>
inline ::std::optional<Scope> symbolizeEnum<Scope>(::llvm::StringRef str) {
  return symbolizeScope(str);
}

} // namespace mlir::amdgpu

namespace mlir {
template <typename T, typename>
struct FieldParser;

template<>
struct FieldParser<::mlir::amdgpu::Scope, ::mlir::amdgpu::Scope> {
  template <typename ParserT>
  static FailureOr<::mlir::amdgpu::Scope> parse(ParserT &parser) {
    // Parse the keyword/string containing the enum.
    std::string enumKeyword;
    auto loc = parser.getCurrentLocation();
    if (failed(parser.parseOptionalKeywordOrString(&enumKeyword)))
      return parser.emitError(loc, "expected keyword for AMDGPU-specific cache scopes. WGP - workgroup processor (CUs); SE - shader engine (GL2); DEV - device; SYS - system");

    // Symbolize the keyword.
    if (::std::optional<::mlir::amdgpu::Scope> attr = ::mlir::amdgpu::symbolizeEnum<::mlir::amdgpu::Scope>(enumKeyword))
      return *attr;
    return parser.emitError(loc, "expected one of [WGP, SE, DEV, SYS] for AMDGPU-specific cache scopes. WGP - workgroup processor (CUs); SE - shader engine (GL2); DEV - device; SYS - system, got: ") << enumKeyword;
  }
};

/// Support for std::optional, useful in attribute/type definition where the enum is
/// used as:
///
///    let parameters = (ins OptionalParameter<"std::optional<TheEnumName>">:$value);
template<>
struct FieldParser<std::optional<::mlir::amdgpu::Scope>, std::optional<::mlir::amdgpu::Scope>> {
  template <typename ParserT>
  static FailureOr<std::optional<::mlir::amdgpu::Scope>> parse(ParserT &parser) {
    // Parse the keyword/string containing the enum.
    std::string enumKeyword;
    auto loc = parser.getCurrentLocation();
    if (failed(parser.parseOptionalKeywordOrString(&enumKeyword, {"WGP", "SE", "DEV", "SYS"})))
      return std::optional<::mlir::amdgpu::Scope>{};

    // Symbolize the keyword.
    if (::std::optional<::mlir::amdgpu::Scope> attr = ::mlir::amdgpu::symbolizeEnum<::mlir::amdgpu::Scope>(enumKeyword))
      return attr;
    return parser.emitError(loc, "expected one of [WGP, SE, DEV, SYS] for AMDGPU-specific cache scopes. WGP - workgroup processor (CUs); SE - shader engine (GL2); DEV - device; SYS - system, got: ") << enumKeyword;
  }
};
} // namespace mlir

namespace llvm {
inline ::llvm::raw_ostream &operator<<(::llvm::raw_ostream &p, ::mlir::amdgpu::Scope value) {
  auto valueStr = stringifyEnum(value);
  return p << valueStr;
}
} // namespace llvm

namespace llvm {
template<> struct DenseMapInfo<::mlir::amdgpu::Scope> {
  using StorageInfo = ::llvm::DenseMapInfo<uint32_t>;

  static unsigned getHashValue(const ::mlir::amdgpu::Scope &val) {
    return StorageInfo::getHashValue(static_cast<uint32_t>(val));
  }

  static bool isEqual(const ::mlir::amdgpu::Scope &lhs, const ::mlir::amdgpu::Scope &rhs) {
    return lhs == rhs;
  }
};
}

namespace mlir::amdgpu {

// The possible permutations for a DPP operation
enum class DPPPerm : uint32_t {
  quad_perm = 0,
  row_shl = 1,
  row_shr = 2,
  row_ror = 3,
  wave_shl = 4,
  wave_shr = 5,
  wave_ror = 6,
  wave_rol = 7,
  row_mirror = 8,
  row_half_mirror = 9,
  row_bcast_15 = 10,
  row_bcast_31 = 11,
};

::std::optional<DPPPerm> symbolizeDPPPerm(uint32_t);
::llvm::StringRef stringifyDPPPerm(DPPPerm);
::std::optional<DPPPerm> symbolizeDPPPerm(::llvm::StringRef);
inline constexpr unsigned getMaxEnumValForDPPPerm() {
  return 11;
}


inline ::llvm::StringRef stringifyEnum(DPPPerm enumValue) {
  return stringifyDPPPerm(enumValue);
}

template <typename EnumType>
::std::optional<EnumType> symbolizeEnum(::llvm::StringRef);

template <>
inline ::std::optional<DPPPerm> symbolizeEnum<DPPPerm>(::llvm::StringRef str) {
  return symbolizeDPPPerm(str);
}

} // namespace mlir::amdgpu

namespace mlir {
template <typename T, typename>
struct FieldParser;

template<>
struct FieldParser<::mlir::amdgpu::DPPPerm, ::mlir::amdgpu::DPPPerm> {
  template <typename ParserT>
  static FailureOr<::mlir::amdgpu::DPPPerm> parse(ParserT &parser) {
    // Parse the keyword/string containing the enum.
    std::string enumKeyword;
    auto loc = parser.getCurrentLocation();
    if (failed(parser.parseOptionalKeywordOrString(&enumKeyword)))
      return parser.emitError(loc, "expected keyword for The possible permutations for a DPP operation");

    // Symbolize the keyword.
    if (::std::optional<::mlir::amdgpu::DPPPerm> attr = ::mlir::amdgpu::symbolizeEnum<::mlir::amdgpu::DPPPerm>(enumKeyword))
      return *attr;
    return parser.emitError(loc, "expected one of [quad_perm, row_shl, row_shr, row_ror, wave_shl, wave_shr, wave_ror, wave_rol, row_mirror, row_half_mirror, row_bcast_15, row_bcast_31] for The possible permutations for a DPP operation, got: ") << enumKeyword;
  }
};

/// Support for std::optional, useful in attribute/type definition where the enum is
/// used as:
///
///    let parameters = (ins OptionalParameter<"std::optional<TheEnumName>">:$value);
template<>
struct FieldParser<std::optional<::mlir::amdgpu::DPPPerm>, std::optional<::mlir::amdgpu::DPPPerm>> {
  template <typename ParserT>
  static FailureOr<std::optional<::mlir::amdgpu::DPPPerm>> parse(ParserT &parser) {
    // Parse the keyword/string containing the enum.
    std::string enumKeyword;
    auto loc = parser.getCurrentLocation();
    if (failed(parser.parseOptionalKeywordOrString(&enumKeyword, {"quad_perm", "row_shl", "row_shr", "row_ror", "wave_shl", "wave_shr", "wave_ror", "wave_rol", "row_mirror", "row_half_mirror", "row_bcast_15", "row_bcast_31"})))
      return std::optional<::mlir::amdgpu::DPPPerm>{};

    // Symbolize the keyword.
    if (::std::optional<::mlir::amdgpu::DPPPerm> attr = ::mlir::amdgpu::symbolizeEnum<::mlir::amdgpu::DPPPerm>(enumKeyword))
      return attr;
    return parser.emitError(loc, "expected one of [quad_perm, row_shl, row_shr, row_ror, wave_shl, wave_shr, wave_ror, wave_rol, row_mirror, row_half_mirror, row_bcast_15, row_bcast_31] for The possible permutations for a DPP operation, got: ") << enumKeyword;
  }
};
} // namespace mlir

namespace llvm {
inline ::llvm::raw_ostream &operator<<(::llvm::raw_ostream &p, ::mlir::amdgpu::DPPPerm value) {
  auto valueStr = stringifyEnum(value);
  return p << valueStr;
}
} // namespace llvm

namespace llvm {
template<> struct DenseMapInfo<::mlir::amdgpu::DPPPerm> {
  using StorageInfo = ::llvm::DenseMapInfo<uint32_t>;

  static unsigned getHashValue(const ::mlir::amdgpu::DPPPerm &val) {
    return StorageInfo::getHashValue(static_cast<uint32_t>(val));
  }

  static bool isEqual(const ::mlir::amdgpu::DPPPerm &lhs, const ::mlir::amdgpu::DPPPerm &rhs) {
    return lhs == rhs;
  }
};
}

namespace mlir::amdgpu {

// AMDGPU-specific prefetch temporal hints for load instructions. RT - regular temporal for both near and far caches; NT - non-temporal for both near and far caches; HT - high-priority temporal for both near and far caches; LU - last-use; NT_RT - non-temporal for near cache(s) and regular for far caches; RT_NT - regular for near cache(s) and non-temporal for far caches; NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches
enum class LoadTemporalHint : uint32_t {
  RT = 0,
  NT = 1,
  HT = 2,
  LU = 3,
  NT_RT = 4,
  RT_NT = 5,
  NT_HT = 6,
};

::std::optional<LoadTemporalHint> symbolizeLoadTemporalHint(uint32_t);
::llvm::StringRef stringifyLoadTemporalHint(LoadTemporalHint);
::std::optional<LoadTemporalHint> symbolizeLoadTemporalHint(::llvm::StringRef);
inline constexpr unsigned getMaxEnumValForLoadTemporalHint() {
  return 6;
}


inline ::llvm::StringRef stringifyEnum(LoadTemporalHint enumValue) {
  return stringifyLoadTemporalHint(enumValue);
}

template <typename EnumType>
::std::optional<EnumType> symbolizeEnum(::llvm::StringRef);

template <>
inline ::std::optional<LoadTemporalHint> symbolizeEnum<LoadTemporalHint>(::llvm::StringRef str) {
  return symbolizeLoadTemporalHint(str);
}

} // namespace mlir::amdgpu

namespace mlir {
template <typename T, typename>
struct FieldParser;

template<>
struct FieldParser<::mlir::amdgpu::LoadTemporalHint, ::mlir::amdgpu::LoadTemporalHint> {
  template <typename ParserT>
  static FailureOr<::mlir::amdgpu::LoadTemporalHint> parse(ParserT &parser) {
    // Parse the keyword/string containing the enum.
    std::string enumKeyword;
    auto loc = parser.getCurrentLocation();
    if (failed(parser.parseOptionalKeywordOrString(&enumKeyword)))
      return parser.emitError(loc, "expected keyword for AMDGPU-specific prefetch temporal hints for load instructions. RT - regular temporal for both near and far caches; NT - non-temporal for both near and far caches; HT - high-priority temporal for both near and far caches; LU - last-use; NT_RT - non-temporal for near cache(s) and regular for far caches; RT_NT - regular for near cache(s) and non-temporal for far caches; NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches");

    // Symbolize the keyword.
    if (::std::optional<::mlir::amdgpu::LoadTemporalHint> attr = ::mlir::amdgpu::symbolizeEnum<::mlir::amdgpu::LoadTemporalHint>(enumKeyword))
      return *attr;
    return parser.emitError(loc, "expected one of [RT, NT, HT, LU, NT_RT, RT_NT, NT_HT] for AMDGPU-specific prefetch temporal hints for load instructions. RT - regular temporal for both near and far caches; NT - non-temporal for both near and far caches; HT - high-priority temporal for both near and far caches; LU - last-use; NT_RT - non-temporal for near cache(s) and regular for far caches; RT_NT - regular for near cache(s) and non-temporal for far caches; NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches, got: ") << enumKeyword;
  }
};

/// Support for std::optional, useful in attribute/type definition where the enum is
/// used as:
///
///    let parameters = (ins OptionalParameter<"std::optional<TheEnumName>">:$value);
template<>
struct FieldParser<std::optional<::mlir::amdgpu::LoadTemporalHint>, std::optional<::mlir::amdgpu::LoadTemporalHint>> {
  template <typename ParserT>
  static FailureOr<std::optional<::mlir::amdgpu::LoadTemporalHint>> parse(ParserT &parser) {
    // Parse the keyword/string containing the enum.
    std::string enumKeyword;
    auto loc = parser.getCurrentLocation();
    if (failed(parser.parseOptionalKeywordOrString(&enumKeyword, {"RT", "NT", "HT", "LU", "NT_RT", "RT_NT", "NT_HT"})))
      return std::optional<::mlir::amdgpu::LoadTemporalHint>{};

    // Symbolize the keyword.
    if (::std::optional<::mlir::amdgpu::LoadTemporalHint> attr = ::mlir::amdgpu::symbolizeEnum<::mlir::amdgpu::LoadTemporalHint>(enumKeyword))
      return attr;
    return parser.emitError(loc, "expected one of [RT, NT, HT, LU, NT_RT, RT_NT, NT_HT] for AMDGPU-specific prefetch temporal hints for load instructions. RT - regular temporal for both near and far caches; NT - non-temporal for both near and far caches; HT - high-priority temporal for both near and far caches; LU - last-use; NT_RT - non-temporal for near cache(s) and regular for far caches; RT_NT - regular for near cache(s) and non-temporal for far caches; NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches, got: ") << enumKeyword;
  }
};
} // namespace mlir

namespace llvm {
inline ::llvm::raw_ostream &operator<<(::llvm::raw_ostream &p, ::mlir::amdgpu::LoadTemporalHint value) {
  auto valueStr = stringifyEnum(value);
  return p << valueStr;
}
} // namespace llvm

namespace llvm {
template<> struct DenseMapInfo<::mlir::amdgpu::LoadTemporalHint> {
  using StorageInfo = ::llvm::DenseMapInfo<uint32_t>;

  static unsigned getHashValue(const ::mlir::amdgpu::LoadTemporalHint &val) {
    return StorageInfo::getHashValue(static_cast<uint32_t>(val));
  }

  static bool isEqual(const ::mlir::amdgpu::LoadTemporalHint &lhs, const ::mlir::amdgpu::LoadTemporalHint &rhs) {
    return lhs == rhs;
  }
};
}