# Rocket ASIC Flow

This flow builds the same Rocket SoC for an ASIC-style shell: no FPGA clock,
startup, BSCAN, or flash access primitives are instantiated. The top level uses
plain clock/reset, UART, SPI, and JTAG pins.

## Commands

The ASIC flow is driven directly by this directory's `Makefile`; there is no
separate flow dispatcher script.

```sh
make -C targets/asic/rocket rtl
make -C targets/asic/rocket sim-rtl
make -C targets/asic/rocket vlog-soc
make -C targets/asic/rocket vlog-tb
make -C targets/asic/rocket sim
make -C targets/asic/rocket sim GUI=1
```

The default simulation app is `hello_uart`.

`make -C targets/asic/rocket sim GUI=1` opens the Questa/ModelSim graphical simulator,
loads `asic_rocket_tb` with `-voptargs="+acc"`, sources
`hardware/sim/asic/rocket/wave.do`, sets `onfinish stop`, and runs only `0 ns`
so the GUI is ready for manual waveform/debug work.

Generated outputs:

- `soc/out/software/`: common bootloader and application ELF/img outputs.
- `soc/out/flash/hello_uart.flash.hex`: SPI flash model contents loaded at `0x06000000`.
- `hardware/generated/asic-rocket-soc/`: FIRRTL, DTS, memory map.
- `hardware/generated/asic-rocket-soc-verilog/`: synthesis-style split SystemVerilog.
- `hardware/generated/asic-rocket-soc-sim-verilog/`: simulation split SystemVerilog with init blocks.
- `targets/asic/rocket/out/generated/asic_rocket_top.sv`: generic ASIC top.
- `targets/asic/rocket/out/generated/asic_rocket_top_sim.sv`: generic ASIC top for simulation RTL.
- `targets/asic/rocket/out/filelists/asic_rtl.f`: RTL compile filelist.
- `targets/asic/rocket/out/filelists/asic_tb.f`: RTL + SimJTAG + models + testbench filelist.
- `hardware/sim/asic/rocket/tb/`: ASIC testbench and behavioral models.

The ASIC config is `freechips.rocketchip.fpga.VCU118RocketJtagConfig`; it uses
JTAG debug export so the testbench can instantiate `SimJTAG`.

`rtl` keeps FIRRTL/CIRCT randomization disabled for synthesis-style output.
`sim-rtl`, `vlog-tb`, and `sim` use deterministic simulation init defines so
Rocket registers that are intentionally not reset come up as concrete 0/1 values
instead of propagating RTL `X` values. The UART console model prints decoded UART
characters to the simulator transcript.

The flash image path can be overridden at simulation runtime with:

```sh
+flash_hex=/path/to/image.hex
```