// Generated by CIRCT firtool-1.151.0
module CLINT(
  input         clock,
                reset,
  output        auto_int_out_0,
                auto_int_out_1,
                auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [1:0]  auto_in_a_bits_size,
  input  [5:0]  auto_in_a_bits_source,
  input  [25:0] auto_in_a_bits_address,
  input  [7:0]  auto_in_a_bits_mask,
  input  [63:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_size,
  output [5:0]  auto_in_d_bits_source,
  output [63:0] auto_in_d_bits_data,
  input         io_rtcTick
);

  wire             out_woready_9;
  wire             out_woready_17;
  reg  [63:0]      time_0;
  reg  [63:0]      timecmp_0;
  reg              ipi_0;
  wire             _out_out_bits_data_WIRE_1 = auto_in_a_bits_address[13:3] == 11'h0;
  wire             _out_out_bits_data_WIRE_2 = &(auto_in_a_bits_address[13:3]);
  wire             valids_1_0 = out_woready_9 & auto_in_a_bits_mask[0];
  wire             valids_1_1 = out_woready_9 & auto_in_a_bits_mask[1];
  wire             valids_1_2 = out_woready_9 & auto_in_a_bits_mask[2];
  wire             valids_1_3 = out_woready_9 & auto_in_a_bits_mask[3];
  wire             valids_1_4 = out_woready_9 & auto_in_a_bits_mask[4];
  wire             valids_1_5 = out_woready_9 & auto_in_a_bits_mask[5];
  wire             valids_1_6 = out_woready_9 & auto_in_a_bits_mask[6];
  wire             valids_1_7 = out_woready_9 & auto_in_a_bits_mask[7];
  wire             valids_0 = out_woready_17 & auto_in_a_bits_mask[0];
  wire             valids_1 = out_woready_17 & auto_in_a_bits_mask[1];
  wire             valids_2 = out_woready_17 & auto_in_a_bits_mask[2];
  wire             valids_3 = out_woready_17 & auto_in_a_bits_mask[3];
  wire             valids_4 = out_woready_17 & auto_in_a_bits_mask[4];
  wire             valids_5 = out_woready_17 & auto_in_a_bits_mask[5];
  wire             valids_6 = out_woready_17 & auto_in_a_bits_mask[6];
  wire             valids_7 = out_woready_17 & auto_in_a_bits_mask[7];
  wire [3:0]       _out_backSel_T = 4'h1 << auto_in_a_bits_address[15:14];
  wire             _out_wofireMux_T_2 =
    auto_in_a_valid & auto_in_d_ready & auto_in_a_bits_opcode != 3'h4;
  assign out_woready_17 =
    _out_wofireMux_T_2 & _out_backSel_T[1] & _out_out_bits_data_WIRE_1;
  assign out_woready_9 =
    _out_wofireMux_T_2 & _out_backSel_T[2] & _out_out_bits_data_WIRE_2;
  wire [3:0]       _GEN =
    {{1'h1},
     {_out_out_bits_data_WIRE_2},
     {_out_out_bits_data_WIRE_1},
     {_out_out_bits_data_WIRE_1}};
  wire [3:0][63:0] _GEN_0 = {{64'h0}, {time_0}, {timecmp_0}, {{63'h0, ipi_0}}};
  always @(posedge clock) begin
    if (reset) begin
      time_0 <= 64'h0;
      ipi_0 <= 1'h0;
    end
    else begin
      if (valids_1_0 | valids_1_1 | valids_1_2 | valids_1_3 | valids_1_4 | valids_1_5
          | valids_1_6 | valids_1_7)
        time_0 <=
          {valids_1_7 ? auto_in_a_bits_data[63:56] : time_0[63:56],
           valids_1_6 ? auto_in_a_bits_data[55:48] : time_0[55:48],
           valids_1_5 ? auto_in_a_bits_data[47:40] : time_0[47:40],
           valids_1_4 ? auto_in_a_bits_data[39:32] : time_0[39:32],
           valids_1_3 ? auto_in_a_bits_data[31:24] : time_0[31:24],
           valids_1_2 ? auto_in_a_bits_data[23:16] : time_0[23:16],
           valids_1_1 ? auto_in_a_bits_data[15:8] : time_0[15:8],
           valids_1_0 ? auto_in_a_bits_data[7:0] : time_0[7:0]};
      else if (io_rtcTick)
        time_0 <= time_0 + 64'h1;
      if (_out_wofireMux_T_2 & _out_backSel_T[0] & _out_out_bits_data_WIRE_1
          & auto_in_a_bits_mask[0])
        ipi_0 <= auto_in_a_bits_data[0];
    end
    if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6
        | valids_7)
      timecmp_0 <=
        {valids_7 ? auto_in_a_bits_data[63:56] : timecmp_0[63:56],
         valids_6 ? auto_in_a_bits_data[55:48] : timecmp_0[55:48],
         valids_5 ? auto_in_a_bits_data[47:40] : timecmp_0[47:40],
         valids_4 ? auto_in_a_bits_data[39:32] : timecmp_0[39:32],
         valids_3 ? auto_in_a_bits_data[31:24] : timecmp_0[31:24],
         valids_2 ? auto_in_a_bits_data[23:16] : timecmp_0[23:16],
         valids_1 ? auto_in_a_bits_data[15:8] : timecmp_0[15:8],
         valids_0 ? auto_in_a_bits_data[7:0] : timecmp_0[7:0]};
  end // always @(posedge)
  assign auto_int_out_0 = ipi_0;
  assign auto_int_out_1 = time_0 >= timecmp_0;
  assign auto_in_a_ready = auto_in_d_ready;
  assign auto_in_d_valid = auto_in_a_valid;
  assign auto_in_d_bits_opcode = {2'h0, auto_in_a_bits_opcode == 3'h4};
  assign auto_in_d_bits_size = auto_in_a_bits_size;
  assign auto_in_d_bits_source = auto_in_a_bits_source;
  assign auto_in_d_bits_data =
    _GEN[auto_in_a_bits_address[15:14]] ? _GEN_0[auto_in_a_bits_address[15:14]] : 64'h0;
endmodule