# Project Layout

This tree keeps upstream Rocket Chip code, project hardware, software, target
flows, and local tools in separate functional areas.

```text
dependencies/                Chisel, diplomacy, cde, hardfloat build dependencies
hardware/                    All project hardware sources, dumps, sim assets
  upstream/rocket-chip/src/   Required upstream Rocket-Chip Scala/resources
  upstream/rocket-chip/bootrom/
                               Required upstream default BootROM image/source
  soc/scala/                  Project Rocket SoC Chisel/Scala layer
  generated/                  FIRRTL and split SystemVerilog dump area
  fpga/vcu118/rtl/            Hand-written VCU118 shell/helper RTL
  fpga/vcu118/constraints/    VCU118 XDC constraints
  fpga/genesys2/rtl/          Hand-written Genesys2 shell/helper RTL
  fpga/genesys2/constraints/  Genesys2 XDC constraints
  sim/fpga/vcu118/            FPGA-oriented smoke/sim entry points
  sim/asic/rocket/            ASIC testbench, models, and wave setup
  external/gps/rtl/           GPS RTL sources and file list used by FPGA/ASIC
soc/software/                 Bootloader, BSP, bare-metal apps, flash image tools
  gps_system/                 GPS bare-metal acquisition/tracking/navigation app
targets/fpga/vcu118/          VCU118 build/programming flow entry point
targets/fpga/genesys2/        Genesys2 build/programming flow entry point
  flow/debug/                 OpenOCD BSCAN and GDB load scripts
targets/asic/rocket/          ASIC wrapper/filelist/simulation flow entry point
tools/local/                  Local mill, JDK, firtool/CIRCT, and Z3 installs
```

Generated/cache directories are disposable:

```text
out/
soc/out/
hardware/generated/
targets/**/out/
targets/**/work/
.Xil/
cong/
tools/local/*-download/
```