// Generated by CIRCT firtool-1.151.0 // Users can define 'PRINTF_COND' to add an extra gate to prints. `ifndef PRINTF_COND_ `ifdef PRINTF_COND `define PRINTF_COND_ (`PRINTF_COND) `else // PRINTF_COND `define PRINTF_COND_ 1 `endif // PRINTF_COND `endif // not def PRINTF_COND_ module CSRFile( input clock, reset, io_ungated_clock, io_interrupts_debug, io_interrupts_mtip, io_interrupts_msip, io_interrupts_meip, input [11:0] io_rw_addr, input [2:0] io_rw_cmd, output [63:0] io_rw_rdata, input [63:0] io_rw_wdata, input [31:0] io_decode_0_inst, output io_decode_0_fp_illegal, io_decode_0_fp_csr, io_decode_0_read_illegal, io_decode_0_write_illegal, io_decode_0_write_flush, io_decode_0_system_illegal, io_decode_0_virtual_access_illegal, io_csr_stall, io_eret, io_singleStep, io_status_debug, io_status_wfi, output [31:0] io_status_isa, output io_status_dv, io_status_v, output [33:0] io_evec, input io_exception, io_retire, input [63:0] io_cause, input [33:0] io_pc, io_tval, input io_gva, output [63:0] io_time, output [2:0] io_fcsr_rm, input io_fcsr_flags_valid, input [4:0] io_fcsr_flags_bits, output io_interrupt, output [63:0] io_interrupt_cause, output io_bp_0_control_action, output [1:0] io_bp_0_control_tmatch, output io_bp_0_control_x, io_bp_0_control_w, io_bp_0_control_r, output [32:0] io_bp_0_address, output io_pmp_0_cfg_l, output [1:0] io_pmp_0_cfg_a, output io_pmp_0_cfg_x, io_pmp_0_cfg_w, io_pmp_0_cfg_r, output [29:0] io_pmp_0_addr, output [31:0] io_pmp_0_mask, output io_pmp_1_cfg_l, output [1:0] io_pmp_1_cfg_a, output io_pmp_1_cfg_x, io_pmp_1_cfg_w, io_pmp_1_cfg_r, output [29:0] io_pmp_1_addr, output [31:0] io_pmp_1_mask, output io_pmp_2_cfg_l, output [1:0] io_pmp_2_cfg_a, output io_pmp_2_cfg_x, io_pmp_2_cfg_w, io_pmp_2_cfg_r, output [29:0] io_pmp_2_addr, output [31:0] io_pmp_2_mask, output io_pmp_3_cfg_l, output [1:0] io_pmp_3_cfg_a, output io_pmp_3_cfg_x, io_pmp_3_cfg_w, io_pmp_3_cfg_r, output [29:0] io_pmp_3_addr, output [31:0] io_pmp_3_mask, output io_pmp_4_cfg_l, output [1:0] io_pmp_4_cfg_a, output io_pmp_4_cfg_x, io_pmp_4_cfg_w, io_pmp_4_cfg_r, output [29:0] io_pmp_4_addr, output [31:0] io_pmp_4_mask, output io_pmp_5_cfg_l, output [1:0] io_pmp_5_cfg_a, output io_pmp_5_cfg_x, io_pmp_5_cfg_w, io_pmp_5_cfg_r, output [29:0] io_pmp_5_addr, output [31:0] io_pmp_5_mask, output io_pmp_6_cfg_l, output [1:0] io_pmp_6_cfg_a, output io_pmp_6_cfg_x, io_pmp_6_cfg_w, io_pmp_6_cfg_r, output [29:0] io_pmp_6_addr, output [31:0] io_pmp_6_mask, output io_pmp_7_cfg_l, output [1:0] io_pmp_7_cfg_a, output io_pmp_7_cfg_x, io_pmp_7_cfg_w, io_pmp_7_cfg_r, output [29:0] io_pmp_7_addr, output [31:0] io_pmp_7_mask, output io_inhibit_cycle, input [31:0] io_inst_0, output io_trace_0_valid, output [33:0] io_trace_0_iaddr, output [31:0] io_trace_0_insn, output io_trace_0_exception, output [63:0] io_customCSRs_0_value ); wire [63:0] io_rw_rdata_0; reg io_status_cease_r; wire io_status_sd; wire io_singleStep_0; reg reg_mstatus_v; reg reg_mstatus_mpv; reg reg_mstatus_gva; reg [1:0] reg_mstatus_fs; reg reg_mstatus_mpie; reg reg_mstatus_mie; reg reg_dcsr_ebreakm; reg [2:0] reg_dcsr_cause; reg reg_dcsr_v; reg reg_dcsr_step; reg reg_debug; reg [33:0] reg_dpc; reg [63:0] reg_dscratch0; reg reg_singleStepped; reg reg_bp_0_control_dmode; reg reg_bp_0_control_action; reg [1:0] reg_bp_0_control_tmatch; reg reg_bp_0_control_x; reg reg_bp_0_control_w; reg reg_bp_0_control_r; reg [32:0] reg_bp_0_address; reg reg_pmp_0_cfg_l; reg [1:0] reg_pmp_0_cfg_a; reg reg_pmp_0_cfg_x; reg reg_pmp_0_cfg_w; reg reg_pmp_0_cfg_r; reg [29:0] reg_pmp_0_addr; reg reg_pmp_1_cfg_l; reg [1:0] reg_pmp_1_cfg_a; reg reg_pmp_1_cfg_x; reg reg_pmp_1_cfg_w; reg reg_pmp_1_cfg_r; reg [29:0] reg_pmp_1_addr; reg reg_pmp_2_cfg_l; reg [1:0] reg_pmp_2_cfg_a; reg reg_pmp_2_cfg_x; reg reg_pmp_2_cfg_w; reg reg_pmp_2_cfg_r; reg [29:0] reg_pmp_2_addr; reg reg_pmp_3_cfg_l; reg [1:0] reg_pmp_3_cfg_a; reg reg_pmp_3_cfg_x; reg reg_pmp_3_cfg_w; reg reg_pmp_3_cfg_r; reg [29:0] reg_pmp_3_addr; reg reg_pmp_4_cfg_l; reg [1:0] reg_pmp_4_cfg_a; reg reg_pmp_4_cfg_x; reg reg_pmp_4_cfg_w; reg reg_pmp_4_cfg_r; reg [29:0] reg_pmp_4_addr; reg reg_pmp_5_cfg_l; reg [1:0] reg_pmp_5_cfg_a; reg reg_pmp_5_cfg_x; reg reg_pmp_5_cfg_w; reg reg_pmp_5_cfg_r; reg [29:0] reg_pmp_5_addr; reg reg_pmp_6_cfg_l; reg [1:0] reg_pmp_6_cfg_a; reg reg_pmp_6_cfg_x; reg reg_pmp_6_cfg_w; reg reg_pmp_6_cfg_r; reg [29:0] reg_pmp_6_addr; reg reg_pmp_7_cfg_l; reg [1:0] reg_pmp_7_cfg_a; reg reg_pmp_7_cfg_x; reg reg_pmp_7_cfg_w; reg reg_pmp_7_cfg_r; reg [29:0] reg_pmp_7_addr; reg [63:0] reg_mie; reg [33:0] reg_mepc; reg [63:0] reg_mcause; reg [33:0] reg_mtval; reg [63:0] reg_mscratch; reg [31:0] reg_mtvec; reg reg_wfi; reg [4:0] reg_fflags; reg [2:0] reg_frm; reg [2:0] reg_mcountinhibit; reg [5:0] small_0; reg [57:0] large_0; wire [63:0] value = {large_0, small_0}; reg [5:0] small_1; reg [57:0] large_1; wire [63:0] io_time_0 = {large_1, small_1}; wire [15:0] read_mip = {4'h0, io_interrupts_meip, 3'h0, io_interrupts_mtip, 3'h0, io_interrupts_msip, 3'h0}; wire [15:0] _GEN = reg_mie[15:0] & read_mip; wire [15:0] m_interrupts = reg_mstatus_mie ? _GEN : 16'h0; wire [29:0] _GEN_0 = {reg_pmp_0_addr[28:0], reg_pmp_0_cfg_a[0]}; wire [29:0] _GEN_1 = {reg_pmp_1_addr[28:0], reg_pmp_1_cfg_a[0]}; wire [29:0] _GEN_2 = {reg_pmp_2_addr[28:0], reg_pmp_2_cfg_a[0]}; wire [29:0] _GEN_3 = {reg_pmp_3_addr[28:0], reg_pmp_3_cfg_a[0]}; wire [29:0] _GEN_4 = {reg_pmp_4_addr[28:0], reg_pmp_4_cfg_a[0]}; wire [29:0] _GEN_5 = {reg_pmp_5_addr[28:0], reg_pmp_5_cfg_a[0]}; wire [29:0] _GEN_6 = {reg_pmp_6_addr[28:0], reg_pmp_6_cfg_a[0]}; wire [29:0] _GEN_7 = {reg_pmp_7_addr[28:0], reg_pmp_7_cfg_a[0]}; reg [63:0] reg_misa; wire [7:0] _GEN_8 = ~(reg_mtvec[0] ? 8'hFE : 8'h2); wire [31:0] _read_mtvec_T_5 = reg_mtvec & {24'hFFFFFF, _GEN_8}; wire [33:0] _io_evec_T_20 = ~reg_mepc; wire [33:0] _read_mapping_T_6 = ~{_io_evec_T_20[33:2], _io_evec_T_20[1:0] | {~(reg_misa[2]), 1'h1}}; wire [33:0] _io_evec_T_10 = ~reg_dpc; wire [33:0] _debug_csrs_T_4 = ~{_io_evec_T_10[33:2], _io_evec_T_10[1:0] | {~(reg_misa[2]), 1'h1}}; reg [63:0] reg_custom_0; wire [11:0] decoded_addr_decoded_decoded_invInputs = ~io_rw_addr; wire decoded_addr_30_2 = &{decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], decoded_addr_decoded_decoded_invInputs[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_58_2 = &{decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], decoded_addr_decoded_decoded_invInputs[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_87_2 = &{io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], decoded_addr_decoded_decoded_invInputs[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_88_2 = &{decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_82_2 = &{io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_65_2 = &{decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_61_2 = &{io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_117_2 = &{decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_116_2 = &{decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_119_2 = &{io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_24_2 = &{decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_123_2 = &{io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_127_2 = &{decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_92_2 = &{decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_7_2 = &{io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_112_2 = &{decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_74_2 = &{io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_45_2 = &{decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_18_2 = &{io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_122_2 = &{decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_103_2 = &{io_rw_addr[0], io_rw_addr[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_46_2 = &{io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_9_2 = &{decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_40_2 = &{decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_78_2 = &{io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_48_2 = &{io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_16_2 = &{io_rw_addr[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; wire decoded_addr_91_2 = &{decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], io_rw_addr[11]}; wire decoded_addr_109_2 = &{decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], io_rw_addr[11]}; wire [63:0] _wdata_T_2 = (io_rw_cmd[1] ? io_rw_rdata_0 : 64'h0) | io_rw_wdata; wire [63:0] _wdata_T_6 = ~((&(io_rw_cmd[1:0])) ? io_rw_wdata : 64'h0); wire system_insn = io_rw_cmd == 3'h4; wire [11:0] _GEN_9 = ~io_rw_addr; wire insn_call = system_insn & (&{_GEN_9[0], _GEN_9[1], _GEN_9[2], _GEN_9[3], _GEN_9[4], _GEN_9[5], _GEN_9[6], _GEN_9[7], _GEN_9[8], _GEN_9[9], _GEN_9[10], _GEN_9[11]}); wire insn_break = system_insn & (&{io_rw_addr[0], _GEN_9[1], _GEN_9[2], _GEN_9[3], _GEN_9[4], _GEN_9[5], _GEN_9[6], _GEN_9[7], _GEN_9[8], _GEN_9[9], _GEN_9[10], _GEN_9[11]}); wire insn_ret = system_insn & (|{&{_GEN_9[2], _GEN_9[3], _GEN_9[4], _GEN_9[5], _GEN_9[6], _GEN_9[7], io_rw_addr[8], io_rw_addr[9], _GEN_9[10], _GEN_9[11]}, &{io_rw_addr[10], _GEN_9[11]}}); wire [9:0] decoded_invInputs_1 = ~(io_decode_0_inst[31:22]); wire [31:0] _GEN_10 = {27'h0, io_decode_0_inst[24:20]}; wire [31:0] _io_decode_0_virtual_access_illegal_T_3 = 32'h0 >> _GEN_10; wire [31:0] _io_decode_0_virtual_access_illegal_T_6 = 32'h0 >> _GEN_10; wire io_decode_0_fp_illegal_0 = reg_mstatus_fs == 2'h0 | ~(reg_misa[5]); wire [2:0] io_decode_0_fp_csr_invInputs = ~(io_decode_0_inst[31:29]); wire io_decode_0_fp_csr_0 = &{io_decode_0_fp_csr_invInputs[0], io_decode_0_fp_csr_invInputs[1], io_decode_0_fp_csr_invInputs[2]}; wire csr_exists = io_decode_0_inst[31:20] == 12'h7A0 | io_decode_0_inst[31:20] == 12'h7A1 | io_decode_0_inst[31:20] == 12'h7A2 | io_decode_0_inst[31:20] == 12'h7A3 | io_decode_0_inst[31:20] == 12'h301 | io_decode_0_inst[31:20] == 12'h300 | io_decode_0_inst[31:20] == 12'h305 | io_decode_0_inst[31:20] == 12'h344 | io_decode_0_inst[31:20] == 12'h304 | io_decode_0_inst[31:20] == 12'h340 | io_decode_0_inst[31:20] == 12'h341 | io_decode_0_inst[31:20] == 12'h343 | io_decode_0_inst[31:20] == 12'h342 | io_decode_0_inst[31:20] == 12'hF14 | io_decode_0_inst[31:20] == 12'h7B0 | io_decode_0_inst[31:20] == 12'h7B1 | io_decode_0_inst[31:20] == 12'h7B2 | io_decode_0_inst[31:20] == 12'h1 | io_decode_0_inst[31:20] == 12'h2 | io_decode_0_inst[31:20] == 12'h3 | io_decode_0_inst[31:20] == 12'h320 | io_decode_0_inst[31:20] == 12'hB00 | io_decode_0_inst[31:20] == 12'hB02 | io_decode_0_inst[31:20] == 12'h323 | io_decode_0_inst[31:20] == 12'hB03 | io_decode_0_inst[31:20] == 12'hC03 | io_decode_0_inst[31:20] == 12'h324 | io_decode_0_inst[31:20] == 12'hB04 | io_decode_0_inst[31:20] == 12'hC04 | io_decode_0_inst[31:20] == 12'h325 | io_decode_0_inst[31:20] == 12'hB05 | io_decode_0_inst[31:20] == 12'hC05 | io_decode_0_inst[31:20] == 12'h326 | io_decode_0_inst[31:20] == 12'hB06 | io_decode_0_inst[31:20] == 12'hC06 | io_decode_0_inst[31:20] == 12'h327 | io_decode_0_inst[31:20] == 12'hB07 | io_decode_0_inst[31:20] == 12'hC07 | io_decode_0_inst[31:20] == 12'h328 | io_decode_0_inst[31:20] == 12'hB08 | io_decode_0_inst[31:20] == 12'hC08 | io_decode_0_inst[31:20] == 12'h329 | io_decode_0_inst[31:20] == 12'hB09 | io_decode_0_inst[31:20] == 12'hC09 | io_decode_0_inst[31:20] == 12'h32A | io_decode_0_inst[31:20] == 12'hB0A | io_decode_0_inst[31:20] == 12'hC0A | io_decode_0_inst[31:20] == 12'h32B | io_decode_0_inst[31:20] == 12'hB0B | io_decode_0_inst[31:20] == 12'hC0B | io_decode_0_inst[31:20] == 12'h32C | io_decode_0_inst[31:20] == 12'hB0C | io_decode_0_inst[31:20] == 12'hC0C | io_decode_0_inst[31:20] == 12'h32D | io_decode_0_inst[31:20] == 12'hB0D | io_decode_0_inst[31:20] == 12'hC0D | io_decode_0_inst[31:20] == 12'h32E | io_decode_0_inst[31:20] == 12'hB0E | io_decode_0_inst[31:20] == 12'hC0E | io_decode_0_inst[31:20] == 12'h32F | io_decode_0_inst[31:20] == 12'hB0F | io_decode_0_inst[31:20] == 12'hC0F | io_decode_0_inst[31:20] == 12'h330 | io_decode_0_inst[31:20] == 12'hB10 | io_decode_0_inst[31:20] == 12'hC10 | io_decode_0_inst[31:20] == 12'h331 | io_decode_0_inst[31:20] == 12'hB11 | io_decode_0_inst[31:20] == 12'hC11 | io_decode_0_inst[31:20] == 12'h332 | io_decode_0_inst[31:20] == 12'hB12 | io_decode_0_inst[31:20] == 12'hC12 | io_decode_0_inst[31:20] == 12'h333 | io_decode_0_inst[31:20] == 12'hB13 | io_decode_0_inst[31:20] == 12'hC13 | io_decode_0_inst[31:20] == 12'h334 | io_decode_0_inst[31:20] == 12'hB14 | io_decode_0_inst[31:20] == 12'hC14 | io_decode_0_inst[31:20] == 12'h335 | io_decode_0_inst[31:20] == 12'hB15 | io_decode_0_inst[31:20] == 12'hC15 | io_decode_0_inst[31:20] == 12'h336 | io_decode_0_inst[31:20] == 12'hB16 | io_decode_0_inst[31:20] == 12'hC16 | io_decode_0_inst[31:20] == 12'h337 | io_decode_0_inst[31:20] == 12'hB17 | io_decode_0_inst[31:20] == 12'hC17 | io_decode_0_inst[31:20] == 12'h338 | io_decode_0_inst[31:20] == 12'hB18 | io_decode_0_inst[31:20] == 12'hC18 | io_decode_0_inst[31:20] == 12'h339 | io_decode_0_inst[31:20] == 12'hB19 | io_decode_0_inst[31:20] == 12'hC19 | io_decode_0_inst[31:20] == 12'h33A | io_decode_0_inst[31:20] == 12'hB1A | io_decode_0_inst[31:20] == 12'hC1A | io_decode_0_inst[31:20] == 12'h33B | io_decode_0_inst[31:20] == 12'hB1B | io_decode_0_inst[31:20] == 12'hC1B | io_decode_0_inst[31:20] == 12'h33C | io_decode_0_inst[31:20] == 12'hB1C | io_decode_0_inst[31:20] == 12'hC1C | io_decode_0_inst[31:20] == 12'h33D | io_decode_0_inst[31:20] == 12'hB1D | io_decode_0_inst[31:20] == 12'hC1D | io_decode_0_inst[31:20] == 12'h33E | io_decode_0_inst[31:20] == 12'hB1E | io_decode_0_inst[31:20] == 12'hC1E | io_decode_0_inst[31:20] == 12'h33F | io_decode_0_inst[31:20] == 12'hB1F | io_decode_0_inst[31:20] == 12'hC1F | io_decode_0_inst[31:20] == 12'hC00 | io_decode_0_inst[31:20] == 12'hC02 | io_decode_0_inst[31:20] == 12'h3A0 | io_decode_0_inst[31:20] == 12'h3A2 | io_decode_0_inst[31:20] == 12'h3B0 | io_decode_0_inst[31:20] == 12'h3B1 | io_decode_0_inst[31:20] == 12'h3B2 | io_decode_0_inst[31:20] == 12'h3B3 | io_decode_0_inst[31:20] == 12'h3B4 | io_decode_0_inst[31:20] == 12'h3B5 | io_decode_0_inst[31:20] == 12'h3B6 | io_decode_0_inst[31:20] == 12'h3B7 | io_decode_0_inst[31:20] == 12'h3B8 | io_decode_0_inst[31:20] == 12'h3B9 | io_decode_0_inst[31:20] == 12'h3BA | io_decode_0_inst[31:20] == 12'h3BB | io_decode_0_inst[31:20] == 12'h3BC | io_decode_0_inst[31:20] == 12'h3BD | io_decode_0_inst[31:20] == 12'h3BE | io_decode_0_inst[31:20] == 12'h3BF | io_decode_0_inst[31:20] == 12'h7C1 | io_decode_0_inst[31:20] == 12'hF12 | io_decode_0_inst[31:20] == 12'hF11 | io_decode_0_inst[31:20] == 12'hF13 | io_decode_0_inst[31:20] == 12'hF15; wire [5:0] io_decode_0_read_illegal_invInputs = ~(io_decode_0_inst[31:26]); wire [11:0] io_decode_0_write_flush_addr_m = {io_decode_0_inst[31:30], io_decode_0_inst[29:20] | 10'h300}; wire [63:0] cause = insn_call ? {60'h0, {3'h1, ~reg_mstatus_v} - 4'h8} : insn_break ? 64'h3 : io_cause; wire _causeIsDebugTrigger_T_2 = cause[7:0] == 8'hE; wire causeIsDebugInt = cause[63] & _causeIsDebugTrigger_T_2; wire causeIsDebugTrigger = ~(cause[63]) & _causeIsDebugTrigger_T_2; wire trapToDebug = reg_singleStepped | causeIsDebugInt | causeIsDebugTrigger | ~(cause[63]) & insn_break & reg_dcsr_ebreakm | reg_debug; wire _exception_T = insn_call | insn_break; assign io_singleStep_0 = reg_dcsr_step & ~reg_debug; assign io_status_sd = ®_mstatus_fs; wire exception = _exception_T | io_exception; wire [2:0] _GEN_11 = {1'h0, {1'h0, insn_ret} + {1'h0, insn_call}} + {1'h0, {1'h0, insn_break} + {1'h0, io_exception}}; wire _GEN_12 = ~reg_singleStepped | ~io_retire; `ifndef SYNTHESIS always @(posedge clock) begin if ((`PRINTF_COND_) & ~reset & (|(_GEN_11[2:1]))) $fwrite(32'h80000002, "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:1023 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, \"these conditions must be mutually exclusive\")\n"); if ((`PRINTF_COND_) & ~reset & ~_GEN_12) $fwrite(32'h80000002, "Assertion failed\n at CSR.scala:1032 assert(!reg_singleStepped || io.retire === 0.U)\n"); end // always @(posedge) `endif // not def SYNTHESIS wire _GEN_13 = io_rw_addr[10] & io_rw_addr[7]; wire io_csr_stall_0 = reg_wfi | io_status_cease_r; wire [63:0] _io_rw_rdata_T_140 = (decoded_addr_46_2 ? {4'h2, reg_bp_0_control_dmode, 46'h40000000000, reg_bp_0_control_action, 3'h0, reg_bp_0_control_tmatch, 4'h8, reg_bp_0_control_x, reg_bp_0_control_w, reg_bp_0_control_r} : 64'h0) | (decoded_addr_9_2 ? {{31{reg_bp_0_address[32]}}, reg_bp_0_address} : 64'h0) | (decoded_addr_82_2 ? reg_misa : 64'h0) | (decoded_addr_88_2 ? {io_status_sd, 23'h0, reg_mstatus_mpv, reg_mstatus_gva, 23'h0, reg_mstatus_fs, 5'h18, reg_mstatus_mpie, 3'h0, reg_mstatus_mie, 3'h0} : 64'h0) | (decoded_addr_61_2 ? {32'h0, _read_mtvec_T_5} : 64'h0); wire [63:0] _io_rw_rdata_T_146 = {_io_rw_rdata_T_140[63:16], _io_rw_rdata_T_140[15:0] | ((&{io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}) ? read_mip : 16'h0)} | (decoded_addr_65_2 ? reg_mie : 64'h0) | (decoded_addr_116_2 ? reg_mscratch : 64'h0) | (decoded_addr_119_2 ? {{30{_read_mapping_T_6[33]}}, _read_mapping_T_6} : 64'h0) | (decoded_addr_123_2 ? {{30{reg_mtval[33]}}, reg_mtval} : 64'h0) | (decoded_addr_24_2 ? reg_mcause : 64'h0); wire [63:0] _io_rw_rdata_T_150 = {_io_rw_rdata_T_146[63:32], _io_rw_rdata_T_146[31:0] | (decoded_addr_40_2 ? {16'h4000, reg_dcsr_ebreakm, 6'h0, reg_dcsr_cause, reg_dcsr_v, 2'h0, reg_dcsr_step, 2'h3} : 32'h0)} | (decoded_addr_78_2 ? {{30{_debug_csrs_T_4[33]}}, _debug_csrs_T_4} : 64'h0) | (decoded_addr_48_2 ? reg_dscratch0 : 64'h0); wire [4:0] _GEN_14 = _io_rw_rdata_T_150[4:0] | (decoded_addr_30_2 ? reg_fflags : 5'h0); wire [7:0] _GEN_15 = {_io_rw_rdata_T_150[7:5], _GEN_14[4:3], _GEN_14[2:0] | (decoded_addr_58_2 ? reg_frm : 3'h0)} | (decoded_addr_87_2 ? {reg_frm, reg_fflags} : 8'h0); wire [63:0] _io_rw_rdata_T_247 = {_io_rw_rdata_T_150[63:8], _GEN_15[7:3], _GEN_15[2:0] | (decoded_addr_117_2 ? reg_mcountinhibit : 3'h0)} | (decoded_addr_91_2 ? io_time_0 : 64'h0) | (decoded_addr_109_2 ? value : 64'h0) | ((&{decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], decoded_addr_decoded_decoded_invInputs[8], decoded_addr_decoded_decoded_invInputs[9], io_rw_addr[10], io_rw_addr[11]}) ? io_time_0 : 64'h0) | ((&{decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], decoded_addr_decoded_decoded_invInputs[8], decoded_addr_decoded_decoded_invInputs[9], io_rw_addr[10], io_rw_addr[11]}) ? value : 64'h0) | (decoded_addr_127_2 ? {reg_pmp_7_cfg_l, 2'h0, reg_pmp_7_cfg_a, reg_pmp_7_cfg_x, reg_pmp_7_cfg_w, reg_pmp_7_cfg_r, reg_pmp_6_cfg_l, 2'h0, reg_pmp_6_cfg_a, reg_pmp_6_cfg_x, reg_pmp_6_cfg_w, reg_pmp_6_cfg_r, reg_pmp_5_cfg_l, 2'h0, reg_pmp_5_cfg_a, reg_pmp_5_cfg_x, reg_pmp_5_cfg_w, reg_pmp_5_cfg_r, reg_pmp_4_cfg_l, 2'h0, reg_pmp_4_cfg_a, reg_pmp_4_cfg_x, reg_pmp_4_cfg_w, reg_pmp_4_cfg_r, reg_pmp_3_cfg_l, 2'h0, reg_pmp_3_cfg_a, reg_pmp_3_cfg_x, reg_pmp_3_cfg_w, reg_pmp_3_cfg_r, reg_pmp_2_cfg_l, 2'h0, reg_pmp_2_cfg_a, reg_pmp_2_cfg_x, reg_pmp_2_cfg_w, reg_pmp_2_cfg_r, reg_pmp_1_cfg_l, 2'h0, reg_pmp_1_cfg_a, reg_pmp_1_cfg_x, reg_pmp_1_cfg_w, reg_pmp_1_cfg_r, reg_pmp_0_cfg_l, 2'h0, reg_pmp_0_cfg_a, reg_pmp_0_cfg_x, reg_pmp_0_cfg_w, reg_pmp_0_cfg_r} : 64'h0); assign io_rw_rdata_0 = {_io_rw_rdata_T_247[63:30], _io_rw_rdata_T_247[29:0] | (decoded_addr_92_2 ? reg_pmp_0_addr : 30'h0) | (decoded_addr_7_2 ? reg_pmp_1_addr : 30'h0) | (decoded_addr_112_2 ? reg_pmp_2_addr : 30'h0) | (decoded_addr_74_2 ? reg_pmp_3_addr : 30'h0) | (decoded_addr_45_2 ? reg_pmp_4_addr : 30'h0) | (decoded_addr_18_2 ? reg_pmp_5_addr : 30'h0) | (decoded_addr_122_2 ? reg_pmp_6_addr : 30'h0) | (decoded_addr_103_2 ? reg_pmp_7_addr : 30'h0)} | (decoded_addr_16_2 ? reg_custom_0 : 64'h0) | {63'h0, &{decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], io_rw_addr[11]}} | ((&{io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], io_rw_addr[11]}) ? 64'h20181004 : 64'h0); wire _csr_wen_T_4 = io_rw_cmd == 3'h6 | (&io_rw_cmd) | io_rw_cmd == 3'h5; wire [5:0] _GEN_16 = _wdata_T_2[5:0] & _wdata_T_6[5:0]; always @(posedge clock) begin automatic logic [63:0] wdata; automatic logic [33:0] epc; automatic logic _GEN_17; automatic logic _GEN_18; automatic logic [33:0] _GEN_19; automatic logic [2:0] _GEN_20; automatic logic _GEN_21 = ~reg_bp_0_control_dmode | reg_debug; automatic logic _GEN_22; automatic logic _GEN_23; automatic logic [29:0] _GEN_24; automatic logic _GEN_25; automatic logic _GEN_26; automatic logic _GEN_27; automatic logic _GEN_28; automatic logic _GEN_29; automatic logic _GEN_30; automatic logic _GEN_31 = reg_pmp_7_cfg_l & ~(reg_pmp_7_cfg_a[1]) & reg_pmp_7_cfg_a[0]; automatic logic _GEN_32; wdata = _wdata_T_2 & _wdata_T_6; epc = {io_pc[33:1], 1'h0}; _GEN_17 = exception & trapToDebug & ~reg_debug; _GEN_18 = ~exception | trapToDebug; _GEN_19 = {wdata[33:1], 1'h0}; _GEN_20 = _wdata_T_2[2:0] & _wdata_T_6[2:0]; _GEN_22 = _csr_wen_T_4 & _GEN_21 & decoded_addr_46_2; _GEN_23 = _csr_wen_T_4 & decoded_addr_127_2 & ~reg_pmp_0_cfg_l; _GEN_24 = _wdata_T_2[29:0] & _wdata_T_6[29:0]; _GEN_25 = _csr_wen_T_4 & decoded_addr_127_2 & ~reg_pmp_1_cfg_l; _GEN_26 = _csr_wen_T_4 & decoded_addr_127_2 & ~reg_pmp_2_cfg_l; _GEN_27 = _csr_wen_T_4 & decoded_addr_127_2 & ~reg_pmp_3_cfg_l; _GEN_28 = _csr_wen_T_4 & decoded_addr_127_2 & ~reg_pmp_4_cfg_l; _GEN_29 = _csr_wen_T_4 & decoded_addr_127_2 & ~reg_pmp_5_cfg_l; _GEN_30 = _csr_wen_T_4 & decoded_addr_127_2 & ~reg_pmp_6_cfg_l; _GEN_32 = _csr_wen_T_4 & decoded_addr_127_2 & ~reg_pmp_7_cfg_l; if (~reset) begin end if (reset) begin reg_mstatus_v <= 1'h0; reg_mstatus_mpv <= 1'h0; reg_mstatus_gva <= 1'h0; reg_mstatus_fs <= 2'h0; reg_mstatus_mpie <= 1'h0; reg_mstatus_mie <= 1'h0; reg_dcsr_ebreakm <= 1'h0; reg_dcsr_cause <= 3'h0; reg_dcsr_v <= 1'h0; reg_dcsr_step <= 1'h0; reg_debug <= 1'h0; reg_bp_0_control_dmode <= 1'h0; reg_bp_0_control_action <= 1'h0; reg_bp_0_control_x <= 1'h0; reg_bp_0_control_w <= 1'h0; reg_bp_0_control_r <= 1'h0; reg_pmp_0_cfg_l <= 1'h0; reg_pmp_0_cfg_a <= 2'h0; reg_pmp_1_cfg_l <= 1'h0; reg_pmp_1_cfg_a <= 2'h0; reg_pmp_2_cfg_l <= 1'h0; reg_pmp_2_cfg_a <= 2'h0; reg_pmp_3_cfg_l <= 1'h0; reg_pmp_3_cfg_a <= 2'h0; reg_pmp_4_cfg_l <= 1'h0; reg_pmp_4_cfg_a <= 2'h0; reg_pmp_5_cfg_l <= 1'h0; reg_pmp_5_cfg_a <= 2'h0; reg_pmp_6_cfg_l <= 1'h0; reg_pmp_6_cfg_a <= 2'h0; reg_pmp_7_cfg_l <= 1'h0; reg_pmp_7_cfg_a <= 2'h0; reg_mcause <= 64'h0; reg_mtvec <= 32'h0; reg_mcountinhibit <= 3'h0; small_0 <= 6'h0; large_0 <= 58'h0; reg_misa <= 64'h800000000080112D; reg_custom_0 <= 64'h8; io_status_cease_r <= 1'h0; end else begin automatic logic _GEN_33 = ~insn_ret | _GEN_13; automatic logic _GEN_34 = _csr_wen_T_4 & decoded_addr_88_2; reg_mstatus_v <= ~insn_ret & (~exception | trapToDebug & reg_debug) & reg_mstatus_v; reg_mstatus_mpv <= _GEN_33 & (_GEN_18 ? reg_mstatus_mpv : reg_mstatus_v); if (_GEN_18) begin end else reg_mstatus_gva <= io_gva; if (_GEN_34) reg_mstatus_fs <= {2{|(wdata[14:13])}}; reg_mstatus_mpie <= _GEN_34 ? wdata[7] : insn_ret & ~_GEN_13 | (_GEN_18 ? reg_mstatus_mpie : reg_mstatus_mie); reg_mstatus_mie <= _GEN_34 ? wdata[3] : _GEN_33 ? _GEN_18 & reg_mstatus_mie : reg_mstatus_mpie; if (_csr_wen_T_4 & decoded_addr_40_2) begin reg_dcsr_ebreakm <= _wdata_T_2[15] & _wdata_T_6[15]; reg_dcsr_step <= _wdata_T_2[2] & _wdata_T_6[2]; end if (_GEN_17) begin reg_dcsr_cause <= reg_singleStepped ? 3'h4 : {1'h0, causeIsDebugInt ? 2'h3 : causeIsDebugTrigger ? 2'h2 : 2'h1}; reg_dcsr_v <= reg_mstatus_v; end reg_debug <= ~(insn_ret & _GEN_13) & (_GEN_17 | reg_debug); if (_GEN_22) begin automatic logic [47:0] _newBPC_T_3 = (io_rw_cmd[1] ? {reg_bp_0_control_dmode, 46'h40000000000, reg_bp_0_control_action} : 48'h0) | io_rw_wdata[59:12]; automatic logic [47:0] _newBPC_T_7 = ~((&(io_rw_cmd[1:0])) ? io_rw_wdata[59:12] : 48'h0); automatic logic dMode = _newBPC_T_3[47] & _newBPC_T_7[47] & reg_debug; reg_bp_0_control_dmode <= dMode; reg_bp_0_control_action <= dMode & _newBPC_T_3[0] & _newBPC_T_7[0]; reg_bp_0_control_x <= _wdata_T_2[2] & _wdata_T_6[2]; reg_bp_0_control_w <= _wdata_T_2[1] & _wdata_T_6[1]; reg_bp_0_control_r <= _wdata_T_2[0] & _wdata_T_6[0]; end if (_GEN_23) begin reg_pmp_0_cfg_l <= _wdata_T_2[7] & _wdata_T_6[7]; reg_pmp_0_cfg_a <= _wdata_T_2[4:3] & _wdata_T_6[4:3]; end if (_GEN_25) begin reg_pmp_1_cfg_l <= _wdata_T_2[15] & _wdata_T_6[15]; reg_pmp_1_cfg_a <= _wdata_T_2[12:11] & _wdata_T_6[12:11]; end if (_GEN_26) begin reg_pmp_2_cfg_l <= _wdata_T_2[23] & _wdata_T_6[23]; reg_pmp_2_cfg_a <= _wdata_T_2[20:19] & _wdata_T_6[20:19]; end if (_GEN_27) begin reg_pmp_3_cfg_l <= _wdata_T_2[31] & _wdata_T_6[31]; reg_pmp_3_cfg_a <= _wdata_T_2[28:27] & _wdata_T_6[28:27]; end if (_GEN_28) begin reg_pmp_4_cfg_l <= _wdata_T_2[39] & _wdata_T_6[39]; reg_pmp_4_cfg_a <= _wdata_T_2[36:35] & _wdata_T_6[36:35]; end if (_GEN_29) begin reg_pmp_5_cfg_l <= _wdata_T_2[47] & _wdata_T_6[47]; reg_pmp_5_cfg_a <= _wdata_T_2[44:43] & _wdata_T_6[44:43]; end if (_GEN_30) begin reg_pmp_6_cfg_l <= _wdata_T_2[55] & _wdata_T_6[55]; reg_pmp_6_cfg_a <= _wdata_T_2[52:51] & _wdata_T_6[52:51]; end if (_GEN_32) begin reg_pmp_7_cfg_l <= _wdata_T_2[63] & _wdata_T_6[63]; reg_pmp_7_cfg_a <= _wdata_T_2[60:59] & _wdata_T_6[60:59]; end if (_csr_wen_T_4 & decoded_addr_24_2) reg_mcause <= wdata & 64'h800000000000000F; else if (_GEN_18) begin end else reg_mcause <= cause; if (_csr_wen_T_4 & decoded_addr_61_2) reg_mtvec <= _wdata_T_2[31:0] & _wdata_T_6[31:0]; if (_csr_wen_T_4 & decoded_addr_117_2) reg_mcountinhibit <= _GEN_20 & 3'h5; if (_csr_wen_T_4 & decoded_addr_109_2) begin small_0 <= _GEN_16; large_0 <= _wdata_T_2[63:6] & _wdata_T_6[63:6]; end else begin automatic logic [6:0] nextSmall; nextSmall = {1'h0, small_0} + {6'h0, io_retire}; if (reg_mcountinhibit[2]) begin end else small_0 <= nextSmall[5:0]; if (nextSmall[6] & ~(reg_mcountinhibit[2])) large_0 <= large_0 + 58'h1; end if (_csr_wen_T_4 & decoded_addr_82_2 & (~(io_pc[1]) | _wdata_T_2[2] & _wdata_T_6[2])) begin automatic logic [12:0] _reg_misa_T; _reg_misa_T = ~(wdata[12:0]); reg_misa <= {51'h0, ~{_reg_misa_T[12:4], _reg_misa_T[3:0] | {~(_wdata_T_2[5] & _wdata_T_6[5]), 3'h0}} & 13'h102D} | {reg_misa[63:1] & 63'h7FFFFFFFFFFFF7E9, 1'h0}; end if (_csr_wen_T_4 & decoded_addr_16_2) reg_custom_0 <= {60'h0, wdata[3], 3'h0} | reg_custom_0 & 64'hFFFFFFFFFFFFFFF7; io_status_cease_r <= system_insn & (&{io_rw_addr[2], _GEN_9[3], _GEN_9[4], _GEN_9[5], _GEN_9[6], _GEN_9[7], io_rw_addr[8], io_rw_addr[9], _GEN_9[10], _GEN_9[11]}) | io_status_cease_r; end if (_csr_wen_T_4 & decoded_addr_78_2) reg_dpc <= _GEN_19; else if (_GEN_17) reg_dpc <= epc; if (_csr_wen_T_4 & decoded_addr_48_2) reg_dscratch0 <= wdata; reg_singleStepped <= io_singleStep_0 & (io_retire | exception | reg_singleStepped); if (_GEN_22) reg_bp_0_control_tmatch <= _wdata_T_2[8:7] & _wdata_T_6[8:7]; if (_csr_wen_T_4 & _GEN_21 & decoded_addr_9_2) reg_bp_0_address <= _wdata_T_2[32:0] & _wdata_T_6[32:0]; if (_GEN_23) begin automatic logic newCfg_r = _wdata_T_2[0] & _wdata_T_6[0]; reg_pmp_0_cfg_x <= _wdata_T_2[2] & _wdata_T_6[2]; reg_pmp_0_cfg_w <= _wdata_T_2[1] & _wdata_T_6[1] & newCfg_r; reg_pmp_0_cfg_r <= newCfg_r; end if (_csr_wen_T_4 & decoded_addr_92_2 & ~(reg_pmp_0_cfg_l | reg_pmp_1_cfg_l & ~(reg_pmp_1_cfg_a[1]) & reg_pmp_1_cfg_a[0])) reg_pmp_0_addr <= _GEN_24; if (_GEN_25) begin automatic logic newCfg_1_r = _wdata_T_2[8] & _wdata_T_6[8]; reg_pmp_1_cfg_x <= _wdata_T_2[10] & _wdata_T_6[10]; reg_pmp_1_cfg_w <= _wdata_T_2[9] & _wdata_T_6[9] & newCfg_1_r; reg_pmp_1_cfg_r <= newCfg_1_r; end if (_csr_wen_T_4 & decoded_addr_7_2 & ~(reg_pmp_1_cfg_l | reg_pmp_2_cfg_l & ~(reg_pmp_2_cfg_a[1]) & reg_pmp_2_cfg_a[0])) reg_pmp_1_addr <= _GEN_24; if (_GEN_26) begin automatic logic newCfg_2_r = _wdata_T_2[16] & _wdata_T_6[16]; reg_pmp_2_cfg_x <= _wdata_T_2[18] & _wdata_T_6[18]; reg_pmp_2_cfg_w <= _wdata_T_2[17] & _wdata_T_6[17] & newCfg_2_r; reg_pmp_2_cfg_r <= newCfg_2_r; end if (_csr_wen_T_4 & decoded_addr_112_2 & ~(reg_pmp_2_cfg_l | reg_pmp_3_cfg_l & ~(reg_pmp_3_cfg_a[1]) & reg_pmp_3_cfg_a[0])) reg_pmp_2_addr <= _GEN_24; if (_GEN_27) begin automatic logic newCfg_3_r = _wdata_T_2[24] & _wdata_T_6[24]; reg_pmp_3_cfg_x <= _wdata_T_2[26] & _wdata_T_6[26]; reg_pmp_3_cfg_w <= _wdata_T_2[25] & _wdata_T_6[25] & newCfg_3_r; reg_pmp_3_cfg_r <= newCfg_3_r; end if (_csr_wen_T_4 & decoded_addr_74_2 & ~(reg_pmp_3_cfg_l | reg_pmp_4_cfg_l & ~(reg_pmp_4_cfg_a[1]) & reg_pmp_4_cfg_a[0])) reg_pmp_3_addr <= _GEN_24; if (_GEN_28) begin automatic logic newCfg_4_r = _wdata_T_2[32] & _wdata_T_6[32]; reg_pmp_4_cfg_x <= _wdata_T_2[34] & _wdata_T_6[34]; reg_pmp_4_cfg_w <= _wdata_T_2[33] & _wdata_T_6[33] & newCfg_4_r; reg_pmp_4_cfg_r <= newCfg_4_r; end if (_csr_wen_T_4 & decoded_addr_45_2 & ~(reg_pmp_4_cfg_l | reg_pmp_5_cfg_l & ~(reg_pmp_5_cfg_a[1]) & reg_pmp_5_cfg_a[0])) reg_pmp_4_addr <= _GEN_24; if (_GEN_29) begin automatic logic newCfg_5_r = _wdata_T_2[40] & _wdata_T_6[40]; reg_pmp_5_cfg_x <= _wdata_T_2[42] & _wdata_T_6[42]; reg_pmp_5_cfg_w <= _wdata_T_2[41] & _wdata_T_6[41] & newCfg_5_r; reg_pmp_5_cfg_r <= newCfg_5_r; end if (_csr_wen_T_4 & decoded_addr_18_2 & ~(reg_pmp_5_cfg_l | reg_pmp_6_cfg_l & ~(reg_pmp_6_cfg_a[1]) & reg_pmp_6_cfg_a[0])) reg_pmp_5_addr <= _GEN_24; if (_GEN_30) begin automatic logic newCfg_6_r = _wdata_T_2[48] & _wdata_T_6[48]; reg_pmp_6_cfg_x <= _wdata_T_2[50] & _wdata_T_6[50]; reg_pmp_6_cfg_w <= _wdata_T_2[49] & _wdata_T_6[49] & newCfg_6_r; reg_pmp_6_cfg_r <= newCfg_6_r; end if (_csr_wen_T_4 & decoded_addr_122_2 & ~(reg_pmp_6_cfg_l | _GEN_31)) reg_pmp_6_addr <= _GEN_24; if (_GEN_32) begin automatic logic newCfg_7_r = _wdata_T_2[56] & _wdata_T_6[56]; reg_pmp_7_cfg_x <= _wdata_T_2[58] & _wdata_T_6[58]; reg_pmp_7_cfg_w <= _wdata_T_2[57] & _wdata_T_6[57] & newCfg_7_r; reg_pmp_7_cfg_r <= newCfg_7_r; end if (_csr_wen_T_4 & decoded_addr_103_2 & ~(reg_pmp_7_cfg_l | _GEN_31)) reg_pmp_7_addr <= _GEN_24; if (_csr_wen_T_4 & decoded_addr_65_2) reg_mie <= {52'h0, _wdata_T_2[11:3] & _wdata_T_6[11:3] & 9'h111, 3'h0}; if (_csr_wen_T_4 & decoded_addr_119_2) reg_mepc <= _GEN_19; else if (_GEN_18) begin end else reg_mepc <= epc; if (_csr_wen_T_4 & decoded_addr_123_2) reg_mtval <= _wdata_T_2[33:0] & _wdata_T_6[33:0]; else if (_GEN_18) begin end else reg_mtval <= insn_break ? epc : io_tval; if (_csr_wen_T_4 & decoded_addr_116_2) reg_mscratch <= wdata; reg_fflags <= _csr_wen_T_4 & (decoded_addr_87_2 | decoded_addr_30_2) ? _wdata_T_2[4:0] & _wdata_T_6[4:0] : {5{io_fcsr_flags_valid}} & io_fcsr_flags_bits | reg_fflags; if (_csr_wen_T_4) begin if (decoded_addr_87_2) reg_frm <= _wdata_T_2[7:5] & _wdata_T_6[7:5]; else if (decoded_addr_58_2) reg_frm <= _GEN_20; end end // always @(posedge) always @(posedge io_ungated_clock) begin if (reset) begin reg_wfi <= 1'h0; small_1 <= 6'h0; large_1 <= 58'h0; end else begin reg_wfi <= ~((|{_GEN[11], _GEN[7], _GEN[3]}) | io_interrupts_debug | exception) & (system_insn & (&{io_rw_addr[8], _GEN_9[9], _GEN_9[10], _GEN_9[11]}) & ~io_singleStep_0 & ~reg_debug | reg_wfi); if (_csr_wen_T_4 & decoded_addr_91_2) begin small_1 <= _GEN_16; large_1 <= _wdata_T_2[63:6] & _wdata_T_6[63:6]; end else begin automatic logic [6:0] nextSmall_1; nextSmall_1 = {1'h0, small_1} + {6'h0, ~io_csr_stall_0}; if (reg_mcountinhibit[0]) begin end else small_1 <= nextSmall_1[5:0]; if (nextSmall_1[6] & ~(reg_mcountinhibit[0])) large_1 <= large_1 + 58'h1; end end end // always @(posedge) assign io_rw_rdata = io_rw_rdata_0; assign io_decode_0_fp_illegal = io_decode_0_fp_illegal_0; assign io_decode_0_fp_csr = io_decode_0_fp_csr_0; assign io_decode_0_read_illegal = ~csr_exists | (&{io_decode_0_inst[24], io_decode_0_inst[25], io_decode_0_read_illegal_invInputs[0], io_decode_0_inst[27], io_decode_0_inst[28], io_decode_0_inst[29], io_decode_0_inst[30], io_decode_0_read_illegal_invInputs[5]}) & ~reg_debug | io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; assign io_decode_0_write_illegal = &(io_decode_0_inst[31:30]); assign io_decode_0_write_flush = ~(io_decode_0_write_flush_addr_m > 12'h33F & io_decode_0_write_flush_addr_m < 12'h344); assign io_decode_0_system_illegal = (|{&{decoded_invInputs_1[0], decoded_invInputs_1[1], decoded_invInputs_1[2], decoded_invInputs_1[3], decoded_invInputs_1[4], decoded_invInputs_1[5], io_decode_0_inst[28], io_decode_0_inst[29], decoded_invInputs_1[8], decoded_invInputs_1[9]}, &{io_decode_0_inst[30], decoded_invInputs_1[9]}}) & io_decode_0_inst[30] & io_decode_0_inst[27] & ~reg_debug; assign io_decode_0_virtual_access_illegal = reg_mstatus_v & csr_exists & (io_decode_0_inst[29:28] == 2'h2 | (io_decode_0_inst[31:20] > 12'hBFF & io_decode_0_inst[31:20] < 12'hC20 | io_decode_0_inst[31:20] > 12'hC7F & io_decode_0_inst[31:20] < 12'hCA0) & _io_decode_0_virtual_access_illegal_T_3[0] & ~(_io_decode_0_virtual_access_illegal_T_6[0])); assign io_csr_stall = io_csr_stall_0; assign io_eret = _exception_T | insn_ret; assign io_singleStep = io_singleStep_0; assign io_status_debug = reg_debug; assign io_status_wfi = reg_wfi; assign io_status_isa = reg_misa[31:0]; assign io_status_dv = reg_mstatus_v; assign io_status_v = reg_mstatus_v; assign io_evec = insn_ret ? (_GEN_13 ? ~{_io_evec_T_10[33:2], _io_evec_T_10[1:0] | {~(reg_misa[2]), 1'h1}} : ~{_io_evec_T_20[33:2], _io_evec_T_20[1:0] | {~(reg_misa[2]), 1'h1}}) : trapToDebug ? {22'h0, reg_debug ? {8'h80, ~insn_break, 3'h0} : 12'h800} : {2'h0, reg_mtvec[0] & _GEN_8[0] & cause[63] & cause[7:6] == 2'h0 ? {_read_mtvec_T_5[31:8], cause[5:0]} : _read_mtvec_T_5[31:2], 2'h0}; assign io_time = io_time_0; assign io_fcsr_rm = reg_frm; assign io_interrupt = ((io_interrupts_debug | m_interrupts[15] | m_interrupts[14] | m_interrupts[13] | m_interrupts[12] | m_interrupts[11] | m_interrupts[3] | m_interrupts[7] | m_interrupts[9] | m_interrupts[1] | m_interrupts[5] | m_interrupts[10] | m_interrupts[2] | m_interrupts[6] | m_interrupts[8] | m_interrupts[0] | m_interrupts[4]) & ~io_singleStep_0 | reg_singleStepped) & ~(reg_debug | io_status_cease_r); assign io_interrupt_cause = {60'h0, io_interrupts_debug ? 4'hE : m_interrupts[15] ? 4'hF : m_interrupts[14] ? 4'hE : m_interrupts[13] ? 4'hD : m_interrupts[12] ? 4'hC : m_interrupts[11] ? 4'hB : m_interrupts[3] ? 4'h3 : m_interrupts[7] ? 4'h7 : m_interrupts[9] ? 4'h9 : m_interrupts[1] ? 4'h1 : m_interrupts[5] ? 4'h5 : m_interrupts[10] ? 4'hA : m_interrupts[2] ? 4'h2 : m_interrupts[6] ? 4'h6 : m_interrupts[8] ? 4'h8 : {1'h0, ~(m_interrupts[0]), 2'h0}} - 64'h8000000000000000; assign io_bp_0_control_action = reg_bp_0_control_action; assign io_bp_0_control_tmatch = reg_bp_0_control_tmatch; assign io_bp_0_control_x = reg_bp_0_control_x; assign io_bp_0_control_w = reg_bp_0_control_w; assign io_bp_0_control_r = reg_bp_0_control_r; assign io_bp_0_address = reg_bp_0_address; assign io_pmp_0_cfg_l = reg_pmp_0_cfg_l; assign io_pmp_0_cfg_a = reg_pmp_0_cfg_a; assign io_pmp_0_cfg_x = reg_pmp_0_cfg_x; assign io_pmp_0_cfg_w = reg_pmp_0_cfg_w; assign io_pmp_0_cfg_r = reg_pmp_0_cfg_r; assign io_pmp_0_addr = reg_pmp_0_addr; assign io_pmp_0_mask = {_GEN_0 & ~(_GEN_0 + 30'h1), 2'h3}; assign io_pmp_1_cfg_l = reg_pmp_1_cfg_l; assign io_pmp_1_cfg_a = reg_pmp_1_cfg_a; assign io_pmp_1_cfg_x = reg_pmp_1_cfg_x; assign io_pmp_1_cfg_w = reg_pmp_1_cfg_w; assign io_pmp_1_cfg_r = reg_pmp_1_cfg_r; assign io_pmp_1_addr = reg_pmp_1_addr; assign io_pmp_1_mask = {_GEN_1 & ~(_GEN_1 + 30'h1), 2'h3}; assign io_pmp_2_cfg_l = reg_pmp_2_cfg_l; assign io_pmp_2_cfg_a = reg_pmp_2_cfg_a; assign io_pmp_2_cfg_x = reg_pmp_2_cfg_x; assign io_pmp_2_cfg_w = reg_pmp_2_cfg_w; assign io_pmp_2_cfg_r = reg_pmp_2_cfg_r; assign io_pmp_2_addr = reg_pmp_2_addr; assign io_pmp_2_mask = {_GEN_2 & ~(_GEN_2 + 30'h1), 2'h3}; assign io_pmp_3_cfg_l = reg_pmp_3_cfg_l; assign io_pmp_3_cfg_a = reg_pmp_3_cfg_a; assign io_pmp_3_cfg_x = reg_pmp_3_cfg_x; assign io_pmp_3_cfg_w = reg_pmp_3_cfg_w; assign io_pmp_3_cfg_r = reg_pmp_3_cfg_r; assign io_pmp_3_addr = reg_pmp_3_addr; assign io_pmp_3_mask = {_GEN_3 & ~(_GEN_3 + 30'h1), 2'h3}; assign io_pmp_4_cfg_l = reg_pmp_4_cfg_l; assign io_pmp_4_cfg_a = reg_pmp_4_cfg_a; assign io_pmp_4_cfg_x = reg_pmp_4_cfg_x; assign io_pmp_4_cfg_w = reg_pmp_4_cfg_w; assign io_pmp_4_cfg_r = reg_pmp_4_cfg_r; assign io_pmp_4_addr = reg_pmp_4_addr; assign io_pmp_4_mask = {_GEN_4 & ~(_GEN_4 + 30'h1), 2'h3}; assign io_pmp_5_cfg_l = reg_pmp_5_cfg_l; assign io_pmp_5_cfg_a = reg_pmp_5_cfg_a; assign io_pmp_5_cfg_x = reg_pmp_5_cfg_x; assign io_pmp_5_cfg_w = reg_pmp_5_cfg_w; assign io_pmp_5_cfg_r = reg_pmp_5_cfg_r; assign io_pmp_5_addr = reg_pmp_5_addr; assign io_pmp_5_mask = {_GEN_5 & ~(_GEN_5 + 30'h1), 2'h3}; assign io_pmp_6_cfg_l = reg_pmp_6_cfg_l; assign io_pmp_6_cfg_a = reg_pmp_6_cfg_a; assign io_pmp_6_cfg_x = reg_pmp_6_cfg_x; assign io_pmp_6_cfg_w = reg_pmp_6_cfg_w; assign io_pmp_6_cfg_r = reg_pmp_6_cfg_r; assign io_pmp_6_addr = reg_pmp_6_addr; assign io_pmp_6_mask = {_GEN_6 & ~(_GEN_6 + 30'h1), 2'h3}; assign io_pmp_7_cfg_l = reg_pmp_7_cfg_l; assign io_pmp_7_cfg_a = reg_pmp_7_cfg_a; assign io_pmp_7_cfg_x = reg_pmp_7_cfg_x; assign io_pmp_7_cfg_w = reg_pmp_7_cfg_w; assign io_pmp_7_cfg_r = reg_pmp_7_cfg_r; assign io_pmp_7_addr = reg_pmp_7_addr; assign io_pmp_7_mask = {_GEN_7 & ~(_GEN_7 + 30'h1), 2'h3}; assign io_inhibit_cycle = reg_mcountinhibit[0]; assign io_trace_0_valid = io_retire | exception; assign io_trace_0_iaddr = io_pc; assign io_trace_0_insn = io_inst_0; assign io_trace_0_exception = exception; assign io_customCSRs_0_value = reg_custom_0; endmodule