// Generated by CIRCT firtool-1.151.0
module NonSyncResetSynchronizerPrimitiveShiftReg_d3(
  input  clock,
         io_d,
  output io_q
);

  reg sync_0;
  reg sync_1;
  reg sync_2;
  always @(posedge clock) begin
    sync_0 <= sync_1;
    sync_1 <= sync_2;
    sync_2 <= io_d;
  end // always @(posedge)
  assign io_q = sync_0;
endmodule