/dts-v1/;

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "freechips,rocketchip-unknown-dev";
	model = "freechips,rocketchip-unknown";
	L30: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <1000000>;
		L6: cpu@0 {
			clock-frequency = <0>;
			compatible = "sifive,rocket0", "riscv";
			device_type = "cpu";
			hardware-exec-breakpoint-count = <1>;
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <4096>;
			reg = <0x0>;
			riscv,isa = "rv64imafdczicsr_zifencei_zihpm_xrocket";
			riscv,pmpgranularity = <4>;
			riscv,pmpregions = <8>;
			sifive,dtim = <&L5>;
			status = "okay";
			timebase-frequency = <1000000>;
			L3: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};
	};
	L29: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
		ranges;
		L1: cbus_clock {
			#clock-cells = <0>;
			clock-frequency = <100000000>;
			clock-output-names = "cbus_clock";
			compatible = "fixed-clock";
		};
		L7: clint@2000000 {
			compatible = "riscv,clint0";
			interrupts-extended = <&L3 3 &L3 7>;
			reg = <0x2000000 0x10000>;
			reg-names = "control";
		};
		L9: debug-controller@0 {
			compatible = "sifive,debug-013", "riscv,debug-013";
			debug-attach = "dmi";
			interrupts-extended = <&L3 65535>;
			reg = <0x0 0x1000>;
			reg-names = "control";
		};
		L5: dtim@80000000 {
			compatible = "sifive,dtim0";
			reg = <0x80000000 0x100000>;
			reg-names = "mem";
		};
		L2: error-device@3000 {
			compatible = "sifive,error0";
			reg = <0x3000 0x1000>;
		};
		L17: gps-acq@10020000 {
			compatible = "anka,gps-acq-apb";
			interrupt-parent = <&L8>;
			interrupts = <1>;
			reg = <0x10020000 0x1000>;
		};
		L27: gps-pps@1002a000 {
			compatible = "anka,gps-pps-apb";
			reg = <0x1002a000 0x1000>;
		};
		L18: gps-tracking0@10021000 {
			compatible = "anka,gps-tracking-apb";
			interrupt-parent = <&L8>;
			interrupts = <2>;
			reg = <0x10021000 0x1000>;
		};
		L19: gps-tracking1@10022000 {
			compatible = "anka,gps-tracking-apb";
			interrupt-parent = <&L8>;
			interrupts = <3>;
			reg = <0x10022000 0x1000>;
		};
		L20: gps-tracking2@10023000 {
			compatible = "anka,gps-tracking-apb";
			interrupt-parent = <&L8>;
			interrupts = <4>;
			reg = <0x10023000 0x1000>;
		};
		L21: gps-tracking3@10024000 {
			compatible = "anka,gps-tracking-apb";
			interrupt-parent = <&L8>;
			interrupts = <5>;
			reg = <0x10024000 0x1000>;
		};
		L22: gps-tracking4@10025000 {
			compatible = "anka,gps-tracking-apb";
			interrupt-parent = <&L8>;
			interrupts = <6>;
			reg = <0x10025000 0x1000>;
		};
		L23: gps-tracking5@10026000 {
			compatible = "anka,gps-tracking-apb";
			interrupt-parent = <&L8>;
			interrupts = <7>;
			reg = <0x10026000 0x1000>;
		};
		L24: gps-tracking6@10027000 {
			compatible = "anka,gps-tracking-apb";
			interrupt-parent = <&L8>;
			interrupts = <8>;
			reg = <0x10027000 0x1000>;
		};
		L25: gps-tracking7@10028000 {
			compatible = "anka,gps-tracking-apb";
			interrupt-parent = <&L8>;
			interrupts = <9>;
			reg = <0x10028000 0x1000>;
		};
		L26: gps-tracking8@10029000 {
			compatible = "anka,gps-tracking-apb";
			interrupt-parent = <&L8>;
			interrupts = <10>;
			reg = <0x10029000 0x1000>;
		};
		L8: interrupt-controller@c000000 {
			#interrupt-cells = <1>;
			compatible = "riscv,plic0";
			interrupt-controller;
			interrupts-extended = <&L3 11>;
			reg = <0xc000000 0x4000000>;
			reg-names = "control";
			riscv,max-priority = <7>;
			riscv,ndev = <11>;
		};
		L0: pbus_clock {
			#clock-cells = <0>;
			clock-frequency = <100000000>;
			clock-output-names = "pbus_clock";
			compatible = "fixed-clock";
		};
		L13: pmod-sensor-irq {
			compatible = "rocket,pmod-sensor-irq";
			interrupt-parent = <&L8>;
			interrupts = <11>;
		};
		L16: pmod-spi@10015000 {
			compatible = "rocket,fpga-pmod-spi", "rocket,fpga-spi";
			reg = <0x10015000 0x1000>;
			reg-names = "control";
		};
		L12: rom@10000 {
			compatible = "sifive,rom0";
			reg = <0x10000 0x10000>;
			reg-names = "mem";
		};
		L15: spi@10014000 {
			compatible = "rocket,fpga-spi";
			reg = <0x10014000 0x1000>;
			reg-names = "control";
		};
		L14: uart@10013000 {
			compatible = "rocket,fpga-uart";
			reg = <0x10013000 0x1000>;
			reg-names = "control";
		};
	};
};