## Digilent Genesys 2 Rev. H, xc7k325tffg900-2.
## Pins are taken from Digilent Genesys-2-Master.xdc.

set_property PACKAGE_PIN AD12 [get_ports sysclk_p]
set_property PACKAGE_PIN AD11 [get_ports sysclk_n]
set_property IOSTANDARD LVDS [get_ports {sysclk_p sysclk_n}]
create_clock -period 5.000 -name sysclk_200 [get_ports sysclk_p]

# Async clock groups and optional RF pins are mode-dependent.
# build.tcl reads the matching companion XDC and applies clock groups after synth.

set_property PACKAGE_PIN R19 [get_ports cpu_resetn]
set_property IOSTANDARD LVCMOS33 [get_ports cpu_resetn]

# UART is routed through PMOD JB.
# uart_rx_out is FPGA UART TX on JB[0], uart_tx_in is FPGA UART RX on JB[1].
# Previous onboard USB-UART pins:
set_property PACKAGE_PIN Y20 [get_ports uart_tx_in]
set_property PACKAGE_PIN Y23 [get_ports uart_rx_out]
#set_property PACKAGE_PIN V30 [get_ports uart_tx_in]
#set_property PACKAGE_PIN V29 [get_ports uart_rx_out]
set_property IOSTANDARD LVCMOS33 [get_ports {uart_tx_in uart_rx_out}]
set_property DRIVE 8 [get_ports uart_rx_out]

set_property PACKAGE_PIN T28 [get_ports {led[0]}]
set_property PACKAGE_PIN V19 [get_ports {led[1]}]
set_property PACKAGE_PIN U30 [get_ports {led[2]}]
set_property PACKAGE_PIN U29 [get_ports {led[3]}]
set_property PACKAGE_PIN V20 [get_ports {led[4]}]
set_property PACKAGE_PIN V26 [get_ports {led[5]}]
set_property PACKAGE_PIN W24 [get_ports {led[6]}]
set_property PACKAGE_PIN W23 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports led[*]]
set_property DRIVE 8 [get_ports led[*]]

set_property PACKAGE_PIN U19 [get_ports qspi_csn]
set_property PACKAGE_PIN P24 [get_ports {qspi_d[0]}]
set_property PACKAGE_PIN R25 [get_ports {qspi_d[1]}]
set_property PACKAGE_PIN R20 [get_ports {qspi_d[2]}]
set_property PACKAGE_PIN R21 [get_ports {qspi_d[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {qspi_csn qspi_d[*]}]
set_property DRIVE 8 [get_ports {qspi_csn qspi_d[*]}]
set_property SLEW SLOW [get_ports {qspi_csn qspi_d[*]}]

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]