.PHONY: help all smoke clean

help:
	@echo "VCU118 simulation targets:"
	@echo "  make smoke  # generate RTL and check expected generated files exist"
	@echo "  make clean  # remove generated simulation inputs"
	@echo ""
	@echo "A full Verilator/FPGA-board simulation harness has not been added yet."

all: smoke

smoke:
	@make -C ../../../../targets/fpga/vcu118 rtl
	test -f ../../../generated/vcu118-soc-verilog/VCU118RocketSystem.sv
	test -f ../../../../targets/fpga/vcu118/out/build/generated/vcu118_rocket_top.sv

clean:
	rm -rf ../../../generated/vcu118-soc-verilog ../../../../targets/fpga/vcu118/out/build/generated