#-----------------------------------------------------------
# Vivado v2025.2 (64-bit)
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
# Start of session at: Sat Jul 11 20:07:29 2026
# Process ID         : 365586
# Current directory  : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
# Command line       : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
# Log file           : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
# Journal file       : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
# Running On         : onur
# Platform           : Ubuntu
# Operating System   : Ubuntu 22.04.5 LTS
# Processor Detail   : AMD Ryzen 7 7800X3D 8-Core Processor
# CPU Frequency      : 4199.924 MHz
# CPU Physical cores : 12
# CPU Logical cores  : 12
# Host memory        : 22112 MB
# Swap memory        : 2147 MB
# Total Virtual      : 24260 MB
# Available Virtual  : 21531 MB
#-----------------------------------------------------------
Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
# set script_dir [file dirname [file normalize [info script]]]
# set fpga_dir [file normalize [file join $script_dir ../..]]
# proc getenv_default {name default} {
#   if {[info exists ::env($name)] && $::env($name) ne ""} {
#     return $::env($name)
#   }
#   return $default
# }
# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
# open_hw_manager
# connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2025.2
  **** Build date : Oct 28 2025 at 16:07:00
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.


INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
INFO: [Labtools 27-3417] Launching cs_server...
INFO: [Labtools 27-2221] Launch Output:


******** Xilinx cs_server v2025.2.0
  ****** Build date   : Nov 14 2025-02:16:52
    **** Build number : 2025.2.1763075812
      ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
      ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.



# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
# set dev [lindex [get_hw_devices $device_pattern] 0]
# if {$dev eq ""} {
#   error "No hardware device found matching $device_pattern"
# }
# current_hw_device $dev
# refresh_hw_device $dev
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
# set_property PROGRAM.FILE $bit_file $dev
# program_hw_devices $dev
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1669.160 ; gain = 1.000 ; free physical = 9122 ; free virtual = 20028
# refresh_hw_device $dev
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
# puts "Programmed FPGA with $bit_file"
Programmed FPGA with /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 20:07:44 2026...