#----------------------------------------------------------- # Vivado v2025.2 (64-bit) # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 # SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 # Start of session at: Sat Jul 11 11:10:57 2026 # Process ID : 4999 # Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs # Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl # Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log # Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou # Running On : onur # Platform : Ubuntu # Operating System : Ubuntu 22.04.5 LTS # Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor # CPU Frequency : 4199.924 MHz # CPU Physical cores : 12 # CPU Logical cores : 12 # Host memory : 22112 MB # Swap memory : 2147 MB # Total Virtual : 24260 MB # Available Virtual : 21129 MB #----------------------------------------------------------- Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl' Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl # set script_dir [file dirname [file normalize [info script]]] # set fpga_dir [file normalize [file join $script_dir ../..]] # proc getenv_default {name default} { # if {[info exists ::env($name)] && $::env($name) ne ""} { # return $::env($name) # } # return $default # } # proc region_end {offset file} { # return [expr {$offset + [file size $file]}] # } # set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]] # set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]] # set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]] # set bin_file [file normalize [getenv_default FLASH_BIN [file join $fpga_dir out flash genesys2_rocket.bin]]] # set flash_size_mb [getenv_default FLASH_SIZE_MB 32] # set flash_interface [getenv_default FLASH_INTERFACE SPIx4] # set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000] # set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000] # file mkdir [file dirname $mcs_file] # file mkdir [file dirname $bin_file] # if {![file exists $bit_file]} { # error "Bitstream not found: $bit_file" # } # if {![file exists $app_image]} { # error "Application flash image not found: $app_image" # } # set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}] # set bitstream_end [region_end $bitstream_offset $bit_file] # set app_end [region_end $app_flash_offset $app_image] # if {$bitstream_end > $flash_size_bytes} { # error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes] # } # if {$app_end > $flash_size_bytes} { # error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes] # } # if {$bitstream_offset < $app_end && $app_flash_offset < $bitstream_end} { # error [format "Bitstream/app flash regions overlap: bit=[0x%08x,0x%08x) app=[0x%08x,0x%08x)" \ # $bitstream_offset $bitstream_end $app_flash_offset $app_end] # } # puts "Generating flash MCS:" Generating flash MCS: # puts " bitstream: $bit_file @ $bitstream_offset" bitstream: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit @ 0x00000000 # puts " app image: $app_image @ $app_flash_offset" app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin @ 0x01800000 # puts " size/interface: ${flash_size_mb}MiB $flash_interface" size/interface: 32MiB SPIx4 # puts [format " flash size: 0x%08x bytes" $flash_size_bytes] flash size: 0x02000000 bytes # puts [format " bitstream end: 0x%08x" $bitstream_end] bitstream end: 0x00ae9e20 # puts [format " app end: 0x%08x" $app_end] app end: 0x018134a0 # write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \ # -loadbit "up $bitstream_offset $bit_file" \ # -loaddata "up $app_flash_offset $app_image" \ # $mcs_file Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs Creating config memory files... Creating bitstream load up from address 0x00000000 Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit Creating bitstream load up from address 0x01800000 Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm =================================== Configuration Memory information =================================== File Format MCS Interface SPIX4 Size 32M Start Address 0x00000000 End Address 0x01FFFFFF Addr1 Addr2 Date File(s) 0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit 0x01800000 0x0181349F Jul 11 11:10:56 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin 0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. write_cfgmem completed successfully # write_cfgmem -force -format BIN -size $flash_size_mb -interface $flash_interface \ # -loadbit "up $bitstream_offset $bit_file" \ # -loaddata "up $app_flash_offset $app_image" \ # $bin_file Command: write_cfgmem -force -format BIN -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin Creating config memory files... Creating bitstream load up from address 0x00000000 Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit Creating bitstream load up from address 0x01800000 Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm =================================== Configuration Memory information =================================== File Format BIN Interface SPIX4 Size 32M Start Address 0x00000000 End Address 0x01FFFFFF Addr1 Addr2 Date File(s) 0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit 0x01800000 0x0181349F Jul 11 11:10:56 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin 0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. write_cfgmem completed successfully # puts "Wrote $mcs_file" Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs # puts "Wrote $bin_file" Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 11:11:02 2026...