#----------------------------------------------------------- # Vivado v2025.2 (64-bit) # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 # SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 # Start of session at: Sat Jul 11 00:16:14 2026 # Process ID : 90489 # Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs # Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl # Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.log # Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash_regions.jou # Running On : onur # Platform : Ubuntu # Operating System : Ubuntu 22.04.5 LTS # Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor # CPU Frequency : 4199.910 MHz # CPU Physical cores : 12 # CPU Logical cores : 12 # Host memory : 22112 MB # Swap memory : 2147 MB # Total Virtual : 24260 MB # Available Virtual : 20488 MB #----------------------------------------------------------- Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl' Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash_regions.tcl # set script_dir [file dirname [file normalize [info script]]] # set fpga_dir [file normalize [file join $script_dir ../..]] # proc getenv_default {name default} { # if {[info exists ::env($name)] && $::env($name) ne ""} { # return $::env($name) # } # return $default # } # proc region_end {offset file} { # return [expr {$offset + [file size $file]}] # } # set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]] # set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]] # set bitstream_mcs [file normalize [getenv_default BITSTREAM_MCS [file join $fpga_dir out flash regions bitstream.mcs]]] # set app_mcs [file normalize [getenv_default APP_MCS [file join $fpga_dir out flash regions app.mcs]]] # set flash_size_mb [getenv_default FLASH_SIZE_MB 32] # set flash_interface [getenv_default FLASH_INTERFACE SPIx4] # set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000] # set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000] # set region_names [split [getenv_default FLASH_REGION_NAMES "bitstream;app"] ";"] # set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}] # foreach region $region_names { # if {$region eq ""} { # continue # } elseif {$region eq "bitstream"} { # if {![file exists $bit_file]} { # error "Bitstream not found: $bit_file" # } # set bitstream_end [region_end $bitstream_offset $bit_file] # if {$bitstream_end > $flash_size_bytes} { # error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes] # } # if {$bitstream_end > $app_flash_offset} { # error [format "Bitstream region crosses APP_FLASH_OFFSET: bit_end=0x%08x app_offset=0x%08x" \ # $bitstream_end $app_flash_offset] # } # file mkdir [file dirname $bitstream_mcs] # puts "Generating bitstream region MCS:" # puts " bitstream: $bit_file @ $bitstream_offset" # puts [format " flash size: 0x%08x bytes" $flash_size_bytes] # puts [format " bitstream end: 0x%08x" $bitstream_end] # write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \ # -loadbit "up $bitstream_offset $bit_file" \ # $bitstream_mcs # puts "Wrote $bitstream_mcs" # } elseif {$region eq "app"} { # if {![file exists $app_image]} { # error "Application flash image not found: $app_image" # } # set app_end [region_end $app_flash_offset $app_image] # if {$app_end > $flash_size_bytes} { # error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes] # } # file mkdir [file dirname $app_mcs] # puts "Generating app region MCS:" # puts " app image: $app_image @ $app_flash_offset" # puts [format " flash size: 0x%08x bytes" $flash_size_bytes] # puts [format " app end: 0x%08x" $app_end] # write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \ # -loaddata "up $app_flash_offset $app_image" \ # $app_mcs # puts "Wrote $app_mcs" # } else { # error "Unknown flash region: $region" # } # } Generating app region MCS: app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin @ 0x01800000 flash size: 0x02000000 bytes app end: 0x01814648 Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs Creating config memory files... Creating bitstream load up from address 0x01800000 Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.prm =================================== Configuration Memory information =================================== File Format MCS Interface SPIX4 Size 32M Start Address 0x00000000 End Address 0x01FFFFFF Addr1 Addr2 Date File(s) 0x01800000 0x01814647 Jul 11 00:16:13 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin 0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. write_cfgmem completed successfully Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/regions/app.mcs INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 00:16:16 2026...