// Generated by CIRCT firtool-1.151.0
module AsyncValidSync(
  input  io_in,
  output io_out,
  input  clock,
         reset
);

  AsyncResetSynchronizerShiftReg_w1_d3_i0_1 io_out_source_valid_0 (
    .clock (clock),
    .reset (reset),
    .io_d  (io_in),
    .io_q  (io_out)
  );
endmodule