// Generated by CIRCT firtool-1.151.0
module HellaCacheArbiter(
  input         clock,
  output        io_requestor_0_req_ready,
  input         io_requestor_0_req_valid,
  input  [33:0] io_requestor_0_req_bits_addr,
  input  [6:0]  io_requestor_0_req_bits_tag,
  input  [4:0]  io_requestor_0_req_bits_cmd,
  input  [1:0]  io_requestor_0_req_bits_size,
  input         io_requestor_0_req_bits_signed,
                io_requestor_0_s1_kill,
  input  [63:0] io_requestor_0_s1_data_data,
  output        io_requestor_0_s2_nack,
                io_requestor_0_resp_valid,
  output [6:0]  io_requestor_0_resp_bits_tag,
  output [1:0]  io_requestor_0_resp_bits_size,
  output [63:0] io_requestor_0_resp_bits_data,
  output        io_requestor_0_resp_bits_replay,
                io_requestor_0_resp_bits_has_data,
  output [63:0] io_requestor_0_resp_bits_data_word_bypass,
  output        io_requestor_0_replay_next,
                io_requestor_0_s2_xcpt_ma_ld,
                io_requestor_0_s2_xcpt_ma_st,
                io_requestor_0_s2_xcpt_pf_ld,
                io_requestor_0_s2_xcpt_pf_st,
                io_requestor_0_s2_xcpt_ae_ld,
                io_requestor_0_s2_xcpt_ae_st,
                io_requestor_0_ordered,
                io_requestor_0_perf_grant,
                io_requestor_1_req_ready,
  input         io_requestor_1_req_valid,
  input  [33:0] io_requestor_1_req_bits_addr,
  input  [4:0]  io_requestor_1_req_bits_cmd,
  input  [1:0]  io_requestor_1_req_bits_size,
  input         io_requestor_1_s1_kill,
  input  [63:0] io_requestor_1_s1_data_data,
  input  [7:0]  io_requestor_1_s1_data_mask,
  output        io_requestor_1_s2_nack,
                io_requestor_1_resp_valid,
  output [63:0] io_requestor_1_resp_bits_data_raw,
  input         io_mem_req_ready,
  output        io_mem_req_valid,
  output [33:0] io_mem_req_bits_addr,
  output [6:0]  io_mem_req_bits_tag,
  output [4:0]  io_mem_req_bits_cmd,
  output [1:0]  io_mem_req_bits_size,
  output        io_mem_req_bits_signed,
  output [1:0]  io_mem_req_bits_dprv,
  output        io_mem_req_bits_no_xcpt,
                io_mem_s1_kill,
  output [63:0] io_mem_s1_data_data,
  output [7:0]  io_mem_s1_data_mask,
  input         io_mem_s2_nack,
                io_mem_resp_valid,
  input  [6:0]  io_mem_resp_bits_tag,
  input  [1:0]  io_mem_resp_bits_size,
  input  [63:0] io_mem_resp_bits_data,
  input         io_mem_resp_bits_replay,
                io_mem_resp_bits_has_data,
  input  [63:0] io_mem_resp_bits_data_word_bypass,
                io_mem_resp_bits_data_raw,
  input         io_mem_replay_next,
                io_mem_s2_xcpt_ma_ld,
                io_mem_s2_xcpt_ma_st,
                io_mem_s2_xcpt_pf_ld,
                io_mem_s2_xcpt_pf_st,
                io_mem_s2_xcpt_ae_ld,
                io_mem_s2_xcpt_ae_st,
                io_mem_ordered,
                io_mem_perf_grant
);

  reg s1_id;
  reg s2_id;
  always @(posedge clock) begin
    s1_id <= ~io_requestor_0_req_valid;
    s2_id <= s1_id;
  end // always @(posedge)
  assign io_requestor_0_req_ready = io_mem_req_ready;
  assign io_requestor_0_s2_nack = io_mem_s2_nack & ~s2_id;
  assign io_requestor_0_resp_valid = io_mem_resp_valid & ~(io_mem_resp_bits_tag[0]);
  assign io_requestor_0_resp_bits_tag = {1'h0, io_mem_resp_bits_tag[6:1]};
  assign io_requestor_0_resp_bits_size = io_mem_resp_bits_size;
  assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data;
  assign io_requestor_0_resp_bits_replay = io_mem_resp_bits_replay;
  assign io_requestor_0_resp_bits_has_data = io_mem_resp_bits_has_data;
  assign io_requestor_0_resp_bits_data_word_bypass = io_mem_resp_bits_data_word_bypass;
  assign io_requestor_0_replay_next = io_mem_replay_next;
  assign io_requestor_0_s2_xcpt_ma_ld = io_mem_s2_xcpt_ma_ld;
  assign io_requestor_0_s2_xcpt_ma_st = io_mem_s2_xcpt_ma_st;
  assign io_requestor_0_s2_xcpt_pf_ld = io_mem_s2_xcpt_pf_ld;
  assign io_requestor_0_s2_xcpt_pf_st = io_mem_s2_xcpt_pf_st;
  assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld;
  assign io_requestor_0_s2_xcpt_ae_st = io_mem_s2_xcpt_ae_st;
  assign io_requestor_0_ordered = io_mem_ordered;
  assign io_requestor_0_perf_grant = io_mem_perf_grant;
  assign io_requestor_1_req_ready = io_mem_req_ready & ~io_requestor_0_req_valid;
  assign io_requestor_1_s2_nack = io_mem_s2_nack & s2_id;
  assign io_requestor_1_resp_valid = io_mem_resp_valid & io_mem_resp_bits_tag[0];
  assign io_requestor_1_resp_bits_data_raw = io_mem_resp_bits_data_raw;
  assign io_mem_req_valid = io_requestor_0_req_valid | io_requestor_1_req_valid;
  assign io_mem_req_bits_addr =
    io_requestor_0_req_valid
      ? io_requestor_0_req_bits_addr
      : io_requestor_1_req_bits_addr;
  assign io_mem_req_bits_tag =
    io_requestor_0_req_valid ? {io_requestor_0_req_bits_tag[5:0], 1'h0} : 7'h1;
  assign io_mem_req_bits_cmd =
    io_requestor_0_req_valid ? io_requestor_0_req_bits_cmd : io_requestor_1_req_bits_cmd;
  assign io_mem_req_bits_size =
    io_requestor_0_req_valid
      ? io_requestor_0_req_bits_size
      : io_requestor_1_req_bits_size;
  assign io_mem_req_bits_signed =
    io_requestor_0_req_valid & io_requestor_0_req_bits_signed;
  assign io_mem_req_bits_dprv = {2{io_requestor_0_req_valid}};
  assign io_mem_req_bits_no_xcpt = ~io_requestor_0_req_valid;
  assign io_mem_s1_kill = s1_id ? io_requestor_1_s1_kill : io_requestor_0_s1_kill;
  assign io_mem_s1_data_data =
    s1_id ? io_requestor_1_s1_data_data : io_requestor_0_s1_data_data;
  assign io_mem_s1_data_mask = s1_id ? io_requestor_1_s1_data_mask : 8'h0;
endmodule