// Generated by CIRCT firtool-1.151.0
module LevelGateway(
  input  clock,
         reset,
         io_interrupt,
  output io_plic_valid,
  input  io_plic_ready,
         io_plic_complete
);

  reg inFlight;
  always @(posedge clock) begin
    if (reset)
      inFlight <= 1'h0;
    else
      inFlight <= ~io_plic_complete & (io_interrupt & io_plic_ready | inFlight);
  end // always @(posedge)
  assign io_plic_valid = io_interrupt & ~inFlight;
endmodule