TARGET := max2771_spi_test
APP_SRCS := main.c
BSP_SRCS := init.c uart.c max2771_spi.c

# Direct builds default to Genesys 2. Board flows override these values.
BSP_UART_CLOCK_HZ ?= 50000000
BSP_CLINT_TIMEBASE_HZ ?= 500000
BSP_MAX2771_INPUT_CLOCK_HZ ?= $(BSP_UART_CLOCK_HZ)

include ../common/app.mk

CFLAGS += -DBSP_MAX2771_INPUT_CLOCK_HZ=$(BSP_MAX2771_INPUT_CLOCK_HZ)UL