// Generated by CIRCT firtool-1.151.0
module IntSyncCrossingSource_n1x1(
  input  clock,
         reset,
         auto_in_0,
  output auto_out_sync_0
);

  AsyncResetRegVec_w1_i0 reg_0 (
    .clock (clock),
    .reset (reset),
    .io_d  (auto_in_0),
    .io_q  (auto_out_sync_0)
  );
endmodule