// Generated by CIRCT firtool-1.151.0
module MulDiv(
  input         clock,
                reset,
  output        io_req_ready,
  input         io_req_valid,
  input  [4:0]  io_req_bits_fn,
  input         io_req_bits_dw,
  input  [63:0] io_req_bits_in1,
                io_req_bits_in2,
  input  [4:0]  io_req_bits_tag,
  input         io_kill,
                io_resp_ready,
  output        io_resp_valid,
  output [63:0] io_resp_bits_data,
  output [4:0]  io_resp_bits_tag
);

  reg  [2:0]   state;
  reg          req_dw;
  reg  [4:0]   req_tag;
  reg  [6:0]   count;
  reg          neg_out;
  reg          isHi;
  reg          resHi;
  reg  [64:0]  divisor;
  reg  [129:0] remainder;
  wire [63:0]  result = resHi ? remainder[128:65] : remainder[63:0];
  wire [31:0]  loOut = req_dw | state[0] ? result[31:0] : result[63:32];
  wire         io_resp_valid_0 = state == 3'h6 | (&state);
  wire         io_req_ready_0 = state == 3'h0;
  always @(posedge clock) begin
    automatic logic [2:0]  decoded_invInputs = ~(io_req_bits_fn[2:0]);
    automatic logic        decoded_andMatrixOutputs_2_2 =
      &{decoded_invInputs[1], decoded_invInputs[2]};
    automatic logic        cmdHi;
    automatic logic        lhs_sign;
    automatic logic        rhs_sign;
    automatic logic [64:0] _subtractor_T_1;
    automatic logic        _GEN;
    automatic logic        _GEN_0;
    automatic logic        _GEN_1;
    automatic logic        _GEN_2;
    automatic logic        _GEN_3;
    automatic logic        _GEN_4;
    automatic logic        _GEN_5;
    cmdHi = |{&{io_req_bits_fn[0], decoded_invInputs[2]}, io_req_bits_fn[1]};
    lhs_sign =
      (|{decoded_invInputs[0], decoded_andMatrixOutputs_2_2})
      & (io_req_bits_dw ? io_req_bits_in1[63] : io_req_bits_in1[31]);
    rhs_sign =
      (|{decoded_andMatrixOutputs_2_2, &{decoded_invInputs[0], io_req_bits_fn[2]}})
      & (io_req_bits_dw ? io_req_bits_in2[63] : io_req_bits_in2[31]);
    _subtractor_T_1 = remainder[128:64] - divisor;
    _GEN = state == 3'h1;
    _GEN_0 = state == 3'h5;
    _GEN_1 = state == 3'h2;
    _GEN_2 = _GEN_1 & count == 7'h3F;
    _GEN_3 = state == 3'h3;
    _GEN_4 = count == 7'h40;
    _GEN_5 = io_req_ready_0 & io_req_valid;
    if (reset)
      state <= 3'h0;
    else if (_GEN_5)
      state <= decoded_invInputs[2] ? 3'h2 : {1'h0, ~(lhs_sign | rhs_sign), 1'h1};
    else if (io_resp_ready & io_resp_valid_0 | io_kill)
      state <= 3'h0;
    else if (_GEN_3 & _GEN_4)
      state <= {1'h1, ~neg_out, 1'h1};
    else if (_GEN_2)
      state <= 3'h6;
    else if (_GEN_0)
      state <= 3'h7;
    else if (_GEN)
      state <= 3'h3;
    if (_GEN_5) begin
      req_dw <= io_req_bits_dw;
      req_tag <= io_req_bits_tag;
      count <= {1'h0, decoded_invInputs[2] & ~io_req_bits_dw, 5'h0};
      isHi <= cmdHi;
      divisor <=
        {rhs_sign,
         io_req_bits_dw ? io_req_bits_in2[63:32] : {32{rhs_sign}},
         io_req_bits_in2[31:0]};
      remainder <=
        {66'h0,
         io_req_bits_dw ? io_req_bits_in1[63:32] : {32{lhs_sign}},
         io_req_bits_in1[31:0]};
    end
    else begin
      if (_GEN_3) begin
        count <= count + 7'h1;
        remainder <=
          {1'h0,
           _subtractor_T_1[64] ? remainder[127:64] : _subtractor_T_1[63:0],
           remainder[63:0],
           ~(_subtractor_T_1[64])};
      end
      else if (_GEN_1) begin
        automatic logic [65:0] _prod_T_4 =
          {{65{remainder[64]}}, remainder[0]} * {divisor[64], divisor}
          + {remainder[129], remainder[129:65]};
        count <= count + 7'h1;
        remainder <=
          {_prod_T_4[65:1], count == 7'h3E & neg_out, _prod_T_4[0], remainder[63:1]};
      end
      else if (_GEN_0 | _GEN & remainder[63])
        remainder <= {66'h0, 64'h0 - result};
      if (_GEN & divisor[63])
        divisor <= _subtractor_T_1;
    end
    neg_out <=
      _GEN_5
        ? (cmdHi ? lhs_sign : lhs_sign != rhs_sign)
        : ~(_GEN_3 & count == 7'h0 & ~(_subtractor_T_1[64]) & ~isHi) & neg_out;
    resHi <= ~_GEN_5 & (_GEN_3 & _GEN_4 | _GEN_2 ? isHi : ~_GEN_0 & resHi);
  end // always @(posedge)
  assign io_req_ready = io_req_ready_0;
  assign io_resp_valid = io_resp_valid_0;
  assign io_resp_bits_data = {req_dw ? result[63:32] : {32{loOut[31]}}, loOut};
  assign io_resp_bits_tag = req_tag;
endmodule