// Generated by CIRCT firtool-1.151.0
module PLICClockSinkDomain(
  input         auto_plic_int_in_0,
                auto_plic_int_in_1,
                auto_plic_int_in_2,
                auto_plic_int_in_3,
                auto_plic_int_in_4,
                auto_plic_int_in_5,
                auto_plic_int_in_6,
                auto_plic_int_in_7,
                auto_plic_int_in_8,
                auto_plic_int_in_9,
                auto_plic_int_in_10,
  output        auto_plic_in_a_ready,
  input         auto_plic_in_a_valid,
  input  [2:0]  auto_plic_in_a_bits_opcode,
  input  [1:0]  auto_plic_in_a_bits_size,
  input  [5:0]  auto_plic_in_a_bits_source,
  input  [27:0] auto_plic_in_a_bits_address,
  input  [7:0]  auto_plic_in_a_bits_mask,
  input  [63:0] auto_plic_in_a_bits_data,
  input         auto_plic_in_d_ready,
  output        auto_plic_in_d_valid,
  output [2:0]  auto_plic_in_d_bits_opcode,
  output [1:0]  auto_plic_in_d_bits_size,
  output [5:0]  auto_plic_in_d_bits_source,
  output [63:0] auto_plic_in_d_bits_data,
  output        auto_int_in_clock_xing_out_sync_0,
  input         auto_clock_in_clock,
                auto_clock_in_reset
);

  wire _plic_auto_int_out_0;
  TLPLIC plic (
    .clock                  (auto_clock_in_clock),
    .reset                  (auto_clock_in_reset),
    .auto_int_in_0          (auto_plic_int_in_0),
    .auto_int_in_1          (auto_plic_int_in_1),
    .auto_int_in_2          (auto_plic_int_in_2),
    .auto_int_in_3          (auto_plic_int_in_3),
    .auto_int_in_4          (auto_plic_int_in_4),
    .auto_int_in_5          (auto_plic_int_in_5),
    .auto_int_in_6          (auto_plic_int_in_6),
    .auto_int_in_7          (auto_plic_int_in_7),
    .auto_int_in_8          (auto_plic_int_in_8),
    .auto_int_in_9          (auto_plic_int_in_9),
    .auto_int_in_10         (auto_plic_int_in_10),
    .auto_int_out_0         (_plic_auto_int_out_0),
    .auto_in_a_ready        (auto_plic_in_a_ready),
    .auto_in_a_valid        (auto_plic_in_a_valid),
    .auto_in_a_bits_opcode  (auto_plic_in_a_bits_opcode),
    .auto_in_a_bits_size    (auto_plic_in_a_bits_size),
    .auto_in_a_bits_source  (auto_plic_in_a_bits_source),
    .auto_in_a_bits_address (auto_plic_in_a_bits_address),
    .auto_in_a_bits_mask    (auto_plic_in_a_bits_mask),
    .auto_in_a_bits_data    (auto_plic_in_a_bits_data),
    .auto_in_d_ready        (auto_plic_in_d_ready),
    .auto_in_d_valid        (auto_plic_in_d_valid),
    .auto_in_d_bits_opcode  (auto_plic_in_d_bits_opcode),
    .auto_in_d_bits_size    (auto_plic_in_d_bits_size),
    .auto_in_d_bits_source  (auto_plic_in_d_bits_source),
    .auto_in_d_bits_data    (auto_plic_in_d_bits_data)
  );
  IntSyncCrossingSource_n1x1 intsource (
    .clock           (auto_clock_in_clock),
    .reset           (auto_clock_in_reset),
    .auto_in_0       (_plic_auto_int_out_0),
    .auto_out_sync_0 (auto_int_in_clock_xing_out_sync_0)
  );
endmodule