// Generated by CIRCT firtool-1.151.0
module PLICFanIn(
  input  [2:0]  io_prio_0,
                io_prio_1,
                io_prio_2,
                io_prio_3,
                io_prio_4,
                io_prio_5,
                io_prio_6,
                io_prio_7,
                io_prio_8,
                io_prio_9,
                io_prio_10,
  input  [10:0] io_ip,
  output [3:0]  io_dev,
  output [2:0]  io_max
);

  wire [3:0] effectivePriority_1 = {io_ip[0], io_prio_0};
  wire [3:0] effectivePriority_2 = {io_ip[1], io_prio_1};
  wire [3:0] effectivePriority_3 = {io_ip[2], io_prio_2};
  wire [3:0] effectivePriority_4 = {io_ip[3], io_prio_3};
  wire [3:0] effectivePriority_5 = {io_ip[4], io_prio_4};
  wire [3:0] effectivePriority_6 = {io_ip[5], io_prio_5};
  wire [3:0] effectivePriority_7 = {io_ip[6], io_prio_6};
  wire [3:0] effectivePriority_8 = {io_ip[7], io_prio_7};
  wire [3:0] effectivePriority_9 = {io_ip[8], io_prio_8};
  wire [3:0] effectivePriority_10 = {io_ip[9], io_prio_9};
  wire [3:0] effectivePriority_11 = {io_ip[10], io_prio_10};
  wire [3:0] left_left_left_1 = effectivePriority_1 < 4'h9 ? 4'h8 : effectivePriority_1;
  wire [3:0] left_left_right_1 =
    effectivePriority_2 >= effectivePriority_3
      ? effectivePriority_2
      : effectivePriority_3;
  wire       _left_left_T = left_left_left_1 >= left_left_right_1;
  wire [3:0] left_left_1 = _left_left_T ? left_left_left_1 : left_left_right_1;
  wire [3:0] left_right_left_1 =
    effectivePriority_4 >= effectivePriority_5
      ? effectivePriority_4
      : effectivePriority_5;
  wire [3:0] left_right_right_1 =
    effectivePriority_6 >= effectivePriority_7
      ? effectivePriority_6
      : effectivePriority_7;
  wire       _left_right_T = left_right_left_1 >= left_right_right_1;
  wire [3:0] left_right_1 = _left_right_T ? left_right_left_1 : left_right_right_1;
  wire       _left_T = left_left_1 >= left_right_1;
  wire [3:0] left_1 = _left_T ? left_left_1 : left_right_1;
  wire [3:0] right_left_1 =
    effectivePriority_8 >= effectivePriority_9
      ? effectivePriority_8
      : effectivePriority_9;
  wire [3:0] right_right_1 =
    effectivePriority_10 >= effectivePriority_11
      ? effectivePriority_10
      : effectivePriority_11;
  wire       _right_T = right_left_1 >= right_right_1;
  wire [3:0] right_1 = _right_T ? right_left_1 : right_right_1;
  wire       _GEN = left_1 >= right_1;
  assign io_dev =
    _GEN
      ? {1'h0,
         _left_T
           ? {1'h0,
              _left_left_T
                ? {1'h0, effectivePriority_1 > 4'h8}
                : {1'h1, effectivePriority_2 < effectivePriority_3}}
           : {1'h1,
              _left_right_T
                ? {1'h0, effectivePriority_4 < effectivePriority_5}
                : {1'h1, effectivePriority_6 < effectivePriority_7}}}
      : {2'h2,
         _right_T
           ? {1'h0, effectivePriority_8 < effectivePriority_9}
           : {1'h1, effectivePriority_10 < effectivePriority_11}};
  assign io_max = _GEN ? left_1[2:0] : right_1[2:0];
endmodule