// Generated by CIRCT firtool-1.151.0
module TLBusBypassBar(
  input         clock,
                reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [8:0]  auto_in_a_bits_address,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
                auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_1_a_ready,
  output        auto_out_1_a_valid,
  output [2:0]  auto_out_1_a_bits_opcode,
  output [8:0]  auto_out_1_a_bits_address,
  output [31:0] auto_out_1_a_bits_data,
  output        auto_out_1_d_ready,
  input         auto_out_1_d_valid,
  input  [2:0]  auto_out_1_d_bits_opcode,
  input         auto_out_1_d_bits_denied,
  input  [31:0] auto_out_1_d_bits_data,
  input         auto_out_1_d_bits_corrupt,
                auto_out_0_a_ready,
  output        auto_out_0_a_valid,
  output [2:0]  auto_out_0_a_bits_opcode,
  output        auto_out_0_d_ready,
  input         auto_out_0_d_valid,
  input  [2:0]  auto_out_0_d_bits_opcode,
  input         auto_out_0_d_bits_denied,
                auto_out_0_d_bits_corrupt,
                io_bypass
);

  reg        in_reset;
  reg        bypass_reg;
  wire       bypass = in_reset ? io_bypass : bypass_reg;
  reg  [1:0] flight;
  reg        r_counter;
  reg        r_counter_3;
  reg        stall_counter;
  wire       stall = bypass != io_bypass & ~stall_counter;
  wire       nodeIn_a_ready = ~stall & (bypass ? auto_out_0_a_ready : auto_out_1_a_ready);
  wire       nodeIn_d_valid = bypass ? auto_out_0_d_valid : auto_out_1_d_valid;
  wire [1:0] nodeIn_d_bits_opcode =
    bypass ? auto_out_0_d_bits_opcode[2:1] : auto_out_1_d_bits_opcode[2:1];
  always @(posedge clock) begin
    automatic logic       r_3;
    automatic logic       d_dec;
    automatic logic [1:0] _next_flight_T_10;
    r_3 = nodeIn_a_ready & auto_in_a_valid;
    d_dec = auto_in_d_ready & nodeIn_d_valid;
    _next_flight_T_10 =
      flight
      + {1'h0,
         d_dec & ~r_counter_3 & nodeIn_d_bits_opcode[1] & ~(nodeIn_d_bits_opcode[0])}
      + {1'h0, r_3 & ~r_counter} - {1'h0, d_dec};
    if (reset) begin
      in_reset <= 1'h1;
      flight <= 2'h0;
      r_counter <= 1'h0;
      r_counter_3 <= 1'h0;
      stall_counter <= 1'h0;
    end
    else begin
      in_reset <= 1'h0;
      flight <= _next_flight_T_10;
      r_counter <= (~r_3 | r_counter - 1'h1) & r_counter;
      r_counter_3 <= (~d_dec | r_counter_3 - 1'h1) & r_counter_3;
      stall_counter <= (~r_3 | stall_counter - 1'h1) & stall_counter;
    end
    if (in_reset | _next_flight_T_10 == 2'h0)
      bypass_reg <= io_bypass;
  end // always @(posedge)
  assign auto_in_a_ready = nodeIn_a_ready;
  assign auto_in_d_valid = nodeIn_d_valid;
  assign auto_in_d_bits_denied =
    bypass ? auto_out_0_d_bits_denied : auto_out_1_d_bits_denied;
  assign auto_in_d_bits_data = bypass ? 32'h0 : auto_out_1_d_bits_data;
  assign auto_in_d_bits_corrupt =
    bypass ? auto_out_0_d_bits_corrupt : auto_out_1_d_bits_corrupt;
  assign auto_out_1_a_valid = ~stall & auto_in_a_valid & ~bypass;
  assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode;
  assign auto_out_1_a_bits_address = auto_in_a_bits_address;
  assign auto_out_1_a_bits_data = auto_in_a_bits_data;
  assign auto_out_1_d_ready = auto_in_d_ready & ~bypass;
  assign auto_out_0_a_valid = ~stall & auto_in_a_valid & bypass;
  assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode;
  assign auto_out_0_d_ready = auto_in_d_ready & bypass;
endmodule