// Generated by CIRCT firtool-1.151.0 // Users can define 'PRINTF_COND' to add an extra gate to prints. `ifndef PRINTF_COND_ `ifdef PRINTF_COND `define PRINTF_COND_ (`PRINTF_COND) `else // PRINTF_COND `define PRINTF_COND_ 1 `endif // PRINTF_COND `endif // not def PRINTF_COND_ module TLPLIC( input clock, reset, auto_int_in_0, auto_int_in_1, auto_int_in_2, auto_int_in_3, auto_int_in_4, auto_int_in_5, auto_int_in_6, auto_int_in_7, auto_int_in_8, auto_int_in_9, auto_int_in_10, output auto_int_out_0, auto_in_a_ready, input auto_in_a_valid, input [2:0] auto_in_a_bits_opcode, input [1:0] auto_in_a_bits_size, input [5:0] auto_in_a_bits_source, input [27:0] auto_in_a_bits_address, input [7:0] auto_in_a_bits_mask, input [63:0] auto_in_a_bits_data, input auto_in_d_ready, output auto_in_d_valid, output [2:0] auto_in_d_bits_opcode, output [1:0] auto_in_d_bits_size, output [5:0] auto_in_d_bits_source, output [63:0] auto_in_d_bits_data ); wire out_woready_22; wire _out_wofireMux_T; wire out_backSel_32; wire completer_0; wire [3:0] completerDev; wire claimer_0; wire _out_back_front_q_io_deq_valid; wire _out_back_front_q_io_deq_bits_read; wire [22:0] _out_back_front_q_io_deq_bits_index; wire [63:0] _out_back_front_q_io_deq_bits_data; wire [7:0] _out_back_front_q_io_deq_bits_mask; wire [3:0] _fanin_io_dev; wire [2:0] _fanin_io_max; wire _gateways_gateway_10_io_plic_valid; wire _gateways_gateway_9_io_plic_valid; wire _gateways_gateway_8_io_plic_valid; wire _gateways_gateway_7_io_plic_valid; wire _gateways_gateway_6_io_plic_valid; wire _gateways_gateway_5_io_plic_valid; wire _gateways_gateway_4_io_plic_valid; wire _gateways_gateway_3_io_plic_valid; wire _gateways_gateway_2_io_plic_valid; wire _gateways_gateway_1_io_plic_valid; wire _gateways_gateway_io_plic_valid; reg [2:0] priority_0; reg [2:0] priority_1; reg [2:0] priority_2; reg [2:0] priority_3; reg [2:0] priority_4; reg [2:0] priority_5; reg [2:0] priority_6; reg [2:0] priority_7; reg [2:0] priority_8; reg [2:0] priority_9; reg [2:0] priority_10; reg [2:0] threshold_0; reg pending_0; reg pending_1; reg pending_2; reg pending_3; reg pending_4; reg pending_5; reg pending_6; reg pending_7; reg pending_8; reg pending_9; reg pending_10; reg [6:0] enables_0_0; reg [3:0] enables_0_1; reg [3:0] maxDevs_0; reg [2:0] intnodeOut_0_REG; wire _GEN = claimer_0 & claimer_0 - 1'h1; wire _GEN_0 = completer_0 & completer_0 - 1'h1; wire [15:0] _completedDevs_T = 16'h1 << completerDev; wire [10:0] completedDevs = completer_0 ? _completedDevs_T[11:1] : 11'h0; wire _out_T_17 = {_out_back_front_q_io_deq_bits_index[22:19], _out_back_front_q_io_deq_bits_index[17:11], _out_back_front_q_io_deq_bits_index[8:3]} == 17'h0; wire [31:0] _out_womask_T_22 = {{8{_out_back_front_q_io_deq_bits_mask[7]}}, {8{_out_back_front_q_io_deq_bits_mask[6]}}, {8{_out_back_front_q_io_deq_bits_mask[5]}}, {8{_out_back_front_q_io_deq_bits_mask[4]}}}; assign claimer_0 = _out_wofireMux_T & _out_back_front_q_io_deq_bits_read & out_backSel_32 & _out_T_17 & (|_out_womask_T_22); assign completerDev = _out_back_front_q_io_deq_bits_data[35:32]; `ifndef SYNTHESIS always @(posedge clock) begin if ((`PRINTF_COND_) & ~reset & _GEN) $fwrite(32'h80000002, "Assertion failed\n at Plic.scala:249 assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot\n"); if ((`PRINTF_COND_) & ~reset & _GEN_0) $fwrite(32'h80000002, "Assertion failed\n at Plic.scala:266 assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot\n"); end // always @(posedge) `endif // not def SYNTHESIS wire [11:0] _out_completer_0_T = {enables_0_1, enables_0_0, 1'h0} >> completerDev; assign completer_0 = out_woready_22 & (&_out_womask_T_22) & _out_completer_0_T[0]; wire [5:0] out_oindex = {_out_back_front_q_io_deq_bits_index[18], _out_back_front_q_io_deq_bits_index[10:9], _out_back_front_q_io_deq_bits_index[2:0]}; wire [63:0] _out_backSel_T = 64'h1 << {58'h0, _out_back_front_q_io_deq_bits_index[18], _out_back_front_q_io_deq_bits_index[10:9], _out_back_front_q_io_deq_bits_index[2:0]}; assign out_backSel_32 = _out_backSel_T[32]; assign _out_wofireMux_T = _out_back_front_q_io_deq_valid & auto_in_d_ready; wire _out_wofireMux_T_2 = _out_wofireMux_T & ~_out_back_front_q_io_deq_bits_read; wire out_woready_3 = _out_wofireMux_T_2 & _out_backSel_T[1] & _out_T_17; wire out_woready_17 = _out_wofireMux_T_2 & _out_backSel_T[2] & _out_T_17; wire out_woready_19 = _out_wofireMux_T_2 & _out_backSel_T[3] & _out_T_17; wire out_woready_24 = _out_wofireMux_T_2 & _out_backSel_T[4] & _out_T_17; wire out_woready_1 = _out_wofireMux_T_2 & _out_backSel_T[5] & _out_T_17; wire out_woready_27 = _out_wofireMux_T_2 & _out_backSel_T[16] & _out_T_17; assign out_woready_22 = _out_wofireMux_T_2 & out_backSel_32 & _out_T_17; wire _out_out_bits_data_T_9 = out_oindex == 6'h0; always @(posedge clock) begin if (~reset) begin end if (_out_wofireMux_T_2 & _out_backSel_T[0] & _out_T_17 & _out_back_front_q_io_deq_bits_mask[4]) priority_0 <= _out_back_front_q_io_deq_bits_data[34:32]; if (out_woready_3 & _out_back_front_q_io_deq_bits_mask[0]) priority_1 <= _out_back_front_q_io_deq_bits_data[2:0]; if (out_woready_3 & _out_back_front_q_io_deq_bits_mask[4]) priority_2 <= _out_back_front_q_io_deq_bits_data[34:32]; if (out_woready_17 & _out_back_front_q_io_deq_bits_mask[0]) priority_3 <= _out_back_front_q_io_deq_bits_data[2:0]; if (out_woready_17 & _out_back_front_q_io_deq_bits_mask[4]) priority_4 <= _out_back_front_q_io_deq_bits_data[34:32]; if (out_woready_19 & _out_back_front_q_io_deq_bits_mask[0]) priority_5 <= _out_back_front_q_io_deq_bits_data[2:0]; if (out_woready_19 & _out_back_front_q_io_deq_bits_mask[4]) priority_6 <= _out_back_front_q_io_deq_bits_data[34:32]; if (out_woready_24 & _out_back_front_q_io_deq_bits_mask[0]) priority_7 <= _out_back_front_q_io_deq_bits_data[2:0]; if (out_woready_24 & _out_back_front_q_io_deq_bits_mask[4]) priority_8 <= _out_back_front_q_io_deq_bits_data[34:32]; if (out_woready_1 & _out_back_front_q_io_deq_bits_mask[0]) priority_9 <= _out_back_front_q_io_deq_bits_data[2:0]; if (out_woready_1 & _out_back_front_q_io_deq_bits_mask[4]) priority_10 <= _out_back_front_q_io_deq_bits_data[34:32]; if (out_woready_22 & _out_back_front_q_io_deq_bits_mask[0]) threshold_0 <= _out_back_front_q_io_deq_bits_data[2:0]; if (out_woready_27 & _out_back_front_q_io_deq_bits_mask[0]) enables_0_0 <= _out_back_front_q_io_deq_bits_data[7:1]; if (out_woready_27 & _out_back_front_q_io_deq_bits_mask[1]) enables_0_1 <= _out_back_front_q_io_deq_bits_data[11:8]; maxDevs_0 <= _fanin_io_dev; intnodeOut_0_REG <= _fanin_io_max; if (reset) begin pending_0 <= 1'h0; pending_1 <= 1'h0; pending_2 <= 1'h0; pending_3 <= 1'h0; pending_4 <= 1'h0; pending_5 <= 1'h0; pending_6 <= 1'h0; pending_7 <= 1'h0; pending_8 <= 1'h0; pending_9 <= 1'h0; pending_10 <= 1'h0; end else begin automatic logic [15:0] _claimedDevs_T = 16'h1 << (claimer_0 ? maxDevs_0 : 4'h0); if (_claimedDevs_T[1] | _gateways_gateway_io_plic_valid) pending_0 <= ~(_claimedDevs_T[1]); if (_claimedDevs_T[2] | _gateways_gateway_1_io_plic_valid) pending_1 <= ~(_claimedDevs_T[2]); if (_claimedDevs_T[3] | _gateways_gateway_2_io_plic_valid) pending_2 <= ~(_claimedDevs_T[3]); if (_claimedDevs_T[4] | _gateways_gateway_3_io_plic_valid) pending_3 <= ~(_claimedDevs_T[4]); if (_claimedDevs_T[5] | _gateways_gateway_4_io_plic_valid) pending_4 <= ~(_claimedDevs_T[5]); if (_claimedDevs_T[6] | _gateways_gateway_5_io_plic_valid) pending_5 <= ~(_claimedDevs_T[6]); if (_claimedDevs_T[7] | _gateways_gateway_6_io_plic_valid) pending_6 <= ~(_claimedDevs_T[7]); if (_claimedDevs_T[8] | _gateways_gateway_7_io_plic_valid) pending_7 <= ~(_claimedDevs_T[8]); if (_claimedDevs_T[9] | _gateways_gateway_8_io_plic_valid) pending_8 <= ~(_claimedDevs_T[9]); if (_claimedDevs_T[10] | _gateways_gateway_9_io_plic_valid) pending_9 <= ~(_claimedDevs_T[10]); if (_claimedDevs_T[11] | _gateways_gateway_10_io_plic_valid) pending_10 <= ~(_claimedDevs_T[11]); end end // always @(posedge) LevelGateway gateways_gateway ( .clock (clock), .reset (reset), .io_interrupt (auto_int_in_0), .io_plic_valid (_gateways_gateway_io_plic_valid), .io_plic_ready (~pending_0), .io_plic_complete (completedDevs[0]) ); LevelGateway gateways_gateway_1 ( .clock (clock), .reset (reset), .io_interrupt (auto_int_in_1), .io_plic_valid (_gateways_gateway_1_io_plic_valid), .io_plic_ready (~pending_1), .io_plic_complete (completedDevs[1]) ); LevelGateway gateways_gateway_2 ( .clock (clock), .reset (reset), .io_interrupt (auto_int_in_2), .io_plic_valid (_gateways_gateway_2_io_plic_valid), .io_plic_ready (~pending_2), .io_plic_complete (completedDevs[2]) ); LevelGateway gateways_gateway_3 ( .clock (clock), .reset (reset), .io_interrupt (auto_int_in_3), .io_plic_valid (_gateways_gateway_3_io_plic_valid), .io_plic_ready (~pending_3), .io_plic_complete (completedDevs[3]) ); LevelGateway gateways_gateway_4 ( .clock (clock), .reset (reset), .io_interrupt (auto_int_in_4), .io_plic_valid (_gateways_gateway_4_io_plic_valid), .io_plic_ready (~pending_4), .io_plic_complete (completedDevs[4]) ); LevelGateway gateways_gateway_5 ( .clock (clock), .reset (reset), .io_interrupt (auto_int_in_5), .io_plic_valid (_gateways_gateway_5_io_plic_valid), .io_plic_ready (~pending_5), .io_plic_complete (completedDevs[5]) ); LevelGateway gateways_gateway_6 ( .clock (clock), .reset (reset), .io_interrupt (auto_int_in_6), .io_plic_valid (_gateways_gateway_6_io_plic_valid), .io_plic_ready (~pending_6), .io_plic_complete (completedDevs[6]) ); LevelGateway gateways_gateway_7 ( .clock (clock), .reset (reset), .io_interrupt (auto_int_in_7), .io_plic_valid (_gateways_gateway_7_io_plic_valid), .io_plic_ready (~pending_7), .io_plic_complete (completedDevs[7]) ); LevelGateway gateways_gateway_8 ( .clock (clock), .reset (reset), .io_interrupt (auto_int_in_8), .io_plic_valid (_gateways_gateway_8_io_plic_valid), .io_plic_ready (~pending_8), .io_plic_complete (completedDevs[8]) ); LevelGateway gateways_gateway_9 ( .clock (clock), .reset (reset), .io_interrupt (auto_int_in_9), .io_plic_valid (_gateways_gateway_9_io_plic_valid), .io_plic_ready (~pending_9), .io_plic_complete (completedDevs[9]) ); LevelGateway gateways_gateway_10 ( .clock (clock), .reset (reset), .io_interrupt (auto_int_in_10), .io_plic_valid (_gateways_gateway_10_io_plic_valid), .io_plic_ready (~pending_10), .io_plic_complete (completedDevs[10]) ); PLICFanIn fanin ( .io_prio_0 (priority_0), .io_prio_1 (priority_1), .io_prio_2 (priority_2), .io_prio_3 (priority_3), .io_prio_4 (priority_4), .io_prio_5 (priority_5), .io_prio_6 (priority_6), .io_prio_7 (priority_7), .io_prio_8 (priority_8), .io_prio_9 (priority_9), .io_prio_10 (priority_10), .io_ip ({enables_0_1, enables_0_0} & {pending_10, pending_9, pending_8, pending_7, pending_6, pending_5, pending_4, pending_3, pending_2, pending_1, pending_0}), .io_dev (_fanin_io_dev), .io_max (_fanin_io_max) ); Queue1_RegMapperInput_i23_m8 out_back_front_q ( .clock (clock), .reset (reset), .io_enq_ready (auto_in_a_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_read (auto_in_a_bits_opcode == 3'h4), .io_enq_bits_index (auto_in_a_bits_address[25:3]), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_extra_tlrr_extra_source (auto_in_a_bits_source), .io_enq_bits_extra_tlrr_extra_size (auto_in_a_bits_size), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_out_back_front_q_io_deq_valid), .io_deq_bits_read (_out_back_front_q_io_deq_bits_read), .io_deq_bits_index (_out_back_front_q_io_deq_bits_index), .io_deq_bits_data (_out_back_front_q_io_deq_bits_data), .io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask), .io_deq_bits_extra_tlrr_extra_source (auto_in_d_bits_source), .io_deq_bits_extra_tlrr_extra_size (auto_in_d_bits_size) ); assign auto_int_out_0 = intnodeOut_0_REG > threshold_0; assign auto_in_d_valid = _out_back_front_q_io_deq_valid; assign auto_in_d_bits_opcode = {2'h0, _out_back_front_q_io_deq_bits_read}; assign auto_in_d_bits_data = ~(_out_out_bits_data_T_9 | out_oindex == 6'h1 | out_oindex == 6'h2 | out_oindex == 6'h3 | out_oindex == 6'h4 | out_oindex == 6'h5 | out_oindex == 6'h8 | out_oindex == 6'h10 | out_oindex == 6'h20) | _out_T_17 ? (_out_out_bits_data_T_9 ? {29'h0, priority_0, 32'h0} : out_oindex == 6'h1 ? {29'h0, priority_2, 29'h0, priority_1} : out_oindex == 6'h2 ? {29'h0, priority_4, 29'h0, priority_3} : out_oindex == 6'h3 ? {29'h0, priority_6, 29'h0, priority_5} : out_oindex == 6'h4 ? {29'h0, priority_8, 29'h0, priority_7} : out_oindex == 6'h5 ? {29'h0, priority_10, 29'h0, priority_9} : out_oindex == 6'h8 ? {52'h0, pending_10, pending_9, pending_8, pending_7, pending_6, pending_5, pending_4, pending_3, pending_2, pending_1, pending_0, 1'h0} : out_oindex == 6'h10 ? {52'h0, enables_0_1, enables_0_0, 1'h0} : out_oindex == 6'h20 ? {28'h0, maxDevs_0, 29'h0, threshold_0} : 64'h0) : 64'h0; endmodule