VCU118RocketSystem VCU118RocketSystem (VCU118RocketSystem) , , , , , , , , , , , , , , , , , Interrupt Node , , , , , , , , , Interrupt Node , , Interrupt Node , Interrupt Node , Interrupt Node , , , fpga_gps_domain FPGAGPSClockSinkDomain (VCU118RocketSystem.fpga_gps_domain) , tl2apb TLToAPB (VCU118RocketSystem.fpga_gps_domain.tl2apb) , dev APBGpsBlock (VCU118RocketSystem.fpga_gps_domain.dev) , , , , , , Interrupt Node , max2771_spi_domain MAX2771SPIClockSinkDomain (VCU118RocketSystem.max2771_spi_domain) , dev TLMAX2771SPI (VCU118RocketSystem.max2771_spi_domain.dev) --------------------------------------------- On Input Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] , , , , , , fpga_pmod_spi_domain FPGAPMODSPIClockSinkDomain (VCU118RocketSystem.fpga_pmod_spi_domain) , dev TLFpgaSPI_1 (VCU118RocketSystem.fpga_pmod_spi_domain.dev) --------------------------------------------- On Input Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] , , , , , , fpga_spi_domain FPGASPIClockSinkDomain (VCU118RocketSystem.fpga_spi_domain) , dev TLFpgaSPI (VCU118RocketSystem.fpga_spi_domain.dev) --------------------------------------------- On Input Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] , , , , , , fpga_uart_domain FPGAUARTClockSinkDomain (VCU118RocketSystem.fpga_uart_domain) , dev TLFpgaUART (VCU118RocketSystem.fpga_uart_domain.dev) --------------------------------------------- On Input Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] , , , bootrom_domain bootromClockSinkDomain (VCU118RocketSystem.bootrom_domain) , bootrom TLROM (VCU118RocketSystem.bootrom_domain.bootrom) --------------------------------------------- On Input Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] , nexus_1 BundleBridgeNexus_TraceCoreInterface (VCU118RocketSystem.nexus_1) , nexus BundleBridgeNexus_TraceBundle (VCU118RocketSystem.nexus) , debugCustomXbarOpt DebugCustomXbar (VCU118RocketSystem.debugCustomXbarOpt) , tlDM TLDebugModule (VCU118RocketSystem.tlDM) dmInner TLDebugModuleInnerAsync (VCU118RocketSystem.tlDM.dmInner) dmiXing TLAsyncCrossingSink_a9d32s1k1z2u (VCU118RocketSystem.tlDM.dmInner.dmiXing) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0x3f), AddressSet(0x44, 0x3), AddressSet(0x4c, 0x3), AddressSet(0x58, 0x7), AddressSet(0x60, 0x1f), AddressSet(0x80, 0x7f), AddressSet(0x100, 0xff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0x3f), AddressSet(0x44, 0x3), AddressSet(0x4c, 0x3), AddressSet(0x58, 0x7), AddressSet(0x60, 0x1f), AddressSet(0x80, 0x7f), AddressSet(0x100, 0xff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] , dmInner TLDebugModuleInner (VCU118RocketSystem.tlDM.dmInner.dmInner) , --------------------------------------------- On Input Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] , --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0x3f), AddressSet(0x44, 0x3), AddressSet(0x4c, 0x3), AddressSet(0x58, 0x7), AddressSet(0x60, 0x1f), AddressSet(0x80, 0x7f), AddressSet(0x100, 0xff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] , sb2tlOpt SBToTL (VCU118RocketSystem.tlDM.dmInner.dmInner.sb2tlOpt) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 1 Slave Port MinLatency = 4 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- , dmOuter TLDebugModuleOuterAsync (VCU118RocketSystem.tlDM.dmOuter) Interrupt Node , asource TLAsyncCrossingSource_a9d32s1k1z2u (VCU118RocketSystem.tlDM.dmOuter.asource) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0x3f), AddressSet(0x44, 0x3), AddressSet(0x4c, 0x3), AddressSet(0x58, 0x7), AddressSet(0x60, 0x1f), AddressSet(0x80, 0x7f), AddressSet(0x100, 0xff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 3 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0x3f), AddressSet(0x44, 0x3), AddressSet(0x4c, 0x3), AddressSet(0x58, 0x7), AddressSet(0x60, 0x1f), AddressSet(0x80, 0x7f), AddressSet(0x100, 0xff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] , dmiBypass TLBusBypass (VCU118RocketSystem.tlDM.dmOuter.dmiBypass) , , error TLError_1 (VCU118RocketSystem.tlDM.dmOuter.dmiBypass.error) --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = error Slave Address = List(AddressSet(0x0, 0xffffffffffffffffffffffffffffffff)) supports = acquireT = TransferSizes[1, 4] acquireB = TransferSizes[1, 4] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[1, 4] , bar TLBusBypassBar (VCU118RocketSystem.tlDM.dmOuter.dmiBypass.bar) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = error Slave Address = List(AddressSet(0x0, 0xffffffffffffffffffffffffffffffff)) supports = acquireT = TransferSizes[1, 4] acquireB = TransferSizes[1, 4] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[1, 4] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 3 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0x3f), AddressSet(0x44, 0x3), AddressSet(0x4c, 0x3), AddressSet(0x58, 0x7), AddressSet(0x60, 0x1f), AddressSet(0x80, 0x7f), AddressSet(0x100, 0xff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0x3f), AddressSet(0x44, 0x3), AddressSet(0x4c, 0x3), AddressSet(0x58, 0x7), AddressSet(0x60, 0x1f), AddressSet(0x80, 0x7f), AddressSet(0x100, 0xff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] , intsource IntSyncCrossingSource_n1x1_Registered (VCU118RocketSystem.tlDM.dmOuter.intsource) Interrupt Node , alreadyRegistered:true dmOuter TLDebugModuleOuter (VCU118RocketSystem.tlDM.dmOuter.dmOuter) --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = dmOuter Slave Address = List(AddressSet(0x40, 0x3), AddressSet(0x48, 0x3), AddressSet(0x50, 0x3), AddressSet(0x54, 0x3)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] , Interrupt Node , dmi2tl DMIToTL (VCU118RocketSystem.tlDM.dmOuter.dmi2tl) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0x3f), AddressSet(0x44, 0x3), AddressSet(0x4c, 0x3), AddressSet(0x58, 0x7), AddressSet(0x60, 0x1f), AddressSet(0x80, 0x7f), AddressSet(0x100, 0xff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dmOuter Slave Address = List(AddressSet(0x40, 0x3), AddressSet(0x48, 0x3), AddressSet(0x50, 0x3), AddressSet(0x54, 0x3)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] --------------------------------------------- , dmiXbar TLXbar_dmixbar_i1_o2_a9d32s1k1z2u (VCU118RocketSystem.tlDM.dmOuter.dmiXbar) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0x3f), AddressSet(0x44, 0x3), AddressSet(0x4c, 0x3), AddressSet(0x58, 0x7), AddressSet(0x60, 0x1f), AddressSet(0x80, 0x7f), AddressSet(0x100, 0xff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = dmOuter Slave Address = List(AddressSet(0x40, 0x3), AddressSet(0x48, 0x3), AddressSet(0x50, 0x3), AddressSet(0x54, 0x3)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[4, 4] putFull = TransferSizes[4, 4] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0x3f), AddressSet(0x44, 0x3), AddressSet(0x4c, 0x3), AddressSet(0x58, 0x7), AddressSet(0x60, 0x1f), AddressSet(0x80, 0x7f), AddressSet(0x100, 0xff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dmOuter Slave Address = List(AddressSet(0x40, 0x3), AddressSet(0x48, 0x3), AddressSet(0x50, 0x3), AddressSet(0x54, 0x3)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] , plic_domain PLICClockSinkDomain (VCU118RocketSystem.plic_domain) Interrupt Node , , intsource IntSyncCrossingSource_n1x1_4 (VCU118RocketSystem.plic_domain.intsource) Interrupt Node , alreadyRegistered:false plic TLPLIC (VCU118RocketSystem.plic_domain.plic) Interrupt Node , --------------------------------------------- On Input Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] , clint_domain CLINTClockSinkDomain (VCU118RocketSystem.clint_domain) Interrupt Node , , intsource IntSyncCrossingSource_n1x2 (VCU118RocketSystem.clint_domain.intsource) Interrupt Node , alreadyRegistered:false clint CLINT (VCU118RocketSystem.clint_domain.clint) Interrupt Node , --------------------------------------------- On Input Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] , broadcast BundleBridgeNexus_UInt32_1 (VCU118RocketSystem.broadcast) , tileHartIdNexusNode BundleBridgeNexus_UInt1_2 (VCU118RocketSystem.tileHartIdNexusNode) , xbar_2 IntXbar_i1_o1_2 (VCU118RocketSystem.xbar_2) Interrupt Node , xbar_1 IntXbar_i1_o1_1 (VCU118RocketSystem.xbar_1) Interrupt Node , xbar IntXbar_i1_o1 (VCU118RocketSystem.xbar) Interrupt Node , tile_prci_domain TilePRCIDomain (VCU118RocketSystem.tile_prci_domain) Interrupt Node , Interrupt Node , Interrupt Node , Interrupt Node , Interrupt Node , Interrupt Node , Interrupt Node , Interrupt Node , , , , intsource_2 IntSyncCrossingSource_n1x1_3 (VCU118RocketSystem.tile_prci_domain.intsource_2) Interrupt Node , alreadyRegistered:false intsink_5 IntSyncSyncCrossingSink_n1x1_3 (VCU118RocketSystem.tile_prci_domain.intsink_5) Interrupt Node , sync:0 intsource_1 IntSyncCrossingSource_n1x1_2 (VCU118RocketSystem.tile_prci_domain.intsource_1) Interrupt Node , alreadyRegistered:false intsink_4 IntSyncSyncCrossingSink_n1x1_2 (VCU118RocketSystem.tile_prci_domain.intsink_4) Interrupt Node , sync:0 intsource IntSyncCrossingSource_n1x1_1 (VCU118RocketSystem.tile_prci_domain.intsource) Interrupt Node , alreadyRegistered:false intsink_3 IntSyncSyncCrossingSink_n1x1_1 (VCU118RocketSystem.tile_prci_domain.intsink_3) Interrupt Node , sync:0 intsink_2 IntSyncSyncCrossingSink_n1x1 (VCU118RocketSystem.tile_prci_domain.intsink_2) Interrupt Node , sync:0 intsink_1 IntSyncSyncCrossingSink_n1x2 (VCU118RocketSystem.tile_prci_domain.intsink_1) Interrupt Node , sync:0 intsink IntSyncAsyncCrossingSink_n1x1_1 (VCU118RocketSystem.tile_prci_domain.intsink) Interrupt Node , sync:3 buffer_1 TLBuffer_a32d64s2k1z3u_1 (VCU118RocketSystem.tile_prci_domain.buffer_1) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[4, 8] logical = TransferSizes[4, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 3 Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[4, 8] logical = TransferSizes[4, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , a:BufferParams:2, b:BufferParams:2, c:BufferParams:2, d:BufferParams:2, e:BufferParams:2 buffer TLBuffer_a32d64s1k1z4u_2 (VCU118RocketSystem.tile_prci_domain.buffer) On Output Edge: Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 2 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 4 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] , a:BufferParams:2, b:BufferParams:2, c:BufferParams:2, d:BufferParams:2, e:BufferParams:2 clockNode FixedClockBroadcast_1_1 (VCU118RocketSystem.tile_prci_domain.clockNode) , element_reset_domain HierarchicalElementResetDomain (VCU118RocketSystem.tile_prci_domain.element_reset_domain) , rockettile RocketTile (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile) , Interrupt Node , Interrupt Node , Interrupt Node , Interrupt Node , Interrupt Node , , , , , , , , , , buffer_1 TLBuffer_a32d64s2k1z3u (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.buffer_1) , a:BufferParams:0, b:BufferParams:0, c:BufferParams:0, d:BufferParams:0, e:BufferParams:0 buffer TLBuffer_a32d64s1k1z4u_1 (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.buffer) , a:BufferParams:0, b:BufferParams:0, c:BufferParams:0, d:BufferParams:0, e:BufferParams:0 fragmenter_1 TLFragmenter_1 (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.fragmenter_1) On Output Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,96) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[4, 8] logical = TransferSizes[4, 8] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[4, 8] logical = TransferSizes[4, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , dtim_adapter ScratchpadSlavePort (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.dtim_adapter) --------------------------------------------- On Input Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,96) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[4, 8] logical = TransferSizes[4, 8] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] , widget_1 TLWidthWidget8_6 (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.widget_1) , frontend Frontend (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.frontend) , icache ICache (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.frontend.icache) On Output Edge: Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 4 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- , dcache DCache (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.dcache) , , On Output Edge: Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 4 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- , widget TLWidthWidget8_5 (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.widget) , broadcast_2 BundleBridgeNexus_NoOutput_4 (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.broadcast_2) , nexus_1 BundleBridgeNexus_TraceAux (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.nexus_1) , nexus BundleBridgeNexus_UInt1_1 (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.nexus) , broadcast_1 BundleBridgeNexus_UInt32 (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.broadcast_1) , broadcast BundleBridgeNexus_UInt1 (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.broadcast) , intXbar IntXbar_i3_o1 (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.intXbar) Interrupt Node , tlSlaveXbar TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.tlSlaveXbar) , tlMasterXbar TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u (VCU118RocketSystem.tile_prci_domain.element_reset_domain.rockettile.tlMasterXbar) On Output Edge: Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 4 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 4 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] On Input Edge: Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 4 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] , cbus PeripheryBus_cbus (VCU118RocketSystem.cbus) , , coupler_to_bootrom TLInterconnectCoupler_cbus_to_bootrom (VCU118RocketSystem.cbus.coupler_to_bootrom) , fragmenter TLFragmenter_bootrom (VCU118RocketSystem.cbus.coupler_to_bootrom.fragmenter) On Output Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] , coupler_to_rockettile TLInterconnectCoupler_cbus_to_rockettile (VCU118RocketSystem.cbus.coupler_to_rockettile) , , , widget TLWidthWidget8_4 (VCU118RocketSystem.cbus.coupler_to_rockettile.widget) , coupler_to_debug TLInterconnectCoupler_cbus_to_debug (VCU118RocketSystem.cbus.coupler_to_debug) , fragmenter TLFragmenter_Debug (VCU118RocketSystem.cbus.coupler_to_debug.fragmenter) On Output Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , coupler_to_plic TLInterconnectCoupler_cbus_to_plic (VCU118RocketSystem.cbus.coupler_to_plic) , fragmenter TLFragmenter_PLIC (VCU118RocketSystem.cbus.coupler_to_plic.fragmenter) On Output Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , coupler_to_clint TLInterconnectCoupler_cbus_to_clint (VCU118RocketSystem.cbus.coupler_to_clint) , fragmenter TLFragmenter_CLINT (VCU118RocketSystem.cbus.coupler_to_clint.fragmenter) On Output Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , coupler_to_bus_named_pbus TLInterconnectCoupler_cbus_to_bus_named_pbus (VCU118RocketSystem.cbus.coupler_to_bus_named_pbus) , widget TLWidthWidget8_3 (VCU118RocketSystem.cbus.coupler_to_bus_named_pbus.widget) , buffer_1 TLBuffer_a32d64s2k1z4u_1 (VCU118RocketSystem.cbus.buffer_1) , a:BufferParams:0, b:BufferParams:0, c:BufferParams:0, d:BufferParams:0, e:BufferParams:0 wrapped_error_device ErrorDeviceWrapper (VCU118RocketSystem.cbus.wrapped_error_device) buffer TLBuffer_a14d64s2k1z4u (VCU118RocketSystem.cbus.wrapped_error_device.buffer) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 3 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] , a:BufferParams:2, b:BufferParams:2, c:BufferParams:2, d:BufferParams:2, e:BufferParams:2 error TLError (VCU118RocketSystem.cbus.wrapped_error_device.error) --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] , atomics TLAtomicAutomata_cbus (VCU118RocketSystem.cbus.atomics) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 2 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[4, 8] logical = TransferSizes[4, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 2 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] , buffer TLBuffer_a32d64s2k1z4u (VCU118RocketSystem.cbus.buffer) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[4, 8] logical = TransferSizes[4, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 2 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[4, 8] logical = TransferSizes[4, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] , a:BufferParams:2, b:BufferParams:2, c:BufferParams:2, d:BufferParams:2, e:BufferParams:2 out_xbar TLXbar_cbus_out_i1_o7_a32d64s2k1z4u (VCU118RocketSystem.cbus.out_xbar) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 3 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 5 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 3 Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[4, 8] logical = TransferSizes[4, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 0 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[4, 8] logical = TransferSizes[4, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] , in_xbar TLXbar_cbus_in_i1_o1_a32d64s2k1z4u (VCU118RocketSystem.cbus.in_xbar) , fixer TLFIFOFixer_2 (VCU118RocketSystem.cbus.fixer) , fixedClockNode FixedClockBroadcast_5 (VCU118RocketSystem.cbus.fixedClockNode) , clockGroup ClockGroup_3 (VCU118RocketSystem.cbus.clockGroup) , cbus_clock_groups ClockGroupAggregator_cbus (VCU118RocketSystem.cbus.cbus_clock_groups) , fbus FrontBus (VCU118RocketSystem.fbus) , , coupler_from_debug_sb TLInterconnectCoupler_fbus_from_debug_sb (VCU118RocketSystem.fbus.coupler_from_debug_sb) , widget TLWidthWidget1 (VCU118RocketSystem.fbus.coupler_from_debug_sb.widget) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 4 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 1 Slave Port MinLatency = 4 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] , buffer TLBuffer_a32d64s1k1z4u (VCU118RocketSystem.fbus.buffer) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 2 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 4 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] , a:BufferParams:2, b:BufferParams:2, c:BufferParams:2, d:BufferParams:2, e:BufferParams:2 fbus_xbar TLXbar_fbus_i1_o1_a32d64s1k1z4u (VCU118RocketSystem.fbus.fbus_xbar) , fixedClockNode FixedClockBroadcast_1 (VCU118RocketSystem.fbus.fixedClockNode) , clockGroup ClockGroup_2 (VCU118RocketSystem.fbus.clockGroup) , fbus_clock_groups ClockGroupAggregator_fbus (VCU118RocketSystem.fbus.fbus_clock_groups) , pbus PeripheryBus_pbus (VCU118RocketSystem.pbus) , , coupler_to_gps TLInterconnectCoupler_pbus_to_gps (VCU118RocketSystem.pbus.coupler_to_gps) , widget TLWidthWidget8_2 (VCU118RocketSystem.pbus.coupler_to_gps.widget) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , fragmenter TLFragmenter_FPGAGPS (VCU118RocketSystem.pbus.coupler_to_gps.fragmenter) On Output Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,96) Slave Port Beatbytes = 4 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 4] putFull = TransferSizes[1, 4] putPartial = TransferSizes[1, 4] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 4 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , coupler_to_max2771_spi TLInterconnectCoupler_pbus_to_max2771_spi (VCU118RocketSystem.pbus.coupler_to_max2771_spi) , fragmenter TLFragmenter_MAX2771SPI (VCU118RocketSystem.pbus.coupler_to_max2771_spi.fragmenter) On Output Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , coupler_to_fpga_pmod_spi TLInterconnectCoupler_pbus_to_fpga_pmod_spi (VCU118RocketSystem.pbus.coupler_to_fpga_pmod_spi) , fragmenter TLFragmenter_FPGAPMODSPI (VCU118RocketSystem.pbus.coupler_to_fpga_pmod_spi.fragmenter) On Output Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , coupler_to_fpga_spi TLInterconnectCoupler_pbus_to_fpga_spi (VCU118RocketSystem.pbus.coupler_to_fpga_spi) , fragmenter TLFragmenter_FPGASPI (VCU118RocketSystem.pbus.coupler_to_fpga_spi.fragmenter) On Output Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , coupler_to_fpga_uart TLInterconnectCoupler_pbus_to_fpga_uart (VCU118RocketSystem.pbus.coupler_to_fpga_uart) , fragmenter TLFragmenter_FPGAUART (VCU118RocketSystem.pbus.coupler_to_fpga_uart.fragmenter) On Output Edge: Master Name = TLFragmenter visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,48) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 8] putFull = TransferSizes[1, 8] putPartial = TransferSizes[1, 8] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , buffer_1 TLBuffer_a29d64s2k1z3u_1 (VCU118RocketSystem.pbus.buffer_1) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 3 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 5 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , a:BufferParams:2, b:BufferParams:2, c:BufferParams:2, d:BufferParams:2, e:BufferParams:2 atomics TLAtomicAutomata_pbus (VCU118RocketSystem.pbus.atomics) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 3 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 3 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , buffer TLBuffer_a29d64s2k1z3u (VCU118RocketSystem.pbus.buffer) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 3 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , a:BufferParams:2, b:BufferParams:2, c:BufferParams:2, d:BufferParams:2, e:BufferParams:2 out_xbar TLXbar_pbus_out_i1_o5_a29d64s2k1z3u (VCU118RocketSystem.pbus.out_xbar) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 1 Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] , in_xbar TLXbar_pbus_in_i1_o1_a29d64s2k1z3u (VCU118RocketSystem.pbus.in_xbar) , fixer TLFIFOFixer_1 (VCU118RocketSystem.pbus.fixer) , fixedClockNode FixedClockBroadcast_6 (VCU118RocketSystem.pbus.fixedClockNode) , clockGroup ClockGroup_1 (VCU118RocketSystem.pbus.clockGroup) , pbus_clock_groups ClockGroupAggregator_pbus (VCU118RocketSystem.pbus.pbus_clock_groups) , sbus SystemBus (VCU118RocketSystem.sbus) , coupler_from_rockettile TLInterconnectCoupler_sbus_from_rockettile (VCU118RocketSystem.sbus.coupler_from_rockettile) , , , coupler_from_bus_named_fbus TLInterconnectCoupler_sbus_from_bus_named_fbus (VCU118RocketSystem.sbus.coupler_from_bus_named_fbus) , widget TLWidthWidget8_1 (VCU118RocketSystem.sbus.coupler_from_bus_named_fbus.widget) , coupler_to_bus_named_cbus TLInterconnectCoupler_sbus_to_bus_named_cbus (VCU118RocketSystem.sbus.coupler_to_bus_named_cbus) , widget TLWidthWidget8 (VCU118RocketSystem.sbus.coupler_to_bus_named_cbus.widget) , fixer TLFIFOFixer (VCU118RocketSystem.sbus.fixer) , system_bus_xbar TLXbar_sbus_i2_o1_a32d64s2k1z4u (VCU118RocketSystem.sbus.system_bus_xbar) On Output Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(2,3) Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 2 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] --------------------------------------------- On Input Edge: Master Name = debug visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 2 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] On Input Edge: Master Name = Core 0 DCache MMIO visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(1,2) Master Name = Core 0 ICache visibility = List(AddressSet(0x0, ~0x0)) emits = acquireT = TransferSizes[1, 4096] acquireB = TransferSizes[1, 4096] arithmetic = TransferSizes[1, 4096] logical = TransferSizes[1, 4096] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] sourceId = IdRange(0,1) Slave Port Beatbytes = 8 Slave Port MinLatency = 2 Slave Name = error Slave Address = List(AddressSet(0x3000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 4096] putFull = TransferSizes[1, 4096] putPartial = TransferSizes[1, 4096] hint = TransferSizes[1, 4096] Slave Name = dev Slave Address = List(AddressSet(0x10013000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10014000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10015000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10016000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10020000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10021000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10022000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10023000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10024000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10025000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10026000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10027000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10028000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x10029000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dev Slave Address = List(AddressSet(0x1002a000, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = clint Slave Address = List(AddressSet(0x2000000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = plic Slave Address = List(AddressSet(0xc000000, 0x3ffffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dmInner Slave Address = List(AddressSet(0x0, 0xfff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = dtim_adapter Slave Address = List(AddressSet(0x80000000, 0xfffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[1, 8] logical = TransferSizes[1, 8] get = TransferSizes[1, 64] putFull = TransferSizes[1, 64] putPartial = TransferSizes[1, 64] hint = TransferSizes[0, 0] Slave Name = bootrom Slave Address = List(AddressSet(0x10000, 0xffff)) supports = acquireT = TransferSizes[0, 0] acquireB = TransferSizes[0, 0] arithmetic = TransferSizes[0, 0] logical = TransferSizes[0, 0] get = TransferSizes[1, 64] putFull = TransferSizes[0, 0] putPartial = TransferSizes[0, 0] hint = TransferSizes[0, 0] , fixedClockNode FixedClockBroadcast_3 (VCU118RocketSystem.sbus.fixedClockNode) , clockGroup ClockGroup (VCU118RocketSystem.sbus.clockGroup) , sbus_clock_groups ClockGroupAggregator_sbus (VCU118RocketSystem.sbus.sbus_clock_groups) , aggregator ClockGroupAggregator_aggregator (VCU118RocketSystem.aggregator) , ibus ClockSinkDomain (VCU118RocketSystem.ibus) Interrupt Node , Interrupt Node , Interrupt Node , , intsource IntSyncCrossingSource_n1x1 (VCU118RocketSystem.ibus.intsource) Interrupt Node , alreadyRegistered:false intsink IntSyncAsyncCrossingSink_n1x1 (VCU118RocketSystem.ibus.intsink) Interrupt Node , sync:3 int_bus IntXbar_i2_o1 (VCU118RocketSystem.ibus.int_bus) Interrupt Node , 1 1 32 10 32 8 1 1 32 32 32 32 1 1 32 32 32 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 2 64 64 1 1 1 1 1 1 1 2 1 64 64 64 1 1 1 1 2 1 64 64 64 64 64 64 64 64 4 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 32 32 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 1 1 1 1 1 11