m255
K4
z2
Z0 !s99 nomlopt
R0
R0
R0
R0
R0
R0
R0
R0
R0
R0
R0
R0
R0
R0
!s11f vlog 2021.2_1 2021.05, May 15 2021
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z1 d/home/ankaoc/Desktop/rocket/rocket-chip/targets/asic/rocket
T_opt
!s110 1783629340
V9_=>WoOE;=zS2=V0ln_fh2
Z2 04 14 4 work asic_rocket_tb fast 0
=1-000ae431a4f1-6a50061b-efa06-ffce
Z3 !s124 OEM100
o-quiet -auto_acc_if_foreign -work targets/asic/rocket/work -suppress 3009
Z4 tCvgOpt 0
n@_opt
Z5 OL;O;2021.2_1;73
R1
T_opt1
!s110 1783633806
ViK;F?JzUaIlf8Vzm70F7P1
R2
=1-000ae431a4f1-6a50178d-cf22e-11760
R3
o-quiet -auto_acc_if_foreign -work /home/onur/Desktop/rocket/rocket-chip/targets/asic/rocket/work -suppress 3009
R4
n@_opt1
R5
R1
T_opt2
!s110 1783629933
VoIglcEU2gJ>Zn49VhbQXD2
R2
=1-000ae431a4f1-6a50086d-29125-10746
R3
o-quiet -auto_acc_if_foreign -work targets/asic/rocket/work -suppress 3009 +acc
R4
n@_opt2
R5
R1
vaccum_dump
Z6 DXx6 sv_std 3 std 0 22 9oUSJO;AeEaW`l:M@^WG92
R6
Z7 DXx4 work 11 definitions 0 22 f]1[P940GzQNm3]c1g86Z2
DXx4 work 18 accum_dump_sv_unit 0 22 GhPX;kk]ULB>BJ0=j=fRN2
Z8 !s110 1783636363
Z9 VDg1SIo80bB@j0V0VzS_@n1
r1
!s85 0
!i10b 1
!s100 J=:0>8Jgoee<[eLDmE2zc3
IM?fYNVQ4Mbmh_TA>9_a8R0
!s105 accum_dump_sv_unit
S1
Z10 d/home/onur/Desktop/rocket/rocket-chip/targets/asic/rocket
Z11 w1780558678
Z12 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv
Z13 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv
!i122 37
L0 3 149
Z14 OL;L;2021.2_1;73
31
Z15 !s108 1783636363.000000
!s107 /home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/registers.svh|/home/onur/Desktop/rocket/rocket-chip/targets/asic/rocket/out/generated/asic_rocket_top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_icache_tag_array_0_64x21.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_icache_data_arrays_512x32.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rf_31x64.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/regfile_32x65.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x99.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x78.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x77.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x124.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x123.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x120.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x115.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x10.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/extern_modules.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/bootromClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/VCU118RocketSystem.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TilePRCIDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_pbus_out_i1_o3_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_dmixbar_i1_o2_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_4.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLToAPB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLROM.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLPLIC.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_bootrom.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_PLIC.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_FPGAUART.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_FPGAGPS.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_Debug.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_CLINT.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaUART.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaSPI.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLError_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLError.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuterAsync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuter.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleInnerAsync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleInner.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModule.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBusBypassBar.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBusBypass.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z3u_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s1k1z4u_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a14d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAtomicAutomata_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAtomicAutomata_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAsyncCrossingSource_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAsyncCrossingSink_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SystemBus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SynchronizerShiftReg_w1_d3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ShiftQueue.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ScratchpadSlavePort.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SBToTL.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundRawFNToRecFN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundRawFNToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_4.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RocketTile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RocketALU.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Rocket.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ResetCatchAndSync_d3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToIN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToIN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RVCExpander.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d8s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleD_a29d32s7k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleA_a29d32s7k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_RegMapperInput_i9_m8.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_RegMapperInput_i23_m8.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PlusArgTimeout.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PTW.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMAChecker.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICFanIn.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/OptimizationBarrier_TLBEntryData.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulDiv.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e8_s24.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/LevelGateway.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagTapController.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagStateMachine.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagBypassChain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntXbar_i3_o1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntXbar_i1_o1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntToFP.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncSyncCrossingSink_n1x2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncSyncCrossingSink_n1x1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x1_Registered.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ITLB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/INToRecFN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/INToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ICache.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IBuf.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/HierarchicalElementResetDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/HellaCacheArbiter.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Frontend.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FrontBus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_5.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_4.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUFMAPipe_l4_f64.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUFMAPipe_l3_f32.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUDecoder.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPU.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPToInt.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPToFP.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGAUARTClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGASPIClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGAGPSClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ErrorDeviceWrapper.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFN_small_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFN_small.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFNToRaw_small_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFNToRaw_small.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRawFN_small_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRawFN_small.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DebugTransportModuleJTAG.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DTLB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DMIToTL.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DCacheDataArray.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DCache.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CompareRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_sbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_aggregator.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroup.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w55.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w43.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w15.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_UInt5_To_UInt5.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_DTMInfo_To_DTMInfo.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureChain_JTAGIdcodeBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CSRFile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CLINTClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CLINT.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/BreakpointUnit.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncValidSync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetRegVec_w2_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetRegVec_w1_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_TLBundleD_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_TLBundleA_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_DebugInternalBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_TLBundleD_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_TLBundleA_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_DebugInternalBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter8_DCacheMetadataReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter4_DCacheDataReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter3_LLWB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter2_Valid_PTWReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/APBGpsBlock.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AMOALU.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/clock/asic_pll_model.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/pulse_gen.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/trck_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acq_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/sync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/spill_register.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/spil_register_flushable.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/gray_to_binary.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/cdc_fifo_gray.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/binary_to_gray.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/xil_fifo.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cos2x.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_one_stage.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/code_loop_discriminator.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/bit_gen.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_code.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/twiddle_ram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/dual_port_ram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/dual_port_bram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/divider_fsm.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/comp_mult.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/bram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_corr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_channel_fast.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_ca_gen.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/sample_counter.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/sample_align.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/reset_synch.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/double_ff_syn.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/gps_top_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/plusarg_reader.v|
Z16 !s90 +define+PRINTF_COND=0|-sv|-work|work|-f|/home/onur/Desktop/rocket/rocket-chip/targets/asic/rocket/out/filelists/asic_rtl.f|
!i113 0
Z17 o-sv -work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
Z18 !s92 +define+PRINTF_COND=0 -sv -work work +incdir+/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
R4
Xaccum_dump_sv_unit
R6
R6
R7
R8
VGhPX;kk]ULB>BJ0=j=fRN2
r1
!s85 0
!i10b 1
!s100 =H74fBC]Zl6z=6F_B_7ND0
IGhPX;kk]ULB>BJ0=j=fRN2
!i103 1
S1
R10
R11
R12
R13
!i122 37
Z19 L0 1 0
R14
31
R15
Z20 !s107 /home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/registers.svh|/home/onur/Desktop/rocket/rocket-chip/targets/asic/rocket/out/generated/asic_rocket_top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_icache_tag_array_0_64x21.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_icache_data_arrays_512x32.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rf_31x64.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/regfile_32x65.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x99.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x78.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x77.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x124.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x123.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x120.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x115.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x10.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/extern_modules.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/bootromClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/VCU118RocketSystem.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TilePRCIDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_pbus_out_i1_o3_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_dmixbar_i1_o2_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_4.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLToAPB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLROM.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLPLIC.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_bootrom.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_PLIC.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_FPGAUART.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_FPGAGPS.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_Debug.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_CLINT.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaUART.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaSPI.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLError_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLError.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuterAsync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuter.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleInnerAsync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleInner.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModule.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBusBypassBar.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBusBypass.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z3u_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s1k1z4u_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a14d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAtomicAutomata_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAtomicAutomata_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAsyncCrossingSource_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAsyncCrossingSink_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SystemBus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SynchronizerShiftReg_w1_d3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ShiftQueue.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ScratchpadSlavePort.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SBToTL.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundRawFNToRecFN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundRawFNToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_4.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RocketTile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RocketALU.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Rocket.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ResetCatchAndSync_d3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToIN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToIN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RVCExpander.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d8s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleD_a29d32s7k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleA_a29d32s7k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_RegMapperInput_i9_m8.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_RegMapperInput_i23_m8.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PlusArgTimeout.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PTW.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMAChecker.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICFanIn.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/OptimizationBarrier_TLBEntryData.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulDiv.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e8_s24.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/LevelGateway.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagTapController.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagStateMachine.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagBypassChain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntXbar_i3_o1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntXbar_i1_o1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntToFP.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncSyncCrossingSink_n1x2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncSyncCrossingSink_n1x1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x1_Registered.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ITLB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/INToRecFN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/INToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ICache.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IBuf.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/HierarchicalElementResetDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/HellaCacheArbiter.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Frontend.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FrontBus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_5.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_4.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUFMAPipe_l4_f64.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUFMAPipe_l3_f32.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUDecoder.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPU.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPToInt.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPToFP.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGAUARTClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGASPIClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGAGPSClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ErrorDeviceWrapper.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFN_small_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFN_small.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFNToRaw_small_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFNToRaw_small.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRawFN_small_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRawFN_small.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DebugTransportModuleJTAG.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DTLB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DMIToTL.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DCacheDataArray.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DCache.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CompareRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_sbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_aggregator.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroup.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w55.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w43.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w15.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_UInt5_To_UInt5.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_DTMInfo_To_DTMInfo.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureChain_JTAGIdcodeBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CSRFile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CLINTClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CLINT.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/BreakpointUnit.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncValidSync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetRegVec_w2_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetRegVec_w1_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_TLBundleD_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_TLBundleA_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_DebugInternalBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_TLBundleD_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_TLBundleA_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_DebugInternalBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter8_DCacheMetadataReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter4_DCacheDataReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter3_LLWB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter2_Valid_PTWReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/APBGpsBlock.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AMOALU.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/clock/asic_pll_model.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/pulse_gen.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/trck_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acq_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/sync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/spill_register.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/spil_register_flushable.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/gray_to_binary.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/cdc_fifo_gray.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/binary_to_gray.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/xil_fifo.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cos2x.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_one_stage.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/code_loop_discriminator.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/bit_gen.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_code.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/twiddle_ram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/dual_port_ram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/dual_port_bram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/divider_fsm.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/comp_mult.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/bram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_corr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_channel_fast.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_ca_gen.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/sample_counter.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/sample_align.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/reset_synch.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/double_ff_syn.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/gps_top_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/plusarg_reader.v|
R16
!i113 0
R17
R18
R4
vacq_ca_gen
R6
R6
R7
DXx4 work 18 acq_ca_gen_sv_unit 0 22 WV99DYM:ZjhDca49LI3=12
R8
R9
r1
!s85 0
!i10b 1
!s100 F8WMY5z^AG4Y`D>Cb@]8[1
IaFXZzGKhOLB1`Wca[zNGH0
!s105 acq_ca_gen_sv_unit
S1
R10
R11
Z21 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_ca_gen.sv
Z22 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_ca_gen.sv
!i122 37
L0 22 80
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xacq_ca_gen_sv_unit
R6
R6
R7
R8
VWV99DYM:ZjhDca49LI3=12
r1
!s85 0
!i10b 1
!s100 JSfZZD0gfBg0O3kiNJbK01
IWV99DYM:ZjhDca49LI3=12
!i103 1
S1
R10
R11
R21
R22
!i122 37
Z23 L0 20 0
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vacq_channel_fast
R6
R8
!i10b 1
!s100 3aFlKN`XGokbG<OgCQPV`3
IoGRXLS0Y0074za[79aW6Q2
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_channel_fast.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_channel_fast.sv
!i122 37
L0 3 129
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vacq_corr
R6
R6
R7
DXx4 work 16 acq_corr_sv_unit 0 22 HG@`:nAjF0FD2ALag7iDX3
R8
R9
r1
!s85 0
!i10b 1
!s100 U^4@Yk`IP=ADaeM[8<^1J1
I3TnmI>[5VG]50ozI8Mc2<1
!s105 acq_corr_sv_unit
S1
R10
R11
Z24 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_corr.sv
Z25 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_corr.sv
!i122 37
L0 23 431
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xacq_corr_sv_unit
R6
R6
R7
R8
VHG@`:nAjF0FD2ALag7iDX3
r1
!s85 0
!i10b 1
!s100 UeW:CY2d8:BO@3NzF8S]J2
IHG@`:nAjF0FD2ALag7iDX3
!i103 1
S1
R10
R11
R24
R25
!i122 37
Z26 L0 21 0
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vacq_nco_carr
R6
R6
R7
DXx4 work 20 acq_nco_carr_sv_unit 0 22 Wm97HQU4XE7hPHbV=S2Y71
R8
R9
r1
!s85 0
!i10b 1
!s100 o47C_Q]O;2S0^bz2dSS<Q1
IZD^?eK=9[DNfo[CjhPfJ;2
!s105 acq_nco_carr_sv_unit
S1
R10
R11
Z27 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv
Z28 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv
!i122 37
L0 3 89
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xacq_nco_carr_sv_unit
R6
R6
R7
R8
VWm97HQU4XE7hPHbV=S2Y71
r1
!s85 0
!i10b 1
!s100 JzVljCTEoA5MA7>6N6E`10
IWm97HQU4XE7hPHbV=S2Y71
!i103 1
S1
R10
R11
R27
R28
!i122 37
R19
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vacq_peak_srch
R6
R8
!i10b 1
!s100 SjeHzkZzl7hfVJU^MoE[91
IXE_PXSGi8?aQAMkI9PzVP2
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv
!i122 37
L0 21 228
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vacq_top
R6
R6
R7
DXx4 work 15 acq_top_sv_unit 0 22 G?SDcc2;O9oBc[1>bPcic2
R8
R9
r1
!s85 0
!i10b 1
!s100 zU[=;VEiG=ZUUB=^eoJY;2
IEPnaJo<ZQSh@oK3417TdR3
!s105 acq_top_sv_unit
S1
R10
R11
Z29 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_top.sv
Z30 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_top.sv
!i122 37
L0 10 334
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xacq_top_sv_unit
R6
R6
R7
R8
VG?SDcc2;O9oBc[1>bPcic2
r1
!s85 0
!i10b 1
!s100 D[Di`W5GZdD0[gAGiA[<13
IG?SDcc2;O9oBc[1>bPcic2
!i103 1
S1
R10
R11
R29
R30
!i122 37
L0 8 0
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vacq_wrapper
R6
R6
R7
Z31 DXx4 work 11 gps_top_pkg 0 22 lZTf1@059?[SFc_=YDUgF1
DXx4 work 15 acq_wrapper_pkg 0 22 Ubhle6:?lg590g_S`n;^b1
R8
!i10b 1
!s100 WROFWc_7AVA<H?C0:JDT[1
I9Ac1zZjRL17bk>b27X5PQ0
S1
R10
w1783373810
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv
!i122 37
L0 1 395
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
Xacq_wrapper_pkg
R6
R8
!i10b 1
!s100 4WW?flfNKJ5Dh]k0cJ8Jk2
IUbhle6:?lg590g_S`n;^b1
S1
R10
w1783113006
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acq_pkg.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acq_pkg.sv
!i122 37
Z32 L0 3 0
VUbhle6:?lg590g_S`n;^b1
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vafe_top
R6
R6
R7
DXx4 work 15 afe_top_sv_unit 0 22 eokLl4n=Qch3iDN9:MRnI1
R8
R9
r1
!s85 0
!i10b 1
!s100 aMMz^1>?@iCz:jTHWg?Zb0
I=4Z<5BU]31N?DeHYGKj5g2
!s105 afe_top_sv_unit
S1
R10
R11
Z33 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv
Z34 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv
!i122 37
L0 22 84
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xafe_top_sv_unit
R6
R6
R7
R8
VeokLl4n=Qch3iDN9:MRnI1
r1
!s85 0
!i10b 1
!s100 PB>5X^MXkRVj:YDkM0_7I1
IeokLl4n=Qch3iDN9:MRnI1
!i103 1
S1
R10
R11
R33
R34
!i122 37
R23
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vAMOALU
R6
R8
!i10b 1
!s100 3SmfPEYYZUG9A2=63jaN^1
I>RW8F_FdFL4<VKKdgYYX]3
S1
R10
Z35 w1783636363
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AMOALU.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AMOALU.sv
!i122 37
L0 31 30
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@a@m@o@a@l@u
vAPBGpsBlock
R6
R8
!i10b 1
!s100 ]3m1fV>GXBUzjR>hcL4^V3
Ib3Af`1z^PoCmVd>KE4z:11
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/APBGpsBlock.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/APBGpsBlock.sv
!i122 37
L0 31 377
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@a@p@b@gps@block
vArbiter2_Valid_PTWReq
R6
R8
!i10b 1
!s100 ]hSn75a=ZCU`82g8WoTi@0
I7SkbTJSXmDN[g<ne>oY5Z3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter2_Valid_PTWReq.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter2_Valid_PTWReq.sv
!i122 37
Z36 L0 31 12
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@arbiter2_@valid_@p@t@w@req
vArbiter3_LLWB
R6
R8
!i10b 1
!s100 NnDb@`7@?n7S[BKVJn2Le3
I97?lW1_2KKAf_F;G=AIR@0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter3_LLWB.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter3_LLWB.sv
!i122 37
Z37 L0 31 16
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@arbiter3_@l@l@w@b
vArbiter4_DCacheDataReq
R6
R8
!i10b 1
!s100 Z59WU5aE4j<`mk]km=Y0L0
I:eG^_aQ4CH02FnhkVMIIj1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter4_DCacheDataReq.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter4_DCacheDataReq.sv
!i122 37
L0 31 40
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@arbiter4_@d@cache@data@req
vArbiter8_DCacheMetadataReq
R6
R8
!i10b 1
!s100 ]dbBlTePLDG670fn4;;3?3
IbKFdic>V0C:XNS`NFKI2O1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter8_DCacheMetadataReq.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Arbiter8_DCacheMetadataReq.sv
!i122 37
L0 31 23
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@arbiter8_@d@cache@metadata@req
vasic_pll_model
R6
R8
!i10b 1
!s100 f[GLhNgG7Y9Q4F]NVmZX@2
IoH`9WL@5bKYBMWhRHV2Ag0
S1
R10
w1783014475
8/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/clock/asic_pll_model.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/clock/asic_pll_model.sv
!i122 37
L0 3 40
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vasic_rocket_tb
R6
Z38 !s110 1783633804
!i10b 1
!s100 GCl84<1Mn?^C:dElFQ0Q;1
IcFmVKUn?nc3>f2O]nc6OA0
S1
R10
w1783027532
8/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/asic_rocket_tb.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/asic_rocket_tb.sv
!i122 35
L0 3 208
R9
R14
r1
!s85 0
31
Z39 !s108 1783633804.000000
Z40 !s107 /home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/registers.svh|/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/asic_rocket_tb.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/uart/uart_rx_model.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/uart/uart_console_model.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/sram/asic_sram_1rw.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/sram/asic_sram_1r1w.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/flash/spi_flash_model.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/clock/asic_pll_model.sv|/home/onur/Desktop/rocket/rocket-chip/targets/asic/rocket/out/generated/asic_rocket_top_sim.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rockettile_icache_tag_array_0_64x21.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rockettile_icache_data_arrays_512x32.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rockettile_dcache_data_arrays_0_131072x64.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rf_31x64.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/regfile_32x65.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x99.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x78.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x77.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x124.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x123.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x120.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x115.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x10.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/extern_modules.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/bootromClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/VCU118RocketSystem.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TilePRCIDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_pbus_out_i1_o3_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_dmixbar_i1_o2_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8_4.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8_3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLToAPB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLROM.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLPLIC.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_pbus_to_gps.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_plic.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_debug.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_clint.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_bootrom.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_PLIC.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_FPGAUART.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_FPGAGPS.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_Debug.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_CLINT.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFpgaUART.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFpgaSPI.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFIFOFixer_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFIFOFixer_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFIFOFixer.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLError_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLError.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleOuterAsync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleOuter.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleInnerAsync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleInner.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModule.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBusBypassBar.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBusBypass.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z4u_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z3u_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s1k1z4u_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a14d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAtomicAutomata_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAtomicAutomata_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAsyncCrossingSource_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAsyncCrossingSink_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/SystemBus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/SynchronizerShiftReg_w1_d3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ShiftQueue.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ScratchpadSlavePort.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/SBToTL.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundRawFNToRecFN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundRawFNToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_4.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RocketTile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RocketALU.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Rocket.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ResetCatchAndSync_d3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a29d64s2k1z3u_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RecFNToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RecFNToIN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RecFNToIN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RVCExpander.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a32d8s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a32d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleD_a29d32s7k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleA_a29d32s7k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_RegMapperInput_i9_m8.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_RegMapperInput_i23_m8.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PlusArgTimeout.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PeripheryBus_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PeripheryBus_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PTW.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PMPChecker_s3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PMPChecker_s2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PMAChecker.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PLICFanIn.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PLICClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/OptimizationBarrier_TLBEntryData.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulDiv.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_preMul_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_preMul.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_postMul_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_postMul.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNPipe_l2_e8_s24.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNPipe_l2_e11_s53.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/LevelGateway.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/JtagTapController.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/JtagStateMachine.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/JtagBypassChain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntXbar_i3_o1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntXbar_i1_o1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntToFP.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncSyncCrossingSink_n1x2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncSyncCrossingSink_n1x1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncCrossingSource_n1x2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncCrossingSource_n1x1_Registered.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncCrossingSource_n1x1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncAsyncCrossingSink_n1x1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ITLB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/INToRecFN_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/INToRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ICache.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IBuf.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/HierarchicalElementResetDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/HellaCacheArbiter.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Frontend.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FrontBus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_5.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_4.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_3.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPUFMAPipe_l4_f64.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPUFMAPipe_l3_f32.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPUDecoder.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPU.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPToInt.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPToFP.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPGAUARTClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPGASPIClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPGAGPSClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ErrorDeviceWrapper.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFN_small_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFN_small.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFNToRaw_small_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFNToRaw_small.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRawFN_small_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRawFN_small.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DebugTransportModuleJTAG.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DTLB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DMIToTL.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DCacheDataArray.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DCache.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CompareRecFN.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_sbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_pbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_cbus.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_aggregator.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroup.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockCrossingReg_w55.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockCrossingReg_w43.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockCrossingReg_w15.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureUpdateChain_UInt5_To_UInt5.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureUpdateChain_DTMInfo_To_DTMInfo.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureChain_JTAGIdcodeBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CSRFile.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CLINTClockSinkDomain.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CLINT.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/BreakpointUnit.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncValidSync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetRegVec_w2_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetRegVec_w1_i0.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSource_TLBundleD_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSource_TLBundleA_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSource_DebugInternalBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSink_TLBundleD_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSink_TLBundleA_a9d32s1k1z2u.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSink_DebugInternalBundle.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Arbiter8_DCacheMetadataReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Arbiter4_DCacheDataReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Arbiter3_LLWB.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Arbiter2_Valid_PTWReq.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/APBGpsBlock.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AMOALU.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/pulse_gen.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/trck_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acq_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/sync.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/spill_register.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/spil_register_flushable.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/gray_to_binary.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/cdc_fifo_gray.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/binary_to_gray.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/xil_fifo.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cos2x.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_one_stage.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/code_loop_discriminator.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/bit_gen.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_code.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/twiddle_ram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/dual_port_ram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/dual_port_bram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/divider_fsm.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/comp_mult.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/bram.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_corr.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_channel_fast.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/acq_ca_gen.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/sample_counter.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/sample_align.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/reset_synch.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/double_ff_syn.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/gps_top_pkg.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv|/home/onur/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/plusarg_reader.v|/home/onur/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/SimJTAG.v|
Z41 !s90 +define+PRINTF_COND=0|+define+RANDOMIZE_REG_INIT|+define+RANDOMIZE_MEM_INIT|+define+RANDOM=0|+define+INIT_RANDOM_PROLOG_|-sv|-work|work|-f|/home/onur/Desktop/rocket/rocket-chip/targets/asic/rocket/out/filelists/asic_tb.f|
!i113 0
R17
Z42 !s92 +define+PRINTF_COND=0 +define+RANDOMIZE_REG_INIT +define+RANDOMIZE_MEM_INIT +define+RANDOM=0 +define+INIT_RANDOM_PROLOG_ -sv -work work +incdir+/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
R4
vasic_rocket_top
R6
R8
!i10b 1
!s100 _T9kF1=O:L07MHaN<R`ON2
I71_EAkf3^A9589o=f69WP0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/targets/asic/rocket/out/generated/asic_rocket_top.sv
F/home/onur/Desktop/rocket/rocket-chip/targets/asic/rocket/out/generated/asic_rocket_top.sv
!i122 37
L0 3 147
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vasic_sram_1r1w
R6
R38
!i10b 1
!s100 KmBP_mnJ<cEl>f=FC0W;R2
ISj2C3Q>eCa6>igJJC2l^J3
S1
R10
Z43 w1782982000
8/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/sram/asic_sram_1r1w.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/sram/asic_sram_1r1w.sv
!i122 35
L0 3 27
R9
R14
r1
!s85 0
31
R39
R40
R41
!i113 0
R17
R42
R4
vasic_sram_1rw
R6
R38
!i10b 1
!s100 1AEKWnh0^:YJMH<4o<>oI0
I5H:9i29SXVG^14P[Z`M9D3
S1
R10
R43
8/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/sram/asic_sram_1rw.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/sram/asic_sram_1rw.sv
!i122 35
L0 3 30
R9
R14
r1
!s85 0
31
R39
R40
R41
!i113 0
R17
R42
R4
vAsyncQueueSink_DebugInternalBundle
R6
R8
!i10b 1
!s100 nY8LSm`KizzaHl]OQ3@Z63
IW[k@3UPdBa;obl3liN[ER3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_DebugInternalBundle.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_DebugInternalBundle.sv
!i122 37
Z44 L0 31 108
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@queue@sink_@debug@internal@bundle
vAsyncQueueSink_TLBundleA_a9d32s1k1z2u
R6
R8
!i10b 1
!s100 IAjmdf3@UQ]iJeI8YL?`I1
ILgAMg_ES0fWFHgfaNFlUF3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_TLBundleA_a9d32s1k1z2u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_TLBundleA_a9d32s1k1z2u.sv
!i122 37
L0 31 114
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@queue@sink_@t@l@bundle@a_a9d32s1k1z2u
vAsyncQueueSink_TLBundleD_a9d32s1k1z2u
R6
R8
!i10b 1
!s100 PHCGP11I18`YBW_E8T65Q2
IVCKDRcF7Q>a_E2Y`89FXB0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_TLBundleD_a9d32s1k1z2u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSink_TLBundleD_a9d32s1k1z2u.sv
!i122 37
L0 31 112
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@queue@sink_@t@l@bundle@d_a9d32s1k1z2u
vAsyncQueueSource_DebugInternalBundle
R6
R8
!i10b 1
!s100 8`AMehQ`QQcU:U[:b=cez0
I5gS9LJ5gAA[@IXV<ZNBRF1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_DebugInternalBundle.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_DebugInternalBundle.sv
!i122 37
Z45 L0 31 110
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@queue@source_@debug@internal@bundle
vAsyncQueueSource_TLBundleA_a9d32s1k1z2u
R6
R8
!i10b 1
!s100 :LRUn0c1o@ClCO`z^kBPP1
IU[6dD@88N1dELdI4@gU^M2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_TLBundleA_a9d32s1k1z2u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_TLBundleA_a9d32s1k1z2u.sv
!i122 37
Z46 L0 31 105
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@queue@source_@t@l@bundle@a_a9d32s1k1z2u
vAsyncQueueSource_TLBundleD_a9d32s1k1z2u
R6
R8
!i10b 1
!s100 [IonEJjAV4D552oS9NK5m1
IY@FMd;1OR1XA0j:V2lZin3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_TLBundleD_a9d32s1k1z2u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncQueueSource_TLBundleD_a9d32s1k1z2u.sv
!i122 37
R45
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@queue@source_@t@l@bundle@d_a9d32s1k1z2u
vAsyncResetRegVec_w1_i0
R6
R8
!i10b 1
!s100 9mBjn0;z17VX5BcgL69eT3
I2:2dG@]_k7oljEPZb]BU32
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetRegVec_w1_i0.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetRegVec_w1_i0.sv
!i122 37
Z47 L0 31 28
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@reset@reg@vec_w1_i0
vAsyncResetRegVec_w2_i0
R6
R8
!i10b 1
!s100 mYAL3h_Q5W8mXk;PYWO6X3
IzjTiRV5VY>=FeP_0kU=`H2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetRegVec_w2_i0.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetRegVec_w2_i0.sv
!i122 37
R47
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@reset@reg@vec_w2_i0
vAsyncResetSynchronizerPrimitiveShiftReg_d3_i0
R6
R8
!i10b 1
!s100 ALR?K@RgK8Rz6X765Z07G1
IRTNFZ3RO`XDzlm^87W4AM1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv
!i122 37
L0 31 39
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@reset@synchronizer@primitive@shift@reg_d3_i0
vAsyncResetSynchronizerShiftReg_w1_d3_i0
R6
R8
!i10b 1
!s100 Q;867RTUEC:YzL9:m:NBY2
IVY37@k_DegoIK6`jK8a`J0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0.sv
!i122 37
Z48 L0 31 14
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@reset@synchronizer@shift@reg_w1_d3_i0
vAsyncResetSynchronizerShiftReg_w1_d3_i0_1
R6
R8
!i10b 1
!s100 HRZC;Q<1@XIggQCC2e[I50
IT@^@A1nRDhYIkzDXZPj=b0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv
!i122 37
R48
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@reset@synchronizer@shift@reg_w1_d3_i0_1
vAsyncValidSync
R6
R8
!i10b 1
!s100 aXVa:2Eg`VYOnb9F@?AEI0
IA>:;LPL31TXC?dB@cK9K12
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncValidSync.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/AsyncValidSync.sv
!i122 37
R48
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@async@valid@sync
vbinary_to_gray
R6
R8
!i10b 1
!s100 h<aF?URczUlk<=7RZ;7c[0
ImJE7lV]AJkF>1JLd>iEl@1
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/binary_to_gray.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/binary_to_gray.sv
!i122 37
L0 15 8
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vbit_gen
R6
R6
R7
DXx4 work 15 bit_gen_sv_unit 0 22 B@dWhnV9]X?3Ue6CEXRg@2
R8
R9
r1
!s85 0
!i10b 1
!s100 0;ln];A4d?ZHKSQbgmnh30
I43ZaNn=`5dmCN3JJaZ=Ph1
!s105 bit_gen_sv_unit
S1
R10
Z49 w1783636045
Z50 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/bit_gen.sv
Z51 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/bit_gen.sv
!i122 37
L0 3 113
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xbit_gen_sv_unit
R6
R6
R7
R8
VB@dWhnV9]X?3Ue6CEXRg@2
r1
!s85 0
!i10b 1
!s100 7M29B<X2HdOzO_:J3bgk;3
IB@dWhnV9]X?3Ue6CEXRg@2
!i103 1
S1
R10
R49
R50
R51
!i122 37
R19
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vbootromClockSinkDomain
R6
R8
!i10b 1
!s100 R5O2:AVFWffA?;jV=<=Xj1
IA0oZT3:TK5:iLBV=A7YFJ2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/bootromClockSinkDomain.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/bootromClockSinkDomain.sv
!i122 37
L0 31 26
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
nbootrom@clock@sink@domain
vbram
R6
R8
!i10b 1
!s100 ZD`M`56_eU72TLB7XI9Ai3
I8NADK:I2gMh2nl?JBQH?;0
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/bram.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/bram.sv
!i122 37
L0 21 26
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vBreakpointUnit
R6
R8
!i10b 1
!s100 ^0ZL[[Ed3T?7In;0nCX=N3
I:[28PbTUi6bdPzY0lFYHC1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/BreakpointUnit.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/BreakpointUnit.sv
!i122 37
Z52 L0 31 86
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@breakpoint@unit
vbutterfly
R6
R8
!i10b 1
!s100 bKDAg>L0]W9KmT4Nj<Z_W2
IPMkUP66o6AIZbc5oa?fag0
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv
!i122 37
Z53 L0 1 57
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vcacode_gen_trck
R6
R8
!i10b 1
!s100 @9zk5;bTGfzO]kE0BoTU:1
IdAHH_dLDWTCZ;D>eYSO?11
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv
!i122 37
R53
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vCaptureChain_JTAGIdcodeBundle
R6
R8
!i10b 1
!s100 WXLkiAi:e1mGT=DSfhK5a2
IBn>26b9B]1Z;@]`QXm_Tm1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureChain_JTAGIdcodeBundle.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureChain_JTAGIdcodeBundle.sv
!i122 37
L0 31 129
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@capture@chain_@j@t@a@g@idcode@bundle
vCaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate
R6
R8
!i10b 1
!s100 =k5OgE2<UGT?8AWQO91TZ1
I`>cXGnUAZ?JF?Sc0]W>I_2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate.sv
!i122 37
Z54 L0 31 202
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@capture@update@chain_@d@m@i@access@capture_@to_@d@m@i@access@update
vCaptureUpdateChain_DTMInfo_To_DTMInfo
R6
R8
!i10b 1
!s100 l1<f[KQYi>h1;0LH`GcZS0
I9GAE:bHz3o>WmJ9OU@cj<3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_DTMInfo_To_DTMInfo.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_DTMInfo_To_DTMInfo.sv
!i122 37
Z55 L0 31 106
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@capture@update@chain_@d@t@m@info_@to_@d@t@m@info
vCaptureUpdateChain_UInt5_To_UInt5
R6
R8
!i10b 1
!s100 ;5:ciedHb4H35UCE55I8I2
IX=;@4G?abj0L]2g8U_IA>3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_UInt5_To_UInt5.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CaptureUpdateChain_UInt5_To_UInt5.sv
!i122 37
L0 31 50
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@capture@update@chain_@u@int5_@to_@u@int5
vcdc_fifo_gray
R6
R8
!i10b 1
!s100 ?j^ThUmZ`8kOIYja;2c^51
I_mF=YJM]F<NLe]V0_UVbQ1
S1
R10
R11
Z56 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/cdc_fifo_gray.sv
Z57 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/cdc_fifo_gray.sv
!i122 37
L0 103 66
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vcdc_fifo_gray_dst
R6
R8
!i10b 1
!s100 ERBa@LPW19OCCQ53dO4>A0
IiZ`ek@S@?cS3QndfAF7hF1
S1
R10
R11
R56
R57
!i122 37
L0 231 64
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vcdc_fifo_gray_src
R6
R8
!i10b 1
!s100 3FOo]Yf]J8MaNDgO79SIZ0
IL9Y=D5:@n>m83<zDeb8n03
S1
R10
R11
R56
R57
!i122 37
L0 173 54
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vCLINT
R6
R8
!i10b 1
!s100 5F9?]^h^NIn[DXKI;EDo43
I[l[A50aFh`cF8nY6<af<I3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CLINT.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CLINT.sv
!i122 37
Z58 L0 31 99
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@c@l@i@n@t
vCLINTClockSinkDomain
R6
R8
!i10b 1
!s100 _4HYiOD5k[NJJ8=8J7jCD0
IX?[KFBZ6P<?ldPWHDn0[N2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CLINTClockSinkDomain.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CLINTClockSinkDomain.sv
!i122 37
Z59 L0 31 58
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@c@l@i@n@t@clock@sink@domain
vClockCrossingReg_w15
R6
R8
!i10b 1
!s100 956j>h^hoDdKM]CBlhJSV1
Il7kd3iAKPj3GHkE`5PODn0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w15.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w15.sv
!i122 37
R48
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@clock@crossing@reg_w15
vClockCrossingReg_w43
R6
R8
!i10b 1
!s100 @AYgQ<5_bUA`[FS;7`Z0;0
IBLKhefTkB]XZ>MkW9`?;o0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w43.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w43.sv
!i122 37
R48
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@clock@crossing@reg_w43
vClockCrossingReg_w55
R6
R8
!i10b 1
!s100 Ob=mfhe``X_1dEI@`BIYn0
IkFF=j7aGGm[LQG[S_e^Hb0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w55.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockCrossingReg_w55.sv
!i122 37
R48
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@clock@crossing@reg_w55
vClockGroup
R6
R8
!i10b 1
!s100 88SXD<`U>jS32PomAN30a2
InaQc;^0O]Q1mia7DF?df;1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroup.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroup.sv
!i122 37
Z60 L0 31 10
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@clock@group
vClockGroupAggregator_aggregator
R6
R8
!i10b 1
!s100 0WOjjaQTW^RN9]WPmK6IQ2
IQW2f0WdeS<Y0:Z7>cmJze2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_aggregator.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_aggregator.sv
!i122 37
R47
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@clock@group@aggregator_aggregator
vClockGroupAggregator_cbus
R6
R8
!i10b 1
!s100 lkFkBkBV`RjJcJh:LDP`92
I2N`47jbib::P9SUd`Ez[G0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_cbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_cbus.sv
!i122 37
R37
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@clock@group@aggregator_cbus
vClockGroupAggregator_pbus
R6
R8
!i10b 1
!s100 Eo[Ym3@0bHoPPK0@]1A4L0
IBn0OzBThNT?CBI01fjH643
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_pbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_pbus.sv
!i122 37
R60
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@clock@group@aggregator_pbus
vClockGroupAggregator_sbus
R6
R8
!i10b 1
!s100 DTJMHIC;D[5W]F9iJ?A?N3
IiS[]Rb3=TcM:9]m2H?8=o0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_sbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockGroupAggregator_sbus.sv
!i122 37
R47
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@clock@group@aggregator_sbus
vClockSinkDomain
R6
R8
!i10b 1
!s100 fOiP8]Yfi5_VP1jRHj_021
IN72N8Vna8O2do`b;]ZbK=3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockSinkDomain.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ClockSinkDomain.sv
!i122 37
Z61 L0 31 46
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@clock@sink@domain
vcode_loop_discriminator
R6
R8
!i10b 1
!s100 3ozd<USLo[XkBPH8^gJ4L0
I5;HLji?JDIV`ZOFod]@Gh2
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/code_loop_discriminator.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/code_loop_discriminator.sv
!i122 37
L0 14 70
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vcomp_mult
R6
R8
!i10b 1
!s100 dURAW<eF:6LLP]nWC8E=d2
ILBK^U9U>nGJ@hKl@o7?X83
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/comp_mult.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/comp_mult.sv
!i122 37
L0 21 100
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vCompareRecFN
R6
R8
!i10b 1
!s100 Bc39i16MXUdg6G?hc6kM^3
INK[9]Cl7>5:ngSz3WHM[K0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CompareRecFN.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CompareRecFN.sv
!i122 37
L0 31 29
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@compare@rec@f@n
vcordic_angle_lut
R6
R8
!i10b 1
!s100 4MJ;6^8`R]YIeEKSe10fX2
IchbmHI7`XdSSa_iK;dN[K0
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv
!i122 37
L0 12 209
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vcordic_atan_basic
R6
R8
!i10b 1
!s100 [^V`4[fZS61[JabhVRR8D0
Ind:EjgRTkVRafM1Ol?C6g3
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv
!i122 37
L0 11 194
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vcordic_atan_one_stage
R6
R8
!i10b 1
!s100 NE3gPPjD5;?>0_2hXbLe>3
IC115Fj>]FkZ3[Rk]8OX_E0
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_one_stage.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_one_stage.sv
!i122 37
L0 1 30
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vcos2x
R6
R8
!i10b 1
!s100 b<Qlm4UOZj_LQlWYSk1G?0
IdHWb^RFVZ[[hX9TNDiL4=0
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cos2x.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/cos2x.sv
!i122 37
L0 12 54
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vCSRFile
R6
R8
!i10b 1
!s100 TXTI2C6e0<GCNz]MJdbaA1
IA5iRZ3408dj@0K9nJI`DH0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CSRFile.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/CSRFile.sv
!i122 37
L0 31 1522
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@c@s@r@file
vDCache
R6
R8
!i10b 1
!s100 ?YZ=h@01A`9SJ`NXMmP;O3
IzMlAA?S]@oGWzhZcClkP`1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DCache.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DCache.sv
!i122 37
L0 31 1318
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@d@cache
vDCacheDataArray
R6
R8
!i10b 1
!s100 >3@;];h:ZWX0ki99Wm]RT2
ITC5ee7a@]fZVK@@EgJM3d0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DCacheDataArray.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DCacheDataArray.sv
!i122 37
R47
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@d@cache@data@array
vDebugTransportModuleJTAG
R6
R8
!i10b 1
!s100 2kb4F:[EC[Zf`dWc@@94=3
IPdAY9][D8kM7:j6IVzJLJ0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DebugTransportModuleJTAG.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DebugTransportModuleJTAG.sv
!i122 37
Z62 L0 31 235
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@debug@transport@module@j@t@a@g
Xdefinitions
R6
R8
!i10b 1
!s100 =4EdZbPlo=nJXVR9GhOXH2
If]1[P940GzQNm3]c1g86Z2
S1
R10
w1783625185
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/definitions.sv
!i122 37
R19
Vf]1[P940GzQNm3]c1g86Z2
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vdivider
R6
R8
!i10b 1
!s100 PmU_U]?n[enL9XXMjb`D:3
I>N0cDnWcIRabhZX3i:<zH0
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv
!i122 37
L0 15 97
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vdivider_fsm
R6
R8
!i10b 1
!s100 >baj8dJGYdMg@HTgaUg=g3
In:ij1XJMm_XHn_TKI?_L12
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/divider_fsm.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/divider_fsm.sv
!i122 37
L0 23 159
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vDivSqrtRawFN_small
R6
R8
!i10b 1
!s100 6>I4?:c9X<kB03T:Vg1<R2
IeZe@`h94EX4K>9FMBLg?]3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRawFN_small.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRawFN_small.sv
!i122 37
L0 31 168
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@div@sqrt@raw@f@n_small
vDivSqrtRawFN_small_1
R6
R8
!i10b 1
!s100 b]9Eh]^4fj0^k_9:F[B3P1
Ib;5X7iSUF`5mA:;2L2<7b2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRawFN_small_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRawFN_small_1.sv
!i122 37
L0 31 169
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@div@sqrt@raw@f@n_small_1
vDivSqrtRecFN_small
R6
R8
!i10b 1
!s100 b`79C>E<[j7VmiD4SP?>@1
IC3@04?AAK9jY`5<b_OlVD1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFN_small.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFN_small.sv
!i122 37
Z63 L0 31 59
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@div@sqrt@rec@f@n_small
vDivSqrtRecFN_small_1
R6
R8
!i10b 1
!s100 M@ab11NGo=g[0o2UgDAIe0
I<_dcOZ^lNCXzZ0X:EFBh]0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFN_small_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFN_small_1.sv
!i122 37
R63
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@div@sqrt@rec@f@n_small_1
vDivSqrtRecFNToRaw_small
R6
R8
!i10b 1
!s100 PNW[>HJ5>CYEL_@<L7=<z2
I^QP:N_kO?R]@nSdLjVDQX0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFNToRaw_small.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFNToRaw_small.sv
!i122 37
Z64 L0 31 54
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@div@sqrt@rec@f@n@to@raw_small
vDivSqrtRecFNToRaw_small_1
R6
R8
!i10b 1
!s100 S__h:gI`[87LgiQnYJ61L3
IY_]FKHBaoGzSh`0Q64]D51
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFNToRaw_small_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DivSqrtRecFNToRaw_small_1.sv
!i122 37
R64
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@div@sqrt@rec@f@n@to@raw_small_1
vDMIToTL
R6
R8
!i10b 1
!s100 @aMPKZB2MaQ>Jfz80GVWk1
IUj:a@^K8FH7aXLSZ<`@nd2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DMIToTL.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DMIToTL.sv
!i122 37
Z65 L0 31 34
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@d@m@i@to@t@l
vdouble_ff_syn
R6
R8
!i10b 1
!s100 Df8njde6UEoRKV<_4ja9l1
I=dNC=ST]X<AX]O4;Allcd3
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/double_ff_syn.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/double_ff_syn.sv
!i122 37
L0 3 48
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vDTLB
R6
R8
!i10b 1
!s100 Q:0PKJGb^j[0kQNd8G@>z2
I13`]GT>V2KT7a2j<mkiCB1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DTLB.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/DTLB.sv
!i122 37
L0 31 386
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@d@t@l@b
vdual_port_bram
R6
R8
!i10b 1
!s100 KLLe;nM4nl2cmj0d@ELG62
I:Zn_DYlhEh:Nm6[bHdVG92
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/dual_port_bram.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/dual_port_bram.sv
!i122 37
L0 1 45
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vdual_port_ram
R6
R8
!i10b 1
!s100 >82J5?52Y;L<J[VWGQXdP0
IHK1G7d0DOWAUbE:PUbhgY1
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/dual_port_ram.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/dual_port_ram.sv
!i122 37
Z66 L0 1 26
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vErrorDeviceWrapper
R6
R8
!i10b 1
!s100 TW4Feiz4WzLhc06KN6:Gb2
IEig91Zlfb<oPA=iVom:CQ3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ErrorDeviceWrapper.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ErrorDeviceWrapper.sv
!i122 37
L0 31 102
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@error@device@wrapper
vfft_radix_2
R6
R8
!i10b 1
!s100 19SMCFH^h5HDZ?7?hCiC32
I;hJ@_LHL?lE6[;;Q>LC:40
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv
!i122 37
L0 11 370
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vFixedClockBroadcast_1
R6
R8
!i10b 1
!s100 _7^9J5H>Y;Lf7BFUYaK@F1
I3^0K4Pa0lZ44JPZRT_eX22
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_1.sv
!i122 37
R60
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@fixed@clock@broadcast_1
vFixedClockBroadcast_3
R6
R8
!i10b 1
!s100 3^>JW=l;]dbG7l[zkGz=K1
IGDY?W:ARMe17DObP=Qz>F3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_3.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_3.sv
!i122 37
R48
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@fixed@clock@broadcast_3
vFixedClockBroadcast_4
R6
R8
!i10b 1
!s100 @dK6R10e[0zXoG:h87AaN2
IYlNc:E5=[0:R?<SbIjUaf0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_4.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_4.sv
!i122 37
Z67 L0 31 22
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@fixed@clock@broadcast_4
vFixedClockBroadcast_5
R6
R8
!i10b 1
!s100 XC64]Yc1jSUee607`hXlb0
I8dm_^Ba]hVaT_0dnQ`BNK0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_5.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FixedClockBroadcast_5.sv
!i122 37
R67
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@fixed@clock@broadcast_5
vFPGAGPSClockSinkDomain
R6
R8
!i10b 1
!s100 7[l=HJbS9[9EeEN]mi2ZA0
IFKFF?3nh?bBiNLlFf1oHU0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGAGPSClockSinkDomain.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGAGPSClockSinkDomain.sv
!i122 37
Z68 L0 31 127
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@f@p@g@a@g@p@s@clock@sink@domain
vFPGASPIClockSinkDomain
R6
R8
!i10b 1
!s100 BP<Wb;2P4CWKD;LbN8k6D0
IPVgZJV_S87iUOeUCm:;DM2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGASPIClockSinkDomain.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGASPIClockSinkDomain.sv
!i122 37
Z69 L0 31 48
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@f@p@g@a@s@p@i@clock@sink@domain
vFPGAUARTClockSinkDomain
R6
R8
!i10b 1
!s100 ?>4TL4zY0]I1:Z??e[50Q2
IWgU7mS0>fVABaL3Zd>fHQ1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGAUARTClockSinkDomain.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPGAUARTClockSinkDomain.sv
!i122 37
L0 31 42
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@f@p@g@a@u@a@r@t@clock@sink@domain
vFPToFP
R6
R8
!i10b 1
!s100 d3JzdhGYSHdGf20;FTePj0
Ioi5NYblMV@Aec@cozIV>S0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPToFP.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPToFP.sv
!i122 37
Z70 L0 31 89
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@f@p@to@f@p
vFPToInt
R6
R8
!i10b 1
!s100 I2Zcj;<]zEe9VSoD]7hc<1
I:P1Ml[NFk`ET8PoLah9zW2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPToInt.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPToInt.sv
!i122 37
Z71 L0 31 257
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@f@p@to@int
vFPU
R6
R8
!i10b 1
!s100 CX]GDkMhTm0Wh=0;Tn8?;1
IXUDIXzFQina17UkYR4YI[3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPU.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPU.sv
!i122 37
L0 31 736
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@f@p@u
vFPUDecoder
R6
R8
!i10b 1
!s100 IlFR`cgfzMRhdL8@;cR:13
I>`eh`C?gKYk[FXcI9P2Vz1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUDecoder.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUDecoder.sv
!i122 37
L0 31 670
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@f@p@u@decoder
vFPUFMAPipe_l3_f32
R6
R8
!i10b 1
!s100 BN]iaJKb8SS3^1gA;:hKX1
I]^Ik6Jf?OXee`:QJe^H]d0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUFMAPipe_l3_f32.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUFMAPipe_l3_f32.sv
!i122 37
Z72 L0 31 49
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@f@p@u@f@m@a@pipe_l3_f32
vFPUFMAPipe_l4_f64
R6
R8
!i10b 1
!s100 421R9JX@E0DNN0=fRJ:Af3
IQ_ai669fAQmMBDjQOg[6d0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUFMAPipe_l4_f64.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FPUFMAPipe_l4_f64.sv
!i122 37
Z73 L0 31 60
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@f@p@u@f@m@a@pipe_l4_f64
vFrontBus
R6
R8
!i10b 1
!s100 ;XmAPJ`;EV;Fm=cVkDHAD1
InG;@K0GEh[olHFMZdhL:k2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FrontBus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/FrontBus.sv
!i122 37
L0 31 254
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@front@bus
vFrontend
R6
R8
!i10b 1
!s100 zH]Lm8:l=ReR20d:Iak@03
I4mWQKaHfTX3CTQB@nLoZa3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Frontend.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Frontend.sv
!i122 37
Z74 L0 31 265
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@frontend
Xgps_top_pkg
R6
R8
!i10b 1
!s100 5@e4XL89KMg;;IIR4m>;?1
IlZTf1@059?[SFc_=YDUgF1
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/gps_top_pkg.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/gps_top_pkg.sv
!i122 37
Z75 L0 2 0
VlZTf1@059?[SFc_=YDUgF1
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vgray_to_binary
R6
R8
!i10b 1
!s100 cG>gFR;z[HIFdEz^]>1O`0
IT7]5LVMjoSoP0a:eIFDY23
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/gray_to_binary.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/gray_to_binary.sv
!i122 37
L0 15 9
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vHellaCacheArbiter
R6
R8
!i10b 1
!s100 LM^N[PAb6fz2O:V`lhhnj3
I@lmdBg<?MWPTKfhaDm0I[0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/HellaCacheArbiter.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/HellaCacheArbiter.sv
!i122 37
Z76 L0 31 121
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@hella@cache@arbiter
vHierarchicalElementResetDomain
R6
R8
!i10b 1
!s100 M7UL>bf=W>66HDaZ:V?_03
Ie<RmhScFFag8_NR_0<PfN0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/HierarchicalElementResetDomain.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/HierarchicalElementResetDomain.sv
!i122 37
L0 31 142
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@hierarchical@element@reset@domain
vIBuf
R6
R8
!i10b 1
!s100 Yd`UNio7IcC`FWPK4XWD_1
I;H<ICb_?J=[Wc6h:6VhzS3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IBuf.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IBuf.sv
!i122 37
R76
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@i@buf
vICache
R6
R8
!i10b 1
!s100 ohHdzF7n;B>gV=29E:gXA2
I;D<??VV2PA1VFkG`1`::Y0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ICache.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ICache.sv
!i122 37
L0 31 151
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@i@cache
vifft_abs_sqr
R6
R8
!i10b 1
!s100 633H2_1?jEK:zF@IHQ@6l0
IzcITPjIb^3nN]o]dNd02c1
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv
!i122 37
L0 21 82
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vINToRecFN
R6
R8
!i10b 1
!s100 1oRXeLiVW35HD>eML]DPV3
IT_;CPg9:@O6WV2GDl><Hj3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/INToRecFN.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/INToRecFN.sv
!i122 37
Z77 L0 31 149
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@i@n@to@rec@f@n
vINToRecFN_1
R6
R8
!i10b 1
!s100 O7g2d2ZYLS8cAKN3]>_8L1
I=i;6e=2d;QC9Lbz`<U`X23
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/INToRecFN_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/INToRecFN_1.sv
!i122 37
R77
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@i@n@to@rec@f@n_1
vIntSyncAsyncCrossingSink_n1x1
R6
R8
!i10b 1
!s100 g0UAMR5KdLPLjdUPd@<l40
Id5M`8K3[nN5GGfiO[nP8N2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv
!i122 37
R36
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@int@sync@async@crossing@sink_n1x1
vIntSyncCrossingSource_n1x1
R6
R8
!i10b 1
!s100 nGBelomZ5<VN>JS6IDhLQ2
I:HFVZ?J_In6XhfHPNEPJ^0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x1.sv
!i122 37
R48
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@int@sync@crossing@source_n1x1
vIntSyncCrossingSource_n1x1_Registered
R6
R8
!i10b 1
!s100 DX1_gD[VK7UKG3i8RBVk`3
I9_2h6:NTNUoD8Ifz9c=j83
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x1_Registered.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x1_Registered.sv
!i122 37
Z78 L0 31 7
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@int@sync@crossing@source_n1x1_@registered
vIntSyncCrossingSource_n1x2
R6
R8
!i10b 1
!s100 RKPaeGF<1Oj?E>[iICWC;0
Io1i8=IE=SJKCHDzU41O[>0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x2.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncCrossingSource_n1x2.sv
!i122 37
L0 31 19
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@int@sync@crossing@source_n1x2
vIntSyncSyncCrossingSink_n1x1
R6
R8
!i10b 1
!s100 H>X<P9i89d1j8lC;zBzRY3
Id9cFK_@FT0fGgGWkIcl7G0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncSyncCrossingSink_n1x1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncSyncCrossingSink_n1x1.sv
!i122 37
R78
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@int@sync@sync@crossing@sink_n1x1
vIntSyncSyncCrossingSink_n1x2
R6
R8
!i10b 1
!s100 A;1JS_<o8=dmlCkf3HSYi3
IbREb4;<SMEefJmLM@@g;I2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncSyncCrossingSink_n1x2.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntSyncSyncCrossingSink_n1x2.sv
!i122 37
R60
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@int@sync@sync@crossing@sink_n1x2
vIntToFP
R6
R8
!i10b 1
!s100 WkoBQeV?038c=LD?P7BXB1
I[S`Xka_BlK=cY0>IFkMLb0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntToFP.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntToFP.sv
!i122 37
L0 31 274
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@int@to@f@p
vIntXbar_i1_o1
R6
R8
!i10b 1
!s100 [A_eam_aNFeO;2]f_L3XK1
I^9n4zI[nC7>nCTiWb>1F>3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntXbar_i1_o1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntXbar_i1_o1.sv
!i122 37
R65
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@int@xbar_i1_o1
vIntXbar_i3_o1
R6
R8
!i10b 1
!s100 FEQUQof8mP0ZMMm1=aD<<0
IJ1AH:S`41a60jSbmiYHcI2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntXbar_i3_o1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/IntXbar_i3_o1.sv
!i122 37
R37
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@int@xbar_i3_o1
vITLB
R6
R8
!i10b 1
!s100 3L[ieDk9PWlbUNBLhXN[o2
InN7S^]bmmhJn82G^eiF1C2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ITLB.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ITLB.sv
!i122 37
L0 31 321
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@i@t@l@b
vJtagBypassChain
R6
R8
!i10b 1
!s100 e6g9gaUFg>6TQno>J2=]Z0
IhaW9FVgXDMeQ5Ec2]E9KD3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagBypassChain.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagBypassChain.sv
!i122 37
L0 31 32
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@jtag@bypass@chain
vJtagStateMachine
R6
R8
!i10b 1
!s100 ]QKB7YP^8Zje[YfDFdWd63
INV36ROiDE=VjDVAgA0XKk0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagStateMachine.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagStateMachine.sv
!i122 37
R61
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@jtag@state@machine
vJtagTapController
R6
R8
!i10b 1
!s100 mXLNINWU=bYcW>S5=VQid1
IJk618Q>PGnUIGTVJSXR583
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagTapController.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/JtagTapController.sv
!i122 37
Z79 L0 31 82
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@jtag@tap@controller
vLevelGateway
R6
R8
!i10b 1
!s100 [AiVAkI<V1Y9L1UzDn^fh3
Io1gND7zS7V3bK`d05GTZ^0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/LevelGateway.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/LevelGateway.sv
!i122 37
L0 31 18
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@level@gateway
vLF_carr
R6
R6
R7
DXx4 work 15 LF_carr_sv_unit 0 22 2nR<[cH7gngS<Af^9Mhdj3
R8
R9
r1
!s85 0
!i10b 1
!s100 W2d[4NTeFA<olBK]5=k>B2
IC94hk9glVB2BZ@E`DlD6@3
!s105 LF_carr_sv_unit
S1
R10
R11
Z80 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv
Z81 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv
!i122 37
L0 19 70
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@l@f_carr
XLF_carr_sv_unit
R6
R6
R7
R8
V2nR<[cH7gngS<Af^9Mhdj3
r1
!s85 0
!i10b 1
!s100 aQ2iilmS>DBz^QLg8?n>a3
I2nR<[cH7gngS<Af^9Mhdj3
!i103 1
S1
R10
R11
R80
R81
!i122 37
L0 17 0
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@l@f_carr_sv_unit
vLF_code
R6
R6
R7
DXx4 work 15 LF_code_sv_unit 0 22 Qc0njBN_R]mViBEkSKjE`3
R8
R9
r1
!s85 0
!i10b 1
!s100 D6;k1D2I6RMNYG63IGD?91
I6Sia0]_HAQ8>=>e]TC7D10
!s105 LF_code_sv_unit
S1
R10
R11
Z82 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv
Z83 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv
!i122 37
L0 18 85
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@l@f_code
XLF_code_sv_unit
R6
R6
R7
R8
VQc0njBN_R]mViBEkSKjE`3
r1
!s85 0
!i10b 1
!s100 [<E5RQULnH>11I^^YPbS=0
IQc0njBN_R]mViBEkSKjE`3
!i103 1
S1
R10
R11
R82
R83
!i122 37
L0 16 0
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@l@f_code_sv_unit
vlock_detector
R6
R6
R7
DXx4 work 21 lock_detector_sv_unit 0 22 kdjF[IBCz`c=7Z[F]Q5P@3
R8
R9
r1
!s85 0
!i10b 1
!s100 Hk7]o9MFB;c4MSlEASSLl1
IHOJ`:dWR``D9_OP3:_>I^1
!s105 lock_detector_sv_unit
S1
R10
R49
Z84 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv
Z85 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv
!i122 37
L0 23 144
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xlock_detector_sv_unit
R6
R6
R7
R8
VkdjF[IBCz`c=7Z[F]Q5P@3
r1
!s85 0
!i10b 1
!s100 g_bAl1Z35o?77^I[V66o@0
IkdjF[IBCz`c=7Z[F]Q5P@3
!i103 1
S1
R10
R49
R84
R85
!i122 37
R26
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vMulAddRecFNPipe_l2_e11_s53
R6
R8
!i10b 1
!s100 nBmOdVZIoXoRHzJUAgngi0
IK7^T`;lkha?MiPXdG006M2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv
!i122 37
L0 31 209
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@pipe_l2_e11_s53
vMulAddRecFNPipe_l2_e8_s24
R6
R8
!i10b 1
!s100 HKO>XKOTS``L;LX`T:bOh2
IFe[o<KCXgfMa3Q:k9SMId3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e8_s24.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNPipe_l2_e8_s24.sv
!i122 37
R54
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@pipe_l2_e8_s24
vMulAddRecFNToRaw_postMul
R6
R8
!i10b 1
!s100 Z[>8[U9DMhkSTQB`OJL6C0
Ia3a8I[zBW[`MaOELdl>YJ0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul.sv
!i122 37
L0 31 165
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@to@raw_post@mul
vMulAddRecFNToRaw_postMul_1
R6
R8
!i10b 1
!s100 _<dm4h_T5GGb;VCN61]]42
IajTHHI;j_LUbnkVE:2zg22
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_postMul_1.sv
!i122 37
L0 31 252
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@to@raw_post@mul_1
vMulAddRecFNToRaw_preMul
R6
R8
!i10b 1
!s100 z`]hA;A;S<jz@o_28@;Q03
I<P441oTE?ohJ`<BYNo<942
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul.sv
!i122 37
Z86 L0 31 83
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@to@raw_pre@mul
vMulAddRecFNToRaw_preMul_1
R6
R8
!i10b 1
!s100 Io:08M:;VNkAlDO1J7V^:2
I]e7igRYAG_JJcfnJQNc0C1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulAddRecFNToRaw_preMul_1.sv
!i122 37
R58
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@add@rec@f@n@to@raw_pre@mul_1
vMulDiv
R6
R8
!i10b 1
!s100 =mK<zIVYXU1hU1nDBS6lf2
I05OjT:]Doa2Zj;=?>J<Bj0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulDiv.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/MulDiv.sv
!i122 37
L0 31 119
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@mul@div
vnav_solve_timer
R6
DXx4 work 19 nav_solve_timer_pkg 0 22 fEzomUEUnah:ca3mRzJLD3
R8
!i10b 1
!s100 SJ?dhoKiGMSQObUz2YQj[1
ISCWCci5RImQ]QiAC0D9YT0
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer.sv
!i122 37
L0 2 77
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
Xnav_solve_timer_pkg
R6
R8
!i10b 1
!s100 i5:488b=QGWggLM0?aEc^3
IfEzomUEUnah:ca3mRzJLD3
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer_pkg.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/gps_timer/nav_solve_timer_pkg.sv
!i122 37
R75
VfEzomUEUnah:ca3mRzJLD3
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vNCO_carr
R6
R6
R7
DXx4 work 16 NCO_carr_sv_unit 0 22 <L6<gRz>J35NDKf:SYT?`1
R8
R9
r1
!s85 0
!i10b 1
!s100 `78U5<Y[ACERAJai<TcNI1
Ic7z_0Q=^dOzz]ZBSkee>Z1
!s105 NCO_carr_sv_unit
S1
R10
R11
Z87 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv
Z88 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv
!i122 37
L0 14 120
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@n@c@o_carr
XNCO_carr_sv_unit
R6
R6
R7
R8
V<L6<gRz>J35NDKf:SYT?`1
r1
!s85 0
!i10b 1
!s100 knc[3zG1VXI^ka`8>nX0K3
I<L6<gRz>J35NDKf:SYT?`1
!i103 1
S1
R10
R11
R87
R88
!i122 37
L0 12 0
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@n@c@o_carr_sv_unit
vNCO_code
R6
R6
R7
DXx4 work 16 NCO_code_sv_unit 0 22 Q^Ge;zzNd2:<JSNNH31191
R8
R9
r1
!s85 0
!i10b 1
!s100 O7=1k7P83m3LQA]6TZY7I1
ISVDTm<XbCi`nmD994eiDE3
!s105 NCO_code_sv_unit
S1
R10
Z89 w1783624211
Z90 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_code.sv
Z91 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_code.sv
!i122 37
L0 22 157
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@n@c@o_code
XNCO_code_sv_unit
R6
R6
R7
R8
VQ^Ge;zzNd2:<JSNNH31191
r1
!s85 0
!i10b 1
!s100 3jjc4:14hMgiz:EFKVENM3
IQ^Ge;zzNd2:<JSNNH31191
!i103 1
S1
R10
R89
R90
R91
!i122 37
R23
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
n@n@c@o_code_sv_unit
vNonSyncResetSynchronizerPrimitiveShiftReg_d3
R6
R8
!i10b 1
!s100 I^_Rhd2nfzBlbkMOIm>5O0
ICBkPZ3n`7oG@5CMT6h5L52
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv
!i122 37
R37
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@non@sync@reset@synchronizer@primitive@shift@reg_d3
vOptimizationBarrier_TLBEntryData
R6
R8
!i10b 1
!s100 9NLE99UkeAB?HI2Oh8GdM2
Ia0UfOkGEY1Q_fjT1z5lm<3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/OptimizationBarrier_TLBEntryData.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/OptimizationBarrier_TLBEntryData.sv
!i122 37
Z92 L0 31 52
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@optimization@barrier_@t@l@b@entry@data
vPeripheryBus_cbus
R6
R8
!i10b 1
!s100 PNUadYGX`m]?cG<9YI0kf3
Ik^B64X]U5jH>feWGOgMSf3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_cbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_cbus.sv
!i122 37
L0 31 1456
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@periphery@bus_cbus
vPeripheryBus_pbus
R6
R8
!i10b 1
!s100 `GM_:@^oETlhk5d?`CckF1
IW<i_IAPPoljVfQ[Cjo`aQ0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_pbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PeripheryBus_pbus.sv
!i122 37
L0 31 1048
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@periphery@bus_pbus
vPLICClockSinkDomain
R6
R8
!i10b 1
!s100 PZ=A9b_TDmh<4Fg:daDoV0
IYYli7h>Ee;F@1;>]N=niB1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICClockSinkDomain.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICClockSinkDomain.sv
!i122 37
L0 31 67
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@l@i@c@clock@sink@domain
vPLICFanIn
R6
R8
!i10b 1
!s100 bHb>42?c;MH08:fidJIDZ3
IA9]d;@1N<`AC?h9?=HHMK1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICFanIn.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PLICFanIn.sv
!i122 37
R63
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@l@i@c@fan@in
vplusarg_reader
R6
R8
!i10b 1
!s100 ]N8Qg;1>hCZ5LO5RiYBEZ1
ICfKI^99AHeHcI;z0>J;=i2
S1
R10
Z93 w1782901798
8/home/onur/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/plusarg_reader.v
F/home/onur/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/plusarg_reader.v
!i122 37
L0 7 20
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vPlusArgTimeout
R6
R8
!i10b 1
!s100 YPMIm?E_ofmnJj8zUnWZ?0
IKNzfQEcWk7B;HF07@nC?H2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PlusArgTimeout.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PlusArgTimeout.sv
!i122 37
Z94 L0 31 25
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@plus@arg@timeout
vPMAChecker
R6
R8
!i10b 1
!s100 ^X`=m?6f?g4;F;LNIhHIE2
IP0bSWB^NG8f^SU4S?a[Qm1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMAChecker.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMAChecker.sv
!i122 37
L0 31 79
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@m@a@checker
vPMPChecker_s2
R6
R8
!i10b 1
!s100 ;MKQoLWk`jZ=]9k9l>PbV3
I4<0RT_1gP4lg76BSRmc:V3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s2.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s2.sv
!i122 37
Z95 L0 31 90
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@m@p@checker_s2
vPMPChecker_s3
R6
R8
!i10b 1
!s100 H_dWQPGgzHbk:;PAXH7fA1
IE`]JOf`2UbCjnR:5ANoCK1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s3.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PMPChecker_s3.sv
!i122 37
R71
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@m@p@checker_s3
vPTW
R6
R8
!i10b 1
!s100 XX`6Q_Q4@CIGUXCMfodOJ1
IF2QG`=A@aK]4AWW]9_Ka03
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PTW.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/PTW.sv
!i122 37
R71
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@p@t@w
vpulse_gen
R6
R8
!i10b 1
!s100 FXEF97F=?OMJ8cJDAebhE1
ImRFbdH_0Vzd_TnL65l6lA1
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/pulse_gen.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/pulse_gen.sv
!i122 37
R66
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vQueue1_RegMapperInput_i23_m8
R6
R8
!i10b 1
!s100 AokH>W`0;NgMn3Kfj_O<J2
I;B55f;ZRGF^FSbMm:V@aN1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_RegMapperInput_i23_m8.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_RegMapperInput_i23_m8.sv
!i122 37
R69
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue1_@reg@mapper@input_i23_m8
vQueue1_RegMapperInput_i9_m8
R6
R8
!i10b 1
!s100 I`K6:A=EXX@DaffM=8:O53
IVIn4dA4Xf7jCTD>8eg?LJ1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_RegMapperInput_i9_m8.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_RegMapperInput_i9_m8.sv
!i122 37
R69
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue1_@reg@mapper@input_i9_m8
vQueue1_TLBundleA_a14d64s2k1z4u
R6
R8
!i10b 1
!s100 Y05LkY85eejggjW?;c:gG0
IGS<FZDC4`fKl[kkbYDQ1N3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv
!i122 37
R61
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue1_@t@l@bundle@a_a14d64s2k1z4u
vQueue1_TLBundleA_a29d32s7k1z2u
R6
R8
!i10b 1
!s100 eNf`oBZ`JJkm8Q5jUAV>Q3
IRnEf8QzR3`ZmWV]H^``Ai1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleA_a29d32s7k1z2u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleA_a29d32s7k1z2u.sv
!i122 37
Z96 L0 31 64
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue1_@t@l@bundle@a_a29d32s7k1z2u
vQueue1_TLBundleA_a29d64s6k1z2u
R6
Z97 !s110 1783105747
!i10b 1
!s100 `PPzzTX;Mm6_6old4jz^G2
I`hN<d6MW2QKSN7?AI=RaE1
S1
R1
Z98 w1783026795
8/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleA_a29d64s6k1z2u.sv
F/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleA_a29d64s6k1z2u.sv
!i122 24
L0 46 86
R9
R14
r1
!s85 0
31
Z99 !s108 1783105747.000000
Z100 !s107 /home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/registers.svh|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/asic_rocket_tb.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/uart/uart_rx_model.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/uart/uart_console_model.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/sram/asic_sram_1rw.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/sram/asic_sram_1r1w.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/flash/spi_flash_model.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/clock/asic_pll_model.sv|/home/ankaoc/Desktop/rocket/rocket-chip/targets/asic/rocket/out/generated/asic_rocket_top_sim.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/VCU118RocketSystem.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_pbus_out_i1_o3_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_dmixbar_i1_o2_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8_3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8_2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLToAPB.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLROM.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLPLIC.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_pbus_to_gps.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_plic.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_debug.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_clint.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_PLIC.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_FPGAUART.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_FPGAGPS.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_Debug.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_CLINT.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_bootrom.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFpgaUART.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFpgaSPI.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFIFOFixer.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFIFOFixer_2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFIFOFixer_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLError.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLError_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModule.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleOuter.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleOuterAsync.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleInner.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleInnerAsync.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBusBypass.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBusBypassBar.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z4u_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z3u_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s1k1z4u_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a14d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAtomicAutomata_pbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAtomicAutomata_cbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAsyncCrossingSource_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAsyncCrossingSink_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TilePRCIDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/SystemBus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/SynchronizerShiftReg_w1_d3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ShiftQueue.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ScratchpadSlavePort.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/SBToTL.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RVCExpander.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundRawFNToRecFN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundRawFNToRecFN_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_4.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RocketTile.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rockettile_icache_tag_array_64x21.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rockettile_icache_data_arrays_512x32.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rockettile_dcache_data_arrays_0_131072x64.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Rocket.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RocketALU.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rf_31x64.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a32d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a29d64s2k1z3u_2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/regfile_32x65.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RecFNToRecFN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RecFNToIN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RecFNToIN_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x99.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x78.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x77.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x124.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x123.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x120.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x115.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x10.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a32d8s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a32d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleD_a29d64s6k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleA_a29d64s6k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_RegMapperInput_i9_m8.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_RegMapperInput_i23_m8.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PTW.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PMPChecker_s3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PMPChecker_s2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PMAChecker.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PlusArgTimeout.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PLICFanIn.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PLICClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PeripheryBus_pbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PeripheryBus_cbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/OptimizationBarrier_TLBEntryData.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulDiv.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_preMul.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_preMul_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_postMul.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_postMul_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNPipe_l2_e8_s24.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNPipe_l2_e11_s53.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/LevelGateway.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/JtagTapController.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/JtagStateMachine.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/JtagBypassChain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ITLB.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntXbar_i3_o1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntXbar_i1_o1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntToFP.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncSyncCrossingSink_n1x2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncSyncCrossingSink_n1x1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncCrossingSource_n1x2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncCrossingSource_n1x1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncCrossingSource_n1x1_Registered.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncAsyncCrossingSink_n1x1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/INToRecFN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/INToRecFN_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ICache.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IBuf.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/HierarchicalElementResetDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/HellaCacheArbiter.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Frontend.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FrontBus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPU.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPUFMAPipe_l4_f64.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPUFMAPipe_l3_f32.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPUDecoder.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPToInt.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPToFP.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPGAUARTClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPGASPIClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPGAGPSClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_5.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_4.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ErrorDeviceWrapper.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DTLB.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DMIToTL.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFNToRaw_small.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFNToRaw_small_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFN_small.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFN_small_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRawFN_small.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRawFN_small_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DebugTransportModuleJTAG.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DCache.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DCacheDataArray.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CSRFile.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CompareRecFN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroup.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_sbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_pbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_cbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_aggregator.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockCrossingReg_w55.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockCrossingReg_w43.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockCrossingReg_w15.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CLINT.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CLINTClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureUpdateChain_UInt5_To_UInt5.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureUpdateChain_DTMInfo_To_DTMInfo.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureChain_JTAGIdcodeBundle.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/BreakpointUnit.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/bootromClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncValidSync.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetRegVec_w2_i0.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetRegVec_w1_i0.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSource_TLBundleD_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSource_TLBundleA_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSource_DebugInternalBundle.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSink_TLBundleD_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSink_TLBundleA_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSink_DebugInternalBundle.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Arbiter8_DCacheMetadataReq.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Arbiter4_DCacheDataReq.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Arbiter3_LLWB.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/APBGpsBlock.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AMOALU.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/apb_wrappers/tracking_wrapper.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/apb_wrappers/pulse_gen.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/apb_wrappers/acqusition_wrapper.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/apb_wrappers/trck_pkg.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/apb_wrappers/acq_pkg.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/gps_timer/nav_solve_timer.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/top.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/sync.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/spill_register.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/spil_register_flushable.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/gray_to_binary.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/cdc_fifo_gray.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/binary_to_gray.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/xil_fifo.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/trck_top.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/trck_cntrl.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/lock_detector.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/divider.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/cos2x.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/cordic_atan_one_stage.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/cordic_atan_basic.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/cordic_angle_lut.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/code_loop_discriminator.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/cacode_gen_trck.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/bit_gen.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/accum_dump.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/NCO_code.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/NCO_carr.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/LF_code.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/LF_carr.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/twiddle_ram.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/ifft_abs_sqr.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/fft_radix_2.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/dual_port_ram.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/dual_port_bram.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/divider_fsm.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/comp_mult.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/butterfly.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/bram.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_top.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_peak_srch.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_nco_carr.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_corr.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_channel_fast.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_ca_gen.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/gps_timer/nav_solve_timer_pkg.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/afe_top.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/sample_counter.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/sample_align.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/reset_synch.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/double_ff_syn.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/gps_top_pkg.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/definitions.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/plusarg_reader.v|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/SimJTAG.v|
Z101 !s90 +define+PRINTF_COND=0|+define+RANDOMIZE_REG_INIT|+define+RANDOMIZE_MEM_INIT|+define+RANDOM=0|+define+INIT_RANDOM_PROLOG_|-sv|-work|work|-f|/home/ankaoc/Desktop/rocket/rocket-chip/targets/asic/rocket/out/filelists/asic_tb.f|
!i113 0
R17
Z102 !s92 +define+PRINTF_COND=0 +define+RANDOMIZE_REG_INIT +define+RANDOMIZE_MEM_INIT +define+RANDOM=0 +define+INIT_RANDOM_PROLOG_ -sv -work work +incdir+/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
R4
n@queue1_@t@l@bundle@a_a29d64s6k1z2u
vQueue1_TLBundleD_a29d32s7k1z2u
R6
R8
!i10b 1
!s100 K[>C[fbC0;m^FO?_2j`e51
IPK8FhOj9FUgDh^31jRb1M3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleD_a29d32s7k1z2u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue1_TLBundleD_a29d32s7k1z2u.sv
!i122 37
R64
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue1_@t@l@bundle@d_a29d32s7k1z2u
vQueue1_TLBundleD_a29d64s6k1z2u
R6
R97
!i10b 1
!s100 LiSF9VHZZFeUlPS?_afaR3
IVgKd[:joiiFR?9Y>aDb2N1
S1
R1
R98
8/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleD_a29d64s6k1z2u.sv
F/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleD_a29d64s6k1z2u.sv
!i122 24
L0 46 76
R9
R14
r1
!s85 0
31
R99
R100
R101
!i113 0
R17
R102
R4
n@queue1_@t@l@bundle@d_a29d64s6k1z2u
vQueue2_TLBundleA_a14d64s2k1z4u
R6
R8
!i10b 1
!s100 j;QcZW[Dm6TToOKabL89z2
IE02k6oAmMd^1;KUzzMh_A0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv
!i122 37
Z103 L0 31 78
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue2_@t@l@bundle@a_a14d64s2k1z4u
vQueue2_TLBundleA_a29d64s2k1z3u
R6
R8
!i10b 1
!s100 `YZ9EYVPaDW2@aB;QA^Ni2
ITPoHW6]X1VF_RlDmP]mzN1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv
!i122 37
R55
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue2_@t@l@bundle@a_a29d64s2k1z3u
vQueue2_TLBundleA_a32d64s1k1z4u
R6
R8
!i10b 1
!s100 F@5G>f6YmP=Nh6ng4IbQZ2
I^7=^K?Bn5WH2gWK?:h:9I2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv
!i122 37
R55
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue2_@t@l@bundle@a_a32d64s1k1z4u
vQueue2_TLBundleA_a32d64s2k1z3u
R6
R8
!i10b 1
!s100 dPf8Y<6CnAoU1XEW]^;=b0
IT?BJP8SKW>mXeVK1KP_l;2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s2k1z3u.sv
!i122 37
L0 31 75
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue2_@t@l@bundle@a_a32d64s2k1z3u
vQueue2_TLBundleA_a32d64s2k1z4u
R6
R8
!i10b 1
!s100 kG=??5InS6A=b3AHXGc0>1
I48LleHEQj@>ED9=iC2ck51
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv
!i122 37
R55
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue2_@t@l@bundle@a_a32d64s2k1z4u
vQueue2_TLBundleD_a29d64s2k1z3u
R6
R8
!i10b 1
!s100 a6ljl;1P4NWbKWTDA7AG@1
IlSC^hiL?NcVbk0IEMag`63
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv
!i122 37
R103
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue2_@t@l@bundle@d_a29d64s2k1z3u
vQueue2_TLBundleD_a32d64s1k1z4u
R6
R8
!i10b 1
!s100 ]LnX7BdBQe4e8lKGjKCSU1
If80W=L6N4Z1`VmS6hRRe;0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv
!i122 37
R103
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue2_@t@l@bundle@d_a32d64s1k1z4u
vQueue2_TLBundleD_a32d64s2k1z4u
R6
R8
!i10b 1
!s100 Y12[`9RW[81P^`@46Dj^O3
ILVM2zi^AB7EC=LJazdjE]1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv
!i122 37
R103
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue2_@t@l@bundle@d_a32d64s2k1z4u
vQueue2_TLBundleD_a32d8s1k1z4u
R6
R8
!i10b 1
!s100 P`PCZ07:Yo_f5MR[bV0Pk1
IN0eDPjOOa[?1]feFKTH]D1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d8s1k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Queue2_TLBundleD_a32d8s1k1z4u.sv
!i122 37
R63
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@queue2_@t@l@bundle@d_a32d8s1k1z4u
vram_2x10
R6
R8
!i10b 1
!s100 CX7`nX9NHUAS0@61X5:`E2
Imb:R@dgJ^5jSN^h7UDV;X0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x10.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x10.sv
!i122 37
Z104 L0 32 18
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vram_2x115
R6
R8
!i10b 1
!s100 S9nA^7?ic42N13kBfhDfJ3
I3K=WfjGFgI33?2Q=3U7I@2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x115.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x115.sv
!i122 37
R104
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vram_2x120
R6
R8
!i10b 1
!s100 @^b6fY1hl`eKmCZ1HMSXI1
I@@o2]U;bO4k1hZMeJYmN[0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x120.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x120.sv
!i122 37
R104
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vram_2x123
R6
R8
!i10b 1
!s100 iI1Agb6g^;7`C_ER3<^3<2
I?Kk6W_aW0Ml24IVd>Z[bX3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x123.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x123.sv
!i122 37
R104
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vram_2x124
R6
R8
!i10b 1
!s100 NBUaBaO:n4Dg3fF8jDS4d0
ILFX_8B1NERkB62Q>`YWFn3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x124.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x124.sv
!i122 37
R104
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vram_2x77
R6
R8
!i10b 1
!s100 KgQ:M`kKcSN2CdTiHKPUC2
I?Mk4kM[HWhgblKnbZBMHU2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x77.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x77.sv
!i122 37
R104
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vram_2x78
R6
R8
!i10b 1
!s100 i8BZzFYB;C[RcQg:C@;PX1
I5mn4K@EAjDjjhcQ::FCYO3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x78.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x78.sv
!i122 37
R104
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vram_2x99
R6
R8
!i10b 1
!s100 e[iR;5bKNYIgQ7U:^_^SC1
I5k^BT>WL?0k[NjI>h`fmN1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x99.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ram_2x99.sv
!i122 37
R104
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vRecFNToIN
R6
R8
!i10b 1
!s100 ^=L_8D``12CZcKD_jYWfd1
I4iYk`h7`n>P0^^1[jkfI71
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToIN.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToIN.sv
!i122 37
R69
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@rec@f@n@to@i@n
vRecFNToIN_1
R6
R8
!i10b 1
!s100 lLVA?7=lN1@C0>HBnFla50
I@1cB?M`3F[<FXfF5zWZST3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToIN_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToIN_1.sv
!i122 37
L0 31 38
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@rec@f@n@to@i@n_1
vRecFNToRecFN
R6
R8
!i10b 1
!s100 ^kA6EK>YXM0n8ImXnba7:0
IDknE`S9^0NNdlV819PTF03
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToRecFN.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RecFNToRecFN.sv
!i122 37
L0 31 21
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@rec@f@n@to@rec@f@n
vregfile_32x65
R6
R8
!i10b 1
!s100 [G<@g?=KV<jfCj312]iDa1
IW]N:;;g2__UkiFNSQLKo]3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/regfile_32x65.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/regfile_32x65.sv
!i122 37
L0 32 34
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vRepeater_TLBundleA_a12d64s2k1z3u
R6
R8
!i10b 1
!s100 Rd<W9;1lKCA6M@@F?:cLB1
IHhlz1bQR1GAd`MF2:OP;i3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv
!i122 37
Z105 L0 31 53
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@repeater_@t@l@bundle@a_a12d64s2k1z3u
vRepeater_TLBundleA_a17d64s2k1z3u
R6
R8
!i10b 1
!s100 J^Z@2A2bSk=XS<Q5W_Pc61
IG@a_[MS^oeH?M1B=SfBjC2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv
!i122 37
R69
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@repeater_@t@l@bundle@a_a17d64s2k1z3u
vRepeater_TLBundleA_a26d64s2k1z3u
R6
R8
!i10b 1
!s100 A1B<>[Fla6m>GTnEaKF0N2
IA5Q:B5Wj0l<Q8c9c?o];L0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv
!i122 37
R105
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@repeater_@t@l@bundle@a_a26d64s2k1z3u
vRepeater_TLBundleA_a28d64s2k1z3u
R6
R8
!i10b 1
!s100 MEOj@RN6:?E]@SVeS?0643
IH0ebe3dD@XE50RBoPW@K[2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv
!i122 37
R105
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@repeater_@t@l@bundle@a_a28d64s2k1z3u
vRepeater_TLBundleA_a29d32s2k1z3u
R6
R8
!i10b 1
!s100 ^X;ijEb6cWN6M52^aD0Oz0
Ik:`6mFdPZ8BgnB;OG[7Yl1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv
!i122 37
R46
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@repeater_@t@l@bundle@a_a29d32s2k1z3u
vRepeater_TLBundleA_a29d64s2k1z3u
R6
R8
!i10b 1
!s100 FZIXhY?2heKeRjWIZS;nb2
Im4Se1:8kndTJIfgeYdliB0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv
!i122 37
R105
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@repeater_@t@l@bundle@a_a29d64s2k1z3u
vRepeater_TLBundleA_a29d64s2k1z3u_2
R6
R8
!i10b 1
!s100 I5:?mXL`kPbiMUfQ[RO330
I>M:abc<E1aR99CKD]RfJP3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_2.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_2.sv
!i122 37
R44
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@repeater_@t@l@bundle@a_a29d64s2k1z3u_2
vRepeater_TLBundleA_a32d64s2k1z3u
R6
R8
!i10b 1
!s100 DBEoc[h9ReP<Le83DS1Ko1
I00h>1K98RCQ:z1U[2dQiD2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a32d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleA_a32d64s2k1z3u.sv
!i122 37
R59
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@repeater_@t@l@bundle@a_a32d64s2k1z3u
vRepeater_TLBundleD_a32d64s1k1z4u
R6
R8
!i10b 1
!s100 [z=NjW;JVm:f<C:KnbQ2R3
IFc0^0FJkh=V?5G3WFK6jz3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv
!i122 37
L0 31 61
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@repeater_@t@l@bundle@d_a32d64s1k1z4u
vreset_synch
R6
R8
!i10b 1
!s100 =OSczUj>z]V`OhMdd@5362
ImJMncAGdHl8PFCVTeFiXb1
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/reset_synch.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/reset_synch.sv
!i122 37
L0 21 49
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vResetCatchAndSync_d3
R6
R8
!i10b 1
!s100 bbK[6Ld`@IY[HM1<n<Ao>3
I6[:^oB9D1^EC:_P<Am=NV3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ResetCatchAndSync_d3.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ResetCatchAndSync_d3.sv
!i122 37
L0 31 15
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@reset@catch@and@sync_d3
vrf_31x64
R6
R8
!i10b 1
!s100 PA6FF8[kOh;Q8jogZUi>G1
IhjCz8B4c5lAHB86:nhH970
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rf_31x64.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rf_31x64.sv
!i122 37
L0 32 23
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vRocket
R6
R8
!i10b 1
!s100 zn?J`5VNb3bB5eeQ[9Izz2
I`?GlMdn=OHCIRa<b@9WA<1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Rocket.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/Rocket.sv
!i122 37
L0 31 3202
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@rocket
vRocketALU
R6
R8
!i10b 1
!s100 @m^NL`mbXZB4ZKT>BYXg92
I5nRG:9Dz=R^hbhXM0iV=U0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RocketALU.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RocketALU.sv
!i122 37
L0 31 139
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@rocket@a@l@u
vRocketTile
R6
R8
!i10b 1
!s100 669W=^0fSJ]6CY1J>KMO>2
I7cz<IT==7@>306V1n0G:F3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RocketTile.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RocketTile.sv
!i122 37
L0 31 1629
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@rocket@tile
vrockettile_dcache_data_arrays_0_131072x64
R6
R8
!i10b 1
!s100 HPDBk^P[?:EmGHiThb@:51
Im5T<RRh8YE>68UI=;n8f_3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv
!i122 37
L0 32 37
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vrockettile_icache_data_arrays_512x32
R6
R8
!i10b 1
!s100 kfBf=CThBb`znW;LO15[83
I`aNF1^jeRzDNT7zZMM^[Q2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_icache_data_arrays_512x32.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_icache_data_arrays_512x32.sv
!i122 37
Z106 L0 32 22
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vrockettile_icache_tag_array_0_64x21
R6
R8
!i10b 1
!s100 MTBGT^SSF@;7L00UANW>30
I5db:>:W13n;gKk6EUhgMY3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_icache_tag_array_0_64x21.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/rockettile_icache_tag_array_0_64x21.sv
!i122 37
R106
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vrockettile_icache_tag_array_64x21
R6
!s110 1783113123
!i10b 1
!s100 m4>0bm>;^nkcLOc8PXkD53
IdCMC<FcAjEoF_k3i:I7792
S1
R1
w1783113122
8/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rockettile_icache_tag_array_64x21.sv
F/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rockettile_icache_tag_array_64x21.sv
!i122 29
L0 60 43
R9
R14
r1
!s85 0
31
!s108 1783113123.000000
!s107 /home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/registers.svh|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/asic_rocket_tb.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/uart/uart_rx_model.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/uart/uart_console_model.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/sram/asic_sram_1rw.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/sram/asic_sram_1r1w.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/flash/spi_flash_model.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/clock/asic_pll_model.sv|/home/ankaoc/Desktop/rocket/rocket-chip/targets/asic/rocket/out/generated/asic_rocket_top_sim.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rockettile_icache_tag_array_64x21.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rockettile_icache_data_arrays_512x32.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rockettile_dcache_data_arrays_0_131072x64.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/rf_31x64.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/regfile_32x65.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x99.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x78.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x77.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x124.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x123.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x120.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x115.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ram_2x10.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/bootromClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/VCU118RocketSystem.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TilePRCIDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_pbus_out_i1_o3_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_dmixbar_i1_o2_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8_4.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8_3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8_2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget8.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLWidthWidget1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLToAPB.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLROM.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLPLIC.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_pbus_to_gps.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_plic.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_debug.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_clint.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_bootrom.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_PLIC.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_FPGAUART.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_FPGAGPS.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_Debug.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_CLINT.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFragmenter_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFpgaUART.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFpgaSPI.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFIFOFixer_2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFIFOFixer_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLFIFOFixer.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLError_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLError.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleOuterAsync.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleOuter.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleInnerAsync.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModuleInner.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLDebugModule.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBusBypassBar.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBusBypass.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z4u_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z3u_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s1k1z4u_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLBuffer_a14d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAtomicAutomata_pbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAtomicAutomata_cbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAsyncCrossingSource_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/TLAsyncCrossingSink_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/SystemBus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/SynchronizerShiftReg_w1_d3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ShiftQueue.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ScratchpadSlavePort.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/SBToTL.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundRawFNToRecFN_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundRawFNToRecFN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_4.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RoundAnyRawFNToRecFN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RocketTile.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RocketALU.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Rocket.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a32d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a29d64s2k1z3u_2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RecFNToRecFN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RecFNToIN_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RecFNToIN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/RVCExpander.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a32d8s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a32d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleD_a29d32s7k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleA_a29d32s7k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_RegMapperInput_i9_m8.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Queue1_RegMapperInput_i23_m8.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PlusArgTimeout.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PeripheryBus_pbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PeripheryBus_cbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PTW.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PMPChecker_s3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PMPChecker_s2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PMAChecker.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PLICFanIn.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/PLICClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/OptimizationBarrier_TLBEntryData.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulDiv.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_preMul_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_preMul.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_postMul_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNToRaw_postMul.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNPipe_l2_e8_s24.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/MulAddRecFNPipe_l2_e11_s53.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/LevelGateway.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/JtagTapController.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/JtagStateMachine.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/JtagBypassChain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntXbar_i3_o1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntXbar_i1_o1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntToFP.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncSyncCrossingSink_n1x2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncSyncCrossingSink_n1x1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncCrossingSource_n1x2.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncCrossingSource_n1x1_Registered.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncCrossingSource_n1x1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IntSyncAsyncCrossingSink_n1x1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ITLB.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/INToRecFN_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/INToRecFN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ICache.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/IBuf.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/HierarchicalElementResetDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/HellaCacheArbiter.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Frontend.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FrontBus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_5.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_4.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_3.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FixedClockBroadcast_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPUFMAPipe_l4_f64.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPUFMAPipe_l3_f32.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPUDecoder.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPU.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPToInt.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPToFP.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPGAUARTClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPGASPIClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/FPGAGPSClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ErrorDeviceWrapper.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFN_small_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFN_small.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFNToRaw_small_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRecFNToRaw_small.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRawFN_small_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DivSqrtRawFN_small.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DebugTransportModuleJTAG.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DTLB.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DMIToTL.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DCacheDataArray.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/DCache.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CompareRecFN.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_sbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_pbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_cbus.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroupAggregator_aggregator.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockGroup.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockCrossingReg_w55.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockCrossingReg_w43.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/ClockCrossingReg_w15.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureUpdateChain_UInt5_To_UInt5.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureUpdateChain_DTMInfo_To_DTMInfo.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CaptureChain_JTAGIdcodeBundle.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CSRFile.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CLINTClockSinkDomain.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/CLINT.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/BreakpointUnit.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncValidSync.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetRegVec_w2_i0.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncResetRegVec_w1_i0.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSource_TLBundleD_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSource_TLBundleA_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSource_DebugInternalBundle.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSink_TLBundleD_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSink_TLBundleA_a9d32s1k1z2u.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AsyncQueueSink_DebugInternalBundle.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Arbiter8_DCacheMetadataReq.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Arbiter4_DCacheDataReq.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/Arbiter3_LLWB.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/APBGpsBlock.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-sim-verilog/AMOALU.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/apb_wrappers/tracking_wrapper.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/apb_wrappers/pulse_gen.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/apb_wrappers/acqusition_wrapper.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/apb_wrappers/trck_pkg.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/apb_wrappers/acq_pkg.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/gps_timer/nav_solve_timer.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/top.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/sync.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/spill_register.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/spil_register_flushable.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/gray_to_binary.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/cdc_fifo_gray.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/pulp_fifo/binary_to_gray.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/xil_fifo.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/trck_top.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/trck_cntrl.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/lock_detector.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/divider.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/cos2x.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/cordic_atan_one_stage.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/cordic_atan_basic.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/cordic_angle_lut.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/code_loop_discriminator.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/cacode_gen_trck.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/bit_gen.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/accum_dump.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/NCO_code.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/NCO_carr.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/LF_code.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/trck_src/LF_carr.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/twiddle_ram.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/ifft_abs_sqr.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/fft_radix_2.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/dual_port_ram.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/dual_port_bram.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/divider_fsm.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/comp_mult.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/butterfly.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/bram.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_top.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_peak_srch.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_nco_carr.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_corr.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_channel_fast.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/acq_src/acq_ca_gen.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/gps_timer/nav_solve_timer_pkg.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/afe_top.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/sample_counter.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/sample_align.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/reset_synch.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/double_ff_syn.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/gps_top_pkg.sv|/home/ankaoc/Desktop/anka-rocket/gps_system/common/definitions.sv|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/plusarg_reader.v|/home/ankaoc/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/SimJTAG.v|
R101
!i113 0
R17
R102
R4
vRoundAnyRawFNToRecFN
R6
R8
!i10b 1
!s100 h^7g:;F3d<D70nQTa0mCC2
I^Q::ef<98IaWagkPXWoSO3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN.sv
!i122 37
L0 31 103
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@round@any@raw@f@n@to@rec@f@n
vRoundAnyRawFNToRecFN_1
R6
R8
!i10b 1
!s100 Wf6F9gN>bf1a]1<dJWDLJ1
IgQ[`SHK6JD9T2DYEF9b`c3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_1.sv
!i122 37
R94
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@round@any@raw@f@n@to@rec@f@n_1
vRoundAnyRawFNToRecFN_2
R6
R8
!i10b 1
!s100 K^bZacZN41]5@MD;DkjIo3
I0N;POQNU[7M]K@4KcKeDz2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_2.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_2.sv
!i122 37
L0 31 27
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@round@any@raw@f@n@to@rec@f@n_2
vRoundAnyRawFNToRecFN_3
R6
R8
!i10b 1
!s100 W@Jcez7X9g3O5IP4OlI;;0
IbL=eTgTmCFjb25a]2>4@L0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_3.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_3.sv
!i122 37
R58
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@round@any@raw@f@n@to@rec@f@n_3
vRoundAnyRawFNToRecFN_4
R6
R8
!i10b 1
!s100 Z03<fomaz@7Z?c@doV58h3
I456FTXYbka[Z=dES6Jam<1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_4.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundAnyRawFNToRecFN_4.sv
!i122 37
L0 31 133
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@round@any@raw@f@n@to@rec@f@n_4
vRoundRawFNToRecFN
R6
R8
!i10b 1
!s100 X1Qe[oO37j^Z7ia:RU=Kj1
Ij@YJ>z5h=95ng>MP^BDgN2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundRawFNToRecFN.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundRawFNToRecFN.sv
!i122 37
R47
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@round@raw@f@n@to@rec@f@n
vRoundRawFNToRecFN_1
R6
R8
!i10b 1
!s100 ea3=_n6W[ZXWDefRUfhLF3
IbVC_HVW0QSKD7_ZijNlo33
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundRawFNToRecFN_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RoundRawFNToRecFN_1.sv
!i122 37
R47
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@round@raw@f@n@to@rec@f@n_1
vRVCExpander
R6
R8
!i10b 1
!s100 ?TlI=j7@eS9VhjBZ<j[8K2
I51UN1EE92kbg;X2DLRf7B2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RVCExpander.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/RVCExpander.sv
!i122 37
L0 31 362
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@r@v@c@expander
vsample_align
R6
R7
DXx4 work 20 sample_align_sv_unit 0 22 @ZdMM`R@>1de7n[iN809<1
R8
R9
r1
!s85 0
!i10b 1
!s100 E@85PlGUWhNe3chLYld7b3
I5SczDiNWNRWJ^chTSKY[M0
!s105 sample_align_sv_unit
S1
R10
R11
Z107 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/sample_align.sv
Z108 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/sample_align.sv
!i122 37
L0 23 56
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xsample_align_sv_unit
R6
R7
R8
V@ZdMM`R@>1de7n[iN809<1
r1
!s85 0
!i10b 1
!s100 ezPeeBIUL8956VE`hQD<c2
I@ZdMM`R@>1de7n[iN809<1
!i103 1
S1
R10
R11
R107
R108
!i122 37
R26
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vsample_counter
R6
R6
R7
DXx4 work 22 sample_counter_sv_unit 0 22 XSFjaT[IN4emhDn?=A`@Y3
R8
R9
r1
!s85 0
!i10b 1
!s100 RNnd96A7zEiKk5H`nnTQb0
Il_bSm9;CJ<kIh=MHC_o:32
!s105 sample_counter_sv_unit
S1
R10
R11
Z109 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/sample_counter.sv
Z110 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/common/sample_counter.sv
!i122 37
L0 3 72
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xsample_counter_sv_unit
R6
R6
R7
R8
VXSFjaT[IN4emhDn?=A`@Y3
r1
!s85 0
!i10b 1
!s100 D5hoJomW7KMO`b:]c?1ZA3
IXSFjaT[IN4emhDn?=A`@Y3
!i103 1
S1
R10
R11
R109
R110
!i122 37
R19
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vSBToTL
R6
R8
!i10b 1
!s100 ^z[31j2?1McB74hhz?OQ43
IzePn_PWW38o8b[jdh?;SS0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SBToTL.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SBToTL.sv
!i122 37
L0 31 162
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@s@b@to@t@l
vScratchpadSlavePort
R6
R8
!i10b 1
!s100 FaY;c@HlbUjYdB@4jhCS;1
IYh:mAJQe1@1J9Wo<B7>E[2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ScratchpadSlavePort.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ScratchpadSlavePort.sv
!i122 37
L0 31 135
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@scratchpad@slave@port
vShiftQueue
R6
R8
!i10b 1
!s100 Yz07Q[@;7fbcb0Q;ADPQG2
I?kGW0In;0M[P3DLo:DX_V2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ShiftQueue.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/ShiftQueue.sv
!i122 37
L0 31 141
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@shift@queue
vSimJTAG
R6
DXx4 work 14 SimJTAG_v_unit 0 22 >9ddlf61@iEgCTj;e;M7i0
R38
R9
r1
!s85 0
!i10b 1
!s100 _;fIe^I:cWC@S4SjZL[1U2
IlE`m[Z:=ZaEj[gLT[I6Pc2
!s105 SimJTAG_v_unit
S1
R10
R93
Z111 8/home/onur/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/SimJTAG.v
Z112 F/home/onur/Desktop/rocket/rocket-chip/hardware/upstream/rocket-chip/src/main/resources/vsrc/SimJTAG.v
!i122 35
L0 13 72
R14
31
R39
R40
R41
!i113 0
R17
R42
R4
n@sim@j@t@a@g
XSimJTAG_v_unit
R6
R38
V>9ddlf61@iEgCTj;e;M7i0
r1
!s85 0
!i10b 1
!s100 G_ERn_dzYUP=hc_U<jVPU2
I>9ddlf61@iEgCTj;e;M7i0
!i103 1
S1
R10
R93
R111
R112
!i122 35
R32
R14
31
R39
R40
R41
!i113 0
R17
R42
R4
n@sim@j@t@a@g_v_unit
vspi_flash_model
R6
R38
!i10b 1
!s100 LA`mmg:BhBPFLFIef88?<0
Ij`icZCXO3ZC`Cen1of:oK0
S1
R10
w1782982818
8/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/flash/spi_flash_model.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/flash/spi_flash_model.sv
!i122 35
L0 3 91
R9
R14
r1
!s85 0
31
R39
R40
R41
!i113 0
R17
R42
R4
vspill_register
R6
R8
!i10b 1
!s100 5AHhK:3fMddFXaXKF@=G40
IfmIN:5Gn36jNKKh_<N3Ih2
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/spill_register.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/spill_register.sv
!i122 37
L0 17 30
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vspill_register_flushable
R6
R8
!i10b 1
!s100 aT8HQ?L^z?D:P_iY_PMN]0
IVb0n5amohC`JgIoG0BElh1
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/spil_register_flushable.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/spil_register_flushable.sv
!i122 37
L0 17 89
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vsync
R6
R8
!i10b 1
!s100 9dU3GhHW:;P6i09`9158;0
IFQamZ[[SZ@5Tn=WEk8AW82
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/sync.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/sync.sv
!i122 37
L0 13 25
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vSynchronizerShiftReg_w1_d3
R6
R8
!i10b 1
!s100 PM_1<hcDR8kV_R=izNbVl3
IWc7Vic[Ad6]?[gKL2:4Q53
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SynchronizerShiftReg_w1_d3.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SynchronizerShiftReg_w1_d3.sv
!i122 37
R36
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@synchronizer@shift@reg_w1_d3
vSystemBus
R6
R8
!i10b 1
!s100 =NYUecl3NbJmU5hU_YV9?3
ISb=R_M6ThZ@kG4^^>@H6F0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SystemBus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/SystemBus.sv
!i122 37
L0 31 960
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@system@bus
vTilePRCIDomain
R6
R8
!i10b 1
!s100 BLi^OWBV@;1oa^IZ`9`2k0
I`4;NEGdzdYg[h2>8?S<oh3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TilePRCIDomain.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TilePRCIDomain.sv
!i122 37
L0 31 388
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@tile@p@r@c@i@domain
vTLAsyncCrossingSink_a9d32s1k1z2u
R6
R8
!i10b 1
!s100 C6UOVA]9no2>fRh3o;=i00
I822_ail2B7mQ74Z[83?lA3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAsyncCrossingSink_a9d32s1k1z2u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAsyncCrossingSink_a9d32s1k1z2u.sv
!i122 37
L0 31 80
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@async@crossing@sink_a9d32s1k1z2u
vTLAsyncCrossingSource_a9d32s1k1z2u
R6
R8
!i10b 1
!s100 9l6H4ZBbSjOi<GYB<Pa1h0
IA^mNzLRjS_>ai1e3aEM183
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAsyncCrossingSource_a9d32s1k1z2u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAsyncCrossingSource_a9d32s1k1z2u.sv
!i122 37
L0 31 74
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@async@crossing@source_a9d32s1k1z2u
vTLAtomicAutomata_cbus
R6
R8
!i10b 1
!s100 5:EN6bBNROz=Y:7:1KKBf2
I>XgXRo=H0SCdNBBY>1S6D1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAtomicAutomata_cbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAtomicAutomata_cbus.sv
!i122 37
L0 31 575
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@atomic@automata_cbus
vTLAtomicAutomata_pbus
R6
R8
!i10b 1
!s100 2H_eh>Woc:=QJXJPm>2Z`0
In6KiLm0SoGOBQ`6MJSo5o1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAtomicAutomata_pbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLAtomicAutomata_pbus.sv
!i122 37
L0 31 540
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@atomic@automata_pbus
vTLBuffer_a14d64s2k1z4u
R6
R8
!i10b 1
!s100 E5GD@=;hGMD<A[`@ITX691
IiB_EPgLz=@YL3VTFJaj>A1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a14d64s2k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a14d64s2k1z4u.sv
!i122 37
R95
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@buffer_a14d64s2k1z4u
vTLBuffer_a29d64s2k1z3u
R6
R8
!i10b 1
!s100 7F8ncmd6=<FR??lFN><:V0
Io8^[S`_QYKA^>eiO3KF5L3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a29d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a29d64s2k1z3u.sv
!i122 37
Z113 L0 31 122
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@buffer_a29d64s2k1z3u
vTLBuffer_a32d64s1k1z4u
R6
R8
!i10b 1
!s100 ^_cb8@:4P]d;XMFA4YZ:g0
I:bOm>Kl4kOa5B2F0TifP<0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s1k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s1k1z4u.sv
!i122 37
R113
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@buffer_a32d64s1k1z4u
vTLBuffer_a32d64s1k1z4u_1
R6
R8
!i10b 1
!s100 QQZ6COKlD_KRJBfg;DzZE1
I77TiJFB1I<@776<>f5CXi1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s1k1z4u_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s1k1z4u_1.sv
!i122 37
R95
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@buffer_a32d64s1k1z4u_1
vTLBuffer_a32d64s2k1z3u
R6
R8
!i10b 1
!s100 l_=<Vo@R`Pa26]1OjRSW31
I0L8Gi^8Qkh`CfEd;R;>eB1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z3u.sv
!i122 37
R72
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@buffer_a32d64s2k1z3u
vTLBuffer_a32d64s2k1z3u_1
R6
R8
!i10b 1
!s100 ][^:Zl[TjTYReH>QnlQ4X2
IKeCPJfJBdRY8oLH985AX10
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z3u_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z3u_1.sv
!i122 37
L0 31 88
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@buffer_a32d64s2k1z3u_1
vTLBuffer_a32d64s2k1z4u
R6
R8
!i10b 1
!s100 G63FO8^5[kcFg32X<kJW@0
I3BC;fM>2E^2b8aD;bPO@93
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z4u.sv
!i122 37
R113
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@buffer_a32d64s2k1z4u
vTLBuffer_a32d64s2k1z4u_1
R6
R8
!i10b 1
!s100 odd25neNEV:ZoS[8X>QM[2
Ibm7==Vf^iH?j=aNOX?DMY0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv
!i122 37
R95
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@buffer_a32d64s2k1z4u_1
vTLBusBypass
R6
R8
!i10b 1
!s100 ?:RoG7AIhHRf6LjOnmzHB0
IloVoU]43fRJTb]XbVj]aR2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBusBypass.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBusBypass.sv
!i122 37
R79
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@bus@bypass
vTLBusBypassBar
R6
R8
!i10b 1
!s100 9KJ4`[^<W49gM1o>f<9G[2
Ih[<IZ@1_`NEKlJe>;6]jo1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBusBypassBar.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLBusBypassBar.sv
!i122 37
L0 31 91
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@bus@bypass@bar
vTLDebugModule
R6
R8
!i10b 1
!s100 alh^kTCQEkRn3o0ko>96S2
IT:ZjAAi_3c4Llf;zG[IJ_3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModule.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModule.sv
!i122 37
L0 31 222
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@debug@module
vTLDebugModuleInner
R6
R8
!i10b 1
!s100 3AQAX4J?DnMEzMN=<Mn@Q2
In9?l=<85;DhgSXY7f[:^P2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleInner.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleInner.sv
!i122 37
L0 31 5083
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@debug@module@inner
vTLDebugModuleInnerAsync
R6
R8
!i10b 1
!s100 HogC5K0lTc>FM>PQk>?Rd1
ICiCo@5eA?>3m;BH;E:DZZ2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleInnerAsync.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleInnerAsync.sv
!i122 37
L0 31 219
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@debug@module@inner@async
vTLDebugModuleOuter
R6
R8
!i10b 1
!s100 >g`d6bFF3Cih7iKeEncoM0
I^9;KCI@dR]37eHQ^dlKhX0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuter.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuter.sv
!i122 37
R68
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@debug@module@outer
vTLDebugModuleOuterAsync
R6
R8
!i10b 1
!s100 aLb]W^X7BIEHaaM8TGAi>1
ImjM5B:`ko[_DgGOb249W13
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuterAsync.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLDebugModuleOuterAsync.sv
!i122 37
R74
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@debug@module@outer@async
vTLError
R6
R8
!i10b 1
!s100 TD^kkU38<VGz^f1VUD?Ni1
IFNb<=J?_S_:_nKMCfL@W]2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLError.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLError.sv
!i122 37
R86
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@error
vTLError_1
R6
R8
!i10b 1
!s100 OEKiaQCQ5O6CU?=i`S87D3
I?HNc_9d1m>SKLCNQDN>zC3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLError_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLError_1.sv
!i122 37
R73
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@error_1
vTLFIFOFixer
R6
R8
!i10b 1
!s100 MWN0Wl`nT>g4L>bJ0jzBU2
I7e5;>KnQ879?GlK>jOTzN1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer.sv
!i122 37
L0 31 177
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@f@i@f@o@fixer
vTLFIFOFixer_1
R6
R8
!i10b 1
!s100 kAh4aRC42[TAK=zBnG^cQ3
IVEKH>8UAin_nzU?Pl09Db3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer_1.sv
!i122 37
Z114 L0 31 92
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@f@i@f@o@fixer_1
vTLFIFOFixer_2
R6
R8
!i10b 1
!s100 MFj^jbW^_bo`QA:3^m>943
IT6K9G8KXNN?K4SF``]zd73
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer_2.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFIFOFixer_2.sv
!i122 37
R114
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@f@i@f@o@fixer_2
vTLFpgaSPI
R6
R8
!i10b 1
!s100 >gTEYF2H]VcjE:iPKkL=F2
I6jcVEUYVIBjo<1XnSdCZP0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaSPI.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaSPI.sv
!i122 37
L0 31 138
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@fpga@s@p@i
vTLFpgaUART
R6
R8
!i10b 1
!s100 `[SJAII8K7[nMfkMOD=KA3
IzA:io2Qc6zH@ThPEN?_GA2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaUART.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFpgaUART.sv
!i122 37
L0 31 192
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@fpga@u@a@r@t
vTLFragmenter_1
R6
R8
!i10b 1
!s100 BQHo`WogbDcBm_JgbA]910
IGEZTfbWjW2b;72Mib1aG>1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_1.sv
!i122 37
L0 31 159
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@fragmenter_1
vTLFragmenter_bootrom
R6
R8
!i10b 1
!s100 l7SUO1:bGEBh^1doO^fGi1
IV^LLFUlLDBng<D>`<hO6g0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_bootrom.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_bootrom.sv
!i122 37
Z115 L0 31 124
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@fragmenter_bootrom
vTLFragmenter_CLINT
R6
R8
!i10b 1
!s100 :Ac4b0^JTj2i=h@>eL=J60
INlEeV4NWA[D4o42cInK@b2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_CLINT.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_CLINT.sv
!i122 37
R77
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@fragmenter_@c@l@i@n@t
vTLFragmenter_Debug
R6
R8
!i10b 1
!s100 NG:DLgLknR:`z^fLKKo1o3
I8C;nYR7][Gm<khCDE5W:f1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_Debug.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_Debug.sv
!i122 37
R77
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@fragmenter_@debug
vTLFragmenter_FPGAGPS
R6
R8
!i10b 1
!s100 W5zk=]Y`hoEh9nzF>=D853
I7mUdUZ8mlaF^a_aZ2Ehki0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_FPGAGPS.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_FPGAGPS.sv
!i122 37
L0 31 237
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@fragmenter_@f@p@g@a@g@p@s
vTLFragmenter_FPGAUART
R6
R8
!i10b 1
!s100 NX?g2HV7FFWDKaTQ]b;Um3
IJ`oQC2h7CD30ed2NXVO<;3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_FPGAUART.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_FPGAUART.sv
!i122 37
R77
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@fragmenter_@f@p@g@a@u@a@r@t
vTLFragmenter_PLIC
R6
R8
!i10b 1
!s100 S=;a0@<73KDPdRm95`<DN1
IcOJo[_ZMMc=4^KO^M^1@10
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_PLIC.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLFragmenter_PLIC.sv
!i122 37
R77
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@fragmenter_@p@l@i@c
vTLInterconnectCoupler_cbus_to_bootrom
R6
R8
!i10b 1
!s100 Hk7GR_WoT?EihK0>VC5mU0
I[`;`nZeUkUNzWQlacY_ME1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv
!i122 37
R92
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_cbus_to_bootrom
vTLInterconnectCoupler_cbus_to_bus_named_pbus
R6
R8
!i10b 1
!s100 30hV`PPMgz82PElCz0_3l2
IZRDOKj8RER7T9^EQSQl:e0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv
!i122 37
Z116 L0 31 128
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_cbus_to_bus_named_pbus
vTLInterconnectCoupler_cbus_to_clint
R6
R8
!i10b 1
!s100 kozX<3MWZBMlXFV0LR0KN3
IMEG@<7`dI6XmLSniiH>Li3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv
!i122 37
Z117 L0 31 66
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_cbus_to_clint
vTLInterconnectCoupler_cbus_to_debug
R6
R8
!i10b 1
!s100 KOMFiR7GP?ohN[<=c`<G^1
IL2mjR[<al>j8`2Tg66?SW0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv
!i122 37
R117
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_cbus_to_debug
vTLInterconnectCoupler_cbus_to_plic
R6
R8
!i10b 1
!s100 l:KZ[d`1NXmZRE;>dQ6Mg1
If4BWNX3Oa8PN7F>_BIVn_1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv
!i122 37
R117
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_cbus_to_plic
vTLInterconnectCoupler_cbus_to_rockettile
R6
R8
!i10b 1
!s100 ?F]ZmBF;j^agi3gPdc8I32
I5C3?PS3aM0_jZA1:`d_8J1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv
!i122 37
R52
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_cbus_to_rockettile
vTLInterconnectCoupler_fbus_from_debug_sb
R6
R8
!i10b 1
!s100 hD^azf8Dl>0iV7JJN;Jmb2
ITJ`FQFWNXe<mI3TEY]<d`0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv
!i122 37
L0 31 72
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_fbus_from_debug_sb
vTLInterconnectCoupler_pbus_to_fpga_uart
R6
R8
!i10b 1
!s100 LT7YOGaNHQ6i3[J_X4]=11
I1cS5g6ae6aaRF>43KP;;K2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv
!i122 37
R117
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_pbus_to_fpga_uart
vTLInterconnectCoupler_pbus_to_gps
R6
R8
!i10b 1
!s100 T[oaCdDS[i38l08SYI[Sh3
I8a]=05?a]YW?^mZTo7fDO1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv
!i122 37
L0 31 267
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_pbus_to_gps
vTLInterconnectCoupler_sbus_from_bus_named_fbus
R6
R8
!i10b 1
!s100 3ba]OMBDQ8bIfPhW95>E>1
I?oO[fBL0``0QeT9e4]3oZ0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv
!i122 37
R115
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_sbus_from_bus_named_fbus
vTLInterconnectCoupler_sbus_from_rockettile
R6
R8
!i10b 1
!s100 3@>8mNk6j0ZkeNjEgj8z83
IP^WWcm6Q6aRzU2Ie>5OWG1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv
!i122 37
R114
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_sbus_from_rockettile
vTLInterconnectCoupler_sbus_to_bus_named_cbus
R6
R8
!i10b 1
!s100 ?4X]HHkaSS5jIWKHVk7So1
IYC7m0NSQE@3OJ04XVf6Eh3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv
!i122 37
R116
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@interconnect@coupler_sbus_to_bus_named_cbus
vTLPLIC
R6
R8
!i10b 1
!s100 o[JkJ[<URP>GoI<6;BaR02
IET_7a_?eojEnhU5bfe;E50
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLPLIC.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLPLIC.sv
!i122 37
L0 31 380
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@p@l@i@c
vTLROM
R6
R8
!i10b 1
!s100 Cf3]^CeiDe4GUFJZE;Jiz3
IS>d2;;S>OjA_5LA0:X6dS3
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLROM.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLROM.sv
!i122 37
L0 31 277
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@r@o@m
vTLToAPB
R6
R8
!i10b 1
!s100 0ff_LnR^7fWN:oIe>21mm1
IAADLLLaUibNmhHE9062`53
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLToAPB.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLToAPB.sv
!i122 37
L0 31 130
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@to@a@p@b
vTLWidthWidget1
R6
R8
!i10b 1
!s100 RBKF>KgXZcKEcABFML[S_3
IaY`iHng5o>d6XgU1Daj>;0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget1.sv
!i122 37
R62
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@width@widget1
vTLWidthWidget8
R6
R8
!i10b 1
!s100 aOg^61TSe>dT:zNL6f2e^1
Iz@FY62><jgbJEdlmc?WnH0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8.sv
!i122 37
R114
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@width@widget8
vTLWidthWidget8_1
R6
R8
!i10b 1
!s100 LAl1P]QjY1@@oN1ZkKP[e3
I3?^h7>ioG[eVS9C7RTFME1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_1.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_1.sv
!i122 37
R70
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@width@widget8_1
vTLWidthWidget8_2
R6
R8
!i10b 1
!s100 :^eOLg1SA`]@L^XWWe4Yh0
IQZ5cKeXU[]cHoz6D1YJ890
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_2.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_2.sv
!i122 37
L0 31 179
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@width@widget8_2
vTLWidthWidget8_3
R6
R8
!i10b 1
!s100 RYBjh5mT23VfJRhP@1[3N1
IKWSGai7TnO9<>G7N<]Q]40
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_3.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_3.sv
!i122 37
R114
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@width@widget8_3
vTLWidthWidget8_4
R6
R8
!i10b 1
!s100 `26M7<di<anW@Tz[GPgYk3
I4nR9HM?IcWJ2F=[XP4HJO0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_4.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLWidthWidget8_4.sv
!i122 37
R96
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@width@widget8_4
vTLXbar_cbus_in_i1_o1_a32d64s2k1z4u
R6
R8
!i10b 1
!s100 W1@8z_LARV0i0eCHd?m3H2
I;z7>53]P;D?z7YHB]Ua_n2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv
!i122 37
R114
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@xbar_cbus_in_i1_o1_a32d64s2k1z4u
vTLXbar_cbus_out_i1_o7_a32d64s2k1z4u
R6
R8
!i10b 1
!s100 ?;0F6Lji_R?e5@HUZ@6L?3
IcBoK^NNzNWBe`m<G=>:[@1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv
!i122 37
L0 31 479
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@xbar_cbus_out_i1_o7_a32d64s2k1z4u
vTLXbar_dmixbar_i1_o2_a9d32s1k1z2u
R6
R8
!i10b 1
!s100 V_2Q;7KK1OkP<LAjNkGiN0
I@2DNNaHn1j@oJ9NMT7T]G0
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_dmixbar_i1_o2_a9d32s1k1z2u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_dmixbar_i1_o2_a9d32s1k1z2u.sv
!i122 37
R113
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@xbar_dmixbar_i1_o2_a9d32s1k1z2u
vTLXbar_fbus_i1_o1_a32d64s1k1z4u
R6
R8
!i10b 1
!s100 2AF9CoVj?X;`1MJCg5CI@0
IY@G80l`NCc;PbhUAPaH<41
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv
!i122 37
R92
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@xbar_fbus_i1_o1_a32d64s1k1z4u
vTLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u
R6
R8
!i10b 1
!s100 ;_WjZnPLfKW8>2]GX46gN2
IP9M[MRlHlD@ZXAnG:aR<]2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv
!i122 37
L0 31 220
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@xbar_@master@xbar_@rocket@tile_i2_o1_a32d64s1k1z4u
vTLXbar_pbus_in_i1_o1_a29d64s2k1z3u
R6
R8
!i10b 1
!s100 mgnid1<kPVRGORdz:=iAM2
IER7TIQaMVm2K1Cd]^5Io^1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv
!i122 37
R114
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@xbar_pbus_in_i1_o1_a29d64s2k1z3u
vTLXbar_pbus_out_i1_o3_a29d64s2k1z3u
R6
R8
!i10b 1
!s100 7oz<_3CJ;BIX:z8>Mjee=1
I5Q8_P51P<a_[E>I6iXYYD2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_pbus_out_i1_o3_a29d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_pbus_out_i1_o3_a29d64s2k1z3u.sv
!i122 37
L0 31 245
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@xbar_pbus_out_i1_o3_a29d64s2k1z3u
vTLXbar_sbus_i2_o1_a32d64s2k1z4u
R6
R8
!i10b 1
!s100 UG85]93>X467hY3gnihPL3
I8LPKW0^`@lbIbG_XH@nQ;1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv
!i122 37
L0 31 226
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@xbar_sbus_i2_o1_a32d64s2k1z4u
vTLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u
R6
R8
!i10b 1
!s100 QcA_DUJIW7@>nLlA>1TSS0
I]Po2f[B]bnla7oIZ<hn_L1
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv
!i122 37
R72
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@t@l@xbar_@slave@xbar_@rocket@tile_i1_o1_a32d64s2k1z3u
vtop
R6
R8
!i10b 1
!s100 BgYTi<jIPMb<K;39_VTb70
IM1LD]C>jRYPQ[Q<Qgk2B30
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/top.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/pulp_fifo/top.sv
!i122 37
L0 23 161
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vtracking_wrapper
R6
R6
R7
DXx4 work 24 tracking_wrapper_sv_unit 0 22 f50n0]ER3iPW27XY;19711
R6
R31
DXx4 work 8 trck_pkg 0 22 6>CbdmbEl4]clFV8BNMmO0
R8
R9
r1
!s85 0
!i10b 1
!s100 3zDB;KOzDO6b@SVFmVK?73
I;aEQEQj<4BHl4Uamd:Jk53
!s105 tracking_wrapper_sv_unit
S1
R10
Z118 w1783636237
Z119 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv
Z120 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv
!i122 37
L0 2 649
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xtracking_wrapper_sv_unit
R6
R6
R7
R8
Vf50n0]ER3iPW27XY;19711
r1
!s85 0
!i10b 1
!s100 C5:_D7HGJkcL757e<X[b>0
If50n0]ER3iPW27XY;19711
!i103 1
S1
R10
R118
R119
R120
!i122 37
R19
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vtrck_cntrl
R6
R6
R7
DXx4 work 18 trck_cntrl_sv_unit 0 22 SXV8ab46_R<a:20RHX7Io2
R8
R9
r1
!s85 0
!i10b 1
!s100 ^46Y4DZT=k[@B^nZaUMd61
I_JPZKahzU?cP]0@P^HH5G2
!s105 trck_cntrl_sv_unit
S1
R10
R11
Z121 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv
Z122 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv
!i122 37
L0 22 243
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xtrck_cntrl_sv_unit
R6
R6
R7
R8
VSXV8ab46_R<a:20RHX7Io2
r1
!s85 0
!i10b 1
!s100 02`PYHBK1R<lzIJ:Kn`;F1
ISXV8ab46_R<a:20RHX7Io2
!i103 1
S1
R10
R11
R121
R122
!i122 37
R23
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vtrck_fifo
R6
R8
!i10b 1
!s100 1gQYfO3cg?Q1X9U:6i[gW1
I7<?685325R_BlYkZG9dP13
S1
R10
R11
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/xil_fifo.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/xil_fifo.sv
!i122 37
L0 57 473
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
Xtrck_pkg
R6
R8
!i10b 1
!s100 8DZ`>aljTcKCO:mANQgQB0
I6>CbdmbEl4]clFV8BNMmO0
S1
R10
R49
8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/trck_pkg.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/apb_wrappers/trck_pkg.sv
!i122 37
R75
V6>CbdmbEl4]clFV8BNMmO0
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
vtrck_top
R6
R6
R7
DXx4 work 16 trck_top_sv_unit 0 22 LLmAROHS8Jan2o[f5>BHi1
R8
R9
r1
!s85 0
!i10b 1
!s100 9cRQl[:YVf8jl9YzDPI`k3
IQ8^eLFe_5jeYoTFGXe>jE3
!s105 trck_top_sv_unit
S1
R10
R49
Z123 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv
Z124 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv
!i122 37
L0 16 298
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xtrck_top_sv_unit
R6
R6
R7
R8
VLLmAROHS8Jan2o[f5>BHi1
r1
!s85 0
!i10b 1
!s100 K<n6nMQ6B^K[K2Mf9KF[72
ILLmAROHS8Jan2o[f5>BHi1
!i103 1
S1
R10
R49
R123
R124
!i122 37
L0 14 0
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vtwiddle_ram
R6
R6
R7
DXx4 work 19 twiddle_ram_sv_unit 0 22 Oe3@H0cSNnagl[amBaOcf0
R8
R9
r1
!s85 0
!i10b 1
!s100 LkS2M>e<=B:0eWfM^K`[l2
In`F2ZAJ2N?9DYdK_5fS740
!s105 twiddle_ram_sv_unit
S1
R10
R11
Z125 8/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/twiddle_ram.sv
Z126 F/home/onur/Desktop/rocket/rocket-chip/hardware/external/gps/rtl/acq_src/twiddle_ram.sv
!i122 37
L0 23 32
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
Xtwiddle_ram_sv_unit
R6
R6
R7
R8
VOe3@H0cSNnagl[amBaOcf0
r1
!s85 0
!i10b 1
!s100 74C7>847nN5oIfWW:cWZM1
IOe3@H0cSNnagl[amBaOcf0
!i103 1
S1
R10
R11
R125
R126
!i122 37
R26
R14
31
R15
R20
R16
!i113 0
R17
R18
R4
vuart_console_model
R6
R38
!i10b 1
!s100 Q[_D7L6?Nnk^U;40Yd9Zm2
I^F8BoAS8RYBGeC:QG1jDc1
S1
R10
Z127 w1783016333
8/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/uart/uart_console_model.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/uart/uart_console_model.sv
!i122 35
L0 3 45
R9
R14
r1
!s85 0
31
R39
R40
R41
!i113 0
R17
R42
R4
vuart_rx_model
R6
R38
!i10b 1
!s100 TnLEBmL0AzzBc60N>Zbgo0
IJYnRhoBUj_K<kbFTEncf31
S1
R10
R127
8/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/uart/uart_rx_model.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/sim/asic/rocket/tb/models/uart/uart_rx_model.sv
!i122 35
L0 3 93
R9
R14
r1
!s85 0
31
R39
R40
R41
!i113 0
R17
R42
R4
vVCU118RocketSystem
R6
R8
!i10b 1
!s100 [B>30F495jRdYhfDU;K_62
I[omlMNZ;hN:MBYaCn@0V^2
S1
R10
R35
8/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/VCU118RocketSystem.sv
F/home/onur/Desktop/rocket/rocket-chip/hardware/generated/asic-rocket-soc-verilog/VCU118RocketSystem.sv
!i122 37
L0 31 1607
R9
R14
r1
!s85 0
31
R15
R20
R16
!i113 0
R17
R18
R4
n@v@c@u118@rocket@system