base_dir=$(abspath ./)
REPO_DIR := $(base_dir)

include $(REPO_DIR)/tools/project.mk

ifneq ($(strip $(BOARD)),)
FPGA_BOARD ?= $(BOARD)
else
FPGA_BOARD ?= vcu118
endif
FPGA_TARGET_DIR := targets/fpga/$(FPGA_BOARD)

.PHONY: help doctor soc-hw fpga-rtl fpga-bitstream fpga-elf-flash-image fpga-mcs fpga-flash-app fpga-flash fpga-flash-bitstream fpga-flash-mcs fpga-flash-all fpga-program fpga-debug-openocd fpga-debug-load fpga-uart fpga-config asic-rtl asic-sim clean
.PHONY: fpga_rtl fpga_bitstream fpga_elf_flash_image fpga_mcs fpga_flash_app fpga_flash fpga_flash_bitstream fpga_flash_mcs fpga_flash_all fpga_program fpga_debug_openocd fpga_debug_load fpga_uart fpga_config

help:
	@printf '%s\n' \
	  'Project targets:' \
	  '  make doctor          # check local JDK/Mill/CIRCT and RISC-V tools' \
	  '  make soc-hw          # emit shared SoC FIRRTL through FPGA config' \
	  '  make fpga-rtl        # emit selected FPGA SystemVerilog and wrapper' \
	  '  make fpga-bitstream  # run selected FPGA Vivado bitstream flow' \
	  '  make fpga-elf-flash-image' \
	  '                       # build APP ELF and board flash-format app image' \
	  '  make fpga-mcs        # generate combined bitstream + app MCS/BIN' \
	  '  make fpga-program    # program selected FPGA SRAM' \
	  '  make fpga-flash-app  # build flash-format app image and program app flash region' \
	  '  make fpga-flash      # alias for fpga-flash-app' \
	  '  make fpga-flash-bitstream' \
	  '                       # program bitstream flash region only' \
	  '  make fpga-flash-mcs  # generate/program combined MCS into board flash' \
	  '  make fpga-flash-all  # program changed bitstream and app regions separately' \
	  '  make fpga-debug-openocd' \
	  '                       # Open OpenOCD BSCAN/GDB server' \
	  '  make fpga-debug-load # load hello/app ELF through GDB' \
	  '  make fpga-uart       # listen to selected FPGA UART' \
	  '  make fpga-config     # show selected FPGA board clocks/RF/flash/UART config' \
	  '  make asic-rtl        # emit ASIC-style SystemVerilog and wrapper' \
	  '  make asic-sim        # run ASIC-style Questa sanity simulation' \
	  '' \
	  'Config:' \
	  '  FPGA_BOARD=$(FPGA_BOARD)  # vcu118 or genesys2' \
	  '  UART_BAUD=460800          # FPGA firmware and host listener default' \
	  '  GPS_ESKF_ENABLE=1         # gps_system: 1 ESKF, 0 GPS-only' \
	  '  IMU_SENSOR=auto           # gps_system: auto, tdk, st or stm' \
	  '' \
	  'Direct entry points:' \
	  '  make -C soc help' \
	  '  make -C hardware/soc help' \
	  '  make -C targets/fpga/vcu118 help' \
	  '  make -C targets/fpga/genesys2 help' \
	  '  make -C targets/asic/rocket help'

doctor:
	@$(REPO_DIR)/tools/doctor.sh

soc-hw:
	$(MAKE) -C hardware/soc firrtl

fpga-rtl:
	$(MAKE) -C $(FPGA_TARGET_DIR) rtl

fpga-bitstream:
	$(MAKE) -C $(FPGA_TARGET_DIR) bitstream

fpga-elf-flash-image:
	$(MAKE) -C $(FPGA_TARGET_DIR) software

fpga-mcs:
	$(MAKE) -C $(FPGA_TARGET_DIR) flash-image

fpga-program:
	$(MAKE) -C $(FPGA_TARGET_DIR) program-fpga

fpga-flash-app fpga-flash:
	$(MAKE) -C $(FPGA_TARGET_DIR) program-flash

fpga-flash-bitstream:
	$(MAKE) -C $(FPGA_TARGET_DIR) program-flash-bitstream

fpga-flash-mcs:
	$(MAKE) -C $(FPGA_TARGET_DIR) program-flash-combined

fpga-flash-all:
	$(MAKE) -C $(FPGA_TARGET_DIR) program-flash-all

fpga-debug-openocd:
	$(MAKE) -C $(FPGA_TARGET_DIR) debug-openocd

fpga-debug-load:
	$(MAKE) -C $(FPGA_TARGET_DIR) debug-load

fpga-uart:
	$(MAKE) -C $(FPGA_TARGET_DIR) uart-listen

fpga-config:
	$(MAKE) -C $(FPGA_TARGET_DIR) fpga-config

fpga_rtl: fpga-rtl
fpga_bitstream: fpga-bitstream
fpga_elf_flash_image: fpga-elf-flash-image
fpga_mcs: fpga-mcs
fpga_flash_app: fpga-flash-app
fpga_flash: fpga-flash
fpga_flash_bitstream: fpga-flash-bitstream
fpga_flash_mcs: fpga-flash-mcs
fpga_flash_all: fpga-flash-all
fpga_program: fpga-program
fpga_debug_openocd: fpga-debug-openocd
fpga_debug_load: fpga-debug-load
fpga_uart: fpga-uart
fpga_config: fpga-config

asic-rtl:
	$(MAKE) -C targets/asic/rocket rtl

asic-sim:
	$(MAKE) -C targets/asic/rocket sim

clean:
	rm -rf out/
	$(MAKE) -C soc clean
	$(MAKE) -C $(FPGA_TARGET_DIR) clean
	$(MAKE) -C targets/asic/rocket clean