/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Enum Utility Definitions                                                   *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|* From: AMDGPUEnums.td                                                       *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

namespace mlir::amdgpu {

::llvm::StringRef stringifyAddressSpace(AddressSpace val) {
  switch (val) {
    case AddressSpace::FatRawBuffer: return "fat_raw_buffer";
    case AddressSpace::BufferRsrc: return "buffer_rsrc";
    case AddressSpace::FatStructuredBuffer: return "fat_structured_buffer";
  }
  return "";
}

::std::optional<AddressSpace> symbolizeAddressSpace(::llvm::StringRef str) {
  return ::llvm::StringSwitch<::std::optional<AddressSpace>>(str)
      .Case("fat_raw_buffer", AddressSpace::FatRawBuffer)
      .Case("buffer_rsrc", AddressSpace::BufferRsrc)
      .Case("fat_structured_buffer", AddressSpace::FatStructuredBuffer)
      .Default(::std::nullopt);
}
::std::optional<AddressSpace> symbolizeAddressSpace(uint32_t value) {
  switch (value) {
  case 0: return AddressSpace::FatRawBuffer;
  case 1: return AddressSpace::BufferRsrc;
  case 2: return AddressSpace::FatStructuredBuffer;
  default: return ::std::nullopt;
  }
}


} // namespace mlir::amdgpu
namespace mlir::amdgpu {

::llvm::StringRef stringifyScope(Scope val) {
  switch (val) {
    case Scope::WGP: return "WGP";
    case Scope::SE: return "SE";
    case Scope::DEV: return "DEV";
    case Scope::SYS: return "SYS";
  }
  return "";
}

::std::optional<Scope> symbolizeScope(::llvm::StringRef str) {
  return ::llvm::StringSwitch<::std::optional<Scope>>(str)
      .Case("WGP", Scope::WGP)
      .Case("SE", Scope::SE)
      .Case("DEV", Scope::DEV)
      .Case("SYS", Scope::SYS)
      .Default(::std::nullopt);
}
::std::optional<Scope> symbolizeScope(uint32_t value) {
  switch (value) {
  case 0: return Scope::WGP;
  case 1: return Scope::SE;
  case 2: return Scope::DEV;
  case 3: return Scope::SYS;
  default: return ::std::nullopt;
  }
}


} // namespace mlir::amdgpu
namespace mlir::amdgpu {

::llvm::StringRef stringifyDPPPerm(DPPPerm val) {
  switch (val) {
    case DPPPerm::quad_perm: return "quad_perm";
    case DPPPerm::row_shl: return "row_shl";
    case DPPPerm::row_shr: return "row_shr";
    case DPPPerm::row_ror: return "row_ror";
    case DPPPerm::wave_shl: return "wave_shl";
    case DPPPerm::wave_shr: return "wave_shr";
    case DPPPerm::wave_ror: return "wave_ror";
    case DPPPerm::wave_rol: return "wave_rol";
    case DPPPerm::row_mirror: return "row_mirror";
    case DPPPerm::row_half_mirror: return "row_half_mirror";
    case DPPPerm::row_bcast_15: return "row_bcast_15";
    case DPPPerm::row_bcast_31: return "row_bcast_31";
  }
  return "";
}

::std::optional<DPPPerm> symbolizeDPPPerm(::llvm::StringRef str) {
  return ::llvm::StringSwitch<::std::optional<DPPPerm>>(str)
      .Case("quad_perm", DPPPerm::quad_perm)
      .Case("row_shl", DPPPerm::row_shl)
      .Case("row_shr", DPPPerm::row_shr)
      .Case("row_ror", DPPPerm::row_ror)
      .Case("wave_shl", DPPPerm::wave_shl)
      .Case("wave_shr", DPPPerm::wave_shr)
      .Case("wave_ror", DPPPerm::wave_ror)
      .Case("wave_rol", DPPPerm::wave_rol)
      .Case("row_mirror", DPPPerm::row_mirror)
      .Case("row_half_mirror", DPPPerm::row_half_mirror)
      .Case("row_bcast_15", DPPPerm::row_bcast_15)
      .Case("row_bcast_31", DPPPerm::row_bcast_31)
      .Default(::std::nullopt);
}
::std::optional<DPPPerm> symbolizeDPPPerm(uint32_t value) {
  switch (value) {
  case 0: return DPPPerm::quad_perm;
  case 1: return DPPPerm::row_shl;
  case 2: return DPPPerm::row_shr;
  case 3: return DPPPerm::row_ror;
  case 4: return DPPPerm::wave_shl;
  case 5: return DPPPerm::wave_shr;
  case 6: return DPPPerm::wave_ror;
  case 7: return DPPPerm::wave_rol;
  case 8: return DPPPerm::row_mirror;
  case 9: return DPPPerm::row_half_mirror;
  case 10: return DPPPerm::row_bcast_15;
  case 11: return DPPPerm::row_bcast_31;
  default: return ::std::nullopt;
  }
}


} // namespace mlir::amdgpu
namespace mlir::amdgpu {

::llvm::StringRef stringifyLoadTemporalHint(LoadTemporalHint val) {
  switch (val) {
    case LoadTemporalHint::RT: return "RT";
    case LoadTemporalHint::NT: return "NT";
    case LoadTemporalHint::HT: return "HT";
    case LoadTemporalHint::LU: return "LU";
    case LoadTemporalHint::NT_RT: return "NT_RT";
    case LoadTemporalHint::RT_NT: return "RT_NT";
    case LoadTemporalHint::NT_HT: return "NT_HT";
  }
  return "";
}

::std::optional<LoadTemporalHint> symbolizeLoadTemporalHint(::llvm::StringRef str) {
  return ::llvm::StringSwitch<::std::optional<LoadTemporalHint>>(str)
      .Case("RT", LoadTemporalHint::RT)
      .Case("NT", LoadTemporalHint::NT)
      .Case("HT", LoadTemporalHint::HT)
      .Case("LU", LoadTemporalHint::LU)
      .Case("NT_RT", LoadTemporalHint::NT_RT)
      .Case("RT_NT", LoadTemporalHint::RT_NT)
      .Case("NT_HT", LoadTemporalHint::NT_HT)
      .Default(::std::nullopt);
}
::std::optional<LoadTemporalHint> symbolizeLoadTemporalHint(uint32_t value) {
  switch (value) {
  case 0: return LoadTemporalHint::RT;
  case 1: return LoadTemporalHint::NT;
  case 2: return LoadTemporalHint::HT;
  case 3: return LoadTemporalHint::LU;
  case 4: return LoadTemporalHint::NT_RT;
  case 5: return LoadTemporalHint::RT_NT;
  case 6: return LoadTemporalHint::NT_HT;
  default: return ::std::nullopt;
  }
}


} // namespace mlir::amdgpu