onur
1dbd1b5151
Keep the current GPS software and Genesys2/VCU118 flows while integrating Ti375C529 Efinity, flash, programming, and debug support. Add board-specific SPI NOR profiles and persistent GPS flash layouts across all three boards.
131 lines
4.3 KiB
Makefile
131 lines
4.3 KiB
Makefile
base_dir=$(abspath ./)
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REPO_DIR := $(base_dir)
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include $(REPO_DIR)/tools/project.mk
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ifneq ($(strip $(BOARD)),)
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FPGA_BOARD ?= $(BOARD)
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else
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FPGA_BOARD ?= vcu118
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endif
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FPGA_TARGET_DIR := targets/fpga/$(FPGA_BOARD)
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.PHONY: help doctor soc-hw fpga-rtl fpga-bitstream fpga-elf-flash-image fpga-mcs fpga-flash-app fpga-flash fpga-flash-bitstream fpga-flash-mcs fpga-flash-all fpga-program fpga-detect fpga-debug-openocd fpga-debug-load fpga-uart fpga-config asic-rtl asic-sim clean
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.PHONY: fpga_rtl fpga_bitstream fpga_elf_flash_image fpga_mcs fpga_flash_app fpga_flash fpga_flash_bitstream fpga_flash_mcs fpga_flash_all fpga_program fpga_detect fpga_debug_openocd fpga_debug_load fpga_uart fpga_config
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help:
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@printf '%s\n' \
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'Project targets:' \
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' make doctor # check local JDK/Mill/CIRCT and RISC-V tools' \
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' make soc-hw # emit shared SoC FIRRTL through FPGA config' \
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' make fpga-rtl # emit selected FPGA SystemVerilog and wrapper' \
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' make fpga-bitstream # run selected board vendor bitstream flow' \
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' make fpga-elf-flash-image' \
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' # build APP ELF and board flash-format app image' \
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' make fpga-mcs # generate combined bitstream + app MCS/BIN' \
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' make fpga-program # program selected FPGA SRAM' \
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' make fpga-detect # run selected board USB/JTAG detection target' \
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' make fpga-flash-app # build flash-format app image and program app flash region' \
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' make fpga-flash # alias for fpga-flash-app' \
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' make fpga-flash-bitstream' \
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' # program bitstream flash region only' \
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' make fpga-flash-mcs # generate/program combined MCS into board flash' \
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' make fpga-flash-all # program changed bitstream and app regions separately' \
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' make fpga-debug-openocd' \
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' # Open OpenOCD BSCAN/GDB server' \
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' make fpga-debug-load # load hello/app ELF through GDB' \
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' make fpga-uart # listen to selected FPGA UART' \
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' make fpga-config # show selected FPGA board clocks/RF/flash/UART config' \
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' make asic-rtl # emit ASIC-style SystemVerilog and wrapper' \
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' make asic-sim # run ASIC-style Questa sanity simulation' \
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'' \
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'Config:' \
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' FPGA_BOARD=$(FPGA_BOARD) # vcu118, genesys2, or ti375c529' \
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' UART_BAUD=460800 # FPGA firmware and host listener default' \
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' GPS_ESKF_ENABLE=1 # gps_system: 1 ESKF, 0 GPS-only' \
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' IMU_SENSOR=auto # gps_system: auto, tdk, st or stm' \
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'' \
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'Direct entry points:' \
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' make -C soc help' \
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' make -C hardware/soc help' \
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' make -C targets/fpga/vcu118 help' \
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' make -C targets/fpga/genesys2 help' \
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' make -C targets/fpga/ti375c529 help' \
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' make -C targets/asic/rocket help'
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doctor:
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@$(REPO_DIR)/tools/doctor.sh
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soc-hw:
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$(MAKE) -C hardware/soc firrtl
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fpga-rtl:
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$(MAKE) -C $(FPGA_TARGET_DIR) rtl
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fpga-bitstream:
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$(MAKE) -C $(FPGA_TARGET_DIR) bitstream
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fpga-elf-flash-image:
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$(MAKE) -C $(FPGA_TARGET_DIR) software
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fpga-mcs:
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$(MAKE) -C $(FPGA_TARGET_DIR) flash-image
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fpga-program:
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$(MAKE) -C $(FPGA_TARGET_DIR) program-fpga
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fpga-detect:
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$(MAKE) -C $(FPGA_TARGET_DIR) detect
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fpga-flash-app fpga-flash:
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$(MAKE) -C $(FPGA_TARGET_DIR) program-flash
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fpga-flash-bitstream:
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$(MAKE) -C $(FPGA_TARGET_DIR) program-flash-bitstream
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fpga-flash-mcs:
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$(MAKE) -C $(FPGA_TARGET_DIR) program-flash-combined
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fpga-flash-all:
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$(MAKE) -C $(FPGA_TARGET_DIR) program-flash-all
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fpga-debug-openocd:
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$(MAKE) -C $(FPGA_TARGET_DIR) debug-openocd
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fpga-debug-load:
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$(MAKE) -C $(FPGA_TARGET_DIR) debug-load
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fpga-uart:
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$(MAKE) -C $(FPGA_TARGET_DIR) uart-listen
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fpga-config:
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$(MAKE) -C $(FPGA_TARGET_DIR) fpga-config
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fpga_rtl: fpga-rtl
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fpga_bitstream: fpga-bitstream
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fpga_elf_flash_image: fpga-elf-flash-image
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fpga_mcs: fpga-mcs
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fpga_flash_app: fpga-flash-app
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fpga_flash: fpga-flash
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fpga_flash_bitstream: fpga-flash-bitstream
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fpga_flash_mcs: fpga-flash-mcs
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fpga_flash_all: fpga-flash-all
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fpga_program: fpga-program
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fpga_detect: fpga-detect
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fpga_debug_openocd: fpga-debug-openocd
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fpga_debug_load: fpga-debug-load
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fpga_uart: fpga-uart
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fpga_config: fpga-config
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asic-rtl:
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$(MAKE) -C targets/asic/rocket rtl
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asic-sim:
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$(MAKE) -C targets/asic/rocket sim
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clean:
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rm -rf out/
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$(MAKE) -C soc clean
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$(MAKE) -C $(FPGA_TARGET_DIR) clean
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$(MAKE) -C targets/asic/rocket clean
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