upstream/rocket-chip/src/
  Required upstream Rocket-Chip Scala sources and Verilog/C++ resources used by
  the generator and simulation helpers.

upstream/rocket-chip/bootrom/
  Required upstream default BootROM image/source for upstream configs. The
  project VCU118 flow uses soc/software/bootloader for the SPI flash boot path.

upstream/rocket-chip/scala
upstream/rocket-chip/resources
  Short symlink views for browsing upstream Scala and resource files inside
  upstream/rocket-chip/src.

soc/scala/
  Project-specific Rocket SoC Chisel/Scala layer. Mill adds this directory to
  the rocketchip module sources through build.sc.

generated/
  FIRRTL and SystemVerilog dump area:
  - generated/vcu118-soc/
  - generated/vcu118-soc-verilog/
  - generated/asic-rocket-soc/
  - generated/asic-rocket-soc-verilog/
  - generated/asic-rocket-soc-sim-verilog/

fpga/vcu118/rtl/
  Hand-written VCU118 shell/helper RTL that Vivado reads in addition to the
  generated Rocket SystemVerilog.

fpga/vcu118/constraints/
  VCU118 XDC constraints.

sim/asic/rocket/
  ASIC testbench, behavioral models, and wave.do.

sim/fpga/vcu118/
  FPGA smoke/sim entry point.

external/gps/rtl/
  GPS RTL sources and filelist consumed by FPGA and ASIC flows. FPGA Makefiles
  pass this path as the default GPS_SYSTEM_DIR, so the Vivado flow does not
  depend on a user-specific /home/... checkout.