21 lines
950 B
TableGen
21 lines
950 B
TableGen
//===- IntrinsicsRISCVXMIPS.td - MIPS intrinsics -------*- tablegen -*----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the MIPS specific intrinsics for RISC-V.
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "riscv" in {
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def int_riscv_mips_pause : ClangBuiltin<"__builtin_riscv_mips_pause">,
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Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
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def int_riscv_mips_ehb : ClangBuiltin<"__builtin_riscv_mips_ehb">,
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Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
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def int_riscv_mips_ihb : ClangBuiltin<"__builtin_riscv_mips_ihb">,
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Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
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}
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