35 lines
1.3 KiB
TableGen
35 lines
1.3 KiB
TableGen
//===- IntrinsicsRISCVXTHead.td - T-Head intrinsics --------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the T-Head vendor intrinsics for RISC-V.
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "riscv" in {
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class RISCV_TH_VdotTernaryWideMasked
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: DefaultAttrsIntrinsic< [llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty,
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LLVMScalarOrSameVectorWidth<2, llvm_i1_ty>,
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llvm_anyint_ty, LLVMMatchType<3>],
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[ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
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let ScalarOperand = 1;
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let VLOperand = 4;
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}
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multiclass RISCV_TH_VdotTernaryWide {
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def "int_riscv_" # NAME : RISCVTernaryWideUnMasked;
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def "int_riscv_" # NAME # "_mask" : RISCV_TH_VdotTernaryWideMasked;
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}
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defm th_vmaqa : RISCV_TH_VdotTernaryWide;
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defm th_vmaqau : RISCV_TH_VdotTernaryWide;
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defm th_vmaqasu : RISCV_TH_VdotTernaryWide;
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defm th_vmaqaus : RISCV_TH_VdotTernaryWide;
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}
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