86 lines
2.9 KiB
TableGen
86 lines
2.9 KiB
TableGen
//===-- AMDGPUEnums.td - AMDGPU dialect enums *- tablegen -*---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef MLIR_DIALECT_AMDGPU_IR_AMDGPUENUMS_TD
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#define MLIR_DIALECT_AMDGPU_IR_AMDGPUENUMS_TD
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include "mlir/Dialect/AMDGPU/IR/AMDGPUBase.td"
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include "mlir/IR/EnumAttr.td"
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include "mlir/IR/Properties.td"
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//===----------------------------------------------------------------------===//
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// AMDGPU general enum definitions
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//===----------------------------------------------------------------------===//
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def AMDGPU_AddressSpace : I32Enum<"AddressSpace",
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"AMDGPU-specific address spaces",
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[
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I32EnumCase<"FatRawBuffer", 0, "fat_raw_buffer">,
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I32EnumCase<"BufferRsrc", 1, "buffer_rsrc">,
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I32EnumCase<"FatStructuredBuffer", 2, "fat_structured_buffer">,
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]> {
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let cppNamespace = "::mlir::amdgpu";
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}
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def AMDGPU_DPPPerm : I32Enum<"DPPPerm",
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"The possible permutations for a DPP operation",
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[
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I32EnumAttrCase<"quad_perm", 0>,
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I32EnumAttrCase<"row_shl", 1>,
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I32EnumAttrCase<"row_shr", 2>,
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I32EnumAttrCase<"row_ror", 3>,
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I32EnumAttrCase<"wave_shl", 4>,
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I32EnumAttrCase<"wave_shr", 5>,
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I32EnumAttrCase<"wave_ror", 6>,
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I32EnumAttrCase<"wave_rol", 7>,
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I32EnumAttrCase<"row_mirror", 8>,
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I32EnumAttrCase<"row_half_mirror", 9>,
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I32EnumAttrCase<"row_bcast_15", 10>,
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I32EnumAttrCase<"row_bcast_31", 11>
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]> {
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let cppNamespace = "::mlir::amdgpu";
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}
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def AMDGPU_LoadTemporalHint : I32Enum<"LoadTemporalHint",
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"AMDGPU-specific prefetch temporal hints for load instructions. "
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"RT - regular temporal for both near and far caches; "
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"NT - non-temporal for both near and far caches; "
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"HT - high-priority temporal for both near and far caches; "
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"LU - last-use; "
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"NT_RT - non-temporal for near cache(s) and regular for far caches; "
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"RT_NT - regular for near cache(s) and non-temporal for far caches; "
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"NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches",
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[
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I32EnumCase<"RT", 0>,
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I32EnumCase<"NT", 1>,
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I32EnumCase<"HT", 2>,
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I32EnumCase<"LU", 3>,
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I32EnumCase<"NT_RT", 4>,
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I32EnumCase<"RT_NT", 5>,
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I32EnumCase<"NT_HT", 6>
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]> {
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let cppNamespace = "::mlir::amdgpu";
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}
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def AMDGPU_CacheScope : I32Enum<"Scope",
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"AMDGPU-specific cache scopes. "
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"WGP - workgroup processor (CUs); "
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"SE - shader engine (GL2); "
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"DEV - device; "
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"SYS - system",
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[
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I32EnumCase<"WGP", 0>,
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I32EnumCase<"SE", 1>,
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I32EnumCase<"DEV", 2>,
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I32EnumCase<"SYS", 3>
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]> {
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let cppNamespace = "::mlir::amdgpu";
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}
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#endif // MLIR_DIALECT_AMDGPU_IR_AMDGPUENUMS_TD
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