Files
gps/hardware/soc/Makefile
T
2026-07-12 11:01:51 +03:00

24 lines
611 B
Makefile

.PHONY: help all firrtl rtl fpga-rtl asic-rtl clean
help:
@echo "Common SoC hardware targets:"
@echo " make firrtl # emit FPGA FIRRTL for the shared Rocket SoC"
@echo " make rtl # emit FPGA SystemVerilog and FPGA wrapper"
@echo " make fpga-rtl # alias for make rtl"
@echo " make asic-rtl # emit ASIC SystemVerilog and ASIC wrapper"
@echo " make clean # remove generated SoC RTL outputs"
all: rtl
firrtl:
@make -C ../../targets/fpga/vcu118 chisel
rtl fpga-rtl:
@make -C ../../targets/fpga/vcu118 rtl
asic-rtl:
@make -C ../../targets/asic/rocket rtl
clean:
rm -rf ../generated