41 lines
2.0 KiB
Tcl
41 lines
2.0 KiB
Tcl
## Genesys2 Ethernet PHY pins used only by RF_INPUT_MODE=ethernet.
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## Source: Digilent Genesys-2-Master.xdc / Genesys 2 reference manual.
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## RTL8211E-VL RGMII/MDIO pins in bank 33 are LVCMOS15; INTB/PMEB are LVCMOS18.
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set_property PACKAGE_PIN AG10 [get_ports eth_rxck]
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set_property PACKAGE_PIN AH11 [get_ports eth_rxctl]
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set_property PACKAGE_PIN AJ14 [get_ports {eth_rxd[0]}]
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set_property PACKAGE_PIN AH14 [get_ports {eth_rxd[1]}]
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set_property PACKAGE_PIN AK13 [get_ports {eth_rxd[2]}]
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set_property PACKAGE_PIN AJ13 [get_ports {eth_rxd[3]}]
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set_property PACKAGE_PIN AE10 [get_ports eth_txck]
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set_property PACKAGE_PIN AK14 [get_ports eth_txctl]
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set_property PACKAGE_PIN AJ12 [get_ports {eth_txd[0]}]
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set_property PACKAGE_PIN AK11 [get_ports {eth_txd[1]}]
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set_property PACKAGE_PIN AJ11 [get_ports {eth_txd[2]}]
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set_property PACKAGE_PIN AK10 [get_ports {eth_txd[3]}]
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set_property IOSTANDARD LVCMOS15 [get_ports {eth_rxck eth_rxctl eth_rxd[*] eth_txck eth_txctl eth_txd[*]}]
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set_property PACKAGE_PIN AF12 [get_ports eth_mdc]
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set_property PACKAGE_PIN AG12 [get_ports eth_mdio]
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set_property IOSTANDARD LVCMOS15 [get_ports {eth_mdc eth_mdio}]
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set_property DRIVE 8 [get_ports {eth_mdc}]
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set_property SLEW SLOW [get_ports {eth_mdc}]
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set_property PACKAGE_PIN AH24 [get_ports eth_phyrst_n]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_phyrst_n]
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set_property DRIVE 8 [get_ports eth_phyrst_n]
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set_property SLEW SLOW [get_ports eth_phyrst_n]
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set_property PACKAGE_PIN AK16 [get_ports eth_int_b]
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set_property PACKAGE_PIN AK15 [get_ports eth_pme_b]
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set_property IOSTANDARD LVCMOS18 [get_ports {eth_int_b eth_pme_b}]
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set_property PULLUP true [get_ports {eth_int_b eth_pme_b}]
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create_clock -period 8.000 -name genesys2_eth_rxck [get_ports eth_rxck]
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set_input_delay 0.000 -clock genesys2_eth_rxck [get_ports {eth_rxctl eth_rxd[*]}]
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set_output_delay 0.000 -clock genesys2_eth_rxck [get_ports {eth_txctl eth_txd[*]}]
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set_false_path -to [get_ports {eth_phyrst_n eth_mdc eth_mdio}]
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set_false_path -from [get_ports {eth_int_b eth_pme_b eth_mdio}]
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