186 lines
6.1 KiB
Systemverilog
186 lines
6.1 KiB
Systemverilog
`timescale 1ns/1ps
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module rocket_bscan_dmi_tunnel #(
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parameter integer DMI_ADDR_WIDTH = 7,
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parameter integer DMI_DATA_WIDTH = 32,
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parameter integer DMI_SCAN_WIDTH = 41
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) (
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input wire tck,
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input wire reset,
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input wire bscan_capture,
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input wire bscan_sel,
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input wire bscan_shift,
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input wire bscan_tdi,
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input wire bscan_update,
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output wire bscan_tdo,
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output wire dmi_clock,
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output wire dmi_reset,
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input wire dmi_req_ready,
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output reg dmi_req_valid,
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output reg [DMI_ADDR_WIDTH-1:0] dmi_req_addr,
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output reg [DMI_DATA_WIDTH-1:0] dmi_req_data,
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output reg [1:0] dmi_req_op,
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output wire dmi_resp_ready,
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input wire dmi_resp_valid,
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input wire [DMI_DATA_WIDTH-1:0] dmi_resp_data,
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input wire [1:0] dmi_resp_resp
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);
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localparam [4:0] IR_DTMCS = 5'h10;
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localparam [4:0] IR_DMI = 5'h11;
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localparam [7:0] DMI_SCAN_WIDTH_U8 = DMI_SCAN_WIDTH;
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localparam [6:0] DMI_SCAN_WIDTH_U7 = DMI_SCAN_WIDTH;
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reg scan_is_dr;
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reg [6:0] scan_width;
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reg [7:0] scan_count;
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reg [DMI_SCAN_WIDTH-1:0] scan_data;
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reg [DMI_SCAN_WIDTH-1:0] response_data;
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reg tdo_reg;
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reg [4:0] selected_ir;
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reg busy_reg;
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reg sticky_busy;
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reg sticky_error;
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reg downgrade_op;
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reg last_resp_valid;
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reg [DMI_ADDR_WIDTH-1:0] last_resp_addr;
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reg [DMI_DATA_WIDTH-1:0] last_resp_data;
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reg [1:0] last_resp_resp;
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wire busy = busy_reg | sticky_busy;
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wire nonzero_resp = sticky_error | (last_resp_valid & (last_resp_resp != 2'b00));
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wire [1:0] dmi_status = {sticky_error, sticky_error | sticky_busy};
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wire [31:0] dtmcs_response = {
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15'd0,
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1'b0,
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1'b0,
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3'd5,
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dmi_status,
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6'd7,
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4'd1
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};
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wire [DMI_SCAN_WIDTH-1:0] dmi_response =
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busy ? {{(DMI_ADDR_WIDTH){1'b0}}, {(DMI_DATA_WIDTH){1'b0}}, 2'b11} :
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last_resp_valid ? {last_resp_addr, last_resp_data, last_resp_resp} :
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{(DMI_SCAN_WIDTH){1'b0}};
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wire [DMI_SCAN_WIDTH-1:0] next_response =
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selected_ir == IR_DTMCS ? {{(DMI_SCAN_WIDTH-32){1'b0}}, dtmcs_response} :
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selected_ir == IR_DMI ? dmi_response :
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{(DMI_SCAN_WIDTH){1'b0}};
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assign bscan_tdo = tdo_reg;
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assign dmi_clock = tck;
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assign dmi_reset = reset;
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assign dmi_resp_ready = 1'b1;
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wire [7:0] data_index = scan_count - 8'd8;
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always @(posedge tck or posedge reset) begin
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if (reset) begin
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scan_is_dr <= 1'b0;
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scan_width <= 7'd0;
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scan_count <= 8'd0;
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scan_data <= {DMI_SCAN_WIDTH{1'b0}};
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response_data <= {DMI_SCAN_WIDTH{1'b0}};
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selected_ir <= IR_DTMCS;
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busy_reg <= 1'b0;
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sticky_busy <= 1'b0;
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sticky_error <= 1'b0;
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downgrade_op <= 1'b0;
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last_resp_valid <= 1'b0;
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last_resp_addr <= {DMI_ADDR_WIDTH{1'b0}};
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last_resp_data <= {DMI_DATA_WIDTH{1'b0}};
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last_resp_resp <= 2'b00;
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dmi_req_valid <= 1'b0;
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dmi_req_addr <= {DMI_ADDR_WIDTH{1'b0}};
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dmi_req_data <= {DMI_DATA_WIDTH{1'b0}};
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dmi_req_op <= 2'b00;
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end else begin
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if (dmi_req_valid && dmi_req_ready) begin
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dmi_req_valid <= 1'b0;
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end
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if (dmi_resp_valid) begin
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last_resp_valid <= 1'b1;
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last_resp_data <= dmi_resp_data;
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last_resp_resp <= dmi_resp_resp;
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last_resp_addr <= dmi_req_addr;
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busy_reg <= 1'b0;
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end
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if (bscan_sel && bscan_capture) begin
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scan_is_dr <= 1'b0;
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scan_width <= 7'd0;
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scan_count <= 8'd0;
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scan_data <= {DMI_SCAN_WIDTH{1'b0}};
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response_data <= next_response;
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if (selected_ir == IR_DMI) begin
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downgrade_op <= !busy & nonzero_resp;
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sticky_busy <= busy;
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sticky_error <= nonzero_resp;
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if (!busy && last_resp_valid) begin
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last_resp_valid <= 1'b0;
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end
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end
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end else if (bscan_sel && bscan_shift) begin
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if (scan_count == 8'd0) begin
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scan_is_dr <= bscan_tdi;
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end else if (scan_count <= 8'd7) begin
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scan_width[scan_count - 8'd1] <= bscan_tdi;
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end else begin
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if (data_index < DMI_SCAN_WIDTH_U8) begin
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scan_data[data_index] <= bscan_tdi;
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end
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end
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scan_count <= scan_count + 8'd1;
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end
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if (bscan_sel && bscan_update) begin
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if (!scan_is_dr) begin
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selected_ir <= scan_data[4:0];
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end else if (selected_ir == IR_DTMCS && scan_width == 7'd32) begin
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if (scan_data[16]) begin
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sticky_busy <= 1'b0;
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sticky_error <= 1'b0;
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end
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end else if (selected_ir == IR_DMI && scan_width == DMI_SCAN_WIDTH_U7) begin
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if (sticky_busy) begin
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dmi_req_valid <= dmi_req_valid;
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end else if (downgrade_op || scan_data[1:0] == 2'b00) begin
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dmi_req_addr <= {DMI_ADDR_WIDTH{1'b0}};
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dmi_req_data <= {DMI_DATA_WIDTH{1'b0}};
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dmi_req_op <= 2'b00;
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end else begin
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dmi_req_addr <= scan_data[DMI_SCAN_WIDTH-1:DMI_DATA_WIDTH+2];
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dmi_req_data <= scan_data[DMI_DATA_WIDTH+1:2];
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dmi_req_op <= scan_data[1:0];
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dmi_req_valid <= 1'b1;
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busy_reg <= 1'b1;
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end
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end
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end
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end
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end
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always @(negedge tck or posedge reset) begin
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if (reset) begin
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tdo_reg <= 1'b0;
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end else if (bscan_sel && bscan_shift) begin
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// Genesys2 Kintex-7 BSCANE2 USER chain needs two extra lead-in bits on
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// TDO. Without this, OpenOCD sees DTMCS right-shifted by two bits
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// (0x5071 becomes 0x141c) and reports an unsupported DTM version.
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if (scan_count <= 8'd7) begin
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tdo_reg <= 1'b0;
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end else if (scan_count <= (DMI_SCAN_WIDTH_U8 + 8'd7)) begin
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tdo_reg <= response_data[scan_count - 8'd8];
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end else begin
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tdo_reg <= 1'b0;
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end
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end else begin
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tdo_reg <= 1'b0;
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end
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end
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endmodule
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