1947 lines
154 KiB
Plaintext
1947 lines
154 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
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| Date : Sat Jul 11 19:55:22 2026
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| Host : onur running 64-bit Ubuntu 22.04.5 LTS
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| Command : report_timing_summary -file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/synth_timing_summary.rpt
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| Design : genesys2_rocket_top
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| Device : 7k325t-ffg900
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| Speed File : -2 PRODUCTION 1.12 2017-02-17
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| Design State : Synthesized
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Timing Summary Report
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------------------------------------------------------------------------------------------------
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| Timer Settings
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| --------------
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------------------------------------------------------------------------------------------------
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Enable Multi Corner Analysis : Yes
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Enable Pessimism Removal : Yes
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Pessimism Removal Resolution : Nearest Common Node
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Enable Input Delay Default Clock : No
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Enable Preset / Clear Arcs : No
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Disable Flight Delays : No
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Ignore I/O Paths : No
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Timing Early Launch at Borrowing Latches : No
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Borrow Time for Max Delay Exceptions : Yes
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Merge Timing Exceptions : Yes
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Inter-SLR Compensation : Conservative
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Corner Analyze Analyze
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Name Max Paths Min Paths
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------ --------- ---------
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Slow Yes Yes
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Fast Yes Yes
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------------------------------------------------------------------------------------------------
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| Report Methodology
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| ------------------
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------------------------------------------------------------------------------------------------
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No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
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check_timing report
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Table of Contents
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-----------------
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1. checking no_clock (392)
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2. checking constant_clock (0)
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3. checking pulse_width_clock (0)
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4. checking unconstrained_internal_endpoints (782)
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5. checking no_input_delay (15)
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6. checking no_output_delay (20)
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7. checking multiple_clock (0)
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8. checking generated_clocks (0)
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9. checking loops (0)
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10. checking partial_input_delay (0)
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11. checking partial_output_delay (0)
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12. checking latch_loops (0)
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1. checking no_clock (392)
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--------------------------
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There are 9 register/latch pins with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/apbReset_gps_apb_reset/io_sync_reset_chain/output_chain/sync_0_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/code_freq_vld_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/prn_o_reg[0]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/prn_o_reg[1]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/prn_o_reg[2]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/prn_o_reg[3]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/prn_o_reg[4]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/code_freq_vld_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/prn_o_reg[0]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/prn_o_reg[1]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/prn_o_reg[2]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/prn_o_reg[3]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/prn_o_reg[4]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/code_freq_vld_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/prn_o_reg[0]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/prn_o_reg[1]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/prn_o_reg[2]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/prn_o_reg[3]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/prn_o_reg[4]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/code_freq_vld_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/prn_o_reg[0]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/prn_o_reg[1]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/prn_o_reg[2]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/prn_o_reg[3]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/prn_o_reg[4]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/code_freq_vld_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/prn_o_reg[0]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/prn_o_reg[1]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/prn_o_reg[2]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/prn_o_reg[3]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/prn_o_reg[4]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/code_freq_vld_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/prn_o_reg[0]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/prn_o_reg[1]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/prn_o_reg[2]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/prn_o_reg[3]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/prn_o_reg[4]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/code_freq_vld_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/prn_o_reg[0]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/prn_o_reg[1]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/prn_o_reg[2]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/prn_o_reg[3]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/prn_o_reg[4]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/code_freq_vld_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/prn_o_reg[0]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/prn_o_reg[1]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/prn_o_reg[2]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/prn_o_reg[3]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/prn_o_reg[4]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/code_freq_vld_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/prn_o_reg[0]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/prn_o_reg[1]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/prn_o_reg[2]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/prn_o_reg[3]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/prn_o_reg[4]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q (HIGH)
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There are 311 register/latch pins with no clock driven by root clock pin: u_rocket_bscan/TCK (HIGH)
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2. checking constant_clock (0)
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------------------------------
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There are 0 register/latch pins with constant_clock.
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3. checking pulse_width_clock (0)
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---------------------------------
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There are 0 register/latch pins which need pulse_width check
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4. checking unconstrained_internal_endpoints (782)
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--------------------------------------------------
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There are 782 pins that are not constrained for maximum delay. (HIGH)
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There are 0 pins that are not constrained for maximum delay due to constant clock.
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5. checking no_input_delay (15)
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-------------------------------
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There are 15 input ports with no input delay specified. (HIGH)
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There are 0 input ports with no input delay but user has a false path constraint.
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6. checking no_output_delay (20)
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--------------------------------
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There are 20 ports with no output delay specified. (HIGH)
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There are 0 ports with no output delay but user has a false path constraint
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There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
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7. checking multiple_clock (0)
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------------------------------
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There are 0 register/latch pins with multiple clocks.
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8. checking generated_clocks (0)
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--------------------------------
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There are 0 generated clocks that are not connected to a clock source.
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9. checking loops (0)
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---------------------
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There are 0 combinational loops in the design.
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10. checking partial_input_delay (0)
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------------------------------------
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There are 0 input ports with partial input delay specified.
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11. checking partial_output_delay (0)
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-------------------------------------
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There are 0 ports with partial output delay specified.
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12. checking latch_loops (0)
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----------------------------
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There are 0 combinational latch loops in the design through latch input
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------------------------------------------------------------------------------------------------
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| Design Timing Summary
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| ---------------------
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------------------------------------------------------------------------------------------------
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WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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1.198 0.000 0 123398 -0.072 -27.056 1838 123398 1.100 0.000 0 43569
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Timing constraints are not met.
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------------------------------------------------------------------------------------------------
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| Clock Summary
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| -------------
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------------------------------------------------------------------------------------------------
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Clock Waveform(ns) Period(ns) Frequency(MHz)
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----- ------------ ---------- --------------
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pmod_rf_clk {0.000 30.548} 61.095 16.368
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gps_ref_clkfb {0.000 30.548} 61.095 16.368
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pll_gps_ref_clk {0.000 9.000} 18.000 55.555
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gps_clkfb {0.000 9.000} 18.000 55.555
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pll_gps_acq_clk {0.000 6.250} 12.500 80.000
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pll_gps_trck_clk {0.000 4.000} 8.000 125.000
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sysclk_200 {0.000 2.500} 5.000 200.000
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fabric_clkfb {0.000 2.500} 5.000 200.000
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pll_fabric_clk {0.000 10.000} 20.000 50.000
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------------------------------------------------------------------------------------------------
|
|
| Intra Clock Table
|
|
| -----------------
|
|
------------------------------------------------------------------------------------------------
|
|
|
|
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
|
|
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
|
|
pmod_rf_clk 58.914 0.000 0 1151 -0.006 -0.268 45 1151 20.547 0.000 0 982
|
|
gps_ref_clkfb 38.905 0.000 0 3
|
|
pll_gps_ref_clk 6.000 0.000 0 3
|
|
gps_clkfb 16.592 0.000 0 3
|
|
pll_gps_acq_clk 1.769 0.000 0 6634 0.041 0.000 0 6634 5.900 0.000 0 1372
|
|
pll_gps_trck_clk 1.198 0.000 0 36466 -0.006 -0.303 51 36466 3.650 0.000 0 17889
|
|
sysclk_200 1.100 0.000 0 1
|
|
fabric_clkfb 3.592 0.000 0 3
|
|
pll_fabric_clk 10.181 0.000 0 48882 -0.072 -26.485 1742 48882 9.232 0.000 0 23313
|
|
|
|
|
|
------------------------------------------------------------------------------------------------
|
|
| Inter Clock Table
|
|
| -----------------
|
|
------------------------------------------------------------------------------------------------
|
|
|
|
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
|
|
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
|
|
|
|
|
|
------------------------------------------------------------------------------------------------
|
|
| Other Path Groups Table
|
|
| -----------------------
|
|
------------------------------------------------------------------------------------------------
|
|
|
|
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
|
|
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
|
|
**async_default** pll_fabric_clk pll_fabric_clk 17.802 0.000 0 11747 0.208 0.000 0 11747
|
|
**async_default** pll_gps_acq_clk pll_gps_acq_clk 10.783 0.000 0 997 0.545 0.000 0 997
|
|
**async_default** pll_gps_trck_clk pll_gps_trck_clk 5.838 0.000 0 17349 0.361 0.000 0 17349
|
|
**async_default** pmod_rf_clk pmod_rf_clk 59.496 0.000 0 172 0.502 0.000 0 172
|
|
|
|
|
|
------------------------------------------------------------------------------------------------
|
|
| Timing Details
|
|
| --------------
|
|
------------------------------------------------------------------------------------------------
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: pmod_rf_clk
|
|
To Clock: pmod_rf_clk
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 58.914ns, Total Violation 0.000ns
|
|
Hold : 45 Failing Endpoints, Worst Slack -0.006ns, Total Violation -0.268ns
|
|
PW : 0 Failing Endpoints, Worst Slack 20.547ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 58.914ns (required time - arrival time)
|
|
Source: u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by pmod_rf_clk {rise@0.000ns fall@30.548ns period=61.095ns})
|
|
Destination: u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by pmod_rf_clk {rise@0.000ns fall@30.548ns period=61.095ns})
|
|
Path Group: pmod_rf_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 61.095ns (pmod_rf_clk rise@61.095ns - pmod_rf_clk rise@0.000ns)
|
|
Data Path Delay: 2.037ns (logic 0.857ns (42.072%) route 1.180ns (57.928%))
|
|
Logic Levels: 4 (CARRY4=3 LUT2=1)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.330ns = ( 63.425 - 61.095 )
|
|
Source Clock Delay (SCD): 2.640ns
|
|
Clock Pessimism Removal (CPR): 0.165ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pmod_rf_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.497 1.497 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.466 1.963 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.584 2.640 u_rocket/fpga_gps_domain/dev/afe/sample_align_i/gps_rf_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.223 2.863 r u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter_reg[4]/Q
|
|
net (fo=2, unplaced) 0.679 3.542 u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter[4]
|
|
CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.303 3.845 r u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter0_carry/CO[3]
|
|
net (fo=1, unplaced) 0.007 3.852 u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter0_carry_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 3.906 r u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter0_carry__0/CO[3]
|
|
net (fo=1, unplaced) 0.000 3.906 u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter0_carry__0_n_0
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.157 4.063 r u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter0_carry__1/O[3]
|
|
net (fo=1, unplaced) 0.494 4.557 u_rocket/fpga_gps_domain/dev/afe/sample_align_i/data0[12]
|
|
LUT2 (Prop_lut2_I1_O) 0.120 4.677 r u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter[12]_i_1/O
|
|
net (fo=1, unplaced) 0.000 4.677 u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter_0[12]
|
|
FDCE r u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pmod_rf_clk rise edge)
|
|
61.095 61.095 r
|
|
U27 0.000 61.095 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 61.095 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.365 62.460 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.442 62.903 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.083 62.986 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.439 63.425 u_rocket/fpga_gps_domain/dev/afe/sample_align_i/gps_rf_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter_reg[12]/C
|
|
clock pessimism 0.165 63.590
|
|
clock uncertainty -0.035 63.554
|
|
FDCE (Setup_fdce_C_D) 0.036 63.590 u_rocket/fpga_gps_domain/dev/afe/sample_align_i/counter_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 63.590
|
|
arrival time -4.677
|
|
-------------------------------------------------------------------
|
|
slack 58.914
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (VIOLATED) : -0.006ns (arrival time - required time)
|
|
Source: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by pmod_rf_clk {rise@0.000ns fall@30.548ns period=61.095ns})
|
|
Destination: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by pmod_rf_clk {rise@0.000ns fall@30.548ns period=61.095ns})
|
|
Path Group: pmod_rf_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (pmod_rf_clk rise@0.000ns - pmod_rf_clk rise@0.000ns)
|
|
Data Path Delay: 0.158ns (logic 0.104ns (65.800%) route 0.054ns (34.200%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.150ns
|
|
Source Clock Delay (SCD): 0.793ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pmod_rf_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 0.422 0.422 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.231 0.653 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.114 0.793 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/gps_rf_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.104 0.897 r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[0]/Q
|
|
net (fo=1, unplaced) 0.054 0.951 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q[0]
|
|
FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pmod_rf_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 0.618 0.618 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.243 0.861 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.259 1.150 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/gps_rf_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[1]/C
|
|
clock pessimism -0.212 0.938
|
|
FDCE (Hold_fdce_C_D) 0.019 0.957 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -0.957
|
|
arrival time 0.951
|
|
-------------------------------------------------------------------
|
|
slack -0.006
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: pmod_rf_clk
|
|
Waveform(ns): { 0.000 30.548 }
|
|
Period(ns): 61.095
|
|
Sources: { rf_clk_pmod }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 61.095 59.256 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/dual_port_ram_i/ram_reg_0_0/CLKARDCLK
|
|
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 61.095 38.905 u_gps_ref_mmcm/CLKIN1
|
|
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 10.000 30.548 20.547 u_gps_ref_mmcm/CLKIN1
|
|
High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 10.000 30.548 20.547 u_gps_ref_mmcm/CLKIN1
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: gps_ref_clkfb
|
|
To Clock: gps_ref_clkfb
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
PW : 0 Failing Endpoints, Worst Slack 38.905ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: gps_ref_clkfb
|
|
Waveform(ns): { 0.000 30.548 }
|
|
Period(ns): 61.095
|
|
Sources: { u_gps_ref_mmcm/CLKFBOUT }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 1.408 61.095 59.686 u_gps_ref_feedback_buf/I
|
|
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 61.095 38.905 u_gps_ref_mmcm/CLKFBIN
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: pll_gps_ref_clk
|
|
To Clock: pll_gps_ref_clk
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
PW : 0 Failing Endpoints, Worst Slack 6.000ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: pll_gps_ref_clk
|
|
Waveform(ns): { 0.000 9.000 }
|
|
Period(ns): 18.000
|
|
Sources: { u_gps_ref_mmcm/CLKOUT0 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 1.408 18.000 16.592 u_gps_ref_clk_buf/I
|
|
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 18.000 82.000 u_gps_domain_mmcm/CLKIN1
|
|
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 9.000 6.000 u_gps_domain_mmcm/CLKIN1
|
|
High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 9.000 6.000 u_gps_domain_mmcm/CLKIN1
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: gps_clkfb
|
|
To Clock: gps_clkfb
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
PW : 0 Failing Endpoints, Worst Slack 16.592ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: gps_clkfb
|
|
Waveform(ns): { 0.000 9.000 }
|
|
Period(ns): 18.000
|
|
Sources: { u_gps_domain_mmcm/CLKFBOUT }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 1.408 18.000 16.592 u_gps_domain_feedback_buf/I
|
|
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 18.000 82.000 u_gps_domain_mmcm/CLKFBIN
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: pll_gps_acq_clk
|
|
To Clock: pll_gps_acq_clk
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 1.769ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.041ns, Total Violation 0.000ns
|
|
PW : 0 Failing Endpoints, Worst Slack 5.900ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 1.769ns (required time - arrival time)
|
|
Source: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_31/CLKARDCLK
|
|
(rising edge-triggered cell RAMB36E1 clocked by pll_gps_acq_clk {rise@0.000ns fall@6.250ns period=12.500ns})
|
|
Destination: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_21/DIADI[1]
|
|
(rising edge-triggered cell RAMB36E1 clocked by pll_gps_acq_clk {rise@0.000ns fall@6.250ns period=12.500ns})
|
|
Path Group: pll_gps_acq_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 12.500ns (pll_gps_acq_clk rise@12.500ns - pll_gps_acq_clk rise@0.000ns)
|
|
Data Path Delay: 10.316ns (logic 7.369ns (71.433%) route 2.947ns (28.567%))
|
|
Logic Levels: 13 (CARRY4=7 DSP48E1=2 LUT2=3 LUT4=1)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.330ns = ( 14.830 - 12.500 )
|
|
Source Clock Delay (SCD): 2.640ns
|
|
Clock Pessimism Removal (CPR): 0.165ns
|
|
Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.161ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_gps_acq_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.497 1.497 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.466 1.963 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.584 2.640 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.143 1.497 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.466 1.963 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.584 2.640 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.143 1.497 r u_gps_domain_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.466 1.963 pll_gps_acq_clk
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_gps_acq_clk_buf/O
|
|
net (fo=1370, unplaced) 0.584 2.640 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/gps_acq_clk
|
|
RAMB36E1 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_31/CLKARDCLK
|
|
------------------------------------------------------------------- -------------------
|
|
RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[0])
|
|
1.800 4.440 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_31/DOADO[0]
|
|
net (fo=3, unplaced) 0.466 4.905 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/port2_rd_data[62]
|
|
DSP48E1 (Prop_dsp48e1_A[16]_PCOUT[47])
|
|
2.879 7.784 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0/PCOUT[47]
|
|
net (fo=1, unplaced) 0.050 7.834 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0_n_106
|
|
DSP48E1 (Prop_dsp48e1_PCIN[47]_P[17])
|
|
1.077 8.911 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1/P[17]
|
|
net (fo=2, unplaced) 0.466 9.377 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1_n_88
|
|
LUT2 (Prop_lut2_I0_O) 0.043 9.420 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_3/O
|
|
net (fo=1, unplaced) 0.000 9.420 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_i_3_n_0
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.256 9.676 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry/CO[3]
|
|
net (fo=1, unplaced) 0.007 9.683 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 9.737 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0/CO[3]
|
|
net (fo=1, unplaced) 0.000 9.737 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__0_n_0
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.157 9.894 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__1/O[3]
|
|
net (fo=1, unplaced) 0.494 10.388 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1_carry__1_n_4
|
|
LUT2 (Prop_lut2_I1_O) 0.120 10.508 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_4/O
|
|
net (fo=1, unplaced) 0.000 10.508 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_i_4_n_0
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.246 10.754 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10/CO[3]
|
|
net (fo=1, unplaced) 0.000 10.754 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__10_n_0
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.157 10.911 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w0_carry__11/O[3]
|
|
net (fo=2, unplaced) 0.505 11.416 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/x1_imag_w[38]
|
|
LUT2 (Prop_lut2_I1_O) 0.120 11.536 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/y1_imag_carry__8_i_2/O
|
|
net (fo=1, unplaced) 0.000 11.536 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_19_0[2]
|
|
CARRY4 (Prop_carry4_S[2]_CO[3])
|
|
0.183 11.719 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/y1_imag_carry__8/CO[3]
|
|
net (fo=1, unplaced) 0.000 11.719 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/y1_imag_carry__8_n_0
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.157 11.876 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/y1_imag_carry__9/O[3]
|
|
net (fo=1, unplaced) 0.494 12.370 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/y1_imag[43]
|
|
LUT4 (Prop_lut4_I3_O) 0.120 12.490 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/ram_reg_21_i_1__1/O
|
|
net (fo=1, unplaced) 0.466 12.956 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/port2_wr_data_i[43]
|
|
RAMB36E1 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_21/DIADI[1]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_gps_acq_clk rise edge)
|
|
12.500 12.500 r
|
|
U27 0.000 12.500 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 12.500 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.365 13.865 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.442 14.308 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.083 14.391 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.439 14.830 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.964 13.865 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.442 14.308 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.083 14.391 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.439 14.830 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.964 13.865 r u_gps_domain_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.442 14.308 pll_gps_acq_clk
|
|
BUFG (Prop_bufg_I_O) 0.083 14.391 r u_gps_acq_clk_buf/O
|
|
net (fo=1370, unplaced) 0.439 14.830 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/gps_acq_clk
|
|
RAMB36E1 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_21/CLKARDCLK
|
|
clock pessimism 0.165 14.995
|
|
clock uncertainty -0.088 14.907
|
|
RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[1])
|
|
-0.182 14.725 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/dual_port_bram_i/ram_reg_21
|
|
-------------------------------------------------------------------
|
|
required time 14.725
|
|
arrival time -12.956
|
|
-------------------------------------------------------------------
|
|
slack 1.769
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.041ns (arrival time - required time)
|
|
Source: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/rf_data_addr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by pll_gps_acq_clk {rise@0.000ns fall@6.250ns period=12.500ns})
|
|
Destination: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/dual_port_ram_i/ram_reg_0_0/ADDRBWRADDR[0]
|
|
(rising edge-triggered cell RAMB36E1 clocked by pll_gps_acq_clk {rise@0.000ns fall@6.250ns period=12.500ns})
|
|
Path Group: pll_gps_acq_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (pll_gps_acq_clk rise@0.000ns - pll_gps_acq_clk rise@0.000ns)
|
|
Data Path Delay: 0.331ns (logic 0.100ns (30.219%) route 0.231ns (69.781%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.150ns
|
|
Source Clock Delay (SCD): 0.793ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_gps_acq_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 0.422 0.422 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.231 0.653 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.114 0.793 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.371 0.422 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.231 0.653 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.114 0.793 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.371 0.422 r u_gps_domain_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.231 0.653 pll_gps_acq_clk
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_gps_acq_clk_buf/O
|
|
net (fo=1370, unplaced) 0.114 0.793 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/gps_acq_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/rf_data_addr_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.100 0.893 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/rf_data_addr_reg[0]/Q
|
|
net (fo=7, unplaced) 0.231 1.124 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/dual_port_ram_i/ADDRBWRADDR[0]
|
|
RAMB36E1 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/dual_port_ram_i/ram_reg_0_0/ADDRBWRADDR[0]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_gps_acq_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 0.618 0.618 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.243 0.861 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.259 1.150 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.532 0.618 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.243 0.861 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.259 1.150 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.532 0.618 r u_gps_domain_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.243 0.861 pll_gps_acq_clk
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_gps_acq_clk_buf/O
|
|
net (fo=1370, unplaced) 0.259 1.150 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/dual_port_ram_i/gps_acq_clk
|
|
RAMB36E1 r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/dual_port_ram_i/ram_reg_0_0/CLKBWRCLK
|
|
clock pessimism -0.212 0.938
|
|
RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_ADDRBWRADDR[0])
|
|
0.145 1.083 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/dual_port_ram_i/ram_reg_0_0
|
|
-------------------------------------------------------------------
|
|
required time -1.083
|
|
arrival time 1.124
|
|
-------------------------------------------------------------------
|
|
slack 0.041
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: pll_gps_acq_clk
|
|
Waveform(ns): { 0.000 6.250 }
|
|
Period(ns): 12.500
|
|
Sources: { u_gps_domain_mmcm/CLKOUT0 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.095 12.500 10.405 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/CLKARDCLK
|
|
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 12.500 200.860 u_gps_domain_mmcm/CLKOUT0
|
|
Low Pulse Width Slow FDCE/C n/a 0.350 6.250 5.900 u_rocket/ram_reg_10_i_5__0/C
|
|
High Pulse Width Slow FDCE/C n/a 0.350 6.250 5.900 u_rocket/ram_reg_10_i_5__0/C
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: pll_gps_trck_clk
|
|
To Clock: pll_gps_trck_clk
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 1.198ns, Total Violation 0.000ns
|
|
Hold : 51 Failing Endpoints, Worst Slack -0.006ns, Total Violation -0.303ns
|
|
PW : 0 Failing Endpoints, Worst Slack 3.650ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 1.198ns (required time - arrival time)
|
|
Source: u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds_work_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by pll_gps_trck_clk {rise@0.000ns fall@4.000ns period=8.000ns})
|
|
Destination: u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by pll_gps_trck_clk {rise@0.000ns fall@4.000ns period=8.000ns})
|
|
Path Group: pll_gps_trck_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 8.000ns (pll_gps_trck_clk rise@8.000ns - pll_gps_trck_clk rise@0.000ns)
|
|
Data Path Delay: 6.612ns (logic 3.463ns (52.374%) route 3.149ns (47.626%))
|
|
Logic Levels: 34 (CARRY4=29 LUT3=2 LUT5=1 LUT6=2)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.330ns = ( 10.330 - 8.000 )
|
|
Source Clock Delay (SCD): 2.640ns
|
|
Clock Pessimism Removal (CPR): 0.165ns
|
|
Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.145ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_gps_trck_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.497 1.497 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.466 1.963 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.584 2.640 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.143 1.497 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.466 1.963 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.584 2.640 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-1.143 1.497 r u_gps_domain_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.466 1.963 pll_gps_trck_clk
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_gps_trck_clk_buf/O
|
|
net (fo=17887, unplaced) 0.584 2.640 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/gps_trck_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds_work_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.233 2.873 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds_work_reg[3]/Q
|
|
net (fo=3, unplaced) 0.514 3.387 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds_work_reg_n_0_[3]
|
|
CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.273 3.660 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_398/CO[3]
|
|
net (fo=1, unplaced) 0.007 3.667 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_398_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 3.721 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_420/CO[3]
|
|
net (fo=1, unplaced) 0.000 3.721 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_420_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 3.775 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_403/CO[3]
|
|
net (fo=1, unplaced) 0.000 3.775 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_403_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 3.829 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_372/CO[3]
|
|
net (fo=1, unplaced) 0.000 3.829 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_372_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 3.883 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_350/CO[3]
|
|
net (fo=1, unplaced) 0.000 3.883 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_350_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 3.937 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_349/CO[3]
|
|
net (fo=1, unplaced) 0.000 3.937 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_349_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 3.991 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_294/CO[3]
|
|
net (fo=1, unplaced) 0.000 3.991 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_294_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 4.045 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_293/CO[3]
|
|
net (fo=1, unplaced) 0.000 4.045 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_293_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 4.099 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_238/CO[3]
|
|
net (fo=1, unplaced) 0.000 4.099 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_238_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 4.153 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_237/CO[3]
|
|
net (fo=1, unplaced) 0.000 4.153 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_237_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 4.207 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_182/CO[3]
|
|
net (fo=1, unplaced) 0.000 4.207 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_182_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 4.261 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_181/CO[3]
|
|
net (fo=1, unplaced) 0.000 4.261 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_181_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 4.315 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_130/CO[3]
|
|
net (fo=1, unplaced) 0.000 4.315 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_130_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 4.369 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_129/CO[3]
|
|
net (fo=1, unplaced) 0.000 4.369 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_129_n_0
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.157 4.526 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_78/O[3]
|
|
net (fo=6, unplaced) 0.526 5.052 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_calculation2[59]
|
|
LUT3 (Prop_lut3_I2_O) 0.120 5.172 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_145/O
|
|
net (fo=1, unplaced) 0.000 5.172 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_145_n_0
|
|
CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.180 5.352 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_92/CO[3]
|
|
net (fo=1, unplaced) 0.000 5.352 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_92_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.089 5.441 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_46/CO[1]
|
|
net (fo=34, unplaced) 0.424 5.865 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_46_n_2
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.989 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_11/O
|
|
net (fo=2, unplaced) 0.281 6.270 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_11_n_0
|
|
LUT6 (Prop_lut6_I5_O) 0.043 6.313 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_5/O
|
|
net (fo=2, unplaced) 0.508 6.821 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_5_n_0
|
|
CARRY4 (Prop_carry4_DI[1]_CO[3])
|
|
0.253 7.074 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[55]_i_2/CO[3]
|
|
net (fo=1, unplaced) 0.000 7.074 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[55]_i_2_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 7.128 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[59]_i_2/CO[3]
|
|
net (fo=1, unplaced) 0.000 7.128 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[59]_i_2_n_0
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.157 7.285 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_6/O[3]
|
|
net (fo=6, unplaced) 0.526 7.811 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_calculation[63]
|
|
LUT3 (Prop_lut3_I2_O) 0.124 7.935 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_436/O
|
|
net (fo=1, unplaced) 0.000 7.935 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_436_n_0
|
|
CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.293 8.228 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_386/CO[3]
|
|
net (fo=1, unplaced) 0.007 8.235 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_386_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 8.289 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_331/CO[3]
|
|
net (fo=1, unplaced) 0.000 8.289 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_331_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 8.343 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_275/CO[3]
|
|
net (fo=1, unplaced) 0.000 8.343 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_275_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 8.397 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_219/CO[3]
|
|
net (fo=1, unplaced) 0.000 8.397 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_219_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 8.451 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_163/CO[3]
|
|
net (fo=1, unplaced) 0.000 8.451 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_163_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 8.505 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_111/CO[3]
|
|
net (fo=1, unplaced) 0.000 8.505 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_111_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 8.559 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_60/CO[3]
|
|
net (fo=1, unplaced) 0.000 8.559 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_60_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 8.613 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_23/CO[3]
|
|
net (fo=1, unplaced) 0.000 8.613 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_23_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[0])
|
|
0.147 8.760 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_8/CO[0]
|
|
net (fo=66, unplaced) 0.356 9.116 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_8_n_3
|
|
LUT5 (Prop_lut5_I0_O) 0.136 9.252 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[0]_i_1/O
|
|
net (fo=1, unplaced) 0.000 9.252 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[0]_i_1_n_0
|
|
FDCE r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_gps_trck_clk rise edge)
|
|
8.000 8.000 r
|
|
U27 0.000 8.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 8.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.365 9.365 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.442 9.808 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.083 9.891 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.439 10.330 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.964 9.365 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.442 9.808 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.083 9.891 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.439 10.330 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-0.964 9.365 r u_gps_domain_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.442 9.808 pll_gps_trck_clk
|
|
BUFG (Prop_bufg_I_O) 0.083 9.891 r u_gps_trck_clk_buf/O
|
|
net (fo=17887, unplaced) 0.439 10.330 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/gps_trck_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[0]/C
|
|
clock pessimism 0.165 10.495
|
|
clock uncertainty -0.081 10.414
|
|
FDCE (Setup_fdce_C_D) 0.036 10.450 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 10.450
|
|
arrival time -9.252
|
|
-------------------------------------------------------------------
|
|
slack 1.198
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (VIOLATED) : -0.006ns (arrival time - required time)
|
|
Source: u_rocket/fpga_gps_domain/dev/pps/control_sync1_p_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by pll_gps_trck_clk {rise@0.000ns fall@4.000ns period=8.000ns})
|
|
Destination: u_rocket/fpga_gps_domain/dev/pps/control_sync2_p_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by pll_gps_trck_clk {rise@0.000ns fall@4.000ns period=8.000ns})
|
|
Path Group: pll_gps_trck_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (pll_gps_trck_clk rise@0.000ns - pll_gps_trck_clk rise@0.000ns)
|
|
Data Path Delay: 0.158ns (logic 0.104ns (65.800%) route 0.054ns (34.200%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.150ns
|
|
Source Clock Delay (SCD): 0.793ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_gps_trck_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 0.422 0.422 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.231 0.653 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.114 0.793 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.371 0.422 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.231 0.653 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.114 0.793 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-0.371 0.422 r u_gps_domain_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.231 0.653 pll_gps_trck_clk
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_gps_trck_clk_buf/O
|
|
net (fo=17887, unplaced) 0.114 0.793 u_rocket/fpga_gps_domain/dev/pps/gps_trck_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/pps/control_sync1_p_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.104 0.897 r u_rocket/fpga_gps_domain/dev/pps/control_sync1_p_reg[0]/Q
|
|
net (fo=1, unplaced) 0.054 0.951 u_rocket/fpga_gps_domain/dev/pps/control_sync1_p[0]
|
|
FDCE r u_rocket/fpga_gps_domain/dev/pps/control_sync2_p_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_gps_trck_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 0.618 0.618 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.243 0.861 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.259 1.150 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.532 0.618 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.243 0.861 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.259 1.150 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-0.532 0.618 r u_gps_domain_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.243 0.861 pll_gps_trck_clk
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_gps_trck_clk_buf/O
|
|
net (fo=17887, unplaced) 0.259 1.150 u_rocket/fpga_gps_domain/dev/pps/gps_trck_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/pps/control_sync2_p_reg[0]/C
|
|
clock pessimism -0.212 0.938
|
|
FDCE (Hold_fdce_C_D) 0.019 0.957 u_rocket/fpga_gps_domain/dev/pps/control_sync2_p_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -0.957
|
|
arrival time 0.951
|
|
-------------------------------------------------------------------
|
|
slack -0.006
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: pll_gps_trck_clk
|
|
Waveform(ns): { 0.000 4.000 }
|
|
Period(ns): 8.000
|
|
Sources: { u_gps_domain_mmcm/CLKOUT1 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a DSP48E1/CLK n/a 1.538 8.000 6.462 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__0/CLK
|
|
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 8.000 205.360 u_gps_domain_mmcm/CLKOUT1
|
|
Low Pulse Width Slow FDCE/C n/a 0.350 4.000 3.650 u_rocket/integrator_candidate_work_reg[111]_i_20/C
|
|
High Pulse Width Slow FDCE/C n/a 0.350 4.000 3.650 u_rocket/integrator_candidate_work_reg[111]_i_20/C
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: sysclk_200
|
|
To Clock: sysclk_200
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
PW : 0 Failing Endpoints, Worst Slack 1.100ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: sysclk_200
|
|
Waveform(ns): { 0.000 2.500 }
|
|
Period(ns): 5.000
|
|
Sources: { sysclk_p }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.071 5.000 3.929 u_clock_mmcm/CLKIN1
|
|
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 5.000 95.000 u_clock_mmcm/CLKIN1
|
|
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 u_clock_mmcm/CLKIN1
|
|
High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 u_clock_mmcm/CLKIN1
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: fabric_clkfb
|
|
To Clock: fabric_clkfb
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
PW : 0 Failing Endpoints, Worst Slack 3.592ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: fabric_clkfb
|
|
Waveform(ns): { 0.000 2.500 }
|
|
Period(ns): 5.000
|
|
Sources: { u_clock_mmcm/CLKFBOUT }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 1.408 5.000 3.591 u_pll_feedback_buf/I
|
|
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 5.000 95.000 u_clock_mmcm/CLKFBIN
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: pll_fabric_clk
|
|
To Clock: pll_fabric_clk
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 10.181ns, Total Violation 0.000ns
|
|
Hold : 1742 Failing Endpoints, Worst Slack -0.072ns, Total Violation -26.485ns
|
|
PW : 0 Failing Endpoints, Worst Slack 9.232ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 10.181ns (required time - arrival time)
|
|
Source: u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/in_in2_reg[61]/C
|
|
(rising edge-triggered cell FDRE clocked by pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[105]/D
|
|
(rising edge-triggered cell FDRE clocked by pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: pll_fabric_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (pll_fabric_clk rise@20.000ns - pll_fabric_clk rise@0.000ns)
|
|
Data Path Delay: 9.656ns (logic 7.139ns (73.931%) route 2.517ns (26.069%))
|
|
Logic Levels: 21 (CARRY4=15 DSP48E1=3 LUT3=2 LUT6=1)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.081ns = ( 17.919 - 20.000 )
|
|
Source Clock Delay (SCD): -2.583ns
|
|
Clock Pessimism Removal (CPR): -0.648ns
|
|
Clock Uncertainty: 0.073ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.128ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_fabric_clk rise edge)
|
|
0.000 0.000 r
|
|
AD12 0.000 0.000 r sysclk_p (IN)
|
|
net (fo=0) 0.000 0.000 sysclk_p
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.906 0.906 r u_sysclk_ibufds/O
|
|
net (fo=1, unplaced) 0.584 1.490 sysclk_200
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-5.216 -3.726 r u_clock_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.466 -3.260 pll_fabric_clk
|
|
BUFG (Prop_bufg_I_O) 0.093 -3.167 r u_fabric_clk_buf/O
|
|
net (fo=23331, unplaced) 0.584 -2.583 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/io_aggregator_0_clock
|
|
FDRE r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/in_in2_reg[61]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.223 -2.360 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/in_in2_reg[61]/Q
|
|
net (fo=17, unplaced) 0.472 -1.888 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/Q[27]
|
|
LUT3 (Prop_lut3_I0_O) 0.123 -1.765 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_i_18/O
|
|
net (fo=3, unplaced) 0.466 -1.300 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_i_18_n_0
|
|
DSP48E1 (Prop_dsp48e1_A[18]_PCOUT[47])
|
|
2.879 1.579 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__2/PCOUT[47]
|
|
net (fo=1, unplaced) 0.050 1.629 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__2_n_106
|
|
DSP48E1 (Prop_dsp48e1_PCIN[47]_PCOUT[47])
|
|
1.219 2.848 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__3/PCOUT[47]
|
|
net (fo=1, unplaced) 0.000 2.848 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__3_n_106
|
|
DSP48E1 (Prop_dsp48e1_PCIN[47]_P[18])
|
|
1.077 3.925 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4/P[18]
|
|
net (fo=3, unplaced) 0.466 4.391 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4_n_87
|
|
LUT3 (Prop_lut3_I1_O) 0.050 4.441 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/i___1_carry__4_i_4/O
|
|
net (fo=2, unplaced) 0.311 4.752 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/i___1_carry__4_i_4_n_0
|
|
CARRY4 (Prop_carry4_DI[0]_CO[3])
|
|
0.374 5.126 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_inferred__1/i___1_carry__4/CO[3]
|
|
net (fo=1, unplaced) 0.000 5.126 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_inferred__1/i___1_carry__4_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 5.180 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_inferred__1/i___1_carry__5/CO[3]
|
|
net (fo=1, unplaced) 0.000 5.180 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_inferred__1/i___1_carry__5_n_0
|
|
CARRY4 (Prop_carry4_CI_O[2])
|
|
0.120 5.300 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_inferred__1/i___1_carry__6/O[2]
|
|
net (fo=2, unplaced) 0.753 6.053 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_preMul/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[67][2]
|
|
LUT6 (Prop_lut6_I3_O) 0.127 6.180 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_preMul/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b[63]_i_2/O
|
|
net (fo=1, unplaced) 0.000 6.180 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_preMul_n_117
|
|
CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.180 6.360 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[63]_i_1/CO[3]
|
|
net (fo=1, unplaced) 0.000 6.360 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[63]_i_1_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 6.414 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[67]_i_1/CO[3]
|
|
net (fo=1, unplaced) 0.000 6.414 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[67]_i_1_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 6.468 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[71]_i_1/CO[3]
|
|
net (fo=1, unplaced) 0.000 6.468 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[71]_i_1_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 6.522 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[75]_i_1/CO[3]
|
|
net (fo=1, unplaced) 0.000 6.522 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[75]_i_1_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 6.576 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[79]_i_1/CO[3]
|
|
net (fo=1, unplaced) 0.000 6.576 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[79]_i_1_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 6.630 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[83]_i_1/CO[3]
|
|
net (fo=1, unplaced) 0.000 6.630 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[83]_i_1_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 6.684 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[87]_i_1/CO[3]
|
|
net (fo=1, unplaced) 0.000 6.684 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[87]_i_1_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 6.738 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[91]_i_1/CO[3]
|
|
net (fo=1, unplaced) 0.000 6.738 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[91]_i_1_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 6.792 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[95]_i_1/CO[3]
|
|
net (fo=1, unplaced) 0.000 6.792 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[95]_i_1_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 6.846 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[99]_i_1/CO[3]
|
|
net (fo=1, unplaced) 0.000 6.846 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[99]_i_1_n_0
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.054 6.900 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[103]_i_1/CO[3]
|
|
net (fo=1, unplaced) 0.000 6.900 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[103]_i_1_n_0
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.173 7.073 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[106]_i_1/O[1]
|
|
net (fo=1, unplaced) 0.000 7.073 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[106]_i_1_n_6
|
|
FDRE r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[105]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_fabric_clk rise edge)
|
|
20.000 20.000 r
|
|
AD12 0.000 20.000 r sysclk_p (IN)
|
|
net (fo=0) 0.000 20.000 sysclk_p
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.803 20.803 r u_sysclk_ibufds/O
|
|
net (fo=1, unplaced) 0.439 21.242 sysclk_200
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-4.287 16.955 r u_clock_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.442 17.397 pll_fabric_clk
|
|
BUFG (Prop_bufg_I_O) 0.083 17.480 r u_fabric_clk_buf/O
|
|
net (fo=23331, unplaced) 0.439 17.919 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/io_aggregator_0_clock
|
|
FDRE r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[105]/C
|
|
clock pessimism -0.648 17.272
|
|
clock uncertainty -0.073 17.198
|
|
FDRE (Setup_fdre_C_D) 0.055 17.253 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[105]
|
|
-------------------------------------------------------------------
|
|
required time 17.253
|
|
arrival time -7.073
|
|
-------------------------------------------------------------------
|
|
slack 10.181
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (VIOLATED) : -0.072ns (arrival time - required time)
|
|
Source: u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/refill_paddr_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/Memory_reg/DIADI[0]
|
|
(rising edge-triggered cell RAMB18E1 clocked by pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: pll_fabric_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (pll_fabric_clk rise@0.000ns - pll_fabric_clk rise@0.000ns)
|
|
Data Path Delay: 0.331ns (logic 0.100ns (30.219%) route 0.231ns (69.781%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.829ns
|
|
Source Clock Delay (SCD): -0.913ns
|
|
Clock Pessimism Removal (CPR): -0.062ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_fabric_clk rise edge)
|
|
0.000 0.000 r
|
|
AD12 0.000 0.000 r sysclk_p (IN)
|
|
net (fo=0) 0.000 0.000 sysclk_p
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.388 0.388 r u_sysclk_ibufds/O
|
|
net (fo=1, unplaced) 0.114 0.502 sysclk_200
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-1.786 -1.283 r u_clock_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.231 -1.053 pll_fabric_clk
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.027 r u_fabric_clk_buf/O
|
|
net (fo=23331, unplaced) 0.114 -0.913 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/io_aggregator_0_clock
|
|
FDRE r u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/refill_paddr_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.100 -0.813 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/refill_paddr_reg[12]/Q
|
|
net (fo=2, unplaced) 0.231 -0.582 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/Q[6]
|
|
RAMB18E1 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/Memory_reg/DIADI[0]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_fabric_clk rise edge)
|
|
0.000 0.000 r
|
|
AD12 0.000 0.000 r sysclk_p (IN)
|
|
net (fo=0) 0.000 0.000 sysclk_p
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.470 0.470 r u_sysclk_ibufds/O
|
|
net (fo=1, unplaced) 0.259 0.729 sysclk_200
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-2.090 -1.361 r u_clock_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.243 -1.118 pll_fabric_clk
|
|
BUFG (Prop_bufg_I_O) 0.030 -1.088 r u_fabric_clk_buf/O
|
|
net (fo=23331, unplaced) 0.259 -0.829 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/io_aggregator_0_clock
|
|
RAMB18E1 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/Memory_reg/CLKARDCLK
|
|
clock pessimism 0.062 -0.768
|
|
RAMB18E1 (Hold_ramb18e1_CLKARDCLK_DIADI[0])
|
|
0.258 -0.510 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/Memory_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.510
|
|
arrival time -0.582
|
|
-------------------------------------------------------------------
|
|
slack -0.072
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: pll_fabric_clk
|
|
Waveform(ns): { 0.000 10.000 }
|
|
Period(ns): 20.000
|
|
Sources: { u_clock_mmcm/CLKOUT1 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.025 20.000 17.975 u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_0_0/CLKARDCLK
|
|
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 20.000 193.360 u_clock_mmcm/CLKOUT1
|
|
Low Pulse Width Slow RAMD32/CLK n/a 0.768 10.000 9.232 u_rocket/cbus/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_0_5/RAMA/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 0.768 10.000 9.232 u_rocket/cbus/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_0_5/RAMA/CLK
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: pll_fabric_clk
|
|
To Clock: pll_fabric_clk
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 17.802ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.208ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 17.802ns (required time - arrival time)
|
|
Source: reset_shift_reg[15]/C
|
|
(rising edge-triggered cell FDSE clocked by pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/sync_0_reg/CLR
|
|
(recovery check against rising-edge clock pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (pll_fabric_clk rise@20.000ns - pll_fabric_clk rise@0.000ns)
|
|
Data Path Delay: 1.766ns (logic 0.389ns (22.027%) route 1.377ns (77.973%))
|
|
Logic Levels: 2 (LUT2=2)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.081ns = ( 17.919 - 20.000 )
|
|
Source Clock Delay (SCD): -2.583ns
|
|
Clock Pessimism Removal (CPR): -0.648ns
|
|
Clock Uncertainty: 0.073ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.128ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_fabric_clk rise edge)
|
|
0.000 0.000 r
|
|
AD12 0.000 0.000 r sysclk_p (IN)
|
|
net (fo=0) 0.000 0.000 sysclk_p
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.906 0.906 r u_sysclk_ibufds/O
|
|
net (fo=1, unplaced) 0.584 1.490 sysclk_200
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-5.216 -3.726 r u_clock_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.466 -3.260 pll_fabric_clk
|
|
BUFG (Prop_bufg_I_O) 0.093 -3.167 r u_fabric_clk_buf/O
|
|
net (fo=23331, unplaced) 0.584 -2.583 fabric_clk
|
|
FDSE r reset_shift_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDSE (Prop_fdse_C_Q) 0.223 -2.360 f reset_shift_reg[15]/Q
|
|
net (fo=57, unplaced) 0.353 -2.007 u_rocket_bscan_dmi_tunnel/led_OBUF[1]
|
|
LUT2 (Prop_lut2_I0_O) 0.123 -1.884 f u_rocket_bscan_dmi_tunnel/u_rocket_i_2/O
|
|
net (fo=228, unplaced) 0.390 -1.494 u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_1/io_out_source_valid_0/output_chain/debug_clockeddmi_dmiReset
|
|
LUT2 (Prop_lut2_I1_O) 0.043 -1.451 f u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_1/io_out_source_valid_0/output_chain/sync_2_i_1/O
|
|
net (fo=9, unplaced) 0.634 -0.817 u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/sync_0_reg_1
|
|
FDCE f u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/sync_0_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_fabric_clk rise edge)
|
|
20.000 20.000 r
|
|
AD12 0.000 20.000 r sysclk_p (IN)
|
|
net (fo=0) 0.000 20.000 sysclk_p
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.803 20.803 r u_sysclk_ibufds/O
|
|
net (fo=1, unplaced) 0.439 21.242 sysclk_200
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-4.287 16.955 r u_clock_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.442 17.397 pll_fabric_clk
|
|
BUFG (Prop_bufg_I_O) 0.083 17.480 r u_fabric_clk_buf/O
|
|
net (fo=23331, unplaced) 0.439 17.919 u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/debug_clock
|
|
FDCE r u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/sync_0_reg/C
|
|
clock pessimism -0.648 17.272
|
|
clock uncertainty -0.073 17.198
|
|
FDCE (Recov_fdce_C_CLR) -0.214 16.984 u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/sync_0_reg
|
|
-------------------------------------------------------------------
|
|
required time 16.984
|
|
arrival time 0.817
|
|
-------------------------------------------------------------------
|
|
slack 17.802
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.208ns (arrival time - required time)
|
|
Source: reset_shift_reg[15]/C
|
|
(rising edge-triggered cell FDSE clocked by pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/sync_0_reg/CLR
|
|
(removal check against rising-edge clock pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (pll_fabric_clk rise@0.000ns - pll_fabric_clk rise@0.000ns)
|
|
Data Path Delay: 0.246ns (logic 0.100ns (40.602%) route 0.146ns (59.398%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.829ns
|
|
Source Clock Delay (SCD): -0.913ns
|
|
Clock Pessimism Removal (CPR): -0.062ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_fabric_clk rise edge)
|
|
0.000 0.000 r
|
|
AD12 0.000 0.000 r sysclk_p (IN)
|
|
net (fo=0) 0.000 0.000 sysclk_p
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.388 0.388 r u_sysclk_ibufds/O
|
|
net (fo=1, unplaced) 0.114 0.502 sysclk_200
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-1.786 -1.283 r u_clock_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.231 -1.053 pll_fabric_clk
|
|
BUFG (Prop_bufg_I_O) 0.026 -1.027 r u_fabric_clk_buf/O
|
|
net (fo=23331, unplaced) 0.114 -0.913 fabric_clk
|
|
FDSE r reset_shift_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDSE (Prop_fdse_C_Q) 0.100 -0.813 f reset_shift_reg[15]/Q
|
|
net (fo=57, unplaced) 0.146 -0.666 u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/debug_reset
|
|
FDCE f u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/sync_0_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_fabric_clk rise edge)
|
|
0.000 0.000 r
|
|
AD12 0.000 0.000 r sysclk_p (IN)
|
|
net (fo=0) 0.000 0.000 sysclk_p
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.470 0.470 r u_sysclk_ibufds/O
|
|
net (fo=1, unplaced) 0.259 0.729 sysclk_200
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-2.090 -1.361 r u_clock_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.243 -1.118 pll_fabric_clk
|
|
BUFG (Prop_bufg_I_O) 0.030 -1.088 r u_fabric_clk_buf/O
|
|
net (fo=23331, unplaced) 0.259 -0.829 u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/debug_clock
|
|
FDCE r u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/sync_0_reg/C
|
|
clock pessimism 0.062 -0.768
|
|
FDCE (Remov_fdce_C_CLR) -0.107 -0.875 u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/sync_0_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.875
|
|
arrival time -0.666
|
|
-------------------------------------------------------------------
|
|
slack 0.208
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: pll_gps_acq_clk
|
|
To Clock: pll_gps_acq_clk
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 10.783ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.545ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 10.783ns (required time - arrival time)
|
|
Source: u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/sync_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by pll_gps_acq_clk {rise@0.000ns fall@6.250ns period=12.500ns})
|
|
Destination: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/FSM_onehot_STATE_reg[1]/CLR
|
|
(recovery check against rising-edge clock pll_gps_acq_clk {rise@0.000ns fall@6.250ns period=12.500ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 12.500ns (pll_gps_acq_clk rise@12.500ns - pll_gps_acq_clk rise@0.000ns)
|
|
Data Path Delay: 1.270ns (logic 0.346ns (27.244%) route 0.924ns (72.756%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.330ns = ( 14.830 - 12.500 )
|
|
Source Clock Delay (SCD): 2.640ns
|
|
Clock Pessimism Removal (CPR): 0.165ns
|
|
Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.161ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_gps_acq_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.497 1.497 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.466 1.963 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.584 2.640 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.143 1.497 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.466 1.963 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.584 2.640 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.143 1.497 r u_gps_domain_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.466 1.963 pll_gps_acq_clk
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_gps_acq_clk_buf/O
|
|
net (fo=1370, unplaced) 0.584 2.640 u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/gps_acq_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/sync_0_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.223 2.863 r u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/sync_0_reg/Q
|
|
net (fo=1, unplaced) 0.191 3.054 u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/sync_0_reg_n_0
|
|
LUT1 (Prop_lut1_I0_O) 0.123 3.177 f u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/sin_phase[31]_i_3/O
|
|
net (fo=997, unplaced) 0.733 3.910 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/write_p_reg_rep__0
|
|
FDCE f u_rocket/fpga_gps_domain/dev/acq/i_acq_top/FSM_onehot_STATE_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_gps_acq_clk rise edge)
|
|
12.500 12.500 r
|
|
U27 0.000 12.500 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 12.500 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.365 13.865 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.442 14.308 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.083 14.391 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.439 14.830 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.964 13.865 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.442 14.308 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.083 14.391 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.439 14.830 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.964 13.865 r u_gps_domain_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.442 14.308 pll_gps_acq_clk
|
|
BUFG (Prop_bufg_I_O) 0.083 14.391 r u_gps_acq_clk_buf/O
|
|
net (fo=1370, unplaced) 0.439 14.830 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/gps_acq_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/FSM_onehot_STATE_reg[1]/C
|
|
clock pessimism 0.165 14.995
|
|
clock uncertainty -0.088 14.907
|
|
FDCE (Recov_fdce_C_CLR) -0.214 14.693 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/FSM_onehot_STATE_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.693
|
|
arrival time -3.910
|
|
-------------------------------------------------------------------
|
|
slack 10.783
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.545ns (arrival time - required time)
|
|
Source: u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/sync_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by pll_gps_acq_clk {rise@0.000ns fall@6.250ns period=12.500ns})
|
|
Destination: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_code_gen_i/phase_acc_reg[21]/CLR
|
|
(removal check against rising-edge clock pll_gps_acq_clk {rise@0.000ns fall@6.250ns period=12.500ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (pll_gps_acq_clk rise@0.000ns - pll_gps_acq_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.357%) route 0.458ns (73.643%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.150ns
|
|
Source Clock Delay (SCD): 0.793ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_gps_acq_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 0.422 0.422 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.231 0.653 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.114 0.793 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.371 0.422 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.231 0.653 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.114 0.793 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.371 0.422 r u_gps_domain_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.231 0.653 pll_gps_acq_clk
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_gps_acq_clk_buf/O
|
|
net (fo=1370, unplaced) 0.114 0.793 u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/gps_acq_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/sync_0_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.100 0.893 r u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/sync_0_reg/Q
|
|
net (fo=1, unplaced) 0.095 0.988 u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/sync_0_reg_n_0
|
|
LUT1 (Prop_lut1_I0_O) 0.064 1.052 f u_rocket/fpga_gps_domain/dev/acqReset_gps_acq_reset/io_sync_reset_chain/output_chain/sin_phase[31]_i_3/O
|
|
net (fo=997, unplaced) 0.363 1.415 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_code_gen_i/phase_acc_reg[24]_0
|
|
FDCE f u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_code_gen_i/phase_acc_reg[21]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_gps_acq_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 0.618 0.618 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.243 0.861 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.259 1.150 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.532 0.618 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.243 0.861 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.259 1.150 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.532 0.618 r u_gps_domain_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.243 0.861 pll_gps_acq_clk
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_gps_acq_clk_buf/O
|
|
net (fo=1370, unplaced) 0.259 1.150 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_code_gen_i/gps_acq_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_code_gen_i/phase_acc_reg[21]/C
|
|
clock pessimism -0.212 0.938
|
|
FDCE (Remov_fdce_C_CLR) -0.068 0.870 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_code_gen_i/phase_acc_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time -0.870
|
|
arrival time 1.415
|
|
-------------------------------------------------------------------
|
|
slack 0.545
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: pll_gps_trck_clk
|
|
To Clock: pll_gps_trck_clk
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 5.838ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.361ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 5.838ns (required time - arrival time)
|
|
Source: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/C
|
|
(rising edge-triggered cell FDCE clocked by pll_gps_trck_clk {rise@0.000ns fall@4.000ns period=8.000ns})
|
|
Destination: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_C/CLR
|
|
(recovery check against rising-edge clock pll_gps_trck_clk {rise@0.000ns fall@4.000ns period=8.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 8.000ns (pll_gps_trck_clk rise@8.000ns - pll_gps_trck_clk rise@0.000ns)
|
|
Data Path Delay: 1.722ns (logic 0.397ns (23.055%) route 1.325ns (76.945%))
|
|
Logic Levels: 2 (LUT4=1 LUT6=1)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.330ns = ( 10.330 - 8.000 )
|
|
Source Clock Delay (SCD): 2.640ns
|
|
Clock Pessimism Removal (CPR): 0.165ns
|
|
Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.145ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_gps_trck_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.497 1.497 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.466 1.963 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.584 2.640 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-1.143 1.497 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.466 1.963 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.584 2.640 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-1.143 1.497 r u_gps_domain_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.466 1.963 pll_gps_trck_clk
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_gps_trck_clk_buf/O
|
|
net (fo=17887, unplaced) 0.584 2.640 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/gps_trck_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.223 2.863 r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q
|
|
net (fo=4, unplaced) 0.440 3.303 u_rocket/fpga_gps_domain/dev/tracking_0/trck_cntrl_i/stop_in_trk_r3
|
|
LUT4 (Prop_lut4_I1_O) 0.131 3.434 r u_rocket/fpga_gps_domain/dev/tracking_0/i___6/O
|
|
net (fo=2, unplaced) 0.281 3.715 u_rocket/fpga_gps_domain/dev/tracking_0/i___6_n_0
|
|
LUT6 (Prop_lut6_I0_O) 0.043 3.758 f u_rocket/fpga_gps_domain/dev/tracking_0/i___4/O
|
|
net (fo=2, unplaced) 0.604 4.362 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_C_1
|
|
FDCE f u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_C/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_gps_trck_clk rise edge)
|
|
8.000 8.000 r
|
|
U27 0.000 8.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 8.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.365 9.365 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.442 9.808 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.083 9.891 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.439 10.330 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.964 9.365 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.442 9.808 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.083 9.891 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.439 10.330 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-0.964 9.365 r u_gps_domain_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.442 9.808 pll_gps_trck_clk
|
|
BUFG (Prop_bufg_I_O) 0.083 9.891 r u_gps_trck_clk_buf/O
|
|
net (fo=17887, unplaced) 0.439 10.330 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/gps_trck_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_C/C
|
|
clock pessimism 0.165 10.495
|
|
clock uncertainty -0.081 10.414
|
|
FDCE (Recov_fdce_C_CLR) -0.214 10.200 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_C
|
|
-------------------------------------------------------------------
|
|
required time 10.200
|
|
arrival time -4.362
|
|
-------------------------------------------------------------------
|
|
slack 5.838
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.361ns (arrival time - required time)
|
|
Source: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/prn_o_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by pll_gps_trck_clk {rise@0.000ns fall@4.000ns period=8.000ns})
|
|
Destination: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_P/PRE
|
|
(removal check against rising-edge clock pll_gps_trck_clk {rise@0.000ns fall@4.000ns period=8.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (pll_gps_trck_clk rise@0.000ns - pll_gps_trck_clk rise@0.000ns)
|
|
Data Path Delay: 0.432ns (logic 0.164ns (37.987%) route 0.268ns (62.013%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.150ns
|
|
Source Clock Delay (SCD): 0.793ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pll_gps_trck_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 0.422 0.422 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.231 0.653 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.114 0.793 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.371 0.422 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.231 0.653 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.114 0.793 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-0.371 0.422 r u_gps_domain_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.231 0.653 pll_gps_trck_clk
|
|
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_gps_trck_clk_buf/O
|
|
net (fo=17887, unplaced) 0.114 0.793 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/gps_trck_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/prn_o_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.100 0.893 r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/prn_o_reg[4]/Q
|
|
net (fo=10, unplaced) 0.154 1.047 u_rocket/fpga_gps_domain/dev/tracking_0/prn[4]
|
|
LUT6 (Prop_lut6_I4_O) 0.064 1.111 f u_rocket/fpga_gps_domain/dev/tracking_0/i___5/O
|
|
net (fo=2, unplaced) 0.114 1.225 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_P_4
|
|
FDPE f u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_P/PRE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pll_gps_trck_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 0.618 0.618 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.243 0.861 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.259 1.150 gps_rf_clk_selected
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
|
-0.532 0.618 r u_gps_ref_mmcm/CLKOUT0
|
|
net (fo=1, unplaced) 0.243 0.861 pll_gps_ref_clk
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_gps_ref_clk_buf/O
|
|
net (fo=1, unplaced) 0.259 1.150 gps_ref_clk_gen
|
|
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
|
|
-0.532 0.618 r u_gps_domain_mmcm/CLKOUT1
|
|
net (fo=1, unplaced) 0.243 0.861 pll_gps_trck_clk
|
|
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_gps_trck_clk_buf/O
|
|
net (fo=17887, unplaced) 0.259 1.150 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/gps_trck_clk
|
|
FDPE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_P/C
|
|
clock pessimism -0.212 0.938
|
|
FDPE (Remov_fdpe_C_PRE) -0.074 0.864 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_P
|
|
-------------------------------------------------------------------
|
|
required time -0.864
|
|
arrival time 1.225
|
|
-------------------------------------------------------------------
|
|
slack 0.361
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: pmod_rf_clk
|
|
To Clock: pmod_rf_clk
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 59.496ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.502ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 59.496ns (required time - arrival time)
|
|
Source: u_rocket/fpga_gps_domain/dev/afeReset_gps_afe_reset/io_sync_reset_chain/output_chain/sync_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by pmod_rf_clk {rise@0.000ns fall@30.548ns period=61.095ns})
|
|
Destination: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_en_reg/CLR
|
|
(recovery check against rising-edge clock pmod_rf_clk {rise@0.000ns fall@30.548ns period=61.095ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 61.095ns (pmod_rf_clk rise@61.095ns - pmod_rf_clk rise@0.000ns)
|
|
Data Path Delay: 1.205ns (logic 0.346ns (28.714%) route 0.859ns (71.286%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.330ns = ( 63.425 - 61.095 )
|
|
Source Clock Delay (SCD): 2.640ns
|
|
Clock Pessimism Removal (CPR): 0.165ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock pmod_rf_clk rise edge)
|
|
0.000 0.000 r
|
|
U27 0.000 0.000 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 0.000 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.497 1.497 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.466 1.963 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.584 2.640 u_rocket/fpga_gps_domain/dev/afeReset_gps_afe_reset/io_sync_reset_chain/output_chain/gps_rf_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/afeReset_gps_afe_reset/io_sync_reset_chain/output_chain/sync_0_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.223 2.863 r u_rocket/fpga_gps_domain/dev/afeReset_gps_afe_reset/io_sync_reset_chain/output_chain/sync_0_reg/Q
|
|
net (fo=1, unplaced) 0.191 3.054 u_rocket/fpga_gps_domain/dev/afeReset_gps_afe_reset/io_sync_reset_chain/output_chain/sync_0_reg_n_0
|
|
LUT1 (Prop_lut1_I0_O) 0.123 3.177 f u_rocket/fpga_gps_domain/dev/afeReset_gps_afe_reset/io_sync_reset_chain/output_chain/start_r1_i_2/O
|
|
net (fo=37, unplaced) 0.668 3.845 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_end_reg_0
|
|
FDCE f u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_en_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock pmod_rf_clk rise edge)
|
|
61.095 61.095 r
|
|
U27 0.000 61.095 r rf_clk_pmod (IN)
|
|
net (fo=0) 0.000 61.095 rf_clk_pmod
|
|
U27 IBUF (Prop_ibuf_I_O) 1.365 62.460 r u_rf_clk_pmod_ibuf/O
|
|
net (fo=1, unplaced) 0.442 62.903 rf_clk_pmod_ibuf
|
|
BUFG (Prop_bufg_I_O) 0.083 62.986 r u_rf_clk_pmod_buf/O
|
|
net (fo=982, unplaced) 0.439 63.425 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/gps_rf_clk
|
|
FDCE r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_en_reg/C
|
|
clock pessimism 0.165 63.590
|
|
clock uncertainty -0.035 63.554
|
|
FDCE (Recov_fdce_C_CLR) -0.214 63.340 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_en_reg
|
|
-------------------------------------------------------------------
|
|
required time 63.340
|
|
arrival time -3.845
|
|
-------------------------------------------------------------------
|
|
slack 59.496
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.502ns (arrival time - required time)
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Source: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/reset_synch_i/afe_r2_reg/C
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(rising edge-triggered cell FDCE clocked by pmod_rf_clk {rise@0.000ns fall@30.548ns period=61.095ns})
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Destination: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[0]/CLR
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(removal check against rising-edge clock pmod_rf_clk {rise@0.000ns fall@30.548ns period=61.095ns})
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Path Group: **async_default**
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Path Type: Removal (Min at Fast Process Corner)
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Requirement: 0.000ns (pmod_rf_clk rise@0.000ns - pmod_rf_clk rise@0.000ns)
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Data Path Delay: 0.579ns (logic 0.164ns (28.321%) route 0.415ns (71.679%))
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Logic Levels: 1 (LUT2=1)
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Clock Path Skew: 0.145ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): 1.150ns
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Source Clock Delay (SCD): 0.793ns
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Clock Pessimism Removal (CPR): 0.212ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock pmod_rf_clk rise edge)
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0.000 0.000 r
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U27 0.000 0.000 r rf_clk_pmod (IN)
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net (fo=0) 0.000 0.000 rf_clk_pmod
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U27 IBUF (Prop_ibuf_I_O) 0.422 0.422 r u_rf_clk_pmod_ibuf/O
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net (fo=1, unplaced) 0.231 0.653 rf_clk_pmod_ibuf
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BUFG (Prop_bufg_I_O) 0.026 0.679 r u_rf_clk_pmod_buf/O
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net (fo=982, unplaced) 0.114 0.793 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/reset_synch_i/gps_rf_clk
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FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/reset_synch_i/afe_r2_reg/C
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------------------------------------------------------------------- -------------------
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FDCE (Prop_fdce_C_Q) 0.100 0.893 r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/reset_synch_i/afe_r2_reg/Q
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net (fo=1, unplaced) 0.095 0.988 u_rocket/fpga_gps_domain/dev/tracking_0/trck_cntrl_i/afe_soft_rstn
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LUT2 (Prop_lut2_I1_O) 0.064 1.052 f u_rocket/fpga_gps_domain/dev/tracking_0/i___183/O
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net (fo=15, unplaced) 0.320 1.372 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[1]_15
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FDCE f u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[0]/CLR
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------------------------------------------------------------------- -------------------
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(clock pmod_rf_clk rise edge)
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0.000 0.000 r
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U27 0.000 0.000 r rf_clk_pmod (IN)
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net (fo=0) 0.000 0.000 rf_clk_pmod
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U27 IBUF (Prop_ibuf_I_O) 0.618 0.618 r u_rf_clk_pmod_ibuf/O
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net (fo=1, unplaced) 0.243 0.861 rf_clk_pmod_ibuf
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BUFG (Prop_bufg_I_O) 0.030 0.891 r u_rf_clk_pmod_buf/O
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net (fo=982, unplaced) 0.259 1.150 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/gps_rf_clk
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FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[0]/C
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clock pessimism -0.212 0.938
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FDCE (Remov_fdce_C_CLR) -0.068 0.870 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[0]
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-------------------------------------------------------------------
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required time -0.870
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arrival time 1.372
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-------------------------------------------------------------------
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slack 0.502
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