onur
1dbd1b5151
Keep the current GPS software and Genesys2/VCU118 flows while integrating Ti375C529 Efinity, flash, programming, and debug support. Add board-specific SPI NOR profiles and persistent GPS flash layouts across all three boards.
277 lines
9.8 KiB
Python
277 lines
9.8 KiB
Python
#!/usr/bin/env python3
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"""Generate the Efinix Ti375 board shell around the shared Rocket subsystem."""
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import argparse
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import re
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from pathlib import Path
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def width_bits(width):
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if not width:
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return 1
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match = re.fullmatch(r"\[(\d+):(\d+)\]", width.strip())
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if not match:
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raise ValueError(f"unsupported width: {width}")
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return abs(int(match.group(1)) - int(match.group(2))) + 1
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def parse_ports(verilog_path):
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text = Path(verilog_path).read_text()
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module_name = Path(verilog_path).stem
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start = text.index(f"module {module_name}(")
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end = text.index(");", start)
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header = re.sub(r"//.*", "", text[start:end])
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pieces = re.split(r"\b(input|output)\b", header)[1:]
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ports = []
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for direction, body in zip(pieces[0::2], pieces[1::2]):
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body = body.replace("\n", " ")
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body = re.split(r"\b(input|output)\b", body)[0]
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default_width = ""
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width_match = re.match(r"\s*(\[[^\]]+\])\s*(.*)", body)
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if width_match:
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default_width = width_match.group(1)
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rest = width_match.group(2)
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else:
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rest = body
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for item in rest.split(","):
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item = item.strip()
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if not item:
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continue
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item_match = re.match(r"(\[[^\]]+\])\s*(\w+)$", item)
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if item_match:
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width, name = item_match.groups()
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else:
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width = default_width
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name = item.split()[-1]
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if re.fullmatch(r"\w+", name):
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ports.append((direction, width, name))
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return ports
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def const_for(width):
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bits = width_bits(width)
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return "1'b0" if bits == 1 else f"{bits}'d0"
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def is_clock(name):
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return name.endswith("_clock") or name == "debug_clock"
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def is_reset(name):
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return name.endswith("_reset") or name == "debug_reset"
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument("--rocket-top", required=True)
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parser.add_argument("--out", required=True)
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args = parser.parse_args()
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ports = parse_ports(args.rocket_top)
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port_by_name = {name: (direction, width) for direction, width, name in ports}
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required = {
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"uart_rxd", "uart_txd",
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"spi_sck", "spi_csn", "spi_dq_i", "spi_dq_o", "spi_dq_oe",
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"pmod_spi_sck", "pmod_spi_csn",
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"pmod_spi_dq_i", "pmod_spi_dq_o", "pmod_spi_dq_oe",
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"max2771_spi_sclk", "max2771_spi_csn",
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"max2771_spi_sdata_i", "max2771_spi_sdata_o",
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"max2771_spi_sdata_oe",
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"pmod_irq", "gps_acq_clk", "gps_trck_clk",
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"gps_rf_clk", "gps_rf_data", "gps_pps",
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}
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missing = sorted(required - port_by_name.keys())
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if missing:
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raise RuntimeError(f"Rocket top is missing required Ti375 ports: {', '.join(missing)}")
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passthrough = {
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"pmod_spi_sck", "pmod_spi_csn",
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"max2771_spi_sclk", "max2771_spi_csn",
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"pmod_irq", "gps_pps",
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}
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def decl(width, name):
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return f" wire {width + ' ' if width else ''}{name};"
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assigns = []
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for direction, width, name in ports:
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if direction != "input" or name in passthrough:
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continue
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if name.startswith("debug_clockeddmi_dmi_req"):
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continue
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if name in {
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"debug_clockeddmi_dmi_resp_ready",
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"debug_clockeddmi_dmiClock",
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"debug_clockeddmi_dmiReset",
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}:
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continue
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if name == "resetctrl_hartIsInReset_0":
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value = "soc_reset"
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elif name == "debug_reset":
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value = "fabric_reset"
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elif is_reset(name):
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value = "soc_reset"
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elif name == "gps_acq_clk":
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value = "gps_acq_clk_gen"
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elif name == "gps_trck_clk":
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value = "gps_trck_clk_gen"
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elif name in {"gps_rf_clk", "gps_afe_clk"}:
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value = "rf_clk"
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elif name == "gps_rf_data":
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value = "rf_data"
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elif is_clock(name):
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value = "fabric_clk"
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elif name == "debug_dmactiveAck":
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value = "debug_dmactive"
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elif name == "uart_rxd":
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value = "uart_rx"
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elif name == "spi_dq_i":
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value = "flash_dq_IN"
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elif name == "pmod_spi_dq_i":
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value = "pmod_spi_dq_IN"
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elif name == "max2771_spi_sdata_i":
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value = "max2771_spi_sdata_IN"
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elif name == "interrupts":
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value = "2'b00"
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else:
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value = const_for(width)
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assigns.append(f" assign {name} = {value};")
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port_map = ",\n".join(f" .{name}({name})" for _, _, name in ports)
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internal_decls = "\n".join(
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decl(width, name) for _, width, name in ports if name not in passthrough
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)
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content = f"""`timescale 1ns/1ps
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module ti375c529_rocket_top (
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(* syn_peri_port = 0 *) input wire fabric_clk,
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(* syn_peri_port = 0 *) input wire fabric_pll_locked,
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(* syn_peri_port = 0 *) input wire board_clk_100,
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(* syn_peri_port = 0 *) input wire gps_ref_clk_gen,
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(* syn_peri_port = 0 *) input wire gps_acq_clk_gen,
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(* syn_peri_port = 0 *) input wire gps_trck_clk_gen,
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(* syn_peri_port = 0 *) input wire gps_domain_feedback,
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(* syn_peri_port = 0 *) input wire gps_ref_pll_locked,
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(* syn_peri_port = 0 *) input wire gps_domain_pll_locked,
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(* syn_peri_port = 0 *) input wire reset_n,
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(* syn_peri_port = 0 *) input wire uart_rx,
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(* syn_peri_port = 0 *) output wire uart_tx,
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(* syn_peri_port = 0 *) output wire flash_sck,
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(* syn_peri_port = 0 *) output wire flash_csn,
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(* syn_peri_port = 0 *) input wire [3:0] flash_dq_IN,
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(* syn_peri_port = 0 *) output wire [3:0] flash_dq_OUT,
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(* syn_peri_port = 0 *) output wire [3:0] flash_dq_OE,
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(* syn_peri_port = 0 *) input wire rf_clk,
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(* syn_peri_port = 0 *) input wire [3:0] rf_data,
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(* syn_peri_port = 0 *) output wire pmod_spi_sck,
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(* syn_peri_port = 0 *) output wire pmod_spi_csn,
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(* syn_peri_port = 0 *) input wire [3:0] pmod_spi_dq_IN,
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(* syn_peri_port = 0 *) output wire [3:0] pmod_spi_dq_OUT,
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(* syn_peri_port = 0 *) output wire [3:0] pmod_spi_dq_OE,
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(* syn_peri_port = 0 *) input wire pmod_irq,
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(* syn_peri_port = 0 *) output wire max2771_spi_sclk,
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(* syn_peri_port = 0 *) output wire max2771_spi_csn,
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(* syn_peri_port = 0 *) input wire max2771_spi_sdata_IN,
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(* syn_peri_port = 0 *) output wire max2771_spi_sdata_OUT,
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(* syn_peri_port = 0 *) output wire max2771_spi_sdata_OE,
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(* syn_peri_port = 0 *) output wire gps_pps,
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(* syn_peri_port = 0 *) input wire jtag_CAPTURE,
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(* syn_peri_port = 0 *) input wire jtag_DRCK,
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(* syn_peri_port = 0 *) input wire jtag_RESET,
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(* syn_peri_port = 0 *) input wire jtag_RUNTEST,
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(* syn_peri_port = 0 *) input wire jtag_SEL,
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(* syn_peri_port = 0 *) input wire jtag_SHIFT,
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(* syn_peri_port = 0 *) input wire jtag_TCK,
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(* syn_peri_port = 0 *) input wire jtag_TDI,
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(* syn_peri_port = 0 *) input wire jtag_TMS,
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(* syn_peri_port = 0 *) input wire jtag_UPDATE,
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(* syn_peri_port = 0 *) output wire jtag_TDO,
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(* syn_peri_port = 0 *) output wire [4:0] led
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);
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wire gps_clock_locked = gps_ref_pll_locked & gps_domain_pll_locked;
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wire pll_ready_async = fabric_pll_locked & gps_clock_locked & reset_n;
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(* async_reg = "true" *) reg [2:0] pll_ready_sync = 3'b000;
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reg [15:0] reset_shift = 16'hffff;
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always @(posedge fabric_clk) begin
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pll_ready_sync <= {{pll_ready_sync[1:0], pll_ready_async}};
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if (!pll_ready_sync[2])
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reset_shift <= 16'hffff;
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else
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reset_shift <= {{reset_shift[14:0], 1'b0}};
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end
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wire fabric_reset = reset_shift[15];
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reg [31:0] heartbeat = 32'd0;
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always @(posedge fabric_clk) begin
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if (fabric_reset)
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heartbeat <= 32'd0;
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else
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heartbeat <= heartbeat + 32'd1;
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end
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{internal_decls}
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wire soc_reset = fabric_reset | debug_ndreset;
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rocket_bscan_dmi_tunnel u_rocket_dmi_tunnel (
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.tck(jtag_TCK),
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.reset(fabric_reset | jtag_RESET),
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.bscan_capture(jtag_CAPTURE),
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.bscan_sel(jtag_SEL),
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.bscan_shift(jtag_SHIFT),
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.bscan_tdi(jtag_TDI),
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.bscan_update(jtag_UPDATE),
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.bscan_tdo(jtag_TDO),
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.dmi_clock(debug_clockeddmi_dmiClock),
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.dmi_reset(debug_clockeddmi_dmiReset),
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.dmi_req_ready(debug_clockeddmi_dmi_req_ready),
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.dmi_req_valid(debug_clockeddmi_dmi_req_valid),
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.dmi_req_addr(debug_clockeddmi_dmi_req_bits_addr),
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.dmi_req_data(debug_clockeddmi_dmi_req_bits_data),
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.dmi_req_op(debug_clockeddmi_dmi_req_bits_op),
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.dmi_resp_ready(debug_clockeddmi_dmi_resp_ready),
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.dmi_resp_valid(debug_clockeddmi_dmi_resp_valid),
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.dmi_resp_data(debug_clockeddmi_dmi_resp_bits_data),
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.dmi_resp_resp(debug_clockeddmi_dmi_resp_bits_resp)
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);
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assign pmod_spi_dq_OUT = pmod_spi_dq_o;
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assign pmod_spi_dq_OE = pmod_spi_dq_oe;
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assign max2771_spi_sdata_OUT = max2771_spi_sdata_o;
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assign max2771_spi_sdata_OE = max2771_spi_sdata_oe;
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assign flash_sck = spi_sck;
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assign flash_csn = spi_csn;
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assign flash_dq_OUT = spi_dq_o;
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assign flash_dq_OE = spi_dq_oe;
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assign uart_tx = uart_txd;
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// The kit LEDs are active-low. Show heartbeat, PLL locks, reset release,
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// and debug-module activity from LED13 down to LED9.
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assign led = ~{{heartbeat[25], gps_clock_locked, fabric_pll_locked,
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~fabric_reset, debug_dmactive}};
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{chr(10).join(assigns)}
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(* syn_preserve = 1 *)
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{Path(args.rocket_top).stem} u_rocket (
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{port_map}
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);
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// These hard-TAP outputs are intentionally unused by the DMI framing logic.
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wire _unused_hard_signals = jtag_DRCK ^ jtag_RUNTEST ^ jtag_TMS ^
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board_clk_100 ^ gps_ref_clk_gen ^
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gps_domain_feedback;
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endmodule
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"""
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output = Path(args.out)
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output.parent.mkdir(parents=True, exist_ok=True)
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output.write_text(content)
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if __name__ == "__main__":
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main()
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