63 lines
1.8 KiB
Diff
63 lines
1.8 KiB
Diff
--- a/src/target/riscv/riscv.c
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+++ b/src/target/riscv/riscv.c
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@@ -127,6 +127,7 @@
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static bscan_tunnel_type_t bscan_tunnel_type;
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int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
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+static int bscan_tunnel_ir_id; /* outer TAP IR used to access the tunnel */
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static const uint8_t bscan_zero[4] = {0};
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static const uint8_t bscan_one[4] = {1};
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@@ -451,8 +452,12 @@
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select_idcode.num_bits = target->tap->ir_length;
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if (bscan_tunnel_ir_width != 0) {
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- assert(target->tap->ir_length >= 6);
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- uint32_t ir_user4_raw = 0x23 << (target->tap->ir_length - 6);
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+ uint32_t ir_user4_raw = bscan_tunnel_ir_id;
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+ /* Preserve the legacy Xilinx USER4 default when no IR was supplied. */
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+ if (ir_user4_raw == 0) {
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+ assert(target->tap->ir_length >= 6);
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+ ir_user4_raw = 0x23 << (target->tap->ir_length - 6);
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+ }
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h_u32_to_le(ir_user4, ir_user4_raw);
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select_user4.num_bits = target->tap->ir_length;
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bscan_tunneled_ir_width[0] = bscan_tunnel_ir_width;
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@@ -2859,6 +2864,21 @@
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return ERROR_OK;
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}
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+COMMAND_HANDLER(riscv_set_bscan_tunnel_ir)
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+{
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+ int ir_id = 0;
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+
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+ if (CMD_ARGC > 1)
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+ return ERROR_COMMAND_SYNTAX_ERROR;
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+
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+ if (CMD_ARGC == 1)
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+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], ir_id);
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+
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+ LOG_INFO("Bscan tunnel IR 0x%x selected", ir_id);
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+ bscan_tunnel_ir_id = ir_id;
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+ return ERROR_OK;
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+}
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+
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COMMAND_HANDLER(riscv_set_enable_virt2phys)
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{
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if (CMD_ARGC != 1) {
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@@ -3072,6 +3092,14 @@
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"1: DATA_REGISTER}"
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},
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{
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+ .name = "set_bscan_tunnel_ir",
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+ .handler = riscv_set_bscan_tunnel_ir,
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+ .mode = COMMAND_ANY,
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+ .usage = "[value]",
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+ .help = "Specify the outer JTAG TAP IR used to access the BSCAN tunnel. "
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+ "The default remains the Xilinx FPGA USER4 instruction."
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+ },
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+ {
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.name = "set_enable_virt2phys",
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.handler = riscv_set_enable_virt2phys,
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.mode = COMMAND_ANY,
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